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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/i2c.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
79e53945 JB |
29 | #include "drmP.h" |
30 | #include "drm.h" | |
31 | #include "drm_crtc.h" | |
32 | #include "drm_crtc_helper.h" | |
33 | #include "intel_drv.h" | |
34 | #include "i915_drm.h" | |
35 | #include "i915_drv.h" | |
36 | ||
c9a1c4cd CW |
37 | struct intel_crt { |
38 | struct intel_encoder base; | |
39 | }; | |
40 | ||
41 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) | |
42 | { | |
43 | return container_of(intel_attached_encoder(connector), | |
44 | struct intel_crt, base); | |
45 | } | |
46 | ||
79e53945 JB |
47 | static void intel_crt_dpms(struct drm_encoder *encoder, int mode) |
48 | { | |
49 | struct drm_device *dev = encoder->dev; | |
50 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 51 | u32 temp, reg; |
79e53945 | 52 | |
bad720ff | 53 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
54 | reg = PCH_ADPA; |
55 | else | |
56 | reg = ADPA; | |
57 | ||
58 | temp = I915_READ(reg); | |
79e53945 | 59 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
febc7694 | 60 | temp &= ~ADPA_DAC_ENABLE; |
79e53945 JB |
61 | |
62 | switch(mode) { | |
63 | case DRM_MODE_DPMS_ON: | |
64 | temp |= ADPA_DAC_ENABLE; | |
65 | break; | |
66 | case DRM_MODE_DPMS_STANDBY: | |
67 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; | |
68 | break; | |
69 | case DRM_MODE_DPMS_SUSPEND: | |
70 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; | |
71 | break; | |
72 | case DRM_MODE_DPMS_OFF: | |
73 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; | |
74 | break; | |
75 | } | |
76 | ||
2c07245f | 77 | I915_WRITE(reg, temp); |
79e53945 JB |
78 | } |
79 | ||
80 | static int intel_crt_mode_valid(struct drm_connector *connector, | |
81 | struct drm_display_mode *mode) | |
82 | { | |
6bcdcd9e ZY |
83 | struct drm_device *dev = connector->dev; |
84 | ||
85 | int max_clock = 0; | |
79e53945 JB |
86 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
87 | return MODE_NO_DBLESCAN; | |
88 | ||
6bcdcd9e ZY |
89 | if (mode->clock < 25000) |
90 | return MODE_CLOCK_LOW; | |
91 | ||
a6c45cf0 | 92 | if (IS_GEN2(dev)) |
6bcdcd9e ZY |
93 | max_clock = 350000; |
94 | else | |
95 | max_clock = 400000; | |
96 | if (mode->clock > max_clock) | |
97 | return MODE_CLOCK_HIGH; | |
79e53945 JB |
98 | |
99 | return MODE_OK; | |
100 | } | |
101 | ||
102 | static bool intel_crt_mode_fixup(struct drm_encoder *encoder, | |
103 | struct drm_display_mode *mode, | |
104 | struct drm_display_mode *adjusted_mode) | |
105 | { | |
106 | return true; | |
107 | } | |
108 | ||
109 | static void intel_crt_mode_set(struct drm_encoder *encoder, | |
110 | struct drm_display_mode *mode, | |
111 | struct drm_display_mode *adjusted_mode) | |
112 | { | |
113 | ||
114 | struct drm_device *dev = encoder->dev; | |
115 | struct drm_crtc *crtc = encoder->crtc; | |
116 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
118 | int dpll_md_reg; | |
119 | u32 adpa, dpll_md; | |
2c07245f | 120 | u32 adpa_reg; |
79e53945 JB |
121 | |
122 | if (intel_crtc->pipe == 0) | |
123 | dpll_md_reg = DPLL_A_MD; | |
124 | else | |
125 | dpll_md_reg = DPLL_B_MD; | |
126 | ||
bad720ff | 127 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
128 | adpa_reg = PCH_ADPA; |
129 | else | |
130 | adpa_reg = ADPA; | |
131 | ||
79e53945 JB |
132 | /* |
133 | * Disable separate mode multiplier used when cloning SDVO to CRT | |
134 | * XXX this needs to be adjusted when we really are cloning | |
135 | */ | |
a6c45cf0 | 136 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
79e53945 JB |
137 | dpll_md = I915_READ(dpll_md_reg); |
138 | I915_WRITE(dpll_md_reg, | |
139 | dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); | |
140 | } | |
141 | ||
142 | adpa = 0; | |
143 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
144 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
145 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
146 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
147 | ||
6bcdcd9e | 148 | if (intel_crtc->pipe == 0) { |
8db9d77b ZW |
149 | if (HAS_PCH_CPT(dev)) |
150 | adpa |= PORT_TRANS_A_SEL_CPT; | |
151 | else | |
152 | adpa |= ADPA_PIPE_A_SELECT; | |
bad720ff | 153 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f | 154 | I915_WRITE(BCLRPAT_A, 0); |
6bcdcd9e | 155 | } else { |
8db9d77b ZW |
156 | if (HAS_PCH_CPT(dev)) |
157 | adpa |= PORT_TRANS_B_SEL_CPT; | |
158 | else | |
159 | adpa |= ADPA_PIPE_B_SELECT; | |
bad720ff | 160 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f | 161 | I915_WRITE(BCLRPAT_B, 0); |
6bcdcd9e | 162 | } |
79e53945 | 163 | |
2c07245f ZW |
164 | I915_WRITE(adpa_reg, adpa); |
165 | } | |
166 | ||
f2b115e6 | 167 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
168 | { |
169 | struct drm_device *dev = connector->dev; | |
170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4a6b901 | 171 | u32 adpa, temp; |
2c07245f | 172 | bool ret; |
d5dd96cb | 173 | bool turn_off_dac = false; |
2c07245f | 174 | |
a4a6b901 | 175 | temp = adpa = I915_READ(PCH_ADPA); |
67941da2 | 176 | |
d5dd96cb DA |
177 | if (HAS_PCH_SPLIT(dev)) |
178 | turn_off_dac = true; | |
179 | ||
180 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; | |
181 | if (turn_off_dac) | |
182 | adpa &= ~ADPA_DAC_ENABLE; | |
183 | ||
184 | /* disable HPD first */ | |
185 | I915_WRITE(PCH_ADPA, adpa); | |
186 | (void)I915_READ(PCH_ADPA); | |
2c07245f ZW |
187 | |
188 | adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 | | |
189 | ADPA_CRT_HOTPLUG_WARMUP_10MS | | |
190 | ADPA_CRT_HOTPLUG_SAMPLE_4S | | |
191 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | /* default */ | |
192 | ADPA_CRT_HOTPLUG_VOLREF_325MV | | |
193 | ADPA_CRT_HOTPLUG_ENABLE | | |
194 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER); | |
195 | ||
28c97730 | 196 | DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa); |
2c07245f ZW |
197 | I915_WRITE(PCH_ADPA, adpa); |
198 | ||
913d8d11 | 199 | if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
481b6af3 | 200 | 1000)) |
79077319 | 201 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
2c07245f | 202 | |
d5dd96cb | 203 | if (turn_off_dac) { |
1510a971 YL |
204 | /* Make sure hotplug is enabled */ |
205 | I915_WRITE(PCH_ADPA, temp | ADPA_CRT_HOTPLUG_ENABLE); | |
a4a6b901 ZW |
206 | (void)I915_READ(PCH_ADPA); |
207 | } | |
208 | ||
2c07245f ZW |
209 | /* Check the status to see if both blue and green are on now */ |
210 | adpa = I915_READ(PCH_ADPA); | |
67941da2 ZW |
211 | adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK; |
212 | if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) || | |
213 | (adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO)) | |
2c07245f ZW |
214 | ret = true; |
215 | else | |
216 | ret = false; | |
217 | ||
2c07245f | 218 | return ret; |
79e53945 JB |
219 | } |
220 | ||
221 | /** | |
222 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
223 | * | |
224 | * Not for i915G/i915GM | |
225 | * | |
226 | * \return true if CRT is connected. | |
227 | * \return false if CRT is disconnected. | |
228 | */ | |
229 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
230 | { | |
231 | struct drm_device *dev = connector->dev; | |
232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a772c49 AJ |
233 | u32 hotplug_en, orig, stat; |
234 | bool ret = false; | |
771cb081 | 235 | int i, tries = 0; |
2c07245f | 236 | |
bad720ff | 237 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 238 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 239 | |
771cb081 ZY |
240 | /* |
241 | * On 4 series desktop, CRT detect sequence need to be done twice | |
242 | * to get a reliable result. | |
243 | */ | |
79e53945 | 244 | |
771cb081 ZY |
245 | if (IS_G4X(dev) && !IS_GM45(dev)) |
246 | tries = 2; | |
247 | else | |
248 | tries = 1; | |
7a772c49 | 249 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
771cb081 ZY |
250 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
251 | ||
771cb081 | 252 | for (i = 0; i < tries ; i++) { |
771cb081 ZY |
253 | /* turn on the FORCE_DETECT */ |
254 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
771cb081 | 255 | /* wait for FORCE_DETECT to go off */ |
913d8d11 CW |
256 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
257 | CRT_HOTPLUG_FORCE_DETECT) == 0, | |
481b6af3 | 258 | 1000)) |
79077319 | 259 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 260 | } |
79e53945 | 261 | |
7a772c49 AJ |
262 | stat = I915_READ(PORT_HOTPLUG_STAT); |
263 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
264 | ret = true; | |
265 | ||
266 | /* clear the interrupt we just generated, if any */ | |
267 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 268 | |
7a772c49 AJ |
269 | /* and put the bits back */ |
270 | I915_WRITE(PORT_HOTPLUG_EN, orig); | |
271 | ||
272 | return ret; | |
79e53945 JB |
273 | } |
274 | ||
6ec3d0c0 CW |
275 | static bool intel_crt_ddc_probe(struct drm_i915_private *dev_priv, int ddc_bus) |
276 | { | |
277 | u8 buf; | |
278 | struct i2c_msg msgs[] = { | |
279 | { | |
280 | .addr = 0xA0, | |
281 | .flags = 0, | |
282 | .len = 1, | |
283 | .buf = &buf, | |
284 | }, | |
285 | }; | |
286 | /* DDC monitor detect: Does it ACK a write to 0xA0? */ | |
287 | return i2c_transfer(&dev_priv->gmbus[ddc_bus].adapter, msgs, 1) == 1; | |
288 | } | |
289 | ||
c9a1c4cd | 290 | static bool intel_crt_detect_ddc(struct intel_crt *crt) |
79e53945 | 291 | { |
c9a1c4cd | 292 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
79e53945 JB |
293 | |
294 | /* CRT should always be at 0, but check anyway */ | |
c9a1c4cd | 295 | if (crt->base.type != INTEL_OUTPUT_ANALOG) |
79e53945 JB |
296 | return false; |
297 | ||
6ec3d0c0 CW |
298 | if (intel_crt_ddc_probe(dev_priv, dev_priv->crt_ddc_pin)) { |
299 | DRM_DEBUG_KMS("CRT detected via DDC:0xa0\n"); | |
300 | return true; | |
301 | } | |
302 | ||
c9a1c4cd | 303 | if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) { |
6ec3d0c0 CW |
304 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
305 | return true; | |
306 | } | |
307 | ||
308 | return false; | |
79e53945 JB |
309 | } |
310 | ||
e4a5d54f | 311 | static enum drm_connector_status |
c9a1c4cd | 312 | intel_crt_load_detect(struct drm_crtc *crtc, struct intel_crt *crt) |
e4a5d54f | 313 | { |
c9a1c4cd | 314 | struct drm_encoder *encoder = &crt->base.base; |
e4a5d54f ML |
315 | struct drm_device *dev = encoder->dev; |
316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
318 | uint32_t pipe = intel_crtc->pipe; | |
319 | uint32_t save_bclrpat; | |
320 | uint32_t save_vtotal; | |
321 | uint32_t vtotal, vactive; | |
322 | uint32_t vsample; | |
323 | uint32_t vblank, vblank_start, vblank_end; | |
324 | uint32_t dsl; | |
325 | uint32_t bclrpat_reg; | |
326 | uint32_t vtotal_reg; | |
327 | uint32_t vblank_reg; | |
328 | uint32_t vsync_reg; | |
329 | uint32_t pipeconf_reg; | |
330 | uint32_t pipe_dsl_reg; | |
331 | uint8_t st00; | |
332 | enum drm_connector_status status; | |
333 | ||
6ec3d0c0 CW |
334 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
335 | ||
e4a5d54f ML |
336 | if (pipe == 0) { |
337 | bclrpat_reg = BCLRPAT_A; | |
338 | vtotal_reg = VTOTAL_A; | |
339 | vblank_reg = VBLANK_A; | |
340 | vsync_reg = VSYNC_A; | |
341 | pipeconf_reg = PIPEACONF; | |
342 | pipe_dsl_reg = PIPEADSL; | |
343 | } else { | |
344 | bclrpat_reg = BCLRPAT_B; | |
345 | vtotal_reg = VTOTAL_B; | |
346 | vblank_reg = VBLANK_B; | |
347 | vsync_reg = VSYNC_B; | |
348 | pipeconf_reg = PIPEBCONF; | |
349 | pipe_dsl_reg = PIPEBDSL; | |
350 | } | |
351 | ||
352 | save_bclrpat = I915_READ(bclrpat_reg); | |
353 | save_vtotal = I915_READ(vtotal_reg); | |
354 | vblank = I915_READ(vblank_reg); | |
355 | ||
356 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
357 | vactive = (save_vtotal & 0x7ff) + 1; | |
358 | ||
359 | vblank_start = (vblank & 0xfff) + 1; | |
360 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
361 | ||
362 | /* Set the border color to purple. */ | |
363 | I915_WRITE(bclrpat_reg, 0x500050); | |
364 | ||
a6c45cf0 | 365 | if (!IS_GEN2(dev)) { |
e4a5d54f ML |
366 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
367 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 368 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
369 | /* Wait for next Vblank to substitue |
370 | * border color for Color info */ | |
9d0498a2 | 371 | intel_wait_for_vblank(dev, pipe); |
e4a5d54f ML |
372 | st00 = I915_READ8(VGA_MSR_WRITE); |
373 | status = ((st00 & (1 << 4)) != 0) ? | |
374 | connector_status_connected : | |
375 | connector_status_disconnected; | |
376 | ||
377 | I915_WRITE(pipeconf_reg, pipeconf); | |
378 | } else { | |
379 | bool restore_vblank = false; | |
380 | int count, detect; | |
381 | ||
382 | /* | |
383 | * If there isn't any border, add some. | |
384 | * Yes, this will flicker | |
385 | */ | |
386 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
387 | uint32_t vsync = I915_READ(vsync_reg); | |
388 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
389 | ||
390 | vblank_start = vsync_start; | |
391 | I915_WRITE(vblank_reg, | |
392 | (vblank_start - 1) | | |
393 | ((vblank_end - 1) << 16)); | |
394 | restore_vblank = true; | |
395 | } | |
396 | /* sample in the vertical border, selecting the larger one */ | |
397 | if (vblank_start - vactive >= vtotal - vblank_end) | |
398 | vsample = (vblank_start + vactive) >> 1; | |
399 | else | |
400 | vsample = (vtotal + vblank_end) >> 1; | |
401 | ||
402 | /* | |
403 | * Wait for the border to be displayed | |
404 | */ | |
405 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
406 | ; | |
407 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
408 | ; | |
409 | /* | |
410 | * Watch ST00 for an entire scanline | |
411 | */ | |
412 | detect = 0; | |
413 | count = 0; | |
414 | do { | |
415 | count++; | |
416 | /* Read the ST00 VGA status register */ | |
417 | st00 = I915_READ8(VGA_MSR_WRITE); | |
418 | if (st00 & (1 << 4)) | |
419 | detect++; | |
420 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
421 | ||
422 | /* restore vblank if necessary */ | |
423 | if (restore_vblank) | |
424 | I915_WRITE(vblank_reg, vblank); | |
425 | /* | |
426 | * If more than 3/4 of the scanline detected a monitor, | |
427 | * then it is assumed to be present. This works even on i830, | |
428 | * where there isn't any way to force the border color across | |
429 | * the screen | |
430 | */ | |
431 | status = detect * 4 > count * 3 ? | |
432 | connector_status_connected : | |
433 | connector_status_disconnected; | |
434 | } | |
435 | ||
436 | /* Restore previous settings */ | |
437 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
438 | ||
439 | return status; | |
440 | } | |
441 | ||
7b334fcb | 442 | static enum drm_connector_status |
930a9e28 | 443 | intel_crt_detect(struct drm_connector *connector, bool force) |
79e53945 JB |
444 | { |
445 | struct drm_device *dev = connector->dev; | |
c9a1c4cd | 446 | struct intel_crt *crt = intel_attached_crt(connector); |
e4a5d54f ML |
447 | struct drm_crtc *crtc; |
448 | int dpms_mode; | |
449 | enum drm_connector_status status; | |
79e53945 | 450 | |
a6c45cf0 | 451 | if (I915_HAS_HOTPLUG(dev)) { |
6ec3d0c0 CW |
452 | if (intel_crt_detect_hotplug(connector)) { |
453 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
79e53945 | 454 | return connector_status_connected; |
6ec3d0c0 | 455 | } else |
79e53945 JB |
456 | return connector_status_disconnected; |
457 | } | |
458 | ||
c9a1c4cd | 459 | if (intel_crt_detect_ddc(crt)) |
79e53945 JB |
460 | return connector_status_connected; |
461 | ||
930a9e28 | 462 | if (!force) |
7b334fcb CW |
463 | return connector->status; |
464 | ||
e4a5d54f | 465 | /* for pre-945g platforms use load detect */ |
c9a1c4cd CW |
466 | crtc = crt->base.base.crtc; |
467 | if (crtc && crtc->enabled) { | |
468 | status = intel_crt_load_detect(crtc, crt); | |
e4a5d54f | 469 | } else { |
c9a1c4cd | 470 | crtc = intel_get_load_detect_pipe(&crt->base, connector, |
e4a5d54f ML |
471 | NULL, &dpms_mode); |
472 | if (crtc) { | |
c9a1c4cd | 473 | if (intel_crt_detect_ddc(crt)) |
6ec3d0c0 CW |
474 | status = connector_status_connected; |
475 | else | |
c9a1c4cd CW |
476 | status = intel_crt_load_detect(crtc, crt); |
477 | intel_release_load_detect_pipe(&crt->base, | |
c1c43977 | 478 | connector, dpms_mode); |
e4a5d54f ML |
479 | } else |
480 | status = connector_status_unknown; | |
481 | } | |
482 | ||
483 | return status; | |
79e53945 JB |
484 | } |
485 | ||
486 | static void intel_crt_destroy(struct drm_connector *connector) | |
487 | { | |
79e53945 JB |
488 | drm_sysfs_connector_remove(connector); |
489 | drm_connector_cleanup(connector); | |
490 | kfree(connector); | |
491 | } | |
492 | ||
493 | static int intel_crt_get_modes(struct drm_connector *connector) | |
494 | { | |
8e4d36b9 | 495 | struct drm_device *dev = connector->dev; |
f899fc64 | 496 | struct drm_i915_private *dev_priv = dev->dev_private; |
890f3359 | 497 | int ret; |
8e4d36b9 | 498 | |
f899fc64 CW |
499 | ret = intel_ddc_get_modes(connector, |
500 | &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter); | |
8e4d36b9 | 501 | if (ret || !IS_G4X(dev)) |
f899fc64 | 502 | return ret; |
8e4d36b9 | 503 | |
8e4d36b9 | 504 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
f899fc64 CW |
505 | return intel_ddc_get_modes(connector, |
506 | &dev_priv->gmbus[GMBUS_PORT_DPB].adapter); | |
79e53945 JB |
507 | } |
508 | ||
509 | static int intel_crt_set_property(struct drm_connector *connector, | |
510 | struct drm_property *property, | |
511 | uint64_t value) | |
512 | { | |
79e53945 JB |
513 | return 0; |
514 | } | |
515 | ||
516 | /* | |
517 | * Routines for controlling stuff on the analog port | |
518 | */ | |
519 | ||
520 | static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = { | |
521 | .dpms = intel_crt_dpms, | |
522 | .mode_fixup = intel_crt_mode_fixup, | |
523 | .prepare = intel_encoder_prepare, | |
524 | .commit = intel_encoder_commit, | |
525 | .mode_set = intel_crt_mode_set, | |
526 | }; | |
527 | ||
528 | static const struct drm_connector_funcs intel_crt_connector_funcs = { | |
c9fb15f6 | 529 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
530 | .detect = intel_crt_detect, |
531 | .fill_modes = drm_helper_probe_single_connector_modes, | |
532 | .destroy = intel_crt_destroy, | |
533 | .set_property = intel_crt_set_property, | |
534 | }; | |
535 | ||
536 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
537 | .mode_valid = intel_crt_mode_valid, | |
538 | .get_modes = intel_crt_get_modes, | |
df0e9248 | 539 | .best_encoder = intel_best_encoder, |
79e53945 JB |
540 | }; |
541 | ||
79e53945 | 542 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
ea5b213a | 543 | .destroy = intel_encoder_destroy, |
79e53945 JB |
544 | }; |
545 | ||
546 | void intel_crt_init(struct drm_device *dev) | |
547 | { | |
548 | struct drm_connector *connector; | |
c9a1c4cd | 549 | struct intel_crt *crt; |
454c1ca8 | 550 | struct intel_connector *intel_connector; |
db545019 | 551 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 552 | |
c9a1c4cd CW |
553 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
554 | if (!crt) | |
79e53945 JB |
555 | return; |
556 | ||
454c1ca8 ZW |
557 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
558 | if (!intel_connector) { | |
c9a1c4cd | 559 | kfree(crt); |
454c1ca8 ZW |
560 | return; |
561 | } | |
562 | ||
563 | connector = &intel_connector->base; | |
564 | drm_connector_init(dev, &intel_connector->base, | |
79e53945 JB |
565 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
566 | ||
c9a1c4cd | 567 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
79e53945 JB |
568 | DRM_MODE_ENCODER_DAC); |
569 | ||
c9a1c4cd | 570 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 571 | |
c9a1c4cd CW |
572 | crt->base.type = INTEL_OUTPUT_ANALOG; |
573 | crt->base.clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT | | |
574 | 1 << INTEL_ANALOG_CLONE_BIT | | |
575 | 1 << INTEL_SDVO_LVDS_CLONE_BIT); | |
576 | crt->base.crtc_mask = (1 << 0) | (1 << 1); | |
734b4157 | 577 | connector->interlace_allowed = 1; |
79e53945 JB |
578 | connector->doublescan_allowed = 0; |
579 | ||
c9a1c4cd | 580 | drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs); |
79e53945 JB |
581 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
582 | ||
583 | drm_sysfs_connector_add(connector); | |
b01f2c3a | 584 | |
eb1f8e4f DA |
585 | if (I915_HAS_HOTPLUG(dev)) |
586 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
587 | else | |
588 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
589 | ||
b01f2c3a | 590 | dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; |
79e53945 | 591 | } |