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7ff89ca2 VS |
1 | /* |
2 | * Copyright © 2006-2017 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "intel_drv.h" | |
25 | ||
26 | /** | |
27 | * DOC: CDCLK / RAWCLK | |
28 | * | |
29 | * The display engine uses several different clocks to do its work. There | |
30 | * are two main clocks involved that aren't directly related to the actual | |
31 | * pixel clock or any symbol/bit clock of the actual output port. These | |
32 | * are the core display clock (CDCLK) and RAWCLK. | |
33 | * | |
34 | * CDCLK clocks most of the display pipe logic, and thus its frequency | |
35 | * must be high enough to support the rate at which pixels are flowing | |
36 | * through the pipes. Downscaling must also be accounted as that increases | |
37 | * the effective pixel rate. | |
38 | * | |
39 | * On several platforms the CDCLK frequency can be changed dynamically | |
40 | * to minimize power consumption for a given display configuration. | |
41 | * Typically changes to the CDCLK frequency require all the display pipes | |
42 | * to be shut down while the frequency is being changed. | |
43 | * | |
44 | * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. | |
45 | * DMC will not change the active CDCLK frequency however, so that part | |
46 | * will still be performed by the driver directly. | |
47 | * | |
48 | * RAWCLK is a fixed frequency clock, often used by various auxiliary | |
49 | * blocks such as AUX CH or backlight PWM. Hence the only thing we | |
50 | * really need to know about RAWCLK is its frequency so that various | |
51 | * dividers can be programmed correctly. | |
52 | */ | |
53 | ||
49cd97a3 VS |
54 | static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, |
55 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 56 | { |
49cd97a3 | 57 | cdclk_state->cdclk = 133333; |
7ff89ca2 VS |
58 | } |
59 | ||
49cd97a3 VS |
60 | static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, |
61 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 62 | { |
49cd97a3 | 63 | cdclk_state->cdclk = 200000; |
7ff89ca2 VS |
64 | } |
65 | ||
49cd97a3 VS |
66 | static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, |
67 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 68 | { |
49cd97a3 | 69 | cdclk_state->cdclk = 266667; |
7ff89ca2 VS |
70 | } |
71 | ||
49cd97a3 VS |
72 | static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, |
73 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 74 | { |
49cd97a3 | 75 | cdclk_state->cdclk = 333333; |
7ff89ca2 VS |
76 | } |
77 | ||
49cd97a3 VS |
78 | static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, |
79 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 80 | { |
49cd97a3 | 81 | cdclk_state->cdclk = 400000; |
7ff89ca2 VS |
82 | } |
83 | ||
49cd97a3 VS |
84 | static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, |
85 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 86 | { |
49cd97a3 | 87 | cdclk_state->cdclk = 450000; |
7ff89ca2 VS |
88 | } |
89 | ||
49cd97a3 VS |
90 | static void i85x_get_cdclk(struct drm_i915_private *dev_priv, |
91 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
92 | { |
93 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
94 | u16 hpllcc = 0; | |
95 | ||
96 | /* | |
97 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
98 | * encoding is different :( | |
99 | * FIXME is this the right way to detect 852GM/852GMV? | |
100 | */ | |
49cd97a3 VS |
101 | if (pdev->revision == 0x1) { |
102 | cdclk_state->cdclk = 133333; | |
103 | return; | |
104 | } | |
7ff89ca2 VS |
105 | |
106 | pci_bus_read_config_word(pdev->bus, | |
107 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
108 | ||
109 | /* Assume that the hardware is in the high speed state. This | |
110 | * should be the default. | |
111 | */ | |
112 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
113 | case GC_CLOCK_133_200: | |
114 | case GC_CLOCK_133_200_2: | |
115 | case GC_CLOCK_100_200: | |
49cd97a3 VS |
116 | cdclk_state->cdclk = 200000; |
117 | break; | |
7ff89ca2 | 118 | case GC_CLOCK_166_250: |
49cd97a3 VS |
119 | cdclk_state->cdclk = 250000; |
120 | break; | |
7ff89ca2 | 121 | case GC_CLOCK_100_133: |
49cd97a3 VS |
122 | cdclk_state->cdclk = 133333; |
123 | break; | |
7ff89ca2 VS |
124 | case GC_CLOCK_133_266: |
125 | case GC_CLOCK_133_266_2: | |
126 | case GC_CLOCK_166_266: | |
49cd97a3 VS |
127 | cdclk_state->cdclk = 266667; |
128 | break; | |
7ff89ca2 | 129 | } |
7ff89ca2 VS |
130 | } |
131 | ||
49cd97a3 VS |
132 | static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, |
133 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
134 | { |
135 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
136 | u16 gcfgc = 0; | |
137 | ||
138 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
139 | ||
49cd97a3 VS |
140 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { |
141 | cdclk_state->cdclk = 133333; | |
142 | return; | |
143 | } | |
7ff89ca2 VS |
144 | |
145 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
146 | case GC_DISPLAY_CLOCK_333_320_MHZ: | |
49cd97a3 VS |
147 | cdclk_state->cdclk = 333333; |
148 | break; | |
7ff89ca2 VS |
149 | default: |
150 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
49cd97a3 VS |
151 | cdclk_state->cdclk = 190000; |
152 | break; | |
7ff89ca2 VS |
153 | } |
154 | } | |
155 | ||
49cd97a3 VS |
156 | static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, |
157 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
158 | { |
159 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
160 | u16 gcfgc = 0; | |
161 | ||
162 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
163 | ||
49cd97a3 VS |
164 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { |
165 | cdclk_state->cdclk = 133333; | |
166 | return; | |
167 | } | |
7ff89ca2 VS |
168 | |
169 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
170 | case GC_DISPLAY_CLOCK_333_320_MHZ: | |
49cd97a3 VS |
171 | cdclk_state->cdclk = 320000; |
172 | break; | |
7ff89ca2 VS |
173 | default: |
174 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
49cd97a3 VS |
175 | cdclk_state->cdclk = 200000; |
176 | break; | |
7ff89ca2 VS |
177 | } |
178 | } | |
179 | ||
180 | static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) | |
181 | { | |
182 | static const unsigned int blb_vco[8] = { | |
183 | [0] = 3200000, | |
184 | [1] = 4000000, | |
185 | [2] = 5333333, | |
186 | [3] = 4800000, | |
187 | [4] = 6400000, | |
188 | }; | |
189 | static const unsigned int pnv_vco[8] = { | |
190 | [0] = 3200000, | |
191 | [1] = 4000000, | |
192 | [2] = 5333333, | |
193 | [3] = 4800000, | |
194 | [4] = 2666667, | |
195 | }; | |
196 | static const unsigned int cl_vco[8] = { | |
197 | [0] = 3200000, | |
198 | [1] = 4000000, | |
199 | [2] = 5333333, | |
200 | [3] = 6400000, | |
201 | [4] = 3333333, | |
202 | [5] = 3566667, | |
203 | [6] = 4266667, | |
204 | }; | |
205 | static const unsigned int elk_vco[8] = { | |
206 | [0] = 3200000, | |
207 | [1] = 4000000, | |
208 | [2] = 5333333, | |
209 | [3] = 4800000, | |
210 | }; | |
211 | static const unsigned int ctg_vco[8] = { | |
212 | [0] = 3200000, | |
213 | [1] = 4000000, | |
214 | [2] = 5333333, | |
215 | [3] = 6400000, | |
216 | [4] = 2666667, | |
217 | [5] = 4266667, | |
218 | }; | |
219 | const unsigned int *vco_table; | |
220 | unsigned int vco; | |
221 | uint8_t tmp = 0; | |
222 | ||
223 | /* FIXME other chipsets? */ | |
224 | if (IS_GM45(dev_priv)) | |
225 | vco_table = ctg_vco; | |
6b9e441d | 226 | else if (IS_G45(dev_priv)) |
7ff89ca2 VS |
227 | vco_table = elk_vco; |
228 | else if (IS_I965GM(dev_priv)) | |
229 | vco_table = cl_vco; | |
230 | else if (IS_PINEVIEW(dev_priv)) | |
231 | vco_table = pnv_vco; | |
232 | else if (IS_G33(dev_priv)) | |
233 | vco_table = blb_vco; | |
234 | else | |
235 | return 0; | |
236 | ||
237 | tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); | |
238 | ||
239 | vco = vco_table[tmp & 0x7]; | |
240 | if (vco == 0) | |
241 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
242 | else | |
243 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
244 | ||
245 | return vco; | |
246 | } | |
247 | ||
49cd97a3 VS |
248 | static void g33_get_cdclk(struct drm_i915_private *dev_priv, |
249 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
250 | { |
251 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
252 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
253 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
254 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
255 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
256 | const uint8_t *div_table; | |
49cd97a3 | 257 | unsigned int cdclk_sel; |
7ff89ca2 VS |
258 | uint16_t tmp = 0; |
259 | ||
49cd97a3 VS |
260 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
261 | ||
7ff89ca2 VS |
262 | pci_read_config_word(pdev, GCFGC, &tmp); |
263 | ||
264 | cdclk_sel = (tmp >> 4) & 0x7; | |
265 | ||
266 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
267 | goto fail; | |
268 | ||
49cd97a3 | 269 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
270 | case 3200000: |
271 | div_table = div_3200; | |
272 | break; | |
273 | case 4000000: | |
274 | div_table = div_4000; | |
275 | break; | |
276 | case 4800000: | |
277 | div_table = div_4800; | |
278 | break; | |
279 | case 5333333: | |
280 | div_table = div_5333; | |
281 | break; | |
282 | default: | |
283 | goto fail; | |
284 | } | |
285 | ||
49cd97a3 VS |
286 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, |
287 | div_table[cdclk_sel]); | |
288 | return; | |
7ff89ca2 VS |
289 | |
290 | fail: | |
291 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", | |
49cd97a3 VS |
292 | cdclk_state->vco, tmp); |
293 | cdclk_state->cdclk = 190476; | |
7ff89ca2 VS |
294 | } |
295 | ||
49cd97a3 VS |
296 | static void pnv_get_cdclk(struct drm_i915_private *dev_priv, |
297 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
298 | { |
299 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
300 | u16 gcfgc = 0; | |
301 | ||
302 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
303 | ||
304 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
305 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
49cd97a3 VS |
306 | cdclk_state->cdclk = 266667; |
307 | break; | |
7ff89ca2 | 308 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
49cd97a3 VS |
309 | cdclk_state->cdclk = 333333; |
310 | break; | |
7ff89ca2 | 311 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
49cd97a3 VS |
312 | cdclk_state->cdclk = 444444; |
313 | break; | |
7ff89ca2 | 314 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
49cd97a3 VS |
315 | cdclk_state->cdclk = 200000; |
316 | break; | |
7ff89ca2 VS |
317 | default: |
318 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
319 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
49cd97a3 VS |
320 | cdclk_state->cdclk = 133333; |
321 | break; | |
7ff89ca2 | 322 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
49cd97a3 VS |
323 | cdclk_state->cdclk = 166667; |
324 | break; | |
7ff89ca2 VS |
325 | } |
326 | } | |
327 | ||
49cd97a3 VS |
328 | static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, |
329 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
330 | { |
331 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
332 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
333 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
334 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
335 | const uint8_t *div_table; | |
49cd97a3 | 336 | unsigned int cdclk_sel; |
7ff89ca2 VS |
337 | uint16_t tmp = 0; |
338 | ||
49cd97a3 VS |
339 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
340 | ||
7ff89ca2 VS |
341 | pci_read_config_word(pdev, GCFGC, &tmp); |
342 | ||
343 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
344 | ||
345 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
346 | goto fail; | |
347 | ||
49cd97a3 | 348 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
349 | case 3200000: |
350 | div_table = div_3200; | |
351 | break; | |
352 | case 4000000: | |
353 | div_table = div_4000; | |
354 | break; | |
355 | case 5333333: | |
356 | div_table = div_5333; | |
357 | break; | |
358 | default: | |
359 | goto fail; | |
360 | } | |
361 | ||
49cd97a3 VS |
362 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, |
363 | div_table[cdclk_sel]); | |
364 | return; | |
7ff89ca2 VS |
365 | |
366 | fail: | |
367 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", | |
49cd97a3 VS |
368 | cdclk_state->vco, tmp); |
369 | cdclk_state->cdclk = 200000; | |
7ff89ca2 VS |
370 | } |
371 | ||
49cd97a3 VS |
372 | static void gm45_get_cdclk(struct drm_i915_private *dev_priv, |
373 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
374 | { |
375 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
49cd97a3 | 376 | unsigned int cdclk_sel; |
7ff89ca2 VS |
377 | uint16_t tmp = 0; |
378 | ||
49cd97a3 VS |
379 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
380 | ||
7ff89ca2 VS |
381 | pci_read_config_word(pdev, GCFGC, &tmp); |
382 | ||
383 | cdclk_sel = (tmp >> 12) & 0x1; | |
384 | ||
49cd97a3 | 385 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
386 | case 2666667: |
387 | case 4000000: | |
388 | case 5333333: | |
49cd97a3 VS |
389 | cdclk_state->cdclk = cdclk_sel ? 333333 : 222222; |
390 | break; | |
7ff89ca2 | 391 | case 3200000: |
49cd97a3 VS |
392 | cdclk_state->cdclk = cdclk_sel ? 320000 : 228571; |
393 | break; | |
7ff89ca2 VS |
394 | default: |
395 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", | |
49cd97a3 VS |
396 | cdclk_state->vco, tmp); |
397 | cdclk_state->cdclk = 222222; | |
398 | break; | |
7ff89ca2 VS |
399 | } |
400 | } | |
401 | ||
49cd97a3 VS |
402 | static void hsw_get_cdclk(struct drm_i915_private *dev_priv, |
403 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
404 | { |
405 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
406 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
407 | ||
408 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
49cd97a3 | 409 | cdclk_state->cdclk = 800000; |
7ff89ca2 | 410 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
49cd97a3 | 411 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 412 | else if (freq == LCPLL_CLK_FREQ_450) |
49cd97a3 | 413 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 414 | else if (IS_HSW_ULT(dev_priv)) |
49cd97a3 | 415 | cdclk_state->cdclk = 337500; |
7ff89ca2 | 416 | else |
49cd97a3 | 417 | cdclk_state->cdclk = 540000; |
7ff89ca2 VS |
418 | } |
419 | ||
420 | static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, | |
421 | int max_pixclk) | |
422 | { | |
423 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? | |
424 | 333333 : 320000; | |
425 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; | |
426 | ||
427 | /* | |
428 | * We seem to get an unstable or solid color picture at 200MHz. | |
429 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
430 | * are off. | |
431 | */ | |
432 | if (!IS_CHERRYVIEW(dev_priv) && | |
433 | max_pixclk > freq_320*limit/100) | |
434 | return 400000; | |
435 | else if (max_pixclk > 266667*limit/100) | |
436 | return freq_320; | |
437 | else if (max_pixclk > 0) | |
438 | return 266667; | |
439 | else | |
440 | return 200000; | |
441 | } | |
442 | ||
49cd97a3 VS |
443 | static void vlv_get_cdclk(struct drm_i915_private *dev_priv, |
444 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 445 | { |
49cd97a3 VS |
446 | cdclk_state->vco = vlv_get_hpll_vco(dev_priv); |
447 | cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", | |
448 | CCK_DISPLAY_CLOCK_CONTROL, | |
449 | cdclk_state->vco); | |
7ff89ca2 VS |
450 | } |
451 | ||
452 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) | |
453 | { | |
454 | unsigned int credits, default_credits; | |
455 | ||
456 | if (IS_CHERRYVIEW(dev_priv)) | |
457 | default_credits = PFI_CREDIT(12); | |
458 | else | |
459 | default_credits = PFI_CREDIT(8); | |
460 | ||
49cd97a3 | 461 | if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { |
7ff89ca2 VS |
462 | /* CHV suggested value is 31 or 63 */ |
463 | if (IS_CHERRYVIEW(dev_priv)) | |
464 | credits = PFI_CREDIT_63; | |
465 | else | |
466 | credits = PFI_CREDIT(15); | |
467 | } else { | |
468 | credits = default_credits; | |
469 | } | |
470 | ||
471 | /* | |
472 | * WA - write default credits before re-programming | |
473 | * FIXME: should we also set the resend bit here? | |
474 | */ | |
475 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
476 | default_credits); | |
477 | ||
478 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
479 | credits | PFI_CREDIT_RESEND); | |
480 | ||
481 | /* | |
482 | * FIXME is this guaranteed to clear | |
483 | * immediately or should we poll for it? | |
484 | */ | |
485 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
486 | } | |
487 | ||
83c5fda7 VS |
488 | static void vlv_set_cdclk(struct drm_i915_private *dev_priv, |
489 | const struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 490 | { |
83c5fda7 | 491 | int cdclk = cdclk_state->cdclk; |
7ff89ca2 VS |
492 | u32 val, cmd; |
493 | ||
7ff89ca2 VS |
494 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
495 | cmd = 2; | |
496 | else if (cdclk == 266667) | |
497 | cmd = 1; | |
498 | else | |
499 | cmd = 0; | |
500 | ||
501 | mutex_lock(&dev_priv->rps.hw_lock); | |
502 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
503 | val &= ~DSPFREQGUAR_MASK; | |
504 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
505 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
506 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
507 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
508 | 50)) { | |
509 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
510 | } | |
511 | mutex_unlock(&dev_priv->rps.hw_lock); | |
512 | ||
513 | mutex_lock(&dev_priv->sb_lock); | |
514 | ||
515 | if (cdclk == 400000) { | |
516 | u32 divider; | |
517 | ||
518 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, | |
519 | cdclk) - 1; | |
520 | ||
521 | /* adjust cdclk divider */ | |
522 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
523 | val &= ~CCK_FREQUENCY_VALUES; | |
524 | val |= divider; | |
525 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
526 | ||
527 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
528 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
529 | 50)) | |
530 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
531 | } | |
532 | ||
533 | /* adjust self-refresh exit latency value */ | |
534 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
535 | val &= ~0x7f; | |
536 | ||
537 | /* | |
538 | * For high bandwidth configs, we set a higher latency in the bunit | |
539 | * so that the core display fetch happens in time to avoid underruns. | |
540 | */ | |
541 | if (cdclk == 400000) | |
542 | val |= 4500 / 250; /* 4.5 usec */ | |
543 | else | |
544 | val |= 3000 / 250; /* 3.0 usec */ | |
545 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
546 | ||
547 | mutex_unlock(&dev_priv->sb_lock); | |
548 | ||
549 | intel_update_cdclk(dev_priv); | |
1a5301a5 VS |
550 | |
551 | vlv_program_pfi_credits(dev_priv); | |
7ff89ca2 VS |
552 | } |
553 | ||
83c5fda7 VS |
554 | static void chv_set_cdclk(struct drm_i915_private *dev_priv, |
555 | const struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 556 | { |
83c5fda7 | 557 | int cdclk = cdclk_state->cdclk; |
7ff89ca2 VS |
558 | u32 val, cmd; |
559 | ||
7ff89ca2 VS |
560 | switch (cdclk) { |
561 | case 333333: | |
562 | case 320000: | |
563 | case 266667: | |
564 | case 200000: | |
565 | break; | |
566 | default: | |
567 | MISSING_CASE(cdclk); | |
568 | return; | |
569 | } | |
570 | ||
571 | /* | |
572 | * Specs are full of misinformation, but testing on actual | |
573 | * hardware has shown that we just need to write the desired | |
574 | * CCK divider into the Punit register. | |
575 | */ | |
576 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
577 | ||
578 | mutex_lock(&dev_priv->rps.hw_lock); | |
579 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
580 | val &= ~DSPFREQGUAR_MASK_CHV; | |
581 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
582 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
583 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
584 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
585 | 50)) { | |
586 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
587 | } | |
588 | mutex_unlock(&dev_priv->rps.hw_lock); | |
589 | ||
590 | intel_update_cdclk(dev_priv); | |
1a5301a5 VS |
591 | |
592 | vlv_program_pfi_credits(dev_priv); | |
7ff89ca2 VS |
593 | } |
594 | ||
595 | static int bdw_calc_cdclk(int max_pixclk) | |
596 | { | |
597 | if (max_pixclk > 540000) | |
598 | return 675000; | |
599 | else if (max_pixclk > 450000) | |
600 | return 540000; | |
601 | else if (max_pixclk > 337500) | |
602 | return 450000; | |
603 | else | |
604 | return 337500; | |
605 | } | |
606 | ||
49cd97a3 VS |
607 | static void bdw_get_cdclk(struct drm_i915_private *dev_priv, |
608 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
609 | { |
610 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
611 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
612 | ||
613 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
49cd97a3 | 614 | cdclk_state->cdclk = 800000; |
7ff89ca2 | 615 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
49cd97a3 | 616 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 617 | else if (freq == LCPLL_CLK_FREQ_450) |
49cd97a3 | 618 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 619 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) |
49cd97a3 | 620 | cdclk_state->cdclk = 540000; |
7ff89ca2 | 621 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) |
49cd97a3 | 622 | cdclk_state->cdclk = 337500; |
7ff89ca2 | 623 | else |
49cd97a3 | 624 | cdclk_state->cdclk = 675000; |
7ff89ca2 VS |
625 | } |
626 | ||
83c5fda7 VS |
627 | static void bdw_set_cdclk(struct drm_i915_private *dev_priv, |
628 | const struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 629 | { |
83c5fda7 | 630 | int cdclk = cdclk_state->cdclk; |
7ff89ca2 VS |
631 | uint32_t val, data; |
632 | int ret; | |
633 | ||
634 | if (WARN((I915_READ(LCPLL_CTL) & | |
635 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
636 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
637 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
638 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
639 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
640 | return; | |
641 | ||
642 | mutex_lock(&dev_priv->rps.hw_lock); | |
643 | ret = sandybridge_pcode_write(dev_priv, | |
644 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
645 | mutex_unlock(&dev_priv->rps.hw_lock); | |
646 | if (ret) { | |
647 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
648 | return; | |
649 | } | |
650 | ||
651 | val = I915_READ(LCPLL_CTL); | |
652 | val |= LCPLL_CD_SOURCE_FCLK; | |
653 | I915_WRITE(LCPLL_CTL, val); | |
654 | ||
655 | if (wait_for_us(I915_READ(LCPLL_CTL) & | |
656 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
657 | DRM_ERROR("Switching to FCLK failed\n"); | |
658 | ||
659 | val = I915_READ(LCPLL_CTL); | |
660 | val &= ~LCPLL_CLK_FREQ_MASK; | |
661 | ||
662 | switch (cdclk) { | |
663 | case 450000: | |
664 | val |= LCPLL_CLK_FREQ_450; | |
665 | data = 0; | |
666 | break; | |
667 | case 540000: | |
668 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
669 | data = 1; | |
670 | break; | |
671 | case 337500: | |
672 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
673 | data = 2; | |
674 | break; | |
675 | case 675000: | |
676 | val |= LCPLL_CLK_FREQ_675_BDW; | |
677 | data = 3; | |
678 | break; | |
679 | default: | |
680 | WARN(1, "invalid cdclk frequency\n"); | |
681 | return; | |
682 | } | |
683 | ||
684 | I915_WRITE(LCPLL_CTL, val); | |
685 | ||
686 | val = I915_READ(LCPLL_CTL); | |
687 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
688 | I915_WRITE(LCPLL_CTL, val); | |
689 | ||
690 | if (wait_for_us((I915_READ(LCPLL_CTL) & | |
691 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
692 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
693 | ||
694 | mutex_lock(&dev_priv->rps.hw_lock); | |
695 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
696 | mutex_unlock(&dev_priv->rps.hw_lock); | |
697 | ||
698 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); | |
699 | ||
700 | intel_update_cdclk(dev_priv); | |
701 | ||
49cd97a3 | 702 | WARN(cdclk != dev_priv->cdclk.hw.cdclk, |
7ff89ca2 | 703 | "cdclk requested %d kHz but got %d kHz\n", |
49cd97a3 | 704 | cdclk, dev_priv->cdclk.hw.cdclk); |
7ff89ca2 VS |
705 | } |
706 | ||
707 | static int skl_calc_cdclk(int max_pixclk, int vco) | |
708 | { | |
709 | if (vco == 8640000) { | |
710 | if (max_pixclk > 540000) | |
711 | return 617143; | |
712 | else if (max_pixclk > 432000) | |
713 | return 540000; | |
714 | else if (max_pixclk > 308571) | |
715 | return 432000; | |
716 | else | |
717 | return 308571; | |
718 | } else { | |
719 | if (max_pixclk > 540000) | |
720 | return 675000; | |
721 | else if (max_pixclk > 450000) | |
722 | return 540000; | |
723 | else if (max_pixclk > 337500) | |
724 | return 450000; | |
725 | else | |
726 | return 337500; | |
727 | } | |
728 | } | |
729 | ||
49cd97a3 VS |
730 | static void skl_dpll0_update(struct drm_i915_private *dev_priv, |
731 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
732 | { |
733 | u32 val; | |
734 | ||
49cd97a3 VS |
735 | cdclk_state->ref = 24000; |
736 | cdclk_state->vco = 0; | |
7ff89ca2 VS |
737 | |
738 | val = I915_READ(LCPLL1_CTL); | |
739 | if ((val & LCPLL_PLL_ENABLE) == 0) | |
740 | return; | |
741 | ||
742 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) | |
743 | return; | |
744 | ||
745 | val = I915_READ(DPLL_CTRL1); | |
746 | ||
747 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | | |
748 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
749 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
750 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
751 | return; | |
752 | ||
753 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { | |
754 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
755 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
756 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
757 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
49cd97a3 | 758 | cdclk_state->vco = 8100000; |
7ff89ca2 VS |
759 | break; |
760 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
761 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
49cd97a3 | 762 | cdclk_state->vco = 8640000; |
7ff89ca2 VS |
763 | break; |
764 | default: | |
765 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
766 | break; | |
767 | } | |
768 | } | |
769 | ||
49cd97a3 VS |
770 | static void skl_get_cdclk(struct drm_i915_private *dev_priv, |
771 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
772 | { |
773 | u32 cdctl; | |
774 | ||
49cd97a3 | 775 | skl_dpll0_update(dev_priv, cdclk_state); |
7ff89ca2 | 776 | |
49cd97a3 VS |
777 | cdclk_state->cdclk = cdclk_state->ref; |
778 | ||
779 | if (cdclk_state->vco == 0) | |
780 | return; | |
7ff89ca2 VS |
781 | |
782 | cdctl = I915_READ(CDCLK_CTL); | |
783 | ||
49cd97a3 | 784 | if (cdclk_state->vco == 8640000) { |
7ff89ca2 VS |
785 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
786 | case CDCLK_FREQ_450_432: | |
49cd97a3 VS |
787 | cdclk_state->cdclk = 432000; |
788 | break; | |
7ff89ca2 | 789 | case CDCLK_FREQ_337_308: |
49cd97a3 VS |
790 | cdclk_state->cdclk = 308571; |
791 | break; | |
7ff89ca2 | 792 | case CDCLK_FREQ_540: |
49cd97a3 VS |
793 | cdclk_state->cdclk = 540000; |
794 | break; | |
7ff89ca2 | 795 | case CDCLK_FREQ_675_617: |
49cd97a3 VS |
796 | cdclk_state->cdclk = 617143; |
797 | break; | |
7ff89ca2 VS |
798 | default: |
799 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); | |
49cd97a3 | 800 | break; |
7ff89ca2 VS |
801 | } |
802 | } else { | |
803 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
804 | case CDCLK_FREQ_450_432: | |
49cd97a3 VS |
805 | cdclk_state->cdclk = 450000; |
806 | break; | |
7ff89ca2 | 807 | case CDCLK_FREQ_337_308: |
49cd97a3 VS |
808 | cdclk_state->cdclk = 337500; |
809 | break; | |
7ff89ca2 | 810 | case CDCLK_FREQ_540: |
49cd97a3 VS |
811 | cdclk_state->cdclk = 540000; |
812 | break; | |
7ff89ca2 | 813 | case CDCLK_FREQ_675_617: |
49cd97a3 VS |
814 | cdclk_state->cdclk = 675000; |
815 | break; | |
7ff89ca2 VS |
816 | default: |
817 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); | |
49cd97a3 | 818 | break; |
7ff89ca2 VS |
819 | } |
820 | } | |
7ff89ca2 VS |
821 | } |
822 | ||
823 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
824 | static int skl_cdclk_decimal(int cdclk) | |
825 | { | |
826 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
827 | } | |
828 | ||
829 | static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, | |
830 | int vco) | |
831 | { | |
832 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
833 | ||
834 | dev_priv->skl_preferred_vco_freq = vco; | |
835 | ||
836 | if (changed) | |
837 | intel_update_max_cdclk(dev_priv); | |
838 | } | |
839 | ||
840 | static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) | |
841 | { | |
842 | int min_cdclk = skl_calc_cdclk(0, vco); | |
843 | u32 val; | |
844 | ||
845 | WARN_ON(vco != 8100000 && vco != 8640000); | |
846 | ||
847 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
848 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); | |
849 | I915_WRITE(CDCLK_CTL, val); | |
850 | POSTING_READ(CDCLK_CTL); | |
851 | ||
852 | /* | |
853 | * We always enable DPLL0 with the lowest link rate possible, but still | |
854 | * taking into account the VCO required to operate the eDP panel at the | |
855 | * desired frequency. The usual DP link rates operate with a VCO of | |
856 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
857 | * The modeset code is responsible for the selection of the exact link | |
858 | * rate later on, with the constraint of choosing a frequency that | |
859 | * works with vco. | |
860 | */ | |
861 | val = I915_READ(DPLL_CTRL1); | |
862 | ||
863 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
864 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
865 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
866 | if (vco == 8640000) | |
867 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
868 | SKL_DPLL0); | |
869 | else | |
870 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
871 | SKL_DPLL0); | |
872 | ||
873 | I915_WRITE(DPLL_CTRL1, val); | |
874 | POSTING_READ(DPLL_CTRL1); | |
875 | ||
876 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
877 | ||
878 | if (intel_wait_for_register(dev_priv, | |
879 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
880 | 5)) | |
881 | DRM_ERROR("DPLL0 not locked\n"); | |
882 | ||
49cd97a3 | 883 | dev_priv->cdclk.hw.vco = vco; |
7ff89ca2 VS |
884 | |
885 | /* We'll want to keep using the current vco from now on. */ | |
886 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
887 | } | |
888 | ||
889 | static void skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
890 | { | |
891 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
892 | if (intel_wait_for_register(dev_priv, | |
893 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
894 | 1)) | |
895 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
896 | ||
49cd97a3 | 897 | dev_priv->cdclk.hw.vco = 0; |
7ff89ca2 VS |
898 | } |
899 | ||
900 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, | |
83c5fda7 | 901 | const struct intel_cdclk_state *cdclk_state) |
7ff89ca2 | 902 | { |
83c5fda7 VS |
903 | int cdclk = cdclk_state->cdclk; |
904 | int vco = cdclk_state->vco; | |
7ff89ca2 VS |
905 | u32 freq_select, pcu_ack; |
906 | int ret; | |
907 | ||
908 | WARN_ON((cdclk == 24000) != (vco == 0)); | |
909 | ||
7ff89ca2 VS |
910 | mutex_lock(&dev_priv->rps.hw_lock); |
911 | ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, | |
912 | SKL_CDCLK_PREPARE_FOR_CHANGE, | |
913 | SKL_CDCLK_READY_FOR_CHANGE, | |
914 | SKL_CDCLK_READY_FOR_CHANGE, 3); | |
915 | mutex_unlock(&dev_priv->rps.hw_lock); | |
916 | if (ret) { | |
917 | DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", | |
918 | ret); | |
919 | return; | |
920 | } | |
921 | ||
922 | /* set CDCLK_CTL */ | |
923 | switch (cdclk) { | |
924 | case 450000: | |
925 | case 432000: | |
926 | freq_select = CDCLK_FREQ_450_432; | |
927 | pcu_ack = 1; | |
928 | break; | |
929 | case 540000: | |
930 | freq_select = CDCLK_FREQ_540; | |
931 | pcu_ack = 2; | |
932 | break; | |
933 | case 308571: | |
934 | case 337500: | |
935 | default: | |
936 | freq_select = CDCLK_FREQ_337_308; | |
937 | pcu_ack = 0; | |
938 | break; | |
939 | case 617143: | |
940 | case 675000: | |
941 | freq_select = CDCLK_FREQ_675_617; | |
942 | pcu_ack = 3; | |
943 | break; | |
944 | } | |
945 | ||
49cd97a3 VS |
946 | if (dev_priv->cdclk.hw.vco != 0 && |
947 | dev_priv->cdclk.hw.vco != vco) | |
7ff89ca2 VS |
948 | skl_dpll0_disable(dev_priv); |
949 | ||
49cd97a3 | 950 | if (dev_priv->cdclk.hw.vco != vco) |
7ff89ca2 VS |
951 | skl_dpll0_enable(dev_priv, vco); |
952 | ||
953 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); | |
954 | POSTING_READ(CDCLK_CTL); | |
955 | ||
956 | /* inform PCU of the change */ | |
957 | mutex_lock(&dev_priv->rps.hw_lock); | |
958 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
959 | mutex_unlock(&dev_priv->rps.hw_lock); | |
960 | ||
961 | intel_update_cdclk(dev_priv); | |
962 | } | |
963 | ||
964 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
965 | { | |
966 | uint32_t cdctl, expected; | |
967 | ||
968 | /* | |
969 | * check if the pre-os initialized the display | |
970 | * There is SWF18 scratchpad register defined which is set by the | |
971 | * pre-os which can be used by the OS drivers to check the status | |
972 | */ | |
973 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
974 | goto sanitize; | |
975 | ||
976 | intel_update_cdclk(dev_priv); | |
977 | /* Is PLL enabled and locked ? */ | |
49cd97a3 VS |
978 | if (dev_priv->cdclk.hw.vco == 0 || |
979 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref) | |
7ff89ca2 VS |
980 | goto sanitize; |
981 | ||
982 | /* DPLL okay; verify the cdclock | |
983 | * | |
984 | * Noticed in some instances that the freq selection is correct but | |
985 | * decimal part is programmed wrong from BIOS where pre-os does not | |
986 | * enable display. Verify the same as well. | |
987 | */ | |
988 | cdctl = I915_READ(CDCLK_CTL); | |
989 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
49cd97a3 | 990 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); |
7ff89ca2 VS |
991 | if (cdctl == expected) |
992 | /* All well; nothing to sanitize */ | |
993 | return; | |
994 | ||
995 | sanitize: | |
996 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
997 | ||
998 | /* force cdclk programming */ | |
49cd97a3 | 999 | dev_priv->cdclk.hw.cdclk = 0; |
7ff89ca2 | 1000 | /* force full PLL disable + enable */ |
49cd97a3 | 1001 | dev_priv->cdclk.hw.vco = -1; |
7ff89ca2 VS |
1002 | } |
1003 | ||
1004 | /** | |
1005 | * skl_init_cdclk - Initialize CDCLK on SKL | |
1006 | * @dev_priv: i915 device | |
1007 | * | |
1008 | * Initialize CDCLK for SKL and derivatives. This is generally | |
1009 | * done only during the display core initialization sequence, | |
1010 | * after which the DMC will take care of turning CDCLK off/on | |
1011 | * as needed. | |
1012 | */ | |
1013 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
1014 | { | |
83c5fda7 | 1015 | struct intel_cdclk_state cdclk_state; |
7ff89ca2 VS |
1016 | |
1017 | skl_sanitize_cdclk(dev_priv); | |
1018 | ||
49cd97a3 VS |
1019 | if (dev_priv->cdclk.hw.cdclk != 0 && |
1020 | dev_priv->cdclk.hw.vco != 0) { | |
7ff89ca2 VS |
1021 | /* |
1022 | * Use the current vco as our initial | |
1023 | * guess as to what the preferred vco is. | |
1024 | */ | |
1025 | if (dev_priv->skl_preferred_vco_freq == 0) | |
1026 | skl_set_preferred_cdclk_vco(dev_priv, | |
49cd97a3 | 1027 | dev_priv->cdclk.hw.vco); |
7ff89ca2 VS |
1028 | return; |
1029 | } | |
1030 | ||
83c5fda7 VS |
1031 | cdclk_state = dev_priv->cdclk.hw; |
1032 | ||
1033 | cdclk_state.vco = dev_priv->skl_preferred_vco_freq; | |
1034 | if (cdclk_state.vco == 0) | |
1035 | cdclk_state.vco = 8100000; | |
1036 | cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); | |
7ff89ca2 | 1037 | |
83c5fda7 | 1038 | skl_set_cdclk(dev_priv, &cdclk_state); |
7ff89ca2 VS |
1039 | } |
1040 | ||
1041 | /** | |
1042 | * skl_uninit_cdclk - Uninitialize CDCLK on SKL | |
1043 | * @dev_priv: i915 device | |
1044 | * | |
1045 | * Uninitialize CDCLK for SKL and derivatives. This is done only | |
1046 | * during the display core uninitialization sequence. | |
1047 | */ | |
1048 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
1049 | { | |
83c5fda7 VS |
1050 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; |
1051 | ||
1052 | cdclk_state.cdclk = cdclk_state.ref; | |
1053 | cdclk_state.vco = 0; | |
1054 | ||
1055 | skl_set_cdclk(dev_priv, &cdclk_state); | |
7ff89ca2 VS |
1056 | } |
1057 | ||
1058 | static int bxt_calc_cdclk(int max_pixclk) | |
1059 | { | |
1060 | if (max_pixclk > 576000) | |
1061 | return 624000; | |
1062 | else if (max_pixclk > 384000) | |
1063 | return 576000; | |
1064 | else if (max_pixclk > 288000) | |
1065 | return 384000; | |
1066 | else if (max_pixclk > 144000) | |
1067 | return 288000; | |
1068 | else | |
1069 | return 144000; | |
1070 | } | |
1071 | ||
1072 | static int glk_calc_cdclk(int max_pixclk) | |
1073 | { | |
97f55ca5 MC |
1074 | /* |
1075 | * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk | |
1076 | * as a temporary workaround. Use a higher cdclk instead. (Note that | |
1077 | * intel_compute_max_dotclk() limits the max pixel clock to 99% of max | |
1078 | * cdclk.) | |
1079 | */ | |
1080 | if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100)) | |
7ff89ca2 | 1081 | return 316800; |
97f55ca5 | 1082 | else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100)) |
7ff89ca2 VS |
1083 | return 158400; |
1084 | else | |
1085 | return 79200; | |
1086 | } | |
1087 | ||
1088 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) | |
1089 | { | |
1090 | int ratio; | |
1091 | ||
49cd97a3 | 1092 | if (cdclk == dev_priv->cdclk.hw.ref) |
7ff89ca2 VS |
1093 | return 0; |
1094 | ||
1095 | switch (cdclk) { | |
1096 | default: | |
1097 | MISSING_CASE(cdclk); | |
1098 | case 144000: | |
1099 | case 288000: | |
1100 | case 384000: | |
1101 | case 576000: | |
1102 | ratio = 60; | |
1103 | break; | |
1104 | case 624000: | |
1105 | ratio = 65; | |
1106 | break; | |
1107 | } | |
1108 | ||
49cd97a3 | 1109 | return dev_priv->cdclk.hw.ref * ratio; |
7ff89ca2 VS |
1110 | } |
1111 | ||
1112 | static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) | |
1113 | { | |
1114 | int ratio; | |
1115 | ||
49cd97a3 | 1116 | if (cdclk == dev_priv->cdclk.hw.ref) |
7ff89ca2 VS |
1117 | return 0; |
1118 | ||
1119 | switch (cdclk) { | |
1120 | default: | |
1121 | MISSING_CASE(cdclk); | |
1122 | case 79200: | |
1123 | case 158400: | |
1124 | case 316800: | |
1125 | ratio = 33; | |
1126 | break; | |
1127 | } | |
1128 | ||
49cd97a3 | 1129 | return dev_priv->cdclk.hw.ref * ratio; |
7ff89ca2 VS |
1130 | } |
1131 | ||
49cd97a3 VS |
1132 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv, |
1133 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
1134 | { |
1135 | u32 val; | |
1136 | ||
49cd97a3 VS |
1137 | cdclk_state->ref = 19200; |
1138 | cdclk_state->vco = 0; | |
7ff89ca2 VS |
1139 | |
1140 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1141 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) | |
1142 | return; | |
1143 | ||
1144 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) | |
1145 | return; | |
1146 | ||
1147 | val = I915_READ(BXT_DE_PLL_CTL); | |
49cd97a3 | 1148 | cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; |
7ff89ca2 VS |
1149 | } |
1150 | ||
49cd97a3 VS |
1151 | static void bxt_get_cdclk(struct drm_i915_private *dev_priv, |
1152 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
1153 | { |
1154 | u32 divider; | |
49cd97a3 | 1155 | int div; |
7ff89ca2 | 1156 | |
49cd97a3 | 1157 | bxt_de_pll_update(dev_priv, cdclk_state); |
7ff89ca2 | 1158 | |
49cd97a3 VS |
1159 | cdclk_state->cdclk = cdclk_state->ref; |
1160 | ||
1161 | if (cdclk_state->vco == 0) | |
1162 | return; | |
7ff89ca2 VS |
1163 | |
1164 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
1165 | ||
1166 | switch (divider) { | |
1167 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
1168 | div = 2; | |
1169 | break; | |
1170 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
1171 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); | |
1172 | div = 3; | |
1173 | break; | |
1174 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
1175 | div = 4; | |
1176 | break; | |
1177 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
1178 | div = 8; | |
1179 | break; | |
1180 | default: | |
1181 | MISSING_CASE(divider); | |
49cd97a3 | 1182 | return; |
7ff89ca2 VS |
1183 | } |
1184 | ||
49cd97a3 | 1185 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); |
7ff89ca2 VS |
1186 | } |
1187 | ||
1188 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) | |
1189 | { | |
1190 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
1191 | ||
1192 | /* Timeout 200us */ | |
1193 | if (intel_wait_for_register(dev_priv, | |
1194 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
1195 | 1)) | |
1196 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); | |
1197 | ||
49cd97a3 | 1198 | dev_priv->cdclk.hw.vco = 0; |
7ff89ca2 VS |
1199 | } |
1200 | ||
1201 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) | |
1202 | { | |
49cd97a3 | 1203 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); |
7ff89ca2 VS |
1204 | u32 val; |
1205 | ||
1206 | val = I915_READ(BXT_DE_PLL_CTL); | |
1207 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
1208 | val |= BXT_DE_PLL_RATIO(ratio); | |
1209 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
1210 | ||
1211 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
1212 | ||
1213 | /* Timeout 200us */ | |
1214 | if (intel_wait_for_register(dev_priv, | |
1215 | BXT_DE_PLL_ENABLE, | |
1216 | BXT_DE_PLL_LOCK, | |
1217 | BXT_DE_PLL_LOCK, | |
1218 | 1)) | |
1219 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
1220 | ||
49cd97a3 | 1221 | dev_priv->cdclk.hw.vco = vco; |
7ff89ca2 VS |
1222 | } |
1223 | ||
8f0cfa4d | 1224 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, |
83c5fda7 | 1225 | const struct intel_cdclk_state *cdclk_state) |
7ff89ca2 | 1226 | { |
83c5fda7 VS |
1227 | int cdclk = cdclk_state->cdclk; |
1228 | int vco = cdclk_state->vco; | |
7ff89ca2 | 1229 | u32 val, divider; |
8f0cfa4d | 1230 | int ret; |
7ff89ca2 | 1231 | |
7ff89ca2 VS |
1232 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ |
1233 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
1234 | case 8: | |
1235 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
1236 | break; | |
1237 | case 4: | |
1238 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
1239 | break; | |
1240 | case 3: | |
1241 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); | |
1242 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
1243 | break; | |
1244 | case 2: | |
1245 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
1246 | break; | |
1247 | default: | |
49cd97a3 | 1248 | WARN_ON(cdclk != dev_priv->cdclk.hw.ref); |
7ff89ca2 VS |
1249 | WARN_ON(vco != 0); |
1250 | ||
1251 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
1252 | break; | |
1253 | } | |
1254 | ||
1255 | /* Inform power controller of upcoming frequency change */ | |
1256 | mutex_lock(&dev_priv->rps.hw_lock); | |
1257 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
1258 | 0x80000000); | |
1259 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1260 | ||
1261 | if (ret) { | |
1262 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
1263 | ret, cdclk); | |
1264 | return; | |
1265 | } | |
1266 | ||
49cd97a3 VS |
1267 | if (dev_priv->cdclk.hw.vco != 0 && |
1268 | dev_priv->cdclk.hw.vco != vco) | |
7ff89ca2 VS |
1269 | bxt_de_pll_disable(dev_priv); |
1270 | ||
49cd97a3 | 1271 | if (dev_priv->cdclk.hw.vco != vco) |
7ff89ca2 VS |
1272 | bxt_de_pll_enable(dev_priv, vco); |
1273 | ||
1274 | val = divider | skl_cdclk_decimal(cdclk); | |
1275 | /* | |
1276 | * FIXME if only the cd2x divider needs changing, it could be done | |
1277 | * without shutting off the pipe (if only one pipe is active). | |
1278 | */ | |
1279 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
1280 | /* | |
1281 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
1282 | * enable otherwise. | |
1283 | */ | |
1284 | if (cdclk >= 500000) | |
1285 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
1286 | I915_WRITE(CDCLK_CTL, val); | |
1287 | ||
1288 | mutex_lock(&dev_priv->rps.hw_lock); | |
1289 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
1290 | DIV_ROUND_UP(cdclk, 25000)); | |
1291 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1292 | ||
1293 | if (ret) { | |
1294 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
1295 | ret, cdclk); | |
1296 | return; | |
1297 | } | |
1298 | ||
1299 | intel_update_cdclk(dev_priv); | |
1300 | } | |
1301 | ||
1302 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
1303 | { | |
1304 | u32 cdctl, expected; | |
1305 | ||
1306 | intel_update_cdclk(dev_priv); | |
1307 | ||
49cd97a3 VS |
1308 | if (dev_priv->cdclk.hw.vco == 0 || |
1309 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref) | |
7ff89ca2 VS |
1310 | goto sanitize; |
1311 | ||
1312 | /* DPLL okay; verify the cdclock | |
1313 | * | |
1314 | * Some BIOS versions leave an incorrect decimal frequency value and | |
1315 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
1316 | * so sanitize this register. | |
1317 | */ | |
1318 | cdctl = I915_READ(CDCLK_CTL); | |
1319 | /* | |
1320 | * Let's ignore the pipe field, since BIOS could have configured the | |
1321 | * dividers both synching to an active pipe, or asynchronously | |
1322 | * (PIPE_NONE). | |
1323 | */ | |
1324 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
1325 | ||
1326 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
49cd97a3 | 1327 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); |
7ff89ca2 VS |
1328 | /* |
1329 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
1330 | * enable otherwise. | |
1331 | */ | |
49cd97a3 | 1332 | if (dev_priv->cdclk.hw.cdclk >= 500000) |
7ff89ca2 VS |
1333 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
1334 | ||
1335 | if (cdctl == expected) | |
1336 | /* All well; nothing to sanitize */ | |
1337 | return; | |
1338 | ||
1339 | sanitize: | |
1340 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
1341 | ||
1342 | /* force cdclk programming */ | |
49cd97a3 | 1343 | dev_priv->cdclk.hw.cdclk = 0; |
7ff89ca2 VS |
1344 | |
1345 | /* force full PLL disable + enable */ | |
49cd97a3 | 1346 | dev_priv->cdclk.hw.vco = -1; |
7ff89ca2 VS |
1347 | } |
1348 | ||
1349 | /** | |
1350 | * bxt_init_cdclk - Initialize CDCLK on BXT | |
1351 | * @dev_priv: i915 device | |
1352 | * | |
1353 | * Initialize CDCLK for BXT and derivatives. This is generally | |
1354 | * done only during the display core initialization sequence, | |
1355 | * after which the DMC will take care of turning CDCLK off/on | |
1356 | * as needed. | |
1357 | */ | |
1358 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) | |
1359 | { | |
83c5fda7 | 1360 | struct intel_cdclk_state cdclk_state; |
7ff89ca2 VS |
1361 | |
1362 | bxt_sanitize_cdclk(dev_priv); | |
1363 | ||
49cd97a3 VS |
1364 | if (dev_priv->cdclk.hw.cdclk != 0 && |
1365 | dev_priv->cdclk.hw.vco != 0) | |
7ff89ca2 VS |
1366 | return; |
1367 | ||
83c5fda7 VS |
1368 | cdclk_state = dev_priv->cdclk.hw; |
1369 | ||
7ff89ca2 VS |
1370 | /* |
1371 | * FIXME: | |
1372 | * - The initial CDCLK needs to be read from VBT. | |
1373 | * Need to make this change after VBT has changes for BXT. | |
1374 | */ | |
8f0cfa4d | 1375 | if (IS_GEMINILAKE(dev_priv)) { |
83c5fda7 VS |
1376 | cdclk_state.cdclk = glk_calc_cdclk(0); |
1377 | cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk); | |
8f0cfa4d | 1378 | } else { |
83c5fda7 VS |
1379 | cdclk_state.cdclk = bxt_calc_cdclk(0); |
1380 | cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk); | |
8f0cfa4d | 1381 | } |
7ff89ca2 | 1382 | |
83c5fda7 | 1383 | bxt_set_cdclk(dev_priv, &cdclk_state); |
7ff89ca2 VS |
1384 | } |
1385 | ||
1386 | /** | |
1387 | * bxt_uninit_cdclk - Uninitialize CDCLK on BXT | |
1388 | * @dev_priv: i915 device | |
1389 | * | |
1390 | * Uninitialize CDCLK for BXT and derivatives. This is done only | |
1391 | * during the display core uninitialization sequence. | |
1392 | */ | |
1393 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) | |
1394 | { | |
83c5fda7 VS |
1395 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; |
1396 | ||
1397 | cdclk_state.cdclk = cdclk_state.ref; | |
1398 | cdclk_state.vco = 0; | |
1399 | ||
1400 | bxt_set_cdclk(dev_priv, &cdclk_state); | |
49cd97a3 VS |
1401 | } |
1402 | ||
945f2672 VS |
1403 | static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv, |
1404 | struct intel_cdclk_state *cdclk_state) | |
1405 | { | |
1406 | u32 val; | |
1407 | ||
1408 | if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz) | |
1409 | cdclk_state->ref = 24000; | |
1410 | else | |
1411 | cdclk_state->ref = 19200; | |
1412 | ||
1413 | cdclk_state->vco = 0; | |
1414 | ||
1415 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1416 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) | |
1417 | return; | |
1418 | ||
1419 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) | |
1420 | return; | |
1421 | ||
1422 | cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref; | |
1423 | } | |
1424 | ||
1425 | static void cnl_get_cdclk(struct drm_i915_private *dev_priv, | |
1426 | struct intel_cdclk_state *cdclk_state) | |
1427 | { | |
1428 | u32 divider; | |
1429 | int div; | |
1430 | ||
1431 | cnl_cdclk_pll_update(dev_priv, cdclk_state); | |
1432 | ||
1433 | cdclk_state->cdclk = cdclk_state->ref; | |
1434 | ||
1435 | if (cdclk_state->vco == 0) | |
1436 | return; | |
1437 | ||
1438 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
1439 | ||
1440 | switch (divider) { | |
1441 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
1442 | div = 2; | |
1443 | break; | |
1444 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
1445 | div = 4; | |
1446 | break; | |
1447 | default: | |
1448 | MISSING_CASE(divider); | |
1449 | return; | |
1450 | } | |
1451 | ||
1452 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); | |
1453 | } | |
1454 | ||
ef4f7a68 VS |
1455 | static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) |
1456 | { | |
1457 | u32 val; | |
1458 | ||
1459 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1460 | val &= ~BXT_DE_PLL_PLL_ENABLE; | |
1461 | I915_WRITE(BXT_DE_PLL_ENABLE, val); | |
1462 | ||
1463 | /* Timeout 200us */ | |
1464 | if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) | |
1465 | DRM_ERROR("timout waiting for CDCLK PLL unlock\n"); | |
1466 | ||
1467 | dev_priv->cdclk.hw.vco = 0; | |
1468 | } | |
1469 | ||
1470 | static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) | |
1471 | { | |
1472 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); | |
1473 | u32 val; | |
1474 | ||
1475 | val = CNL_CDCLK_PLL_RATIO(ratio); | |
1476 | I915_WRITE(BXT_DE_PLL_ENABLE, val); | |
1477 | ||
1478 | val |= BXT_DE_PLL_PLL_ENABLE; | |
1479 | I915_WRITE(BXT_DE_PLL_ENABLE, val); | |
1480 | ||
1481 | /* Timeout 200us */ | |
1482 | if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) | |
1483 | DRM_ERROR("timout waiting for CDCLK PLL lock\n"); | |
1484 | ||
1485 | dev_priv->cdclk.hw.vco = vco; | |
1486 | } | |
1487 | ||
ef4f7a68 VS |
1488 | static void cnl_set_cdclk(struct drm_i915_private *dev_priv, |
1489 | const struct intel_cdclk_state *cdclk_state) | |
1490 | { | |
1491 | int cdclk = cdclk_state->cdclk; | |
1492 | int vco = cdclk_state->vco; | |
1493 | u32 val, divider, pcu_ack; | |
1494 | int ret; | |
1495 | ||
1496 | mutex_lock(&dev_priv->rps.hw_lock); | |
1497 | ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, | |
1498 | SKL_CDCLK_PREPARE_FOR_CHANGE, | |
1499 | SKL_CDCLK_READY_FOR_CHANGE, | |
1500 | SKL_CDCLK_READY_FOR_CHANGE, 3); | |
1501 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1502 | if (ret) { | |
1503 | DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", | |
1504 | ret); | |
1505 | return; | |
1506 | } | |
1507 | ||
1508 | /* cdclk = vco / 2 / div{1,2} */ | |
1509 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
1510 | case 4: | |
1511 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
1512 | break; | |
1513 | case 2: | |
1514 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
1515 | break; | |
1516 | default: | |
1517 | WARN_ON(cdclk != dev_priv->cdclk.hw.ref); | |
1518 | WARN_ON(vco != 0); | |
1519 | ||
1520 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
1521 | break; | |
1522 | } | |
1523 | ||
1524 | switch (cdclk) { | |
1525 | case 528000: | |
1526 | pcu_ack = 2; | |
1527 | break; | |
1528 | case 336000: | |
1529 | pcu_ack = 1; | |
1530 | break; | |
1531 | case 168000: | |
1532 | default: | |
1533 | pcu_ack = 0; | |
1534 | break; | |
1535 | } | |
1536 | ||
1537 | if (dev_priv->cdclk.hw.vco != 0 && | |
1538 | dev_priv->cdclk.hw.vco != vco) | |
1539 | cnl_cdclk_pll_disable(dev_priv); | |
1540 | ||
1541 | if (dev_priv->cdclk.hw.vco != vco) | |
1542 | cnl_cdclk_pll_enable(dev_priv, vco); | |
1543 | ||
1544 | val = divider | skl_cdclk_decimal(cdclk); | |
1545 | /* | |
1546 | * FIXME if only the cd2x divider needs changing, it could be done | |
1547 | * without shutting off the pipe (if only one pipe is active). | |
1548 | */ | |
1549 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
1550 | I915_WRITE(CDCLK_CTL, val); | |
1551 | ||
1552 | /* inform PCU of the change */ | |
1553 | mutex_lock(&dev_priv->rps.hw_lock); | |
1554 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
1555 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1556 | ||
1557 | intel_update_cdclk(dev_priv); | |
1558 | } | |
1559 | ||
d8d4a512 VS |
1560 | static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
1561 | { | |
1562 | int ratio; | |
1563 | ||
1564 | if (cdclk == dev_priv->cdclk.hw.ref) | |
1565 | return 0; | |
1566 | ||
1567 | switch (cdclk) { | |
1568 | default: | |
1569 | MISSING_CASE(cdclk); | |
1570 | case 168000: | |
1571 | case 336000: | |
1572 | ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28; | |
1573 | break; | |
1574 | case 528000: | |
1575 | ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44; | |
1576 | break; | |
1577 | } | |
1578 | ||
1579 | return dev_priv->cdclk.hw.ref * ratio; | |
1580 | } | |
1581 | ||
1582 | static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
1583 | { | |
1584 | u32 cdctl, expected; | |
1585 | ||
1586 | intel_update_cdclk(dev_priv); | |
1587 | ||
1588 | if (dev_priv->cdclk.hw.vco == 0 || | |
1589 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref) | |
1590 | goto sanitize; | |
1591 | ||
1592 | /* DPLL okay; verify the cdclock | |
1593 | * | |
1594 | * Some BIOS versions leave an incorrect decimal frequency value and | |
1595 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
1596 | * so sanitize this register. | |
1597 | */ | |
1598 | cdctl = I915_READ(CDCLK_CTL); | |
1599 | /* | |
1600 | * Let's ignore the pipe field, since BIOS could have configured the | |
1601 | * dividers both synching to an active pipe, or asynchronously | |
1602 | * (PIPE_NONE). | |
1603 | */ | |
1604 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
1605 | ||
1606 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
1607 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); | |
1608 | ||
1609 | if (cdctl == expected) | |
1610 | /* All well; nothing to sanitize */ | |
1611 | return; | |
1612 | ||
1613 | sanitize: | |
1614 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
1615 | ||
1616 | /* force cdclk programming */ | |
1617 | dev_priv->cdclk.hw.cdclk = 0; | |
1618 | ||
1619 | /* force full PLL disable + enable */ | |
1620 | dev_priv->cdclk.hw.vco = -1; | |
1621 | } | |
1622 | ||
1623 | /** | |
1624 | * cnl_init_cdclk - Initialize CDCLK on CNL | |
1625 | * @dev_priv: i915 device | |
1626 | * | |
1627 | * Initialize CDCLK for CNL. This is generally | |
1628 | * done only during the display core initialization sequence, | |
1629 | * after which the DMC will take care of turning CDCLK off/on | |
1630 | * as needed. | |
1631 | */ | |
1632 | void cnl_init_cdclk(struct drm_i915_private *dev_priv) | |
1633 | { | |
1634 | struct intel_cdclk_state cdclk_state; | |
1635 | ||
1636 | cnl_sanitize_cdclk(dev_priv); | |
1637 | ||
1638 | if (dev_priv->cdclk.hw.cdclk != 0 && | |
1639 | dev_priv->cdclk.hw.vco != 0) | |
1640 | return; | |
1641 | ||
1642 | cdclk_state = dev_priv->cdclk.hw; | |
1643 | ||
1644 | cdclk_state.cdclk = 168000; | |
1645 | cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); | |
1646 | ||
1647 | cnl_set_cdclk(dev_priv, &cdclk_state); | |
1648 | } | |
1649 | ||
1650 | /** | |
1651 | * cnl_uninit_cdclk - Uninitialize CDCLK on CNL | |
1652 | * @dev_priv: i915 device | |
1653 | * | |
1654 | * Uninitialize CDCLK for CNL. This is done only | |
1655 | * during the display core uninitialization sequence. | |
1656 | */ | |
1657 | void cnl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
1658 | { | |
1659 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; | |
1660 | ||
1661 | cdclk_state.cdclk = cdclk_state.ref; | |
1662 | cdclk_state.vco = 0; | |
1663 | ||
1664 | cnl_set_cdclk(dev_priv, &cdclk_state); | |
1665 | } | |
1666 | ||
49cd97a3 VS |
1667 | /** |
1668 | * intel_cdclk_state_compare - Determine if two CDCLK states differ | |
1669 | * @a: first CDCLK state | |
1670 | * @b: second CDCLK state | |
1671 | * | |
1672 | * Returns: | |
1673 | * True if the CDCLK states are identical, false if they differ. | |
1674 | */ | |
1675 | bool intel_cdclk_state_compare(const struct intel_cdclk_state *a, | |
1676 | const struct intel_cdclk_state *b) | |
1677 | { | |
1678 | return memcmp(a, b, sizeof(*a)) == 0; | |
7ff89ca2 VS |
1679 | } |
1680 | ||
b0587e4d VS |
1681 | /** |
1682 | * intel_set_cdclk - Push the CDCLK state to the hardware | |
1683 | * @dev_priv: i915 device | |
1684 | * @cdclk_state: new CDCLK state | |
1685 | * | |
1686 | * Program the hardware based on the passed in CDCLK state, | |
1687 | * if necessary. | |
1688 | */ | |
1689 | void intel_set_cdclk(struct drm_i915_private *dev_priv, | |
1690 | const struct intel_cdclk_state *cdclk_state) | |
1691 | { | |
1692 | if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state)) | |
1693 | return; | |
1694 | ||
1695 | if (WARN_ON_ONCE(!dev_priv->display.set_cdclk)) | |
1696 | return; | |
1697 | ||
1698 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n", | |
1699 | cdclk_state->cdclk, cdclk_state->vco, | |
1700 | cdclk_state->ref); | |
1701 | ||
1702 | dev_priv->display.set_cdclk(dev_priv, cdclk_state); | |
1703 | } | |
1704 | ||
7ff89ca2 VS |
1705 | static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, |
1706 | int pixel_rate) | |
1707 | { | |
1708 | struct drm_i915_private *dev_priv = | |
1709 | to_i915(crtc_state->base.crtc->dev); | |
1710 | ||
1711 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
1712 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
1713 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); | |
1714 | ||
78cfa580 PD |
1715 | /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, |
1716 | * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else | |
1717 | * there may be audio corruption or screen corruption." This cdclk | |
1718 | * restriction for GLK is 316.8 MHz and since GLK can output two | |
1719 | * pixels per clock, the pixel rate becomes 2 * 316.8 MHz. | |
7ff89ca2 VS |
1720 | */ |
1721 | if (intel_crtc_has_dp_encoder(crtc_state) && | |
1722 | crtc_state->has_audio && | |
1723 | crtc_state->port_clock >= 540000 && | |
78cfa580 PD |
1724 | crtc_state->lane_count == 4) { |
1725 | if (IS_GEMINILAKE(dev_priv)) | |
1726 | pixel_rate = max(2 * 316800, pixel_rate); | |
1727 | else | |
1728 | pixel_rate = max(432000, pixel_rate); | |
1729 | } | |
7ff89ca2 | 1730 | |
8cbeb06d PD |
1731 | /* According to BSpec, "The CD clock frequency must be at least twice |
1732 | * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. | |
1733 | * The check for GLK has to be adjusted as the platform can output | |
1734 | * two pixels per clock. | |
1735 | */ | |
1736 | if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) { | |
1737 | if (IS_GEMINILAKE(dev_priv)) | |
1738 | pixel_rate = max(2 * 2 * 96000, pixel_rate); | |
1739 | else | |
1740 | pixel_rate = max(2 * 96000, pixel_rate); | |
1741 | } | |
1742 | ||
7ff89ca2 VS |
1743 | return pixel_rate; |
1744 | } | |
1745 | ||
1746 | /* compute the max rate for new configuration */ | |
1747 | static int intel_max_pixel_rate(struct drm_atomic_state *state) | |
1748 | { | |
1749 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
1750 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
1751 | struct drm_crtc *crtc; | |
1752 | struct drm_crtc_state *cstate; | |
1753 | struct intel_crtc_state *crtc_state; | |
1754 | unsigned int max_pixel_rate = 0, i; | |
1755 | enum pipe pipe; | |
1756 | ||
1757 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, | |
1758 | sizeof(intel_state->min_pixclk)); | |
1759 | ||
e6963ccf | 1760 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
7ff89ca2 VS |
1761 | int pixel_rate; |
1762 | ||
1763 | crtc_state = to_intel_crtc_state(cstate); | |
1764 | if (!crtc_state->base.enable) { | |
1765 | intel_state->min_pixclk[i] = 0; | |
1766 | continue; | |
1767 | } | |
1768 | ||
1769 | pixel_rate = crtc_state->pixel_rate; | |
1770 | ||
1771 | if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv)) | |
1772 | pixel_rate = | |
1773 | bdw_adjust_min_pipe_pixel_rate(crtc_state, | |
1774 | pixel_rate); | |
1775 | ||
1776 | intel_state->min_pixclk[i] = pixel_rate; | |
1777 | } | |
1778 | ||
1779 | for_each_pipe(dev_priv, pipe) | |
1780 | max_pixel_rate = max(intel_state->min_pixclk[pipe], | |
1781 | max_pixel_rate); | |
1782 | ||
1783 | return max_pixel_rate; | |
1784 | } | |
1785 | ||
1786 | static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state) | |
1787 | { | |
3d5dbb10 | 1788 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
7ff89ca2 VS |
1789 | int max_pixclk = intel_max_pixel_rate(state); |
1790 | struct intel_atomic_state *intel_state = | |
1791 | to_intel_atomic_state(state); | |
bb0f4aab VS |
1792 | int cdclk; |
1793 | ||
1794 | cdclk = vlv_calc_cdclk(dev_priv, max_pixclk); | |
7ff89ca2 | 1795 | |
bb0f4aab VS |
1796 | if (cdclk > dev_priv->max_cdclk_freq) { |
1797 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
1798 | cdclk, dev_priv->max_cdclk_freq); | |
1799 | return -EINVAL; | |
1800 | } | |
7ff89ca2 | 1801 | |
bb0f4aab VS |
1802 | intel_state->cdclk.logical.cdclk = cdclk; |
1803 | ||
1804 | if (!intel_state->active_crtcs) { | |
1805 | cdclk = vlv_calc_cdclk(dev_priv, 0); | |
1806 | ||
1807 | intel_state->cdclk.actual.cdclk = cdclk; | |
1808 | } else { | |
1809 | intel_state->cdclk.actual = | |
1810 | intel_state->cdclk.logical; | |
1811 | } | |
7ff89ca2 VS |
1812 | |
1813 | return 0; | |
1814 | } | |
1815 | ||
7ff89ca2 VS |
1816 | static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state) |
1817 | { | |
1818 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
1819 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
1820 | int max_pixclk = intel_max_pixel_rate(state); | |
1821 | int cdclk; | |
1822 | ||
1823 | /* | |
1824 | * FIXME should also account for plane ratio | |
1825 | * once 64bpp pixel formats are supported. | |
1826 | */ | |
1827 | cdclk = bdw_calc_cdclk(max_pixclk); | |
1828 | ||
1829 | if (cdclk > dev_priv->max_cdclk_freq) { | |
1830 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
1831 | cdclk, dev_priv->max_cdclk_freq); | |
1832 | return -EINVAL; | |
1833 | } | |
1834 | ||
bb0f4aab VS |
1835 | intel_state->cdclk.logical.cdclk = cdclk; |
1836 | ||
1837 | if (!intel_state->active_crtcs) { | |
1838 | cdclk = bdw_calc_cdclk(0); | |
1839 | ||
1840 | intel_state->cdclk.actual.cdclk = cdclk; | |
1841 | } else { | |
1842 | intel_state->cdclk.actual = | |
1843 | intel_state->cdclk.logical; | |
1844 | } | |
7ff89ca2 VS |
1845 | |
1846 | return 0; | |
1847 | } | |
1848 | ||
7ff89ca2 VS |
1849 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
1850 | { | |
1851 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
1852 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
1853 | const int max_pixclk = intel_max_pixel_rate(state); | |
bb0f4aab VS |
1854 | int cdclk, vco; |
1855 | ||
1856 | vco = intel_state->cdclk.logical.vco; | |
1857 | if (!vco) | |
1858 | vco = dev_priv->skl_preferred_vco_freq; | |
7ff89ca2 VS |
1859 | |
1860 | /* | |
1861 | * FIXME should also account for plane ratio | |
1862 | * once 64bpp pixel formats are supported. | |
1863 | */ | |
1864 | cdclk = skl_calc_cdclk(max_pixclk, vco); | |
1865 | ||
7ff89ca2 | 1866 | if (cdclk > dev_priv->max_cdclk_freq) { |
bb0f4aab VS |
1867 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
1868 | cdclk, dev_priv->max_cdclk_freq); | |
1869 | return -EINVAL; | |
7ff89ca2 VS |
1870 | } |
1871 | ||
bb0f4aab VS |
1872 | intel_state->cdclk.logical.vco = vco; |
1873 | intel_state->cdclk.logical.cdclk = cdclk; | |
1874 | ||
1875 | if (!intel_state->active_crtcs) { | |
1876 | cdclk = skl_calc_cdclk(0, vco); | |
1877 | ||
1878 | intel_state->cdclk.actual.vco = vco; | |
1879 | intel_state->cdclk.actual.cdclk = cdclk; | |
1880 | } else { | |
1881 | intel_state->cdclk.actual = | |
1882 | intel_state->cdclk.logical; | |
1883 | } | |
7ff89ca2 VS |
1884 | |
1885 | return 0; | |
1886 | } | |
1887 | ||
7ff89ca2 VS |
1888 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
1889 | { | |
1890 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
1891 | int max_pixclk = intel_max_pixel_rate(state); | |
1892 | struct intel_atomic_state *intel_state = | |
1893 | to_intel_atomic_state(state); | |
bb0f4aab | 1894 | int cdclk, vco; |
7ff89ca2 | 1895 | |
bb0f4aab | 1896 | if (IS_GEMINILAKE(dev_priv)) { |
7ff89ca2 | 1897 | cdclk = glk_calc_cdclk(max_pixclk); |
bb0f4aab VS |
1898 | vco = glk_de_pll_vco(dev_priv, cdclk); |
1899 | } else { | |
7ff89ca2 | 1900 | cdclk = bxt_calc_cdclk(max_pixclk); |
bb0f4aab VS |
1901 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
1902 | } | |
1903 | ||
1904 | if (cdclk > dev_priv->max_cdclk_freq) { | |
1905 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
1906 | cdclk, dev_priv->max_cdclk_freq); | |
1907 | return -EINVAL; | |
1908 | } | |
7ff89ca2 | 1909 | |
bb0f4aab VS |
1910 | intel_state->cdclk.logical.vco = vco; |
1911 | intel_state->cdclk.logical.cdclk = cdclk; | |
7ff89ca2 VS |
1912 | |
1913 | if (!intel_state->active_crtcs) { | |
bb0f4aab | 1914 | if (IS_GEMINILAKE(dev_priv)) { |
7ff89ca2 | 1915 | cdclk = glk_calc_cdclk(0); |
bb0f4aab VS |
1916 | vco = glk_de_pll_vco(dev_priv, cdclk); |
1917 | } else { | |
7ff89ca2 | 1918 | cdclk = bxt_calc_cdclk(0); |
bb0f4aab VS |
1919 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
1920 | } | |
7ff89ca2 | 1921 | |
bb0f4aab VS |
1922 | intel_state->cdclk.actual.vco = vco; |
1923 | intel_state->cdclk.actual.cdclk = cdclk; | |
1924 | } else { | |
1925 | intel_state->cdclk.actual = | |
1926 | intel_state->cdclk.logical; | |
7ff89ca2 VS |
1927 | } |
1928 | ||
1929 | return 0; | |
1930 | } | |
1931 | ||
7ff89ca2 VS |
1932 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
1933 | { | |
1934 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
1935 | ||
1936 | if (IS_GEMINILAKE(dev_priv)) | |
97f55ca5 MC |
1937 | /* |
1938 | * FIXME: Limiting to 99% as a temporary workaround. See | |
1939 | * glk_calc_cdclk() for details. | |
1940 | */ | |
1941 | return 2 * max_cdclk_freq * 99 / 100; | |
7ff89ca2 VS |
1942 | else if (INTEL_INFO(dev_priv)->gen >= 9 || |
1943 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
1944 | return max_cdclk_freq; | |
1945 | else if (IS_CHERRYVIEW(dev_priv)) | |
1946 | return max_cdclk_freq*95/100; | |
1947 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
1948 | return 2*max_cdclk_freq*90/100; | |
1949 | else | |
1950 | return max_cdclk_freq*90/100; | |
1951 | } | |
1952 | ||
1953 | /** | |
1954 | * intel_update_max_cdclk - Determine the maximum support CDCLK frequency | |
1955 | * @dev_priv: i915 device | |
1956 | * | |
1957 | * Determine the maximum CDCLK frequency the platform supports, and also | |
1958 | * derive the maximum dot clock frequency the maximum CDCLK frequency | |
1959 | * allows. | |
1960 | */ | |
1961 | void intel_update_max_cdclk(struct drm_i915_private *dev_priv) | |
1962 | { | |
1963 | if (IS_GEN9_BC(dev_priv)) { | |
1964 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; | |
1965 | int max_cdclk, vco; | |
1966 | ||
1967 | vco = dev_priv->skl_preferred_vco_freq; | |
1968 | WARN_ON(vco != 8100000 && vco != 8640000); | |
1969 | ||
1970 | /* | |
1971 | * Use the lower (vco 8640) cdclk values as a | |
1972 | * first guess. skl_calc_cdclk() will correct it | |
1973 | * if the preferred vco is 8100 instead. | |
1974 | */ | |
1975 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
1976 | max_cdclk = 617143; | |
1977 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
1978 | max_cdclk = 540000; | |
1979 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
1980 | max_cdclk = 432000; | |
1981 | else | |
1982 | max_cdclk = 308571; | |
1983 | ||
1984 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
1985 | } else if (IS_GEMINILAKE(dev_priv)) { | |
1986 | dev_priv->max_cdclk_freq = 316800; | |
1987 | } else if (IS_BROXTON(dev_priv)) { | |
1988 | dev_priv->max_cdclk_freq = 624000; | |
1989 | } else if (IS_BROADWELL(dev_priv)) { | |
1990 | /* | |
1991 | * FIXME with extra cooling we can allow | |
1992 | * 540 MHz for ULX and 675 Mhz for ULT. | |
1993 | * How can we know if extra cooling is | |
1994 | * available? PCI ID, VTB, something else? | |
1995 | */ | |
1996 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
1997 | dev_priv->max_cdclk_freq = 450000; | |
1998 | else if (IS_BDW_ULX(dev_priv)) | |
1999 | dev_priv->max_cdclk_freq = 450000; | |
2000 | else if (IS_BDW_ULT(dev_priv)) | |
2001 | dev_priv->max_cdclk_freq = 540000; | |
2002 | else | |
2003 | dev_priv->max_cdclk_freq = 675000; | |
2004 | } else if (IS_CHERRYVIEW(dev_priv)) { | |
2005 | dev_priv->max_cdclk_freq = 320000; | |
2006 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
2007 | dev_priv->max_cdclk_freq = 400000; | |
2008 | } else { | |
2009 | /* otherwise assume cdclk is fixed */ | |
49cd97a3 | 2010 | dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; |
7ff89ca2 VS |
2011 | } |
2012 | ||
2013 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); | |
2014 | ||
2015 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", | |
2016 | dev_priv->max_cdclk_freq); | |
2017 | ||
2018 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
2019 | dev_priv->max_dotclk_freq); | |
2020 | } | |
2021 | ||
2022 | /** | |
2023 | * intel_update_cdclk - Determine the current CDCLK frequency | |
2024 | * @dev_priv: i915 device | |
2025 | * | |
2026 | * Determine the current CDCLK frequency. | |
2027 | */ | |
2028 | void intel_update_cdclk(struct drm_i915_private *dev_priv) | |
2029 | { | |
49cd97a3 | 2030 | dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); |
7ff89ca2 | 2031 | |
49cd97a3 VS |
2032 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
2033 | dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco, | |
2034 | dev_priv->cdclk.hw.ref); | |
7ff89ca2 VS |
2035 | |
2036 | /* | |
2037 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): | |
2038 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
2039 | * of cdclk that generates 4MHz reference clock freq which is used to | |
2040 | * generate GMBus clock. This will vary with the cdclk freq. | |
2041 | */ | |
2042 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2043 | I915_WRITE(GMBUSFREQ_VLV, | |
49cd97a3 | 2044 | DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); |
7ff89ca2 VS |
2045 | } |
2046 | ||
9d81a997 RV |
2047 | static int cnp_rawclk(struct drm_i915_private *dev_priv) |
2048 | { | |
2049 | u32 rawclk; | |
2050 | int divider, fraction; | |
2051 | ||
2052 | if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { | |
2053 | /* 24 MHz */ | |
2054 | divider = 24000; | |
2055 | fraction = 0; | |
2056 | } else { | |
2057 | /* 19.2 MHz */ | |
2058 | divider = 19000; | |
2059 | fraction = 200; | |
2060 | } | |
2061 | ||
2062 | rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1); | |
2063 | if (fraction) | |
2064 | rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000, | |
2065 | fraction) - 1); | |
2066 | ||
2067 | I915_WRITE(PCH_RAWCLK_FREQ, rawclk); | |
2068 | return divider + fraction; | |
2069 | } | |
2070 | ||
7ff89ca2 VS |
2071 | static int pch_rawclk(struct drm_i915_private *dev_priv) |
2072 | { | |
2073 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; | |
2074 | } | |
2075 | ||
2076 | static int vlv_hrawclk(struct drm_i915_private *dev_priv) | |
2077 | { | |
2078 | /* RAWCLK_FREQ_VLV register updated from power well code */ | |
2079 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", | |
2080 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
2081 | } | |
2082 | ||
2083 | static int g4x_hrawclk(struct drm_i915_private *dev_priv) | |
2084 | { | |
2085 | uint32_t clkcfg; | |
2086 | ||
2087 | /* hrawclock is 1/4 the FSB frequency */ | |
2088 | clkcfg = I915_READ(CLKCFG); | |
2089 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
2090 | case CLKCFG_FSB_400: | |
2091 | return 100000; | |
2092 | case CLKCFG_FSB_533: | |
2093 | return 133333; | |
2094 | case CLKCFG_FSB_667: | |
2095 | return 166667; | |
2096 | case CLKCFG_FSB_800: | |
2097 | return 200000; | |
2098 | case CLKCFG_FSB_1067: | |
6f38123e | 2099 | case CLKCFG_FSB_1067_ALT: |
7ff89ca2 VS |
2100 | return 266667; |
2101 | case CLKCFG_FSB_1333: | |
6f38123e | 2102 | case CLKCFG_FSB_1333_ALT: |
7ff89ca2 | 2103 | return 333333; |
7ff89ca2 VS |
2104 | default: |
2105 | return 133333; | |
2106 | } | |
2107 | } | |
2108 | ||
2109 | /** | |
2110 | * intel_update_rawclk - Determine the current RAWCLK frequency | |
2111 | * @dev_priv: i915 device | |
2112 | * | |
2113 | * Determine the current RAWCLK frequency. RAWCLK is a fixed | |
2114 | * frequency clock so this needs to done only once. | |
2115 | */ | |
2116 | void intel_update_rawclk(struct drm_i915_private *dev_priv) | |
2117 | { | |
9d81a997 RV |
2118 | |
2119 | if (HAS_PCH_CNP(dev_priv)) | |
2120 | dev_priv->rawclk_freq = cnp_rawclk(dev_priv); | |
2121 | else if (HAS_PCH_SPLIT(dev_priv)) | |
7ff89ca2 VS |
2122 | dev_priv->rawclk_freq = pch_rawclk(dev_priv); |
2123 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2124 | dev_priv->rawclk_freq = vlv_hrawclk(dev_priv); | |
2125 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
2126 | dev_priv->rawclk_freq = g4x_hrawclk(dev_priv); | |
2127 | else | |
2128 | /* no rawclk on other platforms, or no need to know it */ | |
2129 | return; | |
2130 | ||
2131 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
2132 | } | |
2133 | ||
2134 | /** | |
2135 | * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks | |
2136 | * @dev_priv: i915 device | |
2137 | */ | |
2138 | void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) | |
2139 | { | |
b0587e4d VS |
2140 | if (IS_CHERRYVIEW(dev_priv)) { |
2141 | dev_priv->display.set_cdclk = chv_set_cdclk; | |
2142 | dev_priv->display.modeset_calc_cdclk = | |
2143 | vlv_modeset_calc_cdclk; | |
2144 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
2145 | dev_priv->display.set_cdclk = vlv_set_cdclk; | |
7ff89ca2 VS |
2146 | dev_priv->display.modeset_calc_cdclk = |
2147 | vlv_modeset_calc_cdclk; | |
2148 | } else if (IS_BROADWELL(dev_priv)) { | |
b0587e4d | 2149 | dev_priv->display.set_cdclk = bdw_set_cdclk; |
7ff89ca2 VS |
2150 | dev_priv->display.modeset_calc_cdclk = |
2151 | bdw_modeset_calc_cdclk; | |
2152 | } else if (IS_GEN9_LP(dev_priv)) { | |
b0587e4d | 2153 | dev_priv->display.set_cdclk = bxt_set_cdclk; |
7ff89ca2 VS |
2154 | dev_priv->display.modeset_calc_cdclk = |
2155 | bxt_modeset_calc_cdclk; | |
2156 | } else if (IS_GEN9_BC(dev_priv)) { | |
b0587e4d | 2157 | dev_priv->display.set_cdclk = skl_set_cdclk; |
7ff89ca2 VS |
2158 | dev_priv->display.modeset_calc_cdclk = |
2159 | skl_modeset_calc_cdclk; | |
2160 | } | |
2161 | ||
945f2672 VS |
2162 | if (IS_CANNONLAKE(dev_priv)) |
2163 | dev_priv->display.get_cdclk = cnl_get_cdclk; | |
2164 | else if (IS_GEN9_BC(dev_priv)) | |
7ff89ca2 VS |
2165 | dev_priv->display.get_cdclk = skl_get_cdclk; |
2166 | else if (IS_GEN9_LP(dev_priv)) | |
2167 | dev_priv->display.get_cdclk = bxt_get_cdclk; | |
2168 | else if (IS_BROADWELL(dev_priv)) | |
2169 | dev_priv->display.get_cdclk = bdw_get_cdclk; | |
2170 | else if (IS_HASWELL(dev_priv)) | |
2171 | dev_priv->display.get_cdclk = hsw_get_cdclk; | |
2172 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2173 | dev_priv->display.get_cdclk = vlv_get_cdclk; | |
2174 | else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
2175 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
2176 | else if (IS_GEN5(dev_priv)) | |
2177 | dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; | |
2178 | else if (IS_GM45(dev_priv)) | |
2179 | dev_priv->display.get_cdclk = gm45_get_cdclk; | |
6b9e441d | 2180 | else if (IS_G45(dev_priv)) |
7ff89ca2 VS |
2181 | dev_priv->display.get_cdclk = g33_get_cdclk; |
2182 | else if (IS_I965GM(dev_priv)) | |
2183 | dev_priv->display.get_cdclk = i965gm_get_cdclk; | |
2184 | else if (IS_I965G(dev_priv)) | |
2185 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
2186 | else if (IS_PINEVIEW(dev_priv)) | |
2187 | dev_priv->display.get_cdclk = pnv_get_cdclk; | |
2188 | else if (IS_G33(dev_priv)) | |
2189 | dev_priv->display.get_cdclk = g33_get_cdclk; | |
2190 | else if (IS_I945GM(dev_priv)) | |
2191 | dev_priv->display.get_cdclk = i945gm_get_cdclk; | |
2192 | else if (IS_I945G(dev_priv)) | |
2193 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
2194 | else if (IS_I915GM(dev_priv)) | |
2195 | dev_priv->display.get_cdclk = i915gm_get_cdclk; | |
2196 | else if (IS_I915G(dev_priv)) | |
2197 | dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; | |
2198 | else if (IS_I865G(dev_priv)) | |
2199 | dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; | |
2200 | else if (IS_I85X(dev_priv)) | |
2201 | dev_priv->display.get_cdclk = i85x_get_cdclk; | |
2202 | else if (IS_I845G(dev_priv)) | |
2203 | dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; | |
2204 | else { /* 830 */ | |
2205 | WARN(!IS_I830(dev_priv), | |
2206 | "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
2207 | dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; | |
2208 | } | |
2209 | } |