Commit | Line | Data |
---|---|---|
7ff89ca2 VS |
1 | /* |
2 | * Copyright © 2006-2017 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "intel_drv.h" | |
25 | ||
26 | /** | |
27 | * DOC: CDCLK / RAWCLK | |
28 | * | |
29 | * The display engine uses several different clocks to do its work. There | |
30 | * are two main clocks involved that aren't directly related to the actual | |
31 | * pixel clock or any symbol/bit clock of the actual output port. These | |
32 | * are the core display clock (CDCLK) and RAWCLK. | |
33 | * | |
34 | * CDCLK clocks most of the display pipe logic, and thus its frequency | |
35 | * must be high enough to support the rate at which pixels are flowing | |
36 | * through the pipes. Downscaling must also be accounted as that increases | |
37 | * the effective pixel rate. | |
38 | * | |
39 | * On several platforms the CDCLK frequency can be changed dynamically | |
40 | * to minimize power consumption for a given display configuration. | |
41 | * Typically changes to the CDCLK frequency require all the display pipes | |
42 | * to be shut down while the frequency is being changed. | |
43 | * | |
44 | * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. | |
45 | * DMC will not change the active CDCLK frequency however, so that part | |
46 | * will still be performed by the driver directly. | |
47 | * | |
48 | * RAWCLK is a fixed frequency clock, often used by various auxiliary | |
49 | * blocks such as AUX CH or backlight PWM. Hence the only thing we | |
50 | * really need to know about RAWCLK is its frequency so that various | |
51 | * dividers can be programmed correctly. | |
52 | */ | |
53 | ||
49cd97a3 VS |
54 | static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, |
55 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 56 | { |
49cd97a3 | 57 | cdclk_state->cdclk = 133333; |
7ff89ca2 VS |
58 | } |
59 | ||
49cd97a3 VS |
60 | static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, |
61 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 62 | { |
49cd97a3 | 63 | cdclk_state->cdclk = 200000; |
7ff89ca2 VS |
64 | } |
65 | ||
49cd97a3 VS |
66 | static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, |
67 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 68 | { |
49cd97a3 | 69 | cdclk_state->cdclk = 266667; |
7ff89ca2 VS |
70 | } |
71 | ||
49cd97a3 VS |
72 | static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, |
73 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 74 | { |
49cd97a3 | 75 | cdclk_state->cdclk = 333333; |
7ff89ca2 VS |
76 | } |
77 | ||
49cd97a3 VS |
78 | static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, |
79 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 80 | { |
49cd97a3 | 81 | cdclk_state->cdclk = 400000; |
7ff89ca2 VS |
82 | } |
83 | ||
49cd97a3 VS |
84 | static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, |
85 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 86 | { |
49cd97a3 | 87 | cdclk_state->cdclk = 450000; |
7ff89ca2 VS |
88 | } |
89 | ||
49cd97a3 VS |
90 | static void i85x_get_cdclk(struct drm_i915_private *dev_priv, |
91 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
92 | { |
93 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
94 | u16 hpllcc = 0; | |
95 | ||
96 | /* | |
97 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
98 | * encoding is different :( | |
99 | * FIXME is this the right way to detect 852GM/852GMV? | |
100 | */ | |
49cd97a3 VS |
101 | if (pdev->revision == 0x1) { |
102 | cdclk_state->cdclk = 133333; | |
103 | return; | |
104 | } | |
7ff89ca2 VS |
105 | |
106 | pci_bus_read_config_word(pdev->bus, | |
107 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
108 | ||
109 | /* Assume that the hardware is in the high speed state. This | |
110 | * should be the default. | |
111 | */ | |
112 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
113 | case GC_CLOCK_133_200: | |
114 | case GC_CLOCK_133_200_2: | |
115 | case GC_CLOCK_100_200: | |
49cd97a3 VS |
116 | cdclk_state->cdclk = 200000; |
117 | break; | |
7ff89ca2 | 118 | case GC_CLOCK_166_250: |
49cd97a3 VS |
119 | cdclk_state->cdclk = 250000; |
120 | break; | |
7ff89ca2 | 121 | case GC_CLOCK_100_133: |
49cd97a3 VS |
122 | cdclk_state->cdclk = 133333; |
123 | break; | |
7ff89ca2 VS |
124 | case GC_CLOCK_133_266: |
125 | case GC_CLOCK_133_266_2: | |
126 | case GC_CLOCK_166_266: | |
49cd97a3 VS |
127 | cdclk_state->cdclk = 266667; |
128 | break; | |
7ff89ca2 | 129 | } |
7ff89ca2 VS |
130 | } |
131 | ||
49cd97a3 VS |
132 | static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, |
133 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
134 | { |
135 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
136 | u16 gcfgc = 0; | |
137 | ||
138 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
139 | ||
49cd97a3 VS |
140 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { |
141 | cdclk_state->cdclk = 133333; | |
142 | return; | |
143 | } | |
7ff89ca2 VS |
144 | |
145 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
146 | case GC_DISPLAY_CLOCK_333_320_MHZ: | |
49cd97a3 VS |
147 | cdclk_state->cdclk = 333333; |
148 | break; | |
7ff89ca2 VS |
149 | default: |
150 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
49cd97a3 VS |
151 | cdclk_state->cdclk = 190000; |
152 | break; | |
7ff89ca2 VS |
153 | } |
154 | } | |
155 | ||
49cd97a3 VS |
156 | static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, |
157 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
158 | { |
159 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
160 | u16 gcfgc = 0; | |
161 | ||
162 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
163 | ||
49cd97a3 VS |
164 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { |
165 | cdclk_state->cdclk = 133333; | |
166 | return; | |
167 | } | |
7ff89ca2 VS |
168 | |
169 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
170 | case GC_DISPLAY_CLOCK_333_320_MHZ: | |
49cd97a3 VS |
171 | cdclk_state->cdclk = 320000; |
172 | break; | |
7ff89ca2 VS |
173 | default: |
174 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
49cd97a3 VS |
175 | cdclk_state->cdclk = 200000; |
176 | break; | |
7ff89ca2 VS |
177 | } |
178 | } | |
179 | ||
180 | static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) | |
181 | { | |
182 | static const unsigned int blb_vco[8] = { | |
183 | [0] = 3200000, | |
184 | [1] = 4000000, | |
185 | [2] = 5333333, | |
186 | [3] = 4800000, | |
187 | [4] = 6400000, | |
188 | }; | |
189 | static const unsigned int pnv_vco[8] = { | |
190 | [0] = 3200000, | |
191 | [1] = 4000000, | |
192 | [2] = 5333333, | |
193 | [3] = 4800000, | |
194 | [4] = 2666667, | |
195 | }; | |
196 | static const unsigned int cl_vco[8] = { | |
197 | [0] = 3200000, | |
198 | [1] = 4000000, | |
199 | [2] = 5333333, | |
200 | [3] = 6400000, | |
201 | [4] = 3333333, | |
202 | [5] = 3566667, | |
203 | [6] = 4266667, | |
204 | }; | |
205 | static const unsigned int elk_vco[8] = { | |
206 | [0] = 3200000, | |
207 | [1] = 4000000, | |
208 | [2] = 5333333, | |
209 | [3] = 4800000, | |
210 | }; | |
211 | static const unsigned int ctg_vco[8] = { | |
212 | [0] = 3200000, | |
213 | [1] = 4000000, | |
214 | [2] = 5333333, | |
215 | [3] = 6400000, | |
216 | [4] = 2666667, | |
217 | [5] = 4266667, | |
218 | }; | |
219 | const unsigned int *vco_table; | |
220 | unsigned int vco; | |
221 | uint8_t tmp = 0; | |
222 | ||
223 | /* FIXME other chipsets? */ | |
224 | if (IS_GM45(dev_priv)) | |
225 | vco_table = ctg_vco; | |
6b9e441d | 226 | else if (IS_G45(dev_priv)) |
7ff89ca2 VS |
227 | vco_table = elk_vco; |
228 | else if (IS_I965GM(dev_priv)) | |
229 | vco_table = cl_vco; | |
230 | else if (IS_PINEVIEW(dev_priv)) | |
231 | vco_table = pnv_vco; | |
232 | else if (IS_G33(dev_priv)) | |
233 | vco_table = blb_vco; | |
234 | else | |
235 | return 0; | |
236 | ||
237 | tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); | |
238 | ||
239 | vco = vco_table[tmp & 0x7]; | |
240 | if (vco == 0) | |
241 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
242 | else | |
243 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
244 | ||
245 | return vco; | |
246 | } | |
247 | ||
49cd97a3 VS |
248 | static void g33_get_cdclk(struct drm_i915_private *dev_priv, |
249 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
250 | { |
251 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
252 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
253 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
254 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
255 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
256 | const uint8_t *div_table; | |
49cd97a3 | 257 | unsigned int cdclk_sel; |
7ff89ca2 VS |
258 | uint16_t tmp = 0; |
259 | ||
49cd97a3 VS |
260 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
261 | ||
7ff89ca2 VS |
262 | pci_read_config_word(pdev, GCFGC, &tmp); |
263 | ||
264 | cdclk_sel = (tmp >> 4) & 0x7; | |
265 | ||
266 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
267 | goto fail; | |
268 | ||
49cd97a3 | 269 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
270 | case 3200000: |
271 | div_table = div_3200; | |
272 | break; | |
273 | case 4000000: | |
274 | div_table = div_4000; | |
275 | break; | |
276 | case 4800000: | |
277 | div_table = div_4800; | |
278 | break; | |
279 | case 5333333: | |
280 | div_table = div_5333; | |
281 | break; | |
282 | default: | |
283 | goto fail; | |
284 | } | |
285 | ||
49cd97a3 VS |
286 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, |
287 | div_table[cdclk_sel]); | |
288 | return; | |
7ff89ca2 VS |
289 | |
290 | fail: | |
291 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", | |
49cd97a3 VS |
292 | cdclk_state->vco, tmp); |
293 | cdclk_state->cdclk = 190476; | |
7ff89ca2 VS |
294 | } |
295 | ||
49cd97a3 VS |
296 | static void pnv_get_cdclk(struct drm_i915_private *dev_priv, |
297 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
298 | { |
299 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
300 | u16 gcfgc = 0; | |
301 | ||
302 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
303 | ||
304 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
305 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
49cd97a3 VS |
306 | cdclk_state->cdclk = 266667; |
307 | break; | |
7ff89ca2 | 308 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
49cd97a3 VS |
309 | cdclk_state->cdclk = 333333; |
310 | break; | |
7ff89ca2 | 311 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
49cd97a3 VS |
312 | cdclk_state->cdclk = 444444; |
313 | break; | |
7ff89ca2 | 314 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
49cd97a3 VS |
315 | cdclk_state->cdclk = 200000; |
316 | break; | |
7ff89ca2 VS |
317 | default: |
318 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
319 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
49cd97a3 VS |
320 | cdclk_state->cdclk = 133333; |
321 | break; | |
7ff89ca2 | 322 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
49cd97a3 VS |
323 | cdclk_state->cdclk = 166667; |
324 | break; | |
7ff89ca2 VS |
325 | } |
326 | } | |
327 | ||
49cd97a3 VS |
328 | static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, |
329 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
330 | { |
331 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
332 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
333 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
334 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
335 | const uint8_t *div_table; | |
49cd97a3 | 336 | unsigned int cdclk_sel; |
7ff89ca2 VS |
337 | uint16_t tmp = 0; |
338 | ||
49cd97a3 VS |
339 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
340 | ||
7ff89ca2 VS |
341 | pci_read_config_word(pdev, GCFGC, &tmp); |
342 | ||
343 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
344 | ||
345 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
346 | goto fail; | |
347 | ||
49cd97a3 | 348 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
349 | case 3200000: |
350 | div_table = div_3200; | |
351 | break; | |
352 | case 4000000: | |
353 | div_table = div_4000; | |
354 | break; | |
355 | case 5333333: | |
356 | div_table = div_5333; | |
357 | break; | |
358 | default: | |
359 | goto fail; | |
360 | } | |
361 | ||
49cd97a3 VS |
362 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, |
363 | div_table[cdclk_sel]); | |
364 | return; | |
7ff89ca2 VS |
365 | |
366 | fail: | |
367 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", | |
49cd97a3 VS |
368 | cdclk_state->vco, tmp); |
369 | cdclk_state->cdclk = 200000; | |
7ff89ca2 VS |
370 | } |
371 | ||
49cd97a3 VS |
372 | static void gm45_get_cdclk(struct drm_i915_private *dev_priv, |
373 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
374 | { |
375 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
49cd97a3 | 376 | unsigned int cdclk_sel; |
7ff89ca2 VS |
377 | uint16_t tmp = 0; |
378 | ||
49cd97a3 VS |
379 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
380 | ||
7ff89ca2 VS |
381 | pci_read_config_word(pdev, GCFGC, &tmp); |
382 | ||
383 | cdclk_sel = (tmp >> 12) & 0x1; | |
384 | ||
49cd97a3 | 385 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
386 | case 2666667: |
387 | case 4000000: | |
388 | case 5333333: | |
49cd97a3 VS |
389 | cdclk_state->cdclk = cdclk_sel ? 333333 : 222222; |
390 | break; | |
7ff89ca2 | 391 | case 3200000: |
49cd97a3 VS |
392 | cdclk_state->cdclk = cdclk_sel ? 320000 : 228571; |
393 | break; | |
7ff89ca2 VS |
394 | default: |
395 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", | |
49cd97a3 VS |
396 | cdclk_state->vco, tmp); |
397 | cdclk_state->cdclk = 222222; | |
398 | break; | |
7ff89ca2 VS |
399 | } |
400 | } | |
401 | ||
49cd97a3 VS |
402 | static void hsw_get_cdclk(struct drm_i915_private *dev_priv, |
403 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
404 | { |
405 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
406 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
407 | ||
408 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
49cd97a3 | 409 | cdclk_state->cdclk = 800000; |
7ff89ca2 | 410 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
49cd97a3 | 411 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 412 | else if (freq == LCPLL_CLK_FREQ_450) |
49cd97a3 | 413 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 414 | else if (IS_HSW_ULT(dev_priv)) |
49cd97a3 | 415 | cdclk_state->cdclk = 337500; |
7ff89ca2 | 416 | else |
49cd97a3 | 417 | cdclk_state->cdclk = 540000; |
7ff89ca2 VS |
418 | } |
419 | ||
d305e061 | 420 | static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) |
7ff89ca2 VS |
421 | { |
422 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? | |
423 | 333333 : 320000; | |
7ff89ca2 VS |
424 | |
425 | /* | |
426 | * We seem to get an unstable or solid color picture at 200MHz. | |
427 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
428 | * are off. | |
429 | */ | |
d305e061 | 430 | if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) |
7ff89ca2 | 431 | return 400000; |
d305e061 | 432 | else if (min_cdclk > 266667) |
7ff89ca2 | 433 | return freq_320; |
d305e061 | 434 | else if (min_cdclk > 0) |
7ff89ca2 VS |
435 | return 266667; |
436 | else | |
437 | return 200000; | |
438 | } | |
439 | ||
49cd97a3 VS |
440 | static void vlv_get_cdclk(struct drm_i915_private *dev_priv, |
441 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 442 | { |
49cd97a3 VS |
443 | cdclk_state->vco = vlv_get_hpll_vco(dev_priv); |
444 | cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", | |
445 | CCK_DISPLAY_CLOCK_CONTROL, | |
446 | cdclk_state->vco); | |
7ff89ca2 VS |
447 | } |
448 | ||
449 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) | |
450 | { | |
451 | unsigned int credits, default_credits; | |
452 | ||
453 | if (IS_CHERRYVIEW(dev_priv)) | |
454 | default_credits = PFI_CREDIT(12); | |
455 | else | |
456 | default_credits = PFI_CREDIT(8); | |
457 | ||
49cd97a3 | 458 | if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { |
7ff89ca2 VS |
459 | /* CHV suggested value is 31 or 63 */ |
460 | if (IS_CHERRYVIEW(dev_priv)) | |
461 | credits = PFI_CREDIT_63; | |
462 | else | |
463 | credits = PFI_CREDIT(15); | |
464 | } else { | |
465 | credits = default_credits; | |
466 | } | |
467 | ||
468 | /* | |
469 | * WA - write default credits before re-programming | |
470 | * FIXME: should we also set the resend bit here? | |
471 | */ | |
472 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
473 | default_credits); | |
474 | ||
475 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
476 | credits | PFI_CREDIT_RESEND); | |
477 | ||
478 | /* | |
479 | * FIXME is this guaranteed to clear | |
480 | * immediately or should we poll for it? | |
481 | */ | |
482 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
483 | } | |
484 | ||
83c5fda7 VS |
485 | static void vlv_set_cdclk(struct drm_i915_private *dev_priv, |
486 | const struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 487 | { |
83c5fda7 | 488 | int cdclk = cdclk_state->cdclk; |
7ff89ca2 VS |
489 | u32 val, cmd; |
490 | ||
886015a0 GKB |
491 | /* There are cases where we can end up here with power domains |
492 | * off and a CDCLK frequency other than the minimum, like when | |
493 | * issuing a modeset without actually changing any display after | |
494 | * a system suspend. So grab the PIPE-A domain, which covers | |
495 | * the HW blocks needed for the following programming. | |
496 | */ | |
497 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
498 | ||
7ff89ca2 VS |
499 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
500 | cmd = 2; | |
501 | else if (cdclk == 266667) | |
502 | cmd = 1; | |
503 | else | |
504 | cmd = 0; | |
505 | ||
506 | mutex_lock(&dev_priv->rps.hw_lock); | |
507 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
508 | val &= ~DSPFREQGUAR_MASK; | |
509 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
510 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
511 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
512 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
513 | 50)) { | |
514 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
515 | } | |
516 | mutex_unlock(&dev_priv->rps.hw_lock); | |
517 | ||
518 | mutex_lock(&dev_priv->sb_lock); | |
519 | ||
520 | if (cdclk == 400000) { | |
521 | u32 divider; | |
522 | ||
523 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, | |
524 | cdclk) - 1; | |
525 | ||
526 | /* adjust cdclk divider */ | |
527 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
528 | val &= ~CCK_FREQUENCY_VALUES; | |
529 | val |= divider; | |
530 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
531 | ||
532 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
533 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
534 | 50)) | |
535 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
536 | } | |
537 | ||
538 | /* adjust self-refresh exit latency value */ | |
539 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
540 | val &= ~0x7f; | |
541 | ||
542 | /* | |
543 | * For high bandwidth configs, we set a higher latency in the bunit | |
544 | * so that the core display fetch happens in time to avoid underruns. | |
545 | */ | |
546 | if (cdclk == 400000) | |
547 | val |= 4500 / 250; /* 4.5 usec */ | |
548 | else | |
549 | val |= 3000 / 250; /* 3.0 usec */ | |
550 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
551 | ||
552 | mutex_unlock(&dev_priv->sb_lock); | |
553 | ||
554 | intel_update_cdclk(dev_priv); | |
1a5301a5 VS |
555 | |
556 | vlv_program_pfi_credits(dev_priv); | |
886015a0 GKB |
557 | |
558 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); | |
7ff89ca2 VS |
559 | } |
560 | ||
83c5fda7 VS |
561 | static void chv_set_cdclk(struct drm_i915_private *dev_priv, |
562 | const struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 563 | { |
83c5fda7 | 564 | int cdclk = cdclk_state->cdclk; |
7ff89ca2 VS |
565 | u32 val, cmd; |
566 | ||
7ff89ca2 VS |
567 | switch (cdclk) { |
568 | case 333333: | |
569 | case 320000: | |
570 | case 266667: | |
571 | case 200000: | |
572 | break; | |
573 | default: | |
574 | MISSING_CASE(cdclk); | |
575 | return; | |
576 | } | |
577 | ||
886015a0 GKB |
578 | /* There are cases where we can end up here with power domains |
579 | * off and a CDCLK frequency other than the minimum, like when | |
580 | * issuing a modeset without actually changing any display after | |
581 | * a system suspend. So grab the PIPE-A domain, which covers | |
582 | * the HW blocks needed for the following programming. | |
583 | */ | |
584 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
585 | ||
7ff89ca2 VS |
586 | /* |
587 | * Specs are full of misinformation, but testing on actual | |
588 | * hardware has shown that we just need to write the desired | |
589 | * CCK divider into the Punit register. | |
590 | */ | |
591 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
592 | ||
593 | mutex_lock(&dev_priv->rps.hw_lock); | |
594 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
595 | val &= ~DSPFREQGUAR_MASK_CHV; | |
596 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
597 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
598 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
599 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
600 | 50)) { | |
601 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
602 | } | |
603 | mutex_unlock(&dev_priv->rps.hw_lock); | |
604 | ||
605 | intel_update_cdclk(dev_priv); | |
1a5301a5 VS |
606 | |
607 | vlv_program_pfi_credits(dev_priv); | |
886015a0 GKB |
608 | |
609 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); | |
7ff89ca2 VS |
610 | } |
611 | ||
d305e061 | 612 | static int bdw_calc_cdclk(int min_cdclk) |
7ff89ca2 | 613 | { |
d305e061 | 614 | if (min_cdclk > 540000) |
7ff89ca2 | 615 | return 675000; |
d305e061 | 616 | else if (min_cdclk > 450000) |
7ff89ca2 | 617 | return 540000; |
d305e061 | 618 | else if (min_cdclk > 337500) |
7ff89ca2 VS |
619 | return 450000; |
620 | else | |
621 | return 337500; | |
622 | } | |
623 | ||
49cd97a3 VS |
624 | static void bdw_get_cdclk(struct drm_i915_private *dev_priv, |
625 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
626 | { |
627 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
628 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
629 | ||
630 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
49cd97a3 | 631 | cdclk_state->cdclk = 800000; |
7ff89ca2 | 632 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
49cd97a3 | 633 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 634 | else if (freq == LCPLL_CLK_FREQ_450) |
49cd97a3 | 635 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 636 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) |
49cd97a3 | 637 | cdclk_state->cdclk = 540000; |
7ff89ca2 | 638 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) |
49cd97a3 | 639 | cdclk_state->cdclk = 337500; |
7ff89ca2 | 640 | else |
49cd97a3 | 641 | cdclk_state->cdclk = 675000; |
7ff89ca2 VS |
642 | } |
643 | ||
83c5fda7 VS |
644 | static void bdw_set_cdclk(struct drm_i915_private *dev_priv, |
645 | const struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 646 | { |
83c5fda7 | 647 | int cdclk = cdclk_state->cdclk; |
7ff89ca2 VS |
648 | uint32_t val, data; |
649 | int ret; | |
650 | ||
651 | if (WARN((I915_READ(LCPLL_CTL) & | |
652 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
653 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
654 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
655 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
656 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
657 | return; | |
658 | ||
659 | mutex_lock(&dev_priv->rps.hw_lock); | |
660 | ret = sandybridge_pcode_write(dev_priv, | |
661 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
662 | mutex_unlock(&dev_priv->rps.hw_lock); | |
663 | if (ret) { | |
664 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
665 | return; | |
666 | } | |
667 | ||
668 | val = I915_READ(LCPLL_CTL); | |
669 | val |= LCPLL_CD_SOURCE_FCLK; | |
670 | I915_WRITE(LCPLL_CTL, val); | |
671 | ||
672 | if (wait_for_us(I915_READ(LCPLL_CTL) & | |
673 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
674 | DRM_ERROR("Switching to FCLK failed\n"); | |
675 | ||
676 | val = I915_READ(LCPLL_CTL); | |
677 | val &= ~LCPLL_CLK_FREQ_MASK; | |
678 | ||
679 | switch (cdclk) { | |
680 | case 450000: | |
681 | val |= LCPLL_CLK_FREQ_450; | |
682 | data = 0; | |
683 | break; | |
684 | case 540000: | |
685 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
686 | data = 1; | |
687 | break; | |
688 | case 337500: | |
689 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
690 | data = 2; | |
691 | break; | |
692 | case 675000: | |
693 | val |= LCPLL_CLK_FREQ_675_BDW; | |
694 | data = 3; | |
695 | break; | |
696 | default: | |
697 | WARN(1, "invalid cdclk frequency\n"); | |
698 | return; | |
699 | } | |
700 | ||
701 | I915_WRITE(LCPLL_CTL, val); | |
702 | ||
703 | val = I915_READ(LCPLL_CTL); | |
704 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
705 | I915_WRITE(LCPLL_CTL, val); | |
706 | ||
707 | if (wait_for_us((I915_READ(LCPLL_CTL) & | |
708 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
709 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
710 | ||
711 | mutex_lock(&dev_priv->rps.hw_lock); | |
712 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
713 | mutex_unlock(&dev_priv->rps.hw_lock); | |
714 | ||
715 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); | |
716 | ||
717 | intel_update_cdclk(dev_priv); | |
718 | ||
49cd97a3 | 719 | WARN(cdclk != dev_priv->cdclk.hw.cdclk, |
7ff89ca2 | 720 | "cdclk requested %d kHz but got %d kHz\n", |
49cd97a3 | 721 | cdclk, dev_priv->cdclk.hw.cdclk); |
7ff89ca2 VS |
722 | } |
723 | ||
d305e061 | 724 | static int skl_calc_cdclk(int min_cdclk, int vco) |
7ff89ca2 VS |
725 | { |
726 | if (vco == 8640000) { | |
d305e061 | 727 | if (min_cdclk > 540000) |
7ff89ca2 | 728 | return 617143; |
d305e061 | 729 | else if (min_cdclk > 432000) |
7ff89ca2 | 730 | return 540000; |
d305e061 | 731 | else if (min_cdclk > 308571) |
7ff89ca2 VS |
732 | return 432000; |
733 | else | |
734 | return 308571; | |
735 | } else { | |
d305e061 | 736 | if (min_cdclk > 540000) |
7ff89ca2 | 737 | return 675000; |
d305e061 | 738 | else if (min_cdclk > 450000) |
7ff89ca2 | 739 | return 540000; |
d305e061 | 740 | else if (min_cdclk > 337500) |
7ff89ca2 VS |
741 | return 450000; |
742 | else | |
743 | return 337500; | |
744 | } | |
745 | } | |
746 | ||
49cd97a3 VS |
747 | static void skl_dpll0_update(struct drm_i915_private *dev_priv, |
748 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
749 | { |
750 | u32 val; | |
751 | ||
49cd97a3 VS |
752 | cdclk_state->ref = 24000; |
753 | cdclk_state->vco = 0; | |
7ff89ca2 VS |
754 | |
755 | val = I915_READ(LCPLL1_CTL); | |
756 | if ((val & LCPLL_PLL_ENABLE) == 0) | |
757 | return; | |
758 | ||
759 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) | |
760 | return; | |
761 | ||
762 | val = I915_READ(DPLL_CTRL1); | |
763 | ||
764 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | | |
765 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
766 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
767 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
768 | return; | |
769 | ||
770 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { | |
771 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
772 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
773 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
774 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
49cd97a3 | 775 | cdclk_state->vco = 8100000; |
7ff89ca2 VS |
776 | break; |
777 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
778 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
49cd97a3 | 779 | cdclk_state->vco = 8640000; |
7ff89ca2 VS |
780 | break; |
781 | default: | |
782 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
783 | break; | |
784 | } | |
785 | } | |
786 | ||
49cd97a3 VS |
787 | static void skl_get_cdclk(struct drm_i915_private *dev_priv, |
788 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
789 | { |
790 | u32 cdctl; | |
791 | ||
49cd97a3 | 792 | skl_dpll0_update(dev_priv, cdclk_state); |
7ff89ca2 | 793 | |
49cd97a3 VS |
794 | cdclk_state->cdclk = cdclk_state->ref; |
795 | ||
796 | if (cdclk_state->vco == 0) | |
797 | return; | |
7ff89ca2 VS |
798 | |
799 | cdctl = I915_READ(CDCLK_CTL); | |
800 | ||
49cd97a3 | 801 | if (cdclk_state->vco == 8640000) { |
7ff89ca2 VS |
802 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
803 | case CDCLK_FREQ_450_432: | |
49cd97a3 VS |
804 | cdclk_state->cdclk = 432000; |
805 | break; | |
7ff89ca2 | 806 | case CDCLK_FREQ_337_308: |
49cd97a3 VS |
807 | cdclk_state->cdclk = 308571; |
808 | break; | |
7ff89ca2 | 809 | case CDCLK_FREQ_540: |
49cd97a3 VS |
810 | cdclk_state->cdclk = 540000; |
811 | break; | |
7ff89ca2 | 812 | case CDCLK_FREQ_675_617: |
49cd97a3 VS |
813 | cdclk_state->cdclk = 617143; |
814 | break; | |
7ff89ca2 VS |
815 | default: |
816 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); | |
49cd97a3 | 817 | break; |
7ff89ca2 VS |
818 | } |
819 | } else { | |
820 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
821 | case CDCLK_FREQ_450_432: | |
49cd97a3 VS |
822 | cdclk_state->cdclk = 450000; |
823 | break; | |
7ff89ca2 | 824 | case CDCLK_FREQ_337_308: |
49cd97a3 VS |
825 | cdclk_state->cdclk = 337500; |
826 | break; | |
7ff89ca2 | 827 | case CDCLK_FREQ_540: |
49cd97a3 VS |
828 | cdclk_state->cdclk = 540000; |
829 | break; | |
7ff89ca2 | 830 | case CDCLK_FREQ_675_617: |
49cd97a3 VS |
831 | cdclk_state->cdclk = 675000; |
832 | break; | |
7ff89ca2 VS |
833 | default: |
834 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); | |
49cd97a3 | 835 | break; |
7ff89ca2 VS |
836 | } |
837 | } | |
7ff89ca2 VS |
838 | } |
839 | ||
840 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
841 | static int skl_cdclk_decimal(int cdclk) | |
842 | { | |
843 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
844 | } | |
845 | ||
846 | static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, | |
847 | int vco) | |
848 | { | |
849 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
850 | ||
851 | dev_priv->skl_preferred_vco_freq = vco; | |
852 | ||
853 | if (changed) | |
854 | intel_update_max_cdclk(dev_priv); | |
855 | } | |
856 | ||
857 | static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) | |
858 | { | |
859 | int min_cdclk = skl_calc_cdclk(0, vco); | |
860 | u32 val; | |
861 | ||
862 | WARN_ON(vco != 8100000 && vco != 8640000); | |
863 | ||
864 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
865 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); | |
866 | I915_WRITE(CDCLK_CTL, val); | |
867 | POSTING_READ(CDCLK_CTL); | |
868 | ||
869 | /* | |
870 | * We always enable DPLL0 with the lowest link rate possible, but still | |
871 | * taking into account the VCO required to operate the eDP panel at the | |
872 | * desired frequency. The usual DP link rates operate with a VCO of | |
873 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
874 | * The modeset code is responsible for the selection of the exact link | |
875 | * rate later on, with the constraint of choosing a frequency that | |
876 | * works with vco. | |
877 | */ | |
878 | val = I915_READ(DPLL_CTRL1); | |
879 | ||
880 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
881 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
882 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
883 | if (vco == 8640000) | |
884 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
885 | SKL_DPLL0); | |
886 | else | |
887 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
888 | SKL_DPLL0); | |
889 | ||
890 | I915_WRITE(DPLL_CTRL1, val); | |
891 | POSTING_READ(DPLL_CTRL1); | |
892 | ||
893 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
894 | ||
895 | if (intel_wait_for_register(dev_priv, | |
896 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
897 | 5)) | |
898 | DRM_ERROR("DPLL0 not locked\n"); | |
899 | ||
49cd97a3 | 900 | dev_priv->cdclk.hw.vco = vco; |
7ff89ca2 VS |
901 | |
902 | /* We'll want to keep using the current vco from now on. */ | |
903 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
904 | } | |
905 | ||
906 | static void skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
907 | { | |
908 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
909 | if (intel_wait_for_register(dev_priv, | |
910 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
911 | 1)) | |
912 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
913 | ||
49cd97a3 | 914 | dev_priv->cdclk.hw.vco = 0; |
7ff89ca2 VS |
915 | } |
916 | ||
917 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, | |
83c5fda7 | 918 | const struct intel_cdclk_state *cdclk_state) |
7ff89ca2 | 919 | { |
83c5fda7 VS |
920 | int cdclk = cdclk_state->cdclk; |
921 | int vco = cdclk_state->vco; | |
7ff89ca2 VS |
922 | u32 freq_select, pcu_ack; |
923 | int ret; | |
924 | ||
925 | WARN_ON((cdclk == 24000) != (vco == 0)); | |
926 | ||
7ff89ca2 VS |
927 | mutex_lock(&dev_priv->rps.hw_lock); |
928 | ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, | |
929 | SKL_CDCLK_PREPARE_FOR_CHANGE, | |
930 | SKL_CDCLK_READY_FOR_CHANGE, | |
931 | SKL_CDCLK_READY_FOR_CHANGE, 3); | |
932 | mutex_unlock(&dev_priv->rps.hw_lock); | |
933 | if (ret) { | |
934 | DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", | |
935 | ret); | |
936 | return; | |
937 | } | |
938 | ||
939 | /* set CDCLK_CTL */ | |
940 | switch (cdclk) { | |
941 | case 450000: | |
942 | case 432000: | |
943 | freq_select = CDCLK_FREQ_450_432; | |
944 | pcu_ack = 1; | |
945 | break; | |
946 | case 540000: | |
947 | freq_select = CDCLK_FREQ_540; | |
948 | pcu_ack = 2; | |
949 | break; | |
950 | case 308571: | |
951 | case 337500: | |
952 | default: | |
953 | freq_select = CDCLK_FREQ_337_308; | |
954 | pcu_ack = 0; | |
955 | break; | |
956 | case 617143: | |
957 | case 675000: | |
958 | freq_select = CDCLK_FREQ_675_617; | |
959 | pcu_ack = 3; | |
960 | break; | |
961 | } | |
962 | ||
49cd97a3 VS |
963 | if (dev_priv->cdclk.hw.vco != 0 && |
964 | dev_priv->cdclk.hw.vco != vco) | |
7ff89ca2 VS |
965 | skl_dpll0_disable(dev_priv); |
966 | ||
49cd97a3 | 967 | if (dev_priv->cdclk.hw.vco != vco) |
7ff89ca2 VS |
968 | skl_dpll0_enable(dev_priv, vco); |
969 | ||
970 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); | |
971 | POSTING_READ(CDCLK_CTL); | |
972 | ||
973 | /* inform PCU of the change */ | |
974 | mutex_lock(&dev_priv->rps.hw_lock); | |
975 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
976 | mutex_unlock(&dev_priv->rps.hw_lock); | |
977 | ||
978 | intel_update_cdclk(dev_priv); | |
979 | } | |
980 | ||
981 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
982 | { | |
983 | uint32_t cdctl, expected; | |
984 | ||
985 | /* | |
986 | * check if the pre-os initialized the display | |
987 | * There is SWF18 scratchpad register defined which is set by the | |
988 | * pre-os which can be used by the OS drivers to check the status | |
989 | */ | |
990 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
991 | goto sanitize; | |
992 | ||
993 | intel_update_cdclk(dev_priv); | |
994 | /* Is PLL enabled and locked ? */ | |
49cd97a3 VS |
995 | if (dev_priv->cdclk.hw.vco == 0 || |
996 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref) | |
7ff89ca2 VS |
997 | goto sanitize; |
998 | ||
999 | /* DPLL okay; verify the cdclock | |
1000 | * | |
1001 | * Noticed in some instances that the freq selection is correct but | |
1002 | * decimal part is programmed wrong from BIOS where pre-os does not | |
1003 | * enable display. Verify the same as well. | |
1004 | */ | |
1005 | cdctl = I915_READ(CDCLK_CTL); | |
1006 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
49cd97a3 | 1007 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); |
7ff89ca2 VS |
1008 | if (cdctl == expected) |
1009 | /* All well; nothing to sanitize */ | |
1010 | return; | |
1011 | ||
1012 | sanitize: | |
1013 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
1014 | ||
1015 | /* force cdclk programming */ | |
49cd97a3 | 1016 | dev_priv->cdclk.hw.cdclk = 0; |
7ff89ca2 | 1017 | /* force full PLL disable + enable */ |
49cd97a3 | 1018 | dev_priv->cdclk.hw.vco = -1; |
7ff89ca2 VS |
1019 | } |
1020 | ||
1021 | /** | |
1022 | * skl_init_cdclk - Initialize CDCLK on SKL | |
1023 | * @dev_priv: i915 device | |
1024 | * | |
1025 | * Initialize CDCLK for SKL and derivatives. This is generally | |
1026 | * done only during the display core initialization sequence, | |
1027 | * after which the DMC will take care of turning CDCLK off/on | |
1028 | * as needed. | |
1029 | */ | |
1030 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
1031 | { | |
83c5fda7 | 1032 | struct intel_cdclk_state cdclk_state; |
7ff89ca2 VS |
1033 | |
1034 | skl_sanitize_cdclk(dev_priv); | |
1035 | ||
49cd97a3 VS |
1036 | if (dev_priv->cdclk.hw.cdclk != 0 && |
1037 | dev_priv->cdclk.hw.vco != 0) { | |
7ff89ca2 VS |
1038 | /* |
1039 | * Use the current vco as our initial | |
1040 | * guess as to what the preferred vco is. | |
1041 | */ | |
1042 | if (dev_priv->skl_preferred_vco_freq == 0) | |
1043 | skl_set_preferred_cdclk_vco(dev_priv, | |
49cd97a3 | 1044 | dev_priv->cdclk.hw.vco); |
7ff89ca2 VS |
1045 | return; |
1046 | } | |
1047 | ||
83c5fda7 VS |
1048 | cdclk_state = dev_priv->cdclk.hw; |
1049 | ||
1050 | cdclk_state.vco = dev_priv->skl_preferred_vco_freq; | |
1051 | if (cdclk_state.vco == 0) | |
1052 | cdclk_state.vco = 8100000; | |
1053 | cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); | |
7ff89ca2 | 1054 | |
83c5fda7 | 1055 | skl_set_cdclk(dev_priv, &cdclk_state); |
7ff89ca2 VS |
1056 | } |
1057 | ||
1058 | /** | |
1059 | * skl_uninit_cdclk - Uninitialize CDCLK on SKL | |
1060 | * @dev_priv: i915 device | |
1061 | * | |
1062 | * Uninitialize CDCLK for SKL and derivatives. This is done only | |
1063 | * during the display core uninitialization sequence. | |
1064 | */ | |
1065 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
1066 | { | |
83c5fda7 VS |
1067 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; |
1068 | ||
1069 | cdclk_state.cdclk = cdclk_state.ref; | |
1070 | cdclk_state.vco = 0; | |
1071 | ||
1072 | skl_set_cdclk(dev_priv, &cdclk_state); | |
7ff89ca2 VS |
1073 | } |
1074 | ||
d305e061 | 1075 | static int bxt_calc_cdclk(int min_cdclk) |
7ff89ca2 | 1076 | { |
d305e061 | 1077 | if (min_cdclk > 576000) |
7ff89ca2 | 1078 | return 624000; |
d305e061 | 1079 | else if (min_cdclk > 384000) |
7ff89ca2 | 1080 | return 576000; |
d305e061 | 1081 | else if (min_cdclk > 288000) |
7ff89ca2 | 1082 | return 384000; |
d305e061 | 1083 | else if (min_cdclk > 144000) |
7ff89ca2 VS |
1084 | return 288000; |
1085 | else | |
1086 | return 144000; | |
1087 | } | |
1088 | ||
d305e061 | 1089 | static int glk_calc_cdclk(int min_cdclk) |
7ff89ca2 | 1090 | { |
d305e061 | 1091 | if (min_cdclk > 158400) |
7ff89ca2 | 1092 | return 316800; |
d305e061 | 1093 | else if (min_cdclk > 79200) |
7ff89ca2 VS |
1094 | return 158400; |
1095 | else | |
1096 | return 79200; | |
1097 | } | |
1098 | ||
1099 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) | |
1100 | { | |
1101 | int ratio; | |
1102 | ||
49cd97a3 | 1103 | if (cdclk == dev_priv->cdclk.hw.ref) |
7ff89ca2 VS |
1104 | return 0; |
1105 | ||
1106 | switch (cdclk) { | |
1107 | default: | |
1108 | MISSING_CASE(cdclk); | |
1109 | case 144000: | |
1110 | case 288000: | |
1111 | case 384000: | |
1112 | case 576000: | |
1113 | ratio = 60; | |
1114 | break; | |
1115 | case 624000: | |
1116 | ratio = 65; | |
1117 | break; | |
1118 | } | |
1119 | ||
49cd97a3 | 1120 | return dev_priv->cdclk.hw.ref * ratio; |
7ff89ca2 VS |
1121 | } |
1122 | ||
1123 | static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) | |
1124 | { | |
1125 | int ratio; | |
1126 | ||
49cd97a3 | 1127 | if (cdclk == dev_priv->cdclk.hw.ref) |
7ff89ca2 VS |
1128 | return 0; |
1129 | ||
1130 | switch (cdclk) { | |
1131 | default: | |
1132 | MISSING_CASE(cdclk); | |
1133 | case 79200: | |
1134 | case 158400: | |
1135 | case 316800: | |
1136 | ratio = 33; | |
1137 | break; | |
1138 | } | |
1139 | ||
49cd97a3 | 1140 | return dev_priv->cdclk.hw.ref * ratio; |
7ff89ca2 VS |
1141 | } |
1142 | ||
49cd97a3 VS |
1143 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv, |
1144 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
1145 | { |
1146 | u32 val; | |
1147 | ||
49cd97a3 VS |
1148 | cdclk_state->ref = 19200; |
1149 | cdclk_state->vco = 0; | |
7ff89ca2 VS |
1150 | |
1151 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1152 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) | |
1153 | return; | |
1154 | ||
1155 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) | |
1156 | return; | |
1157 | ||
1158 | val = I915_READ(BXT_DE_PLL_CTL); | |
49cd97a3 | 1159 | cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; |
7ff89ca2 VS |
1160 | } |
1161 | ||
49cd97a3 VS |
1162 | static void bxt_get_cdclk(struct drm_i915_private *dev_priv, |
1163 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
1164 | { |
1165 | u32 divider; | |
49cd97a3 | 1166 | int div; |
7ff89ca2 | 1167 | |
49cd97a3 | 1168 | bxt_de_pll_update(dev_priv, cdclk_state); |
7ff89ca2 | 1169 | |
49cd97a3 VS |
1170 | cdclk_state->cdclk = cdclk_state->ref; |
1171 | ||
1172 | if (cdclk_state->vco == 0) | |
1173 | return; | |
7ff89ca2 VS |
1174 | |
1175 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
1176 | ||
1177 | switch (divider) { | |
1178 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
1179 | div = 2; | |
1180 | break; | |
1181 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
1182 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); | |
1183 | div = 3; | |
1184 | break; | |
1185 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
1186 | div = 4; | |
1187 | break; | |
1188 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
1189 | div = 8; | |
1190 | break; | |
1191 | default: | |
1192 | MISSING_CASE(divider); | |
49cd97a3 | 1193 | return; |
7ff89ca2 VS |
1194 | } |
1195 | ||
49cd97a3 | 1196 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); |
7ff89ca2 VS |
1197 | } |
1198 | ||
1199 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) | |
1200 | { | |
1201 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
1202 | ||
1203 | /* Timeout 200us */ | |
1204 | if (intel_wait_for_register(dev_priv, | |
1205 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
1206 | 1)) | |
1207 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); | |
1208 | ||
49cd97a3 | 1209 | dev_priv->cdclk.hw.vco = 0; |
7ff89ca2 VS |
1210 | } |
1211 | ||
1212 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) | |
1213 | { | |
49cd97a3 | 1214 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); |
7ff89ca2 VS |
1215 | u32 val; |
1216 | ||
1217 | val = I915_READ(BXT_DE_PLL_CTL); | |
1218 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
1219 | val |= BXT_DE_PLL_RATIO(ratio); | |
1220 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
1221 | ||
1222 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
1223 | ||
1224 | /* Timeout 200us */ | |
1225 | if (intel_wait_for_register(dev_priv, | |
1226 | BXT_DE_PLL_ENABLE, | |
1227 | BXT_DE_PLL_LOCK, | |
1228 | BXT_DE_PLL_LOCK, | |
1229 | 1)) | |
1230 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
1231 | ||
49cd97a3 | 1232 | dev_priv->cdclk.hw.vco = vco; |
7ff89ca2 VS |
1233 | } |
1234 | ||
8f0cfa4d | 1235 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, |
83c5fda7 | 1236 | const struct intel_cdclk_state *cdclk_state) |
7ff89ca2 | 1237 | { |
83c5fda7 VS |
1238 | int cdclk = cdclk_state->cdclk; |
1239 | int vco = cdclk_state->vco; | |
7ff89ca2 | 1240 | u32 val, divider; |
8f0cfa4d | 1241 | int ret; |
7ff89ca2 | 1242 | |
7ff89ca2 VS |
1243 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ |
1244 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
1245 | case 8: | |
1246 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
1247 | break; | |
1248 | case 4: | |
1249 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
1250 | break; | |
1251 | case 3: | |
1252 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); | |
1253 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
1254 | break; | |
1255 | case 2: | |
1256 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
1257 | break; | |
1258 | default: | |
49cd97a3 | 1259 | WARN_ON(cdclk != dev_priv->cdclk.hw.ref); |
7ff89ca2 VS |
1260 | WARN_ON(vco != 0); |
1261 | ||
1262 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
1263 | break; | |
1264 | } | |
1265 | ||
1266 | /* Inform power controller of upcoming frequency change */ | |
1267 | mutex_lock(&dev_priv->rps.hw_lock); | |
1268 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
1269 | 0x80000000); | |
1270 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1271 | ||
1272 | if (ret) { | |
1273 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
1274 | ret, cdclk); | |
1275 | return; | |
1276 | } | |
1277 | ||
49cd97a3 VS |
1278 | if (dev_priv->cdclk.hw.vco != 0 && |
1279 | dev_priv->cdclk.hw.vco != vco) | |
7ff89ca2 VS |
1280 | bxt_de_pll_disable(dev_priv); |
1281 | ||
49cd97a3 | 1282 | if (dev_priv->cdclk.hw.vco != vco) |
7ff89ca2 VS |
1283 | bxt_de_pll_enable(dev_priv, vco); |
1284 | ||
1285 | val = divider | skl_cdclk_decimal(cdclk); | |
1286 | /* | |
1287 | * FIXME if only the cd2x divider needs changing, it could be done | |
1288 | * without shutting off the pipe (if only one pipe is active). | |
1289 | */ | |
1290 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
1291 | /* | |
1292 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
1293 | * enable otherwise. | |
1294 | */ | |
1295 | if (cdclk >= 500000) | |
1296 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
1297 | I915_WRITE(CDCLK_CTL, val); | |
1298 | ||
1299 | mutex_lock(&dev_priv->rps.hw_lock); | |
1300 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
1301 | DIV_ROUND_UP(cdclk, 25000)); | |
1302 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1303 | ||
1304 | if (ret) { | |
1305 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
1306 | ret, cdclk); | |
1307 | return; | |
1308 | } | |
1309 | ||
1310 | intel_update_cdclk(dev_priv); | |
1311 | } | |
1312 | ||
1313 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
1314 | { | |
1315 | u32 cdctl, expected; | |
1316 | ||
1317 | intel_update_cdclk(dev_priv); | |
1318 | ||
49cd97a3 VS |
1319 | if (dev_priv->cdclk.hw.vco == 0 || |
1320 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref) | |
7ff89ca2 VS |
1321 | goto sanitize; |
1322 | ||
1323 | /* DPLL okay; verify the cdclock | |
1324 | * | |
1325 | * Some BIOS versions leave an incorrect decimal frequency value and | |
1326 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
1327 | * so sanitize this register. | |
1328 | */ | |
1329 | cdctl = I915_READ(CDCLK_CTL); | |
1330 | /* | |
1331 | * Let's ignore the pipe field, since BIOS could have configured the | |
1332 | * dividers both synching to an active pipe, or asynchronously | |
1333 | * (PIPE_NONE). | |
1334 | */ | |
1335 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
1336 | ||
1337 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
49cd97a3 | 1338 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); |
7ff89ca2 VS |
1339 | /* |
1340 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
1341 | * enable otherwise. | |
1342 | */ | |
49cd97a3 | 1343 | if (dev_priv->cdclk.hw.cdclk >= 500000) |
7ff89ca2 VS |
1344 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
1345 | ||
1346 | if (cdctl == expected) | |
1347 | /* All well; nothing to sanitize */ | |
1348 | return; | |
1349 | ||
1350 | sanitize: | |
1351 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
1352 | ||
1353 | /* force cdclk programming */ | |
49cd97a3 | 1354 | dev_priv->cdclk.hw.cdclk = 0; |
7ff89ca2 VS |
1355 | |
1356 | /* force full PLL disable + enable */ | |
49cd97a3 | 1357 | dev_priv->cdclk.hw.vco = -1; |
7ff89ca2 VS |
1358 | } |
1359 | ||
1360 | /** | |
1361 | * bxt_init_cdclk - Initialize CDCLK on BXT | |
1362 | * @dev_priv: i915 device | |
1363 | * | |
1364 | * Initialize CDCLK for BXT and derivatives. This is generally | |
1365 | * done only during the display core initialization sequence, | |
1366 | * after which the DMC will take care of turning CDCLK off/on | |
1367 | * as needed. | |
1368 | */ | |
1369 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) | |
1370 | { | |
83c5fda7 | 1371 | struct intel_cdclk_state cdclk_state; |
7ff89ca2 VS |
1372 | |
1373 | bxt_sanitize_cdclk(dev_priv); | |
1374 | ||
49cd97a3 VS |
1375 | if (dev_priv->cdclk.hw.cdclk != 0 && |
1376 | dev_priv->cdclk.hw.vco != 0) | |
7ff89ca2 VS |
1377 | return; |
1378 | ||
83c5fda7 VS |
1379 | cdclk_state = dev_priv->cdclk.hw; |
1380 | ||
7ff89ca2 VS |
1381 | /* |
1382 | * FIXME: | |
1383 | * - The initial CDCLK needs to be read from VBT. | |
1384 | * Need to make this change after VBT has changes for BXT. | |
1385 | */ | |
8f0cfa4d | 1386 | if (IS_GEMINILAKE(dev_priv)) { |
83c5fda7 VS |
1387 | cdclk_state.cdclk = glk_calc_cdclk(0); |
1388 | cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk); | |
8f0cfa4d | 1389 | } else { |
83c5fda7 VS |
1390 | cdclk_state.cdclk = bxt_calc_cdclk(0); |
1391 | cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk); | |
8f0cfa4d | 1392 | } |
7ff89ca2 | 1393 | |
83c5fda7 | 1394 | bxt_set_cdclk(dev_priv, &cdclk_state); |
7ff89ca2 VS |
1395 | } |
1396 | ||
1397 | /** | |
1398 | * bxt_uninit_cdclk - Uninitialize CDCLK on BXT | |
1399 | * @dev_priv: i915 device | |
1400 | * | |
1401 | * Uninitialize CDCLK for BXT and derivatives. This is done only | |
1402 | * during the display core uninitialization sequence. | |
1403 | */ | |
1404 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) | |
1405 | { | |
83c5fda7 VS |
1406 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; |
1407 | ||
1408 | cdclk_state.cdclk = cdclk_state.ref; | |
1409 | cdclk_state.vco = 0; | |
1410 | ||
1411 | bxt_set_cdclk(dev_priv, &cdclk_state); | |
49cd97a3 VS |
1412 | } |
1413 | ||
d305e061 | 1414 | static int cnl_calc_cdclk(int min_cdclk) |
d1999e9e | 1415 | { |
d305e061 | 1416 | if (min_cdclk > 336000) |
d1999e9e | 1417 | return 528000; |
d305e061 | 1418 | else if (min_cdclk > 168000) |
d1999e9e RV |
1419 | return 336000; |
1420 | else | |
1421 | return 168000; | |
1422 | } | |
1423 | ||
945f2672 VS |
1424 | static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv, |
1425 | struct intel_cdclk_state *cdclk_state) | |
1426 | { | |
1427 | u32 val; | |
1428 | ||
1429 | if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz) | |
1430 | cdclk_state->ref = 24000; | |
1431 | else | |
1432 | cdclk_state->ref = 19200; | |
1433 | ||
1434 | cdclk_state->vco = 0; | |
1435 | ||
1436 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1437 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) | |
1438 | return; | |
1439 | ||
1440 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) | |
1441 | return; | |
1442 | ||
1443 | cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref; | |
1444 | } | |
1445 | ||
1446 | static void cnl_get_cdclk(struct drm_i915_private *dev_priv, | |
1447 | struct intel_cdclk_state *cdclk_state) | |
1448 | { | |
1449 | u32 divider; | |
1450 | int div; | |
1451 | ||
1452 | cnl_cdclk_pll_update(dev_priv, cdclk_state); | |
1453 | ||
1454 | cdclk_state->cdclk = cdclk_state->ref; | |
1455 | ||
1456 | if (cdclk_state->vco == 0) | |
1457 | return; | |
1458 | ||
1459 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
1460 | ||
1461 | switch (divider) { | |
1462 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
1463 | div = 2; | |
1464 | break; | |
1465 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
1466 | div = 4; | |
1467 | break; | |
1468 | default: | |
1469 | MISSING_CASE(divider); | |
1470 | return; | |
1471 | } | |
1472 | ||
1473 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); | |
1474 | } | |
1475 | ||
ef4f7a68 VS |
1476 | static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) |
1477 | { | |
1478 | u32 val; | |
1479 | ||
1480 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1481 | val &= ~BXT_DE_PLL_PLL_ENABLE; | |
1482 | I915_WRITE(BXT_DE_PLL_ENABLE, val); | |
1483 | ||
1484 | /* Timeout 200us */ | |
1485 | if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) | |
1486 | DRM_ERROR("timout waiting for CDCLK PLL unlock\n"); | |
1487 | ||
1488 | dev_priv->cdclk.hw.vco = 0; | |
1489 | } | |
1490 | ||
1491 | static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) | |
1492 | { | |
1493 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); | |
1494 | u32 val; | |
1495 | ||
1496 | val = CNL_CDCLK_PLL_RATIO(ratio); | |
1497 | I915_WRITE(BXT_DE_PLL_ENABLE, val); | |
1498 | ||
1499 | val |= BXT_DE_PLL_PLL_ENABLE; | |
1500 | I915_WRITE(BXT_DE_PLL_ENABLE, val); | |
1501 | ||
1502 | /* Timeout 200us */ | |
1503 | if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) | |
1504 | DRM_ERROR("timout waiting for CDCLK PLL lock\n"); | |
1505 | ||
1506 | dev_priv->cdclk.hw.vco = vco; | |
1507 | } | |
1508 | ||
ef4f7a68 VS |
1509 | static void cnl_set_cdclk(struct drm_i915_private *dev_priv, |
1510 | const struct intel_cdclk_state *cdclk_state) | |
1511 | { | |
1512 | int cdclk = cdclk_state->cdclk; | |
1513 | int vco = cdclk_state->vco; | |
1514 | u32 val, divider, pcu_ack; | |
1515 | int ret; | |
1516 | ||
1517 | mutex_lock(&dev_priv->rps.hw_lock); | |
1518 | ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, | |
1519 | SKL_CDCLK_PREPARE_FOR_CHANGE, | |
1520 | SKL_CDCLK_READY_FOR_CHANGE, | |
1521 | SKL_CDCLK_READY_FOR_CHANGE, 3); | |
1522 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1523 | if (ret) { | |
1524 | DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", | |
1525 | ret); | |
1526 | return; | |
1527 | } | |
1528 | ||
1529 | /* cdclk = vco / 2 / div{1,2} */ | |
1530 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
1531 | case 4: | |
1532 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
1533 | break; | |
1534 | case 2: | |
1535 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
1536 | break; | |
1537 | default: | |
1538 | WARN_ON(cdclk != dev_priv->cdclk.hw.ref); | |
1539 | WARN_ON(vco != 0); | |
1540 | ||
1541 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
1542 | break; | |
1543 | } | |
1544 | ||
1545 | switch (cdclk) { | |
1546 | case 528000: | |
1547 | pcu_ack = 2; | |
1548 | break; | |
1549 | case 336000: | |
1550 | pcu_ack = 1; | |
1551 | break; | |
1552 | case 168000: | |
1553 | default: | |
1554 | pcu_ack = 0; | |
1555 | break; | |
1556 | } | |
1557 | ||
1558 | if (dev_priv->cdclk.hw.vco != 0 && | |
1559 | dev_priv->cdclk.hw.vco != vco) | |
1560 | cnl_cdclk_pll_disable(dev_priv); | |
1561 | ||
1562 | if (dev_priv->cdclk.hw.vco != vco) | |
1563 | cnl_cdclk_pll_enable(dev_priv, vco); | |
1564 | ||
1565 | val = divider | skl_cdclk_decimal(cdclk); | |
1566 | /* | |
1567 | * FIXME if only the cd2x divider needs changing, it could be done | |
1568 | * without shutting off the pipe (if only one pipe is active). | |
1569 | */ | |
1570 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
1571 | I915_WRITE(CDCLK_CTL, val); | |
1572 | ||
1573 | /* inform PCU of the change */ | |
1574 | mutex_lock(&dev_priv->rps.hw_lock); | |
1575 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
1576 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1577 | ||
1578 | intel_update_cdclk(dev_priv); | |
1579 | } | |
1580 | ||
d8d4a512 VS |
1581 | static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
1582 | { | |
1583 | int ratio; | |
1584 | ||
1585 | if (cdclk == dev_priv->cdclk.hw.ref) | |
1586 | return 0; | |
1587 | ||
1588 | switch (cdclk) { | |
1589 | default: | |
1590 | MISSING_CASE(cdclk); | |
1591 | case 168000: | |
1592 | case 336000: | |
1593 | ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28; | |
1594 | break; | |
1595 | case 528000: | |
1596 | ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44; | |
1597 | break; | |
1598 | } | |
1599 | ||
1600 | return dev_priv->cdclk.hw.ref * ratio; | |
1601 | } | |
1602 | ||
1603 | static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
1604 | { | |
1605 | u32 cdctl, expected; | |
1606 | ||
1607 | intel_update_cdclk(dev_priv); | |
1608 | ||
1609 | if (dev_priv->cdclk.hw.vco == 0 || | |
1610 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref) | |
1611 | goto sanitize; | |
1612 | ||
1613 | /* DPLL okay; verify the cdclock | |
1614 | * | |
1615 | * Some BIOS versions leave an incorrect decimal frequency value and | |
1616 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
1617 | * so sanitize this register. | |
1618 | */ | |
1619 | cdctl = I915_READ(CDCLK_CTL); | |
1620 | /* | |
1621 | * Let's ignore the pipe field, since BIOS could have configured the | |
1622 | * dividers both synching to an active pipe, or asynchronously | |
1623 | * (PIPE_NONE). | |
1624 | */ | |
1625 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
1626 | ||
1627 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
1628 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); | |
1629 | ||
1630 | if (cdctl == expected) | |
1631 | /* All well; nothing to sanitize */ | |
1632 | return; | |
1633 | ||
1634 | sanitize: | |
1635 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
1636 | ||
1637 | /* force cdclk programming */ | |
1638 | dev_priv->cdclk.hw.cdclk = 0; | |
1639 | ||
1640 | /* force full PLL disable + enable */ | |
1641 | dev_priv->cdclk.hw.vco = -1; | |
1642 | } | |
1643 | ||
1644 | /** | |
1645 | * cnl_init_cdclk - Initialize CDCLK on CNL | |
1646 | * @dev_priv: i915 device | |
1647 | * | |
1648 | * Initialize CDCLK for CNL. This is generally | |
1649 | * done only during the display core initialization sequence, | |
1650 | * after which the DMC will take care of turning CDCLK off/on | |
1651 | * as needed. | |
1652 | */ | |
1653 | void cnl_init_cdclk(struct drm_i915_private *dev_priv) | |
1654 | { | |
1655 | struct intel_cdclk_state cdclk_state; | |
1656 | ||
1657 | cnl_sanitize_cdclk(dev_priv); | |
1658 | ||
1659 | if (dev_priv->cdclk.hw.cdclk != 0 && | |
1660 | dev_priv->cdclk.hw.vco != 0) | |
1661 | return; | |
1662 | ||
1663 | cdclk_state = dev_priv->cdclk.hw; | |
1664 | ||
d1999e9e | 1665 | cdclk_state.cdclk = cnl_calc_cdclk(0); |
d8d4a512 VS |
1666 | cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); |
1667 | ||
1668 | cnl_set_cdclk(dev_priv, &cdclk_state); | |
1669 | } | |
1670 | ||
1671 | /** | |
1672 | * cnl_uninit_cdclk - Uninitialize CDCLK on CNL | |
1673 | * @dev_priv: i915 device | |
1674 | * | |
1675 | * Uninitialize CDCLK for CNL. This is done only | |
1676 | * during the display core uninitialization sequence. | |
1677 | */ | |
1678 | void cnl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
1679 | { | |
1680 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; | |
1681 | ||
1682 | cdclk_state.cdclk = cdclk_state.ref; | |
1683 | cdclk_state.vco = 0; | |
1684 | ||
1685 | cnl_set_cdclk(dev_priv, &cdclk_state); | |
1686 | } | |
1687 | ||
49cd97a3 VS |
1688 | /** |
1689 | * intel_cdclk_state_compare - Determine if two CDCLK states differ | |
1690 | * @a: first CDCLK state | |
1691 | * @b: second CDCLK state | |
1692 | * | |
1693 | * Returns: | |
1694 | * True if the CDCLK states are identical, false if they differ. | |
1695 | */ | |
1696 | bool intel_cdclk_state_compare(const struct intel_cdclk_state *a, | |
1697 | const struct intel_cdclk_state *b) | |
1698 | { | |
1699 | return memcmp(a, b, sizeof(*a)) == 0; | |
7ff89ca2 VS |
1700 | } |
1701 | ||
b0587e4d VS |
1702 | /** |
1703 | * intel_set_cdclk - Push the CDCLK state to the hardware | |
1704 | * @dev_priv: i915 device | |
1705 | * @cdclk_state: new CDCLK state | |
1706 | * | |
1707 | * Program the hardware based on the passed in CDCLK state, | |
1708 | * if necessary. | |
1709 | */ | |
1710 | void intel_set_cdclk(struct drm_i915_private *dev_priv, | |
1711 | const struct intel_cdclk_state *cdclk_state) | |
1712 | { | |
1713 | if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state)) | |
1714 | return; | |
1715 | ||
1716 | if (WARN_ON_ONCE(!dev_priv->display.set_cdclk)) | |
1717 | return; | |
1718 | ||
1719 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n", | |
1720 | cdclk_state->cdclk, cdclk_state->vco, | |
1721 | cdclk_state->ref); | |
1722 | ||
1723 | dev_priv->display.set_cdclk(dev_priv, cdclk_state); | |
1724 | } | |
1725 | ||
d305e061 VS |
1726 | static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, |
1727 | int pixel_rate) | |
1728 | { | |
1729 | if (INTEL_GEN(dev_priv) >= 10) | |
1730 | /* | |
1731 | * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2) | |
1732 | * once DDI clock voltage requirements are | |
1733 | * handled correctly. | |
1734 | */ | |
1735 | return pixel_rate; | |
1736 | else if (IS_GEMINILAKE(dev_priv)) | |
1737 | /* | |
1738 | * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk | |
1739 | * as a temporary workaround. Use a higher cdclk instead. (Note that | |
1740 | * intel_compute_max_dotclk() limits the max pixel clock to 99% of max | |
1741 | * cdclk.) | |
1742 | */ | |
1743 | return DIV_ROUND_UP(pixel_rate * 100, 2 * 99); | |
1744 | else if (IS_GEN9(dev_priv) || | |
1745 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
1746 | return pixel_rate; | |
1747 | else if (IS_CHERRYVIEW(dev_priv)) | |
1748 | return DIV_ROUND_UP(pixel_rate * 100, 95); | |
1749 | else | |
1750 | return DIV_ROUND_UP(pixel_rate * 100, 90); | |
1751 | } | |
1752 | ||
1753 | int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) | |
7ff89ca2 VS |
1754 | { |
1755 | struct drm_i915_private *dev_priv = | |
1756 | to_i915(crtc_state->base.crtc->dev); | |
d305e061 VS |
1757 | int min_cdclk; |
1758 | ||
1759 | if (!crtc_state->base.enable) | |
1760 | return 0; | |
1761 | ||
1762 | min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); | |
7ff89ca2 VS |
1763 | |
1764 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
1765 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
d305e061 | 1766 | min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); |
7ff89ca2 | 1767 | |
78cfa580 PD |
1768 | /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, |
1769 | * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else | |
1770 | * there may be audio corruption or screen corruption." This cdclk | |
d305e061 | 1771 | * restriction for GLK is 316.8 MHz. |
7ff89ca2 VS |
1772 | */ |
1773 | if (intel_crtc_has_dp_encoder(crtc_state) && | |
1774 | crtc_state->has_audio && | |
1775 | crtc_state->port_clock >= 540000 && | |
78cfa580 | 1776 | crtc_state->lane_count == 4) { |
d305e061 VS |
1777 | if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { |
1778 | /* Display WA #1145: glk,cnl */ | |
1779 | min_cdclk = max(316800, min_cdclk); | |
1780 | } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) { | |
1781 | /* Display WA #1144: skl,bxt */ | |
1782 | min_cdclk = max(432000, min_cdclk); | |
1783 | } | |
78cfa580 | 1784 | } |
7ff89ca2 | 1785 | |
8cbeb06d PD |
1786 | /* According to BSpec, "The CD clock frequency must be at least twice |
1787 | * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. | |
8cbeb06d | 1788 | */ |
d305e061 VS |
1789 | if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) |
1790 | min_cdclk = max(2 * 96000, min_cdclk); | |
8cbeb06d | 1791 | |
9c61de4c VS |
1792 | if (min_cdclk > dev_priv->max_cdclk_freq) { |
1793 | DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n", | |
1794 | min_cdclk, dev_priv->max_cdclk_freq); | |
1795 | return -EINVAL; | |
1796 | } | |
1797 | ||
d305e061 | 1798 | return min_cdclk; |
7ff89ca2 VS |
1799 | } |
1800 | ||
d305e061 | 1801 | static int intel_compute_min_cdclk(struct drm_atomic_state *state) |
7ff89ca2 VS |
1802 | { |
1803 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
1804 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
d305e061 | 1805 | struct intel_crtc *crtc; |
7ff89ca2 | 1806 | struct intel_crtc_state *crtc_state; |
9c61de4c | 1807 | int min_cdclk, i; |
7ff89ca2 VS |
1808 | enum pipe pipe; |
1809 | ||
d305e061 VS |
1810 | memcpy(intel_state->min_cdclk, dev_priv->min_cdclk, |
1811 | sizeof(intel_state->min_cdclk)); | |
7ff89ca2 | 1812 | |
9c61de4c VS |
1813 | for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { |
1814 | min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); | |
1815 | if (min_cdclk < 0) | |
1816 | return min_cdclk; | |
1817 | ||
1818 | intel_state->min_cdclk[i] = min_cdclk; | |
1819 | } | |
7ff89ca2 | 1820 | |
9c61de4c | 1821 | min_cdclk = 0; |
7ff89ca2 | 1822 | for_each_pipe(dev_priv, pipe) |
d305e061 | 1823 | min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk); |
7ff89ca2 | 1824 | |
d305e061 | 1825 | return min_cdclk; |
7ff89ca2 VS |
1826 | } |
1827 | ||
1828 | static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state) | |
1829 | { | |
3d5dbb10 | 1830 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
9c61de4c VS |
1831 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
1832 | int min_cdclk, cdclk; | |
bb0f4aab | 1833 | |
9c61de4c VS |
1834 | min_cdclk = intel_compute_min_cdclk(state); |
1835 | if (min_cdclk < 0) | |
1836 | return min_cdclk; | |
7ff89ca2 | 1837 | |
9c61de4c | 1838 | cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); |
7ff89ca2 | 1839 | |
bb0f4aab VS |
1840 | intel_state->cdclk.logical.cdclk = cdclk; |
1841 | ||
1842 | if (!intel_state->active_crtcs) { | |
1843 | cdclk = vlv_calc_cdclk(dev_priv, 0); | |
1844 | ||
1845 | intel_state->cdclk.actual.cdclk = cdclk; | |
1846 | } else { | |
1847 | intel_state->cdclk.actual = | |
1848 | intel_state->cdclk.logical; | |
1849 | } | |
7ff89ca2 VS |
1850 | |
1851 | return 0; | |
1852 | } | |
1853 | ||
7ff89ca2 VS |
1854 | static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state) |
1855 | { | |
7ff89ca2 | 1856 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9c61de4c VS |
1857 | int min_cdclk, cdclk; |
1858 | ||
1859 | min_cdclk = intel_compute_min_cdclk(state); | |
1860 | if (min_cdclk < 0) | |
1861 | return min_cdclk; | |
7ff89ca2 VS |
1862 | |
1863 | /* | |
1864 | * FIXME should also account for plane ratio | |
1865 | * once 64bpp pixel formats are supported. | |
1866 | */ | |
d305e061 | 1867 | cdclk = bdw_calc_cdclk(min_cdclk); |
7ff89ca2 | 1868 | |
bb0f4aab VS |
1869 | intel_state->cdclk.logical.cdclk = cdclk; |
1870 | ||
1871 | if (!intel_state->active_crtcs) { | |
1872 | cdclk = bdw_calc_cdclk(0); | |
1873 | ||
1874 | intel_state->cdclk.actual.cdclk = cdclk; | |
1875 | } else { | |
1876 | intel_state->cdclk.actual = | |
1877 | intel_state->cdclk.logical; | |
1878 | } | |
7ff89ca2 VS |
1879 | |
1880 | return 0; | |
1881 | } | |
1882 | ||
7ff89ca2 VS |
1883 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
1884 | { | |
7ff89ca2 | 1885 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
9c61de4c VS |
1886 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
1887 | int min_cdclk, cdclk, vco; | |
1888 | ||
1889 | min_cdclk = intel_compute_min_cdclk(state); | |
1890 | if (min_cdclk < 0) | |
1891 | return min_cdclk; | |
bb0f4aab VS |
1892 | |
1893 | vco = intel_state->cdclk.logical.vco; | |
1894 | if (!vco) | |
1895 | vco = dev_priv->skl_preferred_vco_freq; | |
7ff89ca2 VS |
1896 | |
1897 | /* | |
1898 | * FIXME should also account for plane ratio | |
1899 | * once 64bpp pixel formats are supported. | |
1900 | */ | |
d305e061 | 1901 | cdclk = skl_calc_cdclk(min_cdclk, vco); |
7ff89ca2 | 1902 | |
bb0f4aab VS |
1903 | intel_state->cdclk.logical.vco = vco; |
1904 | intel_state->cdclk.logical.cdclk = cdclk; | |
1905 | ||
1906 | if (!intel_state->active_crtcs) { | |
1907 | cdclk = skl_calc_cdclk(0, vco); | |
1908 | ||
1909 | intel_state->cdclk.actual.vco = vco; | |
1910 | intel_state->cdclk.actual.cdclk = cdclk; | |
1911 | } else { | |
1912 | intel_state->cdclk.actual = | |
1913 | intel_state->cdclk.logical; | |
1914 | } | |
7ff89ca2 VS |
1915 | |
1916 | return 0; | |
1917 | } | |
1918 | ||
7ff89ca2 VS |
1919 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
1920 | { | |
1921 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
9c61de4c VS |
1922 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
1923 | int min_cdclk, cdclk, vco; | |
1924 | ||
1925 | min_cdclk = intel_compute_min_cdclk(state); | |
1926 | if (min_cdclk < 0) | |
1927 | return min_cdclk; | |
7ff89ca2 | 1928 | |
bb0f4aab | 1929 | if (IS_GEMINILAKE(dev_priv)) { |
d305e061 | 1930 | cdclk = glk_calc_cdclk(min_cdclk); |
bb0f4aab VS |
1931 | vco = glk_de_pll_vco(dev_priv, cdclk); |
1932 | } else { | |
d305e061 | 1933 | cdclk = bxt_calc_cdclk(min_cdclk); |
bb0f4aab VS |
1934 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
1935 | } | |
1936 | ||
bb0f4aab VS |
1937 | intel_state->cdclk.logical.vco = vco; |
1938 | intel_state->cdclk.logical.cdclk = cdclk; | |
7ff89ca2 VS |
1939 | |
1940 | if (!intel_state->active_crtcs) { | |
bb0f4aab | 1941 | if (IS_GEMINILAKE(dev_priv)) { |
7ff89ca2 | 1942 | cdclk = glk_calc_cdclk(0); |
bb0f4aab VS |
1943 | vco = glk_de_pll_vco(dev_priv, cdclk); |
1944 | } else { | |
7ff89ca2 | 1945 | cdclk = bxt_calc_cdclk(0); |
bb0f4aab VS |
1946 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
1947 | } | |
7ff89ca2 | 1948 | |
bb0f4aab VS |
1949 | intel_state->cdclk.actual.vco = vco; |
1950 | intel_state->cdclk.actual.cdclk = cdclk; | |
1951 | } else { | |
1952 | intel_state->cdclk.actual = | |
1953 | intel_state->cdclk.logical; | |
7ff89ca2 VS |
1954 | } |
1955 | ||
1956 | return 0; | |
1957 | } | |
1958 | ||
d1999e9e RV |
1959 | static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state) |
1960 | { | |
1961 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
9c61de4c VS |
1962 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
1963 | int min_cdclk, cdclk, vco; | |
1964 | ||
1965 | min_cdclk = intel_compute_min_cdclk(state); | |
1966 | if (min_cdclk < 0) | |
1967 | return min_cdclk; | |
d1999e9e | 1968 | |
d305e061 | 1969 | cdclk = cnl_calc_cdclk(min_cdclk); |
d1999e9e RV |
1970 | vco = cnl_cdclk_pll_vco(dev_priv, cdclk); |
1971 | ||
d1999e9e RV |
1972 | intel_state->cdclk.logical.vco = vco; |
1973 | intel_state->cdclk.logical.cdclk = cdclk; | |
1974 | ||
1975 | if (!intel_state->active_crtcs) { | |
1976 | cdclk = cnl_calc_cdclk(0); | |
1977 | vco = cnl_cdclk_pll_vco(dev_priv, cdclk); | |
1978 | ||
1979 | intel_state->cdclk.actual.vco = vco; | |
1980 | intel_state->cdclk.actual.cdclk = cdclk; | |
1981 | } else { | |
1982 | intel_state->cdclk.actual = | |
1983 | intel_state->cdclk.logical; | |
1984 | } | |
1985 | ||
1986 | return 0; | |
1987 | } | |
1988 | ||
7ff89ca2 VS |
1989 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
1990 | { | |
1991 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
1992 | ||
d305e061 VS |
1993 | if (INTEL_GEN(dev_priv) >= 10) |
1994 | /* | |
1995 | * FIXME: Allow '2 * max_cdclk_freq' | |
1996 | * once DDI clock voltage requirements are | |
1997 | * handled correctly. | |
1998 | */ | |
1999 | return max_cdclk_freq; | |
2000 | else if (IS_GEMINILAKE(dev_priv)) | |
97f55ca5 MC |
2001 | /* |
2002 | * FIXME: Limiting to 99% as a temporary workaround. See | |
d305e061 | 2003 | * intel_min_cdclk() for details. |
97f55ca5 MC |
2004 | */ |
2005 | return 2 * max_cdclk_freq * 99 / 100; | |
d305e061 VS |
2006 | else if (IS_GEN9(dev_priv) || |
2007 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
7ff89ca2 VS |
2008 | return max_cdclk_freq; |
2009 | else if (IS_CHERRYVIEW(dev_priv)) | |
2010 | return max_cdclk_freq*95/100; | |
2011 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
2012 | return 2*max_cdclk_freq*90/100; | |
2013 | else | |
2014 | return max_cdclk_freq*90/100; | |
2015 | } | |
2016 | ||
2017 | /** | |
2018 | * intel_update_max_cdclk - Determine the maximum support CDCLK frequency | |
2019 | * @dev_priv: i915 device | |
2020 | * | |
2021 | * Determine the maximum CDCLK frequency the platform supports, and also | |
2022 | * derive the maximum dot clock frequency the maximum CDCLK frequency | |
2023 | * allows. | |
2024 | */ | |
2025 | void intel_update_max_cdclk(struct drm_i915_private *dev_priv) | |
2026 | { | |
d1999e9e RV |
2027 | if (IS_CANNONLAKE(dev_priv)) { |
2028 | dev_priv->max_cdclk_freq = 528000; | |
2029 | } else if (IS_GEN9_BC(dev_priv)) { | |
7ff89ca2 VS |
2030 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
2031 | int max_cdclk, vco; | |
2032 | ||
2033 | vco = dev_priv->skl_preferred_vco_freq; | |
2034 | WARN_ON(vco != 8100000 && vco != 8640000); | |
2035 | ||
2036 | /* | |
2037 | * Use the lower (vco 8640) cdclk values as a | |
2038 | * first guess. skl_calc_cdclk() will correct it | |
2039 | * if the preferred vco is 8100 instead. | |
2040 | */ | |
2041 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
2042 | max_cdclk = 617143; | |
2043 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
2044 | max_cdclk = 540000; | |
2045 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
2046 | max_cdclk = 432000; | |
2047 | else | |
2048 | max_cdclk = 308571; | |
2049 | ||
2050 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
2051 | } else if (IS_GEMINILAKE(dev_priv)) { | |
2052 | dev_priv->max_cdclk_freq = 316800; | |
2053 | } else if (IS_BROXTON(dev_priv)) { | |
2054 | dev_priv->max_cdclk_freq = 624000; | |
2055 | } else if (IS_BROADWELL(dev_priv)) { | |
2056 | /* | |
2057 | * FIXME with extra cooling we can allow | |
2058 | * 540 MHz for ULX and 675 Mhz for ULT. | |
2059 | * How can we know if extra cooling is | |
2060 | * available? PCI ID, VTB, something else? | |
2061 | */ | |
2062 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
2063 | dev_priv->max_cdclk_freq = 450000; | |
2064 | else if (IS_BDW_ULX(dev_priv)) | |
2065 | dev_priv->max_cdclk_freq = 450000; | |
2066 | else if (IS_BDW_ULT(dev_priv)) | |
2067 | dev_priv->max_cdclk_freq = 540000; | |
2068 | else | |
2069 | dev_priv->max_cdclk_freq = 675000; | |
2070 | } else if (IS_CHERRYVIEW(dev_priv)) { | |
2071 | dev_priv->max_cdclk_freq = 320000; | |
2072 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
2073 | dev_priv->max_cdclk_freq = 400000; | |
2074 | } else { | |
2075 | /* otherwise assume cdclk is fixed */ | |
49cd97a3 | 2076 | dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; |
7ff89ca2 VS |
2077 | } |
2078 | ||
2079 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); | |
2080 | ||
2081 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", | |
2082 | dev_priv->max_cdclk_freq); | |
2083 | ||
2084 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
2085 | dev_priv->max_dotclk_freq); | |
2086 | } | |
2087 | ||
2088 | /** | |
2089 | * intel_update_cdclk - Determine the current CDCLK frequency | |
2090 | * @dev_priv: i915 device | |
2091 | * | |
2092 | * Determine the current CDCLK frequency. | |
2093 | */ | |
2094 | void intel_update_cdclk(struct drm_i915_private *dev_priv) | |
2095 | { | |
49cd97a3 | 2096 | dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); |
7ff89ca2 | 2097 | |
49cd97a3 VS |
2098 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
2099 | dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco, | |
2100 | dev_priv->cdclk.hw.ref); | |
7ff89ca2 VS |
2101 | |
2102 | /* | |
2103 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): | |
2104 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
2105 | * of cdclk that generates 4MHz reference clock freq which is used to | |
2106 | * generate GMBus clock. This will vary with the cdclk freq. | |
2107 | */ | |
2108 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2109 | I915_WRITE(GMBUSFREQ_VLV, | |
49cd97a3 | 2110 | DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); |
7ff89ca2 VS |
2111 | } |
2112 | ||
9d81a997 RV |
2113 | static int cnp_rawclk(struct drm_i915_private *dev_priv) |
2114 | { | |
2115 | u32 rawclk; | |
2116 | int divider, fraction; | |
2117 | ||
2118 | if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { | |
2119 | /* 24 MHz */ | |
2120 | divider = 24000; | |
2121 | fraction = 0; | |
2122 | } else { | |
2123 | /* 19.2 MHz */ | |
2124 | divider = 19000; | |
2125 | fraction = 200; | |
2126 | } | |
2127 | ||
2128 | rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1); | |
2129 | if (fraction) | |
2130 | rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000, | |
2131 | fraction) - 1); | |
2132 | ||
2133 | I915_WRITE(PCH_RAWCLK_FREQ, rawclk); | |
2134 | return divider + fraction; | |
2135 | } | |
2136 | ||
7ff89ca2 VS |
2137 | static int pch_rawclk(struct drm_i915_private *dev_priv) |
2138 | { | |
2139 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; | |
2140 | } | |
2141 | ||
2142 | static int vlv_hrawclk(struct drm_i915_private *dev_priv) | |
2143 | { | |
2144 | /* RAWCLK_FREQ_VLV register updated from power well code */ | |
2145 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", | |
2146 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
2147 | } | |
2148 | ||
2149 | static int g4x_hrawclk(struct drm_i915_private *dev_priv) | |
2150 | { | |
2151 | uint32_t clkcfg; | |
2152 | ||
2153 | /* hrawclock is 1/4 the FSB frequency */ | |
2154 | clkcfg = I915_READ(CLKCFG); | |
2155 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
2156 | case CLKCFG_FSB_400: | |
2157 | return 100000; | |
2158 | case CLKCFG_FSB_533: | |
2159 | return 133333; | |
2160 | case CLKCFG_FSB_667: | |
2161 | return 166667; | |
2162 | case CLKCFG_FSB_800: | |
2163 | return 200000; | |
2164 | case CLKCFG_FSB_1067: | |
6f38123e | 2165 | case CLKCFG_FSB_1067_ALT: |
7ff89ca2 VS |
2166 | return 266667; |
2167 | case CLKCFG_FSB_1333: | |
6f38123e | 2168 | case CLKCFG_FSB_1333_ALT: |
7ff89ca2 | 2169 | return 333333; |
7ff89ca2 VS |
2170 | default: |
2171 | return 133333; | |
2172 | } | |
2173 | } | |
2174 | ||
2175 | /** | |
2176 | * intel_update_rawclk - Determine the current RAWCLK frequency | |
2177 | * @dev_priv: i915 device | |
2178 | * | |
2179 | * Determine the current RAWCLK frequency. RAWCLK is a fixed | |
2180 | * frequency clock so this needs to done only once. | |
2181 | */ | |
2182 | void intel_update_rawclk(struct drm_i915_private *dev_priv) | |
2183 | { | |
9d81a997 RV |
2184 | |
2185 | if (HAS_PCH_CNP(dev_priv)) | |
2186 | dev_priv->rawclk_freq = cnp_rawclk(dev_priv); | |
2187 | else if (HAS_PCH_SPLIT(dev_priv)) | |
7ff89ca2 VS |
2188 | dev_priv->rawclk_freq = pch_rawclk(dev_priv); |
2189 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2190 | dev_priv->rawclk_freq = vlv_hrawclk(dev_priv); | |
2191 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
2192 | dev_priv->rawclk_freq = g4x_hrawclk(dev_priv); | |
2193 | else | |
2194 | /* no rawclk on other platforms, or no need to know it */ | |
2195 | return; | |
2196 | ||
2197 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
2198 | } | |
2199 | ||
2200 | /** | |
2201 | * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks | |
2202 | * @dev_priv: i915 device | |
2203 | */ | |
2204 | void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) | |
2205 | { | |
b0587e4d VS |
2206 | if (IS_CHERRYVIEW(dev_priv)) { |
2207 | dev_priv->display.set_cdclk = chv_set_cdclk; | |
2208 | dev_priv->display.modeset_calc_cdclk = | |
2209 | vlv_modeset_calc_cdclk; | |
2210 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
2211 | dev_priv->display.set_cdclk = vlv_set_cdclk; | |
7ff89ca2 VS |
2212 | dev_priv->display.modeset_calc_cdclk = |
2213 | vlv_modeset_calc_cdclk; | |
2214 | } else if (IS_BROADWELL(dev_priv)) { | |
b0587e4d | 2215 | dev_priv->display.set_cdclk = bdw_set_cdclk; |
7ff89ca2 VS |
2216 | dev_priv->display.modeset_calc_cdclk = |
2217 | bdw_modeset_calc_cdclk; | |
2218 | } else if (IS_GEN9_LP(dev_priv)) { | |
b0587e4d | 2219 | dev_priv->display.set_cdclk = bxt_set_cdclk; |
7ff89ca2 VS |
2220 | dev_priv->display.modeset_calc_cdclk = |
2221 | bxt_modeset_calc_cdclk; | |
2222 | } else if (IS_GEN9_BC(dev_priv)) { | |
b0587e4d | 2223 | dev_priv->display.set_cdclk = skl_set_cdclk; |
7ff89ca2 VS |
2224 | dev_priv->display.modeset_calc_cdclk = |
2225 | skl_modeset_calc_cdclk; | |
d1999e9e RV |
2226 | } else if (IS_CANNONLAKE(dev_priv)) { |
2227 | dev_priv->display.set_cdclk = cnl_set_cdclk; | |
2228 | dev_priv->display.modeset_calc_cdclk = | |
2229 | cnl_modeset_calc_cdclk; | |
7ff89ca2 VS |
2230 | } |
2231 | ||
945f2672 VS |
2232 | if (IS_CANNONLAKE(dev_priv)) |
2233 | dev_priv->display.get_cdclk = cnl_get_cdclk; | |
2234 | else if (IS_GEN9_BC(dev_priv)) | |
7ff89ca2 VS |
2235 | dev_priv->display.get_cdclk = skl_get_cdclk; |
2236 | else if (IS_GEN9_LP(dev_priv)) | |
2237 | dev_priv->display.get_cdclk = bxt_get_cdclk; | |
2238 | else if (IS_BROADWELL(dev_priv)) | |
2239 | dev_priv->display.get_cdclk = bdw_get_cdclk; | |
2240 | else if (IS_HASWELL(dev_priv)) | |
2241 | dev_priv->display.get_cdclk = hsw_get_cdclk; | |
2242 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2243 | dev_priv->display.get_cdclk = vlv_get_cdclk; | |
2244 | else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
2245 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
2246 | else if (IS_GEN5(dev_priv)) | |
2247 | dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; | |
2248 | else if (IS_GM45(dev_priv)) | |
2249 | dev_priv->display.get_cdclk = gm45_get_cdclk; | |
6b9e441d | 2250 | else if (IS_G45(dev_priv)) |
7ff89ca2 VS |
2251 | dev_priv->display.get_cdclk = g33_get_cdclk; |
2252 | else if (IS_I965GM(dev_priv)) | |
2253 | dev_priv->display.get_cdclk = i965gm_get_cdclk; | |
2254 | else if (IS_I965G(dev_priv)) | |
2255 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
2256 | else if (IS_PINEVIEW(dev_priv)) | |
2257 | dev_priv->display.get_cdclk = pnv_get_cdclk; | |
2258 | else if (IS_G33(dev_priv)) | |
2259 | dev_priv->display.get_cdclk = g33_get_cdclk; | |
2260 | else if (IS_I945GM(dev_priv)) | |
2261 | dev_priv->display.get_cdclk = i945gm_get_cdclk; | |
2262 | else if (IS_I945G(dev_priv)) | |
2263 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
2264 | else if (IS_I915GM(dev_priv)) | |
2265 | dev_priv->display.get_cdclk = i915gm_get_cdclk; | |
2266 | else if (IS_I915G(dev_priv)) | |
2267 | dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; | |
2268 | else if (IS_I865G(dev_priv)) | |
2269 | dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; | |
2270 | else if (IS_I85X(dev_priv)) | |
2271 | dev_priv->display.get_cdclk = i85x_get_cdclk; | |
2272 | else if (IS_I845G(dev_priv)) | |
2273 | dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; | |
2274 | else { /* 830 */ | |
2275 | WARN(!IS_I830(dev_priv), | |
2276 | "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
2277 | dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; | |
2278 | } | |
2279 | } |