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[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_cdclk.c
CommitLineData
7ff89ca2
VS		 1/*
2 * Copyright © 2006-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include "intel_drv.h"
25
26/**
27 * DOC: CDCLK / RAWCLK
28 *
29 * The display engine uses several different clocks to do its work. There
30 * are two main clocks involved that aren't directly related to the actual
31 * pixel clock or any symbol/bit clock of the actual output port. These
32 * are the core display clock (CDCLK) and RAWCLK.
33 *
34 * CDCLK clocks most of the display pipe logic, and thus its frequency
35 * must be high enough to support the rate at which pixels are flowing
36 * through the pipes. Downscaling must also be accounted as that increases
37 * the effective pixel rate.
38 *
39 * On several platforms the CDCLK frequency can be changed dynamically
40 * to minimize power consumption for a given display configuration.
41 * Typically changes to the CDCLK frequency require all the display pipes
42 * to be shut down while the frequency is being changed.
43 *
44 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
45 * DMC will not change the active CDCLK frequency however, so that part
46 * will still be performed by the driver directly.
47 *
48 * RAWCLK is a fixed frequency clock, often used by various auxiliary
49 * blocks such as AUX CH or backlight PWM. Hence the only thing we
50 * really need to know about RAWCLK is its frequency so that various
51 * dividers can be programmed correctly.
52 */
53
49cd97a3
VS		 54static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
55 struct intel_cdclk_state *cdclk_state)
7ff89ca2 56{
49cd97a3 57 cdclk_state->cdclk = 133333;
7ff89ca2
VS		 58}
59
49cd97a3
VS		 60static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
61 struct intel_cdclk_state *cdclk_state)
7ff89ca2 62{
49cd97a3 63 cdclk_state->cdclk = 200000;
7ff89ca2
VS		 64}
65
49cd97a3
VS		 66static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
67 struct intel_cdclk_state *cdclk_state)
7ff89ca2 68{
49cd97a3 69 cdclk_state->cdclk = 266667;
7ff89ca2
VS		 70}
71
49cd97a3
VS		 72static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
73 struct intel_cdclk_state *cdclk_state)
7ff89ca2 74{
49cd97a3 75 cdclk_state->cdclk = 333333;
7ff89ca2
VS		 76}
77
49cd97a3
VS		 78static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
79 struct intel_cdclk_state *cdclk_state)
7ff89ca2 80{
49cd97a3 81 cdclk_state->cdclk = 400000;
7ff89ca2
VS		 82}
83
49cd97a3
VS		 84static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
85 struct intel_cdclk_state *cdclk_state)
7ff89ca2 86{
49cd97a3 87 cdclk_state->cdclk = 450000;
7ff89ca2
VS		 88}
89
49cd97a3
VS		 90static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
91 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 92{
93 struct pci_dev *pdev = dev_priv->drm.pdev;
94 u16 hpllcc = 0;
95
96 /*
97 * 852GM/852GMV only supports 133 MHz and the HPLLCC
98 * encoding is different :(
99 * FIXME is this the right way to detect 852GM/852GMV?
100 */
49cd97a3
VS		 101 if (pdev->revision == 0x1) {
102 cdclk_state->cdclk = 133333;
103 return;
104 }
7ff89ca2
VS		 105
106 pci_bus_read_config_word(pdev->bus,
107 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
108
109 /* Assume that the hardware is in the high speed state. This
110 * should be the default.
111 */
112 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
113 case GC_CLOCK_133_200:
114 case GC_CLOCK_133_200_2:
115 case GC_CLOCK_100_200:
49cd97a3
VS		 116 cdclk_state->cdclk = 200000;
117 break;
7ff89ca2 118 case GC_CLOCK_166_250:
49cd97a3
VS		 119 cdclk_state->cdclk = 250000;
120 break;
7ff89ca2 121 case GC_CLOCK_100_133:
49cd97a3
VS		 122 cdclk_state->cdclk = 133333;
123 break;
7ff89ca2
VS		 124 case GC_CLOCK_133_266:
125 case GC_CLOCK_133_266_2:
126 case GC_CLOCK_166_266:
49cd97a3
VS		 127 cdclk_state->cdclk = 266667;
128 break;
7ff89ca2 129 }
7ff89ca2
VS		 130}
131
49cd97a3
VS		 132static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
133 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 134{
135 struct pci_dev *pdev = dev_priv->drm.pdev;
136 u16 gcfgc = 0;
137
138 pci_read_config_word(pdev, GCFGC, &gcfgc);
139
49cd97a3
VS		 140 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
141 cdclk_state->cdclk = 133333;
142 return;
143 }
7ff89ca2
VS		 144
145 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
146 case GC_DISPLAY_CLOCK_333_320_MHZ:
49cd97a3
VS		 147 cdclk_state->cdclk = 333333;
148 break;
7ff89ca2
VS		 149 default:
150 case GC_DISPLAY_CLOCK_190_200_MHZ:
49cd97a3
VS		 151 cdclk_state->cdclk = 190000;
152 break;
7ff89ca2
VS		 153 }
154}
155
49cd97a3
VS		 156static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
157 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 158{
159 struct pci_dev *pdev = dev_priv->drm.pdev;
160 u16 gcfgc = 0;
161
162 pci_read_config_word(pdev, GCFGC, &gcfgc);
163
49cd97a3
VS		 164 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
165 cdclk_state->cdclk = 133333;
166 return;
167 }
7ff89ca2
VS		 168
169 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
170 case GC_DISPLAY_CLOCK_333_320_MHZ:
49cd97a3
VS		 171 cdclk_state->cdclk = 320000;
172 break;
7ff89ca2
VS		 173 default:
174 case GC_DISPLAY_CLOCK_190_200_MHZ:
49cd97a3
VS		 175 cdclk_state->cdclk = 200000;
176 break;
7ff89ca2
VS		 177 }
178}
179
180static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
181{
182 static const unsigned int blb_vco[8] = {
183 [0] = 3200000,
184 [1] = 4000000,
185 [2] = 5333333,
186 [3] = 4800000,
187 [4] = 6400000,
188 };
189 static const unsigned int pnv_vco[8] = {
190 [0] = 3200000,
191 [1] = 4000000,
192 [2] = 5333333,
193 [3] = 4800000,
194 [4] = 2666667,
195 };
196 static const unsigned int cl_vco[8] = {
197 [0] = 3200000,
198 [1] = 4000000,
199 [2] = 5333333,
200 [3] = 6400000,
201 [4] = 3333333,
202 [5] = 3566667,
203 [6] = 4266667,
204 };
205 static const unsigned int elk_vco[8] = {
206 [0] = 3200000,
207 [1] = 4000000,
208 [2] = 5333333,
209 [3] = 4800000,
210 };
211 static const unsigned int ctg_vco[8] = {
212 [0] = 3200000,
213 [1] = 4000000,
214 [2] = 5333333,
215 [3] = 6400000,
216 [4] = 2666667,
217 [5] = 4266667,
218 };
219 const unsigned int *vco_table;
220 unsigned int vco;
221 uint8_t tmp = 0;
222
223 /* FIXME other chipsets? */
224 if (IS_GM45(dev_priv))
225 vco_table = ctg_vco;
6b9e441d 226 else if (IS_G45(dev_priv))
7ff89ca2
VS		 227 vco_table = elk_vco;
228 else if (IS_I965GM(dev_priv))
229 vco_table = cl_vco;
230 else if (IS_PINEVIEW(dev_priv))
231 vco_table = pnv_vco;
232 else if (IS_G33(dev_priv))
233 vco_table = blb_vco;
234 else
235 return 0;
236
237 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
238
239 vco = vco_table[tmp & 0x7];
240 if (vco == 0)
241 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
242 else
243 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
244
245 return vco;
246}
247
49cd97a3
VS		 248static void g33_get_cdclk(struct drm_i915_private *dev_priv,
249 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 250{
251 struct pci_dev *pdev = dev_priv->drm.pdev;
252 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
253 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
254 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
255 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
256 const uint8_t *div_table;
49cd97a3 257 unsigned int cdclk_sel;
7ff89ca2
VS		 258 uint16_t tmp = 0;
259
49cd97a3
VS		 260 cdclk_state->vco = intel_hpll_vco(dev_priv);
261
7ff89ca2
VS		 262 pci_read_config_word(pdev, GCFGC, &tmp);
263
264 cdclk_sel = (tmp >> 4) & 0x7;
265
266 if (cdclk_sel >= ARRAY_SIZE(div_3200))
267 goto fail;
268
49cd97a3 269 switch (cdclk_state->vco) {
7ff89ca2
VS		 270 case 3200000:
271 div_table = div_3200;
272 break;
273 case 4000000:
274 div_table = div_4000;
275 break;
276 case 4800000:
277 div_table = div_4800;
278 break;
279 case 5333333:
280 div_table = div_5333;
281 break;
282 default:
283 goto fail;
284 }
285
49cd97a3
VS		 286 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
287 div_table[cdclk_sel]);
288 return;
7ff89ca2
VS		 289
290fail:
291 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
49cd97a3
VS		 292 cdclk_state->vco, tmp);
293 cdclk_state->cdclk = 190476;
7ff89ca2
VS		 294}
295
49cd97a3
VS		 296static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
297 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 298{
299 struct pci_dev *pdev = dev_priv->drm.pdev;
300 u16 gcfgc = 0;
301
302 pci_read_config_word(pdev, GCFGC, &gcfgc);
303
304 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
305 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
49cd97a3
VS		 306 cdclk_state->cdclk = 266667;
307 break;
7ff89ca2 308 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
49cd97a3
VS		 309 cdclk_state->cdclk = 333333;
310 break;
7ff89ca2 311 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
49cd97a3
VS		 312 cdclk_state->cdclk = 444444;
313 break;
7ff89ca2 314 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
49cd97a3
VS		 315 cdclk_state->cdclk = 200000;
316 break;
7ff89ca2
VS		 317 default:
318 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
f0d759f0 319 /* fall through */
7ff89ca2 320 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
49cd97a3
VS		 321 cdclk_state->cdclk = 133333;
322 break;
7ff89ca2 323 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
49cd97a3
VS		 324 cdclk_state->cdclk = 166667;
325 break;
7ff89ca2
VS		 326 }
327}
328
49cd97a3
VS		 329static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
330 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 331{
332 struct pci_dev *pdev = dev_priv->drm.pdev;
333 static const uint8_t div_3200[] = { 16, 10, 8 };
334 static const uint8_t div_4000[] = { 20, 12, 10 };
335 static const uint8_t div_5333[] = { 24, 16, 14 };
336 const uint8_t *div_table;
49cd97a3 337 unsigned int cdclk_sel;
7ff89ca2
VS		 338 uint16_t tmp = 0;
339
49cd97a3
VS		 340 cdclk_state->vco = intel_hpll_vco(dev_priv);
341
7ff89ca2
VS		 342 pci_read_config_word(pdev, GCFGC, &tmp);
343
344 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
345
346 if (cdclk_sel >= ARRAY_SIZE(div_3200))
347 goto fail;
348
49cd97a3 349 switch (cdclk_state->vco) {
7ff89ca2
VS		 350 case 3200000:
351 div_table = div_3200;
352 break;
353 case 4000000:
354 div_table = div_4000;
355 break;
356 case 5333333:
357 div_table = div_5333;
358 break;
359 default:
360 goto fail;
361 }
362
49cd97a3
VS		 363 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
364 div_table[cdclk_sel]);
365 return;
7ff89ca2
VS		 366
367fail:
368 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
49cd97a3
VS		 369 cdclk_state->vco, tmp);
370 cdclk_state->cdclk = 200000;
7ff89ca2
VS		 371}
372
49cd97a3
VS		 373static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
374 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 375{
376 struct pci_dev *pdev = dev_priv->drm.pdev;
49cd97a3 377 unsigned int cdclk_sel;
7ff89ca2
VS		 378 uint16_t tmp = 0;
379
49cd97a3
VS		 380 cdclk_state->vco = intel_hpll_vco(dev_priv);
381
7ff89ca2
VS		 382 pci_read_config_word(pdev, GCFGC, &tmp);
383
384 cdclk_sel = (tmp >> 12) & 0x1;
385
49cd97a3 386 switch (cdclk_state->vco) {
7ff89ca2
VS		 387 case 2666667:
388 case 4000000:
389 case 5333333:
49cd97a3
VS		 390 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
391 break;
7ff89ca2 392 case 3200000:
49cd97a3
VS		 393 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
394 break;
7ff89ca2
VS		 395 default:
396 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
49cd97a3
VS		 397 cdclk_state->vco, tmp);
398 cdclk_state->cdclk = 222222;
399 break;
7ff89ca2
VS		 400 }
401}
402
49cd97a3
VS		 403static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
404 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 405{
406 uint32_t lcpll = I915_READ(LCPLL_CTL);
407 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
408
409 if (lcpll & LCPLL_CD_SOURCE_FCLK)
49cd97a3 410 cdclk_state->cdclk = 800000;
7ff89ca2 411 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
49cd97a3 412 cdclk_state->cdclk = 450000;
7ff89ca2 413 else if (freq == LCPLL_CLK_FREQ_450)
49cd97a3 414 cdclk_state->cdclk = 450000;
7ff89ca2 415 else if (IS_HSW_ULT(dev_priv))
49cd97a3 416 cdclk_state->cdclk = 337500;
7ff89ca2 417 else
49cd97a3 418 cdclk_state->cdclk = 540000;
7ff89ca2
VS		 419}
420
d305e061 421static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
7ff89ca2
VS		 422{
423 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
424 333333 : 320000;
7ff89ca2
VS		 425
426 /*
427 * We seem to get an unstable or solid color picture at 200MHz.
428 * Not sure what's wrong. For now use 200MHz only when all pipes
429 * are off.
430 */
d305e061 431 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
7ff89ca2 432 return 400000;
d305e061 433 else if (min_cdclk > 266667)
7ff89ca2 434 return freq_320;
d305e061 435 else if (min_cdclk > 0)
7ff89ca2
VS		 436 return 266667;
437 else
438 return 200000;
439}
440
999c5766
VS		 441static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
442{
443 if (IS_VALLEYVIEW(dev_priv)) {
444 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
445 return 2;
446 else if (cdclk >= 266667)
447 return 1;
448 else
449 return 0;
450 } else {
451 /*
452 * Specs are full of misinformation, but testing on actual
453 * hardware has shown that we just need to write the desired
454 * CCK divider into the Punit register.
455 */
456 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
457 }
458}
459
49cd97a3
VS		 460static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
461 struct intel_cdclk_state *cdclk_state)
7ff89ca2 462{
999c5766
VS		 463 u32 val;
464
49cd97a3
VS		 465 cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
466 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
467 CCK_DISPLAY_CLOCK_CONTROL,
468 cdclk_state->vco);
999c5766
VS		 469
470 mutex_lock(&dev_priv->pcu_lock);
471 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
472 mutex_unlock(&dev_priv->pcu_lock);
473
474 if (IS_VALLEYVIEW(dev_priv))
475 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
476 DSPFREQGUAR_SHIFT;
477 else
478 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
479 DSPFREQGUAR_SHIFT_CHV;
7ff89ca2
VS		 480}
481
482static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
483{
484 unsigned int credits, default_credits;
485
486 if (IS_CHERRYVIEW(dev_priv))
487 default_credits = PFI_CREDIT(12);
488 else
489 default_credits = PFI_CREDIT(8);
490
49cd97a3 491 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
7ff89ca2
VS		 492 /* CHV suggested value is 31 or 63 */
493 if (IS_CHERRYVIEW(dev_priv))
494 credits = PFI_CREDIT_63;
495 else
496 credits = PFI_CREDIT(15);
497 } else {
498 credits = default_credits;
499 }
500
501 /*
502 * WA - write default credits before re-programming
503 * FIXME: should we also set the resend bit here?
504 */
505 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
506 default_credits);
507
508 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
509 credits | PFI_CREDIT_RESEND);
510
511 /*
512 * FIXME is this guaranteed to clear
513 * immediately or should we poll for it?
514 */
515 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
516}
517
83c5fda7
VS		 518static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
519 const struct intel_cdclk_state *cdclk_state)
7ff89ca2 520{
83c5fda7 521 int cdclk = cdclk_state->cdclk;
999c5766 522 u32 val, cmd = cdclk_state->voltage_level;
7ff89ca2 523
0c9f353f
VS		 524 switch (cdclk) {
525 case 400000:
526 case 333333:
527 case 320000:
528 case 266667:
529 case 200000:
530 break;
531 default:
532 MISSING_CASE(cdclk);
533 return;
534 }
535
886015a0
GKB		 536 /* There are cases where we can end up here with power domains
537 * off and a CDCLK frequency other than the minimum, like when
538 * issuing a modeset without actually changing any display after
539 * a system suspend. So grab the PIPE-A domain, which covers
540 * the HW blocks needed for the following programming.
541 */
542 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
543
9f817501 544 mutex_lock(&dev_priv->pcu_lock);
7ff89ca2
VS		 545 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
546 val &= ~DSPFREQGUAR_MASK;
547 val |= (cmd << DSPFREQGUAR_SHIFT);
548 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
549 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
550 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
551 50)) {
552 DRM_ERROR("timed out waiting for CDclk change\n");
553 }
9f817501 554 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 555
556 mutex_lock(&dev_priv->sb_lock);
557
558 if (cdclk == 400000) {
559 u32 divider;
560
561 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
562 cdclk) - 1;
563
564 /* adjust cdclk divider */
565 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
566 val &= ~CCK_FREQUENCY_VALUES;
567 val |= divider;
568 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
569
570 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
571 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
572 50))
573 DRM_ERROR("timed out waiting for CDclk change\n");
574 }
575
576 /* adjust self-refresh exit latency value */
577 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
578 val &= ~0x7f;
579
580 /*
581 * For high bandwidth configs, we set a higher latency in the bunit
582 * so that the core display fetch happens in time to avoid underruns.
583 */
584 if (cdclk == 400000)
585 val |= 4500 / 250; /* 4.5 usec */
586 else
587 val |= 3000 / 250; /* 3.0 usec */
588 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
589
590 mutex_unlock(&dev_priv->sb_lock);
591
592 intel_update_cdclk(dev_priv);
1a5301a5
VS		 593
594 vlv_program_pfi_credits(dev_priv);
886015a0
GKB		 595
596 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
7ff89ca2
VS		 597}
598
83c5fda7
VS		 599static void chv_set_cdclk(struct drm_i915_private *dev_priv,
600 const struct intel_cdclk_state *cdclk_state)
7ff89ca2 601{
83c5fda7 602 int cdclk = cdclk_state->cdclk;
999c5766 603 u32 val, cmd = cdclk_state->voltage_level;
7ff89ca2 604
7ff89ca2
VS		 605 switch (cdclk) {
606 case 333333:
607 case 320000:
608 case 266667:
609 case 200000:
610 break;
611 default:
612 MISSING_CASE(cdclk);
613 return;
614 }
615
886015a0
GKB		 616 /* There are cases where we can end up here with power domains
617 * off and a CDCLK frequency other than the minimum, like when
618 * issuing a modeset without actually changing any display after
619 * a system suspend. So grab the PIPE-A domain, which covers
620 * the HW blocks needed for the following programming.
621 */
622 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
623
9f817501 624 mutex_lock(&dev_priv->pcu_lock);
7ff89ca2
VS		 625 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
626 val &= ~DSPFREQGUAR_MASK_CHV;
627 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
628 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
629 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
630 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
631 50)) {
632 DRM_ERROR("timed out waiting for CDclk change\n");
633 }
9f817501 634 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 635
636 intel_update_cdclk(dev_priv);
1a5301a5
VS		 637
638 vlv_program_pfi_credits(dev_priv);
886015a0
GKB		 639
640 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
7ff89ca2
VS		 641}
642
d305e061 643static int bdw_calc_cdclk(int min_cdclk)
7ff89ca2 644{
d305e061 645 if (min_cdclk > 540000)
7ff89ca2 646 return 675000;
d305e061 647 else if (min_cdclk > 450000)
7ff89ca2 648 return 540000;
d305e061 649 else if (min_cdclk > 337500)
7ff89ca2
VS		 650 return 450000;
651 else
652 return 337500;
653}
654
d7ffaeef
VS		 655static u8 bdw_calc_voltage_level(int cdclk)
656{
657 switch (cdclk) {
658 default:
659 case 337500:
660 return 2;
661 case 450000:
662 return 0;
663 case 540000:
664 return 1;
665 case 675000:
666 return 3;
667 }
668}
669
49cd97a3
VS		 670static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
671 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 672{
673 uint32_t lcpll = I915_READ(LCPLL_CTL);
674 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
675
676 if (lcpll & LCPLL_CD_SOURCE_FCLK)
49cd97a3 677 cdclk_state->cdclk = 800000;
7ff89ca2 678 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
49cd97a3 679 cdclk_state->cdclk = 450000;
7ff89ca2 680 else if (freq == LCPLL_CLK_FREQ_450)
49cd97a3 681 cdclk_state->cdclk = 450000;
7ff89ca2 682 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
49cd97a3 683 cdclk_state->cdclk = 540000;
7ff89ca2 684 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
49cd97a3 685 cdclk_state->cdclk = 337500;
7ff89ca2 686 else
49cd97a3 687 cdclk_state->cdclk = 675000;
d7ffaeef
VS		 688
689 /*
690 * Can't read this out :( Let's assume it's
691 * at least what the CDCLK frequency requires.
692 */
693 cdclk_state->voltage_level =
694 bdw_calc_voltage_level(cdclk_state->cdclk);
7ff89ca2
VS		 695}
696
83c5fda7
VS		 697static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
698 const struct intel_cdclk_state *cdclk_state)
7ff89ca2 699{
83c5fda7 700 int cdclk = cdclk_state->cdclk;
d7ffaeef 701 uint32_t val;
7ff89ca2
VS		 702 int ret;
703
704 if (WARN((I915_READ(LCPLL_CTL) &
705 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
706 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
707 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
708 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
709 "trying to change cdclk frequency with cdclk not enabled\n"))
710 return;
711
9f817501 712 mutex_lock(&dev_priv->pcu_lock);
7ff89ca2
VS		 713 ret = sandybridge_pcode_write(dev_priv,
714 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9f817501 715 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 716 if (ret) {
717 DRM_ERROR("failed to inform pcode about cdclk change\n");
718 return;
719 }
720
721 val = I915_READ(LCPLL_CTL);
722 val |= LCPLL_CD_SOURCE_FCLK;
723 I915_WRITE(LCPLL_CTL, val);
724
3164888a
ML		 725 /*
726 * According to the spec, it should be enough to poll for this 1 us.
727 * However, extensive testing shows that this can take longer.
728 */
7ff89ca2 729 if (wait_for_us(I915_READ(LCPLL_CTL) &
3164888a 730 LCPLL_CD_SOURCE_FCLK_DONE, 100))
7ff89ca2
VS		 731 DRM_ERROR("Switching to FCLK failed\n");
732
733 val = I915_READ(LCPLL_CTL);
734 val &= ~LCPLL_CLK_FREQ_MASK;
735
736 switch (cdclk) {
2b58417f
VS		 737 default:
738 MISSING_CASE(cdclk);
739 /* fall through */
740 case 337500:
741 val |= LCPLL_CLK_FREQ_337_5_BDW;
2b58417f 742 break;
7ff89ca2
VS		 743 case 450000:
744 val |= LCPLL_CLK_FREQ_450;
7ff89ca2
VS		 745 break;
746 case 540000:
747 val |= LCPLL_CLK_FREQ_54O_BDW;
7ff89ca2 748 break;
7ff89ca2
VS		 749 case 675000:
750 val |= LCPLL_CLK_FREQ_675_BDW;
7ff89ca2 751 break;
7ff89ca2
VS		 752 }
753
754 I915_WRITE(LCPLL_CTL, val);
755
756 val = I915_READ(LCPLL_CTL);
757 val &= ~LCPLL_CD_SOURCE_FCLK;
758 I915_WRITE(LCPLL_CTL, val);
759
760 if (wait_for_us((I915_READ(LCPLL_CTL) &
761 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
762 DRM_ERROR("Switching back to LCPLL failed\n");
763
9f817501 764 mutex_lock(&dev_priv->pcu_lock);
d7ffaeef
VS		 765 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
766 cdclk_state->voltage_level);
9f817501 767 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 768
769 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
770
771 intel_update_cdclk(dev_priv);
7ff89ca2
VS		 772}
773
d305e061 774static int skl_calc_cdclk(int min_cdclk, int vco)
7ff89ca2
VS		 775{
776 if (vco == 8640000) {
d305e061 777 if (min_cdclk > 540000)
7ff89ca2 778 return 617143;
d305e061 779 else if (min_cdclk > 432000)
7ff89ca2 780 return 540000;
d305e061 781 else if (min_cdclk > 308571)
7ff89ca2
VS		 782 return 432000;
783 else
784 return 308571;
785 } else {
d305e061 786 if (min_cdclk > 540000)
7ff89ca2 787 return 675000;
d305e061 788 else if (min_cdclk > 450000)
7ff89ca2 789 return 540000;
d305e061 790 else if (min_cdclk > 337500)
7ff89ca2
VS		 791 return 450000;
792 else
793 return 337500;
794 }
795}
796
2aa97491
VS		 797static u8 skl_calc_voltage_level(int cdclk)
798{
799 switch (cdclk) {
800 default:
801 case 308571:
802 case 337500:
803 return 0;
804 case 450000:
805 case 432000:
806 return 1;
807 case 540000:
808 return 2;
809 case 617143:
810 case 675000:
811 return 3;
812 }
813}
814
49cd97a3
VS		 815static void skl_dpll0_update(struct drm_i915_private *dev_priv,
816 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 817{
818 u32 val;
819
49cd97a3
VS		 820 cdclk_state->ref = 24000;
821 cdclk_state->vco = 0;
7ff89ca2
VS		 822
823 val = I915_READ(LCPLL1_CTL);
824 if ((val & LCPLL_PLL_ENABLE) == 0)
825 return;
826
827 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
828 return;
829
830 val = I915_READ(DPLL_CTRL1);
831
832 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
833 DPLL_CTRL1_SSC(SKL_DPLL0) |
834 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
835 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
836 return;
837
838 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
839 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
840 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
841 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
842 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
49cd97a3 843 cdclk_state->vco = 8100000;
7ff89ca2
VS		 844 break;
845 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
846 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
49cd97a3 847 cdclk_state->vco = 8640000;
7ff89ca2
VS		 848 break;
849 default:
850 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
851 break;
852 }
853}
854
49cd97a3
VS		 855static void skl_get_cdclk(struct drm_i915_private *dev_priv,
856 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 857{
858 u32 cdctl;
859
49cd97a3 860 skl_dpll0_update(dev_priv, cdclk_state);
7ff89ca2 861
b6c51c3e 862 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
49cd97a3
VS		 863
864 if (cdclk_state->vco == 0)
2aa97491 865 goto out;
7ff89ca2
VS		 866
867 cdctl = I915_READ(CDCLK_CTL);
868
49cd97a3 869 if (cdclk_state->vco == 8640000) {
7ff89ca2
VS		 870 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
871 case CDCLK_FREQ_450_432:
49cd97a3
VS		 872 cdclk_state->cdclk = 432000;
873 break;
7ff89ca2 874 case CDCLK_FREQ_337_308:
49cd97a3
VS		 875 cdclk_state->cdclk = 308571;
876 break;
7ff89ca2 877 case CDCLK_FREQ_540:
49cd97a3
VS		 878 cdclk_state->cdclk = 540000;
879 break;
7ff89ca2 880 case CDCLK_FREQ_675_617:
49cd97a3
VS		 881 cdclk_state->cdclk = 617143;
882 break;
7ff89ca2
VS		 883 default:
884 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
49cd97a3 885 break;
7ff89ca2
VS		 886 }
887 } else {
888 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
889 case CDCLK_FREQ_450_432:
49cd97a3
VS		 890 cdclk_state->cdclk = 450000;
891 break;
7ff89ca2 892 case CDCLK_FREQ_337_308:
49cd97a3
VS		 893 cdclk_state->cdclk = 337500;
894 break;
7ff89ca2 895 case CDCLK_FREQ_540:
49cd97a3
VS		 896 cdclk_state->cdclk = 540000;
897 break;
7ff89ca2 898 case CDCLK_FREQ_675_617:
49cd97a3
VS		 899 cdclk_state->cdclk = 675000;
900 break;
7ff89ca2
VS		 901 default:
902 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
49cd97a3 903 break;
7ff89ca2
VS		 904 }
905 }
2aa97491
VS		 906
907 out:
908 /*
909 * Can't read this out :( Let's assume it's
910 * at least what the CDCLK frequency requires.
911 */
912 cdclk_state->voltage_level =
913 skl_calc_voltage_level(cdclk_state->cdclk);
7ff89ca2
VS		 914}
915
916/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
917static int skl_cdclk_decimal(int cdclk)
918{
919 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
920}
921
922static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
923 int vco)
924{
925 bool changed = dev_priv->skl_preferred_vco_freq != vco;
926
927 dev_priv->skl_preferred_vco_freq = vco;
928
929 if (changed)
930 intel_update_max_cdclk(dev_priv);
931}
932
933static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
934{
7ff89ca2
VS		 935 u32 val;
936
937 WARN_ON(vco != 8100000 && vco != 8640000);
938
7ff89ca2
VS		 939 /*
940 * We always enable DPLL0 with the lowest link rate possible, but still
941 * taking into account the VCO required to operate the eDP panel at the
942 * desired frequency. The usual DP link rates operate with a VCO of
943 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
944 * The modeset code is responsible for the selection of the exact link
945 * rate later on, with the constraint of choosing a frequency that
946 * works with vco.
947 */
948 val = I915_READ(DPLL_CTRL1);
949
950 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
951 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
952 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
953 if (vco == 8640000)
954 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
955 SKL_DPLL0);
956 else
957 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
958 SKL_DPLL0);
959
960 I915_WRITE(DPLL_CTRL1, val);
961 POSTING_READ(DPLL_CTRL1);
962
963 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
964
965 if (intel_wait_for_register(dev_priv,
966 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
967 5))
968 DRM_ERROR("DPLL0 not locked\n");
969
49cd97a3 970 dev_priv->cdclk.hw.vco = vco;
7ff89ca2
VS		 971
972 /* We'll want to keep using the current vco from now on. */
973 skl_set_preferred_cdclk_vco(dev_priv, vco);
974}
975
976static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
977{
978 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
979 if (intel_wait_for_register(dev_priv,
980 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
981 1))
982 DRM_ERROR("Couldn't disable DPLL0\n");
983
49cd97a3 984 dev_priv->cdclk.hw.vco = 0;
7ff89ca2
VS		 985}
986
987static void skl_set_cdclk(struct drm_i915_private *dev_priv,
83c5fda7 988 const struct intel_cdclk_state *cdclk_state)
7ff89ca2 989{
83c5fda7
VS		 990 int cdclk = cdclk_state->cdclk;
991 int vco = cdclk_state->vco;
53421c2f 992 u32 freq_select, cdclk_ctl;
7ff89ca2
VS		 993 int ret;
994
602a9de5
ID		 995 /*
996 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
997 * unsupported on SKL. In theory this should never happen since only
998 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
999 * supported on SKL either, see the above WA. WARN whenever trying to
1000 * use the corresponding VCO freq as that always leads to using the
1001 * minimum 308MHz CDCLK.
1002 */
1003 WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000);
1004
9f817501 1005 mutex_lock(&dev_priv->pcu_lock);
7ff89ca2
VS		 1006 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1007 SKL_CDCLK_PREPARE_FOR_CHANGE,
1008 SKL_CDCLK_READY_FOR_CHANGE,
1009 SKL_CDCLK_READY_FOR_CHANGE, 3);
9f817501 1010 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 1011 if (ret) {
1012 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1013 ret);
1014 return;
1015 }
1016
53421c2f 1017 /* Choose frequency for this cdclk */
7ff89ca2 1018 switch (cdclk) {
2b58417f 1019 default:
b6c51c3e 1020 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
2b58417f
VS		 1021 WARN_ON(vco != 0);
1022 /* fall through */
1023 case 308571:
1024 case 337500:
1025 freq_select = CDCLK_FREQ_337_308;
2b58417f 1026 break;
7ff89ca2
VS		 1027 case 450000:
1028 case 432000:
1029 freq_select = CDCLK_FREQ_450_432;
7ff89ca2
VS		 1030 break;
1031 case 540000:
1032 freq_select = CDCLK_FREQ_540;
7ff89ca2 1033 break;
7ff89ca2
VS		 1034 case 617143:
1035 case 675000:
1036 freq_select = CDCLK_FREQ_675_617;
7ff89ca2
VS		 1037 break;
1038 }
1039
49cd97a3
VS		 1040 if (dev_priv->cdclk.hw.vco != 0 &&
1041 dev_priv->cdclk.hw.vco != vco)
7ff89ca2
VS		 1042 skl_dpll0_disable(dev_priv);
1043
53421c2f
LDM		 1044 cdclk_ctl = I915_READ(CDCLK_CTL);
1045
1046 if (dev_priv->cdclk.hw.vco != vco) {
1047 /* Wa Display #1183: skl,kbl,cfl */
1048 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1049 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1050 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1051 }
1052
1053 /* Wa Display #1183: skl,kbl,cfl */
1054 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1055 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1056 POSTING_READ(CDCLK_CTL);
1057
49cd97a3 1058 if (dev_priv->cdclk.hw.vco != vco)
7ff89ca2
VS		 1059 skl_dpll0_enable(dev_priv, vco);
1060
53421c2f
LDM		 1061 /* Wa Display #1183: skl,kbl,cfl */
1062 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1063 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1064
1065 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1066 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1067
1068 /* Wa Display #1183: skl,kbl,cfl */
1069 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1070 I915_WRITE(CDCLK_CTL, cdclk_ctl);
7ff89ca2
VS		 1071 POSTING_READ(CDCLK_CTL);
1072
1073 /* inform PCU of the change */
9f817501 1074 mutex_lock(&dev_priv->pcu_lock);
2aa97491
VS		 1075 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1076 cdclk_state->voltage_level);
9f817501 1077 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 1078
1079 intel_update_cdclk(dev_priv);
1080}
1081
1082static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1083{
1084 uint32_t cdctl, expected;
1085
1086 /*
1087 * check if the pre-os initialized the display
1088 * There is SWF18 scratchpad register defined which is set by the
1089 * pre-os which can be used by the OS drivers to check the status
1090 */
1091 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1092 goto sanitize;
1093
1094 intel_update_cdclk(dev_priv);
cfddadc9
VS		 1095 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1096
7ff89ca2 1097 /* Is PLL enabled and locked ? */
49cd97a3 1098 if (dev_priv->cdclk.hw.vco == 0 ||
b6c51c3e 1099 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
7ff89ca2
VS		 1100 goto sanitize;
1101
1102 /* DPLL okay; verify the cdclock
1103 *
1104 * Noticed in some instances that the freq selection is correct but
1105 * decimal part is programmed wrong from BIOS where pre-os does not
1106 * enable display. Verify the same as well.
1107 */
1108 cdctl = I915_READ(CDCLK_CTL);
1109 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
49cd97a3 1110 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
7ff89ca2
VS		 1111 if (cdctl == expected)
1112 /* All well; nothing to sanitize */
1113 return;
1114
1115sanitize:
1116 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1117
1118 /* force cdclk programming */
49cd97a3 1119 dev_priv->cdclk.hw.cdclk = 0;
7ff89ca2 1120 /* force full PLL disable + enable */
49cd97a3 1121 dev_priv->cdclk.hw.vco = -1;
7ff89ca2
VS		 1122}
1123
1124/**
1125 * skl_init_cdclk - Initialize CDCLK on SKL
1126 * @dev_priv: i915 device
1127 *
1128 * Initialize CDCLK for SKL and derivatives. This is generally
1129 * done only during the display core initialization sequence,
1130 * after which the DMC will take care of turning CDCLK off/on
1131 * as needed.
1132 */
1133void skl_init_cdclk(struct drm_i915_private *dev_priv)
1134{
83c5fda7 1135 struct intel_cdclk_state cdclk_state;
7ff89ca2
VS		 1136
1137 skl_sanitize_cdclk(dev_priv);
1138
49cd97a3
VS		 1139 if (dev_priv->cdclk.hw.cdclk != 0 &&
1140 dev_priv->cdclk.hw.vco != 0) {
7ff89ca2
VS		 1141 /*
1142 * Use the current vco as our initial
1143 * guess as to what the preferred vco is.
1144 */
1145 if (dev_priv->skl_preferred_vco_freq == 0)
1146 skl_set_preferred_cdclk_vco(dev_priv,
49cd97a3 1147 dev_priv->cdclk.hw.vco);
7ff89ca2
VS		 1148 return;
1149 }
1150
83c5fda7
VS		 1151 cdclk_state = dev_priv->cdclk.hw;
1152
1153 cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1154 if (cdclk_state.vco == 0)
1155 cdclk_state.vco = 8100000;
1156 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
2aa97491 1157 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
7ff89ca2 1158
83c5fda7 1159 skl_set_cdclk(dev_priv, &cdclk_state);
7ff89ca2
VS		 1160}
1161
1162/**
1163 * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1164 * @dev_priv: i915 device
1165 *
1166 * Uninitialize CDCLK for SKL and derivatives. This is done only
1167 * during the display core uninitialization sequence.
1168 */
1169void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1170{
83c5fda7
VS		 1171 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1172
b6c51c3e 1173 cdclk_state.cdclk = cdclk_state.bypass;
83c5fda7 1174 cdclk_state.vco = 0;
2aa97491 1175 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
83c5fda7
VS		 1176
1177 skl_set_cdclk(dev_priv, &cdclk_state);
7ff89ca2
VS		 1178}
1179
d305e061 1180static int bxt_calc_cdclk(int min_cdclk)
7ff89ca2 1181{
d305e061 1182 if (min_cdclk > 576000)
7ff89ca2 1183 return 624000;
d305e061 1184 else if (min_cdclk > 384000)
7ff89ca2 1185 return 576000;
d305e061 1186 else if (min_cdclk > 288000)
7ff89ca2 1187 return 384000;
d305e061 1188 else if (min_cdclk > 144000)
7ff89ca2
VS		 1189 return 288000;
1190 else
1191 return 144000;
1192}
1193
d305e061 1194static int glk_calc_cdclk(int min_cdclk)
7ff89ca2 1195{
d305e061 1196 if (min_cdclk > 158400)
7ff89ca2 1197 return 316800;
d305e061 1198 else if (min_cdclk > 79200)
7ff89ca2
VS		 1199 return 158400;
1200 else
1201 return 79200;
1202}
1203
2123f442
VS		 1204static u8 bxt_calc_voltage_level(int cdclk)
1205{
1206 return DIV_ROUND_UP(cdclk, 25000);
1207}
1208
7ff89ca2
VS		 1209static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1210{
1211 int ratio;
1212
b6c51c3e 1213 if (cdclk == dev_priv->cdclk.hw.bypass)
7ff89ca2
VS		 1214 return 0;
1215
1216 switch (cdclk) {
1217 default:
1218 MISSING_CASE(cdclk);
2b58417f 1219 /* fall through */
7ff89ca2
VS		 1220 case 144000:
1221 case 288000:
1222 case 384000:
1223 case 576000:
1224 ratio = 60;
1225 break;
1226 case 624000:
1227 ratio = 65;
1228 break;
1229 }
1230
49cd97a3 1231 return dev_priv->cdclk.hw.ref * ratio;
7ff89ca2
VS		 1232}
1233
1234static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1235{
1236 int ratio;
1237
b6c51c3e 1238 if (cdclk == dev_priv->cdclk.hw.bypass)
7ff89ca2
VS		 1239 return 0;
1240
1241 switch (cdclk) {
1242 default:
1243 MISSING_CASE(cdclk);
2b58417f 1244 /* fall through */
7ff89ca2
VS		 1245 case 79200:
1246 case 158400:
1247 case 316800:
1248 ratio = 33;
1249 break;
1250 }
1251
49cd97a3 1252 return dev_priv->cdclk.hw.ref * ratio;
7ff89ca2
VS		 1253}
1254
49cd97a3
VS		 1255static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1256 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 1257{
1258 u32 val;
1259
49cd97a3
VS		 1260 cdclk_state->ref = 19200;
1261 cdclk_state->vco = 0;
7ff89ca2
VS		 1262
1263 val = I915_READ(BXT_DE_PLL_ENABLE);
1264 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1265 return;
1266
1267 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1268 return;
1269
1270 val = I915_READ(BXT_DE_PLL_CTL);
49cd97a3 1271 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
7ff89ca2
VS		 1272}
1273
49cd97a3
VS		 1274static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1275 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 1276{
1277 u32 divider;
49cd97a3 1278 int div;
7ff89ca2 1279
49cd97a3 1280 bxt_de_pll_update(dev_priv, cdclk_state);
7ff89ca2 1281
b6c51c3e 1282 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
49cd97a3
VS		 1283
1284 if (cdclk_state->vco == 0)
2123f442 1285 goto out;
7ff89ca2
VS		 1286
1287 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1288
1289 switch (divider) {
1290 case BXT_CDCLK_CD2X_DIV_SEL_1:
1291 div = 2;
1292 break;
1293 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1294 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1295 div = 3;
1296 break;
1297 case BXT_CDCLK_CD2X_DIV_SEL_2:
1298 div = 4;
1299 break;
1300 case BXT_CDCLK_CD2X_DIV_SEL_4:
1301 div = 8;
1302 break;
1303 default:
1304 MISSING_CASE(divider);
49cd97a3 1305 return;
7ff89ca2
VS		 1306 }
1307
49cd97a3 1308 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
2123f442
VS		 1309
1310 out:
1311 /*
1312 * Can't read this out :( Let's assume it's
1313 * at least what the CDCLK frequency requires.
1314 */
1315 cdclk_state->voltage_level =
1316 bxt_calc_voltage_level(cdclk_state->cdclk);
7ff89ca2
VS		 1317}
1318
1319static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1320{
1321 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1322
1323 /* Timeout 200us */
1324 if (intel_wait_for_register(dev_priv,
1325 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1326 1))
1327 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1328
49cd97a3 1329 dev_priv->cdclk.hw.vco = 0;
7ff89ca2
VS		 1330}
1331
1332static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1333{
49cd97a3 1334 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
7ff89ca2
VS		 1335 u32 val;
1336
1337 val = I915_READ(BXT_DE_PLL_CTL);
1338 val &= ~BXT_DE_PLL_RATIO_MASK;
1339 val |= BXT_DE_PLL_RATIO(ratio);
1340 I915_WRITE(BXT_DE_PLL_CTL, val);
1341
1342 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1343
1344 /* Timeout 200us */
1345 if (intel_wait_for_register(dev_priv,
1346 BXT_DE_PLL_ENABLE,
1347 BXT_DE_PLL_LOCK,
1348 BXT_DE_PLL_LOCK,
1349 1))
1350 DRM_ERROR("timeout waiting for DE PLL lock\n");
1351
49cd97a3 1352 dev_priv->cdclk.hw.vco = vco;
7ff89ca2
VS		 1353}
1354
8f0cfa4d 1355static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
83c5fda7 1356 const struct intel_cdclk_state *cdclk_state)
7ff89ca2 1357{
83c5fda7
VS		 1358 int cdclk = cdclk_state->cdclk;
1359 int vco = cdclk_state->vco;
7ff89ca2 1360 u32 val, divider;
8f0cfa4d 1361 int ret;
7ff89ca2 1362
7ff89ca2
VS		 1363 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1364 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
2b58417f 1365 default:
b6c51c3e 1366 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
2b58417f
VS		 1367 WARN_ON(vco != 0);
1368 /* fall through */
1369 case 2:
1370 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
7ff89ca2
VS		 1371 break;
1372 case 3:
1373 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1374 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1375 break;
2b58417f
VS		 1376 case 4:
1377 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
7ff89ca2 1378 break;
2b58417f
VS		 1379 case 8:
1380 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
7ff89ca2
VS		 1381 break;
1382 }
1383
e76019a8
ID		 1384 /*
1385 * Inform power controller of upcoming frequency change. BSpec
1386 * requires us to wait up to 150usec, but that leads to timeouts;
1387 * the 2ms used here is based on experiment.
1388 */
9f817501 1389 mutex_lock(&dev_priv->pcu_lock);
e76019a8
ID		 1390 ret = sandybridge_pcode_write_timeout(dev_priv,
1391 HSW_PCODE_DE_WRITE_FREQ_REQ,
006bb4cc 1392 0x80000000, 150, 2);
9f817501 1393 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 1394
1395 if (ret) {
1396 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1397 ret, cdclk);
1398 return;
1399 }
1400
49cd97a3
VS		 1401 if (dev_priv->cdclk.hw.vco != 0 &&
1402 dev_priv->cdclk.hw.vco != vco)
7ff89ca2
VS		 1403 bxt_de_pll_disable(dev_priv);
1404
49cd97a3 1405 if (dev_priv->cdclk.hw.vco != vco)
7ff89ca2
VS		 1406 bxt_de_pll_enable(dev_priv, vco);
1407
1408 val = divider | skl_cdclk_decimal(cdclk);
1409 /*
1410 * FIXME if only the cd2x divider needs changing, it could be done
1411 * without shutting off the pipe (if only one pipe is active).
1412 */
1413 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1414 /*
1415 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1416 * enable otherwise.
1417 */
1418 if (cdclk >= 500000)
1419 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1420 I915_WRITE(CDCLK_CTL, val);
1421
9f817501 1422 mutex_lock(&dev_priv->pcu_lock);
e76019a8
ID		 1423 /*
1424 * The timeout isn't specified, the 2ms used here is based on
1425 * experiment.
1426 * FIXME: Waiting for the request completion could be delayed until
1427 * the next PCODE request based on BSpec.
1428 */
1429 ret = sandybridge_pcode_write_timeout(dev_priv,
1430 HSW_PCODE_DE_WRITE_FREQ_REQ,
006bb4cc 1431 cdclk_state->voltage_level, 150, 2);
9f817501 1432 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 1433
1434 if (ret) {
1435 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1436 ret, cdclk);
1437 return;
1438 }
1439
1440 intel_update_cdclk(dev_priv);
1441}
1442
1443static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1444{
1445 u32 cdctl, expected;
1446
1447 intel_update_cdclk(dev_priv);
cfddadc9 1448 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
7ff89ca2 1449
49cd97a3 1450 if (dev_priv->cdclk.hw.vco == 0 ||
b6c51c3e 1451 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
7ff89ca2
VS		 1452 goto sanitize;
1453
1454 /* DPLL okay; verify the cdclock
1455 *
1456 * Some BIOS versions leave an incorrect decimal frequency value and
1457 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1458 * so sanitize this register.
1459 */
1460 cdctl = I915_READ(CDCLK_CTL);
1461 /*
1462 * Let's ignore the pipe field, since BIOS could have configured the
1463 * dividers both synching to an active pipe, or asynchronously
1464 * (PIPE_NONE).
1465 */
1466 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1467
1468 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
49cd97a3 1469 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
7ff89ca2
VS		 1470 /*
1471 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1472 * enable otherwise.
1473 */
49cd97a3 1474 if (dev_priv->cdclk.hw.cdclk >= 500000)
7ff89ca2
VS		 1475 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1476
1477 if (cdctl == expected)
1478 /* All well; nothing to sanitize */
1479 return;
1480
1481sanitize:
1482 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1483
1484 /* force cdclk programming */
49cd97a3 1485 dev_priv->cdclk.hw.cdclk = 0;
7ff89ca2
VS		 1486
1487 /* force full PLL disable + enable */
49cd97a3 1488 dev_priv->cdclk.hw.vco = -1;
7ff89ca2
VS		 1489}
1490
1491/**
1492 * bxt_init_cdclk - Initialize CDCLK on BXT
1493 * @dev_priv: i915 device
1494 *
1495 * Initialize CDCLK for BXT and derivatives. This is generally
1496 * done only during the display core initialization sequence,
1497 * after which the DMC will take care of turning CDCLK off/on
1498 * as needed.
1499 */
1500void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1501{
83c5fda7 1502 struct intel_cdclk_state cdclk_state;
7ff89ca2
VS		 1503
1504 bxt_sanitize_cdclk(dev_priv);
1505
49cd97a3
VS		 1506 if (dev_priv->cdclk.hw.cdclk != 0 &&
1507 dev_priv->cdclk.hw.vco != 0)
7ff89ca2
VS		 1508 return;
1509
83c5fda7
VS		 1510 cdclk_state = dev_priv->cdclk.hw;
1511
7ff89ca2
VS		 1512 /*
1513 * FIXME:
1514 * - The initial CDCLK needs to be read from VBT.
1515 * Need to make this change after VBT has changes for BXT.
1516 */
8f0cfa4d 1517 if (IS_GEMINILAKE(dev_priv)) {
83c5fda7
VS		 1518 cdclk_state.cdclk = glk_calc_cdclk(0);
1519 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
8f0cfa4d 1520 } else {
83c5fda7
VS		 1521 cdclk_state.cdclk = bxt_calc_cdclk(0);
1522 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
8f0cfa4d 1523 }
2123f442 1524 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
7ff89ca2 1525
83c5fda7 1526 bxt_set_cdclk(dev_priv, &cdclk_state);
7ff89ca2
VS		 1527}
1528
1529/**
1530 * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1531 * @dev_priv: i915 device
1532 *
1533 * Uninitialize CDCLK for BXT and derivatives. This is done only
1534 * during the display core uninitialization sequence.
1535 */
1536void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1537{
83c5fda7
VS		 1538 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1539
b6c51c3e 1540 cdclk_state.cdclk = cdclk_state.bypass;
83c5fda7 1541 cdclk_state.vco = 0;
2123f442 1542 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
83c5fda7
VS		 1543
1544 bxt_set_cdclk(dev_priv, &cdclk_state);
49cd97a3
VS		 1545}
1546
d305e061 1547static int cnl_calc_cdclk(int min_cdclk)
d1999e9e 1548{
d305e061 1549 if (min_cdclk > 336000)
d1999e9e 1550 return 528000;
d305e061 1551 else if (min_cdclk > 168000)
d1999e9e
RV		 1552 return 336000;
1553 else
1554 return 168000;
1555}
1556
48469ece
VS		 1557static u8 cnl_calc_voltage_level(int cdclk)
1558{
1559 switch (cdclk) {
1560 default:
1561 case 168000:
1562 return 0;
1563 case 336000:
1564 return 1;
1565 case 528000:
1566 return 2;
1567 }
1568}
1569
945f2672
VS		 1570static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1571 struct intel_cdclk_state *cdclk_state)
1572{
1573 u32 val;
1574
1575 if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1576 cdclk_state->ref = 24000;
1577 else
1578 cdclk_state->ref = 19200;
1579
1580 cdclk_state->vco = 0;
1581
1582 val = I915_READ(BXT_DE_PLL_ENABLE);
1583 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1584 return;
1585
1586 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1587 return;
1588
1589 cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1590}
1591
1592static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1593 struct intel_cdclk_state *cdclk_state)
1594{
1595 u32 divider;
1596 int div;
1597
1598 cnl_cdclk_pll_update(dev_priv, cdclk_state);
1599
b6c51c3e 1600 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
945f2672
VS		 1601
1602 if (cdclk_state->vco == 0)
48469ece 1603 goto out;
945f2672
VS		 1604
1605 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1606
1607 switch (divider) {
1608 case BXT_CDCLK_CD2X_DIV_SEL_1:
1609 div = 2;
1610 break;
1611 case BXT_CDCLK_CD2X_DIV_SEL_2:
1612 div = 4;
1613 break;
1614 default:
1615 MISSING_CASE(divider);
1616 return;
1617 }
1618
1619 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
48469ece
VS		 1620
1621 out:
1622 /*
1623 * Can't read this out :( Let's assume it's
1624 * at least what the CDCLK frequency requires.
1625 */
1626 cdclk_state->voltage_level =
1627 cnl_calc_voltage_level(cdclk_state->cdclk);
945f2672
VS		 1628}
1629
ef4f7a68
VS		 1630static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1631{
1632 u32 val;
1633
1634 val = I915_READ(BXT_DE_PLL_ENABLE);
1635 val &= ~BXT_DE_PLL_PLL_ENABLE;
1636 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1637
1638 /* Timeout 200us */
1639 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
bc8282a7 1640 DRM_ERROR("timeout waiting for CDCLK PLL unlock\n");
ef4f7a68
VS		 1641
1642 dev_priv->cdclk.hw.vco = 0;
1643}
1644
1645static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1646{
1647 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1648 u32 val;
1649
1650 val = CNL_CDCLK_PLL_RATIO(ratio);
1651 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1652
1653 val |= BXT_DE_PLL_PLL_ENABLE;
1654 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1655
1656 /* Timeout 200us */
1657 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
bc8282a7 1658 DRM_ERROR("timeout waiting for CDCLK PLL lock\n");
ef4f7a68
VS		 1659
1660 dev_priv->cdclk.hw.vco = vco;
1661}
1662
ef4f7a68
VS		 1663static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1664 const struct intel_cdclk_state *cdclk_state)
1665{
1666 int cdclk = cdclk_state->cdclk;
1667 int vco = cdclk_state->vco;
48469ece 1668 u32 val, divider;
ef4f7a68
VS		 1669 int ret;
1670
9f817501 1671 mutex_lock(&dev_priv->pcu_lock);
ef4f7a68
VS		 1672 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1673 SKL_CDCLK_PREPARE_FOR_CHANGE,
1674 SKL_CDCLK_READY_FOR_CHANGE,
1675 SKL_CDCLK_READY_FOR_CHANGE, 3);
9f817501 1676 mutex_unlock(&dev_priv->pcu_lock);
ef4f7a68
VS		 1677 if (ret) {
1678 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1679 ret);
1680 return;
1681 }
1682
1683 /* cdclk = vco / 2 / div{1,2} */
1684 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
ef4f7a68 1685 default:
b6c51c3e 1686 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
ef4f7a68 1687 WARN_ON(vco != 0);
2b58417f
VS		 1688 /* fall through */
1689 case 2:
ef4f7a68
VS		 1690 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1691 break;
2b58417f
VS		 1692 case 4:
1693 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1694 break;
ef4f7a68
VS		 1695 }
1696
ef4f7a68
VS		 1697 if (dev_priv->cdclk.hw.vco != 0 &&
1698 dev_priv->cdclk.hw.vco != vco)
1699 cnl_cdclk_pll_disable(dev_priv);
1700
1701 if (dev_priv->cdclk.hw.vco != vco)
1702 cnl_cdclk_pll_enable(dev_priv, vco);
1703
1704 val = divider | skl_cdclk_decimal(cdclk);
1705 /*
1706 * FIXME if only the cd2x divider needs changing, it could be done
1707 * without shutting off the pipe (if only one pipe is active).
1708 */
1709 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1710 I915_WRITE(CDCLK_CTL, val);
1711
1712 /* inform PCU of the change */
9f817501 1713 mutex_lock(&dev_priv->pcu_lock);
48469ece
VS		 1714 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1715 cdclk_state->voltage_level);
9f817501 1716 mutex_unlock(&dev_priv->pcu_lock);
ef4f7a68
VS		 1717
1718 intel_update_cdclk(dev_priv);
53e9bf5e
VS		 1719
1720 /*
1721 * Can't read out the voltage level :(
1722 * Let's just assume everything is as expected.
1723 */
1724 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
ef4f7a68
VS		 1725}
1726
d8d4a512
VS		 1727static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1728{
1729 int ratio;
1730
b6c51c3e 1731 if (cdclk == dev_priv->cdclk.hw.bypass)
d8d4a512
VS		 1732 return 0;
1733
1734 switch (cdclk) {
1735 default:
1736 MISSING_CASE(cdclk);
2b58417f 1737 /* fall through */
d8d4a512
VS		 1738 case 168000:
1739 case 336000:
1740 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1741 break;
1742 case 528000:
1743 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1744 break;
1745 }
1746
1747 return dev_priv->cdclk.hw.ref * ratio;
1748}
1749
1750static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1751{
1752 u32 cdctl, expected;
1753
1754 intel_update_cdclk(dev_priv);
cfddadc9 1755 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
d8d4a512
VS		 1756
1757 if (dev_priv->cdclk.hw.vco == 0 ||
b6c51c3e 1758 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
d8d4a512
VS		 1759 goto sanitize;
1760
1761 /* DPLL okay; verify the cdclock
1762 *
1763 * Some BIOS versions leave an incorrect decimal frequency value and
1764 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1765 * so sanitize this register.
1766 */
1767 cdctl = I915_READ(CDCLK_CTL);
1768 /*
1769 * Let's ignore the pipe field, since BIOS could have configured the
1770 * dividers both synching to an active pipe, or asynchronously
1771 * (PIPE_NONE).
1772 */
1773 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1774
1775 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1776 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1777
1778 if (cdctl == expected)
1779 /* All well; nothing to sanitize */
1780 return;
1781
1782sanitize:
1783 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1784
1785 /* force cdclk programming */
1786 dev_priv->cdclk.hw.cdclk = 0;
1787
1788 /* force full PLL disable + enable */
1789 dev_priv->cdclk.hw.vco = -1;
1790}
1791
186a277e
PZ		 1792static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
1793{
1794 int ranges_24[] = { 312000, 552000, 648000 };
1795 int ranges_19_38[] = { 307200, 556800, 652800 };
1796 int *ranges;
1797
1798 switch (ref) {
1799 default:
1800 MISSING_CASE(ref);
f0d759f0 1801 /* fall through */
186a277e
PZ		 1802 case 24000:
1803 ranges = ranges_24;
1804 break;
1805 case 19200:
1806 case 38400:
1807 ranges = ranges_19_38;
1808 break;
1809 }
1810
1811 if (min_cdclk > ranges[1])
1812 return ranges[2];
1813 else if (min_cdclk > ranges[0])
1814 return ranges[1];
1815 else
1816 return ranges[0];
1817}
1818
1819static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1820{
1821 int ratio;
1822
1823 if (cdclk == dev_priv->cdclk.hw.bypass)
1824 return 0;
1825
1826 switch (cdclk) {
1827 default:
1828 MISSING_CASE(cdclk);
f0d759f0 1829 /* fall through */
186a277e
PZ		 1830 case 307200:
1831 case 556800:
1832 case 652800:
1833 WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
1834 dev_priv->cdclk.hw.ref != 38400);
1835 break;
1836 case 312000:
1837 case 552000:
1838 case 648000:
1839 WARN_ON(dev_priv->cdclk.hw.ref != 24000);
1840 }
1841
1842 ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
1843
1844 return dev_priv->cdclk.hw.ref * ratio;
1845}
1846
1847static void icl_set_cdclk(struct drm_i915_private *dev_priv,
1848 const struct intel_cdclk_state *cdclk_state)
1849{
1850 unsigned int cdclk = cdclk_state->cdclk;
1851 unsigned int vco = cdclk_state->vco;
1852 int ret;
1853
1854 mutex_lock(&dev_priv->pcu_lock);
1855 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1856 SKL_CDCLK_PREPARE_FOR_CHANGE,
1857 SKL_CDCLK_READY_FOR_CHANGE,
1858 SKL_CDCLK_READY_FOR_CHANGE, 3);
1859 mutex_unlock(&dev_priv->pcu_lock);
1860 if (ret) {
1861 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1862 ret);
1863 return;
1864 }
1865
1866 if (dev_priv->cdclk.hw.vco != 0 &&
1867 dev_priv->cdclk.hw.vco != vco)
1868 cnl_cdclk_pll_disable(dev_priv);
1869
1870 if (dev_priv->cdclk.hw.vco != vco)
1871 cnl_cdclk_pll_enable(dev_priv, vco);
1872
1873 I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
1874 skl_cdclk_decimal(cdclk));
1875
1876 mutex_lock(&dev_priv->pcu_lock);
9378985e
PZ		 1877 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1878 cdclk_state->voltage_level);
186a277e
PZ		 1879 mutex_unlock(&dev_priv->pcu_lock);
1880
1881 intel_update_cdclk(dev_priv);
9378985e
PZ		 1882
1883 /*
1884 * Can't read out the voltage level :(
1885 * Let's just assume everything is as expected.
1886 */
1887 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1888}
1889
1890static u8 icl_calc_voltage_level(int cdclk)
1891{
1892 switch (cdclk) {
1893 case 50000:
1894 case 307200:
1895 case 312000:
1896 return 0;
1897 case 556800:
1898 case 552000:
1899 return 1;
1900 default:
1901 MISSING_CASE(cdclk);
f0d759f0 1902 /* fall through */
9378985e
PZ		 1903 case 652800:
1904 case 648000:
1905 return 2;
1906 }
186a277e
PZ		 1907}
1908
1909static void icl_get_cdclk(struct drm_i915_private *dev_priv,
1910 struct intel_cdclk_state *cdclk_state)
1911{
1912 u32 val;
1913
1914 cdclk_state->bypass = 50000;
1915
1916 val = I915_READ(SKL_DSSM);
1917 switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
1918 default:
1919 MISSING_CASE(val);
f0d759f0 1920 /* fall through */
186a277e
PZ		 1921 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1922 cdclk_state->ref = 24000;
1923 break;
1924 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1925 cdclk_state->ref = 19200;
1926 break;
1927 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1928 cdclk_state->ref = 38400;
1929 break;
1930 }
1931
1932 val = I915_READ(BXT_DE_PLL_ENABLE);
1933 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1934 (val & BXT_DE_PLL_LOCK) == 0) {
1935 /*
1936 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1937 * setting it to zero is a way to signal that.
1938 */
1939 cdclk_state->vco = 0;
1940 cdclk_state->cdclk = cdclk_state->bypass;
9378985e 1941 goto out;
186a277e
PZ		 1942 }
1943
1944 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1945
1946 val = I915_READ(CDCLK_CTL);
1947 WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
1948
1949 cdclk_state->cdclk = cdclk_state->vco / 2;
9378985e
PZ		 1950
1951out:
1952 /*
1953 * Can't read this out :( Let's assume it's
1954 * at least what the CDCLK frequency requires.
1955 */
1956 cdclk_state->voltage_level =
1957 icl_calc_voltage_level(cdclk_state->cdclk);
186a277e
PZ		 1958}
1959
1960/**
1961 * icl_init_cdclk - Initialize CDCLK on ICL
1962 * @dev_priv: i915 device
1963 *
1964 * Initialize CDCLK for ICL. This consists mainly of initializing
1965 * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
1966 * is generally done only during the display core initialization sequence, after
1967 * which the DMC will take care of turning CDCLK off/on as needed.
1968 */
1969void icl_init_cdclk(struct drm_i915_private *dev_priv)
1970{
1971 struct intel_cdclk_state sanitized_state;
1972 u32 val;
1973
1974 /* This sets dev_priv->cdclk.hw. */
1975 intel_update_cdclk(dev_priv);
1976 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1977
1978 /* This means CDCLK disabled. */
1979 if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1980 goto sanitize;
1981
1982 val = I915_READ(CDCLK_CTL);
1983
1984 if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
1985 goto sanitize;
1986
1987 if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
1988 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
1989 goto sanitize;
1990
1991 return;
1992
1993sanitize:
1994 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1995
1996 sanitized_state.ref = dev_priv->cdclk.hw.ref;
1997 sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
1998 sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
1999 sanitized_state.cdclk);
9378985e
PZ		 2000 sanitized_state.voltage_level =
2001 icl_calc_voltage_level(sanitized_state.cdclk);
186a277e
PZ		 2002
2003 icl_set_cdclk(dev_priv, &sanitized_state);
2004}
2005
2006/**
2007 * icl_uninit_cdclk - Uninitialize CDCLK on ICL
2008 * @dev_priv: i915 device
2009 *
2010 * Uninitialize CDCLK for ICL. This is done only during the display core
2011 * uninitialization sequence.
2012 */
2013void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
2014{
2015 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
2016
2017 cdclk_state.cdclk = cdclk_state.bypass;
2018 cdclk_state.vco = 0;
9378985e 2019 cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
186a277e
PZ		 2020
2021 icl_set_cdclk(dev_priv, &cdclk_state);
2022}
2023
d8d4a512
VS		 2024/**
2025 * cnl_init_cdclk - Initialize CDCLK on CNL
2026 * @dev_priv: i915 device
2027 *
2028 * Initialize CDCLK for CNL. This is generally
2029 * done only during the display core initialization sequence,
2030 * after which the DMC will take care of turning CDCLK off/on
2031 * as needed.
2032 */
2033void cnl_init_cdclk(struct drm_i915_private *dev_priv)
2034{
2035 struct intel_cdclk_state cdclk_state;
2036
2037 cnl_sanitize_cdclk(dev_priv);
2038
2039 if (dev_priv->cdclk.hw.cdclk != 0 &&
2040 dev_priv->cdclk.hw.vco != 0)
2041 return;
2042
2043 cdclk_state = dev_priv->cdclk.hw;
2044
d1999e9e 2045 cdclk_state.cdclk = cnl_calc_cdclk(0);
d8d4a512 2046 cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
48469ece 2047 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
d8d4a512
VS		 2048
2049 cnl_set_cdclk(dev_priv, &cdclk_state);
2050}
2051
2052/**
2053 * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
2054 * @dev_priv: i915 device
2055 *
2056 * Uninitialize CDCLK for CNL. This is done only
2057 * during the display core uninitialization sequence.
2058 */
2059void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
2060{
2061 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
2062
b6c51c3e 2063 cdclk_state.cdclk = cdclk_state.bypass;
d8d4a512 2064 cdclk_state.vco = 0;
48469ece 2065 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
d8d4a512
VS		 2066
2067 cnl_set_cdclk(dev_priv, &cdclk_state);
2068}
2069
49cd97a3 2070/**
64600bd5 2071 * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
49cd97a3
VS		 2072 * @a: first CDCLK state
2073 * @b: second CDCLK state
2074 *
2075 * Returns:
64600bd5 2076 * True if the CDCLK states require pipes to be off during reprogramming, false if not.
49cd97a3 2077 */
64600bd5 2078bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
49cd97a3
VS		 2079 const struct intel_cdclk_state *b)
2080{
64600bd5
VS		 2081 return a->cdclk != b->cdclk ||
2082 a->vco != b->vco ||
2083 a->ref != b->ref;
2084}
2085
2086/**
2087 * intel_cdclk_changed - Determine if two CDCLK states are different
2088 * @a: first CDCLK state
2089 * @b: second CDCLK state
2090 *
2091 * Returns:
2092 * True if the CDCLK states don't match, false if they do.
2093 */
2094bool intel_cdclk_changed(const struct intel_cdclk_state *a,
2095 const struct intel_cdclk_state *b)
2096{
2097 return intel_cdclk_needs_modeset(a, b) ||
2098 a->voltage_level != b->voltage_level;
7ff89ca2
VS		 2099}
2100
cfddadc9
VS		 2101void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
2102 const char *context)
2103{
b6c51c3e 2104 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
cfddadc9 2105 context, cdclk_state->cdclk, cdclk_state->vco,
b6c51c3e
ID		 2106 cdclk_state->ref, cdclk_state->bypass,
2107 cdclk_state->voltage_level);
cfddadc9
VS		 2108}
2109
b0587e4d
VS		 2110/**
2111 * intel_set_cdclk - Push the CDCLK state to the hardware
2112 * @dev_priv: i915 device
2113 * @cdclk_state: new CDCLK state
2114 *
2115 * Program the hardware based on the passed in CDCLK state,
2116 * if necessary.
2117 */
2118void intel_set_cdclk(struct drm_i915_private *dev_priv,
2119 const struct intel_cdclk_state *cdclk_state)
2120{
64600bd5 2121 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
b0587e4d
VS		 2122 return;
2123
2124 if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
2125 return;
2126
cfddadc9 2127 intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
b0587e4d
VS		 2128
2129 dev_priv->display.set_cdclk(dev_priv, cdclk_state);
cfddadc9
VS		 2130
2131 if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
2132 "cdclk state doesn't match!\n")) {
2133 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
2134 intel_dump_cdclk_state(cdclk_state, "[sw state]");
2135 }
b0587e4d
VS		 2136}
2137
d305e061
VS		 2138static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
2139 int pixel_rate)
2140{
2c2f6e30 2141 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
43037c86 2142 return DIV_ROUND_UP(pixel_rate, 2);
d305e061
VS		 2143 else if (IS_GEN9(dev_priv) ||
2144 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2145 return pixel_rate;
2146 else if (IS_CHERRYVIEW(dev_priv))
2147 return DIV_ROUND_UP(pixel_rate * 100, 95);
2148 else
2149 return DIV_ROUND_UP(pixel_rate * 100, 90);
2150}
2151
2152int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
7ff89ca2
VS		 2153{
2154 struct drm_i915_private *dev_priv =
2155 to_i915(crtc_state->base.crtc->dev);
d305e061
VS		 2156 int min_cdclk;
2157
2158 if (!crtc_state->base.enable)
2159 return 0;
2160
2161 min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
7ff89ca2
VS		 2162
2163 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
24f28450 2164 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
d305e061 2165 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
7ff89ca2 2166
78cfa580
PD		 2167 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2168 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2169 * there may be audio corruption or screen corruption." This cdclk
d305e061 2170 * restriction for GLK is 316.8 MHz.
7ff89ca2
VS		 2171 */
2172 if (intel_crtc_has_dp_encoder(crtc_state) &&
2173 crtc_state->has_audio &&
2174 crtc_state->port_clock >= 540000 &&
78cfa580 2175 crtc_state->lane_count == 4) {
d305e061
VS		 2176 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2177 /* Display WA #1145: glk,cnl */
2178 min_cdclk = max(316800, min_cdclk);
2179 } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
2180 /* Display WA #1144: skl,bxt */
2181 min_cdclk = max(432000, min_cdclk);
2182 }
78cfa580 2183 }
7ff89ca2 2184
904e1b1f
AK		 2185 /*
2186 * According to BSpec, "The CD clock frequency must be at least twice
8cbeb06d 2187 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
904e1b1f
AK		 2188 *
2189 * FIXME: Check the actual, not default, BCLK being used.
2190 *
2191 * FIXME: This does not depend on ->has_audio because the higher CDCLK
2192 * is required for audio probe, also when there are no audio capable
2193 * displays connected at probe time. This leads to unnecessarily high
2194 * CDCLK when audio is not required.
2195 *
2196 * FIXME: This limit is only applied when there are displays connected
2197 * at probe time. If we probe without displays, we'll still end up using
2198 * the platform minimum CDCLK, failing audio probe.
8cbeb06d 2199 */
904e1b1f 2200 if (INTEL_GEN(dev_priv) >= 9)
d305e061 2201 min_cdclk = max(2 * 96000, min_cdclk);
8cbeb06d 2202
c8dae55a
HG		 2203 /*
2204 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2205 * than 320000KHz.
2206 */
2207 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2208 IS_VALLEYVIEW(dev_priv))
2209 min_cdclk = max(320000, min_cdclk);
2210
9c61de4c
VS		 2211 if (min_cdclk > dev_priv->max_cdclk_freq) {
2212 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
2213 min_cdclk, dev_priv->max_cdclk_freq);
2214 return -EINVAL;
2215 }
2216
d305e061 2217 return min_cdclk;
7ff89ca2
VS		 2218}
2219
d305e061 2220static int intel_compute_min_cdclk(struct drm_atomic_state *state)
7ff89ca2
VS		 2221{
2222 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2223 struct drm_i915_private *dev_priv = to_i915(state->dev);
d305e061 2224 struct intel_crtc *crtc;
7ff89ca2 2225 struct intel_crtc_state *crtc_state;
9c61de4c 2226 int min_cdclk, i;
7ff89ca2
VS		 2227 enum pipe pipe;
2228
d305e061
VS		 2229 memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
2230 sizeof(intel_state->min_cdclk));
7ff89ca2 2231
9c61de4c
VS		 2232 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2233 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2234 if (min_cdclk < 0)
2235 return min_cdclk;
2236
2237 intel_state->min_cdclk[i] = min_cdclk;
2238 }
7ff89ca2 2239
9c61de4c 2240 min_cdclk = 0;
7ff89ca2 2241 for_each_pipe(dev_priv, pipe)
d305e061 2242 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
7ff89ca2 2243
d305e061 2244 return min_cdclk;
7ff89ca2
VS		 2245}
2246
53e9bf5e
VS		 2247/*
2248 * Note that this functions assumes that 0 is
2249 * the lowest voltage value, and higher values
2250 * correspond to increasingly higher voltages.
2251 *
2252 * Should that relationship no longer hold on
2253 * future platforms this code will need to be
2254 * adjusted.
2255 */
2256static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
2257{
2258 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2259 struct intel_crtc *crtc;
2260 struct intel_crtc_state *crtc_state;
2261 u8 min_voltage_level;
2262 int i;
2263 enum pipe pipe;
2264
2265 memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
2266 sizeof(state->min_voltage_level));
2267
2268 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2269 if (crtc_state->base.enable)
2270 state->min_voltage_level[i] =
2271 crtc_state->min_voltage_level;
2272 else
2273 state->min_voltage_level[i] = 0;
2274 }
2275
2276 min_voltage_level = 0;
2277 for_each_pipe(dev_priv, pipe)
2278 min_voltage_level = max(state->min_voltage_level[pipe],
2279 min_voltage_level);
2280
2281 return min_voltage_level;
2282}
2283
7ff89ca2
VS		 2284static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
2285{
3d5dbb10 2286 struct drm_i915_private *dev_priv = to_i915(state->dev);
9c61de4c
VS		 2287 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2288 int min_cdclk, cdclk;
bb0f4aab 2289
9c61de4c
VS		 2290 min_cdclk = intel_compute_min_cdclk(state);
2291 if (min_cdclk < 0)
2292 return min_cdclk;
7ff89ca2 2293
9c61de4c 2294 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
7ff89ca2 2295
bb0f4aab 2296 intel_state->cdclk.logical.cdclk = cdclk;
999c5766
VS		 2297 intel_state->cdclk.logical.voltage_level =
2298 vlv_calc_voltage_level(dev_priv, cdclk);
bb0f4aab
VS		 2299
2300 if (!intel_state->active_crtcs) {
2301 cdclk = vlv_calc_cdclk(dev_priv, 0);
2302
2303 intel_state->cdclk.actual.cdclk = cdclk;
999c5766
VS		 2304 intel_state->cdclk.actual.voltage_level =
2305 vlv_calc_voltage_level(dev_priv, cdclk);
bb0f4aab
VS		 2306 } else {
2307 intel_state->cdclk.actual =
2308 intel_state->cdclk.logical;
2309 }
7ff89ca2
VS		 2310
2311 return 0;
2312}
2313
7ff89ca2
VS		 2314static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
2315{
7ff89ca2 2316 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9c61de4c
VS		 2317 int min_cdclk, cdclk;
2318
2319 min_cdclk = intel_compute_min_cdclk(state);
2320 if (min_cdclk < 0)
2321 return min_cdclk;
7ff89ca2
VS		 2322
2323 /*
2324 * FIXME should also account for plane ratio
2325 * once 64bpp pixel formats are supported.
2326 */
d305e061 2327 cdclk = bdw_calc_cdclk(min_cdclk);
7ff89ca2 2328
bb0f4aab 2329 intel_state->cdclk.logical.cdclk = cdclk;
d7ffaeef
VS		 2330 intel_state->cdclk.logical.voltage_level =
2331 bdw_calc_voltage_level(cdclk);
bb0f4aab
VS		 2332
2333 if (!intel_state->active_crtcs) {
2334 cdclk = bdw_calc_cdclk(0);
2335
2336 intel_state->cdclk.actual.cdclk = cdclk;
d7ffaeef
VS		 2337 intel_state->cdclk.actual.voltage_level =
2338 bdw_calc_voltage_level(cdclk);
bb0f4aab
VS		 2339 } else {
2340 intel_state->cdclk.actual =
2341 intel_state->cdclk.logical;
2342 }
7ff89ca2
VS		 2343
2344 return 0;
2345}
2346
3297234a
RV		 2347static int skl_dpll0_vco(struct intel_atomic_state *intel_state)
2348{
2349 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
2350 struct intel_crtc *crtc;
2351 struct intel_crtc_state *crtc_state;
2352 int vco, i;
2353
2354 vco = intel_state->cdclk.logical.vco;
2355 if (!vco)
2356 vco = dev_priv->skl_preferred_vco_freq;
2357
2358 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2359 if (!crtc_state->base.enable)
2360 continue;
2361
2362 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2363 continue;
2364
2365 /*
2366 * DPLL0 VCO may need to be adjusted to get the correct
2367 * clock for eDP. This will affect cdclk as well.
2368 */
2369 switch (crtc_state->port_clock / 2) {
2370 case 108000:
2371 case 216000:
2372 vco = 8640000;
2373 break;
2374 default:
2375 vco = 8100000;
2376 break;
2377 }
2378 }
2379
2380 return vco;
2381}
2382
7ff89ca2
VS		 2383static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
2384{
9c61de4c
VS		 2385 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2386 int min_cdclk, cdclk, vco;
2387
2388 min_cdclk = intel_compute_min_cdclk(state);
2389 if (min_cdclk < 0)
2390 return min_cdclk;
bb0f4aab 2391
3297234a 2392 vco = skl_dpll0_vco(intel_state);
7ff89ca2
VS		 2393
2394 /*
2395 * FIXME should also account for plane ratio
2396 * once 64bpp pixel formats are supported.
2397 */
d305e061 2398 cdclk = skl_calc_cdclk(min_cdclk, vco);
7ff89ca2 2399
bb0f4aab
VS		 2400 intel_state->cdclk.logical.vco = vco;
2401 intel_state->cdclk.logical.cdclk = cdclk;
2aa97491
VS		 2402 intel_state->cdclk.logical.voltage_level =
2403 skl_calc_voltage_level(cdclk);
bb0f4aab
VS		 2404
2405 if (!intel_state->active_crtcs) {
2406 cdclk = skl_calc_cdclk(0, vco);
2407
2408 intel_state->cdclk.actual.vco = vco;
2409 intel_state->cdclk.actual.cdclk = cdclk;
2aa97491
VS		 2410 intel_state->cdclk.actual.voltage_level =
2411 skl_calc_voltage_level(cdclk);
bb0f4aab
VS		 2412 } else {
2413 intel_state->cdclk.actual =
2414 intel_state->cdclk.logical;
2415 }
7ff89ca2
VS		 2416
2417 return 0;
2418}
2419
7ff89ca2
VS		 2420static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
2421{
2422 struct drm_i915_private *dev_priv = to_i915(state->dev);
9c61de4c
VS		 2423 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2424 int min_cdclk, cdclk, vco;
2425
2426 min_cdclk = intel_compute_min_cdclk(state);
2427 if (min_cdclk < 0)
2428 return min_cdclk;
7ff89ca2 2429
bb0f4aab 2430 if (IS_GEMINILAKE(dev_priv)) {
d305e061 2431 cdclk = glk_calc_cdclk(min_cdclk);
bb0f4aab
VS		 2432 vco = glk_de_pll_vco(dev_priv, cdclk);
2433 } else {
d305e061 2434 cdclk = bxt_calc_cdclk(min_cdclk);
bb0f4aab
VS		 2435 vco = bxt_de_pll_vco(dev_priv, cdclk);
2436 }
2437
bb0f4aab
VS		 2438 intel_state->cdclk.logical.vco = vco;
2439 intel_state->cdclk.logical.cdclk = cdclk;
2123f442
VS		 2440 intel_state->cdclk.logical.voltage_level =
2441 bxt_calc_voltage_level(cdclk);
7ff89ca2
VS		 2442
2443 if (!intel_state->active_crtcs) {
bb0f4aab 2444 if (IS_GEMINILAKE(dev_priv)) {
7ff89ca2 2445 cdclk = glk_calc_cdclk(0);
bb0f4aab
VS		 2446 vco = glk_de_pll_vco(dev_priv, cdclk);
2447 } else {
7ff89ca2 2448 cdclk = bxt_calc_cdclk(0);
bb0f4aab
VS		 2449 vco = bxt_de_pll_vco(dev_priv, cdclk);
2450 }
7ff89ca2 2451
bb0f4aab
VS		 2452 intel_state->cdclk.actual.vco = vco;
2453 intel_state->cdclk.actual.cdclk = cdclk;
2123f442
VS		 2454 intel_state->cdclk.actual.voltage_level =
2455 bxt_calc_voltage_level(cdclk);
bb0f4aab
VS		 2456 } else {
2457 intel_state->cdclk.actual =
2458 intel_state->cdclk.logical;
7ff89ca2
VS		 2459 }
2460
2461 return 0;
2462}
2463
d1999e9e
RV		 2464static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
2465{
2466 struct drm_i915_private *dev_priv = to_i915(state->dev);
9c61de4c
VS		 2467 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2468 int min_cdclk, cdclk, vco;
2469
2470 min_cdclk = intel_compute_min_cdclk(state);
2471 if (min_cdclk < 0)
2472 return min_cdclk;
d1999e9e 2473
d305e061 2474 cdclk = cnl_calc_cdclk(min_cdclk);
d1999e9e
RV		 2475 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2476
d1999e9e
RV		 2477 intel_state->cdclk.logical.vco = vco;
2478 intel_state->cdclk.logical.cdclk = cdclk;
48469ece 2479 intel_state->cdclk.logical.voltage_level =
53e9bf5e
VS		 2480 max(cnl_calc_voltage_level(cdclk),
2481 cnl_compute_min_voltage_level(intel_state));
d1999e9e
RV		 2482
2483 if (!intel_state->active_crtcs) {
2484 cdclk = cnl_calc_cdclk(0);
2485 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2486
2487 intel_state->cdclk.actual.vco = vco;
2488 intel_state->cdclk.actual.cdclk = cdclk;
48469ece
VS		 2489 intel_state->cdclk.actual.voltage_level =
2490 cnl_calc_voltage_level(cdclk);
d1999e9e
RV		 2491 } else {
2492 intel_state->cdclk.actual =
2493 intel_state->cdclk.logical;
2494 }
2495
2496 return 0;
2497}
2498
186a277e
PZ		 2499static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
2500{
2501 struct drm_i915_private *dev_priv = to_i915(state->dev);
2502 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2503 unsigned int ref = intel_state->cdclk.logical.ref;
2504 int min_cdclk, cdclk, vco;
2505
2506 min_cdclk = intel_compute_min_cdclk(state);
2507 if (min_cdclk < 0)
2508 return min_cdclk;
2509
2510 cdclk = icl_calc_cdclk(min_cdclk, ref);
2511 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2512
2513 intel_state->cdclk.logical.vco = vco;
2514 intel_state->cdclk.logical.cdclk = cdclk;
9378985e
PZ		 2515 intel_state->cdclk.logical.voltage_level =
2516 max(icl_calc_voltage_level(cdclk),
2517 cnl_compute_min_voltage_level(intel_state));
186a277e
PZ		 2518
2519 if (!intel_state->active_crtcs) {
2520 cdclk = icl_calc_cdclk(0, ref);
2521 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2522
2523 intel_state->cdclk.actual.vco = vco;
2524 intel_state->cdclk.actual.cdclk = cdclk;
9378985e
PZ		 2525 intel_state->cdclk.actual.voltage_level =
2526 icl_calc_voltage_level(cdclk);
186a277e
PZ		 2527 } else {
2528 intel_state->cdclk.actual = intel_state->cdclk.logical;
2529 }
2530
2531 return 0;
2532}
2533
7ff89ca2
VS		 2534static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2535{
2536 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2537
2c2f6e30 2538 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
43037c86 2539 return 2 * max_cdclk_freq;
d305e061
VS		 2540 else if (IS_GEN9(dev_priv) ||
2541 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
7ff89ca2
VS		 2542 return max_cdclk_freq;
2543 else if (IS_CHERRYVIEW(dev_priv))
2544 return max_cdclk_freq*95/100;
c56b89f1 2545 else if (INTEL_GEN(dev_priv) < 4)
7ff89ca2
VS		 2546 return 2*max_cdclk_freq*90/100;
2547 else
2548 return max_cdclk_freq*90/100;
2549}
2550
2551/**
2552 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2553 * @dev_priv: i915 device
2554 *
2555 * Determine the maximum CDCLK frequency the platform supports, and also
2556 * derive the maximum dot clock frequency the maximum CDCLK frequency
2557 * allows.
2558 */
2559void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2560{
186a277e
PZ		 2561 if (IS_ICELAKE(dev_priv)) {
2562 if (dev_priv->cdclk.hw.ref == 24000)
2563 dev_priv->max_cdclk_freq = 648000;
2564 else
2565 dev_priv->max_cdclk_freq = 652800;
2566 } else if (IS_CANNONLAKE(dev_priv)) {
d1999e9e
RV		 2567 dev_priv->max_cdclk_freq = 528000;
2568 } else if (IS_GEN9_BC(dev_priv)) {
7ff89ca2
VS		 2569 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2570 int max_cdclk, vco;
2571
2572 vco = dev_priv->skl_preferred_vco_freq;
2573 WARN_ON(vco != 8100000 && vco != 8640000);
2574
2575 /*
2576 * Use the lower (vco 8640) cdclk values as a
2577 * first guess. skl_calc_cdclk() will correct it
2578 * if the preferred vco is 8100 instead.
2579 */
2580 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2581 max_cdclk = 617143;
2582 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2583 max_cdclk = 540000;
2584 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2585 max_cdclk = 432000;
2586 else
2587 max_cdclk = 308571;
2588
2589 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2590 } else if (IS_GEMINILAKE(dev_priv)) {
2591 dev_priv->max_cdclk_freq = 316800;
2592 } else if (IS_BROXTON(dev_priv)) {
2593 dev_priv->max_cdclk_freq = 624000;
2594 } else if (IS_BROADWELL(dev_priv)) {
2595 /*
2596 * FIXME with extra cooling we can allow
2597 * 540 MHz for ULX and 675 Mhz for ULT.
2598 * How can we know if extra cooling is
2599 * available? PCI ID, VTB, something else?
2600 */
2601 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2602 dev_priv->max_cdclk_freq = 450000;
2603 else if (IS_BDW_ULX(dev_priv))
2604 dev_priv->max_cdclk_freq = 450000;
2605 else if (IS_BDW_ULT(dev_priv))
2606 dev_priv->max_cdclk_freq = 540000;
2607 else
2608 dev_priv->max_cdclk_freq = 675000;
2609 } else if (IS_CHERRYVIEW(dev_priv)) {
2610 dev_priv->max_cdclk_freq = 320000;
2611 } else if (IS_VALLEYVIEW(dev_priv)) {
2612 dev_priv->max_cdclk_freq = 400000;
2613 } else {
2614 /* otherwise assume cdclk is fixed */
49cd97a3 2615 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
7ff89ca2
VS		 2616 }
2617
2618 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2619
2620 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2621 dev_priv->max_cdclk_freq);
2622
2623 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2624 dev_priv->max_dotclk_freq);
2625}
2626
2627/**
2628 * intel_update_cdclk - Determine the current CDCLK frequency
2629 * @dev_priv: i915 device
2630 *
2631 * Determine the current CDCLK frequency.
2632 */
2633void intel_update_cdclk(struct drm_i915_private *dev_priv)
2634{
49cd97a3 2635 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
7ff89ca2 2636
7ff89ca2
VS		 2637 /*
2638 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2639 * Programmng [sic] note: bit[9:2] should be programmed to the number
2640 * of cdclk that generates 4MHz reference clock freq which is used to
2641 * generate GMBus clock. This will vary with the cdclk freq.
2642 */
2643 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2644 I915_WRITE(GMBUSFREQ_VLV,
49cd97a3 2645 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
7ff89ca2
VS		 2646}
2647
9d81a997
RV		 2648static int cnp_rawclk(struct drm_i915_private *dev_priv)
2649{
2650 u32 rawclk;
2651 int divider, fraction;
2652
2653 if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2654 /* 24 MHz */
2655 divider = 24000;
2656 fraction = 0;
2657 } else {
2658 /* 19.2 MHz */
2659 divider = 19000;
2660 fraction = 200;
2661 }
2662
2663 rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2664 if (fraction)
2665 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2666 fraction) - 1);
2667
2668 I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2669 return divider + fraction;
2670}
2671
4ef99abd
AS		 2672static int icp_rawclk(struct drm_i915_private *dev_priv)
2673{
2674 u32 rawclk;
2675 int divider, numerator, denominator, frequency;
2676
2677 if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2678 frequency = 24000;
2679 divider = 23;
2680 numerator = 0;
2681 denominator = 0;
2682 } else {
2683 frequency = 19200;
2684 divider = 18;
2685 numerator = 1;
2686 denominator = 4;
2687 }
2688
2689 rawclk = CNP_RAWCLK_DIV(divider) | ICP_RAWCLK_NUM(numerator) |
2690 ICP_RAWCLK_DEN(denominator);
2691
2692 I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2693 return frequency;
2694}
2695
7ff89ca2
VS		 2696static int pch_rawclk(struct drm_i915_private *dev_priv)
2697{
2698 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2699}
2700
2701static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2702{
2703 /* RAWCLK_FREQ_VLV register updated from power well code */
2704 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2705 CCK_DISPLAY_REF_CLOCK_CONTROL);
2706}
2707
2708static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2709{
2710 uint32_t clkcfg;
2711
2712 /* hrawclock is 1/4 the FSB frequency */
2713 clkcfg = I915_READ(CLKCFG);
2714 switch (clkcfg & CLKCFG_FSB_MASK) {
2715 case CLKCFG_FSB_400:
2716 return 100000;
2717 case CLKCFG_FSB_533:
2718 return 133333;
2719 case CLKCFG_FSB_667:
2720 return 166667;
2721 case CLKCFG_FSB_800:
2722 return 200000;
2723 case CLKCFG_FSB_1067:
6f38123e 2724 case CLKCFG_FSB_1067_ALT:
7ff89ca2
VS		 2725 return 266667;
2726 case CLKCFG_FSB_1333:
6f38123e 2727 case CLKCFG_FSB_1333_ALT:
7ff89ca2 2728 return 333333;
7ff89ca2
VS		 2729 default:
2730 return 133333;
2731 }
2732}
2733
2734/**
2735 * intel_update_rawclk - Determine the current RAWCLK frequency
2736 * @dev_priv: i915 device
2737 *
2738 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2739 * frequency clock so this needs to done only once.
2740 */
2741void intel_update_rawclk(struct drm_i915_private *dev_priv)
2742{
4ef99abd
AS		 2743 if (HAS_PCH_ICP(dev_priv))
2744 dev_priv->rawclk_freq = icp_rawclk(dev_priv);
2745 else if (HAS_PCH_CNP(dev_priv))
9d81a997
RV		 2746 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2747 else if (HAS_PCH_SPLIT(dev_priv))
7ff89ca2
VS		 2748 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2749 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2750 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2751 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2752 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2753 else
2754 /* no rawclk on other platforms, or no need to know it */
2755 return;
2756
2757 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2758}
2759
2760/**
2761 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2762 * @dev_priv: i915 device
2763 */
2764void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2765{
b0587e4d
VS		 2766 if (IS_CHERRYVIEW(dev_priv)) {
2767 dev_priv->display.set_cdclk = chv_set_cdclk;
2768 dev_priv->display.modeset_calc_cdclk =
2769 vlv_modeset_calc_cdclk;
2770 } else if (IS_VALLEYVIEW(dev_priv)) {
2771 dev_priv->display.set_cdclk = vlv_set_cdclk;
7ff89ca2
VS		 2772 dev_priv->display.modeset_calc_cdclk =
2773 vlv_modeset_calc_cdclk;
2774 } else if (IS_BROADWELL(dev_priv)) {
b0587e4d 2775 dev_priv->display.set_cdclk = bdw_set_cdclk;
7ff89ca2
VS		 2776 dev_priv->display.modeset_calc_cdclk =
2777 bdw_modeset_calc_cdclk;
2778 } else if (IS_GEN9_LP(dev_priv)) {
b0587e4d 2779 dev_priv->display.set_cdclk = bxt_set_cdclk;
7ff89ca2
VS		 2780 dev_priv->display.modeset_calc_cdclk =
2781 bxt_modeset_calc_cdclk;
2782 } else if (IS_GEN9_BC(dev_priv)) {
b0587e4d 2783 dev_priv->display.set_cdclk = skl_set_cdclk;
7ff89ca2
VS		 2784 dev_priv->display.modeset_calc_cdclk =
2785 skl_modeset_calc_cdclk;
d1999e9e
RV		 2786 } else if (IS_CANNONLAKE(dev_priv)) {
2787 dev_priv->display.set_cdclk = cnl_set_cdclk;
2788 dev_priv->display.modeset_calc_cdclk =
2789 cnl_modeset_calc_cdclk;
186a277e
PZ		 2790 } else if (IS_ICELAKE(dev_priv)) {
2791 dev_priv->display.set_cdclk = icl_set_cdclk;
2792 dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
7ff89ca2
VS		 2793 }
2794
186a277e
PZ		 2795 if (IS_ICELAKE(dev_priv))
2796 dev_priv->display.get_cdclk = icl_get_cdclk;
2797 else if (IS_CANNONLAKE(dev_priv))
945f2672
VS		 2798 dev_priv->display.get_cdclk = cnl_get_cdclk;
2799 else if (IS_GEN9_BC(dev_priv))
7ff89ca2
VS		 2800 dev_priv->display.get_cdclk = skl_get_cdclk;
2801 else if (IS_GEN9_LP(dev_priv))
2802 dev_priv->display.get_cdclk = bxt_get_cdclk;
2803 else if (IS_BROADWELL(dev_priv))
2804 dev_priv->display.get_cdclk = bdw_get_cdclk;
2805 else if (IS_HASWELL(dev_priv))
2806 dev_priv->display.get_cdclk = hsw_get_cdclk;
2807 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2808 dev_priv->display.get_cdclk = vlv_get_cdclk;
2809 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2810 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2811 else if (IS_GEN5(dev_priv))
2812 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2813 else if (IS_GM45(dev_priv))
2814 dev_priv->display.get_cdclk = gm45_get_cdclk;
6b9e441d 2815 else if (IS_G45(dev_priv))
7ff89ca2
VS		 2816 dev_priv->display.get_cdclk = g33_get_cdclk;
2817 else if (IS_I965GM(dev_priv))
2818 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2819 else if (IS_I965G(dev_priv))
2820 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2821 else if (IS_PINEVIEW(dev_priv))
2822 dev_priv->display.get_cdclk = pnv_get_cdclk;
2823 else if (IS_G33(dev_priv))
2824 dev_priv->display.get_cdclk = g33_get_cdclk;
2825 else if (IS_I945GM(dev_priv))
2826 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2827 else if (IS_I945G(dev_priv))
2828 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2829 else if (IS_I915GM(dev_priv))
2830 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2831 else if (IS_I915G(dev_priv))
2832 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2833 else if (IS_I865G(dev_priv))
2834 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2835 else if (IS_I85X(dev_priv))
2836 dev_priv->display.get_cdclk = i85x_get_cdclk;
2837 else if (IS_I845G(dev_priv))
2838 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2839 else { /* 830 */
2840 WARN(!IS_I830(dev_priv),
2841 "Unknown platform. Assuming 133 MHz CDCLK\n");
2842 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2843 }
2844}
Linux 6.x block layer and io_uring tree(s)