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7ff89ca2 VS |
1 | /* |
2 | * Copyright © 2006-2017 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "intel_drv.h" | |
25 | ||
26 | /** | |
27 | * DOC: CDCLK / RAWCLK | |
28 | * | |
29 | * The display engine uses several different clocks to do its work. There | |
30 | * are two main clocks involved that aren't directly related to the actual | |
31 | * pixel clock or any symbol/bit clock of the actual output port. These | |
32 | * are the core display clock (CDCLK) and RAWCLK. | |
33 | * | |
34 | * CDCLK clocks most of the display pipe logic, and thus its frequency | |
35 | * must be high enough to support the rate at which pixels are flowing | |
36 | * through the pipes. Downscaling must also be accounted as that increases | |
37 | * the effective pixel rate. | |
38 | * | |
39 | * On several platforms the CDCLK frequency can be changed dynamically | |
40 | * to minimize power consumption for a given display configuration. | |
41 | * Typically changes to the CDCLK frequency require all the display pipes | |
42 | * to be shut down while the frequency is being changed. | |
43 | * | |
44 | * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. | |
45 | * DMC will not change the active CDCLK frequency however, so that part | |
46 | * will still be performed by the driver directly. | |
47 | * | |
48 | * RAWCLK is a fixed frequency clock, often used by various auxiliary | |
49 | * blocks such as AUX CH or backlight PWM. Hence the only thing we | |
50 | * really need to know about RAWCLK is its frequency so that various | |
51 | * dividers can be programmed correctly. | |
52 | */ | |
53 | ||
49cd97a3 VS |
54 | static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, |
55 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 56 | { |
49cd97a3 | 57 | cdclk_state->cdclk = 133333; |
7ff89ca2 VS |
58 | } |
59 | ||
49cd97a3 VS |
60 | static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, |
61 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 62 | { |
49cd97a3 | 63 | cdclk_state->cdclk = 200000; |
7ff89ca2 VS |
64 | } |
65 | ||
49cd97a3 VS |
66 | static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, |
67 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 68 | { |
49cd97a3 | 69 | cdclk_state->cdclk = 266667; |
7ff89ca2 VS |
70 | } |
71 | ||
49cd97a3 VS |
72 | static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, |
73 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 74 | { |
49cd97a3 | 75 | cdclk_state->cdclk = 333333; |
7ff89ca2 VS |
76 | } |
77 | ||
49cd97a3 VS |
78 | static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, |
79 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 80 | { |
49cd97a3 | 81 | cdclk_state->cdclk = 400000; |
7ff89ca2 VS |
82 | } |
83 | ||
49cd97a3 VS |
84 | static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, |
85 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 86 | { |
49cd97a3 | 87 | cdclk_state->cdclk = 450000; |
7ff89ca2 VS |
88 | } |
89 | ||
49cd97a3 VS |
90 | static void i85x_get_cdclk(struct drm_i915_private *dev_priv, |
91 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
92 | { |
93 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
94 | u16 hpllcc = 0; | |
95 | ||
96 | /* | |
97 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
98 | * encoding is different :( | |
99 | * FIXME is this the right way to detect 852GM/852GMV? | |
100 | */ | |
49cd97a3 VS |
101 | if (pdev->revision == 0x1) { |
102 | cdclk_state->cdclk = 133333; | |
103 | return; | |
104 | } | |
7ff89ca2 VS |
105 | |
106 | pci_bus_read_config_word(pdev->bus, | |
107 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
108 | ||
109 | /* Assume that the hardware is in the high speed state. This | |
110 | * should be the default. | |
111 | */ | |
112 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
113 | case GC_CLOCK_133_200: | |
114 | case GC_CLOCK_133_200_2: | |
115 | case GC_CLOCK_100_200: | |
49cd97a3 VS |
116 | cdclk_state->cdclk = 200000; |
117 | break; | |
7ff89ca2 | 118 | case GC_CLOCK_166_250: |
49cd97a3 VS |
119 | cdclk_state->cdclk = 250000; |
120 | break; | |
7ff89ca2 | 121 | case GC_CLOCK_100_133: |
49cd97a3 VS |
122 | cdclk_state->cdclk = 133333; |
123 | break; | |
7ff89ca2 VS |
124 | case GC_CLOCK_133_266: |
125 | case GC_CLOCK_133_266_2: | |
126 | case GC_CLOCK_166_266: | |
49cd97a3 VS |
127 | cdclk_state->cdclk = 266667; |
128 | break; | |
7ff89ca2 | 129 | } |
7ff89ca2 VS |
130 | } |
131 | ||
49cd97a3 VS |
132 | static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, |
133 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
134 | { |
135 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
136 | u16 gcfgc = 0; | |
137 | ||
138 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
139 | ||
49cd97a3 VS |
140 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { |
141 | cdclk_state->cdclk = 133333; | |
142 | return; | |
143 | } | |
7ff89ca2 VS |
144 | |
145 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
146 | case GC_DISPLAY_CLOCK_333_320_MHZ: | |
49cd97a3 VS |
147 | cdclk_state->cdclk = 333333; |
148 | break; | |
7ff89ca2 VS |
149 | default: |
150 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
49cd97a3 VS |
151 | cdclk_state->cdclk = 190000; |
152 | break; | |
7ff89ca2 VS |
153 | } |
154 | } | |
155 | ||
49cd97a3 VS |
156 | static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, |
157 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
158 | { |
159 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
160 | u16 gcfgc = 0; | |
161 | ||
162 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
163 | ||
49cd97a3 VS |
164 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { |
165 | cdclk_state->cdclk = 133333; | |
166 | return; | |
167 | } | |
7ff89ca2 VS |
168 | |
169 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
170 | case GC_DISPLAY_CLOCK_333_320_MHZ: | |
49cd97a3 VS |
171 | cdclk_state->cdclk = 320000; |
172 | break; | |
7ff89ca2 VS |
173 | default: |
174 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
49cd97a3 VS |
175 | cdclk_state->cdclk = 200000; |
176 | break; | |
7ff89ca2 VS |
177 | } |
178 | } | |
179 | ||
180 | static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) | |
181 | { | |
182 | static const unsigned int blb_vco[8] = { | |
183 | [0] = 3200000, | |
184 | [1] = 4000000, | |
185 | [2] = 5333333, | |
186 | [3] = 4800000, | |
187 | [4] = 6400000, | |
188 | }; | |
189 | static const unsigned int pnv_vco[8] = { | |
190 | [0] = 3200000, | |
191 | [1] = 4000000, | |
192 | [2] = 5333333, | |
193 | [3] = 4800000, | |
194 | [4] = 2666667, | |
195 | }; | |
196 | static const unsigned int cl_vco[8] = { | |
197 | [0] = 3200000, | |
198 | [1] = 4000000, | |
199 | [2] = 5333333, | |
200 | [3] = 6400000, | |
201 | [4] = 3333333, | |
202 | [5] = 3566667, | |
203 | [6] = 4266667, | |
204 | }; | |
205 | static const unsigned int elk_vco[8] = { | |
206 | [0] = 3200000, | |
207 | [1] = 4000000, | |
208 | [2] = 5333333, | |
209 | [3] = 4800000, | |
210 | }; | |
211 | static const unsigned int ctg_vco[8] = { | |
212 | [0] = 3200000, | |
213 | [1] = 4000000, | |
214 | [2] = 5333333, | |
215 | [3] = 6400000, | |
216 | [4] = 2666667, | |
217 | [5] = 4266667, | |
218 | }; | |
219 | const unsigned int *vco_table; | |
220 | unsigned int vco; | |
221 | uint8_t tmp = 0; | |
222 | ||
223 | /* FIXME other chipsets? */ | |
224 | if (IS_GM45(dev_priv)) | |
225 | vco_table = ctg_vco; | |
6b9e441d | 226 | else if (IS_G45(dev_priv)) |
7ff89ca2 VS |
227 | vco_table = elk_vco; |
228 | else if (IS_I965GM(dev_priv)) | |
229 | vco_table = cl_vco; | |
230 | else if (IS_PINEVIEW(dev_priv)) | |
231 | vco_table = pnv_vco; | |
232 | else if (IS_G33(dev_priv)) | |
233 | vco_table = blb_vco; | |
234 | else | |
235 | return 0; | |
236 | ||
237 | tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); | |
238 | ||
239 | vco = vco_table[tmp & 0x7]; | |
240 | if (vco == 0) | |
241 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
242 | else | |
243 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
244 | ||
245 | return vco; | |
246 | } | |
247 | ||
49cd97a3 VS |
248 | static void g33_get_cdclk(struct drm_i915_private *dev_priv, |
249 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
250 | { |
251 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
252 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
253 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
254 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
255 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
256 | const uint8_t *div_table; | |
49cd97a3 | 257 | unsigned int cdclk_sel; |
7ff89ca2 VS |
258 | uint16_t tmp = 0; |
259 | ||
49cd97a3 VS |
260 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
261 | ||
7ff89ca2 VS |
262 | pci_read_config_word(pdev, GCFGC, &tmp); |
263 | ||
264 | cdclk_sel = (tmp >> 4) & 0x7; | |
265 | ||
266 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
267 | goto fail; | |
268 | ||
49cd97a3 | 269 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
270 | case 3200000: |
271 | div_table = div_3200; | |
272 | break; | |
273 | case 4000000: | |
274 | div_table = div_4000; | |
275 | break; | |
276 | case 4800000: | |
277 | div_table = div_4800; | |
278 | break; | |
279 | case 5333333: | |
280 | div_table = div_5333; | |
281 | break; | |
282 | default: | |
283 | goto fail; | |
284 | } | |
285 | ||
49cd97a3 VS |
286 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, |
287 | div_table[cdclk_sel]); | |
288 | return; | |
7ff89ca2 VS |
289 | |
290 | fail: | |
291 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", | |
49cd97a3 VS |
292 | cdclk_state->vco, tmp); |
293 | cdclk_state->cdclk = 190476; | |
7ff89ca2 VS |
294 | } |
295 | ||
49cd97a3 VS |
296 | static void pnv_get_cdclk(struct drm_i915_private *dev_priv, |
297 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
298 | { |
299 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
300 | u16 gcfgc = 0; | |
301 | ||
302 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
303 | ||
304 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
305 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
49cd97a3 VS |
306 | cdclk_state->cdclk = 266667; |
307 | break; | |
7ff89ca2 | 308 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
49cd97a3 VS |
309 | cdclk_state->cdclk = 333333; |
310 | break; | |
7ff89ca2 | 311 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
49cd97a3 VS |
312 | cdclk_state->cdclk = 444444; |
313 | break; | |
7ff89ca2 | 314 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
49cd97a3 VS |
315 | cdclk_state->cdclk = 200000; |
316 | break; | |
7ff89ca2 VS |
317 | default: |
318 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
f0d759f0 | 319 | /* fall through */ |
7ff89ca2 | 320 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
49cd97a3 VS |
321 | cdclk_state->cdclk = 133333; |
322 | break; | |
7ff89ca2 | 323 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
49cd97a3 VS |
324 | cdclk_state->cdclk = 166667; |
325 | break; | |
7ff89ca2 VS |
326 | } |
327 | } | |
328 | ||
49cd97a3 VS |
329 | static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, |
330 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
331 | { |
332 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
333 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
334 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
335 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
336 | const uint8_t *div_table; | |
49cd97a3 | 337 | unsigned int cdclk_sel; |
7ff89ca2 VS |
338 | uint16_t tmp = 0; |
339 | ||
49cd97a3 VS |
340 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
341 | ||
7ff89ca2 VS |
342 | pci_read_config_word(pdev, GCFGC, &tmp); |
343 | ||
344 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
345 | ||
346 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
347 | goto fail; | |
348 | ||
49cd97a3 | 349 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
350 | case 3200000: |
351 | div_table = div_3200; | |
352 | break; | |
353 | case 4000000: | |
354 | div_table = div_4000; | |
355 | break; | |
356 | case 5333333: | |
357 | div_table = div_5333; | |
358 | break; | |
359 | default: | |
360 | goto fail; | |
361 | } | |
362 | ||
49cd97a3 VS |
363 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, |
364 | div_table[cdclk_sel]); | |
365 | return; | |
7ff89ca2 VS |
366 | |
367 | fail: | |
368 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", | |
49cd97a3 VS |
369 | cdclk_state->vco, tmp); |
370 | cdclk_state->cdclk = 200000; | |
7ff89ca2 VS |
371 | } |
372 | ||
49cd97a3 VS |
373 | static void gm45_get_cdclk(struct drm_i915_private *dev_priv, |
374 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
375 | { |
376 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
49cd97a3 | 377 | unsigned int cdclk_sel; |
7ff89ca2 VS |
378 | uint16_t tmp = 0; |
379 | ||
49cd97a3 VS |
380 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
381 | ||
7ff89ca2 VS |
382 | pci_read_config_word(pdev, GCFGC, &tmp); |
383 | ||
384 | cdclk_sel = (tmp >> 12) & 0x1; | |
385 | ||
49cd97a3 | 386 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
387 | case 2666667: |
388 | case 4000000: | |
389 | case 5333333: | |
49cd97a3 VS |
390 | cdclk_state->cdclk = cdclk_sel ? 333333 : 222222; |
391 | break; | |
7ff89ca2 | 392 | case 3200000: |
49cd97a3 VS |
393 | cdclk_state->cdclk = cdclk_sel ? 320000 : 228571; |
394 | break; | |
7ff89ca2 VS |
395 | default: |
396 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", | |
49cd97a3 VS |
397 | cdclk_state->vco, tmp); |
398 | cdclk_state->cdclk = 222222; | |
399 | break; | |
7ff89ca2 VS |
400 | } |
401 | } | |
402 | ||
49cd97a3 VS |
403 | static void hsw_get_cdclk(struct drm_i915_private *dev_priv, |
404 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
405 | { |
406 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
407 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
408 | ||
409 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
49cd97a3 | 410 | cdclk_state->cdclk = 800000; |
7ff89ca2 | 411 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
49cd97a3 | 412 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 413 | else if (freq == LCPLL_CLK_FREQ_450) |
49cd97a3 | 414 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 415 | else if (IS_HSW_ULT(dev_priv)) |
49cd97a3 | 416 | cdclk_state->cdclk = 337500; |
7ff89ca2 | 417 | else |
49cd97a3 | 418 | cdclk_state->cdclk = 540000; |
7ff89ca2 VS |
419 | } |
420 | ||
d305e061 | 421 | static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) |
7ff89ca2 VS |
422 | { |
423 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? | |
424 | 333333 : 320000; | |
7ff89ca2 VS |
425 | |
426 | /* | |
427 | * We seem to get an unstable or solid color picture at 200MHz. | |
428 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
429 | * are off. | |
430 | */ | |
d305e061 | 431 | if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) |
7ff89ca2 | 432 | return 400000; |
d305e061 | 433 | else if (min_cdclk > 266667) |
7ff89ca2 | 434 | return freq_320; |
d305e061 | 435 | else if (min_cdclk > 0) |
7ff89ca2 VS |
436 | return 266667; |
437 | else | |
438 | return 200000; | |
439 | } | |
440 | ||
999c5766 VS |
441 | static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) |
442 | { | |
443 | if (IS_VALLEYVIEW(dev_priv)) { | |
444 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ | |
445 | return 2; | |
446 | else if (cdclk >= 266667) | |
447 | return 1; | |
448 | else | |
449 | return 0; | |
450 | } else { | |
451 | /* | |
452 | * Specs are full of misinformation, but testing on actual | |
453 | * hardware has shown that we just need to write the desired | |
454 | * CCK divider into the Punit register. | |
455 | */ | |
456 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
457 | } | |
458 | } | |
459 | ||
49cd97a3 VS |
460 | static void vlv_get_cdclk(struct drm_i915_private *dev_priv, |
461 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 462 | { |
999c5766 VS |
463 | u32 val; |
464 | ||
49cd97a3 VS |
465 | cdclk_state->vco = vlv_get_hpll_vco(dev_priv); |
466 | cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", | |
467 | CCK_DISPLAY_CLOCK_CONTROL, | |
468 | cdclk_state->vco); | |
999c5766 VS |
469 | |
470 | mutex_lock(&dev_priv->pcu_lock); | |
471 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
472 | mutex_unlock(&dev_priv->pcu_lock); | |
473 | ||
474 | if (IS_VALLEYVIEW(dev_priv)) | |
475 | cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >> | |
476 | DSPFREQGUAR_SHIFT; | |
477 | else | |
478 | cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> | |
479 | DSPFREQGUAR_SHIFT_CHV; | |
7ff89ca2 VS |
480 | } |
481 | ||
482 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) | |
483 | { | |
484 | unsigned int credits, default_credits; | |
485 | ||
486 | if (IS_CHERRYVIEW(dev_priv)) | |
487 | default_credits = PFI_CREDIT(12); | |
488 | else | |
489 | default_credits = PFI_CREDIT(8); | |
490 | ||
49cd97a3 | 491 | if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { |
7ff89ca2 VS |
492 | /* CHV suggested value is 31 or 63 */ |
493 | if (IS_CHERRYVIEW(dev_priv)) | |
494 | credits = PFI_CREDIT_63; | |
495 | else | |
496 | credits = PFI_CREDIT(15); | |
497 | } else { | |
498 | credits = default_credits; | |
499 | } | |
500 | ||
501 | /* | |
502 | * WA - write default credits before re-programming | |
503 | * FIXME: should we also set the resend bit here? | |
504 | */ | |
505 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
506 | default_credits); | |
507 | ||
508 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
509 | credits | PFI_CREDIT_RESEND); | |
510 | ||
511 | /* | |
512 | * FIXME is this guaranteed to clear | |
513 | * immediately or should we poll for it? | |
514 | */ | |
515 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
516 | } | |
517 | ||
83c5fda7 VS |
518 | static void vlv_set_cdclk(struct drm_i915_private *dev_priv, |
519 | const struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 520 | { |
83c5fda7 | 521 | int cdclk = cdclk_state->cdclk; |
999c5766 | 522 | u32 val, cmd = cdclk_state->voltage_level; |
0e6e0be4 | 523 | intel_wakeref_t wakeref; |
7ff89ca2 | 524 | |
0c9f353f VS |
525 | switch (cdclk) { |
526 | case 400000: | |
527 | case 333333: | |
528 | case 320000: | |
529 | case 266667: | |
530 | case 200000: | |
531 | break; | |
532 | default: | |
533 | MISSING_CASE(cdclk); | |
534 | return; | |
535 | } | |
536 | ||
886015a0 GKB |
537 | /* There are cases where we can end up here with power domains |
538 | * off and a CDCLK frequency other than the minimum, like when | |
539 | * issuing a modeset without actually changing any display after | |
540 | * a system suspend. So grab the PIPE-A domain, which covers | |
541 | * the HW blocks needed for the following programming. | |
542 | */ | |
0e6e0be4 | 543 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); |
886015a0 | 544 | |
9f817501 | 545 | mutex_lock(&dev_priv->pcu_lock); |
7ff89ca2 VS |
546 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
547 | val &= ~DSPFREQGUAR_MASK; | |
548 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
549 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
550 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
551 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
552 | 50)) { | |
553 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
554 | } | |
9f817501 | 555 | mutex_unlock(&dev_priv->pcu_lock); |
7ff89ca2 VS |
556 | |
557 | mutex_lock(&dev_priv->sb_lock); | |
558 | ||
559 | if (cdclk == 400000) { | |
560 | u32 divider; | |
561 | ||
562 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, | |
563 | cdclk) - 1; | |
564 | ||
565 | /* adjust cdclk divider */ | |
566 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
567 | val &= ~CCK_FREQUENCY_VALUES; | |
568 | val |= divider; | |
569 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
570 | ||
571 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
572 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
573 | 50)) | |
574 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
575 | } | |
576 | ||
577 | /* adjust self-refresh exit latency value */ | |
578 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
579 | val &= ~0x7f; | |
580 | ||
581 | /* | |
582 | * For high bandwidth configs, we set a higher latency in the bunit | |
583 | * so that the core display fetch happens in time to avoid underruns. | |
584 | */ | |
585 | if (cdclk == 400000) | |
586 | val |= 4500 / 250; /* 4.5 usec */ | |
587 | else | |
588 | val |= 3000 / 250; /* 3.0 usec */ | |
589 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
590 | ||
591 | mutex_unlock(&dev_priv->sb_lock); | |
592 | ||
593 | intel_update_cdclk(dev_priv); | |
1a5301a5 VS |
594 | |
595 | vlv_program_pfi_credits(dev_priv); | |
886015a0 | 596 | |
0e6e0be4 | 597 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref); |
7ff89ca2 VS |
598 | } |
599 | ||
83c5fda7 VS |
600 | static void chv_set_cdclk(struct drm_i915_private *dev_priv, |
601 | const struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 602 | { |
83c5fda7 | 603 | int cdclk = cdclk_state->cdclk; |
999c5766 | 604 | u32 val, cmd = cdclk_state->voltage_level; |
0e6e0be4 | 605 | intel_wakeref_t wakeref; |
7ff89ca2 | 606 | |
7ff89ca2 VS |
607 | switch (cdclk) { |
608 | case 333333: | |
609 | case 320000: | |
610 | case 266667: | |
611 | case 200000: | |
612 | break; | |
613 | default: | |
614 | MISSING_CASE(cdclk); | |
615 | return; | |
616 | } | |
617 | ||
886015a0 GKB |
618 | /* There are cases where we can end up here with power domains |
619 | * off and a CDCLK frequency other than the minimum, like when | |
620 | * issuing a modeset without actually changing any display after | |
621 | * a system suspend. So grab the PIPE-A domain, which covers | |
622 | * the HW blocks needed for the following programming. | |
623 | */ | |
0e6e0be4 | 624 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); |
886015a0 | 625 | |
9f817501 | 626 | mutex_lock(&dev_priv->pcu_lock); |
7ff89ca2 VS |
627 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
628 | val &= ~DSPFREQGUAR_MASK_CHV; | |
629 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
630 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
631 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
632 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
633 | 50)) { | |
634 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
635 | } | |
9f817501 | 636 | mutex_unlock(&dev_priv->pcu_lock); |
7ff89ca2 VS |
637 | |
638 | intel_update_cdclk(dev_priv); | |
1a5301a5 VS |
639 | |
640 | vlv_program_pfi_credits(dev_priv); | |
886015a0 | 641 | |
0e6e0be4 | 642 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref); |
7ff89ca2 VS |
643 | } |
644 | ||
d305e061 | 645 | static int bdw_calc_cdclk(int min_cdclk) |
7ff89ca2 | 646 | { |
d305e061 | 647 | if (min_cdclk > 540000) |
7ff89ca2 | 648 | return 675000; |
d305e061 | 649 | else if (min_cdclk > 450000) |
7ff89ca2 | 650 | return 540000; |
d305e061 | 651 | else if (min_cdclk > 337500) |
7ff89ca2 VS |
652 | return 450000; |
653 | else | |
654 | return 337500; | |
655 | } | |
656 | ||
d7ffaeef VS |
657 | static u8 bdw_calc_voltage_level(int cdclk) |
658 | { | |
659 | switch (cdclk) { | |
660 | default: | |
661 | case 337500: | |
662 | return 2; | |
663 | case 450000: | |
664 | return 0; | |
665 | case 540000: | |
666 | return 1; | |
667 | case 675000: | |
668 | return 3; | |
669 | } | |
670 | } | |
671 | ||
49cd97a3 VS |
672 | static void bdw_get_cdclk(struct drm_i915_private *dev_priv, |
673 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
674 | { |
675 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
676 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
677 | ||
678 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
49cd97a3 | 679 | cdclk_state->cdclk = 800000; |
7ff89ca2 | 680 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
49cd97a3 | 681 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 682 | else if (freq == LCPLL_CLK_FREQ_450) |
49cd97a3 | 683 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 684 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) |
49cd97a3 | 685 | cdclk_state->cdclk = 540000; |
7ff89ca2 | 686 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) |
49cd97a3 | 687 | cdclk_state->cdclk = 337500; |
7ff89ca2 | 688 | else |
49cd97a3 | 689 | cdclk_state->cdclk = 675000; |
d7ffaeef VS |
690 | |
691 | /* | |
692 | * Can't read this out :( Let's assume it's | |
693 | * at least what the CDCLK frequency requires. | |
694 | */ | |
695 | cdclk_state->voltage_level = | |
696 | bdw_calc_voltage_level(cdclk_state->cdclk); | |
7ff89ca2 VS |
697 | } |
698 | ||
83c5fda7 VS |
699 | static void bdw_set_cdclk(struct drm_i915_private *dev_priv, |
700 | const struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 701 | { |
83c5fda7 | 702 | int cdclk = cdclk_state->cdclk; |
d7ffaeef | 703 | uint32_t val; |
7ff89ca2 VS |
704 | int ret; |
705 | ||
706 | if (WARN((I915_READ(LCPLL_CTL) & | |
707 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
708 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
709 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
710 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
711 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
712 | return; | |
713 | ||
9f817501 | 714 | mutex_lock(&dev_priv->pcu_lock); |
7ff89ca2 VS |
715 | ret = sandybridge_pcode_write(dev_priv, |
716 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9f817501 | 717 | mutex_unlock(&dev_priv->pcu_lock); |
7ff89ca2 VS |
718 | if (ret) { |
719 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
720 | return; | |
721 | } | |
722 | ||
723 | val = I915_READ(LCPLL_CTL); | |
724 | val |= LCPLL_CD_SOURCE_FCLK; | |
725 | I915_WRITE(LCPLL_CTL, val); | |
726 | ||
3164888a ML |
727 | /* |
728 | * According to the spec, it should be enough to poll for this 1 us. | |
729 | * However, extensive testing shows that this can take longer. | |
730 | */ | |
7ff89ca2 | 731 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
3164888a | 732 | LCPLL_CD_SOURCE_FCLK_DONE, 100)) |
7ff89ca2 VS |
733 | DRM_ERROR("Switching to FCLK failed\n"); |
734 | ||
735 | val = I915_READ(LCPLL_CTL); | |
736 | val &= ~LCPLL_CLK_FREQ_MASK; | |
737 | ||
738 | switch (cdclk) { | |
2b58417f VS |
739 | default: |
740 | MISSING_CASE(cdclk); | |
741 | /* fall through */ | |
742 | case 337500: | |
743 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
2b58417f | 744 | break; |
7ff89ca2 VS |
745 | case 450000: |
746 | val |= LCPLL_CLK_FREQ_450; | |
7ff89ca2 VS |
747 | break; |
748 | case 540000: | |
749 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
7ff89ca2 | 750 | break; |
7ff89ca2 VS |
751 | case 675000: |
752 | val |= LCPLL_CLK_FREQ_675_BDW; | |
7ff89ca2 | 753 | break; |
7ff89ca2 VS |
754 | } |
755 | ||
756 | I915_WRITE(LCPLL_CTL, val); | |
757 | ||
758 | val = I915_READ(LCPLL_CTL); | |
759 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
760 | I915_WRITE(LCPLL_CTL, val); | |
761 | ||
762 | if (wait_for_us((I915_READ(LCPLL_CTL) & | |
763 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
764 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
765 | ||
9f817501 | 766 | mutex_lock(&dev_priv->pcu_lock); |
d7ffaeef VS |
767 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
768 | cdclk_state->voltage_level); | |
9f817501 | 769 | mutex_unlock(&dev_priv->pcu_lock); |
7ff89ca2 VS |
770 | |
771 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); | |
772 | ||
773 | intel_update_cdclk(dev_priv); | |
7ff89ca2 VS |
774 | } |
775 | ||
d305e061 | 776 | static int skl_calc_cdclk(int min_cdclk, int vco) |
7ff89ca2 VS |
777 | { |
778 | if (vco == 8640000) { | |
d305e061 | 779 | if (min_cdclk > 540000) |
7ff89ca2 | 780 | return 617143; |
d305e061 | 781 | else if (min_cdclk > 432000) |
7ff89ca2 | 782 | return 540000; |
d305e061 | 783 | else if (min_cdclk > 308571) |
7ff89ca2 VS |
784 | return 432000; |
785 | else | |
786 | return 308571; | |
787 | } else { | |
d305e061 | 788 | if (min_cdclk > 540000) |
7ff89ca2 | 789 | return 675000; |
d305e061 | 790 | else if (min_cdclk > 450000) |
7ff89ca2 | 791 | return 540000; |
d305e061 | 792 | else if (min_cdclk > 337500) |
7ff89ca2 VS |
793 | return 450000; |
794 | else | |
795 | return 337500; | |
796 | } | |
797 | } | |
798 | ||
2aa97491 VS |
799 | static u8 skl_calc_voltage_level(int cdclk) |
800 | { | |
801 | switch (cdclk) { | |
802 | default: | |
803 | case 308571: | |
804 | case 337500: | |
805 | return 0; | |
806 | case 450000: | |
807 | case 432000: | |
808 | return 1; | |
809 | case 540000: | |
810 | return 2; | |
811 | case 617143: | |
812 | case 675000: | |
813 | return 3; | |
814 | } | |
815 | } | |
816 | ||
49cd97a3 VS |
817 | static void skl_dpll0_update(struct drm_i915_private *dev_priv, |
818 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
819 | { |
820 | u32 val; | |
821 | ||
49cd97a3 VS |
822 | cdclk_state->ref = 24000; |
823 | cdclk_state->vco = 0; | |
7ff89ca2 VS |
824 | |
825 | val = I915_READ(LCPLL1_CTL); | |
826 | if ((val & LCPLL_PLL_ENABLE) == 0) | |
827 | return; | |
828 | ||
829 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) | |
830 | return; | |
831 | ||
832 | val = I915_READ(DPLL_CTRL1); | |
833 | ||
834 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | | |
835 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
836 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
837 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
838 | return; | |
839 | ||
840 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { | |
841 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
842 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
843 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
844 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
49cd97a3 | 845 | cdclk_state->vco = 8100000; |
7ff89ca2 VS |
846 | break; |
847 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
848 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
49cd97a3 | 849 | cdclk_state->vco = 8640000; |
7ff89ca2 VS |
850 | break; |
851 | default: | |
852 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
853 | break; | |
854 | } | |
855 | } | |
856 | ||
49cd97a3 VS |
857 | static void skl_get_cdclk(struct drm_i915_private *dev_priv, |
858 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
859 | { |
860 | u32 cdctl; | |
861 | ||
49cd97a3 | 862 | skl_dpll0_update(dev_priv, cdclk_state); |
7ff89ca2 | 863 | |
b6c51c3e | 864 | cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; |
49cd97a3 VS |
865 | |
866 | if (cdclk_state->vco == 0) | |
2aa97491 | 867 | goto out; |
7ff89ca2 VS |
868 | |
869 | cdctl = I915_READ(CDCLK_CTL); | |
870 | ||
49cd97a3 | 871 | if (cdclk_state->vco == 8640000) { |
7ff89ca2 VS |
872 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
873 | case CDCLK_FREQ_450_432: | |
49cd97a3 VS |
874 | cdclk_state->cdclk = 432000; |
875 | break; | |
7ff89ca2 | 876 | case CDCLK_FREQ_337_308: |
49cd97a3 VS |
877 | cdclk_state->cdclk = 308571; |
878 | break; | |
7ff89ca2 | 879 | case CDCLK_FREQ_540: |
49cd97a3 VS |
880 | cdclk_state->cdclk = 540000; |
881 | break; | |
7ff89ca2 | 882 | case CDCLK_FREQ_675_617: |
49cd97a3 VS |
883 | cdclk_state->cdclk = 617143; |
884 | break; | |
7ff89ca2 VS |
885 | default: |
886 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); | |
49cd97a3 | 887 | break; |
7ff89ca2 VS |
888 | } |
889 | } else { | |
890 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
891 | case CDCLK_FREQ_450_432: | |
49cd97a3 VS |
892 | cdclk_state->cdclk = 450000; |
893 | break; | |
7ff89ca2 | 894 | case CDCLK_FREQ_337_308: |
49cd97a3 VS |
895 | cdclk_state->cdclk = 337500; |
896 | break; | |
7ff89ca2 | 897 | case CDCLK_FREQ_540: |
49cd97a3 VS |
898 | cdclk_state->cdclk = 540000; |
899 | break; | |
7ff89ca2 | 900 | case CDCLK_FREQ_675_617: |
49cd97a3 VS |
901 | cdclk_state->cdclk = 675000; |
902 | break; | |
7ff89ca2 VS |
903 | default: |
904 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); | |
49cd97a3 | 905 | break; |
7ff89ca2 VS |
906 | } |
907 | } | |
2aa97491 VS |
908 | |
909 | out: | |
910 | /* | |
911 | * Can't read this out :( Let's assume it's | |
912 | * at least what the CDCLK frequency requires. | |
913 | */ | |
914 | cdclk_state->voltage_level = | |
915 | skl_calc_voltage_level(cdclk_state->cdclk); | |
7ff89ca2 VS |
916 | } |
917 | ||
918 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
919 | static int skl_cdclk_decimal(int cdclk) | |
920 | { | |
921 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
922 | } | |
923 | ||
924 | static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, | |
925 | int vco) | |
926 | { | |
927 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
928 | ||
929 | dev_priv->skl_preferred_vco_freq = vco; | |
930 | ||
931 | if (changed) | |
932 | intel_update_max_cdclk(dev_priv); | |
933 | } | |
934 | ||
935 | static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) | |
936 | { | |
7ff89ca2 VS |
937 | u32 val; |
938 | ||
939 | WARN_ON(vco != 8100000 && vco != 8640000); | |
940 | ||
7ff89ca2 VS |
941 | /* |
942 | * We always enable DPLL0 with the lowest link rate possible, but still | |
943 | * taking into account the VCO required to operate the eDP panel at the | |
944 | * desired frequency. The usual DP link rates operate with a VCO of | |
945 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
946 | * The modeset code is responsible for the selection of the exact link | |
947 | * rate later on, with the constraint of choosing a frequency that | |
948 | * works with vco. | |
949 | */ | |
950 | val = I915_READ(DPLL_CTRL1); | |
951 | ||
952 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
953 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
954 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
955 | if (vco == 8640000) | |
956 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
957 | SKL_DPLL0); | |
958 | else | |
959 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
960 | SKL_DPLL0); | |
961 | ||
962 | I915_WRITE(DPLL_CTRL1, val); | |
963 | POSTING_READ(DPLL_CTRL1); | |
964 | ||
965 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
966 | ||
967 | if (intel_wait_for_register(dev_priv, | |
968 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
969 | 5)) | |
970 | DRM_ERROR("DPLL0 not locked\n"); | |
971 | ||
49cd97a3 | 972 | dev_priv->cdclk.hw.vco = vco; |
7ff89ca2 VS |
973 | |
974 | /* We'll want to keep using the current vco from now on. */ | |
975 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
976 | } | |
977 | ||
978 | static void skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
979 | { | |
980 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
981 | if (intel_wait_for_register(dev_priv, | |
982 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
983 | 1)) | |
984 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
985 | ||
49cd97a3 | 986 | dev_priv->cdclk.hw.vco = 0; |
7ff89ca2 VS |
987 | } |
988 | ||
989 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, | |
83c5fda7 | 990 | const struct intel_cdclk_state *cdclk_state) |
7ff89ca2 | 991 | { |
83c5fda7 VS |
992 | int cdclk = cdclk_state->cdclk; |
993 | int vco = cdclk_state->vco; | |
53421c2f | 994 | u32 freq_select, cdclk_ctl; |
7ff89ca2 VS |
995 | int ret; |
996 | ||
602a9de5 ID |
997 | /* |
998 | * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are | |
999 | * unsupported on SKL. In theory this should never happen since only | |
1000 | * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not | |
1001 | * supported on SKL either, see the above WA. WARN whenever trying to | |
1002 | * use the corresponding VCO freq as that always leads to using the | |
1003 | * minimum 308MHz CDCLK. | |
1004 | */ | |
1005 | WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000); | |
1006 | ||
9f817501 | 1007 | mutex_lock(&dev_priv->pcu_lock); |
7ff89ca2 VS |
1008 | ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, |
1009 | SKL_CDCLK_PREPARE_FOR_CHANGE, | |
1010 | SKL_CDCLK_READY_FOR_CHANGE, | |
1011 | SKL_CDCLK_READY_FOR_CHANGE, 3); | |
9f817501 | 1012 | mutex_unlock(&dev_priv->pcu_lock); |
7ff89ca2 VS |
1013 | if (ret) { |
1014 | DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", | |
1015 | ret); | |
1016 | return; | |
1017 | } | |
1018 | ||
53421c2f | 1019 | /* Choose frequency for this cdclk */ |
7ff89ca2 | 1020 | switch (cdclk) { |
2b58417f | 1021 | default: |
b6c51c3e | 1022 | WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); |
2b58417f VS |
1023 | WARN_ON(vco != 0); |
1024 | /* fall through */ | |
1025 | case 308571: | |
1026 | case 337500: | |
1027 | freq_select = CDCLK_FREQ_337_308; | |
2b58417f | 1028 | break; |
7ff89ca2 VS |
1029 | case 450000: |
1030 | case 432000: | |
1031 | freq_select = CDCLK_FREQ_450_432; | |
7ff89ca2 VS |
1032 | break; |
1033 | case 540000: | |
1034 | freq_select = CDCLK_FREQ_540; | |
7ff89ca2 | 1035 | break; |
7ff89ca2 VS |
1036 | case 617143: |
1037 | case 675000: | |
1038 | freq_select = CDCLK_FREQ_675_617; | |
7ff89ca2 VS |
1039 | break; |
1040 | } | |
1041 | ||
49cd97a3 VS |
1042 | if (dev_priv->cdclk.hw.vco != 0 && |
1043 | dev_priv->cdclk.hw.vco != vco) | |
7ff89ca2 VS |
1044 | skl_dpll0_disable(dev_priv); |
1045 | ||
53421c2f LDM |
1046 | cdclk_ctl = I915_READ(CDCLK_CTL); |
1047 | ||
1048 | if (dev_priv->cdclk.hw.vco != vco) { | |
1049 | /* Wa Display #1183: skl,kbl,cfl */ | |
1050 | cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); | |
1051 | cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); | |
1052 | I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
1053 | } | |
1054 | ||
1055 | /* Wa Display #1183: skl,kbl,cfl */ | |
1056 | cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; | |
1057 | I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
1058 | POSTING_READ(CDCLK_CTL); | |
1059 | ||
49cd97a3 | 1060 | if (dev_priv->cdclk.hw.vco != vco) |
7ff89ca2 VS |
1061 | skl_dpll0_enable(dev_priv, vco); |
1062 | ||
53421c2f LDM |
1063 | /* Wa Display #1183: skl,kbl,cfl */ |
1064 | cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); | |
1065 | I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
1066 | ||
1067 | cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); | |
1068 | I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
1069 | ||
1070 | /* Wa Display #1183: skl,kbl,cfl */ | |
1071 | cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; | |
1072 | I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
7ff89ca2 VS |
1073 | POSTING_READ(CDCLK_CTL); |
1074 | ||
1075 | /* inform PCU of the change */ | |
9f817501 | 1076 | mutex_lock(&dev_priv->pcu_lock); |
2aa97491 VS |
1077 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, |
1078 | cdclk_state->voltage_level); | |
9f817501 | 1079 | mutex_unlock(&dev_priv->pcu_lock); |
7ff89ca2 VS |
1080 | |
1081 | intel_update_cdclk(dev_priv); | |
1082 | } | |
1083 | ||
1084 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
1085 | { | |
1086 | uint32_t cdctl, expected; | |
1087 | ||
1088 | /* | |
1089 | * check if the pre-os initialized the display | |
1090 | * There is SWF18 scratchpad register defined which is set by the | |
1091 | * pre-os which can be used by the OS drivers to check the status | |
1092 | */ | |
1093 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
1094 | goto sanitize; | |
1095 | ||
1096 | intel_update_cdclk(dev_priv); | |
cfddadc9 VS |
1097 | intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); |
1098 | ||
7ff89ca2 | 1099 | /* Is PLL enabled and locked ? */ |
49cd97a3 | 1100 | if (dev_priv->cdclk.hw.vco == 0 || |
b6c51c3e | 1101 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) |
7ff89ca2 VS |
1102 | goto sanitize; |
1103 | ||
1104 | /* DPLL okay; verify the cdclock | |
1105 | * | |
1106 | * Noticed in some instances that the freq selection is correct but | |
1107 | * decimal part is programmed wrong from BIOS where pre-os does not | |
1108 | * enable display. Verify the same as well. | |
1109 | */ | |
1110 | cdctl = I915_READ(CDCLK_CTL); | |
1111 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
49cd97a3 | 1112 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); |
7ff89ca2 VS |
1113 | if (cdctl == expected) |
1114 | /* All well; nothing to sanitize */ | |
1115 | return; | |
1116 | ||
1117 | sanitize: | |
1118 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
1119 | ||
1120 | /* force cdclk programming */ | |
49cd97a3 | 1121 | dev_priv->cdclk.hw.cdclk = 0; |
7ff89ca2 | 1122 | /* force full PLL disable + enable */ |
49cd97a3 | 1123 | dev_priv->cdclk.hw.vco = -1; |
7ff89ca2 VS |
1124 | } |
1125 | ||
1126 | /** | |
1127 | * skl_init_cdclk - Initialize CDCLK on SKL | |
1128 | * @dev_priv: i915 device | |
1129 | * | |
1130 | * Initialize CDCLK for SKL and derivatives. This is generally | |
1131 | * done only during the display core initialization sequence, | |
1132 | * after which the DMC will take care of turning CDCLK off/on | |
1133 | * as needed. | |
1134 | */ | |
1135 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
1136 | { | |
83c5fda7 | 1137 | struct intel_cdclk_state cdclk_state; |
7ff89ca2 VS |
1138 | |
1139 | skl_sanitize_cdclk(dev_priv); | |
1140 | ||
49cd97a3 VS |
1141 | if (dev_priv->cdclk.hw.cdclk != 0 && |
1142 | dev_priv->cdclk.hw.vco != 0) { | |
7ff89ca2 VS |
1143 | /* |
1144 | * Use the current vco as our initial | |
1145 | * guess as to what the preferred vco is. | |
1146 | */ | |
1147 | if (dev_priv->skl_preferred_vco_freq == 0) | |
1148 | skl_set_preferred_cdclk_vco(dev_priv, | |
49cd97a3 | 1149 | dev_priv->cdclk.hw.vco); |
7ff89ca2 VS |
1150 | return; |
1151 | } | |
1152 | ||
83c5fda7 VS |
1153 | cdclk_state = dev_priv->cdclk.hw; |
1154 | ||
1155 | cdclk_state.vco = dev_priv->skl_preferred_vco_freq; | |
1156 | if (cdclk_state.vco == 0) | |
1157 | cdclk_state.vco = 8100000; | |
1158 | cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); | |
2aa97491 | 1159 | cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); |
7ff89ca2 | 1160 | |
83c5fda7 | 1161 | skl_set_cdclk(dev_priv, &cdclk_state); |
7ff89ca2 VS |
1162 | } |
1163 | ||
1164 | /** | |
1165 | * skl_uninit_cdclk - Uninitialize CDCLK on SKL | |
1166 | * @dev_priv: i915 device | |
1167 | * | |
1168 | * Uninitialize CDCLK for SKL and derivatives. This is done only | |
1169 | * during the display core uninitialization sequence. | |
1170 | */ | |
1171 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
1172 | { | |
83c5fda7 VS |
1173 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; |
1174 | ||
b6c51c3e | 1175 | cdclk_state.cdclk = cdclk_state.bypass; |
83c5fda7 | 1176 | cdclk_state.vco = 0; |
2aa97491 | 1177 | cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); |
83c5fda7 VS |
1178 | |
1179 | skl_set_cdclk(dev_priv, &cdclk_state); | |
7ff89ca2 VS |
1180 | } |
1181 | ||
d305e061 | 1182 | static int bxt_calc_cdclk(int min_cdclk) |
7ff89ca2 | 1183 | { |
d305e061 | 1184 | if (min_cdclk > 576000) |
7ff89ca2 | 1185 | return 624000; |
d305e061 | 1186 | else if (min_cdclk > 384000) |
7ff89ca2 | 1187 | return 576000; |
d305e061 | 1188 | else if (min_cdclk > 288000) |
7ff89ca2 | 1189 | return 384000; |
d305e061 | 1190 | else if (min_cdclk > 144000) |
7ff89ca2 VS |
1191 | return 288000; |
1192 | else | |
1193 | return 144000; | |
1194 | } | |
1195 | ||
d305e061 | 1196 | static int glk_calc_cdclk(int min_cdclk) |
7ff89ca2 | 1197 | { |
d305e061 | 1198 | if (min_cdclk > 158400) |
7ff89ca2 | 1199 | return 316800; |
d305e061 | 1200 | else if (min_cdclk > 79200) |
7ff89ca2 VS |
1201 | return 158400; |
1202 | else | |
1203 | return 79200; | |
1204 | } | |
1205 | ||
2123f442 VS |
1206 | static u8 bxt_calc_voltage_level(int cdclk) |
1207 | { | |
1208 | return DIV_ROUND_UP(cdclk, 25000); | |
1209 | } | |
1210 | ||
7ff89ca2 VS |
1211 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
1212 | { | |
1213 | int ratio; | |
1214 | ||
b6c51c3e | 1215 | if (cdclk == dev_priv->cdclk.hw.bypass) |
7ff89ca2 VS |
1216 | return 0; |
1217 | ||
1218 | switch (cdclk) { | |
1219 | default: | |
1220 | MISSING_CASE(cdclk); | |
2b58417f | 1221 | /* fall through */ |
7ff89ca2 VS |
1222 | case 144000: |
1223 | case 288000: | |
1224 | case 384000: | |
1225 | case 576000: | |
1226 | ratio = 60; | |
1227 | break; | |
1228 | case 624000: | |
1229 | ratio = 65; | |
1230 | break; | |
1231 | } | |
1232 | ||
49cd97a3 | 1233 | return dev_priv->cdclk.hw.ref * ratio; |
7ff89ca2 VS |
1234 | } |
1235 | ||
1236 | static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) | |
1237 | { | |
1238 | int ratio; | |
1239 | ||
b6c51c3e | 1240 | if (cdclk == dev_priv->cdclk.hw.bypass) |
7ff89ca2 VS |
1241 | return 0; |
1242 | ||
1243 | switch (cdclk) { | |
1244 | default: | |
1245 | MISSING_CASE(cdclk); | |
2b58417f | 1246 | /* fall through */ |
7ff89ca2 VS |
1247 | case 79200: |
1248 | case 158400: | |
1249 | case 316800: | |
1250 | ratio = 33; | |
1251 | break; | |
1252 | } | |
1253 | ||
49cd97a3 | 1254 | return dev_priv->cdclk.hw.ref * ratio; |
7ff89ca2 VS |
1255 | } |
1256 | ||
49cd97a3 VS |
1257 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv, |
1258 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
1259 | { |
1260 | u32 val; | |
1261 | ||
49cd97a3 VS |
1262 | cdclk_state->ref = 19200; |
1263 | cdclk_state->vco = 0; | |
7ff89ca2 VS |
1264 | |
1265 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1266 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) | |
1267 | return; | |
1268 | ||
1269 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) | |
1270 | return; | |
1271 | ||
1272 | val = I915_READ(BXT_DE_PLL_CTL); | |
49cd97a3 | 1273 | cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; |
7ff89ca2 VS |
1274 | } |
1275 | ||
49cd97a3 VS |
1276 | static void bxt_get_cdclk(struct drm_i915_private *dev_priv, |
1277 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
1278 | { |
1279 | u32 divider; | |
49cd97a3 | 1280 | int div; |
7ff89ca2 | 1281 | |
49cd97a3 | 1282 | bxt_de_pll_update(dev_priv, cdclk_state); |
7ff89ca2 | 1283 | |
b6c51c3e | 1284 | cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; |
49cd97a3 VS |
1285 | |
1286 | if (cdclk_state->vco == 0) | |
2123f442 | 1287 | goto out; |
7ff89ca2 VS |
1288 | |
1289 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
1290 | ||
1291 | switch (divider) { | |
1292 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
1293 | div = 2; | |
1294 | break; | |
1295 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
1296 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); | |
1297 | div = 3; | |
1298 | break; | |
1299 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
1300 | div = 4; | |
1301 | break; | |
1302 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
1303 | div = 8; | |
1304 | break; | |
1305 | default: | |
1306 | MISSING_CASE(divider); | |
49cd97a3 | 1307 | return; |
7ff89ca2 VS |
1308 | } |
1309 | ||
49cd97a3 | 1310 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); |
2123f442 VS |
1311 | |
1312 | out: | |
1313 | /* | |
1314 | * Can't read this out :( Let's assume it's | |
1315 | * at least what the CDCLK frequency requires. | |
1316 | */ | |
1317 | cdclk_state->voltage_level = | |
1318 | bxt_calc_voltage_level(cdclk_state->cdclk); | |
7ff89ca2 VS |
1319 | } |
1320 | ||
1321 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) | |
1322 | { | |
1323 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
1324 | ||
1325 | /* Timeout 200us */ | |
1326 | if (intel_wait_for_register(dev_priv, | |
1327 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
1328 | 1)) | |
1329 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); | |
1330 | ||
49cd97a3 | 1331 | dev_priv->cdclk.hw.vco = 0; |
7ff89ca2 VS |
1332 | } |
1333 | ||
1334 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) | |
1335 | { | |
49cd97a3 | 1336 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); |
7ff89ca2 VS |
1337 | u32 val; |
1338 | ||
1339 | val = I915_READ(BXT_DE_PLL_CTL); | |
1340 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
1341 | val |= BXT_DE_PLL_RATIO(ratio); | |
1342 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
1343 | ||
1344 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
1345 | ||
1346 | /* Timeout 200us */ | |
1347 | if (intel_wait_for_register(dev_priv, | |
1348 | BXT_DE_PLL_ENABLE, | |
1349 | BXT_DE_PLL_LOCK, | |
1350 | BXT_DE_PLL_LOCK, | |
1351 | 1)) | |
1352 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
1353 | ||
49cd97a3 | 1354 | dev_priv->cdclk.hw.vco = vco; |
7ff89ca2 VS |
1355 | } |
1356 | ||
8f0cfa4d | 1357 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, |
83c5fda7 | 1358 | const struct intel_cdclk_state *cdclk_state) |
7ff89ca2 | 1359 | { |
83c5fda7 VS |
1360 | int cdclk = cdclk_state->cdclk; |
1361 | int vco = cdclk_state->vco; | |
7ff89ca2 | 1362 | u32 val, divider; |
8f0cfa4d | 1363 | int ret; |
7ff89ca2 | 1364 | |
7ff89ca2 VS |
1365 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ |
1366 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
2b58417f | 1367 | default: |
b6c51c3e | 1368 | WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); |
2b58417f VS |
1369 | WARN_ON(vco != 0); |
1370 | /* fall through */ | |
1371 | case 2: | |
1372 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
7ff89ca2 VS |
1373 | break; |
1374 | case 3: | |
1375 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); | |
1376 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
1377 | break; | |
2b58417f VS |
1378 | case 4: |
1379 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
7ff89ca2 | 1380 | break; |
2b58417f VS |
1381 | case 8: |
1382 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
7ff89ca2 VS |
1383 | break; |
1384 | } | |
1385 | ||
e76019a8 ID |
1386 | /* |
1387 | * Inform power controller of upcoming frequency change. BSpec | |
1388 | * requires us to wait up to 150usec, but that leads to timeouts; | |
1389 | * the 2ms used here is based on experiment. | |
1390 | */ | |
9f817501 | 1391 | mutex_lock(&dev_priv->pcu_lock); |
e76019a8 ID |
1392 | ret = sandybridge_pcode_write_timeout(dev_priv, |
1393 | HSW_PCODE_DE_WRITE_FREQ_REQ, | |
006bb4cc | 1394 | 0x80000000, 150, 2); |
9f817501 | 1395 | mutex_unlock(&dev_priv->pcu_lock); |
7ff89ca2 VS |
1396 | |
1397 | if (ret) { | |
1398 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
1399 | ret, cdclk); | |
1400 | return; | |
1401 | } | |
1402 | ||
49cd97a3 VS |
1403 | if (dev_priv->cdclk.hw.vco != 0 && |
1404 | dev_priv->cdclk.hw.vco != vco) | |
7ff89ca2 VS |
1405 | bxt_de_pll_disable(dev_priv); |
1406 | ||
49cd97a3 | 1407 | if (dev_priv->cdclk.hw.vco != vco) |
7ff89ca2 VS |
1408 | bxt_de_pll_enable(dev_priv, vco); |
1409 | ||
1410 | val = divider | skl_cdclk_decimal(cdclk); | |
1411 | /* | |
1412 | * FIXME if only the cd2x divider needs changing, it could be done | |
1413 | * without shutting off the pipe (if only one pipe is active). | |
1414 | */ | |
1415 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
1416 | /* | |
1417 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
1418 | * enable otherwise. | |
1419 | */ | |
1420 | if (cdclk >= 500000) | |
1421 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
1422 | I915_WRITE(CDCLK_CTL, val); | |
1423 | ||
9f817501 | 1424 | mutex_lock(&dev_priv->pcu_lock); |
e76019a8 ID |
1425 | /* |
1426 | * The timeout isn't specified, the 2ms used here is based on | |
1427 | * experiment. | |
1428 | * FIXME: Waiting for the request completion could be delayed until | |
1429 | * the next PCODE request based on BSpec. | |
1430 | */ | |
1431 | ret = sandybridge_pcode_write_timeout(dev_priv, | |
1432 | HSW_PCODE_DE_WRITE_FREQ_REQ, | |
006bb4cc | 1433 | cdclk_state->voltage_level, 150, 2); |
9f817501 | 1434 | mutex_unlock(&dev_priv->pcu_lock); |
7ff89ca2 VS |
1435 | |
1436 | if (ret) { | |
1437 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
1438 | ret, cdclk); | |
1439 | return; | |
1440 | } | |
1441 | ||
1442 | intel_update_cdclk(dev_priv); | |
1443 | } | |
1444 | ||
1445 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
1446 | { | |
1447 | u32 cdctl, expected; | |
1448 | ||
1449 | intel_update_cdclk(dev_priv); | |
cfddadc9 | 1450 | intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); |
7ff89ca2 | 1451 | |
49cd97a3 | 1452 | if (dev_priv->cdclk.hw.vco == 0 || |
b6c51c3e | 1453 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) |
7ff89ca2 VS |
1454 | goto sanitize; |
1455 | ||
1456 | /* DPLL okay; verify the cdclock | |
1457 | * | |
1458 | * Some BIOS versions leave an incorrect decimal frequency value and | |
1459 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
1460 | * so sanitize this register. | |
1461 | */ | |
1462 | cdctl = I915_READ(CDCLK_CTL); | |
1463 | /* | |
1464 | * Let's ignore the pipe field, since BIOS could have configured the | |
1465 | * dividers both synching to an active pipe, or asynchronously | |
1466 | * (PIPE_NONE). | |
1467 | */ | |
1468 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
1469 | ||
1470 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
49cd97a3 | 1471 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); |
7ff89ca2 VS |
1472 | /* |
1473 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
1474 | * enable otherwise. | |
1475 | */ | |
49cd97a3 | 1476 | if (dev_priv->cdclk.hw.cdclk >= 500000) |
7ff89ca2 VS |
1477 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
1478 | ||
1479 | if (cdctl == expected) | |
1480 | /* All well; nothing to sanitize */ | |
1481 | return; | |
1482 | ||
1483 | sanitize: | |
1484 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
1485 | ||
1486 | /* force cdclk programming */ | |
49cd97a3 | 1487 | dev_priv->cdclk.hw.cdclk = 0; |
7ff89ca2 VS |
1488 | |
1489 | /* force full PLL disable + enable */ | |
49cd97a3 | 1490 | dev_priv->cdclk.hw.vco = -1; |
7ff89ca2 VS |
1491 | } |
1492 | ||
1493 | /** | |
1494 | * bxt_init_cdclk - Initialize CDCLK on BXT | |
1495 | * @dev_priv: i915 device | |
1496 | * | |
1497 | * Initialize CDCLK for BXT and derivatives. This is generally | |
1498 | * done only during the display core initialization sequence, | |
1499 | * after which the DMC will take care of turning CDCLK off/on | |
1500 | * as needed. | |
1501 | */ | |
1502 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) | |
1503 | { | |
83c5fda7 | 1504 | struct intel_cdclk_state cdclk_state; |
7ff89ca2 VS |
1505 | |
1506 | bxt_sanitize_cdclk(dev_priv); | |
1507 | ||
49cd97a3 VS |
1508 | if (dev_priv->cdclk.hw.cdclk != 0 && |
1509 | dev_priv->cdclk.hw.vco != 0) | |
7ff89ca2 VS |
1510 | return; |
1511 | ||
83c5fda7 VS |
1512 | cdclk_state = dev_priv->cdclk.hw; |
1513 | ||
7ff89ca2 VS |
1514 | /* |
1515 | * FIXME: | |
1516 | * - The initial CDCLK needs to be read from VBT. | |
1517 | * Need to make this change after VBT has changes for BXT. | |
1518 | */ | |
8f0cfa4d | 1519 | if (IS_GEMINILAKE(dev_priv)) { |
83c5fda7 VS |
1520 | cdclk_state.cdclk = glk_calc_cdclk(0); |
1521 | cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk); | |
8f0cfa4d | 1522 | } else { |
83c5fda7 VS |
1523 | cdclk_state.cdclk = bxt_calc_cdclk(0); |
1524 | cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk); | |
8f0cfa4d | 1525 | } |
2123f442 | 1526 | cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk); |
7ff89ca2 | 1527 | |
83c5fda7 | 1528 | bxt_set_cdclk(dev_priv, &cdclk_state); |
7ff89ca2 VS |
1529 | } |
1530 | ||
1531 | /** | |
1532 | * bxt_uninit_cdclk - Uninitialize CDCLK on BXT | |
1533 | * @dev_priv: i915 device | |
1534 | * | |
1535 | * Uninitialize CDCLK for BXT and derivatives. This is done only | |
1536 | * during the display core uninitialization sequence. | |
1537 | */ | |
1538 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) | |
1539 | { | |
83c5fda7 VS |
1540 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; |
1541 | ||
b6c51c3e | 1542 | cdclk_state.cdclk = cdclk_state.bypass; |
83c5fda7 | 1543 | cdclk_state.vco = 0; |
2123f442 | 1544 | cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk); |
83c5fda7 VS |
1545 | |
1546 | bxt_set_cdclk(dev_priv, &cdclk_state); | |
49cd97a3 VS |
1547 | } |
1548 | ||
d305e061 | 1549 | static int cnl_calc_cdclk(int min_cdclk) |
d1999e9e | 1550 | { |
d305e061 | 1551 | if (min_cdclk > 336000) |
d1999e9e | 1552 | return 528000; |
d305e061 | 1553 | else if (min_cdclk > 168000) |
d1999e9e RV |
1554 | return 336000; |
1555 | else | |
1556 | return 168000; | |
1557 | } | |
1558 | ||
48469ece VS |
1559 | static u8 cnl_calc_voltage_level(int cdclk) |
1560 | { | |
1561 | switch (cdclk) { | |
1562 | default: | |
1563 | case 168000: | |
1564 | return 0; | |
1565 | case 336000: | |
1566 | return 1; | |
1567 | case 528000: | |
1568 | return 2; | |
1569 | } | |
1570 | } | |
1571 | ||
945f2672 VS |
1572 | static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv, |
1573 | struct intel_cdclk_state *cdclk_state) | |
1574 | { | |
1575 | u32 val; | |
1576 | ||
1577 | if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz) | |
1578 | cdclk_state->ref = 24000; | |
1579 | else | |
1580 | cdclk_state->ref = 19200; | |
1581 | ||
1582 | cdclk_state->vco = 0; | |
1583 | ||
1584 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1585 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) | |
1586 | return; | |
1587 | ||
1588 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) | |
1589 | return; | |
1590 | ||
1591 | cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref; | |
1592 | } | |
1593 | ||
1594 | static void cnl_get_cdclk(struct drm_i915_private *dev_priv, | |
1595 | struct intel_cdclk_state *cdclk_state) | |
1596 | { | |
1597 | u32 divider; | |
1598 | int div; | |
1599 | ||
1600 | cnl_cdclk_pll_update(dev_priv, cdclk_state); | |
1601 | ||
b6c51c3e | 1602 | cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; |
945f2672 VS |
1603 | |
1604 | if (cdclk_state->vco == 0) | |
48469ece | 1605 | goto out; |
945f2672 VS |
1606 | |
1607 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
1608 | ||
1609 | switch (divider) { | |
1610 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
1611 | div = 2; | |
1612 | break; | |
1613 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
1614 | div = 4; | |
1615 | break; | |
1616 | default: | |
1617 | MISSING_CASE(divider); | |
1618 | return; | |
1619 | } | |
1620 | ||
1621 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); | |
48469ece VS |
1622 | |
1623 | out: | |
1624 | /* | |
1625 | * Can't read this out :( Let's assume it's | |
1626 | * at least what the CDCLK frequency requires. | |
1627 | */ | |
1628 | cdclk_state->voltage_level = | |
1629 | cnl_calc_voltage_level(cdclk_state->cdclk); | |
945f2672 VS |
1630 | } |
1631 | ||
ef4f7a68 VS |
1632 | static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) |
1633 | { | |
1634 | u32 val; | |
1635 | ||
1636 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1637 | val &= ~BXT_DE_PLL_PLL_ENABLE; | |
1638 | I915_WRITE(BXT_DE_PLL_ENABLE, val); | |
1639 | ||
1640 | /* Timeout 200us */ | |
1641 | if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) | |
bc8282a7 | 1642 | DRM_ERROR("timeout waiting for CDCLK PLL unlock\n"); |
ef4f7a68 VS |
1643 | |
1644 | dev_priv->cdclk.hw.vco = 0; | |
1645 | } | |
1646 | ||
1647 | static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) | |
1648 | { | |
1649 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); | |
1650 | u32 val; | |
1651 | ||
1652 | val = CNL_CDCLK_PLL_RATIO(ratio); | |
1653 | I915_WRITE(BXT_DE_PLL_ENABLE, val); | |
1654 | ||
1655 | val |= BXT_DE_PLL_PLL_ENABLE; | |
1656 | I915_WRITE(BXT_DE_PLL_ENABLE, val); | |
1657 | ||
1658 | /* Timeout 200us */ | |
1659 | if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) | |
bc8282a7 | 1660 | DRM_ERROR("timeout waiting for CDCLK PLL lock\n"); |
ef4f7a68 VS |
1661 | |
1662 | dev_priv->cdclk.hw.vco = vco; | |
1663 | } | |
1664 | ||
ef4f7a68 VS |
1665 | static void cnl_set_cdclk(struct drm_i915_private *dev_priv, |
1666 | const struct intel_cdclk_state *cdclk_state) | |
1667 | { | |
1668 | int cdclk = cdclk_state->cdclk; | |
1669 | int vco = cdclk_state->vco; | |
48469ece | 1670 | u32 val, divider; |
ef4f7a68 VS |
1671 | int ret; |
1672 | ||
9f817501 | 1673 | mutex_lock(&dev_priv->pcu_lock); |
ef4f7a68 VS |
1674 | ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, |
1675 | SKL_CDCLK_PREPARE_FOR_CHANGE, | |
1676 | SKL_CDCLK_READY_FOR_CHANGE, | |
1677 | SKL_CDCLK_READY_FOR_CHANGE, 3); | |
9f817501 | 1678 | mutex_unlock(&dev_priv->pcu_lock); |
ef4f7a68 VS |
1679 | if (ret) { |
1680 | DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", | |
1681 | ret); | |
1682 | return; | |
1683 | } | |
1684 | ||
1685 | /* cdclk = vco / 2 / div{1,2} */ | |
1686 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
ef4f7a68 | 1687 | default: |
b6c51c3e | 1688 | WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); |
ef4f7a68 | 1689 | WARN_ON(vco != 0); |
2b58417f VS |
1690 | /* fall through */ |
1691 | case 2: | |
ef4f7a68 VS |
1692 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
1693 | break; | |
2b58417f VS |
1694 | case 4: |
1695 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
1696 | break; | |
ef4f7a68 VS |
1697 | } |
1698 | ||
ef4f7a68 VS |
1699 | if (dev_priv->cdclk.hw.vco != 0 && |
1700 | dev_priv->cdclk.hw.vco != vco) | |
1701 | cnl_cdclk_pll_disable(dev_priv); | |
1702 | ||
1703 | if (dev_priv->cdclk.hw.vco != vco) | |
1704 | cnl_cdclk_pll_enable(dev_priv, vco); | |
1705 | ||
1706 | val = divider | skl_cdclk_decimal(cdclk); | |
1707 | /* | |
1708 | * FIXME if only the cd2x divider needs changing, it could be done | |
1709 | * without shutting off the pipe (if only one pipe is active). | |
1710 | */ | |
1711 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
1712 | I915_WRITE(CDCLK_CTL, val); | |
1713 | ||
1714 | /* inform PCU of the change */ | |
9f817501 | 1715 | mutex_lock(&dev_priv->pcu_lock); |
48469ece VS |
1716 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, |
1717 | cdclk_state->voltage_level); | |
9f817501 | 1718 | mutex_unlock(&dev_priv->pcu_lock); |
ef4f7a68 VS |
1719 | |
1720 | intel_update_cdclk(dev_priv); | |
53e9bf5e VS |
1721 | |
1722 | /* | |
1723 | * Can't read out the voltage level :( | |
1724 | * Let's just assume everything is as expected. | |
1725 | */ | |
1726 | dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; | |
ef4f7a68 VS |
1727 | } |
1728 | ||
d8d4a512 VS |
1729 | static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
1730 | { | |
1731 | int ratio; | |
1732 | ||
b6c51c3e | 1733 | if (cdclk == dev_priv->cdclk.hw.bypass) |
d8d4a512 VS |
1734 | return 0; |
1735 | ||
1736 | switch (cdclk) { | |
1737 | default: | |
1738 | MISSING_CASE(cdclk); | |
2b58417f | 1739 | /* fall through */ |
d8d4a512 VS |
1740 | case 168000: |
1741 | case 336000: | |
1742 | ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28; | |
1743 | break; | |
1744 | case 528000: | |
1745 | ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44; | |
1746 | break; | |
1747 | } | |
1748 | ||
1749 | return dev_priv->cdclk.hw.ref * ratio; | |
1750 | } | |
1751 | ||
1752 | static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
1753 | { | |
1754 | u32 cdctl, expected; | |
1755 | ||
1756 | intel_update_cdclk(dev_priv); | |
cfddadc9 | 1757 | intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); |
d8d4a512 VS |
1758 | |
1759 | if (dev_priv->cdclk.hw.vco == 0 || | |
b6c51c3e | 1760 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) |
d8d4a512 VS |
1761 | goto sanitize; |
1762 | ||
1763 | /* DPLL okay; verify the cdclock | |
1764 | * | |
1765 | * Some BIOS versions leave an incorrect decimal frequency value and | |
1766 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
1767 | * so sanitize this register. | |
1768 | */ | |
1769 | cdctl = I915_READ(CDCLK_CTL); | |
1770 | /* | |
1771 | * Let's ignore the pipe field, since BIOS could have configured the | |
1772 | * dividers both synching to an active pipe, or asynchronously | |
1773 | * (PIPE_NONE). | |
1774 | */ | |
1775 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
1776 | ||
1777 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
1778 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); | |
1779 | ||
1780 | if (cdctl == expected) | |
1781 | /* All well; nothing to sanitize */ | |
1782 | return; | |
1783 | ||
1784 | sanitize: | |
1785 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
1786 | ||
1787 | /* force cdclk programming */ | |
1788 | dev_priv->cdclk.hw.cdclk = 0; | |
1789 | ||
1790 | /* force full PLL disable + enable */ | |
1791 | dev_priv->cdclk.hw.vco = -1; | |
1792 | } | |
1793 | ||
186a277e PZ |
1794 | static int icl_calc_cdclk(int min_cdclk, unsigned int ref) |
1795 | { | |
1796 | int ranges_24[] = { 312000, 552000, 648000 }; | |
1797 | int ranges_19_38[] = { 307200, 556800, 652800 }; | |
1798 | int *ranges; | |
1799 | ||
1800 | switch (ref) { | |
1801 | default: | |
1802 | MISSING_CASE(ref); | |
f0d759f0 | 1803 | /* fall through */ |
186a277e PZ |
1804 | case 24000: |
1805 | ranges = ranges_24; | |
1806 | break; | |
1807 | case 19200: | |
1808 | case 38400: | |
1809 | ranges = ranges_19_38; | |
1810 | break; | |
1811 | } | |
1812 | ||
1813 | if (min_cdclk > ranges[1]) | |
1814 | return ranges[2]; | |
1815 | else if (min_cdclk > ranges[0]) | |
1816 | return ranges[1]; | |
1817 | else | |
1818 | return ranges[0]; | |
1819 | } | |
1820 | ||
1821 | static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) | |
1822 | { | |
1823 | int ratio; | |
1824 | ||
1825 | if (cdclk == dev_priv->cdclk.hw.bypass) | |
1826 | return 0; | |
1827 | ||
1828 | switch (cdclk) { | |
1829 | default: | |
1830 | MISSING_CASE(cdclk); | |
f0d759f0 | 1831 | /* fall through */ |
186a277e PZ |
1832 | case 307200: |
1833 | case 556800: | |
1834 | case 652800: | |
1835 | WARN_ON(dev_priv->cdclk.hw.ref != 19200 && | |
1836 | dev_priv->cdclk.hw.ref != 38400); | |
1837 | break; | |
1838 | case 312000: | |
1839 | case 552000: | |
1840 | case 648000: | |
1841 | WARN_ON(dev_priv->cdclk.hw.ref != 24000); | |
1842 | } | |
1843 | ||
1844 | ratio = cdclk / (dev_priv->cdclk.hw.ref / 2); | |
1845 | ||
1846 | return dev_priv->cdclk.hw.ref * ratio; | |
1847 | } | |
1848 | ||
1849 | static void icl_set_cdclk(struct drm_i915_private *dev_priv, | |
1850 | const struct intel_cdclk_state *cdclk_state) | |
1851 | { | |
1852 | unsigned int cdclk = cdclk_state->cdclk; | |
1853 | unsigned int vco = cdclk_state->vco; | |
1854 | int ret; | |
1855 | ||
1856 | mutex_lock(&dev_priv->pcu_lock); | |
1857 | ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, | |
1858 | SKL_CDCLK_PREPARE_FOR_CHANGE, | |
1859 | SKL_CDCLK_READY_FOR_CHANGE, | |
1860 | SKL_CDCLK_READY_FOR_CHANGE, 3); | |
1861 | mutex_unlock(&dev_priv->pcu_lock); | |
1862 | if (ret) { | |
1863 | DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", | |
1864 | ret); | |
1865 | return; | |
1866 | } | |
1867 | ||
1868 | if (dev_priv->cdclk.hw.vco != 0 && | |
1869 | dev_priv->cdclk.hw.vco != vco) | |
1870 | cnl_cdclk_pll_disable(dev_priv); | |
1871 | ||
1872 | if (dev_priv->cdclk.hw.vco != vco) | |
1873 | cnl_cdclk_pll_enable(dev_priv, vco); | |
1874 | ||
1875 | I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE | | |
1876 | skl_cdclk_decimal(cdclk)); | |
1877 | ||
1878 | mutex_lock(&dev_priv->pcu_lock); | |
9378985e PZ |
1879 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, |
1880 | cdclk_state->voltage_level); | |
186a277e PZ |
1881 | mutex_unlock(&dev_priv->pcu_lock); |
1882 | ||
1883 | intel_update_cdclk(dev_priv); | |
9378985e PZ |
1884 | |
1885 | /* | |
1886 | * Can't read out the voltage level :( | |
1887 | * Let's just assume everything is as expected. | |
1888 | */ | |
1889 | dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; | |
1890 | } | |
1891 | ||
1892 | static u8 icl_calc_voltage_level(int cdclk) | |
1893 | { | |
1894 | switch (cdclk) { | |
1895 | case 50000: | |
1896 | case 307200: | |
1897 | case 312000: | |
1898 | return 0; | |
1899 | case 556800: | |
1900 | case 552000: | |
1901 | return 1; | |
1902 | default: | |
1903 | MISSING_CASE(cdclk); | |
f0d759f0 | 1904 | /* fall through */ |
9378985e PZ |
1905 | case 652800: |
1906 | case 648000: | |
1907 | return 2; | |
1908 | } | |
186a277e PZ |
1909 | } |
1910 | ||
1911 | static void icl_get_cdclk(struct drm_i915_private *dev_priv, | |
1912 | struct intel_cdclk_state *cdclk_state) | |
1913 | { | |
1914 | u32 val; | |
1915 | ||
1916 | cdclk_state->bypass = 50000; | |
1917 | ||
1918 | val = I915_READ(SKL_DSSM); | |
1919 | switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) { | |
1920 | default: | |
1921 | MISSING_CASE(val); | |
f0d759f0 | 1922 | /* fall through */ |
186a277e PZ |
1923 | case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: |
1924 | cdclk_state->ref = 24000; | |
1925 | break; | |
1926 | case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: | |
1927 | cdclk_state->ref = 19200; | |
1928 | break; | |
1929 | case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: | |
1930 | cdclk_state->ref = 38400; | |
1931 | break; | |
1932 | } | |
1933 | ||
1934 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1935 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || | |
1936 | (val & BXT_DE_PLL_LOCK) == 0) { | |
1937 | /* | |
1938 | * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but | |
1939 | * setting it to zero is a way to signal that. | |
1940 | */ | |
1941 | cdclk_state->vco = 0; | |
1942 | cdclk_state->cdclk = cdclk_state->bypass; | |
9378985e | 1943 | goto out; |
186a277e PZ |
1944 | } |
1945 | ||
1946 | cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; | |
1947 | ||
1948 | val = I915_READ(CDCLK_CTL); | |
1949 | WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0); | |
1950 | ||
1951 | cdclk_state->cdclk = cdclk_state->vco / 2; | |
9378985e PZ |
1952 | |
1953 | out: | |
1954 | /* | |
1955 | * Can't read this out :( Let's assume it's | |
1956 | * at least what the CDCLK frequency requires. | |
1957 | */ | |
1958 | cdclk_state->voltage_level = | |
1959 | icl_calc_voltage_level(cdclk_state->cdclk); | |
186a277e PZ |
1960 | } |
1961 | ||
1962 | /** | |
1963 | * icl_init_cdclk - Initialize CDCLK on ICL | |
1964 | * @dev_priv: i915 device | |
1965 | * | |
1966 | * Initialize CDCLK for ICL. This consists mainly of initializing | |
1967 | * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This | |
1968 | * is generally done only during the display core initialization sequence, after | |
1969 | * which the DMC will take care of turning CDCLK off/on as needed. | |
1970 | */ | |
1971 | void icl_init_cdclk(struct drm_i915_private *dev_priv) | |
1972 | { | |
1973 | struct intel_cdclk_state sanitized_state; | |
1974 | u32 val; | |
1975 | ||
1976 | /* This sets dev_priv->cdclk.hw. */ | |
1977 | intel_update_cdclk(dev_priv); | |
1978 | intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); | |
1979 | ||
1980 | /* This means CDCLK disabled. */ | |
1981 | if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) | |
1982 | goto sanitize; | |
1983 | ||
1984 | val = I915_READ(CDCLK_CTL); | |
1985 | ||
1986 | if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0) | |
1987 | goto sanitize; | |
1988 | ||
1989 | if ((val & CDCLK_FREQ_DECIMAL_MASK) != | |
1990 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk)) | |
1991 | goto sanitize; | |
1992 | ||
1993 | return; | |
1994 | ||
1995 | sanitize: | |
1996 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
1997 | ||
1998 | sanitized_state.ref = dev_priv->cdclk.hw.ref; | |
1999 | sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref); | |
2000 | sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv, | |
2001 | sanitized_state.cdclk); | |
9378985e PZ |
2002 | sanitized_state.voltage_level = |
2003 | icl_calc_voltage_level(sanitized_state.cdclk); | |
186a277e PZ |
2004 | |
2005 | icl_set_cdclk(dev_priv, &sanitized_state); | |
2006 | } | |
2007 | ||
2008 | /** | |
2009 | * icl_uninit_cdclk - Uninitialize CDCLK on ICL | |
2010 | * @dev_priv: i915 device | |
2011 | * | |
2012 | * Uninitialize CDCLK for ICL. This is done only during the display core | |
2013 | * uninitialization sequence. | |
2014 | */ | |
2015 | void icl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
2016 | { | |
2017 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; | |
2018 | ||
2019 | cdclk_state.cdclk = cdclk_state.bypass; | |
2020 | cdclk_state.vco = 0; | |
9378985e | 2021 | cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk); |
186a277e PZ |
2022 | |
2023 | icl_set_cdclk(dev_priv, &cdclk_state); | |
2024 | } | |
2025 | ||
d8d4a512 VS |
2026 | /** |
2027 | * cnl_init_cdclk - Initialize CDCLK on CNL | |
2028 | * @dev_priv: i915 device | |
2029 | * | |
2030 | * Initialize CDCLK for CNL. This is generally | |
2031 | * done only during the display core initialization sequence, | |
2032 | * after which the DMC will take care of turning CDCLK off/on | |
2033 | * as needed. | |
2034 | */ | |
2035 | void cnl_init_cdclk(struct drm_i915_private *dev_priv) | |
2036 | { | |
2037 | struct intel_cdclk_state cdclk_state; | |
2038 | ||
2039 | cnl_sanitize_cdclk(dev_priv); | |
2040 | ||
2041 | if (dev_priv->cdclk.hw.cdclk != 0 && | |
2042 | dev_priv->cdclk.hw.vco != 0) | |
2043 | return; | |
2044 | ||
2045 | cdclk_state = dev_priv->cdclk.hw; | |
2046 | ||
d1999e9e | 2047 | cdclk_state.cdclk = cnl_calc_cdclk(0); |
d8d4a512 | 2048 | cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); |
48469ece | 2049 | cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk); |
d8d4a512 VS |
2050 | |
2051 | cnl_set_cdclk(dev_priv, &cdclk_state); | |
2052 | } | |
2053 | ||
2054 | /** | |
2055 | * cnl_uninit_cdclk - Uninitialize CDCLK on CNL | |
2056 | * @dev_priv: i915 device | |
2057 | * | |
2058 | * Uninitialize CDCLK for CNL. This is done only | |
2059 | * during the display core uninitialization sequence. | |
2060 | */ | |
2061 | void cnl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
2062 | { | |
2063 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; | |
2064 | ||
b6c51c3e | 2065 | cdclk_state.cdclk = cdclk_state.bypass; |
d8d4a512 | 2066 | cdclk_state.vco = 0; |
48469ece | 2067 | cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk); |
d8d4a512 VS |
2068 | |
2069 | cnl_set_cdclk(dev_priv, &cdclk_state); | |
2070 | } | |
2071 | ||
49cd97a3 | 2072 | /** |
64600bd5 | 2073 | * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes |
49cd97a3 VS |
2074 | * @a: first CDCLK state |
2075 | * @b: second CDCLK state | |
2076 | * | |
2077 | * Returns: | |
64600bd5 | 2078 | * True if the CDCLK states require pipes to be off during reprogramming, false if not. |
49cd97a3 | 2079 | */ |
64600bd5 | 2080 | bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, |
49cd97a3 VS |
2081 | const struct intel_cdclk_state *b) |
2082 | { | |
64600bd5 VS |
2083 | return a->cdclk != b->cdclk || |
2084 | a->vco != b->vco || | |
2085 | a->ref != b->ref; | |
2086 | } | |
2087 | ||
2088 | /** | |
2089 | * intel_cdclk_changed - Determine if two CDCLK states are different | |
2090 | * @a: first CDCLK state | |
2091 | * @b: second CDCLK state | |
2092 | * | |
2093 | * Returns: | |
2094 | * True if the CDCLK states don't match, false if they do. | |
2095 | */ | |
2096 | bool intel_cdclk_changed(const struct intel_cdclk_state *a, | |
2097 | const struct intel_cdclk_state *b) | |
2098 | { | |
2099 | return intel_cdclk_needs_modeset(a, b) || | |
2100 | a->voltage_level != b->voltage_level; | |
7ff89ca2 VS |
2101 | } |
2102 | ||
cfddadc9 VS |
2103 | void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, |
2104 | const char *context) | |
2105 | { | |
b6c51c3e | 2106 | DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", |
cfddadc9 | 2107 | context, cdclk_state->cdclk, cdclk_state->vco, |
b6c51c3e ID |
2108 | cdclk_state->ref, cdclk_state->bypass, |
2109 | cdclk_state->voltage_level); | |
cfddadc9 VS |
2110 | } |
2111 | ||
b0587e4d VS |
2112 | /** |
2113 | * intel_set_cdclk - Push the CDCLK state to the hardware | |
2114 | * @dev_priv: i915 device | |
2115 | * @cdclk_state: new CDCLK state | |
2116 | * | |
2117 | * Program the hardware based on the passed in CDCLK state, | |
2118 | * if necessary. | |
2119 | */ | |
2120 | void intel_set_cdclk(struct drm_i915_private *dev_priv, | |
2121 | const struct intel_cdclk_state *cdclk_state) | |
2122 | { | |
64600bd5 | 2123 | if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state)) |
b0587e4d VS |
2124 | return; |
2125 | ||
2126 | if (WARN_ON_ONCE(!dev_priv->display.set_cdclk)) | |
2127 | return; | |
2128 | ||
cfddadc9 | 2129 | intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to"); |
b0587e4d VS |
2130 | |
2131 | dev_priv->display.set_cdclk(dev_priv, cdclk_state); | |
cfddadc9 VS |
2132 | |
2133 | if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state), | |
2134 | "cdclk state doesn't match!\n")) { | |
2135 | intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]"); | |
2136 | intel_dump_cdclk_state(cdclk_state, "[sw state]"); | |
2137 | } | |
b0587e4d VS |
2138 | } |
2139 | ||
d305e061 VS |
2140 | static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, |
2141 | int pixel_rate) | |
2142 | { | |
42882336 | 2143 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
43037c86 | 2144 | return DIV_ROUND_UP(pixel_rate, 2); |
cf819eff | 2145 | else if (IS_GEN(dev_priv, 9) || |
d305e061 VS |
2146 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) |
2147 | return pixel_rate; | |
2148 | else if (IS_CHERRYVIEW(dev_priv)) | |
2149 | return DIV_ROUND_UP(pixel_rate * 100, 95); | |
2150 | else | |
2151 | return DIV_ROUND_UP(pixel_rate * 100, 90); | |
2152 | } | |
2153 | ||
2154 | int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) | |
7ff89ca2 VS |
2155 | { |
2156 | struct drm_i915_private *dev_priv = | |
2157 | to_i915(crtc_state->base.crtc->dev); | |
d305e061 VS |
2158 | int min_cdclk; |
2159 | ||
2160 | if (!crtc_state->base.enable) | |
2161 | return 0; | |
2162 | ||
2163 | min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); | |
7ff89ca2 VS |
2164 | |
2165 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
24f28450 | 2166 | if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) |
d305e061 | 2167 | min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); |
7ff89ca2 | 2168 | |
78cfa580 PD |
2169 | /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, |
2170 | * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else | |
2171 | * there may be audio corruption or screen corruption." This cdclk | |
d305e061 | 2172 | * restriction for GLK is 316.8 MHz. |
7ff89ca2 VS |
2173 | */ |
2174 | if (intel_crtc_has_dp_encoder(crtc_state) && | |
2175 | crtc_state->has_audio && | |
2176 | crtc_state->port_clock >= 540000 && | |
78cfa580 | 2177 | crtc_state->lane_count == 4) { |
d305e061 VS |
2178 | if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { |
2179 | /* Display WA #1145: glk,cnl */ | |
2180 | min_cdclk = max(316800, min_cdclk); | |
cf819eff | 2181 | } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) { |
d305e061 VS |
2182 | /* Display WA #1144: skl,bxt */ |
2183 | min_cdclk = max(432000, min_cdclk); | |
2184 | } | |
78cfa580 | 2185 | } |
7ff89ca2 | 2186 | |
904e1b1f AK |
2187 | /* |
2188 | * According to BSpec, "The CD clock frequency must be at least twice | |
8cbeb06d | 2189 | * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. |
904e1b1f AK |
2190 | * |
2191 | * FIXME: Check the actual, not default, BCLK being used. | |
2192 | * | |
2193 | * FIXME: This does not depend on ->has_audio because the higher CDCLK | |
2194 | * is required for audio probe, also when there are no audio capable | |
2195 | * displays connected at probe time. This leads to unnecessarily high | |
2196 | * CDCLK when audio is not required. | |
2197 | * | |
2198 | * FIXME: This limit is only applied when there are displays connected | |
2199 | * at probe time. If we probe without displays, we'll still end up using | |
2200 | * the platform minimum CDCLK, failing audio probe. | |
8cbeb06d | 2201 | */ |
904e1b1f | 2202 | if (INTEL_GEN(dev_priv) >= 9) |
d305e061 | 2203 | min_cdclk = max(2 * 96000, min_cdclk); |
8cbeb06d | 2204 | |
c8dae55a HG |
2205 | /* |
2206 | * On Valleyview some DSI panels lose (v|h)sync when the clock is lower | |
2207 | * than 320000KHz. | |
2208 | */ | |
2209 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && | |
2210 | IS_VALLEYVIEW(dev_priv)) | |
2211 | min_cdclk = max(320000, min_cdclk); | |
2212 | ||
9c61de4c VS |
2213 | if (min_cdclk > dev_priv->max_cdclk_freq) { |
2214 | DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n", | |
2215 | min_cdclk, dev_priv->max_cdclk_freq); | |
2216 | return -EINVAL; | |
2217 | } | |
2218 | ||
d305e061 | 2219 | return min_cdclk; |
7ff89ca2 VS |
2220 | } |
2221 | ||
d305e061 | 2222 | static int intel_compute_min_cdclk(struct drm_atomic_state *state) |
7ff89ca2 VS |
2223 | { |
2224 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
2225 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
d305e061 | 2226 | struct intel_crtc *crtc; |
7ff89ca2 | 2227 | struct intel_crtc_state *crtc_state; |
9c61de4c | 2228 | int min_cdclk, i; |
7ff89ca2 VS |
2229 | enum pipe pipe; |
2230 | ||
d305e061 VS |
2231 | memcpy(intel_state->min_cdclk, dev_priv->min_cdclk, |
2232 | sizeof(intel_state->min_cdclk)); | |
7ff89ca2 | 2233 | |
9c61de4c VS |
2234 | for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { |
2235 | min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); | |
2236 | if (min_cdclk < 0) | |
2237 | return min_cdclk; | |
2238 | ||
2239 | intel_state->min_cdclk[i] = min_cdclk; | |
2240 | } | |
7ff89ca2 | 2241 | |
9c61de4c | 2242 | min_cdclk = 0; |
7ff89ca2 | 2243 | for_each_pipe(dev_priv, pipe) |
d305e061 | 2244 | min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk); |
7ff89ca2 | 2245 | |
d305e061 | 2246 | return min_cdclk; |
7ff89ca2 VS |
2247 | } |
2248 | ||
53e9bf5e VS |
2249 | /* |
2250 | * Note that this functions assumes that 0 is | |
2251 | * the lowest voltage value, and higher values | |
2252 | * correspond to increasingly higher voltages. | |
2253 | * | |
2254 | * Should that relationship no longer hold on | |
2255 | * future platforms this code will need to be | |
2256 | * adjusted. | |
2257 | */ | |
2258 | static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state) | |
2259 | { | |
2260 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
2261 | struct intel_crtc *crtc; | |
2262 | struct intel_crtc_state *crtc_state; | |
2263 | u8 min_voltage_level; | |
2264 | int i; | |
2265 | enum pipe pipe; | |
2266 | ||
2267 | memcpy(state->min_voltage_level, dev_priv->min_voltage_level, | |
2268 | sizeof(state->min_voltage_level)); | |
2269 | ||
2270 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { | |
2271 | if (crtc_state->base.enable) | |
2272 | state->min_voltage_level[i] = | |
2273 | crtc_state->min_voltage_level; | |
2274 | else | |
2275 | state->min_voltage_level[i] = 0; | |
2276 | } | |
2277 | ||
2278 | min_voltage_level = 0; | |
2279 | for_each_pipe(dev_priv, pipe) | |
2280 | min_voltage_level = max(state->min_voltage_level[pipe], | |
2281 | min_voltage_level); | |
2282 | ||
2283 | return min_voltage_level; | |
2284 | } | |
2285 | ||
7ff89ca2 VS |
2286 | static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state) |
2287 | { | |
3d5dbb10 | 2288 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
9c61de4c VS |
2289 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
2290 | int min_cdclk, cdclk; | |
bb0f4aab | 2291 | |
9c61de4c VS |
2292 | min_cdclk = intel_compute_min_cdclk(state); |
2293 | if (min_cdclk < 0) | |
2294 | return min_cdclk; | |
7ff89ca2 | 2295 | |
9c61de4c | 2296 | cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); |
7ff89ca2 | 2297 | |
bb0f4aab | 2298 | intel_state->cdclk.logical.cdclk = cdclk; |
999c5766 VS |
2299 | intel_state->cdclk.logical.voltage_level = |
2300 | vlv_calc_voltage_level(dev_priv, cdclk); | |
bb0f4aab VS |
2301 | |
2302 | if (!intel_state->active_crtcs) { | |
2303 | cdclk = vlv_calc_cdclk(dev_priv, 0); | |
2304 | ||
2305 | intel_state->cdclk.actual.cdclk = cdclk; | |
999c5766 VS |
2306 | intel_state->cdclk.actual.voltage_level = |
2307 | vlv_calc_voltage_level(dev_priv, cdclk); | |
bb0f4aab VS |
2308 | } else { |
2309 | intel_state->cdclk.actual = | |
2310 | intel_state->cdclk.logical; | |
2311 | } | |
7ff89ca2 VS |
2312 | |
2313 | return 0; | |
2314 | } | |
2315 | ||
7ff89ca2 VS |
2316 | static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state) |
2317 | { | |
7ff89ca2 | 2318 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9c61de4c VS |
2319 | int min_cdclk, cdclk; |
2320 | ||
2321 | min_cdclk = intel_compute_min_cdclk(state); | |
2322 | if (min_cdclk < 0) | |
2323 | return min_cdclk; | |
7ff89ca2 VS |
2324 | |
2325 | /* | |
2326 | * FIXME should also account for plane ratio | |
2327 | * once 64bpp pixel formats are supported. | |
2328 | */ | |
d305e061 | 2329 | cdclk = bdw_calc_cdclk(min_cdclk); |
7ff89ca2 | 2330 | |
bb0f4aab | 2331 | intel_state->cdclk.logical.cdclk = cdclk; |
d7ffaeef VS |
2332 | intel_state->cdclk.logical.voltage_level = |
2333 | bdw_calc_voltage_level(cdclk); | |
bb0f4aab VS |
2334 | |
2335 | if (!intel_state->active_crtcs) { | |
2336 | cdclk = bdw_calc_cdclk(0); | |
2337 | ||
2338 | intel_state->cdclk.actual.cdclk = cdclk; | |
d7ffaeef VS |
2339 | intel_state->cdclk.actual.voltage_level = |
2340 | bdw_calc_voltage_level(cdclk); | |
bb0f4aab VS |
2341 | } else { |
2342 | intel_state->cdclk.actual = | |
2343 | intel_state->cdclk.logical; | |
2344 | } | |
7ff89ca2 VS |
2345 | |
2346 | return 0; | |
2347 | } | |
2348 | ||
3297234a RV |
2349 | static int skl_dpll0_vco(struct intel_atomic_state *intel_state) |
2350 | { | |
2351 | struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); | |
2352 | struct intel_crtc *crtc; | |
2353 | struct intel_crtc_state *crtc_state; | |
2354 | int vco, i; | |
2355 | ||
2356 | vco = intel_state->cdclk.logical.vco; | |
2357 | if (!vco) | |
2358 | vco = dev_priv->skl_preferred_vco_freq; | |
2359 | ||
2360 | for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { | |
2361 | if (!crtc_state->base.enable) | |
2362 | continue; | |
2363 | ||
2364 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) | |
2365 | continue; | |
2366 | ||
2367 | /* | |
2368 | * DPLL0 VCO may need to be adjusted to get the correct | |
2369 | * clock for eDP. This will affect cdclk as well. | |
2370 | */ | |
2371 | switch (crtc_state->port_clock / 2) { | |
2372 | case 108000: | |
2373 | case 216000: | |
2374 | vco = 8640000; | |
2375 | break; | |
2376 | default: | |
2377 | vco = 8100000; | |
2378 | break; | |
2379 | } | |
2380 | } | |
2381 | ||
2382 | return vco; | |
2383 | } | |
2384 | ||
7ff89ca2 VS |
2385 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
2386 | { | |
9c61de4c VS |
2387 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
2388 | int min_cdclk, cdclk, vco; | |
2389 | ||
2390 | min_cdclk = intel_compute_min_cdclk(state); | |
2391 | if (min_cdclk < 0) | |
2392 | return min_cdclk; | |
bb0f4aab | 2393 | |
3297234a | 2394 | vco = skl_dpll0_vco(intel_state); |
7ff89ca2 VS |
2395 | |
2396 | /* | |
2397 | * FIXME should also account for plane ratio | |
2398 | * once 64bpp pixel formats are supported. | |
2399 | */ | |
d305e061 | 2400 | cdclk = skl_calc_cdclk(min_cdclk, vco); |
7ff89ca2 | 2401 | |
bb0f4aab VS |
2402 | intel_state->cdclk.logical.vco = vco; |
2403 | intel_state->cdclk.logical.cdclk = cdclk; | |
2aa97491 VS |
2404 | intel_state->cdclk.logical.voltage_level = |
2405 | skl_calc_voltage_level(cdclk); | |
bb0f4aab VS |
2406 | |
2407 | if (!intel_state->active_crtcs) { | |
2408 | cdclk = skl_calc_cdclk(0, vco); | |
2409 | ||
2410 | intel_state->cdclk.actual.vco = vco; | |
2411 | intel_state->cdclk.actual.cdclk = cdclk; | |
2aa97491 VS |
2412 | intel_state->cdclk.actual.voltage_level = |
2413 | skl_calc_voltage_level(cdclk); | |
bb0f4aab VS |
2414 | } else { |
2415 | intel_state->cdclk.actual = | |
2416 | intel_state->cdclk.logical; | |
2417 | } | |
7ff89ca2 VS |
2418 | |
2419 | return 0; | |
2420 | } | |
2421 | ||
7ff89ca2 VS |
2422 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
2423 | { | |
2424 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
9c61de4c VS |
2425 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
2426 | int min_cdclk, cdclk, vco; | |
2427 | ||
2428 | min_cdclk = intel_compute_min_cdclk(state); | |
2429 | if (min_cdclk < 0) | |
2430 | return min_cdclk; | |
7ff89ca2 | 2431 | |
bb0f4aab | 2432 | if (IS_GEMINILAKE(dev_priv)) { |
d305e061 | 2433 | cdclk = glk_calc_cdclk(min_cdclk); |
bb0f4aab VS |
2434 | vco = glk_de_pll_vco(dev_priv, cdclk); |
2435 | } else { | |
d305e061 | 2436 | cdclk = bxt_calc_cdclk(min_cdclk); |
bb0f4aab VS |
2437 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
2438 | } | |
2439 | ||
bb0f4aab VS |
2440 | intel_state->cdclk.logical.vco = vco; |
2441 | intel_state->cdclk.logical.cdclk = cdclk; | |
2123f442 VS |
2442 | intel_state->cdclk.logical.voltage_level = |
2443 | bxt_calc_voltage_level(cdclk); | |
7ff89ca2 VS |
2444 | |
2445 | if (!intel_state->active_crtcs) { | |
bb0f4aab | 2446 | if (IS_GEMINILAKE(dev_priv)) { |
7ff89ca2 | 2447 | cdclk = glk_calc_cdclk(0); |
bb0f4aab VS |
2448 | vco = glk_de_pll_vco(dev_priv, cdclk); |
2449 | } else { | |
7ff89ca2 | 2450 | cdclk = bxt_calc_cdclk(0); |
bb0f4aab VS |
2451 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
2452 | } | |
7ff89ca2 | 2453 | |
bb0f4aab VS |
2454 | intel_state->cdclk.actual.vco = vco; |
2455 | intel_state->cdclk.actual.cdclk = cdclk; | |
2123f442 VS |
2456 | intel_state->cdclk.actual.voltage_level = |
2457 | bxt_calc_voltage_level(cdclk); | |
bb0f4aab VS |
2458 | } else { |
2459 | intel_state->cdclk.actual = | |
2460 | intel_state->cdclk.logical; | |
7ff89ca2 VS |
2461 | } |
2462 | ||
2463 | return 0; | |
2464 | } | |
2465 | ||
d1999e9e RV |
2466 | static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state) |
2467 | { | |
2468 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
9c61de4c VS |
2469 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
2470 | int min_cdclk, cdclk, vco; | |
2471 | ||
2472 | min_cdclk = intel_compute_min_cdclk(state); | |
2473 | if (min_cdclk < 0) | |
2474 | return min_cdclk; | |
d1999e9e | 2475 | |
d305e061 | 2476 | cdclk = cnl_calc_cdclk(min_cdclk); |
d1999e9e RV |
2477 | vco = cnl_cdclk_pll_vco(dev_priv, cdclk); |
2478 | ||
d1999e9e RV |
2479 | intel_state->cdclk.logical.vco = vco; |
2480 | intel_state->cdclk.logical.cdclk = cdclk; | |
48469ece | 2481 | intel_state->cdclk.logical.voltage_level = |
53e9bf5e VS |
2482 | max(cnl_calc_voltage_level(cdclk), |
2483 | cnl_compute_min_voltage_level(intel_state)); | |
d1999e9e RV |
2484 | |
2485 | if (!intel_state->active_crtcs) { | |
2486 | cdclk = cnl_calc_cdclk(0); | |
2487 | vco = cnl_cdclk_pll_vco(dev_priv, cdclk); | |
2488 | ||
2489 | intel_state->cdclk.actual.vco = vco; | |
2490 | intel_state->cdclk.actual.cdclk = cdclk; | |
48469ece VS |
2491 | intel_state->cdclk.actual.voltage_level = |
2492 | cnl_calc_voltage_level(cdclk); | |
d1999e9e RV |
2493 | } else { |
2494 | intel_state->cdclk.actual = | |
2495 | intel_state->cdclk.logical; | |
2496 | } | |
2497 | ||
2498 | return 0; | |
2499 | } | |
2500 | ||
186a277e PZ |
2501 | static int icl_modeset_calc_cdclk(struct drm_atomic_state *state) |
2502 | { | |
2503 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
2504 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
2505 | unsigned int ref = intel_state->cdclk.logical.ref; | |
2506 | int min_cdclk, cdclk, vco; | |
2507 | ||
2508 | min_cdclk = intel_compute_min_cdclk(state); | |
2509 | if (min_cdclk < 0) | |
2510 | return min_cdclk; | |
2511 | ||
2512 | cdclk = icl_calc_cdclk(min_cdclk, ref); | |
2513 | vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk); | |
2514 | ||
2515 | intel_state->cdclk.logical.vco = vco; | |
2516 | intel_state->cdclk.logical.cdclk = cdclk; | |
9378985e PZ |
2517 | intel_state->cdclk.logical.voltage_level = |
2518 | max(icl_calc_voltage_level(cdclk), | |
2519 | cnl_compute_min_voltage_level(intel_state)); | |
186a277e PZ |
2520 | |
2521 | if (!intel_state->active_crtcs) { | |
2522 | cdclk = icl_calc_cdclk(0, ref); | |
2523 | vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk); | |
2524 | ||
2525 | intel_state->cdclk.actual.vco = vco; | |
2526 | intel_state->cdclk.actual.cdclk = cdclk; | |
9378985e PZ |
2527 | intel_state->cdclk.actual.voltage_level = |
2528 | icl_calc_voltage_level(cdclk); | |
186a277e PZ |
2529 | } else { |
2530 | intel_state->cdclk.actual = intel_state->cdclk.logical; | |
2531 | } | |
2532 | ||
2533 | return 0; | |
2534 | } | |
2535 | ||
7ff89ca2 VS |
2536 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
2537 | { | |
2538 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
2539 | ||
42882336 | 2540 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
43037c86 | 2541 | return 2 * max_cdclk_freq; |
cf819eff | 2542 | else if (IS_GEN(dev_priv, 9) || |
d305e061 | 2543 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) |
7ff89ca2 VS |
2544 | return max_cdclk_freq; |
2545 | else if (IS_CHERRYVIEW(dev_priv)) | |
2546 | return max_cdclk_freq*95/100; | |
c56b89f1 | 2547 | else if (INTEL_GEN(dev_priv) < 4) |
7ff89ca2 VS |
2548 | return 2*max_cdclk_freq*90/100; |
2549 | else | |
2550 | return max_cdclk_freq*90/100; | |
2551 | } | |
2552 | ||
2553 | /** | |
2554 | * intel_update_max_cdclk - Determine the maximum support CDCLK frequency | |
2555 | * @dev_priv: i915 device | |
2556 | * | |
2557 | * Determine the maximum CDCLK frequency the platform supports, and also | |
2558 | * derive the maximum dot clock frequency the maximum CDCLK frequency | |
2559 | * allows. | |
2560 | */ | |
2561 | void intel_update_max_cdclk(struct drm_i915_private *dev_priv) | |
2562 | { | |
186a277e PZ |
2563 | if (IS_ICELAKE(dev_priv)) { |
2564 | if (dev_priv->cdclk.hw.ref == 24000) | |
2565 | dev_priv->max_cdclk_freq = 648000; | |
2566 | else | |
2567 | dev_priv->max_cdclk_freq = 652800; | |
2568 | } else if (IS_CANNONLAKE(dev_priv)) { | |
d1999e9e RV |
2569 | dev_priv->max_cdclk_freq = 528000; |
2570 | } else if (IS_GEN9_BC(dev_priv)) { | |
7ff89ca2 VS |
2571 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
2572 | int max_cdclk, vco; | |
2573 | ||
2574 | vco = dev_priv->skl_preferred_vco_freq; | |
2575 | WARN_ON(vco != 8100000 && vco != 8640000); | |
2576 | ||
2577 | /* | |
2578 | * Use the lower (vco 8640) cdclk values as a | |
2579 | * first guess. skl_calc_cdclk() will correct it | |
2580 | * if the preferred vco is 8100 instead. | |
2581 | */ | |
2582 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
2583 | max_cdclk = 617143; | |
2584 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
2585 | max_cdclk = 540000; | |
2586 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
2587 | max_cdclk = 432000; | |
2588 | else | |
2589 | max_cdclk = 308571; | |
2590 | ||
2591 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
2592 | } else if (IS_GEMINILAKE(dev_priv)) { | |
2593 | dev_priv->max_cdclk_freq = 316800; | |
2594 | } else if (IS_BROXTON(dev_priv)) { | |
2595 | dev_priv->max_cdclk_freq = 624000; | |
2596 | } else if (IS_BROADWELL(dev_priv)) { | |
2597 | /* | |
2598 | * FIXME with extra cooling we can allow | |
2599 | * 540 MHz for ULX and 675 Mhz for ULT. | |
2600 | * How can we know if extra cooling is | |
2601 | * available? PCI ID, VTB, something else? | |
2602 | */ | |
2603 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
2604 | dev_priv->max_cdclk_freq = 450000; | |
2605 | else if (IS_BDW_ULX(dev_priv)) | |
2606 | dev_priv->max_cdclk_freq = 450000; | |
2607 | else if (IS_BDW_ULT(dev_priv)) | |
2608 | dev_priv->max_cdclk_freq = 540000; | |
2609 | else | |
2610 | dev_priv->max_cdclk_freq = 675000; | |
2611 | } else if (IS_CHERRYVIEW(dev_priv)) { | |
2612 | dev_priv->max_cdclk_freq = 320000; | |
2613 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
2614 | dev_priv->max_cdclk_freq = 400000; | |
2615 | } else { | |
2616 | /* otherwise assume cdclk is fixed */ | |
49cd97a3 | 2617 | dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; |
7ff89ca2 VS |
2618 | } |
2619 | ||
2620 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); | |
2621 | ||
2622 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", | |
2623 | dev_priv->max_cdclk_freq); | |
2624 | ||
2625 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
2626 | dev_priv->max_dotclk_freq); | |
2627 | } | |
2628 | ||
2629 | /** | |
2630 | * intel_update_cdclk - Determine the current CDCLK frequency | |
2631 | * @dev_priv: i915 device | |
2632 | * | |
2633 | * Determine the current CDCLK frequency. | |
2634 | */ | |
2635 | void intel_update_cdclk(struct drm_i915_private *dev_priv) | |
2636 | { | |
49cd97a3 | 2637 | dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); |
7ff89ca2 | 2638 | |
7ff89ca2 VS |
2639 | /* |
2640 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): | |
2641 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
2642 | * of cdclk that generates 4MHz reference clock freq which is used to | |
2643 | * generate GMBus clock. This will vary with the cdclk freq. | |
2644 | */ | |
2645 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2646 | I915_WRITE(GMBUSFREQ_VLV, | |
49cd97a3 | 2647 | DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); |
7ff89ca2 VS |
2648 | } |
2649 | ||
9d81a997 RV |
2650 | static int cnp_rawclk(struct drm_i915_private *dev_priv) |
2651 | { | |
2652 | u32 rawclk; | |
2653 | int divider, fraction; | |
2654 | ||
2655 | if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { | |
2656 | /* 24 MHz */ | |
2657 | divider = 24000; | |
2658 | fraction = 0; | |
2659 | } else { | |
2660 | /* 19.2 MHz */ | |
2661 | divider = 19000; | |
2662 | fraction = 200; | |
2663 | } | |
2664 | ||
af4de6ad | 2665 | rawclk = CNP_RAWCLK_DIV(divider / 1000); |
704e504b PZ |
2666 | if (fraction) { |
2667 | int numerator = 1; | |
9d81a997 | 2668 | |
704e504b PZ |
2669 | rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, |
2670 | fraction) - 1); | |
2671 | if (HAS_PCH_ICP(dev_priv)) | |
2672 | rawclk |= ICP_RAWCLK_NUM(numerator); | |
4ef99abd AS |
2673 | } |
2674 | ||
4ef99abd | 2675 | I915_WRITE(PCH_RAWCLK_FREQ, rawclk); |
704e504b | 2676 | return divider + fraction; |
4ef99abd AS |
2677 | } |
2678 | ||
7ff89ca2 VS |
2679 | static int pch_rawclk(struct drm_i915_private *dev_priv) |
2680 | { | |
2681 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; | |
2682 | } | |
2683 | ||
2684 | static int vlv_hrawclk(struct drm_i915_private *dev_priv) | |
2685 | { | |
2686 | /* RAWCLK_FREQ_VLV register updated from power well code */ | |
2687 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", | |
2688 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
2689 | } | |
2690 | ||
2691 | static int g4x_hrawclk(struct drm_i915_private *dev_priv) | |
2692 | { | |
2693 | uint32_t clkcfg; | |
2694 | ||
2695 | /* hrawclock is 1/4 the FSB frequency */ | |
2696 | clkcfg = I915_READ(CLKCFG); | |
2697 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
2698 | case CLKCFG_FSB_400: | |
2699 | return 100000; | |
2700 | case CLKCFG_FSB_533: | |
2701 | return 133333; | |
2702 | case CLKCFG_FSB_667: | |
2703 | return 166667; | |
2704 | case CLKCFG_FSB_800: | |
2705 | return 200000; | |
2706 | case CLKCFG_FSB_1067: | |
6f38123e | 2707 | case CLKCFG_FSB_1067_ALT: |
7ff89ca2 VS |
2708 | return 266667; |
2709 | case CLKCFG_FSB_1333: | |
6f38123e | 2710 | case CLKCFG_FSB_1333_ALT: |
7ff89ca2 | 2711 | return 333333; |
7ff89ca2 VS |
2712 | default: |
2713 | return 133333; | |
2714 | } | |
2715 | } | |
2716 | ||
2717 | /** | |
2718 | * intel_update_rawclk - Determine the current RAWCLK frequency | |
2719 | * @dev_priv: i915 device | |
2720 | * | |
2721 | * Determine the current RAWCLK frequency. RAWCLK is a fixed | |
2722 | * frequency clock so this needs to done only once. | |
2723 | */ | |
2724 | void intel_update_rawclk(struct drm_i915_private *dev_priv) | |
2725 | { | |
704e504b | 2726 | if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv)) |
9d81a997 RV |
2727 | dev_priv->rawclk_freq = cnp_rawclk(dev_priv); |
2728 | else if (HAS_PCH_SPLIT(dev_priv)) | |
7ff89ca2 VS |
2729 | dev_priv->rawclk_freq = pch_rawclk(dev_priv); |
2730 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2731 | dev_priv->rawclk_freq = vlv_hrawclk(dev_priv); | |
2732 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
2733 | dev_priv->rawclk_freq = g4x_hrawclk(dev_priv); | |
2734 | else | |
2735 | /* no rawclk on other platforms, or no need to know it */ | |
2736 | return; | |
2737 | ||
2738 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
2739 | } | |
2740 | ||
2741 | /** | |
2742 | * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks | |
2743 | * @dev_priv: i915 device | |
2744 | */ | |
2745 | void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) | |
2746 | { | |
b0587e4d VS |
2747 | if (IS_CHERRYVIEW(dev_priv)) { |
2748 | dev_priv->display.set_cdclk = chv_set_cdclk; | |
2749 | dev_priv->display.modeset_calc_cdclk = | |
2750 | vlv_modeset_calc_cdclk; | |
2751 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
2752 | dev_priv->display.set_cdclk = vlv_set_cdclk; | |
7ff89ca2 VS |
2753 | dev_priv->display.modeset_calc_cdclk = |
2754 | vlv_modeset_calc_cdclk; | |
2755 | } else if (IS_BROADWELL(dev_priv)) { | |
b0587e4d | 2756 | dev_priv->display.set_cdclk = bdw_set_cdclk; |
7ff89ca2 VS |
2757 | dev_priv->display.modeset_calc_cdclk = |
2758 | bdw_modeset_calc_cdclk; | |
2759 | } else if (IS_GEN9_LP(dev_priv)) { | |
b0587e4d | 2760 | dev_priv->display.set_cdclk = bxt_set_cdclk; |
7ff89ca2 VS |
2761 | dev_priv->display.modeset_calc_cdclk = |
2762 | bxt_modeset_calc_cdclk; | |
2763 | } else if (IS_GEN9_BC(dev_priv)) { | |
b0587e4d | 2764 | dev_priv->display.set_cdclk = skl_set_cdclk; |
7ff89ca2 VS |
2765 | dev_priv->display.modeset_calc_cdclk = |
2766 | skl_modeset_calc_cdclk; | |
d1999e9e RV |
2767 | } else if (IS_CANNONLAKE(dev_priv)) { |
2768 | dev_priv->display.set_cdclk = cnl_set_cdclk; | |
2769 | dev_priv->display.modeset_calc_cdclk = | |
2770 | cnl_modeset_calc_cdclk; | |
186a277e PZ |
2771 | } else if (IS_ICELAKE(dev_priv)) { |
2772 | dev_priv->display.set_cdclk = icl_set_cdclk; | |
2773 | dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk; | |
7ff89ca2 VS |
2774 | } |
2775 | ||
186a277e PZ |
2776 | if (IS_ICELAKE(dev_priv)) |
2777 | dev_priv->display.get_cdclk = icl_get_cdclk; | |
2778 | else if (IS_CANNONLAKE(dev_priv)) | |
945f2672 VS |
2779 | dev_priv->display.get_cdclk = cnl_get_cdclk; |
2780 | else if (IS_GEN9_BC(dev_priv)) | |
7ff89ca2 VS |
2781 | dev_priv->display.get_cdclk = skl_get_cdclk; |
2782 | else if (IS_GEN9_LP(dev_priv)) | |
2783 | dev_priv->display.get_cdclk = bxt_get_cdclk; | |
2784 | else if (IS_BROADWELL(dev_priv)) | |
2785 | dev_priv->display.get_cdclk = bdw_get_cdclk; | |
2786 | else if (IS_HASWELL(dev_priv)) | |
2787 | dev_priv->display.get_cdclk = hsw_get_cdclk; | |
2788 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2789 | dev_priv->display.get_cdclk = vlv_get_cdclk; | |
cf819eff | 2790 | else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) |
7ff89ca2 | 2791 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; |
cf819eff | 2792 | else if (IS_GEN(dev_priv, 5)) |
7ff89ca2 VS |
2793 | dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; |
2794 | else if (IS_GM45(dev_priv)) | |
2795 | dev_priv->display.get_cdclk = gm45_get_cdclk; | |
6b9e441d | 2796 | else if (IS_G45(dev_priv)) |
7ff89ca2 VS |
2797 | dev_priv->display.get_cdclk = g33_get_cdclk; |
2798 | else if (IS_I965GM(dev_priv)) | |
2799 | dev_priv->display.get_cdclk = i965gm_get_cdclk; | |
2800 | else if (IS_I965G(dev_priv)) | |
2801 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
2802 | else if (IS_PINEVIEW(dev_priv)) | |
2803 | dev_priv->display.get_cdclk = pnv_get_cdclk; | |
2804 | else if (IS_G33(dev_priv)) | |
2805 | dev_priv->display.get_cdclk = g33_get_cdclk; | |
2806 | else if (IS_I945GM(dev_priv)) | |
2807 | dev_priv->display.get_cdclk = i945gm_get_cdclk; | |
2808 | else if (IS_I945G(dev_priv)) | |
2809 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
2810 | else if (IS_I915GM(dev_priv)) | |
2811 | dev_priv->display.get_cdclk = i915gm_get_cdclk; | |
2812 | else if (IS_I915G(dev_priv)) | |
2813 | dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; | |
2814 | else if (IS_I865G(dev_priv)) | |
2815 | dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; | |
2816 | else if (IS_I85X(dev_priv)) | |
2817 | dev_priv->display.get_cdclk = i85x_get_cdclk; | |
2818 | else if (IS_I845G(dev_priv)) | |
2819 | dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; | |
2820 | else { /* 830 */ | |
2821 | WARN(!IS_I830(dev_priv), | |
2822 | "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
2823 | dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; | |
2824 | } | |
2825 | } |