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7ff89ca2 VS |
1 | /* |
2 | * Copyright © 2006-2017 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "intel_drv.h" | |
25 | ||
26 | /** | |
27 | * DOC: CDCLK / RAWCLK | |
28 | * | |
29 | * The display engine uses several different clocks to do its work. There | |
30 | * are two main clocks involved that aren't directly related to the actual | |
31 | * pixel clock or any symbol/bit clock of the actual output port. These | |
32 | * are the core display clock (CDCLK) and RAWCLK. | |
33 | * | |
34 | * CDCLK clocks most of the display pipe logic, and thus its frequency | |
35 | * must be high enough to support the rate at which pixels are flowing | |
36 | * through the pipes. Downscaling must also be accounted as that increases | |
37 | * the effective pixel rate. | |
38 | * | |
39 | * On several platforms the CDCLK frequency can be changed dynamically | |
40 | * to minimize power consumption for a given display configuration. | |
41 | * Typically changes to the CDCLK frequency require all the display pipes | |
42 | * to be shut down while the frequency is being changed. | |
43 | * | |
44 | * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. | |
45 | * DMC will not change the active CDCLK frequency however, so that part | |
46 | * will still be performed by the driver directly. | |
47 | * | |
48 | * RAWCLK is a fixed frequency clock, often used by various auxiliary | |
49 | * blocks such as AUX CH or backlight PWM. Hence the only thing we | |
50 | * really need to know about RAWCLK is its frequency so that various | |
51 | * dividers can be programmed correctly. | |
52 | */ | |
53 | ||
49cd97a3 VS |
54 | static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, |
55 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 56 | { |
49cd97a3 | 57 | cdclk_state->cdclk = 133333; |
7ff89ca2 VS |
58 | } |
59 | ||
49cd97a3 VS |
60 | static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, |
61 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 62 | { |
49cd97a3 | 63 | cdclk_state->cdclk = 200000; |
7ff89ca2 VS |
64 | } |
65 | ||
49cd97a3 VS |
66 | static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, |
67 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 68 | { |
49cd97a3 | 69 | cdclk_state->cdclk = 266667; |
7ff89ca2 VS |
70 | } |
71 | ||
49cd97a3 VS |
72 | static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, |
73 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 74 | { |
49cd97a3 | 75 | cdclk_state->cdclk = 333333; |
7ff89ca2 VS |
76 | } |
77 | ||
49cd97a3 VS |
78 | static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, |
79 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 80 | { |
49cd97a3 | 81 | cdclk_state->cdclk = 400000; |
7ff89ca2 VS |
82 | } |
83 | ||
49cd97a3 VS |
84 | static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, |
85 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 86 | { |
49cd97a3 | 87 | cdclk_state->cdclk = 450000; |
7ff89ca2 VS |
88 | } |
89 | ||
49cd97a3 VS |
90 | static void i85x_get_cdclk(struct drm_i915_private *dev_priv, |
91 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
92 | { |
93 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
94 | u16 hpllcc = 0; | |
95 | ||
96 | /* | |
97 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
98 | * encoding is different :( | |
99 | * FIXME is this the right way to detect 852GM/852GMV? | |
100 | */ | |
49cd97a3 VS |
101 | if (pdev->revision == 0x1) { |
102 | cdclk_state->cdclk = 133333; | |
103 | return; | |
104 | } | |
7ff89ca2 VS |
105 | |
106 | pci_bus_read_config_word(pdev->bus, | |
107 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
108 | ||
109 | /* Assume that the hardware is in the high speed state. This | |
110 | * should be the default. | |
111 | */ | |
112 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
113 | case GC_CLOCK_133_200: | |
114 | case GC_CLOCK_133_200_2: | |
115 | case GC_CLOCK_100_200: | |
49cd97a3 VS |
116 | cdclk_state->cdclk = 200000; |
117 | break; | |
7ff89ca2 | 118 | case GC_CLOCK_166_250: |
49cd97a3 VS |
119 | cdclk_state->cdclk = 250000; |
120 | break; | |
7ff89ca2 | 121 | case GC_CLOCK_100_133: |
49cd97a3 VS |
122 | cdclk_state->cdclk = 133333; |
123 | break; | |
7ff89ca2 VS |
124 | case GC_CLOCK_133_266: |
125 | case GC_CLOCK_133_266_2: | |
126 | case GC_CLOCK_166_266: | |
49cd97a3 VS |
127 | cdclk_state->cdclk = 266667; |
128 | break; | |
7ff89ca2 | 129 | } |
7ff89ca2 VS |
130 | } |
131 | ||
49cd97a3 VS |
132 | static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, |
133 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
134 | { |
135 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
136 | u16 gcfgc = 0; | |
137 | ||
138 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
139 | ||
49cd97a3 VS |
140 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { |
141 | cdclk_state->cdclk = 133333; | |
142 | return; | |
143 | } | |
7ff89ca2 VS |
144 | |
145 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
146 | case GC_DISPLAY_CLOCK_333_320_MHZ: | |
49cd97a3 VS |
147 | cdclk_state->cdclk = 333333; |
148 | break; | |
7ff89ca2 VS |
149 | default: |
150 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
49cd97a3 VS |
151 | cdclk_state->cdclk = 190000; |
152 | break; | |
7ff89ca2 VS |
153 | } |
154 | } | |
155 | ||
49cd97a3 VS |
156 | static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, |
157 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
158 | { |
159 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
160 | u16 gcfgc = 0; | |
161 | ||
162 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
163 | ||
49cd97a3 VS |
164 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { |
165 | cdclk_state->cdclk = 133333; | |
166 | return; | |
167 | } | |
7ff89ca2 VS |
168 | |
169 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
170 | case GC_DISPLAY_CLOCK_333_320_MHZ: | |
49cd97a3 VS |
171 | cdclk_state->cdclk = 320000; |
172 | break; | |
7ff89ca2 VS |
173 | default: |
174 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
49cd97a3 VS |
175 | cdclk_state->cdclk = 200000; |
176 | break; | |
7ff89ca2 VS |
177 | } |
178 | } | |
179 | ||
180 | static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) | |
181 | { | |
182 | static const unsigned int blb_vco[8] = { | |
183 | [0] = 3200000, | |
184 | [1] = 4000000, | |
185 | [2] = 5333333, | |
186 | [3] = 4800000, | |
187 | [4] = 6400000, | |
188 | }; | |
189 | static const unsigned int pnv_vco[8] = { | |
190 | [0] = 3200000, | |
191 | [1] = 4000000, | |
192 | [2] = 5333333, | |
193 | [3] = 4800000, | |
194 | [4] = 2666667, | |
195 | }; | |
196 | static const unsigned int cl_vco[8] = { | |
197 | [0] = 3200000, | |
198 | [1] = 4000000, | |
199 | [2] = 5333333, | |
200 | [3] = 6400000, | |
201 | [4] = 3333333, | |
202 | [5] = 3566667, | |
203 | [6] = 4266667, | |
204 | }; | |
205 | static const unsigned int elk_vco[8] = { | |
206 | [0] = 3200000, | |
207 | [1] = 4000000, | |
208 | [2] = 5333333, | |
209 | [3] = 4800000, | |
210 | }; | |
211 | static const unsigned int ctg_vco[8] = { | |
212 | [0] = 3200000, | |
213 | [1] = 4000000, | |
214 | [2] = 5333333, | |
215 | [3] = 6400000, | |
216 | [4] = 2666667, | |
217 | [5] = 4266667, | |
218 | }; | |
219 | const unsigned int *vco_table; | |
220 | unsigned int vco; | |
221 | uint8_t tmp = 0; | |
222 | ||
223 | /* FIXME other chipsets? */ | |
224 | if (IS_GM45(dev_priv)) | |
225 | vco_table = ctg_vco; | |
226 | else if (IS_G4X(dev_priv)) | |
227 | vco_table = elk_vco; | |
228 | else if (IS_I965GM(dev_priv)) | |
229 | vco_table = cl_vco; | |
230 | else if (IS_PINEVIEW(dev_priv)) | |
231 | vco_table = pnv_vco; | |
232 | else if (IS_G33(dev_priv)) | |
233 | vco_table = blb_vco; | |
234 | else | |
235 | return 0; | |
236 | ||
237 | tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); | |
238 | ||
239 | vco = vco_table[tmp & 0x7]; | |
240 | if (vco == 0) | |
241 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
242 | else | |
243 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
244 | ||
245 | return vco; | |
246 | } | |
247 | ||
49cd97a3 VS |
248 | static void g33_get_cdclk(struct drm_i915_private *dev_priv, |
249 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
250 | { |
251 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
252 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
253 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
254 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
255 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
256 | const uint8_t *div_table; | |
49cd97a3 | 257 | unsigned int cdclk_sel; |
7ff89ca2 VS |
258 | uint16_t tmp = 0; |
259 | ||
49cd97a3 VS |
260 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
261 | ||
7ff89ca2 VS |
262 | pci_read_config_word(pdev, GCFGC, &tmp); |
263 | ||
264 | cdclk_sel = (tmp >> 4) & 0x7; | |
265 | ||
266 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
267 | goto fail; | |
268 | ||
49cd97a3 | 269 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
270 | case 3200000: |
271 | div_table = div_3200; | |
272 | break; | |
273 | case 4000000: | |
274 | div_table = div_4000; | |
275 | break; | |
276 | case 4800000: | |
277 | div_table = div_4800; | |
278 | break; | |
279 | case 5333333: | |
280 | div_table = div_5333; | |
281 | break; | |
282 | default: | |
283 | goto fail; | |
284 | } | |
285 | ||
49cd97a3 VS |
286 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, |
287 | div_table[cdclk_sel]); | |
288 | return; | |
7ff89ca2 VS |
289 | |
290 | fail: | |
291 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", | |
49cd97a3 VS |
292 | cdclk_state->vco, tmp); |
293 | cdclk_state->cdclk = 190476; | |
7ff89ca2 VS |
294 | } |
295 | ||
49cd97a3 VS |
296 | static void pnv_get_cdclk(struct drm_i915_private *dev_priv, |
297 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
298 | { |
299 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
300 | u16 gcfgc = 0; | |
301 | ||
302 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
303 | ||
304 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
305 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
49cd97a3 VS |
306 | cdclk_state->cdclk = 266667; |
307 | break; | |
7ff89ca2 | 308 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
49cd97a3 VS |
309 | cdclk_state->cdclk = 333333; |
310 | break; | |
7ff89ca2 | 311 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
49cd97a3 VS |
312 | cdclk_state->cdclk = 444444; |
313 | break; | |
7ff89ca2 | 314 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
49cd97a3 VS |
315 | cdclk_state->cdclk = 200000; |
316 | break; | |
7ff89ca2 VS |
317 | default: |
318 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
319 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
49cd97a3 VS |
320 | cdclk_state->cdclk = 133333; |
321 | break; | |
7ff89ca2 | 322 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
49cd97a3 VS |
323 | cdclk_state->cdclk = 166667; |
324 | break; | |
7ff89ca2 VS |
325 | } |
326 | } | |
327 | ||
49cd97a3 VS |
328 | static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, |
329 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
330 | { |
331 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
332 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
333 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
334 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
335 | const uint8_t *div_table; | |
49cd97a3 | 336 | unsigned int cdclk_sel; |
7ff89ca2 VS |
337 | uint16_t tmp = 0; |
338 | ||
49cd97a3 VS |
339 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
340 | ||
7ff89ca2 VS |
341 | pci_read_config_word(pdev, GCFGC, &tmp); |
342 | ||
343 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
344 | ||
345 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
346 | goto fail; | |
347 | ||
49cd97a3 | 348 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
349 | case 3200000: |
350 | div_table = div_3200; | |
351 | break; | |
352 | case 4000000: | |
353 | div_table = div_4000; | |
354 | break; | |
355 | case 5333333: | |
356 | div_table = div_5333; | |
357 | break; | |
358 | default: | |
359 | goto fail; | |
360 | } | |
361 | ||
49cd97a3 VS |
362 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, |
363 | div_table[cdclk_sel]); | |
364 | return; | |
7ff89ca2 VS |
365 | |
366 | fail: | |
367 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", | |
49cd97a3 VS |
368 | cdclk_state->vco, tmp); |
369 | cdclk_state->cdclk = 200000; | |
7ff89ca2 VS |
370 | } |
371 | ||
49cd97a3 VS |
372 | static void gm45_get_cdclk(struct drm_i915_private *dev_priv, |
373 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
374 | { |
375 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
49cd97a3 | 376 | unsigned int cdclk_sel; |
7ff89ca2 VS |
377 | uint16_t tmp = 0; |
378 | ||
49cd97a3 VS |
379 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
380 | ||
7ff89ca2 VS |
381 | pci_read_config_word(pdev, GCFGC, &tmp); |
382 | ||
383 | cdclk_sel = (tmp >> 12) & 0x1; | |
384 | ||
49cd97a3 | 385 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
386 | case 2666667: |
387 | case 4000000: | |
388 | case 5333333: | |
49cd97a3 VS |
389 | cdclk_state->cdclk = cdclk_sel ? 333333 : 222222; |
390 | break; | |
7ff89ca2 | 391 | case 3200000: |
49cd97a3 VS |
392 | cdclk_state->cdclk = cdclk_sel ? 320000 : 228571; |
393 | break; | |
7ff89ca2 VS |
394 | default: |
395 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", | |
49cd97a3 VS |
396 | cdclk_state->vco, tmp); |
397 | cdclk_state->cdclk = 222222; | |
398 | break; | |
7ff89ca2 VS |
399 | } |
400 | } | |
401 | ||
49cd97a3 VS |
402 | static void hsw_get_cdclk(struct drm_i915_private *dev_priv, |
403 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
404 | { |
405 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
406 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
407 | ||
408 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
49cd97a3 | 409 | cdclk_state->cdclk = 800000; |
7ff89ca2 | 410 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
49cd97a3 | 411 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 412 | else if (freq == LCPLL_CLK_FREQ_450) |
49cd97a3 | 413 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 414 | else if (IS_HSW_ULT(dev_priv)) |
49cd97a3 | 415 | cdclk_state->cdclk = 337500; |
7ff89ca2 | 416 | else |
49cd97a3 | 417 | cdclk_state->cdclk = 540000; |
7ff89ca2 VS |
418 | } |
419 | ||
420 | static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, | |
421 | int max_pixclk) | |
422 | { | |
423 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? | |
424 | 333333 : 320000; | |
425 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; | |
426 | ||
427 | /* | |
428 | * We seem to get an unstable or solid color picture at 200MHz. | |
429 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
430 | * are off. | |
431 | */ | |
432 | if (!IS_CHERRYVIEW(dev_priv) && | |
433 | max_pixclk > freq_320*limit/100) | |
434 | return 400000; | |
435 | else if (max_pixclk > 266667*limit/100) | |
436 | return freq_320; | |
437 | else if (max_pixclk > 0) | |
438 | return 266667; | |
439 | else | |
440 | return 200000; | |
441 | } | |
442 | ||
49cd97a3 VS |
443 | static void vlv_get_cdclk(struct drm_i915_private *dev_priv, |
444 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 445 | { |
49cd97a3 VS |
446 | cdclk_state->vco = vlv_get_hpll_vco(dev_priv); |
447 | cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", | |
448 | CCK_DISPLAY_CLOCK_CONTROL, | |
449 | cdclk_state->vco); | |
7ff89ca2 VS |
450 | } |
451 | ||
452 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) | |
453 | { | |
454 | unsigned int credits, default_credits; | |
455 | ||
456 | if (IS_CHERRYVIEW(dev_priv)) | |
457 | default_credits = PFI_CREDIT(12); | |
458 | else | |
459 | default_credits = PFI_CREDIT(8); | |
460 | ||
49cd97a3 | 461 | if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { |
7ff89ca2 VS |
462 | /* CHV suggested value is 31 or 63 */ |
463 | if (IS_CHERRYVIEW(dev_priv)) | |
464 | credits = PFI_CREDIT_63; | |
465 | else | |
466 | credits = PFI_CREDIT(15); | |
467 | } else { | |
468 | credits = default_credits; | |
469 | } | |
470 | ||
471 | /* | |
472 | * WA - write default credits before re-programming | |
473 | * FIXME: should we also set the resend bit here? | |
474 | */ | |
475 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
476 | default_credits); | |
477 | ||
478 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
479 | credits | PFI_CREDIT_RESEND); | |
480 | ||
481 | /* | |
482 | * FIXME is this guaranteed to clear | |
483 | * immediately or should we poll for it? | |
484 | */ | |
485 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
486 | } | |
487 | ||
83c5fda7 VS |
488 | static void vlv_set_cdclk(struct drm_i915_private *dev_priv, |
489 | const struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 490 | { |
83c5fda7 | 491 | int cdclk = cdclk_state->cdclk; |
7ff89ca2 VS |
492 | u32 val, cmd; |
493 | ||
7ff89ca2 VS |
494 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
495 | cmd = 2; | |
496 | else if (cdclk == 266667) | |
497 | cmd = 1; | |
498 | else | |
499 | cmd = 0; | |
500 | ||
501 | mutex_lock(&dev_priv->rps.hw_lock); | |
502 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
503 | val &= ~DSPFREQGUAR_MASK; | |
504 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
505 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
506 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
507 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
508 | 50)) { | |
509 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
510 | } | |
511 | mutex_unlock(&dev_priv->rps.hw_lock); | |
512 | ||
513 | mutex_lock(&dev_priv->sb_lock); | |
514 | ||
515 | if (cdclk == 400000) { | |
516 | u32 divider; | |
517 | ||
518 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, | |
519 | cdclk) - 1; | |
520 | ||
521 | /* adjust cdclk divider */ | |
522 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
523 | val &= ~CCK_FREQUENCY_VALUES; | |
524 | val |= divider; | |
525 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
526 | ||
527 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
528 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
529 | 50)) | |
530 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
531 | } | |
532 | ||
533 | /* adjust self-refresh exit latency value */ | |
534 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
535 | val &= ~0x7f; | |
536 | ||
537 | /* | |
538 | * For high bandwidth configs, we set a higher latency in the bunit | |
539 | * so that the core display fetch happens in time to avoid underruns. | |
540 | */ | |
541 | if (cdclk == 400000) | |
542 | val |= 4500 / 250; /* 4.5 usec */ | |
543 | else | |
544 | val |= 3000 / 250; /* 3.0 usec */ | |
545 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
546 | ||
547 | mutex_unlock(&dev_priv->sb_lock); | |
548 | ||
549 | intel_update_cdclk(dev_priv); | |
550 | } | |
551 | ||
83c5fda7 VS |
552 | static void chv_set_cdclk(struct drm_i915_private *dev_priv, |
553 | const struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 554 | { |
83c5fda7 | 555 | int cdclk = cdclk_state->cdclk; |
7ff89ca2 VS |
556 | u32 val, cmd; |
557 | ||
7ff89ca2 VS |
558 | switch (cdclk) { |
559 | case 333333: | |
560 | case 320000: | |
561 | case 266667: | |
562 | case 200000: | |
563 | break; | |
564 | default: | |
565 | MISSING_CASE(cdclk); | |
566 | return; | |
567 | } | |
568 | ||
569 | /* | |
570 | * Specs are full of misinformation, but testing on actual | |
571 | * hardware has shown that we just need to write the desired | |
572 | * CCK divider into the Punit register. | |
573 | */ | |
574 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
575 | ||
576 | mutex_lock(&dev_priv->rps.hw_lock); | |
577 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
578 | val &= ~DSPFREQGUAR_MASK_CHV; | |
579 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
580 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
581 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
582 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
583 | 50)) { | |
584 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
585 | } | |
586 | mutex_unlock(&dev_priv->rps.hw_lock); | |
587 | ||
588 | intel_update_cdclk(dev_priv); | |
589 | } | |
590 | ||
591 | static int bdw_calc_cdclk(int max_pixclk) | |
592 | { | |
593 | if (max_pixclk > 540000) | |
594 | return 675000; | |
595 | else if (max_pixclk > 450000) | |
596 | return 540000; | |
597 | else if (max_pixclk > 337500) | |
598 | return 450000; | |
599 | else | |
600 | return 337500; | |
601 | } | |
602 | ||
49cd97a3 VS |
603 | static void bdw_get_cdclk(struct drm_i915_private *dev_priv, |
604 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
605 | { |
606 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
607 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
608 | ||
609 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
49cd97a3 | 610 | cdclk_state->cdclk = 800000; |
7ff89ca2 | 611 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
49cd97a3 | 612 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 613 | else if (freq == LCPLL_CLK_FREQ_450) |
49cd97a3 | 614 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 615 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) |
49cd97a3 | 616 | cdclk_state->cdclk = 540000; |
7ff89ca2 | 617 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) |
49cd97a3 | 618 | cdclk_state->cdclk = 337500; |
7ff89ca2 | 619 | else |
49cd97a3 | 620 | cdclk_state->cdclk = 675000; |
7ff89ca2 VS |
621 | } |
622 | ||
83c5fda7 VS |
623 | static void bdw_set_cdclk(struct drm_i915_private *dev_priv, |
624 | const struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 625 | { |
83c5fda7 | 626 | int cdclk = cdclk_state->cdclk; |
7ff89ca2 VS |
627 | uint32_t val, data; |
628 | int ret; | |
629 | ||
630 | if (WARN((I915_READ(LCPLL_CTL) & | |
631 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
632 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
633 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
634 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
635 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
636 | return; | |
637 | ||
638 | mutex_lock(&dev_priv->rps.hw_lock); | |
639 | ret = sandybridge_pcode_write(dev_priv, | |
640 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
641 | mutex_unlock(&dev_priv->rps.hw_lock); | |
642 | if (ret) { | |
643 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
644 | return; | |
645 | } | |
646 | ||
647 | val = I915_READ(LCPLL_CTL); | |
648 | val |= LCPLL_CD_SOURCE_FCLK; | |
649 | I915_WRITE(LCPLL_CTL, val); | |
650 | ||
651 | if (wait_for_us(I915_READ(LCPLL_CTL) & | |
652 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
653 | DRM_ERROR("Switching to FCLK failed\n"); | |
654 | ||
655 | val = I915_READ(LCPLL_CTL); | |
656 | val &= ~LCPLL_CLK_FREQ_MASK; | |
657 | ||
658 | switch (cdclk) { | |
659 | case 450000: | |
660 | val |= LCPLL_CLK_FREQ_450; | |
661 | data = 0; | |
662 | break; | |
663 | case 540000: | |
664 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
665 | data = 1; | |
666 | break; | |
667 | case 337500: | |
668 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
669 | data = 2; | |
670 | break; | |
671 | case 675000: | |
672 | val |= LCPLL_CLK_FREQ_675_BDW; | |
673 | data = 3; | |
674 | break; | |
675 | default: | |
676 | WARN(1, "invalid cdclk frequency\n"); | |
677 | return; | |
678 | } | |
679 | ||
680 | I915_WRITE(LCPLL_CTL, val); | |
681 | ||
682 | val = I915_READ(LCPLL_CTL); | |
683 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
684 | I915_WRITE(LCPLL_CTL, val); | |
685 | ||
686 | if (wait_for_us((I915_READ(LCPLL_CTL) & | |
687 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
688 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
689 | ||
690 | mutex_lock(&dev_priv->rps.hw_lock); | |
691 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
692 | mutex_unlock(&dev_priv->rps.hw_lock); | |
693 | ||
694 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); | |
695 | ||
696 | intel_update_cdclk(dev_priv); | |
697 | ||
49cd97a3 | 698 | WARN(cdclk != dev_priv->cdclk.hw.cdclk, |
7ff89ca2 | 699 | "cdclk requested %d kHz but got %d kHz\n", |
49cd97a3 | 700 | cdclk, dev_priv->cdclk.hw.cdclk); |
7ff89ca2 VS |
701 | } |
702 | ||
703 | static int skl_calc_cdclk(int max_pixclk, int vco) | |
704 | { | |
705 | if (vco == 8640000) { | |
706 | if (max_pixclk > 540000) | |
707 | return 617143; | |
708 | else if (max_pixclk > 432000) | |
709 | return 540000; | |
710 | else if (max_pixclk > 308571) | |
711 | return 432000; | |
712 | else | |
713 | return 308571; | |
714 | } else { | |
715 | if (max_pixclk > 540000) | |
716 | return 675000; | |
717 | else if (max_pixclk > 450000) | |
718 | return 540000; | |
719 | else if (max_pixclk > 337500) | |
720 | return 450000; | |
721 | else | |
722 | return 337500; | |
723 | } | |
724 | } | |
725 | ||
49cd97a3 VS |
726 | static void skl_dpll0_update(struct drm_i915_private *dev_priv, |
727 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
728 | { |
729 | u32 val; | |
730 | ||
49cd97a3 VS |
731 | cdclk_state->ref = 24000; |
732 | cdclk_state->vco = 0; | |
7ff89ca2 VS |
733 | |
734 | val = I915_READ(LCPLL1_CTL); | |
735 | if ((val & LCPLL_PLL_ENABLE) == 0) | |
736 | return; | |
737 | ||
738 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) | |
739 | return; | |
740 | ||
741 | val = I915_READ(DPLL_CTRL1); | |
742 | ||
743 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | | |
744 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
745 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
746 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
747 | return; | |
748 | ||
749 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { | |
750 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
751 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
752 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
753 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
49cd97a3 | 754 | cdclk_state->vco = 8100000; |
7ff89ca2 VS |
755 | break; |
756 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
757 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
49cd97a3 | 758 | cdclk_state->vco = 8640000; |
7ff89ca2 VS |
759 | break; |
760 | default: | |
761 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
762 | break; | |
763 | } | |
764 | } | |
765 | ||
49cd97a3 VS |
766 | static void skl_get_cdclk(struct drm_i915_private *dev_priv, |
767 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
768 | { |
769 | u32 cdctl; | |
770 | ||
49cd97a3 | 771 | skl_dpll0_update(dev_priv, cdclk_state); |
7ff89ca2 | 772 | |
49cd97a3 VS |
773 | cdclk_state->cdclk = cdclk_state->ref; |
774 | ||
775 | if (cdclk_state->vco == 0) | |
776 | return; | |
7ff89ca2 VS |
777 | |
778 | cdctl = I915_READ(CDCLK_CTL); | |
779 | ||
49cd97a3 | 780 | if (cdclk_state->vco == 8640000) { |
7ff89ca2 VS |
781 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
782 | case CDCLK_FREQ_450_432: | |
49cd97a3 VS |
783 | cdclk_state->cdclk = 432000; |
784 | break; | |
7ff89ca2 | 785 | case CDCLK_FREQ_337_308: |
49cd97a3 VS |
786 | cdclk_state->cdclk = 308571; |
787 | break; | |
7ff89ca2 | 788 | case CDCLK_FREQ_540: |
49cd97a3 VS |
789 | cdclk_state->cdclk = 540000; |
790 | break; | |
7ff89ca2 | 791 | case CDCLK_FREQ_675_617: |
49cd97a3 VS |
792 | cdclk_state->cdclk = 617143; |
793 | break; | |
7ff89ca2 VS |
794 | default: |
795 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); | |
49cd97a3 | 796 | break; |
7ff89ca2 VS |
797 | } |
798 | } else { | |
799 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
800 | case CDCLK_FREQ_450_432: | |
49cd97a3 VS |
801 | cdclk_state->cdclk = 450000; |
802 | break; | |
7ff89ca2 | 803 | case CDCLK_FREQ_337_308: |
49cd97a3 VS |
804 | cdclk_state->cdclk = 337500; |
805 | break; | |
7ff89ca2 | 806 | case CDCLK_FREQ_540: |
49cd97a3 VS |
807 | cdclk_state->cdclk = 540000; |
808 | break; | |
7ff89ca2 | 809 | case CDCLK_FREQ_675_617: |
49cd97a3 VS |
810 | cdclk_state->cdclk = 675000; |
811 | break; | |
7ff89ca2 VS |
812 | default: |
813 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); | |
49cd97a3 | 814 | break; |
7ff89ca2 VS |
815 | } |
816 | } | |
7ff89ca2 VS |
817 | } |
818 | ||
819 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
820 | static int skl_cdclk_decimal(int cdclk) | |
821 | { | |
822 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
823 | } | |
824 | ||
825 | static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, | |
826 | int vco) | |
827 | { | |
828 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
829 | ||
830 | dev_priv->skl_preferred_vco_freq = vco; | |
831 | ||
832 | if (changed) | |
833 | intel_update_max_cdclk(dev_priv); | |
834 | } | |
835 | ||
836 | static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) | |
837 | { | |
838 | int min_cdclk = skl_calc_cdclk(0, vco); | |
839 | u32 val; | |
840 | ||
841 | WARN_ON(vco != 8100000 && vco != 8640000); | |
842 | ||
843 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
844 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); | |
845 | I915_WRITE(CDCLK_CTL, val); | |
846 | POSTING_READ(CDCLK_CTL); | |
847 | ||
848 | /* | |
849 | * We always enable DPLL0 with the lowest link rate possible, but still | |
850 | * taking into account the VCO required to operate the eDP panel at the | |
851 | * desired frequency. The usual DP link rates operate with a VCO of | |
852 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
853 | * The modeset code is responsible for the selection of the exact link | |
854 | * rate later on, with the constraint of choosing a frequency that | |
855 | * works with vco. | |
856 | */ | |
857 | val = I915_READ(DPLL_CTRL1); | |
858 | ||
859 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
860 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
861 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
862 | if (vco == 8640000) | |
863 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
864 | SKL_DPLL0); | |
865 | else | |
866 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
867 | SKL_DPLL0); | |
868 | ||
869 | I915_WRITE(DPLL_CTRL1, val); | |
870 | POSTING_READ(DPLL_CTRL1); | |
871 | ||
872 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
873 | ||
874 | if (intel_wait_for_register(dev_priv, | |
875 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
876 | 5)) | |
877 | DRM_ERROR("DPLL0 not locked\n"); | |
878 | ||
49cd97a3 | 879 | dev_priv->cdclk.hw.vco = vco; |
7ff89ca2 VS |
880 | |
881 | /* We'll want to keep using the current vco from now on. */ | |
882 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
883 | } | |
884 | ||
885 | static void skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
886 | { | |
887 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
888 | if (intel_wait_for_register(dev_priv, | |
889 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
890 | 1)) | |
891 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
892 | ||
49cd97a3 | 893 | dev_priv->cdclk.hw.vco = 0; |
7ff89ca2 VS |
894 | } |
895 | ||
896 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, | |
83c5fda7 | 897 | const struct intel_cdclk_state *cdclk_state) |
7ff89ca2 | 898 | { |
83c5fda7 VS |
899 | int cdclk = cdclk_state->cdclk; |
900 | int vco = cdclk_state->vco; | |
7ff89ca2 VS |
901 | u32 freq_select, pcu_ack; |
902 | int ret; | |
903 | ||
904 | WARN_ON((cdclk == 24000) != (vco == 0)); | |
905 | ||
906 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", | |
907 | cdclk, vco); | |
908 | ||
909 | mutex_lock(&dev_priv->rps.hw_lock); | |
910 | ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, | |
911 | SKL_CDCLK_PREPARE_FOR_CHANGE, | |
912 | SKL_CDCLK_READY_FOR_CHANGE, | |
913 | SKL_CDCLK_READY_FOR_CHANGE, 3); | |
914 | mutex_unlock(&dev_priv->rps.hw_lock); | |
915 | if (ret) { | |
916 | DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", | |
917 | ret); | |
918 | return; | |
919 | } | |
920 | ||
921 | /* set CDCLK_CTL */ | |
922 | switch (cdclk) { | |
923 | case 450000: | |
924 | case 432000: | |
925 | freq_select = CDCLK_FREQ_450_432; | |
926 | pcu_ack = 1; | |
927 | break; | |
928 | case 540000: | |
929 | freq_select = CDCLK_FREQ_540; | |
930 | pcu_ack = 2; | |
931 | break; | |
932 | case 308571: | |
933 | case 337500: | |
934 | default: | |
935 | freq_select = CDCLK_FREQ_337_308; | |
936 | pcu_ack = 0; | |
937 | break; | |
938 | case 617143: | |
939 | case 675000: | |
940 | freq_select = CDCLK_FREQ_675_617; | |
941 | pcu_ack = 3; | |
942 | break; | |
943 | } | |
944 | ||
49cd97a3 VS |
945 | if (dev_priv->cdclk.hw.vco != 0 && |
946 | dev_priv->cdclk.hw.vco != vco) | |
7ff89ca2 VS |
947 | skl_dpll0_disable(dev_priv); |
948 | ||
49cd97a3 | 949 | if (dev_priv->cdclk.hw.vco != vco) |
7ff89ca2 VS |
950 | skl_dpll0_enable(dev_priv, vco); |
951 | ||
952 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); | |
953 | POSTING_READ(CDCLK_CTL); | |
954 | ||
955 | /* inform PCU of the change */ | |
956 | mutex_lock(&dev_priv->rps.hw_lock); | |
957 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
958 | mutex_unlock(&dev_priv->rps.hw_lock); | |
959 | ||
960 | intel_update_cdclk(dev_priv); | |
961 | } | |
962 | ||
963 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
964 | { | |
965 | uint32_t cdctl, expected; | |
966 | ||
967 | /* | |
968 | * check if the pre-os initialized the display | |
969 | * There is SWF18 scratchpad register defined which is set by the | |
970 | * pre-os which can be used by the OS drivers to check the status | |
971 | */ | |
972 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
973 | goto sanitize; | |
974 | ||
975 | intel_update_cdclk(dev_priv); | |
976 | /* Is PLL enabled and locked ? */ | |
49cd97a3 VS |
977 | if (dev_priv->cdclk.hw.vco == 0 || |
978 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref) | |
7ff89ca2 VS |
979 | goto sanitize; |
980 | ||
981 | /* DPLL okay; verify the cdclock | |
982 | * | |
983 | * Noticed in some instances that the freq selection is correct but | |
984 | * decimal part is programmed wrong from BIOS where pre-os does not | |
985 | * enable display. Verify the same as well. | |
986 | */ | |
987 | cdctl = I915_READ(CDCLK_CTL); | |
988 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
49cd97a3 | 989 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); |
7ff89ca2 VS |
990 | if (cdctl == expected) |
991 | /* All well; nothing to sanitize */ | |
992 | return; | |
993 | ||
994 | sanitize: | |
995 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
996 | ||
997 | /* force cdclk programming */ | |
49cd97a3 | 998 | dev_priv->cdclk.hw.cdclk = 0; |
7ff89ca2 | 999 | /* force full PLL disable + enable */ |
49cd97a3 | 1000 | dev_priv->cdclk.hw.vco = -1; |
7ff89ca2 VS |
1001 | } |
1002 | ||
1003 | /** | |
1004 | * skl_init_cdclk - Initialize CDCLK on SKL | |
1005 | * @dev_priv: i915 device | |
1006 | * | |
1007 | * Initialize CDCLK for SKL and derivatives. This is generally | |
1008 | * done only during the display core initialization sequence, | |
1009 | * after which the DMC will take care of turning CDCLK off/on | |
1010 | * as needed. | |
1011 | */ | |
1012 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
1013 | { | |
83c5fda7 | 1014 | struct intel_cdclk_state cdclk_state; |
7ff89ca2 VS |
1015 | |
1016 | skl_sanitize_cdclk(dev_priv); | |
1017 | ||
49cd97a3 VS |
1018 | if (dev_priv->cdclk.hw.cdclk != 0 && |
1019 | dev_priv->cdclk.hw.vco != 0) { | |
7ff89ca2 VS |
1020 | /* |
1021 | * Use the current vco as our initial | |
1022 | * guess as to what the preferred vco is. | |
1023 | */ | |
1024 | if (dev_priv->skl_preferred_vco_freq == 0) | |
1025 | skl_set_preferred_cdclk_vco(dev_priv, | |
49cd97a3 | 1026 | dev_priv->cdclk.hw.vco); |
7ff89ca2 VS |
1027 | return; |
1028 | } | |
1029 | ||
83c5fda7 VS |
1030 | cdclk_state = dev_priv->cdclk.hw; |
1031 | ||
1032 | cdclk_state.vco = dev_priv->skl_preferred_vco_freq; | |
1033 | if (cdclk_state.vco == 0) | |
1034 | cdclk_state.vco = 8100000; | |
1035 | cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); | |
7ff89ca2 | 1036 | |
83c5fda7 | 1037 | skl_set_cdclk(dev_priv, &cdclk_state); |
7ff89ca2 VS |
1038 | } |
1039 | ||
1040 | /** | |
1041 | * skl_uninit_cdclk - Uninitialize CDCLK on SKL | |
1042 | * @dev_priv: i915 device | |
1043 | * | |
1044 | * Uninitialize CDCLK for SKL and derivatives. This is done only | |
1045 | * during the display core uninitialization sequence. | |
1046 | */ | |
1047 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
1048 | { | |
83c5fda7 VS |
1049 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; |
1050 | ||
1051 | cdclk_state.cdclk = cdclk_state.ref; | |
1052 | cdclk_state.vco = 0; | |
1053 | ||
1054 | skl_set_cdclk(dev_priv, &cdclk_state); | |
7ff89ca2 VS |
1055 | } |
1056 | ||
1057 | static int bxt_calc_cdclk(int max_pixclk) | |
1058 | { | |
1059 | if (max_pixclk > 576000) | |
1060 | return 624000; | |
1061 | else if (max_pixclk > 384000) | |
1062 | return 576000; | |
1063 | else if (max_pixclk > 288000) | |
1064 | return 384000; | |
1065 | else if (max_pixclk > 144000) | |
1066 | return 288000; | |
1067 | else | |
1068 | return 144000; | |
1069 | } | |
1070 | ||
1071 | static int glk_calc_cdclk(int max_pixclk) | |
1072 | { | |
1073 | if (max_pixclk > 2 * 158400) | |
1074 | return 316800; | |
1075 | else if (max_pixclk > 2 * 79200) | |
1076 | return 158400; | |
1077 | else | |
1078 | return 79200; | |
1079 | } | |
1080 | ||
1081 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) | |
1082 | { | |
1083 | int ratio; | |
1084 | ||
49cd97a3 | 1085 | if (cdclk == dev_priv->cdclk.hw.ref) |
7ff89ca2 VS |
1086 | return 0; |
1087 | ||
1088 | switch (cdclk) { | |
1089 | default: | |
1090 | MISSING_CASE(cdclk); | |
1091 | case 144000: | |
1092 | case 288000: | |
1093 | case 384000: | |
1094 | case 576000: | |
1095 | ratio = 60; | |
1096 | break; | |
1097 | case 624000: | |
1098 | ratio = 65; | |
1099 | break; | |
1100 | } | |
1101 | ||
49cd97a3 | 1102 | return dev_priv->cdclk.hw.ref * ratio; |
7ff89ca2 VS |
1103 | } |
1104 | ||
1105 | static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) | |
1106 | { | |
1107 | int ratio; | |
1108 | ||
49cd97a3 | 1109 | if (cdclk == dev_priv->cdclk.hw.ref) |
7ff89ca2 VS |
1110 | return 0; |
1111 | ||
1112 | switch (cdclk) { | |
1113 | default: | |
1114 | MISSING_CASE(cdclk); | |
1115 | case 79200: | |
1116 | case 158400: | |
1117 | case 316800: | |
1118 | ratio = 33; | |
1119 | break; | |
1120 | } | |
1121 | ||
49cd97a3 | 1122 | return dev_priv->cdclk.hw.ref * ratio; |
7ff89ca2 VS |
1123 | } |
1124 | ||
49cd97a3 VS |
1125 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv, |
1126 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
1127 | { |
1128 | u32 val; | |
1129 | ||
49cd97a3 VS |
1130 | cdclk_state->ref = 19200; |
1131 | cdclk_state->vco = 0; | |
7ff89ca2 VS |
1132 | |
1133 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1134 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) | |
1135 | return; | |
1136 | ||
1137 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) | |
1138 | return; | |
1139 | ||
1140 | val = I915_READ(BXT_DE_PLL_CTL); | |
49cd97a3 | 1141 | cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; |
7ff89ca2 VS |
1142 | } |
1143 | ||
49cd97a3 VS |
1144 | static void bxt_get_cdclk(struct drm_i915_private *dev_priv, |
1145 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
1146 | { |
1147 | u32 divider; | |
49cd97a3 | 1148 | int div; |
7ff89ca2 | 1149 | |
49cd97a3 | 1150 | bxt_de_pll_update(dev_priv, cdclk_state); |
7ff89ca2 | 1151 | |
49cd97a3 VS |
1152 | cdclk_state->cdclk = cdclk_state->ref; |
1153 | ||
1154 | if (cdclk_state->vco == 0) | |
1155 | return; | |
7ff89ca2 VS |
1156 | |
1157 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
1158 | ||
1159 | switch (divider) { | |
1160 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
1161 | div = 2; | |
1162 | break; | |
1163 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
1164 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); | |
1165 | div = 3; | |
1166 | break; | |
1167 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
1168 | div = 4; | |
1169 | break; | |
1170 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
1171 | div = 8; | |
1172 | break; | |
1173 | default: | |
1174 | MISSING_CASE(divider); | |
49cd97a3 | 1175 | return; |
7ff89ca2 VS |
1176 | } |
1177 | ||
49cd97a3 | 1178 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); |
7ff89ca2 VS |
1179 | } |
1180 | ||
1181 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) | |
1182 | { | |
1183 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
1184 | ||
1185 | /* Timeout 200us */ | |
1186 | if (intel_wait_for_register(dev_priv, | |
1187 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
1188 | 1)) | |
1189 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); | |
1190 | ||
49cd97a3 | 1191 | dev_priv->cdclk.hw.vco = 0; |
7ff89ca2 VS |
1192 | } |
1193 | ||
1194 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) | |
1195 | { | |
49cd97a3 | 1196 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); |
7ff89ca2 VS |
1197 | u32 val; |
1198 | ||
1199 | val = I915_READ(BXT_DE_PLL_CTL); | |
1200 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
1201 | val |= BXT_DE_PLL_RATIO(ratio); | |
1202 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
1203 | ||
1204 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
1205 | ||
1206 | /* Timeout 200us */ | |
1207 | if (intel_wait_for_register(dev_priv, | |
1208 | BXT_DE_PLL_ENABLE, | |
1209 | BXT_DE_PLL_LOCK, | |
1210 | BXT_DE_PLL_LOCK, | |
1211 | 1)) | |
1212 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
1213 | ||
49cd97a3 | 1214 | dev_priv->cdclk.hw.vco = vco; |
7ff89ca2 VS |
1215 | } |
1216 | ||
8f0cfa4d | 1217 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, |
83c5fda7 | 1218 | const struct intel_cdclk_state *cdclk_state) |
7ff89ca2 | 1219 | { |
83c5fda7 VS |
1220 | int cdclk = cdclk_state->cdclk; |
1221 | int vco = cdclk_state->vco; | |
7ff89ca2 | 1222 | u32 val, divider; |
8f0cfa4d | 1223 | int ret; |
7ff89ca2 VS |
1224 | |
1225 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", | |
1226 | cdclk, vco); | |
1227 | ||
1228 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
1229 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
1230 | case 8: | |
1231 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
1232 | break; | |
1233 | case 4: | |
1234 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
1235 | break; | |
1236 | case 3: | |
1237 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); | |
1238 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
1239 | break; | |
1240 | case 2: | |
1241 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
1242 | break; | |
1243 | default: | |
49cd97a3 | 1244 | WARN_ON(cdclk != dev_priv->cdclk.hw.ref); |
7ff89ca2 VS |
1245 | WARN_ON(vco != 0); |
1246 | ||
1247 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
1248 | break; | |
1249 | } | |
1250 | ||
1251 | /* Inform power controller of upcoming frequency change */ | |
1252 | mutex_lock(&dev_priv->rps.hw_lock); | |
1253 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
1254 | 0x80000000); | |
1255 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1256 | ||
1257 | if (ret) { | |
1258 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
1259 | ret, cdclk); | |
1260 | return; | |
1261 | } | |
1262 | ||
49cd97a3 VS |
1263 | if (dev_priv->cdclk.hw.vco != 0 && |
1264 | dev_priv->cdclk.hw.vco != vco) | |
7ff89ca2 VS |
1265 | bxt_de_pll_disable(dev_priv); |
1266 | ||
49cd97a3 | 1267 | if (dev_priv->cdclk.hw.vco != vco) |
7ff89ca2 VS |
1268 | bxt_de_pll_enable(dev_priv, vco); |
1269 | ||
1270 | val = divider | skl_cdclk_decimal(cdclk); | |
1271 | /* | |
1272 | * FIXME if only the cd2x divider needs changing, it could be done | |
1273 | * without shutting off the pipe (if only one pipe is active). | |
1274 | */ | |
1275 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
1276 | /* | |
1277 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
1278 | * enable otherwise. | |
1279 | */ | |
1280 | if (cdclk >= 500000) | |
1281 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
1282 | I915_WRITE(CDCLK_CTL, val); | |
1283 | ||
1284 | mutex_lock(&dev_priv->rps.hw_lock); | |
1285 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
1286 | DIV_ROUND_UP(cdclk, 25000)); | |
1287 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1288 | ||
1289 | if (ret) { | |
1290 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
1291 | ret, cdclk); | |
1292 | return; | |
1293 | } | |
1294 | ||
1295 | intel_update_cdclk(dev_priv); | |
1296 | } | |
1297 | ||
1298 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
1299 | { | |
1300 | u32 cdctl, expected; | |
1301 | ||
1302 | intel_update_cdclk(dev_priv); | |
1303 | ||
49cd97a3 VS |
1304 | if (dev_priv->cdclk.hw.vco == 0 || |
1305 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref) | |
7ff89ca2 VS |
1306 | goto sanitize; |
1307 | ||
1308 | /* DPLL okay; verify the cdclock | |
1309 | * | |
1310 | * Some BIOS versions leave an incorrect decimal frequency value and | |
1311 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
1312 | * so sanitize this register. | |
1313 | */ | |
1314 | cdctl = I915_READ(CDCLK_CTL); | |
1315 | /* | |
1316 | * Let's ignore the pipe field, since BIOS could have configured the | |
1317 | * dividers both synching to an active pipe, or asynchronously | |
1318 | * (PIPE_NONE). | |
1319 | */ | |
1320 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
1321 | ||
1322 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
49cd97a3 | 1323 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); |
7ff89ca2 VS |
1324 | /* |
1325 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
1326 | * enable otherwise. | |
1327 | */ | |
49cd97a3 | 1328 | if (dev_priv->cdclk.hw.cdclk >= 500000) |
7ff89ca2 VS |
1329 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
1330 | ||
1331 | if (cdctl == expected) | |
1332 | /* All well; nothing to sanitize */ | |
1333 | return; | |
1334 | ||
1335 | sanitize: | |
1336 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
1337 | ||
1338 | /* force cdclk programming */ | |
49cd97a3 | 1339 | dev_priv->cdclk.hw.cdclk = 0; |
7ff89ca2 VS |
1340 | |
1341 | /* force full PLL disable + enable */ | |
49cd97a3 | 1342 | dev_priv->cdclk.hw.vco = -1; |
7ff89ca2 VS |
1343 | } |
1344 | ||
1345 | /** | |
1346 | * bxt_init_cdclk - Initialize CDCLK on BXT | |
1347 | * @dev_priv: i915 device | |
1348 | * | |
1349 | * Initialize CDCLK for BXT and derivatives. This is generally | |
1350 | * done only during the display core initialization sequence, | |
1351 | * after which the DMC will take care of turning CDCLK off/on | |
1352 | * as needed. | |
1353 | */ | |
1354 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) | |
1355 | { | |
83c5fda7 | 1356 | struct intel_cdclk_state cdclk_state; |
7ff89ca2 VS |
1357 | |
1358 | bxt_sanitize_cdclk(dev_priv); | |
1359 | ||
49cd97a3 VS |
1360 | if (dev_priv->cdclk.hw.cdclk != 0 && |
1361 | dev_priv->cdclk.hw.vco != 0) | |
7ff89ca2 VS |
1362 | return; |
1363 | ||
83c5fda7 VS |
1364 | cdclk_state = dev_priv->cdclk.hw; |
1365 | ||
7ff89ca2 VS |
1366 | /* |
1367 | * FIXME: | |
1368 | * - The initial CDCLK needs to be read from VBT. | |
1369 | * Need to make this change after VBT has changes for BXT. | |
1370 | */ | |
8f0cfa4d | 1371 | if (IS_GEMINILAKE(dev_priv)) { |
83c5fda7 VS |
1372 | cdclk_state.cdclk = glk_calc_cdclk(0); |
1373 | cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk); | |
8f0cfa4d | 1374 | } else { |
83c5fda7 VS |
1375 | cdclk_state.cdclk = bxt_calc_cdclk(0); |
1376 | cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk); | |
8f0cfa4d | 1377 | } |
7ff89ca2 | 1378 | |
83c5fda7 | 1379 | bxt_set_cdclk(dev_priv, &cdclk_state); |
7ff89ca2 VS |
1380 | } |
1381 | ||
1382 | /** | |
1383 | * bxt_uninit_cdclk - Uninitialize CDCLK on BXT | |
1384 | * @dev_priv: i915 device | |
1385 | * | |
1386 | * Uninitialize CDCLK for BXT and derivatives. This is done only | |
1387 | * during the display core uninitialization sequence. | |
1388 | */ | |
1389 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) | |
1390 | { | |
83c5fda7 VS |
1391 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; |
1392 | ||
1393 | cdclk_state.cdclk = cdclk_state.ref; | |
1394 | cdclk_state.vco = 0; | |
1395 | ||
1396 | bxt_set_cdclk(dev_priv, &cdclk_state); | |
49cd97a3 VS |
1397 | } |
1398 | ||
1399 | /** | |
1400 | * intel_cdclk_state_compare - Determine if two CDCLK states differ | |
1401 | * @a: first CDCLK state | |
1402 | * @b: second CDCLK state | |
1403 | * | |
1404 | * Returns: | |
1405 | * True if the CDCLK states are identical, false if they differ. | |
1406 | */ | |
1407 | bool intel_cdclk_state_compare(const struct intel_cdclk_state *a, | |
1408 | const struct intel_cdclk_state *b) | |
1409 | { | |
1410 | return memcmp(a, b, sizeof(*a)) == 0; | |
7ff89ca2 VS |
1411 | } |
1412 | ||
1413 | static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, | |
1414 | int pixel_rate) | |
1415 | { | |
1416 | struct drm_i915_private *dev_priv = | |
1417 | to_i915(crtc_state->base.crtc->dev); | |
1418 | ||
1419 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
1420 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
1421 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); | |
1422 | ||
1423 | /* BSpec says "Do not use DisplayPort with CDCLK less than | |
1424 | * 432 MHz, audio enabled, port width x4, and link rate | |
1425 | * HBR2 (5.4 GHz), or else there may be audio corruption or | |
1426 | * screen corruption." | |
1427 | */ | |
1428 | if (intel_crtc_has_dp_encoder(crtc_state) && | |
1429 | crtc_state->has_audio && | |
1430 | crtc_state->port_clock >= 540000 && | |
1431 | crtc_state->lane_count == 4) | |
1432 | pixel_rate = max(432000, pixel_rate); | |
1433 | ||
1434 | return pixel_rate; | |
1435 | } | |
1436 | ||
1437 | /* compute the max rate for new configuration */ | |
1438 | static int intel_max_pixel_rate(struct drm_atomic_state *state) | |
1439 | { | |
1440 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
1441 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
1442 | struct drm_crtc *crtc; | |
1443 | struct drm_crtc_state *cstate; | |
1444 | struct intel_crtc_state *crtc_state; | |
1445 | unsigned int max_pixel_rate = 0, i; | |
1446 | enum pipe pipe; | |
1447 | ||
1448 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, | |
1449 | sizeof(intel_state->min_pixclk)); | |
1450 | ||
1451 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
1452 | int pixel_rate; | |
1453 | ||
1454 | crtc_state = to_intel_crtc_state(cstate); | |
1455 | if (!crtc_state->base.enable) { | |
1456 | intel_state->min_pixclk[i] = 0; | |
1457 | continue; | |
1458 | } | |
1459 | ||
1460 | pixel_rate = crtc_state->pixel_rate; | |
1461 | ||
1462 | if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv)) | |
1463 | pixel_rate = | |
1464 | bdw_adjust_min_pipe_pixel_rate(crtc_state, | |
1465 | pixel_rate); | |
1466 | ||
1467 | intel_state->min_pixclk[i] = pixel_rate; | |
1468 | } | |
1469 | ||
1470 | for_each_pipe(dev_priv, pipe) | |
1471 | max_pixel_rate = max(intel_state->min_pixclk[pipe], | |
1472 | max_pixel_rate); | |
1473 | ||
1474 | return max_pixel_rate; | |
1475 | } | |
1476 | ||
1477 | static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state) | |
1478 | { | |
3d5dbb10 | 1479 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
7ff89ca2 VS |
1480 | int max_pixclk = intel_max_pixel_rate(state); |
1481 | struct intel_atomic_state *intel_state = | |
1482 | to_intel_atomic_state(state); | |
bb0f4aab VS |
1483 | int cdclk; |
1484 | ||
1485 | cdclk = vlv_calc_cdclk(dev_priv, max_pixclk); | |
7ff89ca2 | 1486 | |
bb0f4aab VS |
1487 | if (cdclk > dev_priv->max_cdclk_freq) { |
1488 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
1489 | cdclk, dev_priv->max_cdclk_freq); | |
1490 | return -EINVAL; | |
1491 | } | |
7ff89ca2 | 1492 | |
bb0f4aab VS |
1493 | intel_state->cdclk.logical.cdclk = cdclk; |
1494 | ||
1495 | if (!intel_state->active_crtcs) { | |
1496 | cdclk = vlv_calc_cdclk(dev_priv, 0); | |
1497 | ||
1498 | intel_state->cdclk.actual.cdclk = cdclk; | |
1499 | } else { | |
1500 | intel_state->cdclk.actual = | |
1501 | intel_state->cdclk.logical; | |
1502 | } | |
7ff89ca2 VS |
1503 | |
1504 | return 0; | |
1505 | } | |
1506 | ||
1507 | static void vlv_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
1508 | { | |
3d5dbb10 | 1509 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
7ff89ca2 VS |
1510 | |
1511 | /* | |
1512 | * FIXME: We can end up here with all power domains off, yet | |
1513 | * with a CDCLK frequency other than the minimum. To account | |
1514 | * for this take the PIPE-A power domain, which covers the HW | |
1515 | * blocks needed for the following programming. This can be | |
1516 | * removed once it's guaranteed that we get here either with | |
1517 | * the minimum CDCLK set, or the required power domains | |
1518 | * enabled. | |
1519 | */ | |
1520 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
1521 | ||
1522 | if (IS_CHERRYVIEW(dev_priv)) | |
83c5fda7 | 1523 | chv_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
7ff89ca2 | 1524 | else |
83c5fda7 | 1525 | vlv_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
7ff89ca2 VS |
1526 | |
1527 | vlv_program_pfi_credits(dev_priv); | |
1528 | ||
1529 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); | |
1530 | } | |
1531 | ||
1532 | static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state) | |
1533 | { | |
1534 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
1535 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
1536 | int max_pixclk = intel_max_pixel_rate(state); | |
1537 | int cdclk; | |
1538 | ||
1539 | /* | |
1540 | * FIXME should also account for plane ratio | |
1541 | * once 64bpp pixel formats are supported. | |
1542 | */ | |
1543 | cdclk = bdw_calc_cdclk(max_pixclk); | |
1544 | ||
1545 | if (cdclk > dev_priv->max_cdclk_freq) { | |
1546 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
1547 | cdclk, dev_priv->max_cdclk_freq); | |
1548 | return -EINVAL; | |
1549 | } | |
1550 | ||
bb0f4aab VS |
1551 | intel_state->cdclk.logical.cdclk = cdclk; |
1552 | ||
1553 | if (!intel_state->active_crtcs) { | |
1554 | cdclk = bdw_calc_cdclk(0); | |
1555 | ||
1556 | intel_state->cdclk.actual.cdclk = cdclk; | |
1557 | } else { | |
1558 | intel_state->cdclk.actual = | |
1559 | intel_state->cdclk.logical; | |
1560 | } | |
7ff89ca2 VS |
1561 | |
1562 | return 0; | |
1563 | } | |
1564 | ||
1565 | static void bdw_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
1566 | { | |
3d5dbb10 | 1567 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
7ff89ca2 | 1568 | |
83c5fda7 | 1569 | bdw_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
7ff89ca2 VS |
1570 | } |
1571 | ||
1572 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) | |
1573 | { | |
1574 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
1575 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
1576 | const int max_pixclk = intel_max_pixel_rate(state); | |
bb0f4aab VS |
1577 | int cdclk, vco; |
1578 | ||
1579 | vco = intel_state->cdclk.logical.vco; | |
1580 | if (!vco) | |
1581 | vco = dev_priv->skl_preferred_vco_freq; | |
7ff89ca2 VS |
1582 | |
1583 | /* | |
1584 | * FIXME should also account for plane ratio | |
1585 | * once 64bpp pixel formats are supported. | |
1586 | */ | |
1587 | cdclk = skl_calc_cdclk(max_pixclk, vco); | |
1588 | ||
7ff89ca2 | 1589 | if (cdclk > dev_priv->max_cdclk_freq) { |
bb0f4aab VS |
1590 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
1591 | cdclk, dev_priv->max_cdclk_freq); | |
1592 | return -EINVAL; | |
7ff89ca2 VS |
1593 | } |
1594 | ||
bb0f4aab VS |
1595 | intel_state->cdclk.logical.vco = vco; |
1596 | intel_state->cdclk.logical.cdclk = cdclk; | |
1597 | ||
1598 | if (!intel_state->active_crtcs) { | |
1599 | cdclk = skl_calc_cdclk(0, vco); | |
1600 | ||
1601 | intel_state->cdclk.actual.vco = vco; | |
1602 | intel_state->cdclk.actual.cdclk = cdclk; | |
1603 | } else { | |
1604 | intel_state->cdclk.actual = | |
1605 | intel_state->cdclk.logical; | |
1606 | } | |
7ff89ca2 VS |
1607 | |
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
1612 | { | |
1613 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); | |
7ff89ca2 | 1614 | |
83c5fda7 | 1615 | skl_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
7ff89ca2 VS |
1616 | } |
1617 | ||
1618 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) | |
1619 | { | |
1620 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
1621 | int max_pixclk = intel_max_pixel_rate(state); | |
1622 | struct intel_atomic_state *intel_state = | |
1623 | to_intel_atomic_state(state); | |
bb0f4aab | 1624 | int cdclk, vco; |
7ff89ca2 | 1625 | |
bb0f4aab | 1626 | if (IS_GEMINILAKE(dev_priv)) { |
7ff89ca2 | 1627 | cdclk = glk_calc_cdclk(max_pixclk); |
bb0f4aab VS |
1628 | vco = glk_de_pll_vco(dev_priv, cdclk); |
1629 | } else { | |
7ff89ca2 | 1630 | cdclk = bxt_calc_cdclk(max_pixclk); |
bb0f4aab VS |
1631 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
1632 | } | |
1633 | ||
1634 | if (cdclk > dev_priv->max_cdclk_freq) { | |
1635 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
1636 | cdclk, dev_priv->max_cdclk_freq); | |
1637 | return -EINVAL; | |
1638 | } | |
7ff89ca2 | 1639 | |
bb0f4aab VS |
1640 | intel_state->cdclk.logical.vco = vco; |
1641 | intel_state->cdclk.logical.cdclk = cdclk; | |
7ff89ca2 VS |
1642 | |
1643 | if (!intel_state->active_crtcs) { | |
bb0f4aab | 1644 | if (IS_GEMINILAKE(dev_priv)) { |
7ff89ca2 | 1645 | cdclk = glk_calc_cdclk(0); |
bb0f4aab VS |
1646 | vco = glk_de_pll_vco(dev_priv, cdclk); |
1647 | } else { | |
7ff89ca2 | 1648 | cdclk = bxt_calc_cdclk(0); |
bb0f4aab VS |
1649 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
1650 | } | |
7ff89ca2 | 1651 | |
bb0f4aab VS |
1652 | intel_state->cdclk.actual.vco = vco; |
1653 | intel_state->cdclk.actual.cdclk = cdclk; | |
1654 | } else { | |
1655 | intel_state->cdclk.actual = | |
1656 | intel_state->cdclk.logical; | |
7ff89ca2 VS |
1657 | } |
1658 | ||
1659 | return 0; | |
1660 | } | |
1661 | ||
1662 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
1663 | { | |
8f0cfa4d | 1664 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
7ff89ca2 | 1665 | |
83c5fda7 | 1666 | bxt_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
7ff89ca2 VS |
1667 | } |
1668 | ||
1669 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) | |
1670 | { | |
1671 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
1672 | ||
1673 | if (IS_GEMINILAKE(dev_priv)) | |
1674 | return 2 * max_cdclk_freq; | |
1675 | else if (INTEL_INFO(dev_priv)->gen >= 9 || | |
1676 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
1677 | return max_cdclk_freq; | |
1678 | else if (IS_CHERRYVIEW(dev_priv)) | |
1679 | return max_cdclk_freq*95/100; | |
1680 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
1681 | return 2*max_cdclk_freq*90/100; | |
1682 | else | |
1683 | return max_cdclk_freq*90/100; | |
1684 | } | |
1685 | ||
1686 | /** | |
1687 | * intel_update_max_cdclk - Determine the maximum support CDCLK frequency | |
1688 | * @dev_priv: i915 device | |
1689 | * | |
1690 | * Determine the maximum CDCLK frequency the platform supports, and also | |
1691 | * derive the maximum dot clock frequency the maximum CDCLK frequency | |
1692 | * allows. | |
1693 | */ | |
1694 | void intel_update_max_cdclk(struct drm_i915_private *dev_priv) | |
1695 | { | |
1696 | if (IS_GEN9_BC(dev_priv)) { | |
1697 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; | |
1698 | int max_cdclk, vco; | |
1699 | ||
1700 | vco = dev_priv->skl_preferred_vco_freq; | |
1701 | WARN_ON(vco != 8100000 && vco != 8640000); | |
1702 | ||
1703 | /* | |
1704 | * Use the lower (vco 8640) cdclk values as a | |
1705 | * first guess. skl_calc_cdclk() will correct it | |
1706 | * if the preferred vco is 8100 instead. | |
1707 | */ | |
1708 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
1709 | max_cdclk = 617143; | |
1710 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
1711 | max_cdclk = 540000; | |
1712 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
1713 | max_cdclk = 432000; | |
1714 | else | |
1715 | max_cdclk = 308571; | |
1716 | ||
1717 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
1718 | } else if (IS_GEMINILAKE(dev_priv)) { | |
1719 | dev_priv->max_cdclk_freq = 316800; | |
1720 | } else if (IS_BROXTON(dev_priv)) { | |
1721 | dev_priv->max_cdclk_freq = 624000; | |
1722 | } else if (IS_BROADWELL(dev_priv)) { | |
1723 | /* | |
1724 | * FIXME with extra cooling we can allow | |
1725 | * 540 MHz for ULX and 675 Mhz for ULT. | |
1726 | * How can we know if extra cooling is | |
1727 | * available? PCI ID, VTB, something else? | |
1728 | */ | |
1729 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
1730 | dev_priv->max_cdclk_freq = 450000; | |
1731 | else if (IS_BDW_ULX(dev_priv)) | |
1732 | dev_priv->max_cdclk_freq = 450000; | |
1733 | else if (IS_BDW_ULT(dev_priv)) | |
1734 | dev_priv->max_cdclk_freq = 540000; | |
1735 | else | |
1736 | dev_priv->max_cdclk_freq = 675000; | |
1737 | } else if (IS_CHERRYVIEW(dev_priv)) { | |
1738 | dev_priv->max_cdclk_freq = 320000; | |
1739 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
1740 | dev_priv->max_cdclk_freq = 400000; | |
1741 | } else { | |
1742 | /* otherwise assume cdclk is fixed */ | |
49cd97a3 | 1743 | dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; |
7ff89ca2 VS |
1744 | } |
1745 | ||
1746 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); | |
1747 | ||
1748 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", | |
1749 | dev_priv->max_cdclk_freq); | |
1750 | ||
1751 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
1752 | dev_priv->max_dotclk_freq); | |
1753 | } | |
1754 | ||
1755 | /** | |
1756 | * intel_update_cdclk - Determine the current CDCLK frequency | |
1757 | * @dev_priv: i915 device | |
1758 | * | |
1759 | * Determine the current CDCLK frequency. | |
1760 | */ | |
1761 | void intel_update_cdclk(struct drm_i915_private *dev_priv) | |
1762 | { | |
49cd97a3 | 1763 | dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); |
7ff89ca2 | 1764 | |
49cd97a3 VS |
1765 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
1766 | dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco, | |
1767 | dev_priv->cdclk.hw.ref); | |
7ff89ca2 VS |
1768 | |
1769 | /* | |
1770 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): | |
1771 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
1772 | * of cdclk that generates 4MHz reference clock freq which is used to | |
1773 | * generate GMBus clock. This will vary with the cdclk freq. | |
1774 | */ | |
1775 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
1776 | I915_WRITE(GMBUSFREQ_VLV, | |
49cd97a3 | 1777 | DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); |
7ff89ca2 VS |
1778 | } |
1779 | ||
1780 | static int pch_rawclk(struct drm_i915_private *dev_priv) | |
1781 | { | |
1782 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; | |
1783 | } | |
1784 | ||
1785 | static int vlv_hrawclk(struct drm_i915_private *dev_priv) | |
1786 | { | |
1787 | /* RAWCLK_FREQ_VLV register updated from power well code */ | |
1788 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", | |
1789 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
1790 | } | |
1791 | ||
1792 | static int g4x_hrawclk(struct drm_i915_private *dev_priv) | |
1793 | { | |
1794 | uint32_t clkcfg; | |
1795 | ||
1796 | /* hrawclock is 1/4 the FSB frequency */ | |
1797 | clkcfg = I915_READ(CLKCFG); | |
1798 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
1799 | case CLKCFG_FSB_400: | |
1800 | return 100000; | |
1801 | case CLKCFG_FSB_533: | |
1802 | return 133333; | |
1803 | case CLKCFG_FSB_667: | |
1804 | return 166667; | |
1805 | case CLKCFG_FSB_800: | |
1806 | return 200000; | |
1807 | case CLKCFG_FSB_1067: | |
1808 | return 266667; | |
1809 | case CLKCFG_FSB_1333: | |
1810 | return 333333; | |
1811 | /* these two are just a guess; one of them might be right */ | |
1812 | case CLKCFG_FSB_1600: | |
1813 | case CLKCFG_FSB_1600_ALT: | |
1814 | return 400000; | |
1815 | default: | |
1816 | return 133333; | |
1817 | } | |
1818 | } | |
1819 | ||
1820 | /** | |
1821 | * intel_update_rawclk - Determine the current RAWCLK frequency | |
1822 | * @dev_priv: i915 device | |
1823 | * | |
1824 | * Determine the current RAWCLK frequency. RAWCLK is a fixed | |
1825 | * frequency clock so this needs to done only once. | |
1826 | */ | |
1827 | void intel_update_rawclk(struct drm_i915_private *dev_priv) | |
1828 | { | |
1829 | if (HAS_PCH_SPLIT(dev_priv)) | |
1830 | dev_priv->rawclk_freq = pch_rawclk(dev_priv); | |
1831 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
1832 | dev_priv->rawclk_freq = vlv_hrawclk(dev_priv); | |
1833 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
1834 | dev_priv->rawclk_freq = g4x_hrawclk(dev_priv); | |
1835 | else | |
1836 | /* no rawclk on other platforms, or no need to know it */ | |
1837 | return; | |
1838 | ||
1839 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
1840 | } | |
1841 | ||
1842 | /** | |
1843 | * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks | |
1844 | * @dev_priv: i915 device | |
1845 | */ | |
1846 | void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) | |
1847 | { | |
1848 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
1849 | dev_priv->display.modeset_commit_cdclk = | |
1850 | vlv_modeset_commit_cdclk; | |
1851 | dev_priv->display.modeset_calc_cdclk = | |
1852 | vlv_modeset_calc_cdclk; | |
1853 | } else if (IS_BROADWELL(dev_priv)) { | |
1854 | dev_priv->display.modeset_commit_cdclk = | |
1855 | bdw_modeset_commit_cdclk; | |
1856 | dev_priv->display.modeset_calc_cdclk = | |
1857 | bdw_modeset_calc_cdclk; | |
1858 | } else if (IS_GEN9_LP(dev_priv)) { | |
1859 | dev_priv->display.modeset_commit_cdclk = | |
1860 | bxt_modeset_commit_cdclk; | |
1861 | dev_priv->display.modeset_calc_cdclk = | |
1862 | bxt_modeset_calc_cdclk; | |
1863 | } else if (IS_GEN9_BC(dev_priv)) { | |
1864 | dev_priv->display.modeset_commit_cdclk = | |
1865 | skl_modeset_commit_cdclk; | |
1866 | dev_priv->display.modeset_calc_cdclk = | |
1867 | skl_modeset_calc_cdclk; | |
1868 | } | |
1869 | ||
1870 | if (IS_GEN9_BC(dev_priv)) | |
1871 | dev_priv->display.get_cdclk = skl_get_cdclk; | |
1872 | else if (IS_GEN9_LP(dev_priv)) | |
1873 | dev_priv->display.get_cdclk = bxt_get_cdclk; | |
1874 | else if (IS_BROADWELL(dev_priv)) | |
1875 | dev_priv->display.get_cdclk = bdw_get_cdclk; | |
1876 | else if (IS_HASWELL(dev_priv)) | |
1877 | dev_priv->display.get_cdclk = hsw_get_cdclk; | |
1878 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
1879 | dev_priv->display.get_cdclk = vlv_get_cdclk; | |
1880 | else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
1881 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
1882 | else if (IS_GEN5(dev_priv)) | |
1883 | dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; | |
1884 | else if (IS_GM45(dev_priv)) | |
1885 | dev_priv->display.get_cdclk = gm45_get_cdclk; | |
1886 | else if (IS_G4X(dev_priv)) | |
1887 | dev_priv->display.get_cdclk = g33_get_cdclk; | |
1888 | else if (IS_I965GM(dev_priv)) | |
1889 | dev_priv->display.get_cdclk = i965gm_get_cdclk; | |
1890 | else if (IS_I965G(dev_priv)) | |
1891 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
1892 | else if (IS_PINEVIEW(dev_priv)) | |
1893 | dev_priv->display.get_cdclk = pnv_get_cdclk; | |
1894 | else if (IS_G33(dev_priv)) | |
1895 | dev_priv->display.get_cdclk = g33_get_cdclk; | |
1896 | else if (IS_I945GM(dev_priv)) | |
1897 | dev_priv->display.get_cdclk = i945gm_get_cdclk; | |
1898 | else if (IS_I945G(dev_priv)) | |
1899 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
1900 | else if (IS_I915GM(dev_priv)) | |
1901 | dev_priv->display.get_cdclk = i915gm_get_cdclk; | |
1902 | else if (IS_I915G(dev_priv)) | |
1903 | dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; | |
1904 | else if (IS_I865G(dev_priv)) | |
1905 | dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; | |
1906 | else if (IS_I85X(dev_priv)) | |
1907 | dev_priv->display.get_cdclk = i85x_get_cdclk; | |
1908 | else if (IS_I845G(dev_priv)) | |
1909 | dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; | |
1910 | else { /* 830 */ | |
1911 | WARN(!IS_I830(dev_priv), | |
1912 | "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
1913 | dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; | |
1914 | } | |
1915 | } |