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drm/i915: Move the decision to use the breadcrumb tasklet to the backend
[linux-block.git] / drivers / gpu / drm / i915 / intel_cdclk.c
CommitLineData
7ff89ca2
VS		 1/*
2 * Copyright © 2006-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include "intel_drv.h"
25
26/**
27 * DOC: CDCLK / RAWCLK
28 *
29 * The display engine uses several different clocks to do its work. There
30 * are two main clocks involved that aren't directly related to the actual
31 * pixel clock or any symbol/bit clock of the actual output port. These
32 * are the core display clock (CDCLK) and RAWCLK.
33 *
34 * CDCLK clocks most of the display pipe logic, and thus its frequency
35 * must be high enough to support the rate at which pixels are flowing
36 * through the pipes. Downscaling must also be accounted as that increases
37 * the effective pixel rate.
38 *
39 * On several platforms the CDCLK frequency can be changed dynamically
40 * to minimize power consumption for a given display configuration.
41 * Typically changes to the CDCLK frequency require all the display pipes
42 * to be shut down while the frequency is being changed.
43 *
44 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
45 * DMC will not change the active CDCLK frequency however, so that part
46 * will still be performed by the driver directly.
47 *
48 * RAWCLK is a fixed frequency clock, often used by various auxiliary
49 * blocks such as AUX CH or backlight PWM. Hence the only thing we
50 * really need to know about RAWCLK is its frequency so that various
51 * dividers can be programmed correctly.
52 */
53
49cd97a3
VS		 54static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
55 struct intel_cdclk_state *cdclk_state)
7ff89ca2 56{
49cd97a3 57 cdclk_state->cdclk = 133333;
7ff89ca2
VS		 58}
59
49cd97a3
VS		 60static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
61 struct intel_cdclk_state *cdclk_state)
7ff89ca2 62{
49cd97a3 63 cdclk_state->cdclk = 200000;
7ff89ca2
VS		 64}
65
49cd97a3
VS		 66static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
67 struct intel_cdclk_state *cdclk_state)
7ff89ca2 68{
49cd97a3 69 cdclk_state->cdclk = 266667;
7ff89ca2
VS		 70}
71
49cd97a3
VS		 72static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
73 struct intel_cdclk_state *cdclk_state)
7ff89ca2 74{
49cd97a3 75 cdclk_state->cdclk = 333333;
7ff89ca2
VS		 76}
77
49cd97a3
VS		 78static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
79 struct intel_cdclk_state *cdclk_state)
7ff89ca2 80{
49cd97a3 81 cdclk_state->cdclk = 400000;
7ff89ca2
VS		 82}
83
49cd97a3
VS		 84static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
85 struct intel_cdclk_state *cdclk_state)
7ff89ca2 86{
49cd97a3 87 cdclk_state->cdclk = 450000;
7ff89ca2
VS		 88}
89
49cd97a3
VS		 90static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
91 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 92{
93 struct pci_dev *pdev = dev_priv->drm.pdev;
94 u16 hpllcc = 0;
95
96 /*
97 * 852GM/852GMV only supports 133 MHz and the HPLLCC
98 * encoding is different :(
99 * FIXME is this the right way to detect 852GM/852GMV?
100 */
49cd97a3
VS		 101 if (pdev->revision == 0x1) {
102 cdclk_state->cdclk = 133333;
103 return;
104 }
7ff89ca2
VS		 105
106 pci_bus_read_config_word(pdev->bus,
107 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
108
109 /* Assume that the hardware is in the high speed state. This
110 * should be the default.
111 */
112 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
113 case GC_CLOCK_133_200:
114 case GC_CLOCK_133_200_2:
115 case GC_CLOCK_100_200:
49cd97a3
VS		 116 cdclk_state->cdclk = 200000;
117 break;
7ff89ca2 118 case GC_CLOCK_166_250:
49cd97a3
VS		 119 cdclk_state->cdclk = 250000;
120 break;
7ff89ca2 121 case GC_CLOCK_100_133:
49cd97a3
VS		 122 cdclk_state->cdclk = 133333;
123 break;
7ff89ca2
VS		 124 case GC_CLOCK_133_266:
125 case GC_CLOCK_133_266_2:
126 case GC_CLOCK_166_266:
49cd97a3
VS		 127 cdclk_state->cdclk = 266667;
128 break;
7ff89ca2 129 }
7ff89ca2
VS		 130}
131
49cd97a3
VS		 132static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
133 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 134{
135 struct pci_dev *pdev = dev_priv->drm.pdev;
136 u16 gcfgc = 0;
137
138 pci_read_config_word(pdev, GCFGC, &gcfgc);
139
49cd97a3
VS		 140 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
141 cdclk_state->cdclk = 133333;
142 return;
143 }
7ff89ca2
VS		 144
145 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
146 case GC_DISPLAY_CLOCK_333_320_MHZ:
49cd97a3
VS		 147 cdclk_state->cdclk = 333333;
148 break;
7ff89ca2
VS		 149 default:
150 case GC_DISPLAY_CLOCK_190_200_MHZ:
49cd97a3
VS		 151 cdclk_state->cdclk = 190000;
152 break;
7ff89ca2
VS		 153 }
154}
155
49cd97a3
VS		 156static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
157 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 158{
159 struct pci_dev *pdev = dev_priv->drm.pdev;
160 u16 gcfgc = 0;
161
162 pci_read_config_word(pdev, GCFGC, &gcfgc);
163
49cd97a3
VS		 164 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
165 cdclk_state->cdclk = 133333;
166 return;
167 }
7ff89ca2
VS		 168
169 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
170 case GC_DISPLAY_CLOCK_333_320_MHZ:
49cd97a3
VS		 171 cdclk_state->cdclk = 320000;
172 break;
7ff89ca2
VS		 173 default:
174 case GC_DISPLAY_CLOCK_190_200_MHZ:
49cd97a3
VS		 175 cdclk_state->cdclk = 200000;
176 break;
7ff89ca2
VS		 177 }
178}
179
180static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
181{
182 static const unsigned int blb_vco[8] = {
183 [0] = 3200000,
184 [1] = 4000000,
185 [2] = 5333333,
186 [3] = 4800000,
187 [4] = 6400000,
188 };
189 static const unsigned int pnv_vco[8] = {
190 [0] = 3200000,
191 [1] = 4000000,
192 [2] = 5333333,
193 [3] = 4800000,
194 [4] = 2666667,
195 };
196 static const unsigned int cl_vco[8] = {
197 [0] = 3200000,
198 [1] = 4000000,
199 [2] = 5333333,
200 [3] = 6400000,
201 [4] = 3333333,
202 [5] = 3566667,
203 [6] = 4266667,
204 };
205 static const unsigned int elk_vco[8] = {
206 [0] = 3200000,
207 [1] = 4000000,
208 [2] = 5333333,
209 [3] = 4800000,
210 };
211 static const unsigned int ctg_vco[8] = {
212 [0] = 3200000,
213 [1] = 4000000,
214 [2] = 5333333,
215 [3] = 6400000,
216 [4] = 2666667,
217 [5] = 4266667,
218 };
219 const unsigned int *vco_table;
220 unsigned int vco;
cbe974fb 221 u8 tmp = 0;
7ff89ca2
VS		 222
223 /* FIXME other chipsets? */
224 if (IS_GM45(dev_priv))
225 vco_table = ctg_vco;
6b9e441d 226 else if (IS_G45(dev_priv))
7ff89ca2
VS		 227 vco_table = elk_vco;
228 else if (IS_I965GM(dev_priv))
229 vco_table = cl_vco;
230 else if (IS_PINEVIEW(dev_priv))
231 vco_table = pnv_vco;
232 else if (IS_G33(dev_priv))
233 vco_table = blb_vco;
234 else
235 return 0;
236
4677faf6
VS		 237 tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ?
238 HPLLVCO_MOBILE : HPLLVCO);
7ff89ca2
VS		 239
240 vco = vco_table[tmp & 0x7];
241 if (vco == 0)
242 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
243 else
244 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
245
246 return vco;
247}
248
49cd97a3
VS		 249static void g33_get_cdclk(struct drm_i915_private *dev_priv,
250 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 251{
252 struct pci_dev *pdev = dev_priv->drm.pdev;
cbe974fb
JN		 253 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
254 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
255 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
256 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
257 const u8 *div_table;
49cd97a3 258 unsigned int cdclk_sel;
cbe974fb 259 u16 tmp = 0;
7ff89ca2 260
49cd97a3
VS		 261 cdclk_state->vco = intel_hpll_vco(dev_priv);
262
7ff89ca2
VS		 263 pci_read_config_word(pdev, GCFGC, &tmp);
264
265 cdclk_sel = (tmp >> 4) & 0x7;
266
267 if (cdclk_sel >= ARRAY_SIZE(div_3200))
268 goto fail;
269
49cd97a3 270 switch (cdclk_state->vco) {
7ff89ca2
VS		 271 case 3200000:
272 div_table = div_3200;
273 break;
274 case 4000000:
275 div_table = div_4000;
276 break;
277 case 4800000:
278 div_table = div_4800;
279 break;
280 case 5333333:
281 div_table = div_5333;
282 break;
283 default:
284 goto fail;
285 }
286
49cd97a3
VS		 287 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
288 div_table[cdclk_sel]);
289 return;
7ff89ca2
VS		 290
291fail:
292 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
49cd97a3
VS		 293 cdclk_state->vco, tmp);
294 cdclk_state->cdclk = 190476;
7ff89ca2
VS		 295}
296
49cd97a3
VS		 297static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
298 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 299{
300 struct pci_dev *pdev = dev_priv->drm.pdev;
301 u16 gcfgc = 0;
302
303 pci_read_config_word(pdev, GCFGC, &gcfgc);
304
305 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
306 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
49cd97a3
VS		 307 cdclk_state->cdclk = 266667;
308 break;
7ff89ca2 309 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
49cd97a3
VS		 310 cdclk_state->cdclk = 333333;
311 break;
7ff89ca2 312 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
49cd97a3
VS		 313 cdclk_state->cdclk = 444444;
314 break;
7ff89ca2 315 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
49cd97a3
VS		 316 cdclk_state->cdclk = 200000;
317 break;
7ff89ca2
VS		 318 default:
319 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
f0d759f0 320 /* fall through */
7ff89ca2 321 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
49cd97a3
VS		 322 cdclk_state->cdclk = 133333;
323 break;
7ff89ca2 324 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
49cd97a3
VS		 325 cdclk_state->cdclk = 166667;
326 break;
7ff89ca2
VS		 327 }
328}
329
49cd97a3
VS		 330static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
331 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 332{
333 struct pci_dev *pdev = dev_priv->drm.pdev;
cbe974fb
JN		 334 static const u8 div_3200[] = { 16, 10, 8 };
335 static const u8 div_4000[] = { 20, 12, 10 };
336 static const u8 div_5333[] = { 24, 16, 14 };
337 const u8 *div_table;
49cd97a3 338 unsigned int cdclk_sel;
cbe974fb 339 u16 tmp = 0;
7ff89ca2 340
49cd97a3
VS		 341 cdclk_state->vco = intel_hpll_vco(dev_priv);
342
7ff89ca2
VS		 343 pci_read_config_word(pdev, GCFGC, &tmp);
344
345 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
346
347 if (cdclk_sel >= ARRAY_SIZE(div_3200))
348 goto fail;
349
49cd97a3 350 switch (cdclk_state->vco) {
7ff89ca2
VS		 351 case 3200000:
352 div_table = div_3200;
353 break;
354 case 4000000:
355 div_table = div_4000;
356 break;
357 case 5333333:
358 div_table = div_5333;
359 break;
360 default:
361 goto fail;
362 }
363
49cd97a3
VS		 364 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
365 div_table[cdclk_sel]);
366 return;
7ff89ca2
VS		 367
368fail:
369 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
49cd97a3
VS		 370 cdclk_state->vco, tmp);
371 cdclk_state->cdclk = 200000;
7ff89ca2
VS		 372}
373
49cd97a3
VS		 374static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
375 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 376{
377 struct pci_dev *pdev = dev_priv->drm.pdev;
49cd97a3 378 unsigned int cdclk_sel;
cbe974fb 379 u16 tmp = 0;
7ff89ca2 380
49cd97a3
VS		 381 cdclk_state->vco = intel_hpll_vco(dev_priv);
382
7ff89ca2
VS		 383 pci_read_config_word(pdev, GCFGC, &tmp);
384
385 cdclk_sel = (tmp >> 12) & 0x1;
386
49cd97a3 387 switch (cdclk_state->vco) {
7ff89ca2
VS		 388 case 2666667:
389 case 4000000:
390 case 5333333:
49cd97a3
VS		 391 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
392 break;
7ff89ca2 393 case 3200000:
49cd97a3
VS		 394 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
395 break;
7ff89ca2
VS		 396 default:
397 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
49cd97a3
VS		 398 cdclk_state->vco, tmp);
399 cdclk_state->cdclk = 222222;
400 break;
7ff89ca2
VS		 401 }
402}
403
49cd97a3
VS		 404static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
405 struct intel_cdclk_state *cdclk_state)
7ff89ca2 406{
cbe974fb
JN		 407 u32 lcpll = I915_READ(LCPLL_CTL);
408 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
7ff89ca2
VS		 409
410 if (lcpll & LCPLL_CD_SOURCE_FCLK)
49cd97a3 411 cdclk_state->cdclk = 800000;
7ff89ca2 412 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
49cd97a3 413 cdclk_state->cdclk = 450000;
7ff89ca2 414 else if (freq == LCPLL_CLK_FREQ_450)
49cd97a3 415 cdclk_state->cdclk = 450000;
7ff89ca2 416 else if (IS_HSW_ULT(dev_priv))
49cd97a3 417 cdclk_state->cdclk = 337500;
7ff89ca2 418 else
49cd97a3 419 cdclk_state->cdclk = 540000;
7ff89ca2
VS		 420}
421
d305e061 422static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
7ff89ca2
VS		 423{
424 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
425 333333 : 320000;
7ff89ca2
VS		 426
427 /*
428 * We seem to get an unstable or solid color picture at 200MHz.
429 * Not sure what's wrong. For now use 200MHz only when all pipes
430 * are off.
431 */
d305e061 432 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
7ff89ca2 433 return 400000;
d305e061 434 else if (min_cdclk > 266667)
7ff89ca2 435 return freq_320;
d305e061 436 else if (min_cdclk > 0)
7ff89ca2
VS		 437 return 266667;
438 else
439 return 200000;
440}
441
999c5766
VS		 442static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
443{
444 if (IS_VALLEYVIEW(dev_priv)) {
445 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
446 return 2;
447 else if (cdclk >= 266667)
448 return 1;
449 else
450 return 0;
451 } else {
452 /*
453 * Specs are full of misinformation, but testing on actual
454 * hardware has shown that we just need to write the desired
455 * CCK divider into the Punit register.
456 */
457 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
458 }
459}
460
49cd97a3
VS		 461static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
462 struct intel_cdclk_state *cdclk_state)
7ff89ca2 463{
999c5766
VS		 464 u32 val;
465
49cd97a3
VS		 466 cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
467 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
468 CCK_DISPLAY_CLOCK_CONTROL,
469 cdclk_state->vco);
999c5766
VS		 470
471 mutex_lock(&dev_priv->pcu_lock);
c11b813f 472 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
999c5766
VS		 473 mutex_unlock(&dev_priv->pcu_lock);
474
475 if (IS_VALLEYVIEW(dev_priv))
476 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
477 DSPFREQGUAR_SHIFT;
478 else
479 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
480 DSPFREQGUAR_SHIFT_CHV;
7ff89ca2
VS		 481}
482
483static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
484{
485 unsigned int credits, default_credits;
486
487 if (IS_CHERRYVIEW(dev_priv))
488 default_credits = PFI_CREDIT(12);
489 else
490 default_credits = PFI_CREDIT(8);
491
49cd97a3 492 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
7ff89ca2
VS		 493 /* CHV suggested value is 31 or 63 */
494 if (IS_CHERRYVIEW(dev_priv))
495 credits = PFI_CREDIT_63;
496 else
497 credits = PFI_CREDIT(15);
498 } else {
499 credits = default_credits;
500 }
501
502 /*
503 * WA - write default credits before re-programming
504 * FIXME: should we also set the resend bit here?
505 */
506 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
507 default_credits);
508
509 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
510 credits | PFI_CREDIT_RESEND);
511
512 /*
513 * FIXME is this guaranteed to clear
514 * immediately or should we poll for it?
515 */
516 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
517}
518
83c5fda7
VS		 519static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
520 const struct intel_cdclk_state *cdclk_state)
7ff89ca2 521{
83c5fda7 522 int cdclk = cdclk_state->cdclk;
999c5766 523 u32 val, cmd = cdclk_state->voltage_level;
0e6e0be4 524 intel_wakeref_t wakeref;
7ff89ca2 525
0c9f353f
VS		 526 switch (cdclk) {
527 case 400000:
528 case 333333:
529 case 320000:
530 case 266667:
531 case 200000:
532 break;
533 default:
534 MISSING_CASE(cdclk);
535 return;
536 }
537
886015a0
GKB		 538 /* There are cases where we can end up here with power domains
539 * off and a CDCLK frequency other than the minimum, like when
540 * issuing a modeset without actually changing any display after
541 * a system suspend. So grab the PIPE-A domain, which covers
542 * the HW blocks needed for the following programming.
543 */
0e6e0be4 544 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
886015a0 545
9f817501 546 mutex_lock(&dev_priv->pcu_lock);
c11b813f 547 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
7ff89ca2
VS		 548 val &= ~DSPFREQGUAR_MASK;
549 val |= (cmd << DSPFREQGUAR_SHIFT);
c11b813f
VS		 550 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
551 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
7ff89ca2
VS		 552 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
553 50)) {
554 DRM_ERROR("timed out waiting for CDclk change\n");
555 }
9f817501 556 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 557
558 mutex_lock(&dev_priv->sb_lock);
559
560 if (cdclk == 400000) {
561 u32 divider;
562
563 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
564 cdclk) - 1;
565
566 /* adjust cdclk divider */
567 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
568 val &= ~CCK_FREQUENCY_VALUES;
569 val |= divider;
570 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
571
572 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
573 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
574 50))
575 DRM_ERROR("timed out waiting for CDclk change\n");
576 }
577
578 /* adjust self-refresh exit latency value */
579 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
580 val &= ~0x7f;
581
582 /*
583 * For high bandwidth configs, we set a higher latency in the bunit
584 * so that the core display fetch happens in time to avoid underruns.
585 */
586 if (cdclk == 400000)
587 val |= 4500 / 250; /* 4.5 usec */
588 else
589 val |= 3000 / 250; /* 3.0 usec */
590 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
591
592 mutex_unlock(&dev_priv->sb_lock);
593
594 intel_update_cdclk(dev_priv);
1a5301a5
VS		 595
596 vlv_program_pfi_credits(dev_priv);
886015a0 597
0e6e0be4 598 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
7ff89ca2
VS		 599}
600
83c5fda7
VS		 601static void chv_set_cdclk(struct drm_i915_private *dev_priv,
602 const struct intel_cdclk_state *cdclk_state)
7ff89ca2 603{
83c5fda7 604 int cdclk = cdclk_state->cdclk;
999c5766 605 u32 val, cmd = cdclk_state->voltage_level;
0e6e0be4 606 intel_wakeref_t wakeref;
7ff89ca2 607
7ff89ca2
VS		 608 switch (cdclk) {
609 case 333333:
610 case 320000:
611 case 266667:
612 case 200000:
613 break;
614 default:
615 MISSING_CASE(cdclk);
616 return;
617 }
618
886015a0
GKB		 619 /* There are cases where we can end up here with power domains
620 * off and a CDCLK frequency other than the minimum, like when
621 * issuing a modeset without actually changing any display after
622 * a system suspend. So grab the PIPE-A domain, which covers
623 * the HW blocks needed for the following programming.
624 */
0e6e0be4 625 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
886015a0 626
9f817501 627 mutex_lock(&dev_priv->pcu_lock);
c11b813f 628 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
7ff89ca2
VS		 629 val &= ~DSPFREQGUAR_MASK_CHV;
630 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
c11b813f
VS		 631 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
632 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
7ff89ca2
VS		 633 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
634 50)) {
635 DRM_ERROR("timed out waiting for CDclk change\n");
636 }
9f817501 637 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 638
639 intel_update_cdclk(dev_priv);
1a5301a5
VS		 640
641 vlv_program_pfi_credits(dev_priv);
886015a0 642
0e6e0be4 643 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
7ff89ca2
VS		 644}
645
d305e061 646static int bdw_calc_cdclk(int min_cdclk)
7ff89ca2 647{
d305e061 648 if (min_cdclk > 540000)
7ff89ca2 649 return 675000;
d305e061 650 else if (min_cdclk > 450000)
7ff89ca2 651 return 540000;
d305e061 652 else if (min_cdclk > 337500)
7ff89ca2
VS		 653 return 450000;
654 else
655 return 337500;
656}
657
d7ffaeef
VS		 658static u8 bdw_calc_voltage_level(int cdclk)
659{
660 switch (cdclk) {
661 default:
662 case 337500:
663 return 2;
664 case 450000:
665 return 0;
666 case 540000:
667 return 1;
668 case 675000:
669 return 3;
670 }
671}
672
49cd97a3
VS		 673static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
674 struct intel_cdclk_state *cdclk_state)
7ff89ca2 675{
cbe974fb
JN		 676 u32 lcpll = I915_READ(LCPLL_CTL);
677 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
7ff89ca2
VS		 678
679 if (lcpll & LCPLL_CD_SOURCE_FCLK)
49cd97a3 680 cdclk_state->cdclk = 800000;
7ff89ca2 681 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
49cd97a3 682 cdclk_state->cdclk = 450000;
7ff89ca2 683 else if (freq == LCPLL_CLK_FREQ_450)
49cd97a3 684 cdclk_state->cdclk = 450000;
7ff89ca2 685 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
49cd97a3 686 cdclk_state->cdclk = 540000;
7ff89ca2 687 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
49cd97a3 688 cdclk_state->cdclk = 337500;
7ff89ca2 689 else
49cd97a3 690 cdclk_state->cdclk = 675000;
d7ffaeef
VS		 691
692 /*
693 * Can't read this out :( Let's assume it's
694 * at least what the CDCLK frequency requires.
695 */
696 cdclk_state->voltage_level =
697 bdw_calc_voltage_level(cdclk_state->cdclk);
7ff89ca2
VS		 698}
699
83c5fda7
VS		 700static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
701 const struct intel_cdclk_state *cdclk_state)
7ff89ca2 702{
83c5fda7 703 int cdclk = cdclk_state->cdclk;
cbe974fb 704 u32 val;
7ff89ca2
VS		 705 int ret;
706
707 if (WARN((I915_READ(LCPLL_CTL) &
708 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
709 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
710 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
711 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
712 "trying to change cdclk frequency with cdclk not enabled\n"))
713 return;
714
9f817501 715 mutex_lock(&dev_priv->pcu_lock);
7ff89ca2
VS		 716 ret = sandybridge_pcode_write(dev_priv,
717 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9f817501 718 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 719 if (ret) {
720 DRM_ERROR("failed to inform pcode about cdclk change\n");
721 return;
722 }
723
724 val = I915_READ(LCPLL_CTL);
725 val |= LCPLL_CD_SOURCE_FCLK;
726 I915_WRITE(LCPLL_CTL, val);
727
3164888a
ML		 728 /*
729 * According to the spec, it should be enough to poll for this 1 us.
730 * However, extensive testing shows that this can take longer.
731 */
7ff89ca2 732 if (wait_for_us(I915_READ(LCPLL_CTL) &
3164888a 733 LCPLL_CD_SOURCE_FCLK_DONE, 100))
7ff89ca2
VS		 734 DRM_ERROR("Switching to FCLK failed\n");
735
736 val = I915_READ(LCPLL_CTL);
737 val &= ~LCPLL_CLK_FREQ_MASK;
738
739 switch (cdclk) {
2b58417f
VS		 740 default:
741 MISSING_CASE(cdclk);
742 /* fall through */
743 case 337500:
744 val |= LCPLL_CLK_FREQ_337_5_BDW;
2b58417f 745 break;
7ff89ca2
VS		 746 case 450000:
747 val |= LCPLL_CLK_FREQ_450;
7ff89ca2
VS		 748 break;
749 case 540000:
750 val |= LCPLL_CLK_FREQ_54O_BDW;
7ff89ca2 751 break;
7ff89ca2
VS		 752 case 675000:
753 val |= LCPLL_CLK_FREQ_675_BDW;
7ff89ca2 754 break;
7ff89ca2
VS		 755 }
756
757 I915_WRITE(LCPLL_CTL, val);
758
759 val = I915_READ(LCPLL_CTL);
760 val &= ~LCPLL_CD_SOURCE_FCLK;
761 I915_WRITE(LCPLL_CTL, val);
762
763 if (wait_for_us((I915_READ(LCPLL_CTL) &
764 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
765 DRM_ERROR("Switching back to LCPLL failed\n");
766
9f817501 767 mutex_lock(&dev_priv->pcu_lock);
d7ffaeef
VS		 768 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
769 cdclk_state->voltage_level);
9f817501 770 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 771
772 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
773
774 intel_update_cdclk(dev_priv);
7ff89ca2
VS		 775}
776
d305e061 777static int skl_calc_cdclk(int min_cdclk, int vco)
7ff89ca2
VS		 778{
779 if (vco == 8640000) {
d305e061 780 if (min_cdclk > 540000)
7ff89ca2 781 return 617143;
d305e061 782 else if (min_cdclk > 432000)
7ff89ca2 783 return 540000;
d305e061 784 else if (min_cdclk > 308571)
7ff89ca2
VS		 785 return 432000;
786 else
787 return 308571;
788 } else {
d305e061 789 if (min_cdclk > 540000)
7ff89ca2 790 return 675000;
d305e061 791 else if (min_cdclk > 450000)
7ff89ca2 792 return 540000;
d305e061 793 else if (min_cdclk > 337500)
7ff89ca2
VS		 794 return 450000;
795 else
796 return 337500;
797 }
798}
799
2aa97491
VS		 800static u8 skl_calc_voltage_level(int cdclk)
801{
802 switch (cdclk) {
803 default:
804 case 308571:
805 case 337500:
806 return 0;
807 case 450000:
808 case 432000:
809 return 1;
810 case 540000:
811 return 2;
812 case 617143:
813 case 675000:
814 return 3;
815 }
816}
817
49cd97a3
VS		 818static void skl_dpll0_update(struct drm_i915_private *dev_priv,
819 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 820{
821 u32 val;
822
49cd97a3
VS		 823 cdclk_state->ref = 24000;
824 cdclk_state->vco = 0;
7ff89ca2
VS		 825
826 val = I915_READ(LCPLL1_CTL);
827 if ((val & LCPLL_PLL_ENABLE) == 0)
828 return;
829
830 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
831 return;
832
833 val = I915_READ(DPLL_CTRL1);
834
835 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
836 DPLL_CTRL1_SSC(SKL_DPLL0) |
837 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
838 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
839 return;
840
841 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
842 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
843 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
844 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
845 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
49cd97a3 846 cdclk_state->vco = 8100000;
7ff89ca2
VS		 847 break;
848 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
849 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
49cd97a3 850 cdclk_state->vco = 8640000;
7ff89ca2
VS		 851 break;
852 default:
853 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
854 break;
855 }
856}
857
49cd97a3
VS		 858static void skl_get_cdclk(struct drm_i915_private *dev_priv,
859 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 860{
861 u32 cdctl;
862
49cd97a3 863 skl_dpll0_update(dev_priv, cdclk_state);
7ff89ca2 864
b6c51c3e 865 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
49cd97a3
VS		 866
867 if (cdclk_state->vco == 0)
2aa97491 868 goto out;
7ff89ca2
VS		 869
870 cdctl = I915_READ(CDCLK_CTL);
871
49cd97a3 872 if (cdclk_state->vco == 8640000) {
7ff89ca2
VS		 873 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
874 case CDCLK_FREQ_450_432:
49cd97a3
VS		 875 cdclk_state->cdclk = 432000;
876 break;
7ff89ca2 877 case CDCLK_FREQ_337_308:
49cd97a3
VS		 878 cdclk_state->cdclk = 308571;
879 break;
7ff89ca2 880 case CDCLK_FREQ_540:
49cd97a3
VS		 881 cdclk_state->cdclk = 540000;
882 break;
7ff89ca2 883 case CDCLK_FREQ_675_617:
49cd97a3
VS		 884 cdclk_state->cdclk = 617143;
885 break;
7ff89ca2
VS		 886 default:
887 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
49cd97a3 888 break;
7ff89ca2
VS		 889 }
890 } else {
891 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
892 case CDCLK_FREQ_450_432:
49cd97a3
VS		 893 cdclk_state->cdclk = 450000;
894 break;
7ff89ca2 895 case CDCLK_FREQ_337_308:
49cd97a3
VS		 896 cdclk_state->cdclk = 337500;
897 break;
7ff89ca2 898 case CDCLK_FREQ_540:
49cd97a3
VS		 899 cdclk_state->cdclk = 540000;
900 break;
7ff89ca2 901 case CDCLK_FREQ_675_617:
49cd97a3
VS		 902 cdclk_state->cdclk = 675000;
903 break;
7ff89ca2
VS		 904 default:
905 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
49cd97a3 906 break;
7ff89ca2
VS		 907 }
908 }
2aa97491
VS		 909
910 out:
911 /*
912 * Can't read this out :( Let's assume it's
913 * at least what the CDCLK frequency requires.
914 */
915 cdclk_state->voltage_level =
916 skl_calc_voltage_level(cdclk_state->cdclk);
7ff89ca2
VS		 917}
918
919/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
920static int skl_cdclk_decimal(int cdclk)
921{
922 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
923}
924
925static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
926 int vco)
927{
928 bool changed = dev_priv->skl_preferred_vco_freq != vco;
929
930 dev_priv->skl_preferred_vco_freq = vco;
931
932 if (changed)
933 intel_update_max_cdclk(dev_priv);
934}
935
936static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
937{
7ff89ca2
VS		 938 u32 val;
939
940 WARN_ON(vco != 8100000 && vco != 8640000);
941
7ff89ca2
VS		 942 /*
943 * We always enable DPLL0 with the lowest link rate possible, but still
944 * taking into account the VCO required to operate the eDP panel at the
945 * desired frequency. The usual DP link rates operate with a VCO of
946 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
947 * The modeset code is responsible for the selection of the exact link
948 * rate later on, with the constraint of choosing a frequency that
949 * works with vco.
950 */
951 val = I915_READ(DPLL_CTRL1);
952
953 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
954 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
955 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
956 if (vco == 8640000)
957 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
958 SKL_DPLL0);
959 else
960 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
961 SKL_DPLL0);
962
963 I915_WRITE(DPLL_CTRL1, val);
964 POSTING_READ(DPLL_CTRL1);
965
966 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
967
97a04e0d 968 if (intel_wait_for_register(&dev_priv->uncore,
7ff89ca2
VS		 969 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
970 5))
971 DRM_ERROR("DPLL0 not locked\n");
972
49cd97a3 973 dev_priv->cdclk.hw.vco = vco;
7ff89ca2
VS		 974
975 /* We'll want to keep using the current vco from now on. */
976 skl_set_preferred_cdclk_vco(dev_priv, vco);
977}
978
979static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
980{
981 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
97a04e0d
DCS		 982 if (intel_wait_for_register(&dev_priv->uncore,
983 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
984 1))
7ff89ca2
VS		 985 DRM_ERROR("Couldn't disable DPLL0\n");
986
49cd97a3 987 dev_priv->cdclk.hw.vco = 0;
7ff89ca2
VS		 988}
989
990static void skl_set_cdclk(struct drm_i915_private *dev_priv,
83c5fda7 991 const struct intel_cdclk_state *cdclk_state)
7ff89ca2 992{
83c5fda7
VS		 993 int cdclk = cdclk_state->cdclk;
994 int vco = cdclk_state->vco;
53421c2f 995 u32 freq_select, cdclk_ctl;
7ff89ca2
VS		 996 int ret;
997
602a9de5
ID		 998 /*
999 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1000 * unsupported on SKL. In theory this should never happen since only
1001 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1002 * supported on SKL either, see the above WA. WARN whenever trying to
1003 * use the corresponding VCO freq as that always leads to using the
1004 * minimum 308MHz CDCLK.
1005 */
1006 WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000);
1007
9f817501 1008 mutex_lock(&dev_priv->pcu_lock);
7ff89ca2
VS		 1009 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1010 SKL_CDCLK_PREPARE_FOR_CHANGE,
1011 SKL_CDCLK_READY_FOR_CHANGE,
1012 SKL_CDCLK_READY_FOR_CHANGE, 3);
9f817501 1013 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 1014 if (ret) {
1015 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1016 ret);
1017 return;
1018 }
1019
53421c2f 1020 /* Choose frequency for this cdclk */
7ff89ca2 1021 switch (cdclk) {
2b58417f 1022 default:
b6c51c3e 1023 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
2b58417f
VS		 1024 WARN_ON(vco != 0);
1025 /* fall through */
1026 case 308571:
1027 case 337500:
1028 freq_select = CDCLK_FREQ_337_308;
2b58417f 1029 break;
7ff89ca2
VS		 1030 case 450000:
1031 case 432000:
1032 freq_select = CDCLK_FREQ_450_432;
7ff89ca2
VS		 1033 break;
1034 case 540000:
1035 freq_select = CDCLK_FREQ_540;
7ff89ca2 1036 break;
7ff89ca2
VS		 1037 case 617143:
1038 case 675000:
1039 freq_select = CDCLK_FREQ_675_617;
7ff89ca2
VS		 1040 break;
1041 }
1042
49cd97a3
VS		 1043 if (dev_priv->cdclk.hw.vco != 0 &&
1044 dev_priv->cdclk.hw.vco != vco)
7ff89ca2
VS		 1045 skl_dpll0_disable(dev_priv);
1046
53421c2f
LDM		 1047 cdclk_ctl = I915_READ(CDCLK_CTL);
1048
1049 if (dev_priv->cdclk.hw.vco != vco) {
1050 /* Wa Display #1183: skl,kbl,cfl */
1051 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1052 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1053 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1054 }
1055
1056 /* Wa Display #1183: skl,kbl,cfl */
1057 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1058 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1059 POSTING_READ(CDCLK_CTL);
1060
49cd97a3 1061 if (dev_priv->cdclk.hw.vco != vco)
7ff89ca2
VS		 1062 skl_dpll0_enable(dev_priv, vco);
1063
53421c2f
LDM		 1064 /* Wa Display #1183: skl,kbl,cfl */
1065 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1066 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1067
1068 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1069 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1070
1071 /* Wa Display #1183: skl,kbl,cfl */
1072 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1073 I915_WRITE(CDCLK_CTL, cdclk_ctl);
7ff89ca2
VS		 1074 POSTING_READ(CDCLK_CTL);
1075
1076 /* inform PCU of the change */
9f817501 1077 mutex_lock(&dev_priv->pcu_lock);
2aa97491
VS		 1078 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1079 cdclk_state->voltage_level);
9f817501 1080 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 1081
1082 intel_update_cdclk(dev_priv);
1083}
1084
1085static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1086{
cbe974fb 1087 u32 cdctl, expected;
7ff89ca2
VS		 1088
1089 /*
1090 * check if the pre-os initialized the display
1091 * There is SWF18 scratchpad register defined which is set by the
1092 * pre-os which can be used by the OS drivers to check the status
1093 */
1094 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1095 goto sanitize;
1096
1097 intel_update_cdclk(dev_priv);
cfddadc9
VS		 1098 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1099
7ff89ca2 1100 /* Is PLL enabled and locked ? */
49cd97a3 1101 if (dev_priv->cdclk.hw.vco == 0 ||
b6c51c3e 1102 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
7ff89ca2
VS		 1103 goto sanitize;
1104
1105 /* DPLL okay; verify the cdclock
1106 *
1107 * Noticed in some instances that the freq selection is correct but
1108 * decimal part is programmed wrong from BIOS where pre-os does not
1109 * enable display. Verify the same as well.
1110 */
1111 cdctl = I915_READ(CDCLK_CTL);
1112 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
49cd97a3 1113 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
7ff89ca2
VS		 1114 if (cdctl == expected)
1115 /* All well; nothing to sanitize */
1116 return;
1117
1118sanitize:
1119 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1120
1121 /* force cdclk programming */
49cd97a3 1122 dev_priv->cdclk.hw.cdclk = 0;
7ff89ca2 1123 /* force full PLL disable + enable */
49cd97a3 1124 dev_priv->cdclk.hw.vco = -1;
7ff89ca2
VS		 1125}
1126
1127/**
1128 * skl_init_cdclk - Initialize CDCLK on SKL
1129 * @dev_priv: i915 device
1130 *
1131 * Initialize CDCLK for SKL and derivatives. This is generally
1132 * done only during the display core initialization sequence,
1133 * after which the DMC will take care of turning CDCLK off/on
1134 * as needed.
1135 */
1136void skl_init_cdclk(struct drm_i915_private *dev_priv)
1137{
83c5fda7 1138 struct intel_cdclk_state cdclk_state;
7ff89ca2
VS		 1139
1140 skl_sanitize_cdclk(dev_priv);
1141
49cd97a3
VS		 1142 if (dev_priv->cdclk.hw.cdclk != 0 &&
1143 dev_priv->cdclk.hw.vco != 0) {
7ff89ca2
VS		 1144 /*
1145 * Use the current vco as our initial
1146 * guess as to what the preferred vco is.
1147 */
1148 if (dev_priv->skl_preferred_vco_freq == 0)
1149 skl_set_preferred_cdclk_vco(dev_priv,
49cd97a3 1150 dev_priv->cdclk.hw.vco);
7ff89ca2
VS		 1151 return;
1152 }
1153
83c5fda7
VS		 1154 cdclk_state = dev_priv->cdclk.hw;
1155
1156 cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1157 if (cdclk_state.vco == 0)
1158 cdclk_state.vco = 8100000;
1159 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
2aa97491 1160 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
7ff89ca2 1161
83c5fda7 1162 skl_set_cdclk(dev_priv, &cdclk_state);
7ff89ca2
VS		 1163}
1164
1165/**
1166 * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1167 * @dev_priv: i915 device
1168 *
1169 * Uninitialize CDCLK for SKL and derivatives. This is done only
1170 * during the display core uninitialization sequence.
1171 */
1172void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1173{
83c5fda7
VS		 1174 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1175
b6c51c3e 1176 cdclk_state.cdclk = cdclk_state.bypass;
83c5fda7 1177 cdclk_state.vco = 0;
2aa97491 1178 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
83c5fda7
VS		 1179
1180 skl_set_cdclk(dev_priv, &cdclk_state);
7ff89ca2
VS		 1181}
1182
d305e061 1183static int bxt_calc_cdclk(int min_cdclk)
7ff89ca2 1184{
d305e061 1185 if (min_cdclk > 576000)
7ff89ca2 1186 return 624000;
d305e061 1187 else if (min_cdclk > 384000)
7ff89ca2 1188 return 576000;
d305e061 1189 else if (min_cdclk > 288000)
7ff89ca2 1190 return 384000;
d305e061 1191 else if (min_cdclk > 144000)
7ff89ca2
VS		 1192 return 288000;
1193 else
1194 return 144000;
1195}
1196
d305e061 1197static int glk_calc_cdclk(int min_cdclk)
7ff89ca2 1198{
d305e061 1199 if (min_cdclk > 158400)
7ff89ca2 1200 return 316800;
d305e061 1201 else if (min_cdclk > 79200)
7ff89ca2
VS		 1202 return 158400;
1203 else
1204 return 79200;
1205}
1206
2123f442
VS		 1207static u8 bxt_calc_voltage_level(int cdclk)
1208{
1209 return DIV_ROUND_UP(cdclk, 25000);
1210}
1211
7ff89ca2
VS		 1212static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1213{
1214 int ratio;
1215
b6c51c3e 1216 if (cdclk == dev_priv->cdclk.hw.bypass)
7ff89ca2
VS		 1217 return 0;
1218
1219 switch (cdclk) {
1220 default:
1221 MISSING_CASE(cdclk);
2b58417f 1222 /* fall through */
7ff89ca2
VS		 1223 case 144000:
1224 case 288000:
1225 case 384000:
1226 case 576000:
1227 ratio = 60;
1228 break;
1229 case 624000:
1230 ratio = 65;
1231 break;
1232 }
1233
49cd97a3 1234 return dev_priv->cdclk.hw.ref * ratio;
7ff89ca2
VS		 1235}
1236
1237static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1238{
1239 int ratio;
1240
b6c51c3e 1241 if (cdclk == dev_priv->cdclk.hw.bypass)
7ff89ca2
VS		 1242 return 0;
1243
1244 switch (cdclk) {
1245 default:
1246 MISSING_CASE(cdclk);
2b58417f 1247 /* fall through */
7ff89ca2
VS		 1248 case 79200:
1249 case 158400:
1250 case 316800:
1251 ratio = 33;
1252 break;
1253 }
1254
49cd97a3 1255 return dev_priv->cdclk.hw.ref * ratio;
7ff89ca2
VS		 1256}
1257
49cd97a3
VS		 1258static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1259 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 1260{
1261 u32 val;
1262
49cd97a3
VS		 1263 cdclk_state->ref = 19200;
1264 cdclk_state->vco = 0;
7ff89ca2
VS		 1265
1266 val = I915_READ(BXT_DE_PLL_ENABLE);
1267 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1268 return;
1269
1270 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1271 return;
1272
1273 val = I915_READ(BXT_DE_PLL_CTL);
49cd97a3 1274 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
7ff89ca2
VS		 1275}
1276
49cd97a3
VS		 1277static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1278 struct intel_cdclk_state *cdclk_state)
7ff89ca2
VS		 1279{
1280 u32 divider;
49cd97a3 1281 int div;
7ff89ca2 1282
49cd97a3 1283 bxt_de_pll_update(dev_priv, cdclk_state);
7ff89ca2 1284
b6c51c3e 1285 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
49cd97a3
VS		 1286
1287 if (cdclk_state->vco == 0)
2123f442 1288 goto out;
7ff89ca2
VS		 1289
1290 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1291
1292 switch (divider) {
1293 case BXT_CDCLK_CD2X_DIV_SEL_1:
1294 div = 2;
1295 break;
1296 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1297 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1298 div = 3;
1299 break;
1300 case BXT_CDCLK_CD2X_DIV_SEL_2:
1301 div = 4;
1302 break;
1303 case BXT_CDCLK_CD2X_DIV_SEL_4:
1304 div = 8;
1305 break;
1306 default:
1307 MISSING_CASE(divider);
49cd97a3 1308 return;
7ff89ca2
VS		 1309 }
1310
49cd97a3 1311 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
2123f442
VS		 1312
1313 out:
1314 /*
1315 * Can't read this out :( Let's assume it's
1316 * at least what the CDCLK frequency requires.
1317 */
1318 cdclk_state->voltage_level =
1319 bxt_calc_voltage_level(cdclk_state->cdclk);
7ff89ca2
VS		 1320}
1321
1322static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1323{
1324 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1325
1326 /* Timeout 200us */
97a04e0d 1327 if (intel_wait_for_register(&dev_priv->uncore,
7ff89ca2
VS		 1328 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1329 1))
1330 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1331
49cd97a3 1332 dev_priv->cdclk.hw.vco = 0;
7ff89ca2
VS		 1333}
1334
1335static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1336{
49cd97a3 1337 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
7ff89ca2
VS		 1338 u32 val;
1339
1340 val = I915_READ(BXT_DE_PLL_CTL);
1341 val &= ~BXT_DE_PLL_RATIO_MASK;
1342 val |= BXT_DE_PLL_RATIO(ratio);
1343 I915_WRITE(BXT_DE_PLL_CTL, val);
1344
1345 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1346
1347 /* Timeout 200us */
97a04e0d 1348 if (intel_wait_for_register(&dev_priv->uncore,
7ff89ca2
VS		 1349 BXT_DE_PLL_ENABLE,
1350 BXT_DE_PLL_LOCK,
1351 BXT_DE_PLL_LOCK,
1352 1))
1353 DRM_ERROR("timeout waiting for DE PLL lock\n");
1354
49cd97a3 1355 dev_priv->cdclk.hw.vco = vco;
7ff89ca2
VS		 1356}
1357
8f0cfa4d 1358static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
83c5fda7 1359 const struct intel_cdclk_state *cdclk_state)
7ff89ca2 1360{
83c5fda7
VS		 1361 int cdclk = cdclk_state->cdclk;
1362 int vco = cdclk_state->vco;
7ff89ca2 1363 u32 val, divider;
8f0cfa4d 1364 int ret;
7ff89ca2 1365
7ff89ca2
VS		 1366 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1367 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
2b58417f 1368 default:
b6c51c3e 1369 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
2b58417f
VS		 1370 WARN_ON(vco != 0);
1371 /* fall through */
1372 case 2:
1373 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
7ff89ca2
VS		 1374 break;
1375 case 3:
1376 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1377 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1378 break;
2b58417f
VS		 1379 case 4:
1380 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
7ff89ca2 1381 break;
2b58417f
VS		 1382 case 8:
1383 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
7ff89ca2
VS		 1384 break;
1385 }
1386
e76019a8
ID		 1387 /*
1388 * Inform power controller of upcoming frequency change. BSpec
1389 * requires us to wait up to 150usec, but that leads to timeouts;
1390 * the 2ms used here is based on experiment.
1391 */
9f817501 1392 mutex_lock(&dev_priv->pcu_lock);
e76019a8
ID		 1393 ret = sandybridge_pcode_write_timeout(dev_priv,
1394 HSW_PCODE_DE_WRITE_FREQ_REQ,
006bb4cc 1395 0x80000000, 150, 2);
9f817501 1396 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 1397
1398 if (ret) {
1399 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1400 ret, cdclk);
1401 return;
1402 }
1403
49cd97a3
VS		 1404 if (dev_priv->cdclk.hw.vco != 0 &&
1405 dev_priv->cdclk.hw.vco != vco)
7ff89ca2
VS		 1406 bxt_de_pll_disable(dev_priv);
1407
49cd97a3 1408 if (dev_priv->cdclk.hw.vco != vco)
7ff89ca2
VS		 1409 bxt_de_pll_enable(dev_priv, vco);
1410
1411 val = divider | skl_cdclk_decimal(cdclk);
1412 /*
1413 * FIXME if only the cd2x divider needs changing, it could be done
1414 * without shutting off the pipe (if only one pipe is active).
1415 */
1416 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1417 /*
1418 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1419 * enable otherwise.
1420 */
1421 if (cdclk >= 500000)
1422 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1423 I915_WRITE(CDCLK_CTL, val);
1424
9f817501 1425 mutex_lock(&dev_priv->pcu_lock);
e76019a8
ID		 1426 /*
1427 * The timeout isn't specified, the 2ms used here is based on
1428 * experiment.
1429 * FIXME: Waiting for the request completion could be delayed until
1430 * the next PCODE request based on BSpec.
1431 */
1432 ret = sandybridge_pcode_write_timeout(dev_priv,
1433 HSW_PCODE_DE_WRITE_FREQ_REQ,
006bb4cc 1434 cdclk_state->voltage_level, 150, 2);
9f817501 1435 mutex_unlock(&dev_priv->pcu_lock);
7ff89ca2
VS		 1436
1437 if (ret) {
1438 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1439 ret, cdclk);
1440 return;
1441 }
1442
1443 intel_update_cdclk(dev_priv);
1444}
1445
1446static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1447{
1448 u32 cdctl, expected;
1449
1450 intel_update_cdclk(dev_priv);
cfddadc9 1451 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
7ff89ca2 1452
49cd97a3 1453 if (dev_priv->cdclk.hw.vco == 0 ||
b6c51c3e 1454 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
7ff89ca2
VS		 1455 goto sanitize;
1456
1457 /* DPLL okay; verify the cdclock
1458 *
1459 * Some BIOS versions leave an incorrect decimal frequency value and
1460 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1461 * so sanitize this register.
1462 */
1463 cdctl = I915_READ(CDCLK_CTL);
1464 /*
1465 * Let's ignore the pipe field, since BIOS could have configured the
1466 * dividers both synching to an active pipe, or asynchronously
1467 * (PIPE_NONE).
1468 */
1469 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1470
1471 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
49cd97a3 1472 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
7ff89ca2
VS		 1473 /*
1474 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1475 * enable otherwise.
1476 */
49cd97a3 1477 if (dev_priv->cdclk.hw.cdclk >= 500000)
7ff89ca2
VS		 1478 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1479
1480 if (cdctl == expected)
1481 /* All well; nothing to sanitize */
1482 return;
1483
1484sanitize:
1485 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1486
1487 /* force cdclk programming */
49cd97a3 1488 dev_priv->cdclk.hw.cdclk = 0;
7ff89ca2
VS		 1489
1490 /* force full PLL disable + enable */
49cd97a3 1491 dev_priv->cdclk.hw.vco = -1;
7ff89ca2
VS		 1492}
1493
1494/**
1495 * bxt_init_cdclk - Initialize CDCLK on BXT
1496 * @dev_priv: i915 device
1497 *
1498 * Initialize CDCLK for BXT and derivatives. This is generally
1499 * done only during the display core initialization sequence,
1500 * after which the DMC will take care of turning CDCLK off/on
1501 * as needed.
1502 */
1503void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1504{
83c5fda7 1505 struct intel_cdclk_state cdclk_state;
7ff89ca2
VS		 1506
1507 bxt_sanitize_cdclk(dev_priv);
1508
49cd97a3
VS		 1509 if (dev_priv->cdclk.hw.cdclk != 0 &&
1510 dev_priv->cdclk.hw.vco != 0)
7ff89ca2
VS		 1511 return;
1512
83c5fda7
VS		 1513 cdclk_state = dev_priv->cdclk.hw;
1514
7ff89ca2
VS		 1515 /*
1516 * FIXME:
1517 * - The initial CDCLK needs to be read from VBT.
1518 * Need to make this change after VBT has changes for BXT.
1519 */
8f0cfa4d 1520 if (IS_GEMINILAKE(dev_priv)) {
83c5fda7
VS		 1521 cdclk_state.cdclk = glk_calc_cdclk(0);
1522 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
8f0cfa4d 1523 } else {
83c5fda7
VS		 1524 cdclk_state.cdclk = bxt_calc_cdclk(0);
1525 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
8f0cfa4d 1526 }
2123f442 1527 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
7ff89ca2 1528
83c5fda7 1529 bxt_set_cdclk(dev_priv, &cdclk_state);
7ff89ca2
VS		 1530}
1531
1532/**
1533 * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1534 * @dev_priv: i915 device
1535 *
1536 * Uninitialize CDCLK for BXT and derivatives. This is done only
1537 * during the display core uninitialization sequence.
1538 */
1539void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1540{
83c5fda7
VS		 1541 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1542
b6c51c3e 1543 cdclk_state.cdclk = cdclk_state.bypass;
83c5fda7 1544 cdclk_state.vco = 0;
2123f442 1545 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
83c5fda7
VS		 1546
1547 bxt_set_cdclk(dev_priv, &cdclk_state);
49cd97a3
VS		 1548}
1549
d305e061 1550static int cnl_calc_cdclk(int min_cdclk)
d1999e9e 1551{
d305e061 1552 if (min_cdclk > 336000)
d1999e9e 1553 return 528000;
d305e061 1554 else if (min_cdclk > 168000)
d1999e9e
RV		 1555 return 336000;
1556 else
1557 return 168000;
1558}
1559
48469ece
VS		 1560static u8 cnl_calc_voltage_level(int cdclk)
1561{
1562 switch (cdclk) {
1563 default:
1564 case 168000:
1565 return 0;
1566 case 336000:
1567 return 1;
1568 case 528000:
1569 return 2;
1570 }
1571}
1572
945f2672
VS		 1573static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1574 struct intel_cdclk_state *cdclk_state)
1575{
1576 u32 val;
1577
1578 if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1579 cdclk_state->ref = 24000;
1580 else
1581 cdclk_state->ref = 19200;
1582
1583 cdclk_state->vco = 0;
1584
1585 val = I915_READ(BXT_DE_PLL_ENABLE);
1586 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1587 return;
1588
1589 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1590 return;
1591
1592 cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1593}
1594
1595static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1596 struct intel_cdclk_state *cdclk_state)
1597{
1598 u32 divider;
1599 int div;
1600
1601 cnl_cdclk_pll_update(dev_priv, cdclk_state);
1602
b6c51c3e 1603 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
945f2672
VS		 1604
1605 if (cdclk_state->vco == 0)
48469ece 1606 goto out;
945f2672
VS		 1607
1608 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1609
1610 switch (divider) {
1611 case BXT_CDCLK_CD2X_DIV_SEL_1:
1612 div = 2;
1613 break;
1614 case BXT_CDCLK_CD2X_DIV_SEL_2:
1615 div = 4;
1616 break;
1617 default:
1618 MISSING_CASE(divider);
1619 return;
1620 }
1621
1622 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
48469ece
VS		 1623
1624 out:
1625 /*
1626 * Can't read this out :( Let's assume it's
1627 * at least what the CDCLK frequency requires.
1628 */
1629 cdclk_state->voltage_level =
1630 cnl_calc_voltage_level(cdclk_state->cdclk);
945f2672
VS		 1631}
1632
ef4f7a68
VS		 1633static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1634{
1635 u32 val;
1636
1637 val = I915_READ(BXT_DE_PLL_ENABLE);
1638 val &= ~BXT_DE_PLL_PLL_ENABLE;
1639 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1640
1641 /* Timeout 200us */
1642 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
bc8282a7 1643 DRM_ERROR("timeout waiting for CDCLK PLL unlock\n");
ef4f7a68
VS		 1644
1645 dev_priv->cdclk.hw.vco = 0;
1646}
1647
1648static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1649{
1650 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1651 u32 val;
1652
1653 val = CNL_CDCLK_PLL_RATIO(ratio);
1654 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1655
1656 val |= BXT_DE_PLL_PLL_ENABLE;
1657 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1658
1659 /* Timeout 200us */
1660 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
bc8282a7 1661 DRM_ERROR("timeout waiting for CDCLK PLL lock\n");
ef4f7a68
VS		 1662
1663 dev_priv->cdclk.hw.vco = vco;
1664}
1665
ef4f7a68
VS		 1666static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1667 const struct intel_cdclk_state *cdclk_state)
1668{
1669 int cdclk = cdclk_state->cdclk;
1670 int vco = cdclk_state->vco;
48469ece 1671 u32 val, divider;
ef4f7a68
VS		 1672 int ret;
1673
9f817501 1674 mutex_lock(&dev_priv->pcu_lock);
ef4f7a68
VS		 1675 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1676 SKL_CDCLK_PREPARE_FOR_CHANGE,
1677 SKL_CDCLK_READY_FOR_CHANGE,
1678 SKL_CDCLK_READY_FOR_CHANGE, 3);
9f817501 1679 mutex_unlock(&dev_priv->pcu_lock);
ef4f7a68
VS		 1680 if (ret) {
1681 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1682 ret);
1683 return;
1684 }
1685
1686 /* cdclk = vco / 2 / div{1,2} */
1687 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
ef4f7a68 1688 default:
b6c51c3e 1689 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
ef4f7a68 1690 WARN_ON(vco != 0);
2b58417f
VS		 1691 /* fall through */
1692 case 2:
ef4f7a68
VS		 1693 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1694 break;
2b58417f
VS		 1695 case 4:
1696 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1697 break;
ef4f7a68
VS		 1698 }
1699
ef4f7a68
VS		 1700 if (dev_priv->cdclk.hw.vco != 0 &&
1701 dev_priv->cdclk.hw.vco != vco)
1702 cnl_cdclk_pll_disable(dev_priv);
1703
1704 if (dev_priv->cdclk.hw.vco != vco)
1705 cnl_cdclk_pll_enable(dev_priv, vco);
1706
1707 val = divider | skl_cdclk_decimal(cdclk);
1708 /*
1709 * FIXME if only the cd2x divider needs changing, it could be done
1710 * without shutting off the pipe (if only one pipe is active).
1711 */
1712 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1713 I915_WRITE(CDCLK_CTL, val);
1714
1715 /* inform PCU of the change */
9f817501 1716 mutex_lock(&dev_priv->pcu_lock);
48469ece
VS		 1717 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1718 cdclk_state->voltage_level);
9f817501 1719 mutex_unlock(&dev_priv->pcu_lock);
ef4f7a68
VS		 1720
1721 intel_update_cdclk(dev_priv);
53e9bf5e
VS		 1722
1723 /*
1724 * Can't read out the voltage level :(
1725 * Let's just assume everything is as expected.
1726 */
1727 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
ef4f7a68
VS		 1728}
1729
d8d4a512
VS		 1730static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1731{
1732 int ratio;
1733
b6c51c3e 1734 if (cdclk == dev_priv->cdclk.hw.bypass)
d8d4a512
VS		 1735 return 0;
1736
1737 switch (cdclk) {
1738 default:
1739 MISSING_CASE(cdclk);
2b58417f 1740 /* fall through */
d8d4a512
VS		 1741 case 168000:
1742 case 336000:
1743 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1744 break;
1745 case 528000:
1746 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1747 break;
1748 }
1749
1750 return dev_priv->cdclk.hw.ref * ratio;
1751}
1752
1753static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1754{
1755 u32 cdctl, expected;
1756
1757 intel_update_cdclk(dev_priv);
cfddadc9 1758 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
d8d4a512
VS		 1759
1760 if (dev_priv->cdclk.hw.vco == 0 ||
b6c51c3e 1761 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
d8d4a512
VS		 1762 goto sanitize;
1763
1764 /* DPLL okay; verify the cdclock
1765 *
1766 * Some BIOS versions leave an incorrect decimal frequency value and
1767 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1768 * so sanitize this register.
1769 */
1770 cdctl = I915_READ(CDCLK_CTL);
1771 /*
1772 * Let's ignore the pipe field, since BIOS could have configured the
1773 * dividers both synching to an active pipe, or asynchronously
1774 * (PIPE_NONE).
1775 */
1776 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1777
1778 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1779 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1780
1781 if (cdctl == expected)
1782 /* All well; nothing to sanitize */
1783 return;
1784
1785sanitize:
1786 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1787
1788 /* force cdclk programming */
1789 dev_priv->cdclk.hw.cdclk = 0;
1790
1791 /* force full PLL disable + enable */
1792 dev_priv->cdclk.hw.vco = -1;
1793}
1794
186a277e
PZ		 1795static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
1796{
1797 int ranges_24[] = { 312000, 552000, 648000 };
1798 int ranges_19_38[] = { 307200, 556800, 652800 };
1799 int *ranges;
1800
1801 switch (ref) {
1802 default:
1803 MISSING_CASE(ref);
f0d759f0 1804 /* fall through */
186a277e
PZ		 1805 case 24000:
1806 ranges = ranges_24;
1807 break;
1808 case 19200:
1809 case 38400:
1810 ranges = ranges_19_38;
1811 break;
1812 }
1813
1814 if (min_cdclk > ranges[1])
1815 return ranges[2];
1816 else if (min_cdclk > ranges[0])
1817 return ranges[1];
1818 else
1819 return ranges[0];
1820}
1821
1822static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1823{
1824 int ratio;
1825
1826 if (cdclk == dev_priv->cdclk.hw.bypass)
1827 return 0;
1828
1829 switch (cdclk) {
1830 default:
1831 MISSING_CASE(cdclk);
f0d759f0 1832 /* fall through */
186a277e
PZ		 1833 case 307200:
1834 case 556800:
1835 case 652800:
1836 WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
1837 dev_priv->cdclk.hw.ref != 38400);
1838 break;
1839 case 312000:
1840 case 552000:
1841 case 648000:
1842 WARN_ON(dev_priv->cdclk.hw.ref != 24000);
1843 }
1844
1845 ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
1846
1847 return dev_priv->cdclk.hw.ref * ratio;
1848}
1849
1850static void icl_set_cdclk(struct drm_i915_private *dev_priv,
1851 const struct intel_cdclk_state *cdclk_state)
1852{
1853 unsigned int cdclk = cdclk_state->cdclk;
1854 unsigned int vco = cdclk_state->vco;
1855 int ret;
1856
1857 mutex_lock(&dev_priv->pcu_lock);
1858 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1859 SKL_CDCLK_PREPARE_FOR_CHANGE,
1860 SKL_CDCLK_READY_FOR_CHANGE,
1861 SKL_CDCLK_READY_FOR_CHANGE, 3);
1862 mutex_unlock(&dev_priv->pcu_lock);
1863 if (ret) {
1864 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1865 ret);
1866 return;
1867 }
1868
1869 if (dev_priv->cdclk.hw.vco != 0 &&
1870 dev_priv->cdclk.hw.vco != vco)
1871 cnl_cdclk_pll_disable(dev_priv);
1872
1873 if (dev_priv->cdclk.hw.vco != vco)
1874 cnl_cdclk_pll_enable(dev_priv, vco);
1875
1876 I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
1877 skl_cdclk_decimal(cdclk));
1878
1879 mutex_lock(&dev_priv->pcu_lock);
9378985e
PZ		 1880 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1881 cdclk_state->voltage_level);
186a277e
PZ		 1882 mutex_unlock(&dev_priv->pcu_lock);
1883
1884 intel_update_cdclk(dev_priv);
9378985e
PZ		 1885
1886 /*
1887 * Can't read out the voltage level :(
1888 * Let's just assume everything is as expected.
1889 */
1890 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1891}
1892
1893static u8 icl_calc_voltage_level(int cdclk)
1894{
1895 switch (cdclk) {
1896 case 50000:
1897 case 307200:
1898 case 312000:
1899 return 0;
1900 case 556800:
1901 case 552000:
1902 return 1;
1903 default:
1904 MISSING_CASE(cdclk);
f0d759f0 1905 /* fall through */
9378985e
PZ		 1906 case 652800:
1907 case 648000:
1908 return 2;
1909 }
186a277e
PZ		 1910}
1911
1912static void icl_get_cdclk(struct drm_i915_private *dev_priv,
1913 struct intel_cdclk_state *cdclk_state)
1914{
1915 u32 val;
1916
1917 cdclk_state->bypass = 50000;
1918
1919 val = I915_READ(SKL_DSSM);
1920 switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
1921 default:
1922 MISSING_CASE(val);
f0d759f0 1923 /* fall through */
186a277e
PZ		 1924 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1925 cdclk_state->ref = 24000;
1926 break;
1927 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1928 cdclk_state->ref = 19200;
1929 break;
1930 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1931 cdclk_state->ref = 38400;
1932 break;
1933 }
1934
1935 val = I915_READ(BXT_DE_PLL_ENABLE);
1936 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1937 (val & BXT_DE_PLL_LOCK) == 0) {
1938 /*
1939 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1940 * setting it to zero is a way to signal that.
1941 */
1942 cdclk_state->vco = 0;
1943 cdclk_state->cdclk = cdclk_state->bypass;
9378985e 1944 goto out;
186a277e
PZ		 1945 }
1946
1947 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1948
1949 val = I915_READ(CDCLK_CTL);
1950 WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
1951
1952 cdclk_state->cdclk = cdclk_state->vco / 2;
9378985e
PZ		 1953
1954out:
1955 /*
1956 * Can't read this out :( Let's assume it's
1957 * at least what the CDCLK frequency requires.
1958 */
1959 cdclk_state->voltage_level =
1960 icl_calc_voltage_level(cdclk_state->cdclk);
186a277e
PZ		 1961}
1962
1963/**
1964 * icl_init_cdclk - Initialize CDCLK on ICL
1965 * @dev_priv: i915 device
1966 *
1967 * Initialize CDCLK for ICL. This consists mainly of initializing
1968 * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
1969 * is generally done only during the display core initialization sequence, after
1970 * which the DMC will take care of turning CDCLK off/on as needed.
1971 */
1972void icl_init_cdclk(struct drm_i915_private *dev_priv)
1973{
1974 struct intel_cdclk_state sanitized_state;
1975 u32 val;
1976
1977 /* This sets dev_priv->cdclk.hw. */
1978 intel_update_cdclk(dev_priv);
1979 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1980
1981 /* This means CDCLK disabled. */
1982 if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1983 goto sanitize;
1984
1985 val = I915_READ(CDCLK_CTL);
1986
1987 if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
1988 goto sanitize;
1989
1990 if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
1991 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
1992 goto sanitize;
1993
1994 return;
1995
1996sanitize:
1997 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1998
1999 sanitized_state.ref = dev_priv->cdclk.hw.ref;
2000 sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
2001 sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
2002 sanitized_state.cdclk);
9378985e
PZ		 2003 sanitized_state.voltage_level =
2004 icl_calc_voltage_level(sanitized_state.cdclk);
186a277e
PZ		 2005
2006 icl_set_cdclk(dev_priv, &sanitized_state);
2007}
2008
2009/**
2010 * icl_uninit_cdclk - Uninitialize CDCLK on ICL
2011 * @dev_priv: i915 device
2012 *
2013 * Uninitialize CDCLK for ICL. This is done only during the display core
2014 * uninitialization sequence.
2015 */
2016void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
2017{
2018 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
2019
2020 cdclk_state.cdclk = cdclk_state.bypass;
2021 cdclk_state.vco = 0;
9378985e 2022 cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
186a277e
PZ		 2023
2024 icl_set_cdclk(dev_priv, &cdclk_state);
2025}
2026
d8d4a512
VS		 2027/**
2028 * cnl_init_cdclk - Initialize CDCLK on CNL
2029 * @dev_priv: i915 device
2030 *
2031 * Initialize CDCLK for CNL. This is generally
2032 * done only during the display core initialization sequence,
2033 * after which the DMC will take care of turning CDCLK off/on
2034 * as needed.
2035 */
2036void cnl_init_cdclk(struct drm_i915_private *dev_priv)
2037{
2038 struct intel_cdclk_state cdclk_state;
2039
2040 cnl_sanitize_cdclk(dev_priv);
2041
2042 if (dev_priv->cdclk.hw.cdclk != 0 &&
2043 dev_priv->cdclk.hw.vco != 0)
2044 return;
2045
2046 cdclk_state = dev_priv->cdclk.hw;
2047
d1999e9e 2048 cdclk_state.cdclk = cnl_calc_cdclk(0);
d8d4a512 2049 cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
48469ece 2050 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
d8d4a512
VS		 2051
2052 cnl_set_cdclk(dev_priv, &cdclk_state);
2053}
2054
2055/**
2056 * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
2057 * @dev_priv: i915 device
2058 *
2059 * Uninitialize CDCLK for CNL. This is done only
2060 * during the display core uninitialization sequence.
2061 */
2062void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
2063{
2064 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
2065
b6c51c3e 2066 cdclk_state.cdclk = cdclk_state.bypass;
d8d4a512 2067 cdclk_state.vco = 0;
48469ece 2068 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
d8d4a512
VS		 2069
2070 cnl_set_cdclk(dev_priv, &cdclk_state);
2071}
2072
49cd97a3 2073/**
64600bd5 2074 * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
49cd97a3
VS		 2075 * @a: first CDCLK state
2076 * @b: second CDCLK state
2077 *
2078 * Returns:
64600bd5 2079 * True if the CDCLK states require pipes to be off during reprogramming, false if not.
49cd97a3 2080 */
64600bd5 2081bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
49cd97a3
VS		 2082 const struct intel_cdclk_state *b)
2083{
64600bd5
VS		 2084 return a->cdclk != b->cdclk ||
2085 a->vco != b->vco ||
2086 a->ref != b->ref;
2087}
2088
2089/**
2090 * intel_cdclk_changed - Determine if two CDCLK states are different
2091 * @a: first CDCLK state
2092 * @b: second CDCLK state
2093 *
2094 * Returns:
2095 * True if the CDCLK states don't match, false if they do.
2096 */
2097bool intel_cdclk_changed(const struct intel_cdclk_state *a,
2098 const struct intel_cdclk_state *b)
2099{
2100 return intel_cdclk_needs_modeset(a, b) ||
2101 a->voltage_level != b->voltage_level;
7ff89ca2
VS		 2102}
2103
cfddadc9
VS		 2104void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
2105 const char *context)
2106{
b6c51c3e 2107 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
cfddadc9 2108 context, cdclk_state->cdclk, cdclk_state->vco,
b6c51c3e
ID		 2109 cdclk_state->ref, cdclk_state->bypass,
2110 cdclk_state->voltage_level);
cfddadc9
VS		 2111}
2112
b0587e4d
VS		 2113/**
2114 * intel_set_cdclk - Push the CDCLK state to the hardware
2115 * @dev_priv: i915 device
2116 * @cdclk_state: new CDCLK state
2117 *
2118 * Program the hardware based on the passed in CDCLK state,
2119 * if necessary.
2120 */
2121void intel_set_cdclk(struct drm_i915_private *dev_priv,
2122 const struct intel_cdclk_state *cdclk_state)
2123{
64600bd5 2124 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
b0587e4d
VS		 2125 return;
2126
2127 if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
2128 return;
2129
cfddadc9 2130 intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
b0587e4d
VS		 2131
2132 dev_priv->display.set_cdclk(dev_priv, cdclk_state);
cfddadc9
VS		 2133
2134 if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
2135 "cdclk state doesn't match!\n")) {
2136 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
2137 intel_dump_cdclk_state(cdclk_state, "[sw state]");
2138 }
b0587e4d
VS		 2139}
2140
d305e061
VS		 2141static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
2142 int pixel_rate)
2143{
42882336 2144 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
43037c86 2145 return DIV_ROUND_UP(pixel_rate, 2);
cf819eff 2146 else if (IS_GEN(dev_priv, 9) ||
d305e061
VS		 2147 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2148 return pixel_rate;
2149 else if (IS_CHERRYVIEW(dev_priv))
2150 return DIV_ROUND_UP(pixel_rate * 100, 95);
2151 else
2152 return DIV_ROUND_UP(pixel_rate * 100, 90);
2153}
2154
2155int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
7ff89ca2
VS		 2156{
2157 struct drm_i915_private *dev_priv =
2158 to_i915(crtc_state->base.crtc->dev);
d305e061
VS		 2159 int min_cdclk;
2160
2161 if (!crtc_state->base.enable)
2162 return 0;
2163
2164 min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
7ff89ca2
VS		 2165
2166 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
24f28450 2167 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
d305e061 2168 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
7ff89ca2 2169
78cfa580
PD		 2170 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2171 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2172 * there may be audio corruption or screen corruption." This cdclk
d305e061 2173 * restriction for GLK is 316.8 MHz.
7ff89ca2
VS		 2174 */
2175 if (intel_crtc_has_dp_encoder(crtc_state) &&
2176 crtc_state->has_audio &&
2177 crtc_state->port_clock >= 540000 &&
78cfa580 2178 crtc_state->lane_count == 4) {
d305e061
VS		 2179 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2180 /* Display WA #1145: glk,cnl */
2181 min_cdclk = max(316800, min_cdclk);
cf819eff 2182 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
d305e061
VS		 2183 /* Display WA #1144: skl,bxt */
2184 min_cdclk = max(432000, min_cdclk);
2185 }
78cfa580 2186 }
7ff89ca2 2187
904e1b1f
AK		 2188 /*
2189 * According to BSpec, "The CD clock frequency must be at least twice
8cbeb06d 2190 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
904e1b1f
AK		 2191 *
2192 * FIXME: Check the actual, not default, BCLK being used.
2193 *
2194 * FIXME: This does not depend on ->has_audio because the higher CDCLK
2195 * is required for audio probe, also when there are no audio capable
2196 * displays connected at probe time. This leads to unnecessarily high
2197 * CDCLK when audio is not required.
2198 *
2199 * FIXME: This limit is only applied when there are displays connected
2200 * at probe time. If we probe without displays, we'll still end up using
2201 * the platform minimum CDCLK, failing audio probe.
8cbeb06d 2202 */
904e1b1f 2203 if (INTEL_GEN(dev_priv) >= 9)
d305e061 2204 min_cdclk = max(2 * 96000, min_cdclk);
8cbeb06d 2205
c8dae55a
HG		 2206 /*
2207 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2208 * than 320000KHz.
2209 */
2210 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2211 IS_VALLEYVIEW(dev_priv))
2212 min_cdclk = max(320000, min_cdclk);
2213
9c61de4c
VS		 2214 if (min_cdclk > dev_priv->max_cdclk_freq) {
2215 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
2216 min_cdclk, dev_priv->max_cdclk_freq);
2217 return -EINVAL;
2218 }
2219
d305e061 2220 return min_cdclk;
7ff89ca2
VS		 2221}
2222
d305e061 2223static int intel_compute_min_cdclk(struct drm_atomic_state *state)
7ff89ca2
VS		 2224{
2225 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2226 struct drm_i915_private *dev_priv = to_i915(state->dev);
d305e061 2227 struct intel_crtc *crtc;
7ff89ca2 2228 struct intel_crtc_state *crtc_state;
9c61de4c 2229 int min_cdclk, i;
7ff89ca2
VS		 2230 enum pipe pipe;
2231
d305e061
VS		 2232 memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
2233 sizeof(intel_state->min_cdclk));
7ff89ca2 2234
9c61de4c
VS		 2235 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2236 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2237 if (min_cdclk < 0)
2238 return min_cdclk;
2239
2240 intel_state->min_cdclk[i] = min_cdclk;
2241 }
7ff89ca2 2242
9c61de4c 2243 min_cdclk = 0;
7ff89ca2 2244 for_each_pipe(dev_priv, pipe)
d305e061 2245 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
7ff89ca2 2246
d305e061 2247 return min_cdclk;
7ff89ca2
VS		 2248}
2249
53e9bf5e
VS		 2250/*
2251 * Note that this functions assumes that 0 is
2252 * the lowest voltage value, and higher values
2253 * correspond to increasingly higher voltages.
2254 *
2255 * Should that relationship no longer hold on
2256 * future platforms this code will need to be
2257 * adjusted.
2258 */
2259static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
2260{
2261 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2262 struct intel_crtc *crtc;
2263 struct intel_crtc_state *crtc_state;
2264 u8 min_voltage_level;
2265 int i;
2266 enum pipe pipe;
2267
2268 memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
2269 sizeof(state->min_voltage_level));
2270
2271 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2272 if (crtc_state->base.enable)
2273 state->min_voltage_level[i] =
2274 crtc_state->min_voltage_level;
2275 else
2276 state->min_voltage_level[i] = 0;
2277 }
2278
2279 min_voltage_level = 0;
2280 for_each_pipe(dev_priv, pipe)
2281 min_voltage_level = max(state->min_voltage_level[pipe],
2282 min_voltage_level);
2283
2284 return min_voltage_level;
2285}
2286
7ff89ca2
VS		 2287static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
2288{
3d5dbb10 2289 struct drm_i915_private *dev_priv = to_i915(state->dev);
9c61de4c
VS		 2290 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2291 int min_cdclk, cdclk;
bb0f4aab 2292
9c61de4c
VS		 2293 min_cdclk = intel_compute_min_cdclk(state);
2294 if (min_cdclk < 0)
2295 return min_cdclk;
7ff89ca2 2296
9c61de4c 2297 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
7ff89ca2 2298
bb0f4aab 2299 intel_state->cdclk.logical.cdclk = cdclk;
999c5766
VS		 2300 intel_state->cdclk.logical.voltage_level =
2301 vlv_calc_voltage_level(dev_priv, cdclk);
bb0f4aab
VS		 2302
2303 if (!intel_state->active_crtcs) {
2304 cdclk = vlv_calc_cdclk(dev_priv, 0);
2305
2306 intel_state->cdclk.actual.cdclk = cdclk;
999c5766
VS		 2307 intel_state->cdclk.actual.voltage_level =
2308 vlv_calc_voltage_level(dev_priv, cdclk);
bb0f4aab
VS		 2309 } else {
2310 intel_state->cdclk.actual =
2311 intel_state->cdclk.logical;
2312 }
7ff89ca2
VS		 2313
2314 return 0;
2315}
2316
7ff89ca2
VS		 2317static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
2318{
7ff89ca2 2319 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9c61de4c
VS		 2320 int min_cdclk, cdclk;
2321
2322 min_cdclk = intel_compute_min_cdclk(state);
2323 if (min_cdclk < 0)
2324 return min_cdclk;
7ff89ca2
VS		 2325
2326 /*
2327 * FIXME should also account for plane ratio
2328 * once 64bpp pixel formats are supported.
2329 */
d305e061 2330 cdclk = bdw_calc_cdclk(min_cdclk);
7ff89ca2 2331
bb0f4aab 2332 intel_state->cdclk.logical.cdclk = cdclk;
d7ffaeef
VS		 2333 intel_state->cdclk.logical.voltage_level =
2334 bdw_calc_voltage_level(cdclk);
bb0f4aab
VS		 2335
2336 if (!intel_state->active_crtcs) {
2337 cdclk = bdw_calc_cdclk(0);
2338
2339 intel_state->cdclk.actual.cdclk = cdclk;
d7ffaeef
VS		 2340 intel_state->cdclk.actual.voltage_level =
2341 bdw_calc_voltage_level(cdclk);
bb0f4aab
VS		 2342 } else {
2343 intel_state->cdclk.actual =
2344 intel_state->cdclk.logical;
2345 }
7ff89ca2
VS		 2346
2347 return 0;
2348}
2349
3297234a
RV		 2350static int skl_dpll0_vco(struct intel_atomic_state *intel_state)
2351{
2352 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
2353 struct intel_crtc *crtc;
2354 struct intel_crtc_state *crtc_state;
2355 int vco, i;
2356
2357 vco = intel_state->cdclk.logical.vco;
2358 if (!vco)
2359 vco = dev_priv->skl_preferred_vco_freq;
2360
2361 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2362 if (!crtc_state->base.enable)
2363 continue;
2364
2365 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2366 continue;
2367
2368 /*
2369 * DPLL0 VCO may need to be adjusted to get the correct
2370 * clock for eDP. This will affect cdclk as well.
2371 */
2372 switch (crtc_state->port_clock / 2) {
2373 case 108000:
2374 case 216000:
2375 vco = 8640000;
2376 break;
2377 default:
2378 vco = 8100000;
2379 break;
2380 }
2381 }
2382
2383 return vco;
2384}
2385
7ff89ca2
VS		 2386static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
2387{
9c61de4c
VS		 2388 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2389 int min_cdclk, cdclk, vco;
2390
2391 min_cdclk = intel_compute_min_cdclk(state);
2392 if (min_cdclk < 0)
2393 return min_cdclk;
bb0f4aab 2394
3297234a 2395 vco = skl_dpll0_vco(intel_state);
7ff89ca2
VS		 2396
2397 /*
2398 * FIXME should also account for plane ratio
2399 * once 64bpp pixel formats are supported.
2400 */
d305e061 2401 cdclk = skl_calc_cdclk(min_cdclk, vco);
7ff89ca2 2402
bb0f4aab
VS		 2403 intel_state->cdclk.logical.vco = vco;
2404 intel_state->cdclk.logical.cdclk = cdclk;
2aa97491
VS		 2405 intel_state->cdclk.logical.voltage_level =
2406 skl_calc_voltage_level(cdclk);
bb0f4aab
VS		 2407
2408 if (!intel_state->active_crtcs) {
2409 cdclk = skl_calc_cdclk(0, vco);
2410
2411 intel_state->cdclk.actual.vco = vco;
2412 intel_state->cdclk.actual.cdclk = cdclk;
2aa97491
VS		 2413 intel_state->cdclk.actual.voltage_level =
2414 skl_calc_voltage_level(cdclk);
bb0f4aab
VS		 2415 } else {
2416 intel_state->cdclk.actual =
2417 intel_state->cdclk.logical;
2418 }
7ff89ca2
VS		 2419
2420 return 0;
2421}
2422
7ff89ca2
VS		 2423static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
2424{
2425 struct drm_i915_private *dev_priv = to_i915(state->dev);
9c61de4c
VS		 2426 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2427 int min_cdclk, cdclk, vco;
2428
2429 min_cdclk = intel_compute_min_cdclk(state);
2430 if (min_cdclk < 0)
2431 return min_cdclk;
7ff89ca2 2432
bb0f4aab 2433 if (IS_GEMINILAKE(dev_priv)) {
d305e061 2434 cdclk = glk_calc_cdclk(min_cdclk);
bb0f4aab
VS		 2435 vco = glk_de_pll_vco(dev_priv, cdclk);
2436 } else {
d305e061 2437 cdclk = bxt_calc_cdclk(min_cdclk);
bb0f4aab
VS		 2438 vco = bxt_de_pll_vco(dev_priv, cdclk);
2439 }
2440
bb0f4aab
VS		 2441 intel_state->cdclk.logical.vco = vco;
2442 intel_state->cdclk.logical.cdclk = cdclk;
2123f442
VS		 2443 intel_state->cdclk.logical.voltage_level =
2444 bxt_calc_voltage_level(cdclk);
7ff89ca2
VS		 2445
2446 if (!intel_state->active_crtcs) {
bb0f4aab 2447 if (IS_GEMINILAKE(dev_priv)) {
7ff89ca2 2448 cdclk = glk_calc_cdclk(0);
bb0f4aab
VS		 2449 vco = glk_de_pll_vco(dev_priv, cdclk);
2450 } else {
7ff89ca2 2451 cdclk = bxt_calc_cdclk(0);
bb0f4aab
VS		 2452 vco = bxt_de_pll_vco(dev_priv, cdclk);
2453 }
7ff89ca2 2454
bb0f4aab
VS		 2455 intel_state->cdclk.actual.vco = vco;
2456 intel_state->cdclk.actual.cdclk = cdclk;
2123f442
VS		 2457 intel_state->cdclk.actual.voltage_level =
2458 bxt_calc_voltage_level(cdclk);
bb0f4aab
VS		 2459 } else {
2460 intel_state->cdclk.actual =
2461 intel_state->cdclk.logical;
7ff89ca2
VS		 2462 }
2463
2464 return 0;
2465}
2466
d1999e9e
RV		 2467static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
2468{
2469 struct drm_i915_private *dev_priv = to_i915(state->dev);
9c61de4c
VS		 2470 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2471 int min_cdclk, cdclk, vco;
2472
2473 min_cdclk = intel_compute_min_cdclk(state);
2474 if (min_cdclk < 0)
2475 return min_cdclk;
d1999e9e 2476
d305e061 2477 cdclk = cnl_calc_cdclk(min_cdclk);
d1999e9e
RV		 2478 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2479
d1999e9e
RV		 2480 intel_state->cdclk.logical.vco = vco;
2481 intel_state->cdclk.logical.cdclk = cdclk;
48469ece 2482 intel_state->cdclk.logical.voltage_level =
53e9bf5e
VS		 2483 max(cnl_calc_voltage_level(cdclk),
2484 cnl_compute_min_voltage_level(intel_state));
d1999e9e
RV		 2485
2486 if (!intel_state->active_crtcs) {
2487 cdclk = cnl_calc_cdclk(0);
2488 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2489
2490 intel_state->cdclk.actual.vco = vco;
2491 intel_state->cdclk.actual.cdclk = cdclk;
48469ece
VS		 2492 intel_state->cdclk.actual.voltage_level =
2493 cnl_calc_voltage_level(cdclk);
d1999e9e
RV		 2494 } else {
2495 intel_state->cdclk.actual =
2496 intel_state->cdclk.logical;
2497 }
2498
2499 return 0;
2500}
2501
186a277e
PZ		 2502static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
2503{
2504 struct drm_i915_private *dev_priv = to_i915(state->dev);
2505 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2506 unsigned int ref = intel_state->cdclk.logical.ref;
2507 int min_cdclk, cdclk, vco;
2508
2509 min_cdclk = intel_compute_min_cdclk(state);
2510 if (min_cdclk < 0)
2511 return min_cdclk;
2512
2513 cdclk = icl_calc_cdclk(min_cdclk, ref);
2514 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2515
2516 intel_state->cdclk.logical.vco = vco;
2517 intel_state->cdclk.logical.cdclk = cdclk;
9378985e
PZ		 2518 intel_state->cdclk.logical.voltage_level =
2519 max(icl_calc_voltage_level(cdclk),
2520 cnl_compute_min_voltage_level(intel_state));
186a277e
PZ		 2521
2522 if (!intel_state->active_crtcs) {
2523 cdclk = icl_calc_cdclk(0, ref);
2524 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2525
2526 intel_state->cdclk.actual.vco = vco;
2527 intel_state->cdclk.actual.cdclk = cdclk;
9378985e
PZ		 2528 intel_state->cdclk.actual.voltage_level =
2529 icl_calc_voltage_level(cdclk);
186a277e
PZ		 2530 } else {
2531 intel_state->cdclk.actual = intel_state->cdclk.logical;
2532 }
2533
2534 return 0;
2535}
2536
7ff89ca2
VS		 2537static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2538{
2539 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2540
42882336 2541 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
43037c86 2542 return 2 * max_cdclk_freq;
cf819eff 2543 else if (IS_GEN(dev_priv, 9) ||
d305e061 2544 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
7ff89ca2
VS		 2545 return max_cdclk_freq;
2546 else if (IS_CHERRYVIEW(dev_priv))
2547 return max_cdclk_freq*95/100;
c56b89f1 2548 else if (INTEL_GEN(dev_priv) < 4)
7ff89ca2
VS		 2549 return 2*max_cdclk_freq*90/100;
2550 else
2551 return max_cdclk_freq*90/100;
2552}
2553
2554/**
2555 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2556 * @dev_priv: i915 device
2557 *
2558 * Determine the maximum CDCLK frequency the platform supports, and also
2559 * derive the maximum dot clock frequency the maximum CDCLK frequency
2560 * allows.
2561 */
2562void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2563{
2dd24a9c 2564 if (INTEL_GEN(dev_priv) >= 11) {
186a277e
PZ		 2565 if (dev_priv->cdclk.hw.ref == 24000)
2566 dev_priv->max_cdclk_freq = 648000;
2567 else
2568 dev_priv->max_cdclk_freq = 652800;
2569 } else if (IS_CANNONLAKE(dev_priv)) {
d1999e9e
RV		 2570 dev_priv->max_cdclk_freq = 528000;
2571 } else if (IS_GEN9_BC(dev_priv)) {
7ff89ca2
VS		 2572 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2573 int max_cdclk, vco;
2574
2575 vco = dev_priv->skl_preferred_vco_freq;
2576 WARN_ON(vco != 8100000 && vco != 8640000);
2577
2578 /*
2579 * Use the lower (vco 8640) cdclk values as a
2580 * first guess. skl_calc_cdclk() will correct it
2581 * if the preferred vco is 8100 instead.
2582 */
2583 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2584 max_cdclk = 617143;
2585 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2586 max_cdclk = 540000;
2587 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2588 max_cdclk = 432000;
2589 else
2590 max_cdclk = 308571;
2591
2592 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2593 } else if (IS_GEMINILAKE(dev_priv)) {
2594 dev_priv->max_cdclk_freq = 316800;
2595 } else if (IS_BROXTON(dev_priv)) {
2596 dev_priv->max_cdclk_freq = 624000;
2597 } else if (IS_BROADWELL(dev_priv)) {
2598 /*
2599 * FIXME with extra cooling we can allow
2600 * 540 MHz for ULX and 675 Mhz for ULT.
2601 * How can we know if extra cooling is
2602 * available? PCI ID, VTB, something else?
2603 */
2604 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2605 dev_priv->max_cdclk_freq = 450000;
2606 else if (IS_BDW_ULX(dev_priv))
2607 dev_priv->max_cdclk_freq = 450000;
2608 else if (IS_BDW_ULT(dev_priv))
2609 dev_priv->max_cdclk_freq = 540000;
2610 else
2611 dev_priv->max_cdclk_freq = 675000;
2612 } else if (IS_CHERRYVIEW(dev_priv)) {
2613 dev_priv->max_cdclk_freq = 320000;
2614 } else if (IS_VALLEYVIEW(dev_priv)) {
2615 dev_priv->max_cdclk_freq = 400000;
2616 } else {
2617 /* otherwise assume cdclk is fixed */
49cd97a3 2618 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
7ff89ca2
VS		 2619 }
2620
2621 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2622
2623 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2624 dev_priv->max_cdclk_freq);
2625
2626 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2627 dev_priv->max_dotclk_freq);
2628}
2629
2630/**
2631 * intel_update_cdclk - Determine the current CDCLK frequency
2632 * @dev_priv: i915 device
2633 *
2634 * Determine the current CDCLK frequency.
2635 */
2636void intel_update_cdclk(struct drm_i915_private *dev_priv)
2637{
49cd97a3 2638 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
7ff89ca2 2639
7ff89ca2
VS		 2640 /*
2641 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2642 * Programmng [sic] note: bit[9:2] should be programmed to the number
2643 * of cdclk that generates 4MHz reference clock freq which is used to
2644 * generate GMBus clock. This will vary with the cdclk freq.
2645 */
2646 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2647 I915_WRITE(GMBUSFREQ_VLV,
49cd97a3 2648 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
7ff89ca2
VS		 2649}
2650
9d81a997
RV		 2651static int cnp_rawclk(struct drm_i915_private *dev_priv)
2652{
2653 u32 rawclk;
2654 int divider, fraction;
2655
2656 if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2657 /* 24 MHz */
2658 divider = 24000;
2659 fraction = 0;
2660 } else {
2661 /* 19.2 MHz */
2662 divider = 19000;
2663 fraction = 200;
2664 }
2665
af4de6ad 2666 rawclk = CNP_RAWCLK_DIV(divider / 1000);
704e504b
PZ		 2667 if (fraction) {
2668 int numerator = 1;
9d81a997 2669
704e504b
PZ		 2670 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
2671 fraction) - 1);
29b43ae2 2672 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
704e504b 2673 rawclk |= ICP_RAWCLK_NUM(numerator);
4ef99abd
AS		 2674 }
2675
4ef99abd 2676 I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
704e504b 2677 return divider + fraction;
4ef99abd
AS		 2678}
2679
7ff89ca2
VS		 2680static int pch_rawclk(struct drm_i915_private *dev_priv)
2681{
2682 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2683}
2684
2685static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2686{
2687 /* RAWCLK_FREQ_VLV register updated from power well code */
2688 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2689 CCK_DISPLAY_REF_CLOCK_CONTROL);
2690}
2691
2692static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2693{
cbe974fb 2694 u32 clkcfg;
7ff89ca2
VS		 2695
2696 /* hrawclock is 1/4 the FSB frequency */
2697 clkcfg = I915_READ(CLKCFG);
2698 switch (clkcfg & CLKCFG_FSB_MASK) {
2699 case CLKCFG_FSB_400:
2700 return 100000;
2701 case CLKCFG_FSB_533:
2702 return 133333;
2703 case CLKCFG_FSB_667:
2704 return 166667;
2705 case CLKCFG_FSB_800:
2706 return 200000;
2707 case CLKCFG_FSB_1067:
6f38123e 2708 case CLKCFG_FSB_1067_ALT:
7ff89ca2
VS		 2709 return 266667;
2710 case CLKCFG_FSB_1333:
6f38123e 2711 case CLKCFG_FSB_1333_ALT:
7ff89ca2 2712 return 333333;
7ff89ca2
VS		 2713 default:
2714 return 133333;
2715 }
2716}
2717
2718/**
2719 * intel_update_rawclk - Determine the current RAWCLK frequency
2720 * @dev_priv: i915 device
2721 *
2722 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2723 * frequency clock so this needs to done only once.
2724 */
2725void intel_update_rawclk(struct drm_i915_private *dev_priv)
2726{
c6c30b91 2727 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
9d81a997
RV		 2728 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2729 else if (HAS_PCH_SPLIT(dev_priv))
7ff89ca2
VS		 2730 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2731 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2732 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2733 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2734 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2735 else
2736 /* no rawclk on other platforms, or no need to know it */
2737 return;
2738
2739 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2740}
2741
2742/**
2743 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2744 * @dev_priv: i915 device
2745 */
2746void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2747{
2dd24a9c 2748 if (INTEL_GEN(dev_priv) >= 11) {
993298af
RV		 2749 dev_priv->display.set_cdclk = icl_set_cdclk;
2750 dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
2751 } else if (IS_CANNONLAKE(dev_priv)) {
2752 dev_priv->display.set_cdclk = cnl_set_cdclk;
7ff89ca2 2753 dev_priv->display.modeset_calc_cdclk =
993298af 2754 cnl_modeset_calc_cdclk;
7ff89ca2 2755 } else if (IS_GEN9_LP(dev_priv)) {
b0587e4d 2756 dev_priv->display.set_cdclk = bxt_set_cdclk;
7ff89ca2
VS		 2757 dev_priv->display.modeset_calc_cdclk =
2758 bxt_modeset_calc_cdclk;
2759 } else if (IS_GEN9_BC(dev_priv)) {
b0587e4d 2760 dev_priv->display.set_cdclk = skl_set_cdclk;
7ff89ca2
VS		 2761 dev_priv->display.modeset_calc_cdclk =
2762 skl_modeset_calc_cdclk;
993298af
RV		 2763 } else if (IS_BROADWELL(dev_priv)) {
2764 dev_priv->display.set_cdclk = bdw_set_cdclk;
d1999e9e 2765 dev_priv->display.modeset_calc_cdclk =
993298af
RV		 2766 bdw_modeset_calc_cdclk;
2767 } else if (IS_CHERRYVIEW(dev_priv)) {
2768 dev_priv->display.set_cdclk = chv_set_cdclk;
2769 dev_priv->display.modeset_calc_cdclk =
2770 vlv_modeset_calc_cdclk;
2771 } else if (IS_VALLEYVIEW(dev_priv)) {
2772 dev_priv->display.set_cdclk = vlv_set_cdclk;
2773 dev_priv->display.modeset_calc_cdclk =
2774 vlv_modeset_calc_cdclk;
7ff89ca2
VS		 2775 }
2776
2dd24a9c 2777 if (INTEL_GEN(dev_priv) >= 11)
186a277e
PZ		 2778 dev_priv->display.get_cdclk = icl_get_cdclk;
2779 else if (IS_CANNONLAKE(dev_priv))
945f2672 2780 dev_priv->display.get_cdclk = cnl_get_cdclk;
7ff89ca2
VS		 2781 else if (IS_GEN9_LP(dev_priv))
2782 dev_priv->display.get_cdclk = bxt_get_cdclk;
993298af
RV		 2783 else if (IS_GEN9_BC(dev_priv))
2784 dev_priv->display.get_cdclk = skl_get_cdclk;
7ff89ca2
VS		 2785 else if (IS_BROADWELL(dev_priv))
2786 dev_priv->display.get_cdclk = bdw_get_cdclk;
2787 else if (IS_HASWELL(dev_priv))
2788 dev_priv->display.get_cdclk = hsw_get_cdclk;
2789 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2790 dev_priv->display.get_cdclk = vlv_get_cdclk;
cf819eff 2791 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
7ff89ca2 2792 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
cf819eff 2793 else if (IS_GEN(dev_priv, 5))
7ff89ca2
VS		 2794 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2795 else if (IS_GM45(dev_priv))
2796 dev_priv->display.get_cdclk = gm45_get_cdclk;
6b9e441d 2797 else if (IS_G45(dev_priv))
7ff89ca2
VS		 2798 dev_priv->display.get_cdclk = g33_get_cdclk;
2799 else if (IS_I965GM(dev_priv))
2800 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2801 else if (IS_I965G(dev_priv))
2802 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2803 else if (IS_PINEVIEW(dev_priv))
2804 dev_priv->display.get_cdclk = pnv_get_cdclk;
2805 else if (IS_G33(dev_priv))
2806 dev_priv->display.get_cdclk = g33_get_cdclk;
2807 else if (IS_I945GM(dev_priv))
2808 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2809 else if (IS_I945G(dev_priv))
2810 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2811 else if (IS_I915GM(dev_priv))
2812 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2813 else if (IS_I915G(dev_priv))
2814 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2815 else if (IS_I865G(dev_priv))
2816 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2817 else if (IS_I85X(dev_priv))
2818 dev_priv->display.get_cdclk = i85x_get_cdclk;
2819 else if (IS_I845G(dev_priv))
2820 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2821 else { /* 830 */
2822 WARN(!IS_I830(dev_priv),
2823 "Unknown platform. Assuming 133 MHz CDCLK\n");
2824 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2825 }
2826}
Linux 6.x block layer and io_uring tree(s)