Commit | Line | Data |
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79e53945 | 1 | /* |
39507259 | 2 | * Copyright © 2006 Intel Corporation |
79e53945 JB |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
b30581a4 | 27 | |
9f0e7ff4 | 28 | #include <drm/drm_dp_helper.h> |
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
79e53945 JB |
31 | #include "i915_drv.h" |
32 | #include "intel_bios.h" | |
33 | ||
dd97950a JN |
34 | /** |
35 | * DOC: Video BIOS Table (VBT) | |
36 | * | |
37 | * The Video BIOS Table, or VBT, provides platform and board specific | |
38 | * configuration information to the driver that is not discoverable or available | |
39 | * through other means. The configuration is mostly related to display | |
40 | * hardware. The VBT is available via the ACPI OpRegion or, on older systems, in | |
41 | * the PCI ROM. | |
42 | * | |
43 | * The VBT consists of a VBT Header (defined as &struct vbt_header), a BDB | |
44 | * Header (&struct bdb_header), and a number of BIOS Data Blocks (BDB) that | |
45 | * contain the actual configuration information. The VBT Header, and thus the | |
46 | * VBT, begins with "$VBT" signature. The VBT Header contains the offset of the | |
47 | * BDB Header. The data blocks are concatenated after the BDB Header. The data | |
48 | * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of | |
49 | * data. (Block 53, the MIPI Sequence Block is an exception.) | |
50 | * | |
51 | * The driver parses the VBT during load. The relevant information is stored in | |
52 | * driver private data for ease of use, and the actual VBT is not read after | |
53 | * that. | |
54 | */ | |
55 | ||
9b9d172d | 56 | #define SLAVE_ADDR1 0x70 |
57 | #define SLAVE_ADDR2 0x72 | |
79e53945 | 58 | |
500a8cc4 ZW |
59 | static int panel_type; |
60 | ||
e8ef3b4c JN |
61 | static const void * |
62 | find_section(const void *_bdb, int section_id) | |
79e53945 | 63 | { |
e8ef3b4c JN |
64 | const struct bdb_header *bdb = _bdb; |
65 | const u8 *base = _bdb; | |
79e53945 | 66 | int index = 0; |
cd67d226 | 67 | u32 total, current_size; |
79e53945 JB |
68 | u8 current_id; |
69 | ||
70 | /* skip to first section */ | |
71 | index += bdb->header_size; | |
72 | total = bdb->bdb_size; | |
73 | ||
74 | /* walk the sections looking for section_id */ | |
d1f13fd2 | 75 | while (index + 3 < total) { |
79e53945 JB |
76 | current_id = *(base + index); |
77 | index++; | |
d1f13fd2 | 78 | |
e8ef3b4c | 79 | current_size = *((const u16 *)(base + index)); |
79e53945 | 80 | index += 2; |
d1f13fd2 | 81 | |
cd67d226 JN |
82 | /* The MIPI Sequence Block v3+ has a separate size field. */ |
83 | if (current_id == BDB_MIPI_SEQUENCE && *(base + index) >= 3) | |
84 | current_size = *((const u32 *)(base + index + 1)); | |
85 | ||
d1f13fd2 CW |
86 | if (index + current_size > total) |
87 | return NULL; | |
88 | ||
79e53945 JB |
89 | if (current_id == section_id) |
90 | return base + index; | |
d1f13fd2 | 91 | |
79e53945 JB |
92 | index += current_size; |
93 | } | |
94 | ||
95 | return NULL; | |
96 | } | |
97 | ||
db545019 | 98 | static u16 |
e8ef3b4c | 99 | get_blocksize(const void *p) |
db545019 DMEA |
100 | { |
101 | u16 *block_ptr, block_size; | |
102 | ||
103 | block_ptr = (u16 *)((char *)p - 2); | |
104 | block_size = *block_ptr; | |
105 | return block_size; | |
106 | } | |
107 | ||
79e53945 | 108 | static void |
88631706 | 109 | fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode, |
99834ea4 | 110 | const struct lvds_dvo_timing *dvo_timing) |
88631706 ML |
111 | { |
112 | panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) | | |
113 | dvo_timing->hactive_lo; | |
114 | panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay + | |
115 | ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo); | |
116 | panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start + | |
117 | dvo_timing->hsync_pulse_width; | |
118 | panel_fixed_mode->htotal = panel_fixed_mode->hdisplay + | |
119 | ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo); | |
120 | ||
121 | panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) | | |
122 | dvo_timing->vactive_lo; | |
123 | panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay + | |
124 | dvo_timing->vsync_off; | |
125 | panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start + | |
126 | dvo_timing->vsync_pulse_width; | |
127 | panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay + | |
128 | ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo); | |
129 | panel_fixed_mode->clock = dvo_timing->clock * 10; | |
130 | panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; | |
131 | ||
9bc35499 AJ |
132 | if (dvo_timing->hsync_positive) |
133 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
134 | else | |
135 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
136 | ||
137 | if (dvo_timing->vsync_positive) | |
138 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
139 | else | |
140 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
141 | ||
88631706 ML |
142 | /* Some VBTs have bogus h/vtotal values */ |
143 | if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) | |
144 | panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1; | |
145 | if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) | |
146 | panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1; | |
147 | ||
148 | drm_mode_set_name(panel_fixed_mode); | |
149 | } | |
150 | ||
99834ea4 CW |
151 | static const struct lvds_dvo_timing * |
152 | get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data, | |
153 | const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs, | |
154 | int index) | |
155 | { | |
156 | /* | |
157 | * the size of fp_timing varies on the different platform. | |
158 | * So calculate the DVO timing relative offset in LVDS data | |
159 | * entry to get the DVO timing entry | |
160 | */ | |
161 | ||
162 | int lfp_data_size = | |
163 | lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset - | |
164 | lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset; | |
165 | int dvo_timing_offset = | |
166 | lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset - | |
167 | lvds_lfp_data_ptrs->ptr[0].fp_timing_offset; | |
168 | char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index; | |
169 | ||
170 | return (struct lvds_dvo_timing *)(entry + dvo_timing_offset); | |
171 | } | |
172 | ||
b0354385 TI |
173 | /* get lvds_fp_timing entry |
174 | * this function may return NULL if the corresponding entry is invalid | |
175 | */ | |
176 | static const struct lvds_fp_timing * | |
177 | get_lvds_fp_timing(const struct bdb_header *bdb, | |
178 | const struct bdb_lvds_lfp_data *data, | |
179 | const struct bdb_lvds_lfp_data_ptrs *ptrs, | |
180 | int index) | |
181 | { | |
182 | size_t data_ofs = (const u8 *)data - (const u8 *)bdb; | |
183 | u16 data_size = ((const u16 *)data)[-1]; /* stored in header */ | |
184 | size_t ofs; | |
185 | ||
186 | if (index >= ARRAY_SIZE(ptrs->ptr)) | |
187 | return NULL; | |
188 | ofs = ptrs->ptr[index].fp_timing_offset; | |
189 | if (ofs < data_ofs || | |
190 | ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size) | |
191 | return NULL; | |
192 | return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs); | |
193 | } | |
194 | ||
88631706 ML |
195 | /* Try to find integrated panel data */ |
196 | static void | |
197 | parse_lfp_panel_data(struct drm_i915_private *dev_priv, | |
dcb58a40 | 198 | const struct bdb_header *bdb) |
79e53945 | 199 | { |
99834ea4 CW |
200 | const struct bdb_lvds_options *lvds_options; |
201 | const struct bdb_lvds_lfp_data *lvds_lfp_data; | |
202 | const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs; | |
203 | const struct lvds_dvo_timing *panel_dvo_timing; | |
b0354385 | 204 | const struct lvds_fp_timing *fp_timing; |
79e53945 | 205 | struct drm_display_mode *panel_fixed_mode; |
c329a4ec | 206 | int drrs_mode; |
79e53945 | 207 | |
79e53945 JB |
208 | lvds_options = find_section(bdb, BDB_LVDS_OPTIONS); |
209 | if (!lvds_options) | |
210 | return; | |
211 | ||
41aa3448 | 212 | dev_priv->vbt.lvds_dither = lvds_options->pixel_dither; |
79e53945 JB |
213 | if (lvds_options->panel_type == 0xff) |
214 | return; | |
6a04002b | 215 | |
500a8cc4 | 216 | panel_type = lvds_options->panel_type; |
79e53945 | 217 | |
83a7280e PB |
218 | drrs_mode = (lvds_options->dps_panel_type_bits |
219 | >> (panel_type * 2)) & MODE_MASK; | |
220 | /* | |
221 | * VBT has static DRRS = 0 and seamless DRRS = 2. | |
222 | * The below piece of code is required to adjust vbt.drrs_type | |
223 | * to match the enum drrs_support_type. | |
224 | */ | |
225 | switch (drrs_mode) { | |
226 | case 0: | |
227 | dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT; | |
228 | DRM_DEBUG_KMS("DRRS supported mode is static\n"); | |
229 | break; | |
230 | case 2: | |
231 | dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT; | |
232 | DRM_DEBUG_KMS("DRRS supported mode is seamless\n"); | |
233 | break; | |
234 | default: | |
235 | dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; | |
236 | DRM_DEBUG_KMS("DRRS not supported (VBT input)\n"); | |
237 | break; | |
238 | } | |
239 | ||
79e53945 JB |
240 | lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA); |
241 | if (!lvds_lfp_data) | |
242 | return; | |
243 | ||
1b16de0b JB |
244 | lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS); |
245 | if (!lvds_lfp_data_ptrs) | |
246 | return; | |
247 | ||
41aa3448 | 248 | dev_priv->vbt.lvds_vbt = 1; |
79e53945 | 249 | |
99834ea4 CW |
250 | panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data, |
251 | lvds_lfp_data_ptrs, | |
252 | lvds_options->panel_type); | |
79e53945 | 253 | |
9a298b2a | 254 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
6edc3242 CW |
255 | if (!panel_fixed_mode) |
256 | return; | |
79e53945 | 257 | |
99834ea4 | 258 | fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing); |
79e53945 | 259 | |
41aa3448 | 260 | dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 261 | |
28c97730 | 262 | DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n"); |
88631706 | 263 | drm_mode_debug_printmodeline(panel_fixed_mode); |
37df9673 | 264 | |
b0354385 TI |
265 | fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data, |
266 | lvds_lfp_data_ptrs, | |
267 | lvds_options->panel_type); | |
268 | if (fp_timing) { | |
269 | /* check the resolution, just to be sure */ | |
270 | if (fp_timing->x_res == panel_fixed_mode->hdisplay && | |
271 | fp_timing->y_res == panel_fixed_mode->vdisplay) { | |
41aa3448 | 272 | dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val; |
b0354385 | 273 | DRM_DEBUG_KMS("VBT initial LVDS value %x\n", |
41aa3448 | 274 | dev_priv->vbt.bios_lvds_val); |
b0354385 TI |
275 | } |
276 | } | |
88631706 ML |
277 | } |
278 | ||
f00076d2 | 279 | static void |
dcb58a40 JN |
280 | parse_lfp_backlight(struct drm_i915_private *dev_priv, |
281 | const struct bdb_header *bdb) | |
f00076d2 JN |
282 | { |
283 | const struct bdb_lfp_backlight_data *backlight_data; | |
284 | const struct bdb_lfp_backlight_data_entry *entry; | |
285 | ||
286 | backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT); | |
287 | if (!backlight_data) | |
288 | return; | |
289 | ||
290 | if (backlight_data->entry_size != sizeof(backlight_data->data[0])) { | |
291 | DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n", | |
292 | backlight_data->entry_size); | |
293 | return; | |
294 | } | |
295 | ||
296 | entry = &backlight_data->data[panel_type]; | |
297 | ||
39fbc9c8 JN |
298 | dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM; |
299 | if (!dev_priv->vbt.backlight.present) { | |
300 | DRM_DEBUG_KMS("PWM backlight not present in VBT (type %u)\n", | |
301 | entry->type); | |
302 | return; | |
303 | } | |
304 | ||
f00076d2 JN |
305 | dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; |
306 | dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm; | |
1de6068e | 307 | dev_priv->vbt.backlight.min_brightness = entry->min_brightness; |
f00076d2 JN |
308 | DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, " |
309 | "active %s, min brightness %u, level %u\n", | |
310 | dev_priv->vbt.backlight.pwm_freq_hz, | |
311 | dev_priv->vbt.backlight.active_low_pwm ? "low" : "high", | |
1de6068e | 312 | dev_priv->vbt.backlight.min_brightness, |
f00076d2 JN |
313 | backlight_data->level[panel_type]); |
314 | } | |
315 | ||
88631706 ML |
316 | /* Try to find sdvo panel data */ |
317 | static void | |
318 | parse_sdvo_panel_data(struct drm_i915_private *dev_priv, | |
dcb58a40 | 319 | const struct bdb_header *bdb) |
88631706 | 320 | { |
e8ef3b4c | 321 | const struct lvds_dvo_timing *dvo_timing; |
88631706 | 322 | struct drm_display_mode *panel_fixed_mode; |
5a1e5b6c | 323 | int index; |
79e53945 | 324 | |
d330a953 | 325 | index = i915.vbt_sdvo_panel_type; |
c10e408a MF |
326 | if (index == -2) { |
327 | DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n"); | |
328 | return; | |
329 | } | |
330 | ||
5a1e5b6c | 331 | if (index == -1) { |
e8ef3b4c | 332 | const struct bdb_sdvo_lvds_options *sdvo_lvds_options; |
5a1e5b6c CW |
333 | |
334 | sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS); | |
335 | if (!sdvo_lvds_options) | |
336 | return; | |
337 | ||
338 | index = sdvo_lvds_options->panel_type; | |
339 | } | |
88631706 ML |
340 | |
341 | dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS); | |
342 | if (!dvo_timing) | |
343 | return; | |
344 | ||
9a298b2a | 345 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
88631706 ML |
346 | if (!panel_fixed_mode) |
347 | return; | |
348 | ||
5a1e5b6c | 349 | fill_detail_timing_data(panel_fixed_mode, dvo_timing + index); |
88631706 | 350 | |
41aa3448 | 351 | dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 352 | |
5a1e5b6c CW |
353 | DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n"); |
354 | drm_mode_debug_printmodeline(panel_fixed_mode); | |
79e53945 JB |
355 | } |
356 | ||
98f3a1dc | 357 | static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, |
9a4114ff BF |
358 | bool alternate) |
359 | { | |
98f3a1dc | 360 | switch (INTEL_INFO(dev_priv)->gen) { |
9a4114ff | 361 | case 2: |
e91e941b | 362 | return alternate ? 66667 : 48000; |
9a4114ff BF |
363 | case 3: |
364 | case 4: | |
e91e941b | 365 | return alternate ? 100000 : 96000; |
9a4114ff | 366 | default: |
e91e941b | 367 | return alternate ? 100000 : 120000; |
9a4114ff BF |
368 | } |
369 | } | |
370 | ||
79e53945 JB |
371 | static void |
372 | parse_general_features(struct drm_i915_private *dev_priv, | |
dcb58a40 | 373 | const struct bdb_header *bdb) |
79e53945 | 374 | { |
e8ef3b4c | 375 | const struct bdb_general_features *general; |
79e53945 | 376 | |
79e53945 | 377 | general = find_section(bdb, BDB_GENERAL_FEATURES); |
34957e8c JN |
378 | if (!general) |
379 | return; | |
380 | ||
381 | dev_priv->vbt.int_tv_support = general->int_tv_support; | |
382 | /* int_crt_support can't be trusted on earlier platforms */ | |
383 | if (bdb->version >= 155 && | |
384 | (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv))) | |
385 | dev_priv->vbt.int_crt_support = general->int_crt_support; | |
386 | dev_priv->vbt.lvds_use_ssc = general->enable_ssc; | |
387 | dev_priv->vbt.lvds_ssc_freq = | |
388 | intel_bios_ssc_frequency(dev_priv, general->ssc_freq); | |
389 | dev_priv->vbt.display_clock_mode = general->display_clock_mode; | |
390 | dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; | |
391 | DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", | |
392 | dev_priv->vbt.int_tv_support, | |
393 | dev_priv->vbt.int_crt_support, | |
394 | dev_priv->vbt.lvds_use_ssc, | |
395 | dev_priv->vbt.lvds_ssc_freq, | |
396 | dev_priv->vbt.display_clock_mode, | |
397 | dev_priv->vbt.fdi_rx_polarity_inverted); | |
79e53945 JB |
398 | } |
399 | ||
db545019 DMEA |
400 | static void |
401 | parse_general_definitions(struct drm_i915_private *dev_priv, | |
dcb58a40 | 402 | const struct bdb_header *bdb) |
db545019 | 403 | { |
e8ef3b4c | 404 | const struct bdb_general_definitions *general; |
db545019 | 405 | |
db545019 DMEA |
406 | general = find_section(bdb, BDB_GENERAL_DEFINITIONS); |
407 | if (general) { | |
408 | u16 block_size = get_blocksize(general); | |
409 | if (block_size >= sizeof(*general)) { | |
410 | int bus_pin = general->crt_ddc_gmbus_pin; | |
28c97730 | 411 | DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin); |
88ac7939 | 412 | if (intel_gmbus_is_valid_pin(dev_priv, bus_pin)) |
41aa3448 | 413 | dev_priv->vbt.crt_ddc_pin = bus_pin; |
db545019 | 414 | } else { |
28c97730 | 415 | DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n", |
3bd7d909 | 416 | block_size); |
db545019 DMEA |
417 | } |
418 | } | |
419 | } | |
420 | ||
e8ef3b4c JN |
421 | static const union child_device_config * |
422 | child_device_ptr(const struct bdb_general_definitions *p_defs, int i) | |
90e4f159 | 423 | { |
e8ef3b4c | 424 | return (const void *) &p_defs->devices[i * p_defs->child_dev_size]; |
90e4f159 VS |
425 | } |
426 | ||
9b9d172d | 427 | static void |
428 | parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, | |
dcb58a40 | 429 | const struct bdb_header *bdb) |
9b9d172d | 430 | { |
431 | struct sdvo_device_mapping *p_mapping; | |
e8ef3b4c | 432 | const struct bdb_general_definitions *p_defs; |
6cc38aca | 433 | const struct old_child_dev_config *child; /* legacy */ |
9b9d172d | 434 | int i, child_device_num, count; |
db545019 | 435 | u16 block_size; |
9b9d172d | 436 | |
437 | p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); | |
438 | if (!p_defs) { | |
44834a67 | 439 | DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n"); |
9b9d172d | 440 | return; |
441 | } | |
6cc38aca JN |
442 | |
443 | /* | |
444 | * Only parse SDVO mappings when the general definitions block child | |
445 | * device size matches that of the *legacy* child device config | |
446 | * struct. Thus, SDVO mapping will be skipped for newer VBT. | |
9b9d172d | 447 | */ |
6cc38aca JN |
448 | if (p_defs->child_dev_size != sizeof(*child)) { |
449 | DRM_DEBUG_KMS("Unsupported child device size for SDVO mapping.\n"); | |
9b9d172d | 450 | return; |
451 | } | |
452 | /* get the block size of general definitions */ | |
db545019 | 453 | block_size = get_blocksize(p_defs); |
9b9d172d | 454 | /* get the number of child device */ |
455 | child_device_num = (block_size - sizeof(*p_defs)) / | |
90e4f159 | 456 | p_defs->child_dev_size; |
9b9d172d | 457 | count = 0; |
458 | for (i = 0; i < child_device_num; i++) { | |
6cc38aca JN |
459 | child = &child_device_ptr(p_defs, i)->old; |
460 | if (!child->device_type) { | |
9b9d172d | 461 | /* skip the device block if device type is invalid */ |
462 | continue; | |
463 | } | |
6cc38aca JN |
464 | if (child->slave_addr != SLAVE_ADDR1 && |
465 | child->slave_addr != SLAVE_ADDR2) { | |
9b9d172d | 466 | /* |
467 | * If the slave address is neither 0x70 nor 0x72, | |
468 | * it is not a SDVO device. Skip it. | |
469 | */ | |
470 | continue; | |
471 | } | |
6cc38aca JN |
472 | if (child->dvo_port != DEVICE_PORT_DVOB && |
473 | child->dvo_port != DEVICE_PORT_DVOC) { | |
9b9d172d | 474 | /* skip the incorrect SDVO port */ |
0206e353 | 475 | DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n"); |
9b9d172d | 476 | continue; |
477 | } | |
28c97730 | 478 | DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on" |
6cc38aca JN |
479 | " %s port\n", |
480 | child->slave_addr, | |
481 | (child->dvo_port == DEVICE_PORT_DVOB) ? | |
482 | "SDVOB" : "SDVOC"); | |
483 | p_mapping = &(dev_priv->sdvo_mappings[child->dvo_port - 1]); | |
9b9d172d | 484 | if (!p_mapping->initialized) { |
6cc38aca JN |
485 | p_mapping->dvo_port = child->dvo_port; |
486 | p_mapping->slave_addr = child->slave_addr; | |
487 | p_mapping->dvo_wiring = child->dvo_wiring; | |
488 | p_mapping->ddc_pin = child->ddc_pin; | |
489 | p_mapping->i2c_pin = child->i2c_pin; | |
9b9d172d | 490 | p_mapping->initialized = 1; |
46eb3036 | 491 | DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", |
e957d772 CW |
492 | p_mapping->dvo_port, |
493 | p_mapping->slave_addr, | |
494 | p_mapping->dvo_wiring, | |
495 | p_mapping->ddc_pin, | |
46eb3036 | 496 | p_mapping->i2c_pin); |
9b9d172d | 497 | } else { |
28c97730 | 498 | DRM_DEBUG_KMS("Maybe one SDVO port is shared by " |
9b9d172d | 499 | "two SDVO device.\n"); |
500 | } | |
6cc38aca | 501 | if (child->slave2_addr) { |
9b9d172d | 502 | /* Maybe this is a SDVO device with multiple inputs */ |
503 | /* And the mapping info is not added */ | |
28c97730 ZY |
504 | DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this" |
505 | " is a SDVO device with multiple inputs.\n"); | |
9b9d172d | 506 | } |
507 | count++; | |
508 | } | |
509 | ||
510 | if (!count) { | |
511 | /* No SDVO device info is found */ | |
28c97730 | 512 | DRM_DEBUG_KMS("No SDVO device info is found in VBT\n"); |
9b9d172d | 513 | } |
514 | return; | |
515 | } | |
32f9d658 ZW |
516 | |
517 | static void | |
518 | parse_driver_features(struct drm_i915_private *dev_priv, | |
dcb58a40 | 519 | const struct bdb_header *bdb) |
32f9d658 | 520 | { |
e8ef3b4c | 521 | const struct bdb_driver_features *driver; |
32f9d658 | 522 | |
32f9d658 | 523 | driver = find_section(bdb, BDB_DRIVER_FEATURES); |
652c393a JB |
524 | if (!driver) |
525 | return; | |
526 | ||
6fca55b1 | 527 | if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP) |
41aa3448 | 528 | dev_priv->vbt.edp_support = 1; |
652c393a | 529 | |
5ceb0f9b | 530 | if (driver->dual_frequency) |
652c393a | 531 | dev_priv->render_reclock_avail = true; |
83a7280e PB |
532 | |
533 | DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled); | |
534 | /* | |
535 | * If DRRS is not supported, drrs_type has to be set to 0. | |
536 | * This is because, VBT is configured in such a way that | |
537 | * static DRRS is 0 and DRRS not supported is represented by | |
538 | * driver->drrs_enabled=false | |
539 | */ | |
540 | if (!driver->drrs_enabled) | |
541 | dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; | |
32f9d658 ZW |
542 | } |
543 | ||
500a8cc4 | 544 | static void |
dcb58a40 | 545 | parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) |
500a8cc4 | 546 | { |
e8ef3b4c JN |
547 | const struct bdb_edp *edp; |
548 | const struct edp_power_seq *edp_pps; | |
549 | const struct edp_link_params *edp_link_params; | |
500a8cc4 ZW |
550 | |
551 | edp = find_section(bdb, BDB_EDP); | |
552 | if (!edp) { | |
6fca55b1 | 553 | if (dev_priv->vbt.edp_support) |
9a30a61f | 554 | DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported.\n"); |
500a8cc4 ZW |
555 | return; |
556 | } | |
557 | ||
558 | switch ((edp->color_depth >> (panel_type * 2)) & 3) { | |
559 | case EDP_18BPP: | |
41aa3448 | 560 | dev_priv->vbt.edp_bpp = 18; |
500a8cc4 ZW |
561 | break; |
562 | case EDP_24BPP: | |
41aa3448 | 563 | dev_priv->vbt.edp_bpp = 24; |
500a8cc4 ZW |
564 | break; |
565 | case EDP_30BPP: | |
41aa3448 | 566 | dev_priv->vbt.edp_bpp = 30; |
500a8cc4 ZW |
567 | break; |
568 | } | |
5ceb0f9b | 569 | |
9f0e7ff4 JB |
570 | /* Get the eDP sequencing and link info */ |
571 | edp_pps = &edp->power_seqs[panel_type]; | |
572 | edp_link_params = &edp->link_params[panel_type]; | |
5ceb0f9b | 573 | |
41aa3448 | 574 | dev_priv->vbt.edp_pps = *edp_pps; |
5ceb0f9b | 575 | |
e13e2b2c JN |
576 | switch (edp_link_params->rate) { |
577 | case EDP_RATE_1_62: | |
578 | dev_priv->vbt.edp_rate = DP_LINK_BW_1_62; | |
579 | break; | |
580 | case EDP_RATE_2_7: | |
581 | dev_priv->vbt.edp_rate = DP_LINK_BW_2_7; | |
582 | break; | |
583 | default: | |
584 | DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n", | |
585 | edp_link_params->rate); | |
586 | break; | |
587 | } | |
588 | ||
9f0e7ff4 | 589 | switch (edp_link_params->lanes) { |
e13e2b2c | 590 | case EDP_LANE_1: |
41aa3448 | 591 | dev_priv->vbt.edp_lanes = 1; |
9f0e7ff4 | 592 | break; |
e13e2b2c | 593 | case EDP_LANE_2: |
41aa3448 | 594 | dev_priv->vbt.edp_lanes = 2; |
9f0e7ff4 | 595 | break; |
e13e2b2c | 596 | case EDP_LANE_4: |
41aa3448 | 597 | dev_priv->vbt.edp_lanes = 4; |
9f0e7ff4 | 598 | break; |
e13e2b2c JN |
599 | default: |
600 | DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n", | |
601 | edp_link_params->lanes); | |
602 | break; | |
9f0e7ff4 | 603 | } |
e13e2b2c | 604 | |
9f0e7ff4 | 605 | switch (edp_link_params->preemphasis) { |
e13e2b2c | 606 | case EDP_PREEMPHASIS_NONE: |
bd60018a | 607 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0; |
9f0e7ff4 | 608 | break; |
e13e2b2c | 609 | case EDP_PREEMPHASIS_3_5dB: |
bd60018a | 610 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1; |
9f0e7ff4 | 611 | break; |
e13e2b2c | 612 | case EDP_PREEMPHASIS_6dB: |
bd60018a | 613 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2; |
9f0e7ff4 | 614 | break; |
e13e2b2c | 615 | case EDP_PREEMPHASIS_9_5dB: |
bd60018a | 616 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; |
9f0e7ff4 | 617 | break; |
e13e2b2c JN |
618 | default: |
619 | DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n", | |
620 | edp_link_params->preemphasis); | |
621 | break; | |
9f0e7ff4 | 622 | } |
e13e2b2c | 623 | |
9f0e7ff4 | 624 | switch (edp_link_params->vswing) { |
e13e2b2c | 625 | case EDP_VSWING_0_4V: |
bd60018a | 626 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; |
9f0e7ff4 | 627 | break; |
e13e2b2c | 628 | case EDP_VSWING_0_6V: |
bd60018a | 629 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1; |
9f0e7ff4 | 630 | break; |
e13e2b2c | 631 | case EDP_VSWING_0_8V: |
bd60018a | 632 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
9f0e7ff4 | 633 | break; |
e13e2b2c | 634 | case EDP_VSWING_1_2V: |
bd60018a | 635 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
9f0e7ff4 | 636 | break; |
e13e2b2c JN |
637 | default: |
638 | DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n", | |
639 | edp_link_params->vswing); | |
640 | break; | |
9f0e7ff4 | 641 | } |
9a57f5bb SJ |
642 | |
643 | if (bdb->version >= 173) { | |
644 | uint8_t vswing; | |
645 | ||
9e458034 SJ |
646 | /* Don't read from VBT if module parameter has valid value*/ |
647 | if (i915.edp_vswing) { | |
648 | dev_priv->edp_low_vswing = i915.edp_vswing == 1; | |
649 | } else { | |
650 | vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; | |
651 | dev_priv->edp_low_vswing = vswing == 0; | |
652 | } | |
9a57f5bb | 653 | } |
500a8cc4 ZW |
654 | } |
655 | ||
bfd7ebda | 656 | static void |
dcb58a40 | 657 | parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) |
bfd7ebda | 658 | { |
e8ef3b4c JN |
659 | const struct bdb_psr *psr; |
660 | const struct psr_table *psr_table; | |
bfd7ebda RV |
661 | |
662 | psr = find_section(bdb, BDB_PSR); | |
663 | if (!psr) { | |
664 | DRM_DEBUG_KMS("No PSR BDB found.\n"); | |
665 | return; | |
666 | } | |
667 | ||
668 | psr_table = &psr->psr_table[panel_type]; | |
669 | ||
670 | dev_priv->vbt.psr.full_link = psr_table->full_link; | |
671 | dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; | |
672 | ||
673 | /* Allowed VBT values goes from 0 to 15 */ | |
674 | dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : | |
675 | psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames; | |
676 | ||
677 | switch (psr_table->lines_to_wait) { | |
678 | case 0: | |
679 | dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT; | |
680 | break; | |
681 | case 1: | |
682 | dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT; | |
683 | break; | |
684 | case 2: | |
685 | dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT; | |
686 | break; | |
687 | case 3: | |
688 | dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT; | |
689 | break; | |
690 | default: | |
691 | DRM_DEBUG_KMS("VBT has unknown PSR lines to wait %u\n", | |
692 | psr_table->lines_to_wait); | |
693 | break; | |
694 | } | |
695 | ||
696 | dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time; | |
697 | dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time; | |
698 | } | |
699 | ||
d3b542fc SK |
700 | static u8 *goto_next_sequence(u8 *data, int *size) |
701 | { | |
702 | u16 len; | |
703 | int tmp = *size; | |
704 | ||
705 | if (--tmp < 0) | |
706 | return NULL; | |
707 | ||
708 | /* goto first element */ | |
709 | data++; | |
710 | while (1) { | |
711 | switch (*data) { | |
712 | case MIPI_SEQ_ELEM_SEND_PKT: | |
713 | /* | |
714 | * skip by this element payload size | |
715 | * skip elem id, command flag and data type | |
716 | */ | |
b0256cdc SK |
717 | tmp -= 5; |
718 | if (tmp < 0) | |
d3b542fc SK |
719 | return NULL; |
720 | ||
721 | data += 3; | |
722 | len = *((u16 *)data); | |
723 | ||
b0256cdc SK |
724 | tmp -= len; |
725 | if (tmp < 0) | |
d3b542fc SK |
726 | return NULL; |
727 | ||
728 | /* skip by len */ | |
729 | data = data + 2 + len; | |
730 | break; | |
731 | case MIPI_SEQ_ELEM_DELAY: | |
732 | /* skip by elem id, and delay is 4 bytes */ | |
b0256cdc SK |
733 | tmp -= 5; |
734 | if (tmp < 0) | |
d3b542fc SK |
735 | return NULL; |
736 | ||
737 | data += 5; | |
738 | break; | |
739 | case MIPI_SEQ_ELEM_GPIO: | |
b0256cdc SK |
740 | tmp -= 3; |
741 | if (tmp < 0) | |
d3b542fc SK |
742 | return NULL; |
743 | ||
744 | data += 3; | |
745 | break; | |
746 | default: | |
747 | DRM_ERROR("Unknown element\n"); | |
748 | return NULL; | |
749 | } | |
750 | ||
751 | /* end of sequence ? */ | |
752 | if (*data == 0) | |
753 | break; | |
754 | } | |
755 | ||
756 | /* goto next sequence or end of block byte */ | |
757 | if (--tmp < 0) | |
758 | return NULL; | |
759 | ||
760 | data++; | |
761 | ||
762 | /* update amount of data left for the sequence block to be parsed */ | |
763 | *size = tmp; | |
764 | return data; | |
765 | } | |
766 | ||
d17c5443 | 767 | static void |
dcb58a40 | 768 | parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) |
d17c5443 | 769 | { |
e8ef3b4c JN |
770 | const struct bdb_mipi_config *start; |
771 | const struct bdb_mipi_sequence *sequence; | |
772 | const struct mipi_config *config; | |
773 | const struct mipi_pps_data *pps; | |
774 | u8 *data; | |
775 | const u8 *seq_data; | |
d3b542fc SK |
776 | int i, panel_id, seq_size; |
777 | u16 block_size; | |
778 | ||
3e6bd011 SK |
779 | /* parse MIPI blocks only if LFP type is MIPI */ |
780 | if (!dev_priv->vbt.has_mipi) | |
781 | return; | |
782 | ||
d3b542fc SK |
783 | /* Initialize this to undefined indicating no generic MIPI support */ |
784 | dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; | |
785 | ||
786 | /* Block #40 is already parsed and panel_fixed_mode is | |
787 | * stored in dev_priv->lfp_lvds_vbt_mode | |
788 | * resuse this when needed | |
789 | */ | |
d17c5443 | 790 | |
d3b542fc SK |
791 | /* Parse #52 for panel index used from panel_type already |
792 | * parsed | |
793 | */ | |
794 | start = find_section(bdb, BDB_MIPI_CONFIG); | |
795 | if (!start) { | |
796 | DRM_DEBUG_KMS("No MIPI config BDB found"); | |
d17c5443 SK |
797 | return; |
798 | } | |
799 | ||
d3b542fc SK |
800 | DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n", |
801 | panel_type); | |
802 | ||
803 | /* | |
804 | * get hold of the correct configuration block and pps data as per | |
805 | * the panel_type as index | |
806 | */ | |
807 | config = &start->config[panel_type]; | |
808 | pps = &start->pps[panel_type]; | |
809 | ||
810 | /* store as of now full data. Trim when we realise all is not needed */ | |
811 | dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL); | |
812 | if (!dev_priv->vbt.dsi.config) | |
813 | return; | |
814 | ||
815 | dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL); | |
816 | if (!dev_priv->vbt.dsi.pps) { | |
817 | kfree(dev_priv->vbt.dsi.config); | |
818 | return; | |
819 | } | |
820 | ||
821 | /* We have mandatory mipi config blocks. Initialize as generic panel */ | |
ea9a6baf | 822 | dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID; |
d3b542fc SK |
823 | |
824 | /* Check if we have sequence block as well */ | |
825 | sequence = find_section(bdb, BDB_MIPI_SEQUENCE); | |
826 | if (!sequence) { | |
827 | DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n"); | |
828 | return; | |
829 | } | |
830 | ||
cd67d226 JN |
831 | /* Fail gracefully for forward incompatible sequence block. */ |
832 | if (sequence->version >= 3) { | |
833 | DRM_ERROR("Unable to parse MIPI Sequence Block v3+\n"); | |
834 | return; | |
835 | } | |
836 | ||
d3b542fc SK |
837 | DRM_DEBUG_DRIVER("Found MIPI sequence block\n"); |
838 | ||
839 | block_size = get_blocksize(sequence); | |
840 | ||
841 | /* | |
842 | * parse the sequence block for individual sequences | |
843 | */ | |
844 | dev_priv->vbt.dsi.seq_version = sequence->version; | |
845 | ||
846 | seq_data = &sequence->data[0]; | |
847 | ||
848 | /* | |
849 | * sequence block is variable length and hence we need to parse and | |
850 | * get the sequence data for specific panel id | |
851 | */ | |
852 | for (i = 0; i < MAX_MIPI_CONFIGURATIONS; i++) { | |
853 | panel_id = *seq_data; | |
854 | seq_size = *((u16 *) (seq_data + 1)); | |
855 | if (panel_id == panel_type) | |
856 | break; | |
857 | ||
858 | /* skip the sequence including seq header of 3 bytes */ | |
859 | seq_data = seq_data + 3 + seq_size; | |
860 | if ((seq_data - &sequence->data[0]) > block_size) { | |
861 | DRM_ERROR("Sequence start is beyond sequence block size, corrupted sequence block\n"); | |
862 | return; | |
863 | } | |
864 | } | |
865 | ||
866 | if (i == MAX_MIPI_CONFIGURATIONS) { | |
867 | DRM_ERROR("Sequence block detected but no valid configuration\n"); | |
868 | return; | |
869 | } | |
870 | ||
871 | /* check if found sequence is completely within the sequence block | |
872 | * just being paranoid */ | |
873 | if (seq_size > block_size) { | |
874 | DRM_ERROR("Corrupted sequence/size, bailing out\n"); | |
875 | return; | |
876 | } | |
877 | ||
878 | /* skip the panel id(1 byte) and seq size(2 bytes) */ | |
879 | dev_priv->vbt.dsi.data = kmemdup(seq_data + 3, seq_size, GFP_KERNEL); | |
880 | if (!dev_priv->vbt.dsi.data) | |
881 | return; | |
882 | ||
883 | /* | |
884 | * loop into the sequence data and split into multiple sequneces | |
885 | * There are only 5 types of sequences as of now | |
886 | */ | |
887 | data = dev_priv->vbt.dsi.data; | |
888 | dev_priv->vbt.dsi.size = seq_size; | |
889 | ||
890 | /* two consecutive 0x00 indicate end of all sequences */ | |
891 | while (1) { | |
892 | int seq_id = *data; | |
893 | if (MIPI_SEQ_MAX > seq_id && seq_id > MIPI_SEQ_UNDEFINED) { | |
894 | dev_priv->vbt.dsi.sequence[seq_id] = data; | |
895 | DRM_DEBUG_DRIVER("Found mipi sequence - %d\n", seq_id); | |
896 | } else { | |
897 | DRM_ERROR("undefined sequence\n"); | |
898 | goto err; | |
899 | } | |
900 | ||
901 | /* partial parsing to skip elements */ | |
902 | data = goto_next_sequence(data, &seq_size); | |
903 | ||
904 | if (data == NULL) { | |
905 | DRM_ERROR("Sequence elements going beyond block itself. Sequence block parsing failed\n"); | |
906 | goto err; | |
907 | } | |
908 | ||
909 | if (*data == 0) | |
910 | break; /* end of sequence reached */ | |
911 | } | |
912 | ||
913 | DRM_DEBUG_DRIVER("MIPI related vbt parsing complete\n"); | |
914 | return; | |
915 | err: | |
916 | kfree(dev_priv->vbt.dsi.data); | |
917 | dev_priv->vbt.dsi.data = NULL; | |
918 | ||
919 | /* error during parsing so set all pointers to null | |
920 | * because of partial parsing */ | |
ed3b6679 | 921 | memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence)); |
d17c5443 SK |
922 | } |
923 | ||
75067dde AK |
924 | static u8 translate_iboost(u8 val) |
925 | { | |
926 | static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */ | |
927 | ||
928 | if (val >= ARRAY_SIZE(mapping)) { | |
929 | DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val); | |
930 | return 0; | |
931 | } | |
932 | return mapping[val]; | |
933 | } | |
934 | ||
6acab15a | 935 | static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, |
dcb58a40 | 936 | const struct bdb_header *bdb) |
6acab15a PZ |
937 | { |
938 | union child_device_config *it, *child = NULL; | |
939 | struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; | |
940 | uint8_t hdmi_level_shift; | |
941 | int i, j; | |
554d6af5 | 942 | bool is_dvi, is_hdmi, is_dp, is_edp, is_crt; |
11c1b657 | 943 | uint8_t aux_channel, ddc_pin; |
6acab15a PZ |
944 | /* Each DDI port can have more than one value on the "DVO Port" field, |
945 | * so look for all the possible values for each port and abort if more | |
946 | * than one is found. */ | |
2800e4c2 RV |
947 | int dvo_ports[][3] = { |
948 | {DVO_PORT_HDMIA, DVO_PORT_DPA, -1}, | |
949 | {DVO_PORT_HDMIB, DVO_PORT_DPB, -1}, | |
950 | {DVO_PORT_HDMIC, DVO_PORT_DPC, -1}, | |
951 | {DVO_PORT_HDMID, DVO_PORT_DPD, -1}, | |
952 | {DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE}, | |
6acab15a PZ |
953 | }; |
954 | ||
955 | /* Find the child device to use, abort if more than one found. */ | |
956 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
957 | it = dev_priv->vbt.child_dev + i; | |
958 | ||
2800e4c2 | 959 | for (j = 0; j < 3; j++) { |
6acab15a PZ |
960 | if (dvo_ports[port][j] == -1) |
961 | break; | |
962 | ||
963 | if (it->common.dvo_port == dvo_ports[port][j]) { | |
964 | if (child) { | |
965 | DRM_DEBUG_KMS("More than one child device for port %c in VBT.\n", | |
966 | port_name(port)); | |
967 | return; | |
968 | } | |
969 | child = it; | |
970 | } | |
971 | } | |
972 | } | |
973 | if (!child) | |
974 | return; | |
975 | ||
6bf19e7c | 976 | aux_channel = child->raw[25]; |
11c1b657 | 977 | ddc_pin = child->common.ddc_pin; |
6bf19e7c | 978 | |
78eb06c3 VS |
979 | is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; |
980 | is_dp = child->common.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; | |
981 | is_crt = child->common.device_type & DEVICE_TYPE_ANALOG_OUTPUT; | |
982 | is_hdmi = is_dvi && (child->common.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0; | |
983 | is_edp = is_dp && (child->common.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR); | |
554d6af5 | 984 | |
311a2094 PZ |
985 | info->supports_dvi = is_dvi; |
986 | info->supports_hdmi = is_hdmi; | |
987 | info->supports_dp = is_dp; | |
988 | ||
554d6af5 PZ |
989 | DRM_DEBUG_KMS("Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d\n", |
990 | port_name(port), is_dp, is_hdmi, is_dvi, is_edp, is_crt); | |
991 | ||
992 | if (is_edp && is_dvi) | |
993 | DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n", | |
994 | port_name(port)); | |
995 | if (is_crt && port != PORT_E) | |
996 | DRM_DEBUG_KMS("Port %c is analog\n", port_name(port)); | |
997 | if (is_crt && (is_dvi || is_dp)) | |
998 | DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n", | |
999 | port_name(port)); | |
1000 | if (is_dvi && (port == PORT_A || port == PORT_E)) | |
9b13494c | 1001 | DRM_DEBUG_KMS("Port %c is TMDS compatible\n", port_name(port)); |
554d6af5 PZ |
1002 | if (!is_dvi && !is_dp && !is_crt) |
1003 | DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n", | |
1004 | port_name(port)); | |
1005 | if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E)) | |
1006 | DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port)); | |
6bf19e7c PZ |
1007 | |
1008 | if (is_dvi) { | |
11c1b657 XZ |
1009 | if (port == PORT_E) { |
1010 | info->alternate_ddc_pin = ddc_pin; | |
1011 | /* if DDIE share ddc pin with other port, then | |
1012 | * dvi/hdmi couldn't exist on the shared port. | |
1013 | * Otherwise they share the same ddc bin and system | |
1014 | * couldn't communicate with them seperately. */ | |
1015 | if (ddc_pin == DDC_PIN_B) { | |
1016 | dev_priv->vbt.ddi_port_info[PORT_B].supports_dvi = 0; | |
1017 | dev_priv->vbt.ddi_port_info[PORT_B].supports_hdmi = 0; | |
1018 | } else if (ddc_pin == DDC_PIN_C) { | |
1019 | dev_priv->vbt.ddi_port_info[PORT_C].supports_dvi = 0; | |
1020 | dev_priv->vbt.ddi_port_info[PORT_C].supports_hdmi = 0; | |
1021 | } else if (ddc_pin == DDC_PIN_D) { | |
1022 | dev_priv->vbt.ddi_port_info[PORT_D].supports_dvi = 0; | |
1023 | dev_priv->vbt.ddi_port_info[PORT_D].supports_hdmi = 0; | |
1024 | } | |
1025 | } else if (ddc_pin == DDC_PIN_B && port != PORT_B) | |
6bf19e7c | 1026 | DRM_DEBUG_KMS("Unexpected DDC pin for port B\n"); |
11c1b657 | 1027 | else if (ddc_pin == DDC_PIN_C && port != PORT_C) |
6bf19e7c | 1028 | DRM_DEBUG_KMS("Unexpected DDC pin for port C\n"); |
11c1b657 | 1029 | else if (ddc_pin == DDC_PIN_D && port != PORT_D) |
6bf19e7c PZ |
1030 | DRM_DEBUG_KMS("Unexpected DDC pin for port D\n"); |
1031 | } | |
1032 | ||
1033 | if (is_dp) { | |
500ea70d RV |
1034 | if (port == PORT_E) { |
1035 | info->alternate_aux_channel = aux_channel; | |
1036 | /* if DDIE share aux channel with other port, then | |
1037 | * DP couldn't exist on the shared port. Otherwise | |
1038 | * they share the same aux channel and system | |
1039 | * couldn't communicate with them seperately. */ | |
1040 | if (aux_channel == DP_AUX_A) | |
1041 | dev_priv->vbt.ddi_port_info[PORT_A].supports_dp = 0; | |
1042 | else if (aux_channel == DP_AUX_B) | |
1043 | dev_priv->vbt.ddi_port_info[PORT_B].supports_dp = 0; | |
1044 | else if (aux_channel == DP_AUX_C) | |
1045 | dev_priv->vbt.ddi_port_info[PORT_C].supports_dp = 0; | |
1046 | else if (aux_channel == DP_AUX_D) | |
1047 | dev_priv->vbt.ddi_port_info[PORT_D].supports_dp = 0; | |
1048 | } | |
1049 | else if (aux_channel == DP_AUX_A && port != PORT_A) | |
6bf19e7c | 1050 | DRM_DEBUG_KMS("Unexpected AUX channel for port A\n"); |
500ea70d | 1051 | else if (aux_channel == DP_AUX_B && port != PORT_B) |
6bf19e7c | 1052 | DRM_DEBUG_KMS("Unexpected AUX channel for port B\n"); |
500ea70d | 1053 | else if (aux_channel == DP_AUX_C && port != PORT_C) |
6bf19e7c | 1054 | DRM_DEBUG_KMS("Unexpected AUX channel for port C\n"); |
500ea70d | 1055 | else if (aux_channel == DP_AUX_D && port != PORT_D) |
6bf19e7c PZ |
1056 | DRM_DEBUG_KMS("Unexpected AUX channel for port D\n"); |
1057 | } | |
1058 | ||
6acab15a PZ |
1059 | if (bdb->version >= 158) { |
1060 | /* The VBT HDMI level shift values match the table we have. */ | |
1061 | hdmi_level_shift = child->raw[7] & 0xF; | |
ce4dd49e DL |
1062 | DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n", |
1063 | port_name(port), | |
1064 | hdmi_level_shift); | |
1065 | info->hdmi_level_shift = hdmi_level_shift; | |
6acab15a | 1066 | } |
75067dde AK |
1067 | |
1068 | /* Parse the I_boost config for SKL and above */ | |
1069 | if (bdb->version >= 196 && (child->common.flags_1 & IBOOST_ENABLE)) { | |
1070 | info->dp_boost_level = translate_iboost(child->common.iboost_level & 0xF); | |
1071 | DRM_DEBUG_KMS("VBT (e)DP boost level for port %c: %d\n", | |
1072 | port_name(port), info->dp_boost_level); | |
1073 | info->hdmi_boost_level = translate_iboost(child->common.iboost_level >> 4); | |
1074 | DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n", | |
1075 | port_name(port), info->hdmi_boost_level); | |
1076 | } | |
6acab15a PZ |
1077 | } |
1078 | ||
1079 | static void parse_ddi_ports(struct drm_i915_private *dev_priv, | |
dcb58a40 | 1080 | const struct bdb_header *bdb) |
6acab15a | 1081 | { |
6acab15a PZ |
1082 | enum port port; |
1083 | ||
98f3a1dc | 1084 | if (!HAS_DDI(dev_priv)) |
6acab15a PZ |
1085 | return; |
1086 | ||
1087 | if (!dev_priv->vbt.child_dev_num) | |
1088 | return; | |
1089 | ||
1090 | if (bdb->version < 155) | |
1091 | return; | |
1092 | ||
1093 | for (port = PORT_A; port < I915_MAX_PORTS; port++) | |
1094 | parse_ddi_port(dev_priv, port, bdb); | |
1095 | } | |
1096 | ||
6363ee6f ZY |
1097 | static void |
1098 | parse_device_mapping(struct drm_i915_private *dev_priv, | |
dcb58a40 | 1099 | const struct bdb_header *bdb) |
6363ee6f | 1100 | { |
e8ef3b4c JN |
1101 | const struct bdb_general_definitions *p_defs; |
1102 | const union child_device_config *p_child; | |
1103 | union child_device_config *child_dev_ptr; | |
6363ee6f | 1104 | int i, child_device_num, count; |
e2d6cf7f DW |
1105 | u8 expected_size; |
1106 | u16 block_size; | |
6363ee6f ZY |
1107 | |
1108 | p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); | |
1109 | if (!p_defs) { | |
44834a67 | 1110 | DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n"); |
6363ee6f ZY |
1111 | return; |
1112 | } | |
e2d6cf7f DW |
1113 | if (bdb->version < 195) { |
1114 | expected_size = sizeof(struct old_child_dev_config); | |
1115 | } else if (bdb->version == 195) { | |
1116 | expected_size = 37; | |
1117 | } else if (bdb->version <= 197) { | |
1118 | expected_size = 38; | |
1119 | } else { | |
1120 | expected_size = 38; | |
1121 | BUILD_BUG_ON(sizeof(*p_child) < 38); | |
1122 | DRM_DEBUG_DRIVER("Expected child device config size for VBT version %u not known; assuming %u\n", | |
1123 | bdb->version, expected_size); | |
1124 | } | |
1125 | ||
1126 | /* The legacy sized child device config is the minimum we need. */ | |
1127 | if (p_defs->child_dev_size < sizeof(struct old_child_dev_config)) { | |
1128 | DRM_ERROR("Child device config size %u is too small.\n", | |
1129 | p_defs->child_dev_size); | |
6363ee6f ZY |
1130 | return; |
1131 | } | |
e2d6cf7f DW |
1132 | |
1133 | /* Flag an error for unexpected size, but continue anyway. */ | |
1134 | if (p_defs->child_dev_size != expected_size) | |
1135 | DRM_ERROR("Unexpected child device config size %u (expected %u for VBT version %u)\n", | |
1136 | p_defs->child_dev_size, expected_size, bdb->version); | |
1137 | ||
6363ee6f ZY |
1138 | /* get the block size of general definitions */ |
1139 | block_size = get_blocksize(p_defs); | |
1140 | /* get the number of child device */ | |
1141 | child_device_num = (block_size - sizeof(*p_defs)) / | |
90e4f159 | 1142 | p_defs->child_dev_size; |
6363ee6f ZY |
1143 | count = 0; |
1144 | /* get the number of child device that is present */ | |
1145 | for (i = 0; i < child_device_num; i++) { | |
90e4f159 | 1146 | p_child = child_device_ptr(p_defs, i); |
768f69c9 | 1147 | if (!p_child->common.device_type) { |
6363ee6f ZY |
1148 | /* skip the device block if device type is invalid */ |
1149 | continue; | |
1150 | } | |
1151 | count++; | |
1152 | } | |
1153 | if (!count) { | |
0206e353 | 1154 | DRM_DEBUG_KMS("no child dev is parsed from VBT\n"); |
6363ee6f ZY |
1155 | return; |
1156 | } | |
41aa3448 RV |
1157 | dev_priv->vbt.child_dev = kcalloc(count, sizeof(*p_child), GFP_KERNEL); |
1158 | if (!dev_priv->vbt.child_dev) { | |
6363ee6f ZY |
1159 | DRM_DEBUG_KMS("No memory space for child device\n"); |
1160 | return; | |
1161 | } | |
1162 | ||
41aa3448 | 1163 | dev_priv->vbt.child_dev_num = count; |
6363ee6f ZY |
1164 | count = 0; |
1165 | for (i = 0; i < child_device_num; i++) { | |
90e4f159 | 1166 | p_child = child_device_ptr(p_defs, i); |
768f69c9 | 1167 | if (!p_child->common.device_type) { |
6363ee6f ZY |
1168 | /* skip the device block if device type is invalid */ |
1169 | continue; | |
1170 | } | |
3e6bd011 SK |
1171 | |
1172 | if (p_child->common.dvo_port >= DVO_PORT_MIPIA | |
1173 | && p_child->common.dvo_port <= DVO_PORT_MIPID | |
1174 | &&p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT) { | |
1175 | DRM_DEBUG_KMS("Found MIPI as LFP\n"); | |
1176 | dev_priv->vbt.has_mipi = 1; | |
1177 | dev_priv->vbt.dsi.port = p_child->common.dvo_port; | |
1178 | } | |
1179 | ||
41aa3448 | 1180 | child_dev_ptr = dev_priv->vbt.child_dev + count; |
6363ee6f | 1181 | count++; |
e2d6cf7f DW |
1182 | |
1183 | /* | |
1184 | * Copy as much as we know (sizeof) and is available | |
1185 | * (child_dev_size) of the child device. Accessing the data must | |
1186 | * depend on VBT version. | |
1187 | */ | |
1188 | memcpy(child_dev_ptr, p_child, | |
1189 | min_t(size_t, p_defs->child_dev_size, sizeof(*p_child))); | |
6363ee6f ZY |
1190 | } |
1191 | return; | |
1192 | } | |
44834a67 | 1193 | |
6a04002b SQ |
1194 | static void |
1195 | init_vbt_defaults(struct drm_i915_private *dev_priv) | |
1196 | { | |
6acab15a | 1197 | enum port port; |
9a4114ff | 1198 | |
988c7015 | 1199 | dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; |
6a04002b | 1200 | |
56c4b63a JN |
1201 | /* Default to having backlight */ |
1202 | dev_priv->vbt.backlight.present = true; | |
1203 | ||
6a04002b | 1204 | /* LFP panel data */ |
41aa3448 RV |
1205 | dev_priv->vbt.lvds_dither = 1; |
1206 | dev_priv->vbt.lvds_vbt = 0; | |
6a04002b SQ |
1207 | |
1208 | /* SDVO panel data */ | |
41aa3448 | 1209 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; |
6a04002b SQ |
1210 | |
1211 | /* general features */ | |
41aa3448 RV |
1212 | dev_priv->vbt.int_tv_support = 1; |
1213 | dev_priv->vbt.int_crt_support = 1; | |
9a4114ff BF |
1214 | |
1215 | /* Default to using SSC */ | |
41aa3448 | 1216 | dev_priv->vbt.lvds_use_ssc = 1; |
f69e5156 DL |
1217 | /* |
1218 | * Core/SandyBridge/IvyBridge use alternative (120MHz) reference | |
1219 | * clock for LVDS. | |
1220 | */ | |
98f3a1dc JN |
1221 | dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev_priv, |
1222 | !HAS_PCH_SPLIT(dev_priv)); | |
e91e941b | 1223 | DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq); |
6acab15a PZ |
1224 | |
1225 | for (port = PORT_A; port < I915_MAX_PORTS; port++) { | |
311a2094 PZ |
1226 | struct ddi_vbt_port_info *info = |
1227 | &dev_priv->vbt.ddi_port_info[port]; | |
1228 | ||
ce4dd49e | 1229 | info->hdmi_level_shift = HDMI_LEVEL_SHIFT_UNKNOWN; |
311a2094 PZ |
1230 | |
1231 | info->supports_dvi = (port != PORT_A && port != PORT_E); | |
1232 | info->supports_hdmi = info->supports_dvi; | |
1233 | info->supports_dp = (port != PORT_E); | |
6acab15a | 1234 | } |
6a04002b SQ |
1235 | } |
1236 | ||
caf37fa4 JN |
1237 | static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt) |
1238 | { | |
1239 | const void *_vbt = vbt; | |
1240 | ||
1241 | return _vbt + vbt->bdb_offset; | |
1242 | } | |
1243 | ||
f0067a31 JN |
1244 | /** |
1245 | * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT | |
1246 | * @buf: pointer to a buffer to validate | |
1247 | * @size: size of the buffer | |
1248 | * | |
1249 | * Returns true on valid VBT. | |
1250 | */ | |
1251 | bool intel_bios_is_valid_vbt(const void *buf, size_t size) | |
3dd4e846 | 1252 | { |
f0067a31 | 1253 | const struct vbt_header *vbt = buf; |
dcb58a40 | 1254 | const struct bdb_header *bdb; |
3dd4e846 | 1255 | |
caf37fa4 | 1256 | if (!vbt) |
f0067a31 | 1257 | return false; |
caf37fa4 | 1258 | |
f0067a31 | 1259 | if (sizeof(struct vbt_header) > size) { |
3dd4e846 | 1260 | DRM_DEBUG_DRIVER("VBT header incomplete\n"); |
f0067a31 | 1261 | return false; |
3dd4e846 CW |
1262 | } |
1263 | ||
1264 | if (memcmp(vbt->signature, "$VBT", 4)) { | |
1265 | DRM_DEBUG_DRIVER("VBT invalid signature\n"); | |
f0067a31 | 1266 | return false; |
3dd4e846 CW |
1267 | } |
1268 | ||
f0067a31 | 1269 | if (vbt->bdb_offset + sizeof(struct bdb_header) > size) { |
3dd4e846 | 1270 | DRM_DEBUG_DRIVER("BDB header incomplete\n"); |
f0067a31 | 1271 | return false; |
3dd4e846 CW |
1272 | } |
1273 | ||
caf37fa4 | 1274 | bdb = get_bdb_header(vbt); |
f0067a31 | 1275 | if (vbt->bdb_offset + bdb->bdb_size > size) { |
3dd4e846 | 1276 | DRM_DEBUG_DRIVER("BDB incomplete\n"); |
f0067a31 | 1277 | return false; |
3dd4e846 CW |
1278 | } |
1279 | ||
caf37fa4 | 1280 | return vbt; |
3dd4e846 CW |
1281 | } |
1282 | ||
caf37fa4 | 1283 | static const struct vbt_header *find_vbt(void __iomem *bios, size_t size) |
b34a991a | 1284 | { |
b34a991a JN |
1285 | size_t i; |
1286 | ||
1287 | /* Scour memory looking for the VBT signature. */ | |
1288 | for (i = 0; i + 4 < size; i++) { | |
f0067a31 | 1289 | void *vbt; |
115719fc | 1290 | |
f0067a31 JN |
1291 | if (ioread32(bios + i) != *((const u32 *) "$VBT")) |
1292 | continue; | |
1293 | ||
1294 | /* | |
1295 | * This is the one place where we explicitly discard the address | |
1296 | * space (__iomem) of the BIOS/VBT. | |
1297 | */ | |
1298 | vbt = (void __force *) bios + i; | |
1299 | if (intel_bios_is_valid_vbt(vbt, size - i)) | |
1300 | return vbt; | |
1301 | ||
1302 | break; | |
b34a991a JN |
1303 | } |
1304 | ||
f0067a31 | 1305 | return NULL; |
b34a991a JN |
1306 | } |
1307 | ||
79e53945 | 1308 | /** |
8b8e1a89 | 1309 | * intel_bios_init - find VBT and initialize settings from the BIOS |
dd97950a | 1310 | * @dev_priv: i915 device instance |
79e53945 JB |
1311 | * |
1312 | * Loads the Video BIOS and checks that the VBT exists. Sets scratch registers | |
1313 | * to appropriate values. | |
1314 | * | |
79e53945 JB |
1315 | * Returns 0 on success, nonzero on failure. |
1316 | */ | |
0317c6ce | 1317 | int |
98f3a1dc | 1318 | intel_bios_init(struct drm_i915_private *dev_priv) |
79e53945 | 1319 | { |
98f3a1dc | 1320 | struct pci_dev *pdev = dev_priv->dev->pdev; |
f0067a31 | 1321 | const struct vbt_header *vbt = dev_priv->opregion.vbt; |
caf37fa4 | 1322 | const struct bdb_header *bdb; |
44834a67 CW |
1323 | u8 __iomem *bios = NULL; |
1324 | ||
98f3a1dc | 1325 | if (HAS_PCH_NOP(dev_priv)) |
ab5c608b BW |
1326 | return -ENODEV; |
1327 | ||
6a04002b | 1328 | init_vbt_defaults(dev_priv); |
f899fc64 | 1329 | |
f0067a31 | 1330 | if (!vbt) { |
b34a991a | 1331 | size_t size; |
79e53945 | 1332 | |
44834a67 CW |
1333 | bios = pci_map_rom(pdev, &size); |
1334 | if (!bios) | |
1335 | return -1; | |
1336 | ||
caf37fa4 JN |
1337 | vbt = find_vbt(bios, size); |
1338 | if (!vbt) { | |
44834a67 CW |
1339 | pci_unmap_rom(pdev, bios); |
1340 | return -1; | |
1341 | } | |
e2051c44 JN |
1342 | |
1343 | DRM_DEBUG_KMS("Found valid VBT in PCI ROM\n"); | |
44834a67 | 1344 | } |
79e53945 | 1345 | |
caf37fa4 JN |
1346 | bdb = get_bdb_header(vbt); |
1347 | ||
3556dd40 JN |
1348 | DRM_DEBUG_KMS("VBT signature \"%.*s\", BDB version %d\n", |
1349 | (int)sizeof(vbt->signature), vbt->signature, bdb->version); | |
e2051c44 | 1350 | |
79e53945 JB |
1351 | /* Grab useful general definitions */ |
1352 | parse_general_features(dev_priv, bdb); | |
db545019 | 1353 | parse_general_definitions(dev_priv, bdb); |
88631706 | 1354 | parse_lfp_panel_data(dev_priv, bdb); |
f00076d2 | 1355 | parse_lfp_backlight(dev_priv, bdb); |
88631706 | 1356 | parse_sdvo_panel_data(dev_priv, bdb); |
9b9d172d | 1357 | parse_sdvo_device_mapping(dev_priv, bdb); |
6363ee6f | 1358 | parse_device_mapping(dev_priv, bdb); |
32f9d658 | 1359 | parse_driver_features(dev_priv, bdb); |
500a8cc4 | 1360 | parse_edp(dev_priv, bdb); |
bfd7ebda | 1361 | parse_psr(dev_priv, bdb); |
d17c5443 | 1362 | parse_mipi(dev_priv, bdb); |
6acab15a | 1363 | parse_ddi_ports(dev_priv, bdb); |
32f9d658 | 1364 | |
44834a67 CW |
1365 | if (bios) |
1366 | pci_unmap_rom(pdev, bios); | |
79e53945 JB |
1367 | |
1368 | return 0; | |
1369 | } |