Commit | Line | Data |
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79e53945 | 1 | /* |
39507259 | 2 | * Copyright © 2006 Intel Corporation |
79e53945 JB |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
b30581a4 | 27 | |
9f0e7ff4 | 28 | #include <drm/drm_dp_helper.h> |
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
79e53945 | 31 | #include "i915_drv.h" |
72341af4 JN |
32 | |
33 | #define _INTEL_BIOS_PRIVATE | |
34 | #include "intel_vbt_defs.h" | |
79e53945 | 35 | |
dd97950a JN |
36 | /** |
37 | * DOC: Video BIOS Table (VBT) | |
38 | * | |
39 | * The Video BIOS Table, or VBT, provides platform and board specific | |
40 | * configuration information to the driver that is not discoverable or available | |
41 | * through other means. The configuration is mostly related to display | |
42 | * hardware. The VBT is available via the ACPI OpRegion or, on older systems, in | |
43 | * the PCI ROM. | |
44 | * | |
45 | * The VBT consists of a VBT Header (defined as &struct vbt_header), a BDB | |
46 | * Header (&struct bdb_header), and a number of BIOS Data Blocks (BDB) that | |
47 | * contain the actual configuration information. The VBT Header, and thus the | |
48 | * VBT, begins with "$VBT" signature. The VBT Header contains the offset of the | |
49 | * BDB Header. The data blocks are concatenated after the BDB Header. The data | |
50 | * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of | |
51 | * data. (Block 53, the MIPI Sequence Block is an exception.) | |
52 | * | |
53 | * The driver parses the VBT during load. The relevant information is stored in | |
54 | * driver private data for ease of use, and the actual VBT is not read after | |
55 | * that. | |
56 | */ | |
57 | ||
9b9d172d | 58 | #define SLAVE_ADDR1 0x70 |
59 | #define SLAVE_ADDR2 0x72 | |
79e53945 | 60 | |
08c0888b JN |
61 | /* Get BDB block size given a pointer to Block ID. */ |
62 | static u32 _get_blocksize(const u8 *block_base) | |
63 | { | |
64 | /* The MIPI Sequence Block v3+ has a separate size field. */ | |
65 | if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3) | |
66 | return *((const u32 *)(block_base + 4)); | |
67 | else | |
68 | return *((const u16 *)(block_base + 1)); | |
69 | } | |
70 | ||
71 | /* Get BDB block size give a pointer to data after Block ID and Block Size. */ | |
72 | static u32 get_blocksize(const void *block_data) | |
73 | { | |
74 | return _get_blocksize(block_data - 3); | |
75 | } | |
76 | ||
e8ef3b4c JN |
77 | static const void * |
78 | find_section(const void *_bdb, int section_id) | |
79e53945 | 79 | { |
e8ef3b4c JN |
80 | const struct bdb_header *bdb = _bdb; |
81 | const u8 *base = _bdb; | |
79e53945 | 82 | int index = 0; |
cd67d226 | 83 | u32 total, current_size; |
79e53945 JB |
84 | u8 current_id; |
85 | ||
86 | /* skip to first section */ | |
87 | index += bdb->header_size; | |
88 | total = bdb->bdb_size; | |
89 | ||
90 | /* walk the sections looking for section_id */ | |
d1f13fd2 | 91 | while (index + 3 < total) { |
79e53945 | 92 | current_id = *(base + index); |
08c0888b JN |
93 | current_size = _get_blocksize(base + index); |
94 | index += 3; | |
cd67d226 | 95 | |
d1f13fd2 CW |
96 | if (index + current_size > total) |
97 | return NULL; | |
98 | ||
79e53945 JB |
99 | if (current_id == section_id) |
100 | return base + index; | |
d1f13fd2 | 101 | |
79e53945 JB |
102 | index += current_size; |
103 | } | |
104 | ||
105 | return NULL; | |
106 | } | |
107 | ||
79e53945 | 108 | static void |
88631706 | 109 | fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode, |
99834ea4 | 110 | const struct lvds_dvo_timing *dvo_timing) |
88631706 ML |
111 | { |
112 | panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) | | |
113 | dvo_timing->hactive_lo; | |
114 | panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay + | |
115 | ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo); | |
116 | panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start + | |
ce2e87b4 VT |
117 | ((dvo_timing->hsync_pulse_width_hi << 8) | |
118 | dvo_timing->hsync_pulse_width_lo); | |
88631706 ML |
119 | panel_fixed_mode->htotal = panel_fixed_mode->hdisplay + |
120 | ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo); | |
121 | ||
122 | panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) | | |
123 | dvo_timing->vactive_lo; | |
124 | panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay + | |
ce2e87b4 | 125 | ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo); |
88631706 | 126 | panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start + |
ce2e87b4 VT |
127 | ((dvo_timing->vsync_pulse_width_hi << 4) | |
128 | dvo_timing->vsync_pulse_width_lo); | |
88631706 ML |
129 | panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay + |
130 | ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo); | |
131 | panel_fixed_mode->clock = dvo_timing->clock * 10; | |
132 | panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; | |
133 | ||
9bc35499 AJ |
134 | if (dvo_timing->hsync_positive) |
135 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
136 | else | |
137 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
138 | ||
139 | if (dvo_timing->vsync_positive) | |
140 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
141 | else | |
142 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
143 | ||
df457245 VS |
144 | panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) | |
145 | dvo_timing->himage_lo; | |
146 | panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) | | |
147 | dvo_timing->vimage_lo; | |
148 | ||
88631706 ML |
149 | /* Some VBTs have bogus h/vtotal values */ |
150 | if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) | |
151 | panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1; | |
152 | if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) | |
153 | panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1; | |
154 | ||
155 | drm_mode_set_name(panel_fixed_mode); | |
156 | } | |
157 | ||
99834ea4 CW |
158 | static const struct lvds_dvo_timing * |
159 | get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data, | |
160 | const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs, | |
161 | int index) | |
162 | { | |
163 | /* | |
164 | * the size of fp_timing varies on the different platform. | |
165 | * So calculate the DVO timing relative offset in LVDS data | |
166 | * entry to get the DVO timing entry | |
167 | */ | |
168 | ||
169 | int lfp_data_size = | |
170 | lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset - | |
171 | lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset; | |
172 | int dvo_timing_offset = | |
173 | lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset - | |
174 | lvds_lfp_data_ptrs->ptr[0].fp_timing_offset; | |
175 | char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index; | |
176 | ||
177 | return (struct lvds_dvo_timing *)(entry + dvo_timing_offset); | |
178 | } | |
179 | ||
b0354385 TI |
180 | /* get lvds_fp_timing entry |
181 | * this function may return NULL if the corresponding entry is invalid | |
182 | */ | |
183 | static const struct lvds_fp_timing * | |
184 | get_lvds_fp_timing(const struct bdb_header *bdb, | |
185 | const struct bdb_lvds_lfp_data *data, | |
186 | const struct bdb_lvds_lfp_data_ptrs *ptrs, | |
187 | int index) | |
188 | { | |
189 | size_t data_ofs = (const u8 *)data - (const u8 *)bdb; | |
190 | u16 data_size = ((const u16 *)data)[-1]; /* stored in header */ | |
191 | size_t ofs; | |
192 | ||
193 | if (index >= ARRAY_SIZE(ptrs->ptr)) | |
194 | return NULL; | |
195 | ofs = ptrs->ptr[index].fp_timing_offset; | |
196 | if (ofs < data_ofs || | |
197 | ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size) | |
198 | return NULL; | |
199 | return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs); | |
200 | } | |
201 | ||
88631706 ML |
202 | /* Try to find integrated panel data */ |
203 | static void | |
204 | parse_lfp_panel_data(struct drm_i915_private *dev_priv, | |
dcb58a40 | 205 | const struct bdb_header *bdb) |
79e53945 | 206 | { |
99834ea4 CW |
207 | const struct bdb_lvds_options *lvds_options; |
208 | const struct bdb_lvds_lfp_data *lvds_lfp_data; | |
209 | const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs; | |
210 | const struct lvds_dvo_timing *panel_dvo_timing; | |
b0354385 | 211 | const struct lvds_fp_timing *fp_timing; |
79e53945 | 212 | struct drm_display_mode *panel_fixed_mode; |
3e845c7a | 213 | int panel_type; |
c329a4ec | 214 | int drrs_mode; |
a0562819 | 215 | int ret; |
79e53945 | 216 | |
79e53945 JB |
217 | lvds_options = find_section(bdb, BDB_LVDS_OPTIONS); |
218 | if (!lvds_options) | |
219 | return; | |
220 | ||
41aa3448 | 221 | dev_priv->vbt.lvds_dither = lvds_options->pixel_dither; |
a0562819 | 222 | |
6f9f4b7a | 223 | ret = intel_opregion_get_panel_type(dev_priv); |
a0562819 VS |
224 | if (ret >= 0) { |
225 | WARN_ON(ret > 0xf); | |
226 | panel_type = ret; | |
227 | DRM_DEBUG_KMS("Panel type: %d (OpRegion)\n", panel_type); | |
228 | } else { | |
229 | if (lvds_options->panel_type > 0xf) { | |
230 | DRM_DEBUG_KMS("Invalid VBT panel type 0x%x\n", | |
231 | lvds_options->panel_type); | |
232 | return; | |
233 | } | |
234 | panel_type = lvds_options->panel_type; | |
235 | DRM_DEBUG_KMS("Panel type: %d (VBT)\n", panel_type); | |
eeeebea6 | 236 | } |
6a04002b | 237 | |
3e845c7a | 238 | dev_priv->vbt.panel_type = panel_type; |
79e53945 | 239 | |
83a7280e PB |
240 | drrs_mode = (lvds_options->dps_panel_type_bits |
241 | >> (panel_type * 2)) & MODE_MASK; | |
242 | /* | |
243 | * VBT has static DRRS = 0 and seamless DRRS = 2. | |
244 | * The below piece of code is required to adjust vbt.drrs_type | |
245 | * to match the enum drrs_support_type. | |
246 | */ | |
247 | switch (drrs_mode) { | |
248 | case 0: | |
249 | dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT; | |
250 | DRM_DEBUG_KMS("DRRS supported mode is static\n"); | |
251 | break; | |
252 | case 2: | |
253 | dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT; | |
254 | DRM_DEBUG_KMS("DRRS supported mode is seamless\n"); | |
255 | break; | |
256 | default: | |
257 | dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; | |
258 | DRM_DEBUG_KMS("DRRS not supported (VBT input)\n"); | |
259 | break; | |
260 | } | |
261 | ||
79e53945 JB |
262 | lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA); |
263 | if (!lvds_lfp_data) | |
264 | return; | |
265 | ||
1b16de0b JB |
266 | lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS); |
267 | if (!lvds_lfp_data_ptrs) | |
268 | return; | |
269 | ||
99834ea4 CW |
270 | panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data, |
271 | lvds_lfp_data_ptrs, | |
3e845c7a | 272 | panel_type); |
79e53945 | 273 | |
9a298b2a | 274 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
6edc3242 CW |
275 | if (!panel_fixed_mode) |
276 | return; | |
79e53945 | 277 | |
99834ea4 | 278 | fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing); |
79e53945 | 279 | |
41aa3448 | 280 | dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 281 | |
28c97730 | 282 | DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n"); |
88631706 | 283 | drm_mode_debug_printmodeline(panel_fixed_mode); |
37df9673 | 284 | |
b0354385 TI |
285 | fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data, |
286 | lvds_lfp_data_ptrs, | |
3e845c7a | 287 | panel_type); |
b0354385 TI |
288 | if (fp_timing) { |
289 | /* check the resolution, just to be sure */ | |
290 | if (fp_timing->x_res == panel_fixed_mode->hdisplay && | |
291 | fp_timing->y_res == panel_fixed_mode->vdisplay) { | |
41aa3448 | 292 | dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val; |
b0354385 | 293 | DRM_DEBUG_KMS("VBT initial LVDS value %x\n", |
41aa3448 | 294 | dev_priv->vbt.bios_lvds_val); |
b0354385 TI |
295 | } |
296 | } | |
88631706 ML |
297 | } |
298 | ||
f00076d2 | 299 | static void |
dcb58a40 JN |
300 | parse_lfp_backlight(struct drm_i915_private *dev_priv, |
301 | const struct bdb_header *bdb) | |
f00076d2 JN |
302 | { |
303 | const struct bdb_lfp_backlight_data *backlight_data; | |
304 | const struct bdb_lfp_backlight_data_entry *entry; | |
3e845c7a | 305 | int panel_type = dev_priv->vbt.panel_type; |
f00076d2 JN |
306 | |
307 | backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT); | |
308 | if (!backlight_data) | |
309 | return; | |
310 | ||
311 | if (backlight_data->entry_size != sizeof(backlight_data->data[0])) { | |
312 | DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n", | |
313 | backlight_data->entry_size); | |
314 | return; | |
315 | } | |
316 | ||
317 | entry = &backlight_data->data[panel_type]; | |
318 | ||
39fbc9c8 JN |
319 | dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM; |
320 | if (!dev_priv->vbt.backlight.present) { | |
321 | DRM_DEBUG_KMS("PWM backlight not present in VBT (type %u)\n", | |
322 | entry->type); | |
323 | return; | |
324 | } | |
325 | ||
9a41e17d D |
326 | dev_priv->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI; |
327 | if (bdb->version >= 191 && | |
328 | get_blocksize(backlight_data) >= sizeof(*backlight_data)) { | |
329 | const struct bdb_lfp_backlight_control_method *method; | |
330 | ||
331 | method = &backlight_data->backlight_control[panel_type]; | |
332 | dev_priv->vbt.backlight.type = method->type; | |
add03379 | 333 | dev_priv->vbt.backlight.controller = method->controller; |
9a41e17d D |
334 | } |
335 | ||
f00076d2 JN |
336 | dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; |
337 | dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm; | |
1de6068e | 338 | dev_priv->vbt.backlight.min_brightness = entry->min_brightness; |
f00076d2 | 339 | DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, " |
add03379 | 340 | "active %s, min brightness %u, level %u, controller %u\n", |
f00076d2 JN |
341 | dev_priv->vbt.backlight.pwm_freq_hz, |
342 | dev_priv->vbt.backlight.active_low_pwm ? "low" : "high", | |
1de6068e | 343 | dev_priv->vbt.backlight.min_brightness, |
add03379 VS |
344 | backlight_data->level[panel_type], |
345 | dev_priv->vbt.backlight.controller); | |
f00076d2 JN |
346 | } |
347 | ||
88631706 ML |
348 | /* Try to find sdvo panel data */ |
349 | static void | |
350 | parse_sdvo_panel_data(struct drm_i915_private *dev_priv, | |
dcb58a40 | 351 | const struct bdb_header *bdb) |
88631706 | 352 | { |
e8ef3b4c | 353 | const struct lvds_dvo_timing *dvo_timing; |
88631706 | 354 | struct drm_display_mode *panel_fixed_mode; |
5a1e5b6c | 355 | int index; |
79e53945 | 356 | |
4f044a88 | 357 | index = i915_modparams.vbt_sdvo_panel_type; |
c10e408a MF |
358 | if (index == -2) { |
359 | DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n"); | |
360 | return; | |
361 | } | |
362 | ||
5a1e5b6c | 363 | if (index == -1) { |
e8ef3b4c | 364 | const struct bdb_sdvo_lvds_options *sdvo_lvds_options; |
5a1e5b6c CW |
365 | |
366 | sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS); | |
367 | if (!sdvo_lvds_options) | |
368 | return; | |
369 | ||
370 | index = sdvo_lvds_options->panel_type; | |
371 | } | |
88631706 ML |
372 | |
373 | dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS); | |
374 | if (!dvo_timing) | |
375 | return; | |
376 | ||
9a298b2a | 377 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
88631706 ML |
378 | if (!panel_fixed_mode) |
379 | return; | |
380 | ||
5a1e5b6c | 381 | fill_detail_timing_data(panel_fixed_mode, dvo_timing + index); |
88631706 | 382 | |
41aa3448 | 383 | dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 384 | |
5a1e5b6c CW |
385 | DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n"); |
386 | drm_mode_debug_printmodeline(panel_fixed_mode); | |
79e53945 JB |
387 | } |
388 | ||
98f3a1dc | 389 | static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, |
9a4114ff BF |
390 | bool alternate) |
391 | { | |
c56b89f1 | 392 | switch (INTEL_GEN(dev_priv)) { |
9a4114ff | 393 | case 2: |
e91e941b | 394 | return alternate ? 66667 : 48000; |
9a4114ff BF |
395 | case 3: |
396 | case 4: | |
e91e941b | 397 | return alternate ? 100000 : 96000; |
9a4114ff | 398 | default: |
e91e941b | 399 | return alternate ? 100000 : 120000; |
9a4114ff BF |
400 | } |
401 | } | |
402 | ||
79e53945 JB |
403 | static void |
404 | parse_general_features(struct drm_i915_private *dev_priv, | |
dcb58a40 | 405 | const struct bdb_header *bdb) |
79e53945 | 406 | { |
e8ef3b4c | 407 | const struct bdb_general_features *general; |
79e53945 | 408 | |
79e53945 | 409 | general = find_section(bdb, BDB_GENERAL_FEATURES); |
34957e8c JN |
410 | if (!general) |
411 | return; | |
412 | ||
413 | dev_priv->vbt.int_tv_support = general->int_tv_support; | |
414 | /* int_crt_support can't be trusted on earlier platforms */ | |
415 | if (bdb->version >= 155 && | |
416 | (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv))) | |
417 | dev_priv->vbt.int_crt_support = general->int_crt_support; | |
418 | dev_priv->vbt.lvds_use_ssc = general->enable_ssc; | |
419 | dev_priv->vbt.lvds_ssc_freq = | |
420 | intel_bios_ssc_frequency(dev_priv, general->ssc_freq); | |
421 | dev_priv->vbt.display_clock_mode = general->display_clock_mode; | |
422 | dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; | |
423 | DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", | |
424 | dev_priv->vbt.int_tv_support, | |
425 | dev_priv->vbt.int_crt_support, | |
426 | dev_priv->vbt.lvds_use_ssc, | |
427 | dev_priv->vbt.lvds_ssc_freq, | |
428 | dev_priv->vbt.display_clock_mode, | |
429 | dev_priv->vbt.fdi_rx_polarity_inverted); | |
79e53945 JB |
430 | } |
431 | ||
cc998589 | 432 | static const struct child_device_config * |
e192839e | 433 | child_device_ptr(const struct bdb_general_definitions *defs, int i) |
90e4f159 | 434 | { |
e192839e | 435 | return (const void *) &defs->devices[i * defs->child_dev_size]; |
90e4f159 VS |
436 | } |
437 | ||
9b9d172d | 438 | static void |
0ead5f81 | 439 | parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) |
9b9d172d | 440 | { |
e192839e | 441 | struct sdvo_device_mapping *mapping; |
cc998589 | 442 | const struct child_device_config *child; |
0ebdabe6 | 443 | int i, count = 0; |
6cc38aca JN |
444 | |
445 | /* | |
0ebdabe6 JN |
446 | * Only parse SDVO mappings on gens that could have SDVO. This isn't |
447 | * accurate and doesn't have to be, as long as it's not too strict. | |
9b9d172d | 448 | */ |
0ebdabe6 JN |
449 | if (!IS_GEN(dev_priv, 3, 7)) { |
450 | DRM_DEBUG_KMS("Skipping SDVO device mapping\n"); | |
9b9d172d | 451 | return; |
452 | } | |
0ebdabe6 JN |
453 | |
454 | for (i = 0, count = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
455 | child = dev_priv->vbt.child_dev + i; | |
456 | ||
6cc38aca JN |
457 | if (child->slave_addr != SLAVE_ADDR1 && |
458 | child->slave_addr != SLAVE_ADDR2) { | |
9b9d172d | 459 | /* |
460 | * If the slave address is neither 0x70 nor 0x72, | |
461 | * it is not a SDVO device. Skip it. | |
462 | */ | |
463 | continue; | |
464 | } | |
6cc38aca JN |
465 | if (child->dvo_port != DEVICE_PORT_DVOB && |
466 | child->dvo_port != DEVICE_PORT_DVOC) { | |
9b9d172d | 467 | /* skip the incorrect SDVO port */ |
0206e353 | 468 | DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n"); |
9b9d172d | 469 | continue; |
470 | } | |
28c97730 | 471 | DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on" |
6cc38aca JN |
472 | " %s port\n", |
473 | child->slave_addr, | |
474 | (child->dvo_port == DEVICE_PORT_DVOB) ? | |
475 | "SDVOB" : "SDVOC"); | |
e192839e JN |
476 | mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1]; |
477 | if (!mapping->initialized) { | |
478 | mapping->dvo_port = child->dvo_port; | |
479 | mapping->slave_addr = child->slave_addr; | |
480 | mapping->dvo_wiring = child->dvo_wiring; | |
481 | mapping->ddc_pin = child->ddc_pin; | |
482 | mapping->i2c_pin = child->i2c_pin; | |
483 | mapping->initialized = 1; | |
46eb3036 | 484 | DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", |
e192839e JN |
485 | mapping->dvo_port, |
486 | mapping->slave_addr, | |
487 | mapping->dvo_wiring, | |
488 | mapping->ddc_pin, | |
489 | mapping->i2c_pin); | |
9b9d172d | 490 | } else { |
28c97730 | 491 | DRM_DEBUG_KMS("Maybe one SDVO port is shared by " |
9b9d172d | 492 | "two SDVO device.\n"); |
493 | } | |
6cc38aca | 494 | if (child->slave2_addr) { |
9b9d172d | 495 | /* Maybe this is a SDVO device with multiple inputs */ |
496 | /* And the mapping info is not added */ | |
28c97730 ZY |
497 | DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this" |
498 | " is a SDVO device with multiple inputs.\n"); | |
9b9d172d | 499 | } |
500 | count++; | |
501 | } | |
502 | ||
503 | if (!count) { | |
504 | /* No SDVO device info is found */ | |
28c97730 | 505 | DRM_DEBUG_KMS("No SDVO device info is found in VBT\n"); |
9b9d172d | 506 | } |
9b9d172d | 507 | } |
32f9d658 ZW |
508 | |
509 | static void | |
510 | parse_driver_features(struct drm_i915_private *dev_priv, | |
dcb58a40 | 511 | const struct bdb_header *bdb) |
32f9d658 | 512 | { |
e8ef3b4c | 513 | const struct bdb_driver_features *driver; |
32f9d658 | 514 | |
32f9d658 | 515 | driver = find_section(bdb, BDB_DRIVER_FEATURES); |
652c393a JB |
516 | if (!driver) |
517 | return; | |
518 | ||
ca3b3fa3 VS |
519 | if (INTEL_GEN(dev_priv) >= 5) { |
520 | /* | |
521 | * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS | |
522 | * to mean "eDP". The VBT spec doesn't agree with that | |
523 | * interpretation, but real world VBTs seem to. | |
524 | */ | |
525 | if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS) | |
526 | dev_priv->vbt.int_lvds_support = 0; | |
527 | } else { | |
528 | /* | |
529 | * FIXME it's not clear which BDB version has the LVDS config | |
530 | * bits defined. Revision history in the VBT spec says: | |
531 | * "0.92 | Add two definitions for VBT value of LVDS Active | |
532 | * Config (00b and 11b values defined) | 06/13/2005" | |
533 | * but does not the specify the BDB version. | |
534 | * | |
535 | * So far version 134 (on i945gm) is the oldest VBT observed | |
536 | * in the wild with the bits correctly populated. Version | |
537 | * 108 (on i85x) does not have the bits correctly populated. | |
538 | */ | |
539 | if (bdb->version >= 134 && | |
540 | driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS && | |
541 | driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS) | |
542 | dev_priv->vbt.int_lvds_support = 0; | |
543 | } | |
652c393a | 544 | |
83a7280e PB |
545 | DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled); |
546 | /* | |
547 | * If DRRS is not supported, drrs_type has to be set to 0. | |
548 | * This is because, VBT is configured in such a way that | |
549 | * static DRRS is 0 and DRRS not supported is represented by | |
550 | * driver->drrs_enabled=false | |
551 | */ | |
552 | if (!driver->drrs_enabled) | |
553 | dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; | |
2bdd045e | 554 | dev_priv->vbt.psr.enable = driver->psr_enabled; |
32f9d658 ZW |
555 | } |
556 | ||
500a8cc4 | 557 | static void |
dcb58a40 | 558 | parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) |
500a8cc4 | 559 | { |
e8ef3b4c JN |
560 | const struct bdb_edp *edp; |
561 | const struct edp_power_seq *edp_pps; | |
058727ee | 562 | const struct edp_fast_link_params *edp_link_params; |
3e845c7a | 563 | int panel_type = dev_priv->vbt.panel_type; |
500a8cc4 ZW |
564 | |
565 | edp = find_section(bdb, BDB_EDP); | |
5255e2f8 | 566 | if (!edp) |
500a8cc4 | 567 | return; |
500a8cc4 ZW |
568 | |
569 | switch ((edp->color_depth >> (panel_type * 2)) & 3) { | |
570 | case EDP_18BPP: | |
6aa23e65 | 571 | dev_priv->vbt.edp.bpp = 18; |
500a8cc4 ZW |
572 | break; |
573 | case EDP_24BPP: | |
6aa23e65 | 574 | dev_priv->vbt.edp.bpp = 24; |
500a8cc4 ZW |
575 | break; |
576 | case EDP_30BPP: | |
6aa23e65 | 577 | dev_priv->vbt.edp.bpp = 30; |
500a8cc4 ZW |
578 | break; |
579 | } | |
5ceb0f9b | 580 | |
9f0e7ff4 JB |
581 | /* Get the eDP sequencing and link info */ |
582 | edp_pps = &edp->power_seqs[panel_type]; | |
058727ee | 583 | edp_link_params = &edp->fast_link_params[panel_type]; |
5ceb0f9b | 584 | |
6aa23e65 | 585 | dev_priv->vbt.edp.pps = *edp_pps; |
5ceb0f9b | 586 | |
e13e2b2c JN |
587 | switch (edp_link_params->rate) { |
588 | case EDP_RATE_1_62: | |
6aa23e65 | 589 | dev_priv->vbt.edp.rate = DP_LINK_BW_1_62; |
e13e2b2c JN |
590 | break; |
591 | case EDP_RATE_2_7: | |
6aa23e65 | 592 | dev_priv->vbt.edp.rate = DP_LINK_BW_2_7; |
e13e2b2c JN |
593 | break; |
594 | default: | |
595 | DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n", | |
596 | edp_link_params->rate); | |
597 | break; | |
598 | } | |
599 | ||
9f0e7ff4 | 600 | switch (edp_link_params->lanes) { |
e13e2b2c | 601 | case EDP_LANE_1: |
6aa23e65 | 602 | dev_priv->vbt.edp.lanes = 1; |
9f0e7ff4 | 603 | break; |
e13e2b2c | 604 | case EDP_LANE_2: |
6aa23e65 | 605 | dev_priv->vbt.edp.lanes = 2; |
9f0e7ff4 | 606 | break; |
e13e2b2c | 607 | case EDP_LANE_4: |
6aa23e65 | 608 | dev_priv->vbt.edp.lanes = 4; |
9f0e7ff4 | 609 | break; |
e13e2b2c JN |
610 | default: |
611 | DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n", | |
612 | edp_link_params->lanes); | |
613 | break; | |
9f0e7ff4 | 614 | } |
e13e2b2c | 615 | |
9f0e7ff4 | 616 | switch (edp_link_params->preemphasis) { |
e13e2b2c | 617 | case EDP_PREEMPHASIS_NONE: |
6aa23e65 | 618 | dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0; |
9f0e7ff4 | 619 | break; |
e13e2b2c | 620 | case EDP_PREEMPHASIS_3_5dB: |
6aa23e65 | 621 | dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1; |
9f0e7ff4 | 622 | break; |
e13e2b2c | 623 | case EDP_PREEMPHASIS_6dB: |
6aa23e65 | 624 | dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2; |
9f0e7ff4 | 625 | break; |
e13e2b2c | 626 | case EDP_PREEMPHASIS_9_5dB: |
6aa23e65 | 627 | dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; |
9f0e7ff4 | 628 | break; |
e13e2b2c JN |
629 | default: |
630 | DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n", | |
631 | edp_link_params->preemphasis); | |
632 | break; | |
9f0e7ff4 | 633 | } |
e13e2b2c | 634 | |
9f0e7ff4 | 635 | switch (edp_link_params->vswing) { |
e13e2b2c | 636 | case EDP_VSWING_0_4V: |
6aa23e65 | 637 | dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; |
9f0e7ff4 | 638 | break; |
e13e2b2c | 639 | case EDP_VSWING_0_6V: |
6aa23e65 | 640 | dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1; |
9f0e7ff4 | 641 | break; |
e13e2b2c | 642 | case EDP_VSWING_0_8V: |
6aa23e65 | 643 | dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
9f0e7ff4 | 644 | break; |
e13e2b2c | 645 | case EDP_VSWING_1_2V: |
6aa23e65 | 646 | dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
9f0e7ff4 | 647 | break; |
e13e2b2c JN |
648 | default: |
649 | DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n", | |
650 | edp_link_params->vswing); | |
651 | break; | |
9f0e7ff4 | 652 | } |
9a57f5bb SJ |
653 | |
654 | if (bdb->version >= 173) { | |
655 | uint8_t vswing; | |
656 | ||
9e458034 | 657 | /* Don't read from VBT if module parameter has valid value*/ |
4f044a88 MW |
658 | if (i915_modparams.edp_vswing) { |
659 | dev_priv->vbt.edp.low_vswing = | |
660 | i915_modparams.edp_vswing == 1; | |
9e458034 SJ |
661 | } else { |
662 | vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; | |
06411f08 | 663 | dev_priv->vbt.edp.low_vswing = vswing == 0; |
9e458034 | 664 | } |
9a57f5bb | 665 | } |
500a8cc4 ZW |
666 | } |
667 | ||
bfd7ebda | 668 | static void |
dcb58a40 | 669 | parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) |
bfd7ebda | 670 | { |
e8ef3b4c JN |
671 | const struct bdb_psr *psr; |
672 | const struct psr_table *psr_table; | |
3e845c7a | 673 | int panel_type = dev_priv->vbt.panel_type; |
bfd7ebda RV |
674 | |
675 | psr = find_section(bdb, BDB_PSR); | |
676 | if (!psr) { | |
677 | DRM_DEBUG_KMS("No PSR BDB found.\n"); | |
678 | return; | |
679 | } | |
680 | ||
681 | psr_table = &psr->psr_table[panel_type]; | |
682 | ||
683 | dev_priv->vbt.psr.full_link = psr_table->full_link; | |
684 | dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; | |
685 | ||
686 | /* Allowed VBT values goes from 0 to 15 */ | |
687 | dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : | |
688 | psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames; | |
689 | ||
690 | switch (psr_table->lines_to_wait) { | |
691 | case 0: | |
692 | dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT; | |
693 | break; | |
694 | case 1: | |
695 | dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT; | |
696 | break; | |
697 | case 2: | |
698 | dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT; | |
699 | break; | |
700 | case 3: | |
701 | dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT; | |
702 | break; | |
703 | default: | |
704 | DRM_DEBUG_KMS("VBT has unknown PSR lines to wait %u\n", | |
705 | psr_table->lines_to_wait); | |
706 | break; | |
707 | } | |
708 | ||
77312ae8 VN |
709 | /* |
710 | * New psr options 0=500us, 1=100us, 2=2500us, 3=0us | |
711 | * Old decimal value is wake up time in multiples of 100 us. | |
712 | */ | |
713 | if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) { | |
714 | switch (psr_table->tp1_wakeup_time) { | |
715 | case 0: | |
716 | dev_priv->vbt.psr.tp1_wakeup_time_us = 500; | |
717 | break; | |
718 | case 1: | |
719 | dev_priv->vbt.psr.tp1_wakeup_time_us = 100; | |
720 | break; | |
721 | case 3: | |
722 | dev_priv->vbt.psr.tp1_wakeup_time_us = 0; | |
723 | break; | |
724 | default: | |
725 | DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", | |
726 | psr_table->tp1_wakeup_time); | |
727 | /* fallthrough */ | |
728 | case 2: | |
729 | dev_priv->vbt.psr.tp1_wakeup_time_us = 2500; | |
730 | break; | |
731 | } | |
732 | ||
733 | switch (psr_table->tp2_tp3_wakeup_time) { | |
734 | case 0: | |
735 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500; | |
736 | break; | |
737 | case 1: | |
738 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100; | |
739 | break; | |
740 | case 3: | |
741 | dev_priv->vbt.psr.tp1_wakeup_time_us = 0; | |
742 | break; | |
743 | default: | |
744 | DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", | |
745 | psr_table->tp2_tp3_wakeup_time); | |
746 | /* fallthrough */ | |
747 | case 2: | |
748 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500; | |
749 | break; | |
750 | } | |
751 | } else { | |
752 | dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100; | |
753 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100; | |
754 | } | |
bfd7ebda RV |
755 | } |
756 | ||
46e58320 MC |
757 | static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv, |
758 | u16 version, enum port port) | |
759 | { | |
760 | if (!dev_priv->vbt.dsi.config->dual_link || version < 197) { | |
761 | dev_priv->vbt.dsi.bl_ports = BIT(port); | |
762 | if (dev_priv->vbt.dsi.config->cabc_supported) | |
763 | dev_priv->vbt.dsi.cabc_ports = BIT(port); | |
764 | ||
46e58320 MC |
765 | return; |
766 | } | |
767 | ||
768 | switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) { | |
769 | case DL_DCS_PORT_A: | |
770 | dev_priv->vbt.dsi.bl_ports = BIT(PORT_A); | |
771 | break; | |
772 | case DL_DCS_PORT_C: | |
773 | dev_priv->vbt.dsi.bl_ports = BIT(PORT_C); | |
774 | break; | |
775 | default: | |
776 | case DL_DCS_PORT_A_AND_C: | |
777 | dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C); | |
778 | break; | |
779 | } | |
780 | ||
781 | if (!dev_priv->vbt.dsi.config->cabc_supported) | |
782 | return; | |
783 | ||
784 | switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) { | |
785 | case DL_DCS_PORT_A: | |
786 | dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A); | |
787 | break; | |
788 | case DL_DCS_PORT_C: | |
789 | dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C); | |
790 | break; | |
791 | default: | |
792 | case DL_DCS_PORT_A_AND_C: | |
793 | dev_priv->vbt.dsi.cabc_ports = | |
794 | BIT(PORT_A) | BIT(PORT_C); | |
795 | break; | |
796 | } | |
797 | } | |
798 | ||
d17c5443 | 799 | static void |
0f8689f5 JN |
800 | parse_mipi_config(struct drm_i915_private *dev_priv, |
801 | const struct bdb_header *bdb) | |
d17c5443 | 802 | { |
e8ef3b4c | 803 | const struct bdb_mipi_config *start; |
e8ef3b4c JN |
804 | const struct mipi_config *config; |
805 | const struct mipi_pps_data *pps; | |
3e845c7a | 806 | int panel_type = dev_priv->vbt.panel_type; |
46e58320 | 807 | enum port port; |
d3b542fc | 808 | |
3e6bd011 | 809 | /* parse MIPI blocks only if LFP type is MIPI */ |
46e58320 | 810 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
3e6bd011 SK |
811 | return; |
812 | ||
d3b542fc SK |
813 | /* Initialize this to undefined indicating no generic MIPI support */ |
814 | dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; | |
815 | ||
816 | /* Block #40 is already parsed and panel_fixed_mode is | |
817 | * stored in dev_priv->lfp_lvds_vbt_mode | |
818 | * resuse this when needed | |
819 | */ | |
d17c5443 | 820 | |
d3b542fc SK |
821 | /* Parse #52 for panel index used from panel_type already |
822 | * parsed | |
823 | */ | |
824 | start = find_section(bdb, BDB_MIPI_CONFIG); | |
825 | if (!start) { | |
826 | DRM_DEBUG_KMS("No MIPI config BDB found"); | |
d17c5443 SK |
827 | return; |
828 | } | |
829 | ||
d3b542fc SK |
830 | DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n", |
831 | panel_type); | |
832 | ||
833 | /* | |
834 | * get hold of the correct configuration block and pps data as per | |
835 | * the panel_type as index | |
836 | */ | |
837 | config = &start->config[panel_type]; | |
838 | pps = &start->pps[panel_type]; | |
839 | ||
840 | /* store as of now full data. Trim when we realise all is not needed */ | |
841 | dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL); | |
842 | if (!dev_priv->vbt.dsi.config) | |
843 | return; | |
844 | ||
845 | dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL); | |
846 | if (!dev_priv->vbt.dsi.pps) { | |
847 | kfree(dev_priv->vbt.dsi.config); | |
848 | return; | |
849 | } | |
850 | ||
46e58320 | 851 | parse_dsi_backlight_ports(dev_priv, bdb->version, port); |
9f7c5b17 | 852 | |
d3b542fc | 853 | /* We have mandatory mipi config blocks. Initialize as generic panel */ |
ea9a6baf | 854 | dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID; |
0f8689f5 JN |
855 | } |
856 | ||
5db72099 JN |
857 | /* Find the sequence block and size for the given panel. */ |
858 | static const u8 * | |
859 | find_panel_sequence_block(const struct bdb_mipi_sequence *sequence, | |
2a33d934 | 860 | u16 panel_id, u32 *seq_size) |
5db72099 JN |
861 | { |
862 | u32 total = get_blocksize(sequence); | |
863 | const u8 *data = &sequence->data[0]; | |
864 | u8 current_id; | |
2a33d934 JN |
865 | u32 current_size; |
866 | int header_size = sequence->version >= 3 ? 5 : 3; | |
5db72099 JN |
867 | int index = 0; |
868 | int i; | |
869 | ||
2a33d934 JN |
870 | /* skip new block size */ |
871 | if (sequence->version >= 3) | |
872 | data += 4; | |
873 | ||
874 | for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) { | |
875 | if (index + header_size > total) { | |
876 | DRM_ERROR("Invalid sequence block (header)\n"); | |
877 | return NULL; | |
878 | } | |
879 | ||
5db72099 | 880 | current_id = *(data + index); |
2a33d934 JN |
881 | if (sequence->version >= 3) |
882 | current_size = *((const u32 *)(data + index + 1)); | |
883 | else | |
884 | current_size = *((const u16 *)(data + index + 1)); | |
5db72099 | 885 | |
2a33d934 | 886 | index += header_size; |
5db72099 JN |
887 | |
888 | if (index + current_size > total) { | |
889 | DRM_ERROR("Invalid sequence block\n"); | |
890 | return NULL; | |
891 | } | |
892 | ||
893 | if (current_id == panel_id) { | |
894 | *seq_size = current_size; | |
895 | return data + index; | |
896 | } | |
897 | ||
898 | index += current_size; | |
899 | } | |
900 | ||
901 | DRM_ERROR("Sequence block detected but no valid configuration\n"); | |
902 | ||
903 | return NULL; | |
904 | } | |
905 | ||
8d3ed2f3 JN |
906 | static int goto_next_sequence(const u8 *data, int index, int total) |
907 | { | |
908 | u16 len; | |
909 | ||
910 | /* Skip Sequence Byte. */ | |
911 | for (index = index + 1; index < total; index += len) { | |
912 | u8 operation_byte = *(data + index); | |
913 | index++; | |
914 | ||
915 | switch (operation_byte) { | |
916 | case MIPI_SEQ_ELEM_END: | |
917 | return index; | |
918 | case MIPI_SEQ_ELEM_SEND_PKT: | |
919 | if (index + 4 > total) | |
920 | return 0; | |
921 | ||
922 | len = *((const u16 *)(data + index + 2)) + 4; | |
923 | break; | |
924 | case MIPI_SEQ_ELEM_DELAY: | |
925 | len = 4; | |
926 | break; | |
927 | case MIPI_SEQ_ELEM_GPIO: | |
928 | len = 2; | |
929 | break; | |
f4d64936 JN |
930 | case MIPI_SEQ_ELEM_I2C: |
931 | if (index + 7 > total) | |
932 | return 0; | |
933 | len = *(data + index + 6) + 7; | |
934 | break; | |
8d3ed2f3 JN |
935 | default: |
936 | DRM_ERROR("Unknown operation byte\n"); | |
937 | return 0; | |
938 | } | |
939 | } | |
940 | ||
941 | return 0; | |
942 | } | |
943 | ||
2a33d934 JN |
944 | static int goto_next_sequence_v3(const u8 *data, int index, int total) |
945 | { | |
946 | int seq_end; | |
947 | u16 len; | |
6765bd6d | 948 | u32 size_of_sequence; |
2a33d934 JN |
949 | |
950 | /* | |
951 | * Could skip sequence based on Size of Sequence alone, but also do some | |
952 | * checking on the structure. | |
953 | */ | |
954 | if (total < 5) { | |
955 | DRM_ERROR("Too small sequence size\n"); | |
956 | return 0; | |
957 | } | |
958 | ||
6765bd6d JN |
959 | /* Skip Sequence Byte. */ |
960 | index++; | |
961 | ||
962 | /* | |
963 | * Size of Sequence. Excludes the Sequence Byte and the size itself, | |
964 | * includes MIPI_SEQ_ELEM_END byte, excludes the final MIPI_SEQ_END | |
965 | * byte. | |
966 | */ | |
967 | size_of_sequence = *((const uint32_t *)(data + index)); | |
968 | index += 4; | |
969 | ||
970 | seq_end = index + size_of_sequence; | |
2a33d934 JN |
971 | if (seq_end > total) { |
972 | DRM_ERROR("Invalid sequence size\n"); | |
973 | return 0; | |
974 | } | |
975 | ||
6765bd6d | 976 | for (; index < total; index += len) { |
2a33d934 JN |
977 | u8 operation_byte = *(data + index); |
978 | index++; | |
979 | ||
980 | if (operation_byte == MIPI_SEQ_ELEM_END) { | |
981 | if (index != seq_end) { | |
982 | DRM_ERROR("Invalid element structure\n"); | |
983 | return 0; | |
984 | } | |
985 | return index; | |
986 | } | |
987 | ||
988 | len = *(data + index); | |
989 | index++; | |
990 | ||
991 | /* | |
992 | * FIXME: Would be nice to check elements like for v1/v2 in | |
993 | * goto_next_sequence() above. | |
994 | */ | |
995 | switch (operation_byte) { | |
996 | case MIPI_SEQ_ELEM_SEND_PKT: | |
997 | case MIPI_SEQ_ELEM_DELAY: | |
998 | case MIPI_SEQ_ELEM_GPIO: | |
999 | case MIPI_SEQ_ELEM_I2C: | |
1000 | case MIPI_SEQ_ELEM_SPI: | |
1001 | case MIPI_SEQ_ELEM_PMIC: | |
1002 | break; | |
1003 | default: | |
1004 | DRM_ERROR("Unknown operation byte %u\n", | |
1005 | operation_byte); | |
1006 | break; | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | return 0; | |
1011 | } | |
1012 | ||
fb38e7ad HG |
1013 | /* |
1014 | * Get len of pre-fixed deassert fragment from a v1 init OTP sequence, | |
1015 | * skip all delay + gpio operands and stop at the first DSI packet op. | |
1016 | */ | |
1017 | static int get_init_otp_deassert_fragment_len(struct drm_i915_private *dev_priv) | |
1018 | { | |
1019 | const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; | |
1020 | int index, len; | |
1021 | ||
1022 | if (WARN_ON(!data || dev_priv->vbt.dsi.seq_version != 1)) | |
1023 | return 0; | |
1024 | ||
1025 | /* index = 1 to skip sequence byte */ | |
1026 | for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) { | |
1027 | switch (data[index]) { | |
1028 | case MIPI_SEQ_ELEM_SEND_PKT: | |
1029 | return index == 1 ? 0 : index; | |
1030 | case MIPI_SEQ_ELEM_DELAY: | |
1031 | len = 5; /* 1 byte for operand + uint32 */ | |
1032 | break; | |
1033 | case MIPI_SEQ_ELEM_GPIO: | |
1034 | len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */ | |
1035 | break; | |
1036 | default: | |
1037 | return 0; | |
1038 | } | |
1039 | } | |
1040 | ||
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | /* | |
1045 | * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence. | |
1046 | * The deassert must be done before calling intel_dsi_device_ready, so for | |
1047 | * these devices we split the init OTP sequence into a deassert sequence and | |
1048 | * the actual init OTP part. | |
1049 | */ | |
1050 | static void fixup_mipi_sequences(struct drm_i915_private *dev_priv) | |
1051 | { | |
1052 | u8 *init_otp; | |
1053 | int len; | |
1054 | ||
1055 | /* Limit this to VLV for now. */ | |
1056 | if (!IS_VALLEYVIEW(dev_priv)) | |
1057 | return; | |
1058 | ||
1059 | /* Limit this to v1 vid-mode sequences */ | |
1060 | if (dev_priv->vbt.dsi.config->is_cmd_mode || | |
1061 | dev_priv->vbt.dsi.seq_version != 1) | |
1062 | return; | |
1063 | ||
1064 | /* Only do this if there are otp and assert seqs and no deassert seq */ | |
1065 | if (!dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] || | |
1066 | !dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] || | |
1067 | dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) | |
1068 | return; | |
1069 | ||
1070 | /* The deassert-sequence ends at the first DSI packet */ | |
1071 | len = get_init_otp_deassert_fragment_len(dev_priv); | |
1072 | if (!len) | |
1073 | return; | |
1074 | ||
1075 | DRM_DEBUG_KMS("Using init OTP fragment to deassert reset\n"); | |
1076 | ||
1077 | /* Copy the fragment, update seq byte and terminate it */ | |
1078 | init_otp = (u8 *)dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; | |
1079 | dev_priv->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL); | |
1080 | if (!dev_priv->vbt.dsi.deassert_seq) | |
1081 | return; | |
1082 | dev_priv->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET; | |
1083 | dev_priv->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END; | |
1084 | /* Use the copy for deassert */ | |
1085 | dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] = | |
1086 | dev_priv->vbt.dsi.deassert_seq; | |
1087 | /* Replace the last byte of the fragment with init OTP seq byte */ | |
1088 | init_otp[len - 1] = MIPI_SEQ_INIT_OTP; | |
1089 | /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */ | |
1090 | dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1; | |
1091 | } | |
1092 | ||
0f8689f5 JN |
1093 | static void |
1094 | parse_mipi_sequence(struct drm_i915_private *dev_priv, | |
1095 | const struct bdb_header *bdb) | |
1096 | { | |
3e845c7a | 1097 | int panel_type = dev_priv->vbt.panel_type; |
0f8689f5 JN |
1098 | const struct bdb_mipi_sequence *sequence; |
1099 | const u8 *seq_data; | |
2a33d934 | 1100 | u32 seq_size; |
0f8689f5 | 1101 | u8 *data; |
8d3ed2f3 | 1102 | int index = 0; |
0f8689f5 JN |
1103 | |
1104 | /* Only our generic panel driver uses the sequence block. */ | |
1105 | if (dev_priv->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID) | |
1106 | return; | |
d3b542fc | 1107 | |
d3b542fc SK |
1108 | sequence = find_section(bdb, BDB_MIPI_SEQUENCE); |
1109 | if (!sequence) { | |
1110 | DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n"); | |
1111 | return; | |
1112 | } | |
1113 | ||
cd67d226 | 1114 | /* Fail gracefully for forward incompatible sequence block. */ |
2a33d934 JN |
1115 | if (sequence->version >= 4) { |
1116 | DRM_ERROR("Unable to parse MIPI Sequence Block v%u\n", | |
1117 | sequence->version); | |
cd67d226 JN |
1118 | return; |
1119 | } | |
1120 | ||
2a33d934 | 1121 | DRM_DEBUG_DRIVER("Found MIPI sequence block v%u\n", sequence->version); |
d3b542fc | 1122 | |
5db72099 JN |
1123 | seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size); |
1124 | if (!seq_data) | |
d3b542fc | 1125 | return; |
d3b542fc | 1126 | |
8d3ed2f3 JN |
1127 | data = kmemdup(seq_data, seq_size, GFP_KERNEL); |
1128 | if (!data) | |
d3b542fc SK |
1129 | return; |
1130 | ||
8d3ed2f3 JN |
1131 | /* Parse the sequences, store pointers to each sequence. */ |
1132 | for (;;) { | |
1133 | u8 seq_id = *(data + index); | |
1134 | if (seq_id == MIPI_SEQ_END) | |
1135 | break; | |
d3b542fc | 1136 | |
8d3ed2f3 JN |
1137 | if (seq_id >= MIPI_SEQ_MAX) { |
1138 | DRM_ERROR("Unknown sequence %u\n", seq_id); | |
d3b542fc SK |
1139 | goto err; |
1140 | } | |
1141 | ||
4b4f497e JN |
1142 | /* Log about presence of sequences we won't run. */ |
1143 | if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF) | |
1144 | DRM_DEBUG_KMS("Unsupported sequence %u\n", seq_id); | |
1145 | ||
8d3ed2f3 | 1146 | dev_priv->vbt.dsi.sequence[seq_id] = data + index; |
d3b542fc | 1147 | |
2a33d934 JN |
1148 | if (sequence->version >= 3) |
1149 | index = goto_next_sequence_v3(data, index, seq_size); | |
1150 | else | |
1151 | index = goto_next_sequence(data, index, seq_size); | |
8d3ed2f3 JN |
1152 | if (!index) { |
1153 | DRM_ERROR("Invalid sequence %u\n", seq_id); | |
d3b542fc SK |
1154 | goto err; |
1155 | } | |
d3b542fc SK |
1156 | } |
1157 | ||
8d3ed2f3 JN |
1158 | dev_priv->vbt.dsi.data = data; |
1159 | dev_priv->vbt.dsi.size = seq_size; | |
1160 | dev_priv->vbt.dsi.seq_version = sequence->version; | |
1161 | ||
fb38e7ad HG |
1162 | fixup_mipi_sequences(dev_priv); |
1163 | ||
8d3ed2f3 | 1164 | DRM_DEBUG_DRIVER("MIPI related VBT parsing complete\n"); |
d3b542fc | 1165 | return; |
d3b542fc | 1166 | |
8d3ed2f3 JN |
1167 | err: |
1168 | kfree(data); | |
ed3b6679 | 1169 | memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence)); |
d17c5443 SK |
1170 | } |
1171 | ||
75067dde AK |
1172 | static u8 translate_iboost(u8 val) |
1173 | { | |
1174 | static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */ | |
1175 | ||
1176 | if (val >= ARRAY_SIZE(mapping)) { | |
1177 | DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val); | |
1178 | return 0; | |
1179 | } | |
1180 | return mapping[val]; | |
1181 | } | |
1182 | ||
9454fa87 VS |
1183 | static void sanitize_ddc_pin(struct drm_i915_private *dev_priv, |
1184 | enum port port) | |
1185 | { | |
1186 | const struct ddi_vbt_port_info *info = | |
1187 | &dev_priv->vbt.ddi_port_info[port]; | |
1188 | enum port p; | |
1189 | ||
1190 | if (!info->alternate_ddc_pin) | |
1191 | return; | |
1192 | ||
1193 | for_each_port_masked(p, (1 << port) - 1) { | |
1194 | struct ddi_vbt_port_info *i = &dev_priv->vbt.ddi_port_info[p]; | |
1195 | ||
1196 | if (info->alternate_ddc_pin != i->alternate_ddc_pin) | |
1197 | continue; | |
1198 | ||
1199 | DRM_DEBUG_KMS("port %c trying to use the same DDC pin (0x%x) as port %c, " | |
1200 | "disabling port %c DVI/HDMI support\n", | |
1201 | port_name(p), i->alternate_ddc_pin, | |
1202 | port_name(port), port_name(p)); | |
1203 | ||
1204 | /* | |
1205 | * If we have multiple ports supposedly sharing the | |
1206 | * pin, then dvi/hdmi couldn't exist on the shared | |
1207 | * port. Otherwise they share the same ddc bin and | |
1208 | * system couldn't communicate with them separately. | |
1209 | * | |
1210 | * Due to parsing the ports in alphabetical order, | |
1211 | * a higher port will always clobber a lower one. | |
1212 | */ | |
1213 | i->supports_dvi = false; | |
1214 | i->supports_hdmi = false; | |
1215 | i->alternate_ddc_pin = 0; | |
1216 | } | |
1217 | } | |
1218 | ||
1219 | static void sanitize_aux_ch(struct drm_i915_private *dev_priv, | |
1220 | enum port port) | |
1221 | { | |
1222 | const struct ddi_vbt_port_info *info = | |
1223 | &dev_priv->vbt.ddi_port_info[port]; | |
1224 | enum port p; | |
1225 | ||
1226 | if (!info->alternate_aux_channel) | |
1227 | return; | |
1228 | ||
1229 | for_each_port_masked(p, (1 << port) - 1) { | |
1230 | struct ddi_vbt_port_info *i = &dev_priv->vbt.ddi_port_info[p]; | |
1231 | ||
1232 | if (info->alternate_aux_channel != i->alternate_aux_channel) | |
1233 | continue; | |
1234 | ||
1235 | DRM_DEBUG_KMS("port %c trying to use the same AUX CH (0x%x) as port %c, " | |
1236 | "disabling port %c DP support\n", | |
1237 | port_name(p), i->alternate_aux_channel, | |
1238 | port_name(port), port_name(p)); | |
1239 | ||
1240 | /* | |
1241 | * If we have multiple ports supposedlt sharing the | |
1242 | * aux channel, then DP couldn't exist on the shared | |
1243 | * port. Otherwise they share the same aux channel | |
1244 | * and system couldn't communicate with them separately. | |
1245 | * | |
1246 | * Due to parsing the ports in alphabetical order, | |
1247 | * a higher port will always clobber a lower one. | |
1248 | */ | |
1249 | i->supports_dp = false; | |
1250 | i->alternate_aux_channel = 0; | |
1251 | } | |
1252 | } | |
1253 | ||
9c3b2689 | 1254 | static const u8 cnp_ddc_pin_map[] = { |
3393ce1e | 1255 | [0] = 0, /* N/A */ |
9c3b2689 RV |
1256 | [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT, |
1257 | [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT, | |
1258 | [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP, /* sic */ | |
1259 | [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */ | |
1260 | }; | |
1261 | ||
3937eb1a RS |
1262 | static const u8 icp_ddc_pin_map[] = { |
1263 | [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, | |
1264 | [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, | |
1265 | [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP, | |
1266 | [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP, | |
1267 | [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP, | |
1268 | [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP, | |
1269 | }; | |
1270 | ||
9c3b2689 RV |
1271 | static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) |
1272 | { | |
3937eb1a RS |
1273 | const u8 *ddc_pin_map; |
1274 | int n_entries; | |
1275 | ||
1276 | if (HAS_PCH_ICP(dev_priv)) { | |
1277 | ddc_pin_map = icp_ddc_pin_map; | |
1278 | n_entries = ARRAY_SIZE(icp_ddc_pin_map); | |
1279 | } else if (HAS_PCH_CNP(dev_priv)) { | |
1280 | ddc_pin_map = cnp_ddc_pin_map; | |
1281 | n_entries = ARRAY_SIZE(cnp_ddc_pin_map); | |
1282 | } else { | |
1283 | /* Assuming direct map */ | |
1284 | return vbt_pin; | |
a8e6f388 | 1285 | } |
9c3b2689 | 1286 | |
3937eb1a RS |
1287 | if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0) |
1288 | return ddc_pin_map[vbt_pin]; | |
1289 | ||
1290 | DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", | |
1291 | vbt_pin); | |
1292 | return 0; | |
9c3b2689 RV |
1293 | } |
1294 | ||
6acab15a | 1295 | static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, |
0ead5f81 | 1296 | u8 bdb_version) |
6acab15a | 1297 | { |
cc998589 | 1298 | struct child_device_config *it, *child = NULL; |
6acab15a | 1299 | struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; |
6acab15a | 1300 | int i, j; |
554d6af5 | 1301 | bool is_dvi, is_hdmi, is_dp, is_edp, is_crt; |
6acab15a | 1302 | /* Each DDI port can have more than one value on the "DVO Port" field, |
b5273d72 JN |
1303 | * so look for all the possible values for each port. |
1304 | */ | |
2800e4c2 RV |
1305 | int dvo_ports[][3] = { |
1306 | {DVO_PORT_HDMIA, DVO_PORT_DPA, -1}, | |
1307 | {DVO_PORT_HDMIB, DVO_PORT_DPB, -1}, | |
1308 | {DVO_PORT_HDMIC, DVO_PORT_DPC, -1}, | |
1309 | {DVO_PORT_HDMID, DVO_PORT_DPD, -1}, | |
1310 | {DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE}, | |
841b5ed7 | 1311 | {DVO_PORT_HDMIF, DVO_PORT_DPF, -1}, |
6acab15a PZ |
1312 | }; |
1313 | ||
b5273d72 JN |
1314 | /* |
1315 | * Find the first child device to reference the port, report if more | |
1316 | * than one found. | |
1317 | */ | |
6acab15a PZ |
1318 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
1319 | it = dev_priv->vbt.child_dev + i; | |
1320 | ||
2800e4c2 | 1321 | for (j = 0; j < 3; j++) { |
6acab15a PZ |
1322 | if (dvo_ports[port][j] == -1) |
1323 | break; | |
1324 | ||
cc998589 | 1325 | if (it->dvo_port == dvo_ports[port][j]) { |
6acab15a | 1326 | if (child) { |
b5273d72 | 1327 | DRM_DEBUG_KMS("More than one child device for port %c in VBT, using the first.\n", |
6acab15a | 1328 | port_name(port)); |
b5273d72 JN |
1329 | } else { |
1330 | child = it; | |
6acab15a | 1331 | } |
6acab15a PZ |
1332 | } |
1333 | } | |
1334 | } | |
1335 | if (!child) | |
1336 | return; | |
1337 | ||
cc998589 JN |
1338 | is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; |
1339 | is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; | |
1340 | is_crt = child->device_type & DEVICE_TYPE_ANALOG_OUTPUT; | |
1341 | is_hdmi = is_dvi && (child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0; | |
1342 | is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR); | |
554d6af5 | 1343 | |
2ba7d7e0 JN |
1344 | if (port == PORT_A && is_dvi) { |
1345 | DRM_DEBUG_KMS("VBT claims port A supports DVI%s, ignoring\n", | |
1346 | is_hdmi ? "/HDMI" : ""); | |
1347 | is_dvi = false; | |
1348 | is_hdmi = false; | |
1349 | } | |
1350 | ||
311a2094 PZ |
1351 | info->supports_dvi = is_dvi; |
1352 | info->supports_hdmi = is_hdmi; | |
1353 | info->supports_dp = is_dp; | |
a98d9c1d | 1354 | info->supports_edp = is_edp; |
311a2094 | 1355 | |
554d6af5 PZ |
1356 | DRM_DEBUG_KMS("Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d\n", |
1357 | port_name(port), is_dp, is_hdmi, is_dvi, is_edp, is_crt); | |
1358 | ||
1359 | if (is_edp && is_dvi) | |
1360 | DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n", | |
1361 | port_name(port)); | |
1362 | if (is_crt && port != PORT_E) | |
1363 | DRM_DEBUG_KMS("Port %c is analog\n", port_name(port)); | |
1364 | if (is_crt && (is_dvi || is_dp)) | |
1365 | DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n", | |
1366 | port_name(port)); | |
1367 | if (is_dvi && (port == PORT_A || port == PORT_E)) | |
9b13494c | 1368 | DRM_DEBUG_KMS("Port %c is TMDS compatible\n", port_name(port)); |
554d6af5 PZ |
1369 | if (!is_dvi && !is_dp && !is_crt) |
1370 | DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n", | |
1371 | port_name(port)); | |
1372 | if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E)) | |
1373 | DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port)); | |
6bf19e7c PZ |
1374 | |
1375 | if (is_dvi) { | |
e53a1058 JN |
1376 | u8 ddc_pin; |
1377 | ||
f212bf9a JN |
1378 | ddc_pin = map_ddc_pin(dev_priv, child->ddc_pin); |
1379 | if (intel_gmbus_is_valid_pin(dev_priv, ddc_pin)) { | |
1380 | info->alternate_ddc_pin = ddc_pin; | |
1381 | sanitize_ddc_pin(dev_priv, port); | |
1382 | } else { | |
1383 | DRM_DEBUG_KMS("Port %c has invalid DDC pin %d, " | |
1384 | "sticking to defaults\n", | |
1385 | port_name(port), ddc_pin); | |
1386 | } | |
6bf19e7c PZ |
1387 | } |
1388 | ||
1389 | if (is_dp) { | |
e53a1058 | 1390 | info->alternate_aux_channel = child->aux_channel; |
9454fa87 VS |
1391 | |
1392 | sanitize_aux_ch(dev_priv, port); | |
6bf19e7c PZ |
1393 | } |
1394 | ||
0ead5f81 | 1395 | if (bdb_version >= 158) { |
6acab15a | 1396 | /* The VBT HDMI level shift values match the table we have. */ |
e53a1058 | 1397 | u8 hdmi_level_shift = child->hdmi_level_shifter_value; |
ce4dd49e DL |
1398 | DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n", |
1399 | port_name(port), | |
1400 | hdmi_level_shift); | |
1401 | info->hdmi_level_shift = hdmi_level_shift; | |
6acab15a | 1402 | } |
75067dde | 1403 | |
d6038611 VS |
1404 | if (bdb_version >= 204) { |
1405 | int max_tmds_clock; | |
1406 | ||
1407 | switch (child->hdmi_max_data_rate) { | |
1408 | default: | |
1409 | MISSING_CASE(child->hdmi_max_data_rate); | |
1410 | /* fall through */ | |
1411 | case HDMI_MAX_DATA_RATE_PLATFORM: | |
1412 | max_tmds_clock = 0; | |
1413 | break; | |
1414 | case HDMI_MAX_DATA_RATE_297: | |
1415 | max_tmds_clock = 297000; | |
1416 | break; | |
1417 | case HDMI_MAX_DATA_RATE_165: | |
1418 | max_tmds_clock = 165000; | |
1419 | break; | |
1420 | } | |
1421 | ||
1422 | if (max_tmds_clock) | |
1423 | DRM_DEBUG_KMS("VBT HDMI max TMDS clock for port %c: %d kHz\n", | |
1424 | port_name(port), max_tmds_clock); | |
1425 | info->max_tmds_clock = max_tmds_clock; | |
1426 | } | |
1427 | ||
75067dde | 1428 | /* Parse the I_boost config for SKL and above */ |
0ead5f81 | 1429 | if (bdb_version >= 196 && child->iboost) { |
f22bb358 | 1430 | info->dp_boost_level = translate_iboost(child->dp_iboost_level); |
75067dde AK |
1431 | DRM_DEBUG_KMS("VBT (e)DP boost level for port %c: %d\n", |
1432 | port_name(port), info->dp_boost_level); | |
f22bb358 | 1433 | info->hdmi_boost_level = translate_iboost(child->hdmi_iboost_level); |
75067dde AK |
1434 | DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n", |
1435 | port_name(port), info->hdmi_boost_level); | |
1436 | } | |
99b91bda JN |
1437 | |
1438 | /* DP max link rate for CNL+ */ | |
1439 | if (bdb_version >= 216) { | |
1440 | switch (child->dp_max_link_rate) { | |
1441 | default: | |
1442 | case VBT_DP_MAX_LINK_RATE_HBR3: | |
1443 | info->dp_max_link_rate = 810000; | |
1444 | break; | |
1445 | case VBT_DP_MAX_LINK_RATE_HBR2: | |
1446 | info->dp_max_link_rate = 540000; | |
1447 | break; | |
1448 | case VBT_DP_MAX_LINK_RATE_HBR: | |
1449 | info->dp_max_link_rate = 270000; | |
1450 | break; | |
1451 | case VBT_DP_MAX_LINK_RATE_LBR: | |
1452 | info->dp_max_link_rate = 162000; | |
1453 | break; | |
1454 | } | |
1455 | DRM_DEBUG_KMS("VBT DP max link rate for port %c: %d\n", | |
1456 | port_name(port), info->dp_max_link_rate); | |
1457 | } | |
6acab15a PZ |
1458 | } |
1459 | ||
0ead5f81 | 1460 | static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version) |
6acab15a | 1461 | { |
6acab15a PZ |
1462 | enum port port; |
1463 | ||
348e4058 | 1464 | if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6acab15a PZ |
1465 | return; |
1466 | ||
1467 | if (!dev_priv->vbt.child_dev_num) | |
1468 | return; | |
1469 | ||
0ead5f81 | 1470 | if (bdb_version < 155) |
6acab15a PZ |
1471 | return; |
1472 | ||
1473 | for (port = PORT_A; port < I915_MAX_PORTS; port++) | |
0ead5f81 | 1474 | parse_ddi_port(dev_priv, port, bdb_version); |
6acab15a PZ |
1475 | } |
1476 | ||
6363ee6f | 1477 | static void |
b3ca1f43 JN |
1478 | parse_general_definitions(struct drm_i915_private *dev_priv, |
1479 | const struct bdb_header *bdb) | |
6363ee6f | 1480 | { |
e192839e JN |
1481 | const struct bdb_general_definitions *defs; |
1482 | const struct child_device_config *child; | |
6363ee6f | 1483 | int i, child_device_num, count; |
e2d6cf7f DW |
1484 | u8 expected_size; |
1485 | u16 block_size; | |
b3ca1f43 | 1486 | int bus_pin; |
6363ee6f | 1487 | |
e192839e JN |
1488 | defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); |
1489 | if (!defs) { | |
44834a67 | 1490 | DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n"); |
6363ee6f ZY |
1491 | return; |
1492 | } | |
b3ca1f43 JN |
1493 | |
1494 | block_size = get_blocksize(defs); | |
1495 | if (block_size < sizeof(*defs)) { | |
1496 | DRM_DEBUG_KMS("General definitions block too small (%u)\n", | |
1497 | block_size); | |
1498 | return; | |
1499 | } | |
1500 | ||
1501 | bus_pin = defs->crt_ddc_gmbus_pin; | |
1502 | DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin); | |
1503 | if (intel_gmbus_is_valid_pin(dev_priv, bus_pin)) | |
1504 | dev_priv->vbt.crt_ddc_pin = bus_pin; | |
1505 | ||
7244f309 VS |
1506 | if (bdb->version < 106) { |
1507 | expected_size = 22; | |
fa05178c | 1508 | } else if (bdb->version < 111) { |
52b69c84 VS |
1509 | expected_size = 27; |
1510 | } else if (bdb->version < 195) { | |
21907e72 | 1511 | expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE; |
e2d6cf7f DW |
1512 | } else if (bdb->version == 195) { |
1513 | expected_size = 37; | |
c4fb60b9 | 1514 | } else if (bdb->version <= 215) { |
e2d6cf7f | 1515 | expected_size = 38; |
c4fb60b9 JN |
1516 | } else if (bdb->version <= 216) { |
1517 | expected_size = 39; | |
e2d6cf7f | 1518 | } else { |
c4fb60b9 JN |
1519 | expected_size = sizeof(*child); |
1520 | BUILD_BUG_ON(sizeof(*child) < 39); | |
e2d6cf7f DW |
1521 | DRM_DEBUG_DRIVER("Expected child device config size for VBT version %u not known; assuming %u\n", |
1522 | bdb->version, expected_size); | |
1523 | } | |
1524 | ||
e2d6cf7f | 1525 | /* Flag an error for unexpected size, but continue anyway. */ |
e192839e | 1526 | if (defs->child_dev_size != expected_size) |
e2d6cf7f | 1527 | DRM_ERROR("Unexpected child device config size %u (expected %u for VBT version %u)\n", |
e192839e | 1528 | defs->child_dev_size, expected_size, bdb->version); |
e2d6cf7f | 1529 | |
52b69c84 | 1530 | /* The legacy sized child device config is the minimum we need. */ |
e192839e | 1531 | if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) { |
52b69c84 | 1532 | DRM_DEBUG_KMS("Child device config size %u is too small.\n", |
e192839e | 1533 | defs->child_dev_size); |
52b69c84 VS |
1534 | return; |
1535 | } | |
1536 | ||
6363ee6f | 1537 | /* get the number of child device */ |
e192839e | 1538 | child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size; |
6363ee6f ZY |
1539 | count = 0; |
1540 | /* get the number of child device that is present */ | |
1541 | for (i = 0; i < child_device_num; i++) { | |
e192839e | 1542 | child = child_device_ptr(defs, i); |
53f6b243 | 1543 | if (!child->device_type) |
6363ee6f | 1544 | continue; |
6363ee6f ZY |
1545 | count++; |
1546 | } | |
1547 | if (!count) { | |
0206e353 | 1548 | DRM_DEBUG_KMS("no child dev is parsed from VBT\n"); |
6363ee6f ZY |
1549 | return; |
1550 | } | |
e192839e | 1551 | dev_priv->vbt.child_dev = kcalloc(count, sizeof(*child), GFP_KERNEL); |
41aa3448 | 1552 | if (!dev_priv->vbt.child_dev) { |
6363ee6f ZY |
1553 | DRM_DEBUG_KMS("No memory space for child device\n"); |
1554 | return; | |
1555 | } | |
1556 | ||
41aa3448 | 1557 | dev_priv->vbt.child_dev_num = count; |
6363ee6f ZY |
1558 | count = 0; |
1559 | for (i = 0; i < child_device_num; i++) { | |
e192839e | 1560 | child = child_device_ptr(defs, i); |
53f6b243 | 1561 | if (!child->device_type) |
6363ee6f | 1562 | continue; |
3e6bd011 | 1563 | |
e2d6cf7f DW |
1564 | /* |
1565 | * Copy as much as we know (sizeof) and is available | |
1566 | * (child_dev_size) of the child device. Accessing the data must | |
1567 | * depend on VBT version. | |
1568 | */ | |
127704f5 | 1569 | memcpy(dev_priv->vbt.child_dev + count, child, |
e192839e | 1570 | min_t(size_t, defs->child_dev_size, sizeof(*child))); |
127704f5 | 1571 | count++; |
6363ee6f | 1572 | } |
6363ee6f | 1573 | } |
44834a67 | 1574 | |
bb1d1329 | 1575 | /* Common defaults which may be overridden by VBT. */ |
6a04002b SQ |
1576 | static void |
1577 | init_vbt_defaults(struct drm_i915_private *dev_priv) | |
1578 | { | |
6acab15a | 1579 | enum port port; |
9a4114ff | 1580 | |
988c7015 | 1581 | dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; |
6a04002b | 1582 | |
56c4b63a JN |
1583 | /* Default to having backlight */ |
1584 | dev_priv->vbt.backlight.present = true; | |
1585 | ||
6a04002b | 1586 | /* LFP panel data */ |
41aa3448 | 1587 | dev_priv->vbt.lvds_dither = 1; |
6a04002b SQ |
1588 | |
1589 | /* SDVO panel data */ | |
41aa3448 | 1590 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; |
6a04002b SQ |
1591 | |
1592 | /* general features */ | |
41aa3448 RV |
1593 | dev_priv->vbt.int_tv_support = 1; |
1594 | dev_priv->vbt.int_crt_support = 1; | |
9a4114ff | 1595 | |
5255e2f8 VS |
1596 | /* driver features */ |
1597 | dev_priv->vbt.int_lvds_support = 1; | |
1598 | ||
9a4114ff | 1599 | /* Default to using SSC */ |
41aa3448 | 1600 | dev_priv->vbt.lvds_use_ssc = 1; |
f69e5156 DL |
1601 | /* |
1602 | * Core/SandyBridge/IvyBridge use alternative (120MHz) reference | |
1603 | * clock for LVDS. | |
1604 | */ | |
98f3a1dc JN |
1605 | dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev_priv, |
1606 | !HAS_PCH_SPLIT(dev_priv)); | |
e91e941b | 1607 | DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq); |
6acab15a PZ |
1608 | |
1609 | for (port = PORT_A; port < I915_MAX_PORTS; port++) { | |
311a2094 PZ |
1610 | struct ddi_vbt_port_info *info = |
1611 | &dev_priv->vbt.ddi_port_info[port]; | |
1612 | ||
ce4dd49e | 1613 | info->hdmi_level_shift = HDMI_LEVEL_SHIFT_UNKNOWN; |
bb1d1329 JN |
1614 | } |
1615 | } | |
1616 | ||
1617 | /* Defaults to initialize only if there is no VBT. */ | |
1618 | static void | |
1619 | init_vbt_missing_defaults(struct drm_i915_private *dev_priv) | |
1620 | { | |
1621 | enum port port; | |
1622 | ||
1623 | for (port = PORT_A; port < I915_MAX_PORTS; port++) { | |
1624 | struct ddi_vbt_port_info *info = | |
1625 | &dev_priv->vbt.ddi_port_info[port]; | |
311a2094 PZ |
1626 | |
1627 | info->supports_dvi = (port != PORT_A && port != PORT_E); | |
1628 | info->supports_hdmi = info->supports_dvi; | |
1629 | info->supports_dp = (port != PORT_E); | |
6acab15a | 1630 | } |
6a04002b SQ |
1631 | } |
1632 | ||
caf37fa4 JN |
1633 | static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt) |
1634 | { | |
1635 | const void *_vbt = vbt; | |
1636 | ||
1637 | return _vbt + vbt->bdb_offset; | |
1638 | } | |
1639 | ||
f0067a31 JN |
1640 | /** |
1641 | * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT | |
1642 | * @buf: pointer to a buffer to validate | |
1643 | * @size: size of the buffer | |
1644 | * | |
1645 | * Returns true on valid VBT. | |
1646 | */ | |
1647 | bool intel_bios_is_valid_vbt(const void *buf, size_t size) | |
3dd4e846 | 1648 | { |
f0067a31 | 1649 | const struct vbt_header *vbt = buf; |
dcb58a40 | 1650 | const struct bdb_header *bdb; |
3dd4e846 | 1651 | |
caf37fa4 | 1652 | if (!vbt) |
f0067a31 | 1653 | return false; |
caf37fa4 | 1654 | |
f0067a31 | 1655 | if (sizeof(struct vbt_header) > size) { |
3dd4e846 | 1656 | DRM_DEBUG_DRIVER("VBT header incomplete\n"); |
f0067a31 | 1657 | return false; |
3dd4e846 CW |
1658 | } |
1659 | ||
1660 | if (memcmp(vbt->signature, "$VBT", 4)) { | |
1661 | DRM_DEBUG_DRIVER("VBT invalid signature\n"); | |
f0067a31 | 1662 | return false; |
3dd4e846 CW |
1663 | } |
1664 | ||
e8f9ae9b CW |
1665 | if (range_overflows_t(size_t, |
1666 | vbt->bdb_offset, | |
1667 | sizeof(struct bdb_header), | |
1668 | size)) { | |
3dd4e846 | 1669 | DRM_DEBUG_DRIVER("BDB header incomplete\n"); |
f0067a31 | 1670 | return false; |
3dd4e846 CW |
1671 | } |
1672 | ||
caf37fa4 | 1673 | bdb = get_bdb_header(vbt); |
e8f9ae9b | 1674 | if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) { |
3dd4e846 | 1675 | DRM_DEBUG_DRIVER("BDB incomplete\n"); |
f0067a31 | 1676 | return false; |
3dd4e846 CW |
1677 | } |
1678 | ||
caf37fa4 | 1679 | return vbt; |
3dd4e846 CW |
1680 | } |
1681 | ||
caf37fa4 | 1682 | static const struct vbt_header *find_vbt(void __iomem *bios, size_t size) |
b34a991a | 1683 | { |
b34a991a JN |
1684 | size_t i; |
1685 | ||
1686 | /* Scour memory looking for the VBT signature. */ | |
1687 | for (i = 0; i + 4 < size; i++) { | |
f0067a31 | 1688 | void *vbt; |
115719fc | 1689 | |
f0067a31 JN |
1690 | if (ioread32(bios + i) != *((const u32 *) "$VBT")) |
1691 | continue; | |
1692 | ||
1693 | /* | |
1694 | * This is the one place where we explicitly discard the address | |
1695 | * space (__iomem) of the BIOS/VBT. | |
1696 | */ | |
1697 | vbt = (void __force *) bios + i; | |
1698 | if (intel_bios_is_valid_vbt(vbt, size - i)) | |
1699 | return vbt; | |
1700 | ||
1701 | break; | |
b34a991a JN |
1702 | } |
1703 | ||
f0067a31 | 1704 | return NULL; |
b34a991a JN |
1705 | } |
1706 | ||
79e53945 | 1707 | /** |
8b8e1a89 | 1708 | * intel_bios_init - find VBT and initialize settings from the BIOS |
dd97950a | 1709 | * @dev_priv: i915 device instance |
79e53945 | 1710 | * |
66578857 JN |
1711 | * Parse and initialize settings from the Video BIOS Tables (VBT). If the VBT |
1712 | * was not found in ACPI OpRegion, try to find it in PCI ROM first. Also | |
1713 | * initialize some defaults if the VBT is not present at all. | |
79e53945 | 1714 | */ |
66578857 | 1715 | void intel_bios_init(struct drm_i915_private *dev_priv) |
79e53945 | 1716 | { |
91c8a326 | 1717 | struct pci_dev *pdev = dev_priv->drm.pdev; |
f0067a31 | 1718 | const struct vbt_header *vbt = dev_priv->opregion.vbt; |
caf37fa4 | 1719 | const struct bdb_header *bdb; |
44834a67 CW |
1720 | u8 __iomem *bios = NULL; |
1721 | ||
13d0464b | 1722 | if (INTEL_INFO(dev_priv)->num_pipes == 0) { |
66578857 JN |
1723 | DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n"); |
1724 | return; | |
1725 | } | |
ab5c608b | 1726 | |
6a04002b | 1727 | init_vbt_defaults(dev_priv); |
f899fc64 | 1728 | |
66578857 | 1729 | /* If the OpRegion does not have VBT, look in PCI ROM. */ |
f0067a31 | 1730 | if (!vbt) { |
b34a991a | 1731 | size_t size; |
79e53945 | 1732 | |
44834a67 CW |
1733 | bios = pci_map_rom(pdev, &size); |
1734 | if (!bios) | |
66578857 | 1735 | goto out; |
44834a67 | 1736 | |
caf37fa4 | 1737 | vbt = find_vbt(bios, size); |
66578857 JN |
1738 | if (!vbt) |
1739 | goto out; | |
e2051c44 JN |
1740 | |
1741 | DRM_DEBUG_KMS("Found valid VBT in PCI ROM\n"); | |
44834a67 | 1742 | } |
79e53945 | 1743 | |
caf37fa4 JN |
1744 | bdb = get_bdb_header(vbt); |
1745 | ||
3556dd40 JN |
1746 | DRM_DEBUG_KMS("VBT signature \"%.*s\", BDB version %d\n", |
1747 | (int)sizeof(vbt->signature), vbt->signature, bdb->version); | |
e2051c44 | 1748 | |
79e53945 JB |
1749 | /* Grab useful general definitions */ |
1750 | parse_general_features(dev_priv, bdb); | |
db545019 | 1751 | parse_general_definitions(dev_priv, bdb); |
88631706 | 1752 | parse_lfp_panel_data(dev_priv, bdb); |
f00076d2 | 1753 | parse_lfp_backlight(dev_priv, bdb); |
88631706 | 1754 | parse_sdvo_panel_data(dev_priv, bdb); |
32f9d658 | 1755 | parse_driver_features(dev_priv, bdb); |
500a8cc4 | 1756 | parse_edp(dev_priv, bdb); |
bfd7ebda | 1757 | parse_psr(dev_priv, bdb); |
0f8689f5 JN |
1758 | parse_mipi_config(dev_priv, bdb); |
1759 | parse_mipi_sequence(dev_priv, bdb); | |
0ebdabe6 JN |
1760 | |
1761 | /* Further processing on pre-parsed data */ | |
0ead5f81 JN |
1762 | parse_sdvo_device_mapping(dev_priv, bdb->version); |
1763 | parse_ddi_ports(dev_priv, bdb->version); | |
32f9d658 | 1764 | |
66578857 | 1765 | out: |
bb1d1329 | 1766 | if (!vbt) { |
66578857 | 1767 | DRM_INFO("Failed to find VBIOS tables (VBT)\n"); |
bb1d1329 JN |
1768 | init_vbt_missing_defaults(dev_priv); |
1769 | } | |
66578857 | 1770 | |
44834a67 CW |
1771 | if (bios) |
1772 | pci_unmap_rom(pdev, bios); | |
79e53945 | 1773 | } |
3bdd14d5 | 1774 | |
785f076b HG |
1775 | /** |
1776 | * intel_bios_cleanup - Free any resources allocated by intel_bios_init() | |
1777 | * @dev_priv: i915 device instance | |
1778 | */ | |
1779 | void intel_bios_cleanup(struct drm_i915_private *dev_priv) | |
1780 | { | |
1781 | kfree(dev_priv->vbt.child_dev); | |
1782 | dev_priv->vbt.child_dev = NULL; | |
1783 | dev_priv->vbt.child_dev_num = 0; | |
1784 | kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); | |
1785 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; | |
1786 | kfree(dev_priv->vbt.lfp_lvds_vbt_mode); | |
1787 | dev_priv->vbt.lfp_lvds_vbt_mode = NULL; | |
e1b86c85 HG |
1788 | kfree(dev_priv->vbt.dsi.data); |
1789 | dev_priv->vbt.dsi.data = NULL; | |
1790 | kfree(dev_priv->vbt.dsi.pps); | |
1791 | dev_priv->vbt.dsi.pps = NULL; | |
1792 | kfree(dev_priv->vbt.dsi.config); | |
1793 | dev_priv->vbt.dsi.config = NULL; | |
fb38e7ad HG |
1794 | kfree(dev_priv->vbt.dsi.deassert_seq); |
1795 | dev_priv->vbt.dsi.deassert_seq = NULL; | |
785f076b HG |
1796 | } |
1797 | ||
3bdd14d5 JN |
1798 | /** |
1799 | * intel_bios_is_tv_present - is integrated TV present in VBT | |
1800 | * @dev_priv: i915 device instance | |
1801 | * | |
1802 | * Return true if TV is present. If no child devices were parsed from VBT, | |
1803 | * assume TV is present. | |
1804 | */ | |
1805 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv) | |
1806 | { | |
cc998589 | 1807 | const struct child_device_config *child; |
3bdd14d5 JN |
1808 | int i; |
1809 | ||
1810 | if (!dev_priv->vbt.int_tv_support) | |
1811 | return false; | |
1812 | ||
1813 | if (!dev_priv->vbt.child_dev_num) | |
1814 | return true; | |
1815 | ||
1816 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
cc998589 | 1817 | child = dev_priv->vbt.child_dev + i; |
3bdd14d5 JN |
1818 | /* |
1819 | * If the device type is not TV, continue. | |
1820 | */ | |
cc998589 | 1821 | switch (child->device_type) { |
3bdd14d5 JN |
1822 | case DEVICE_TYPE_INT_TV: |
1823 | case DEVICE_TYPE_TV: | |
1824 | case DEVICE_TYPE_TV_SVIDEO_COMPOSITE: | |
1825 | break; | |
1826 | default: | |
1827 | continue; | |
1828 | } | |
1829 | /* Only when the addin_offset is non-zero, it is regarded | |
1830 | * as present. | |
1831 | */ | |
cc998589 | 1832 | if (child->addin_offset) |
3bdd14d5 JN |
1833 | return true; |
1834 | } | |
1835 | ||
1836 | return false; | |
1837 | } | |
5a69d13d JN |
1838 | |
1839 | /** | |
1840 | * intel_bios_is_lvds_present - is LVDS present in VBT | |
1841 | * @dev_priv: i915 device instance | |
1842 | * @i2c_pin: i2c pin for LVDS if present | |
1843 | * | |
1844 | * Return true if LVDS is present. If no child devices were parsed from VBT, | |
1845 | * assume LVDS is present. | |
1846 | */ | |
1847 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin) | |
1848 | { | |
cc998589 | 1849 | const struct child_device_config *child; |
5a69d13d JN |
1850 | int i; |
1851 | ||
1852 | if (!dev_priv->vbt.child_dev_num) | |
1853 | return true; | |
1854 | ||
1855 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
cc998589 | 1856 | child = dev_priv->vbt.child_dev + i; |
5a69d13d JN |
1857 | |
1858 | /* If the device type is not LFP, continue. | |
1859 | * We have to check both the new identifiers as well as the | |
1860 | * old for compatibility with some BIOSes. | |
1861 | */ | |
1862 | if (child->device_type != DEVICE_TYPE_INT_LFP && | |
1863 | child->device_type != DEVICE_TYPE_LFP) | |
1864 | continue; | |
1865 | ||
1866 | if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin)) | |
1867 | *i2c_pin = child->i2c_pin; | |
1868 | ||
1869 | /* However, we cannot trust the BIOS writers to populate | |
1870 | * the VBT correctly. Since LVDS requires additional | |
1871 | * information from AIM blocks, a non-zero addin offset is | |
1872 | * a good indicator that the LVDS is actually present. | |
1873 | */ | |
1874 | if (child->addin_offset) | |
1875 | return true; | |
1876 | ||
1877 | /* But even then some BIOS writers perform some black magic | |
1878 | * and instantiate the device without reference to any | |
1879 | * additional data. Trust that if the VBT was written into | |
1880 | * the OpRegion then they have validated the LVDS's existence. | |
1881 | */ | |
1882 | if (dev_priv->opregion.vbt) | |
1883 | return true; | |
1884 | } | |
1885 | ||
1886 | return false; | |
1887 | } | |
951d9efe | 1888 | |
22f35042 VS |
1889 | /** |
1890 | * intel_bios_is_port_present - is the specified digital port present | |
1891 | * @dev_priv: i915 device instance | |
1892 | * @port: port to check | |
1893 | * | |
1894 | * Return true if the device in %port is present. | |
1895 | */ | |
1896 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port) | |
1897 | { | |
cc998589 | 1898 | const struct child_device_config *child; |
22f35042 VS |
1899 | static const struct { |
1900 | u16 dp, hdmi; | |
1901 | } port_mapping[] = { | |
1902 | [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, }, | |
1903 | [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, }, | |
1904 | [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, }, | |
1905 | [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, }, | |
841b5ed7 | 1906 | [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, }, |
22f35042 VS |
1907 | }; |
1908 | int i; | |
1909 | ||
1910 | /* FIXME maybe deal with port A as well? */ | |
1911 | if (WARN_ON(port == PORT_A) || port >= ARRAY_SIZE(port_mapping)) | |
1912 | return false; | |
1913 | ||
1914 | if (!dev_priv->vbt.child_dev_num) | |
1915 | return false; | |
1916 | ||
1917 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
cc998589 JN |
1918 | child = dev_priv->vbt.child_dev + i; |
1919 | ||
1920 | if ((child->dvo_port == port_mapping[port].dp || | |
1921 | child->dvo_port == port_mapping[port].hdmi) && | |
1922 | (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING | | |
1923 | DEVICE_TYPE_DISPLAYPORT_OUTPUT))) | |
22f35042 VS |
1924 | return true; |
1925 | } | |
1926 | ||
1927 | return false; | |
1928 | } | |
1929 | ||
951d9efe JN |
1930 | /** |
1931 | * intel_bios_is_port_edp - is the device in given port eDP | |
1932 | * @dev_priv: i915 device instance | |
1933 | * @port: port to check | |
1934 | * | |
1935 | * Return true if the device in %port is eDP. | |
1936 | */ | |
1937 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port) | |
1938 | { | |
cc998589 | 1939 | const struct child_device_config *child; |
951d9efe JN |
1940 | static const short port_mapping[] = { |
1941 | [PORT_B] = DVO_PORT_DPB, | |
1942 | [PORT_C] = DVO_PORT_DPC, | |
1943 | [PORT_D] = DVO_PORT_DPD, | |
1944 | [PORT_E] = DVO_PORT_DPE, | |
841b5ed7 | 1945 | [PORT_F] = DVO_PORT_DPF, |
951d9efe JN |
1946 | }; |
1947 | int i; | |
1948 | ||
a98d9c1d ID |
1949 | if (HAS_DDI(dev_priv)) |
1950 | return dev_priv->vbt.ddi_port_info[port].supports_edp; | |
1951 | ||
951d9efe JN |
1952 | if (!dev_priv->vbt.child_dev_num) |
1953 | return false; | |
1954 | ||
1955 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
cc998589 | 1956 | child = dev_priv->vbt.child_dev + i; |
951d9efe | 1957 | |
cc998589 JN |
1958 | if (child->dvo_port == port_mapping[port] && |
1959 | (child->device_type & DEVICE_TYPE_eDP_BITS) == | |
951d9efe JN |
1960 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
1961 | return true; | |
1962 | } | |
1963 | ||
1964 | return false; | |
1965 | } | |
7137aec1 | 1966 | |
cc998589 | 1967 | static bool child_dev_is_dp_dual_mode(const struct child_device_config *child, |
7a17995a | 1968 | enum port port) |
d6199256 VS |
1969 | { |
1970 | static const struct { | |
1971 | u16 dp, hdmi; | |
1972 | } port_mapping[] = { | |
1973 | /* | |
1974 | * Buggy VBTs may declare DP ports as having | |
1975 | * HDMI type dvo_port :( So let's check both. | |
1976 | */ | |
1977 | [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, }, | |
1978 | [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, }, | |
1979 | [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, }, | |
1980 | [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, }, | |
841b5ed7 | 1981 | [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, }, |
d6199256 | 1982 | }; |
d6199256 VS |
1983 | |
1984 | if (port == PORT_A || port >= ARRAY_SIZE(port_mapping)) | |
1985 | return false; | |
1986 | ||
cc998589 | 1987 | if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) != |
7a17995a | 1988 | (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS)) |
d6199256 VS |
1989 | return false; |
1990 | ||
cc998589 | 1991 | if (child->dvo_port == port_mapping[port].dp) |
7a17995a VS |
1992 | return true; |
1993 | ||
1994 | /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */ | |
cc998589 JN |
1995 | if (child->dvo_port == port_mapping[port].hdmi && |
1996 | child->aux_channel != 0) | |
7a17995a VS |
1997 | return true; |
1998 | ||
1999 | return false; | |
2000 | } | |
2001 | ||
2002 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, | |
2003 | enum port port) | |
2004 | { | |
cc998589 | 2005 | const struct child_device_config *child; |
7a17995a VS |
2006 | int i; |
2007 | ||
d6199256 | 2008 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
cc998589 | 2009 | child = dev_priv->vbt.child_dev + i; |
d6199256 | 2010 | |
cc998589 | 2011 | if (child_dev_is_dp_dual_mode(child, port)) |
d6199256 VS |
2012 | return true; |
2013 | } | |
2014 | ||
2015 | return false; | |
2016 | } | |
2017 | ||
7137aec1 JN |
2018 | /** |
2019 | * intel_bios_is_dsi_present - is DSI present in VBT | |
2020 | * @dev_priv: i915 device instance | |
2021 | * @port: port for DSI if present | |
2022 | * | |
2023 | * Return true if DSI is present, and return the port in %port. | |
2024 | */ | |
2025 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, | |
2026 | enum port *port) | |
2027 | { | |
cc998589 | 2028 | const struct child_device_config *child; |
7137aec1 JN |
2029 | u8 dvo_port; |
2030 | int i; | |
2031 | ||
2032 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
cc998589 | 2033 | child = dev_priv->vbt.child_dev + i; |
7137aec1 | 2034 | |
cc998589 | 2035 | if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) |
7137aec1 JN |
2036 | continue; |
2037 | ||
cc998589 | 2038 | dvo_port = child->dvo_port; |
7137aec1 JN |
2039 | |
2040 | switch (dvo_port) { | |
2041 | case DVO_PORT_MIPIA: | |
2042 | case DVO_PORT_MIPIC: | |
7caaef33 JN |
2043 | if (port) |
2044 | *port = dvo_port - DVO_PORT_MIPIA; | |
7137aec1 JN |
2045 | return true; |
2046 | case DVO_PORT_MIPIB: | |
2047 | case DVO_PORT_MIPID: | |
2048 | DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n", | |
2049 | port_name(dvo_port - DVO_PORT_MIPIA)); | |
2050 | break; | |
2051 | } | |
2052 | } | |
2053 | ||
2054 | return false; | |
2055 | } | |
d252bf68 SS |
2056 | |
2057 | /** | |
2058 | * intel_bios_is_port_hpd_inverted - is HPD inverted for %port | |
2059 | * @dev_priv: i915 device instance | |
2060 | * @port: port to check | |
2061 | * | |
2062 | * Return true if HPD should be inverted for %port. | |
2063 | */ | |
2064 | bool | |
2065 | intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, | |
2066 | enum port port) | |
2067 | { | |
cc998589 | 2068 | const struct child_device_config *child; |
d252bf68 SS |
2069 | int i; |
2070 | ||
cc3f90f0 | 2071 | if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv))) |
d252bf68 SS |
2072 | return false; |
2073 | ||
2074 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
cc998589 JN |
2075 | child = dev_priv->vbt.child_dev + i; |
2076 | ||
2077 | if (!child->hpd_invert) | |
d252bf68 SS |
2078 | continue; |
2079 | ||
cc998589 | 2080 | switch (child->dvo_port) { |
d252bf68 SS |
2081 | case DVO_PORT_DPA: |
2082 | case DVO_PORT_HDMIA: | |
2083 | if (port == PORT_A) | |
2084 | return true; | |
2085 | break; | |
2086 | case DVO_PORT_DPB: | |
2087 | case DVO_PORT_HDMIB: | |
2088 | if (port == PORT_B) | |
2089 | return true; | |
2090 | break; | |
2091 | case DVO_PORT_DPC: | |
2092 | case DVO_PORT_HDMIC: | |
2093 | if (port == PORT_C) | |
2094 | return true; | |
2095 | break; | |
2096 | default: | |
2097 | break; | |
2098 | } | |
2099 | } | |
2100 | ||
2101 | return false; | |
2102 | } | |
6389dd83 SS |
2103 | |
2104 | /** | |
2105 | * intel_bios_is_lspcon_present - if LSPCON is attached on %port | |
2106 | * @dev_priv: i915 device instance | |
2107 | * @port: port to check | |
2108 | * | |
2109 | * Return true if LSPCON is present on this port | |
2110 | */ | |
2111 | bool | |
2112 | intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv, | |
2113 | enum port port) | |
2114 | { | |
cc998589 | 2115 | const struct child_device_config *child; |
6389dd83 SS |
2116 | int i; |
2117 | ||
2118 | if (!HAS_LSPCON(dev_priv)) | |
2119 | return false; | |
2120 | ||
2121 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
cc998589 JN |
2122 | child = dev_priv->vbt.child_dev + i; |
2123 | ||
2124 | if (!child->lspcon) | |
6389dd83 SS |
2125 | continue; |
2126 | ||
cc998589 | 2127 | switch (child->dvo_port) { |
6389dd83 SS |
2128 | case DVO_PORT_DPA: |
2129 | case DVO_PORT_HDMIA: | |
2130 | if (port == PORT_A) | |
2131 | return true; | |
2132 | break; | |
2133 | case DVO_PORT_DPB: | |
2134 | case DVO_PORT_HDMIB: | |
2135 | if (port == PORT_B) | |
2136 | return true; | |
2137 | break; | |
2138 | case DVO_PORT_DPC: | |
2139 | case DVO_PORT_HDMIC: | |
2140 | if (port == PORT_C) | |
2141 | return true; | |
2142 | break; | |
2143 | case DVO_PORT_DPD: | |
2144 | case DVO_PORT_HDMID: | |
2145 | if (port == PORT_D) | |
2146 | return true; | |
2147 | break; | |
841b5ed7 RV |
2148 | case DVO_PORT_DPF: |
2149 | case DVO_PORT_HDMIF: | |
2150 | if (port == PORT_F) | |
2151 | return true; | |
2152 | break; | |
6389dd83 SS |
2153 | default: |
2154 | break; | |
2155 | } | |
2156 | } | |
2157 | ||
2158 | return false; | |
2159 | } |