drm/i915/bios: assume eDP is present on port A when there is no VBT
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_bios.c
CommitLineData
79e53945 1/*
39507259 2 * Copyright © 2006 Intel Corporation
79e53945
JB
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
b30581a4 27
9f0e7ff4 28#include <drm/drm_dp_helper.h>
760285e7 29#include <drm/i915_drm.h>
79e53945 30#include "i915_drv.h"
72341af4
JN
31
32#define _INTEL_BIOS_PRIVATE
33#include "intel_vbt_defs.h"
79e53945 34
dd97950a
JN
35/**
36 * DOC: Video BIOS Table (VBT)
37 *
38 * The Video BIOS Table, or VBT, provides platform and board specific
39 * configuration information to the driver that is not discoverable or available
40 * through other means. The configuration is mostly related to display
41 * hardware. The VBT is available via the ACPI OpRegion or, on older systems, in
42 * the PCI ROM.
43 *
44 * The VBT consists of a VBT Header (defined as &struct vbt_header), a BDB
45 * Header (&struct bdb_header), and a number of BIOS Data Blocks (BDB) that
46 * contain the actual configuration information. The VBT Header, and thus the
47 * VBT, begins with "$VBT" signature. The VBT Header contains the offset of the
48 * BDB Header. The data blocks are concatenated after the BDB Header. The data
49 * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of
50 * data. (Block 53, the MIPI Sequence Block is an exception.)
51 *
52 * The driver parses the VBT during load. The relevant information is stored in
53 * driver private data for ease of use, and the actual VBT is not read after
54 * that.
55 */
56
9b9d172d 57#define SLAVE_ADDR1 0x70
58#define SLAVE_ADDR2 0x72
79e53945 59
08c0888b
JN
60/* Get BDB block size given a pointer to Block ID. */
61static u32 _get_blocksize(const u8 *block_base)
62{
63 /* The MIPI Sequence Block v3+ has a separate size field. */
64 if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3)
65 return *((const u32 *)(block_base + 4));
66 else
67 return *((const u16 *)(block_base + 1));
68}
69
70/* Get BDB block size give a pointer to data after Block ID and Block Size. */
71static u32 get_blocksize(const void *block_data)
72{
73 return _get_blocksize(block_data - 3);
74}
75
e8ef3b4c
JN
76static const void *
77find_section(const void *_bdb, int section_id)
79e53945 78{
e8ef3b4c
JN
79 const struct bdb_header *bdb = _bdb;
80 const u8 *base = _bdb;
79e53945 81 int index = 0;
cd67d226 82 u32 total, current_size;
79e53945
JB
83 u8 current_id;
84
85 /* skip to first section */
86 index += bdb->header_size;
87 total = bdb->bdb_size;
88
89 /* walk the sections looking for section_id */
d1f13fd2 90 while (index + 3 < total) {
79e53945 91 current_id = *(base + index);
08c0888b
JN
92 current_size = _get_blocksize(base + index);
93 index += 3;
cd67d226 94
d1f13fd2
CW
95 if (index + current_size > total)
96 return NULL;
97
79e53945
JB
98 if (current_id == section_id)
99 return base + index;
d1f13fd2 100
79e53945
JB
101 index += current_size;
102 }
103
104 return NULL;
105}
106
79e53945 107static void
88631706 108fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
99834ea4 109 const struct lvds_dvo_timing *dvo_timing)
88631706
ML
110{
111 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
112 dvo_timing->hactive_lo;
113 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
114 ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
115 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
ce2e87b4
VT
116 ((dvo_timing->hsync_pulse_width_hi << 8) |
117 dvo_timing->hsync_pulse_width_lo);
88631706
ML
118 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
119 ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
120
121 panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
122 dvo_timing->vactive_lo;
123 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
ce2e87b4 124 ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo);
88631706 125 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
ce2e87b4
VT
126 ((dvo_timing->vsync_pulse_width_hi << 4) |
127 dvo_timing->vsync_pulse_width_lo);
88631706
ML
128 panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
129 ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
130 panel_fixed_mode->clock = dvo_timing->clock * 10;
131 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
132
9bc35499
AJ
133 if (dvo_timing->hsync_positive)
134 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
135 else
136 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
137
138 if (dvo_timing->vsync_positive)
139 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
140 else
141 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
142
df457245
VS
143 panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) |
144 dvo_timing->himage_lo;
145 panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) |
146 dvo_timing->vimage_lo;
147
88631706
ML
148 /* Some VBTs have bogus h/vtotal values */
149 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
150 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
151 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
152 panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
153
154 drm_mode_set_name(panel_fixed_mode);
155}
156
99834ea4
CW
157static const struct lvds_dvo_timing *
158get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data,
159 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs,
160 int index)
161{
162 /*
163 * the size of fp_timing varies on the different platform.
164 * So calculate the DVO timing relative offset in LVDS data
165 * entry to get the DVO timing entry
166 */
167
168 int lfp_data_size =
169 lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset -
170 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
171 int dvo_timing_offset =
172 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
173 lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
174 char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index;
175
176 return (struct lvds_dvo_timing *)(entry + dvo_timing_offset);
177}
178
b0354385
TI
179/* get lvds_fp_timing entry
180 * this function may return NULL if the corresponding entry is invalid
181 */
182static const struct lvds_fp_timing *
183get_lvds_fp_timing(const struct bdb_header *bdb,
184 const struct bdb_lvds_lfp_data *data,
185 const struct bdb_lvds_lfp_data_ptrs *ptrs,
186 int index)
187{
188 size_t data_ofs = (const u8 *)data - (const u8 *)bdb;
189 u16 data_size = ((const u16 *)data)[-1]; /* stored in header */
190 size_t ofs;
191
192 if (index >= ARRAY_SIZE(ptrs->ptr))
193 return NULL;
194 ofs = ptrs->ptr[index].fp_timing_offset;
195 if (ofs < data_ofs ||
196 ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size)
197 return NULL;
198 return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
199}
200
88631706
ML
201/* Try to find integrated panel data */
202static void
203parse_lfp_panel_data(struct drm_i915_private *dev_priv,
dcb58a40 204 const struct bdb_header *bdb)
79e53945 205{
99834ea4
CW
206 const struct bdb_lvds_options *lvds_options;
207 const struct bdb_lvds_lfp_data *lvds_lfp_data;
208 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
209 const struct lvds_dvo_timing *panel_dvo_timing;
b0354385 210 const struct lvds_fp_timing *fp_timing;
79e53945 211 struct drm_display_mode *panel_fixed_mode;
3e845c7a 212 int panel_type;
c329a4ec 213 int drrs_mode;
a0562819 214 int ret;
79e53945 215
79e53945
JB
216 lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
217 if (!lvds_options)
218 return;
219
41aa3448 220 dev_priv->vbt.lvds_dither = lvds_options->pixel_dither;
a0562819 221
6f9f4b7a 222 ret = intel_opregion_get_panel_type(dev_priv);
a0562819
VS
223 if (ret >= 0) {
224 WARN_ON(ret > 0xf);
225 panel_type = ret;
226 DRM_DEBUG_KMS("Panel type: %d (OpRegion)\n", panel_type);
227 } else {
228 if (lvds_options->panel_type > 0xf) {
229 DRM_DEBUG_KMS("Invalid VBT panel type 0x%x\n",
230 lvds_options->panel_type);
231 return;
232 }
233 panel_type = lvds_options->panel_type;
234 DRM_DEBUG_KMS("Panel type: %d (VBT)\n", panel_type);
eeeebea6 235 }
6a04002b 236
3e845c7a 237 dev_priv->vbt.panel_type = panel_type;
79e53945 238
83a7280e
PB
239 drrs_mode = (lvds_options->dps_panel_type_bits
240 >> (panel_type * 2)) & MODE_MASK;
241 /*
242 * VBT has static DRRS = 0 and seamless DRRS = 2.
243 * The below piece of code is required to adjust vbt.drrs_type
244 * to match the enum drrs_support_type.
245 */
246 switch (drrs_mode) {
247 case 0:
248 dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
249 DRM_DEBUG_KMS("DRRS supported mode is static\n");
250 break;
251 case 2:
252 dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
253 DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
254 break;
255 default:
256 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
257 DRM_DEBUG_KMS("DRRS not supported (VBT input)\n");
258 break;
259 }
260
79e53945
JB
261 lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
262 if (!lvds_lfp_data)
263 return;
264
1b16de0b
JB
265 lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
266 if (!lvds_lfp_data_ptrs)
267 return;
268
99834ea4
CW
269 panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
270 lvds_lfp_data_ptrs,
3e845c7a 271 panel_type);
79e53945 272
9a298b2a 273 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
6edc3242
CW
274 if (!panel_fixed_mode)
275 return;
79e53945 276
99834ea4 277 fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
79e53945 278
41aa3448 279 dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
79e53945 280
28c97730 281 DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");
88631706 282 drm_mode_debug_printmodeline(panel_fixed_mode);
37df9673 283
b0354385
TI
284 fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data,
285 lvds_lfp_data_ptrs,
3e845c7a 286 panel_type);
b0354385
TI
287 if (fp_timing) {
288 /* check the resolution, just to be sure */
289 if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
290 fp_timing->y_res == panel_fixed_mode->vdisplay) {
41aa3448 291 dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val;
b0354385 292 DRM_DEBUG_KMS("VBT initial LVDS value %x\n",
41aa3448 293 dev_priv->vbt.bios_lvds_val);
b0354385
TI
294 }
295 }
88631706
ML
296}
297
f00076d2 298static void
dcb58a40
JN
299parse_lfp_backlight(struct drm_i915_private *dev_priv,
300 const struct bdb_header *bdb)
f00076d2
JN
301{
302 const struct bdb_lfp_backlight_data *backlight_data;
303 const struct bdb_lfp_backlight_data_entry *entry;
3e845c7a 304 int panel_type = dev_priv->vbt.panel_type;
f00076d2
JN
305
306 backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
307 if (!backlight_data)
308 return;
309
310 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) {
311 DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n",
312 backlight_data->entry_size);
313 return;
314 }
315
316 entry = &backlight_data->data[panel_type];
317
39fbc9c8
JN
318 dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
319 if (!dev_priv->vbt.backlight.present) {
320 DRM_DEBUG_KMS("PWM backlight not present in VBT (type %u)\n",
321 entry->type);
322 return;
323 }
324
9a41e17d
D
325 dev_priv->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
326 if (bdb->version >= 191 &&
327 get_blocksize(backlight_data) >= sizeof(*backlight_data)) {
328 const struct bdb_lfp_backlight_control_method *method;
329
330 method = &backlight_data->backlight_control[panel_type];
331 dev_priv->vbt.backlight.type = method->type;
add03379 332 dev_priv->vbt.backlight.controller = method->controller;
9a41e17d
D
333 }
334
f00076d2
JN
335 dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
336 dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
1de6068e 337 dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
f00076d2 338 DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, "
add03379 339 "active %s, min brightness %u, level %u, controller %u\n",
f00076d2
JN
340 dev_priv->vbt.backlight.pwm_freq_hz,
341 dev_priv->vbt.backlight.active_low_pwm ? "low" : "high",
1de6068e 342 dev_priv->vbt.backlight.min_brightness,
add03379
VS
343 backlight_data->level[panel_type],
344 dev_priv->vbt.backlight.controller);
f00076d2
JN
345}
346
88631706
ML
347/* Try to find sdvo panel data */
348static void
349parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
dcb58a40 350 const struct bdb_header *bdb)
88631706 351{
e8ef3b4c 352 const struct lvds_dvo_timing *dvo_timing;
88631706 353 struct drm_display_mode *panel_fixed_mode;
5a1e5b6c 354 int index;
79e53945 355
4f044a88 356 index = i915_modparams.vbt_sdvo_panel_type;
c10e408a
MF
357 if (index == -2) {
358 DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n");
359 return;
360 }
361
5a1e5b6c 362 if (index == -1) {
e8ef3b4c 363 const struct bdb_sdvo_lvds_options *sdvo_lvds_options;
5a1e5b6c
CW
364
365 sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
366 if (!sdvo_lvds_options)
367 return;
368
369 index = sdvo_lvds_options->panel_type;
370 }
88631706
ML
371
372 dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);
373 if (!dvo_timing)
374 return;
375
9a298b2a 376 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
88631706
ML
377 if (!panel_fixed_mode)
378 return;
379
5a1e5b6c 380 fill_detail_timing_data(panel_fixed_mode, dvo_timing + index);
88631706 381
41aa3448 382 dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
79e53945 383
5a1e5b6c
CW
384 DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n");
385 drm_mode_debug_printmodeline(panel_fixed_mode);
79e53945
JB
386}
387
98f3a1dc 388static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
9a4114ff
BF
389 bool alternate)
390{
c56b89f1 391 switch (INTEL_GEN(dev_priv)) {
9a4114ff 392 case 2:
e91e941b 393 return alternate ? 66667 : 48000;
9a4114ff
BF
394 case 3:
395 case 4:
e91e941b 396 return alternate ? 100000 : 96000;
9a4114ff 397 default:
e91e941b 398 return alternate ? 100000 : 120000;
9a4114ff
BF
399 }
400}
401
79e53945
JB
402static void
403parse_general_features(struct drm_i915_private *dev_priv,
dcb58a40 404 const struct bdb_header *bdb)
79e53945 405{
e8ef3b4c 406 const struct bdb_general_features *general;
79e53945 407
79e53945 408 general = find_section(bdb, BDB_GENERAL_FEATURES);
34957e8c
JN
409 if (!general)
410 return;
411
412 dev_priv->vbt.int_tv_support = general->int_tv_support;
413 /* int_crt_support can't be trusted on earlier platforms */
414 if (bdb->version >= 155 &&
415 (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv)))
416 dev_priv->vbt.int_crt_support = general->int_crt_support;
417 dev_priv->vbt.lvds_use_ssc = general->enable_ssc;
418 dev_priv->vbt.lvds_ssc_freq =
419 intel_bios_ssc_frequency(dev_priv, general->ssc_freq);
420 dev_priv->vbt.display_clock_mode = general->display_clock_mode;
421 dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
c1cd5b24
VS
422 if (bdb->version >= 181) {
423 dev_priv->vbt.orientation = general->rotate_180 ?
424 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP :
425 DRM_MODE_PANEL_ORIENTATION_NORMAL;
426 } else {
427 dev_priv->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
428 }
34957e8c
JN
429 DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
430 dev_priv->vbt.int_tv_support,
431 dev_priv->vbt.int_crt_support,
432 dev_priv->vbt.lvds_use_ssc,
433 dev_priv->vbt.lvds_ssc_freq,
434 dev_priv->vbt.display_clock_mode,
435 dev_priv->vbt.fdi_rx_polarity_inverted);
79e53945
JB
436}
437
cc998589 438static const struct child_device_config *
e192839e 439child_device_ptr(const struct bdb_general_definitions *defs, int i)
90e4f159 440{
e192839e 441 return (const void *) &defs->devices[i * defs->child_dev_size];
90e4f159
VS
442}
443
9b9d172d 444static void
0ead5f81 445parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)
9b9d172d 446{
e192839e 447 struct sdvo_device_mapping *mapping;
cc998589 448 const struct child_device_config *child;
0ebdabe6 449 int i, count = 0;
6cc38aca
JN
450
451 /*
0ebdabe6
JN
452 * Only parse SDVO mappings on gens that could have SDVO. This isn't
453 * accurate and doesn't have to be, as long as it's not too strict.
9b9d172d 454 */
00690008 455 if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
0ebdabe6 456 DRM_DEBUG_KMS("Skipping SDVO device mapping\n");
9b9d172d 457 return;
458 }
0ebdabe6
JN
459
460 for (i = 0, count = 0; i < dev_priv->vbt.child_dev_num; i++) {
461 child = dev_priv->vbt.child_dev + i;
462
6cc38aca
JN
463 if (child->slave_addr != SLAVE_ADDR1 &&
464 child->slave_addr != SLAVE_ADDR2) {
9b9d172d 465 /*
466 * If the slave address is neither 0x70 nor 0x72,
467 * it is not a SDVO device. Skip it.
468 */
469 continue;
470 }
6cc38aca
JN
471 if (child->dvo_port != DEVICE_PORT_DVOB &&
472 child->dvo_port != DEVICE_PORT_DVOC) {
9b9d172d 473 /* skip the incorrect SDVO port */
0206e353 474 DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n");
9b9d172d 475 continue;
476 }
28c97730 477 DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
6cc38aca
JN
478 " %s port\n",
479 child->slave_addr,
480 (child->dvo_port == DEVICE_PORT_DVOB) ?
481 "SDVOB" : "SDVOC");
e192839e
JN
482 mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1];
483 if (!mapping->initialized) {
484 mapping->dvo_port = child->dvo_port;
485 mapping->slave_addr = child->slave_addr;
486 mapping->dvo_wiring = child->dvo_wiring;
487 mapping->ddc_pin = child->ddc_pin;
488 mapping->i2c_pin = child->i2c_pin;
489 mapping->initialized = 1;
46eb3036 490 DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",
e192839e
JN
491 mapping->dvo_port,
492 mapping->slave_addr,
493 mapping->dvo_wiring,
494 mapping->ddc_pin,
495 mapping->i2c_pin);
9b9d172d 496 } else {
28c97730 497 DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
9b9d172d 498 "two SDVO device.\n");
499 }
6cc38aca 500 if (child->slave2_addr) {
9b9d172d 501 /* Maybe this is a SDVO device with multiple inputs */
502 /* And the mapping info is not added */
28c97730
ZY
503 DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"
504 " is a SDVO device with multiple inputs.\n");
9b9d172d 505 }
506 count++;
507 }
508
509 if (!count) {
510 /* No SDVO device info is found */
28c97730 511 DRM_DEBUG_KMS("No SDVO device info is found in VBT\n");
9b9d172d 512 }
9b9d172d 513}
32f9d658
ZW
514
515static void
516parse_driver_features(struct drm_i915_private *dev_priv,
dcb58a40 517 const struct bdb_header *bdb)
32f9d658 518{
e8ef3b4c 519 const struct bdb_driver_features *driver;
32f9d658 520
32f9d658 521 driver = find_section(bdb, BDB_DRIVER_FEATURES);
652c393a
JB
522 if (!driver)
523 return;
524
ca3b3fa3
VS
525 if (INTEL_GEN(dev_priv) >= 5) {
526 /*
527 * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS
528 * to mean "eDP". The VBT spec doesn't agree with that
529 * interpretation, but real world VBTs seem to.
530 */
531 if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS)
532 dev_priv->vbt.int_lvds_support = 0;
533 } else {
534 /*
535 * FIXME it's not clear which BDB version has the LVDS config
536 * bits defined. Revision history in the VBT spec says:
537 * "0.92 | Add two definitions for VBT value of LVDS Active
538 * Config (00b and 11b values defined) | 06/13/2005"
539 * but does not the specify the BDB version.
540 *
541 * So far version 134 (on i945gm) is the oldest VBT observed
542 * in the wild with the bits correctly populated. Version
543 * 108 (on i85x) does not have the bits correctly populated.
544 */
545 if (bdb->version >= 134 &&
546 driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS &&
547 driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
548 dev_priv->vbt.int_lvds_support = 0;
549 }
652c393a 550
83a7280e
PB
551 DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
552 /*
553 * If DRRS is not supported, drrs_type has to be set to 0.
554 * This is because, VBT is configured in such a way that
555 * static DRRS is 0 and DRRS not supported is represented by
556 * driver->drrs_enabled=false
557 */
558 if (!driver->drrs_enabled)
559 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
2bdd045e 560 dev_priv->vbt.psr.enable = driver->psr_enabled;
32f9d658
ZW
561}
562
500a8cc4 563static void
dcb58a40 564parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
500a8cc4 565{
e8ef3b4c
JN
566 const struct bdb_edp *edp;
567 const struct edp_power_seq *edp_pps;
058727ee 568 const struct edp_fast_link_params *edp_link_params;
3e845c7a 569 int panel_type = dev_priv->vbt.panel_type;
500a8cc4
ZW
570
571 edp = find_section(bdb, BDB_EDP);
5255e2f8 572 if (!edp)
500a8cc4 573 return;
500a8cc4
ZW
574
575 switch ((edp->color_depth >> (panel_type * 2)) & 3) {
576 case EDP_18BPP:
6aa23e65 577 dev_priv->vbt.edp.bpp = 18;
500a8cc4
ZW
578 break;
579 case EDP_24BPP:
6aa23e65 580 dev_priv->vbt.edp.bpp = 24;
500a8cc4
ZW
581 break;
582 case EDP_30BPP:
6aa23e65 583 dev_priv->vbt.edp.bpp = 30;
500a8cc4
ZW
584 break;
585 }
5ceb0f9b 586
9f0e7ff4
JB
587 /* Get the eDP sequencing and link info */
588 edp_pps = &edp->power_seqs[panel_type];
058727ee 589 edp_link_params = &edp->fast_link_params[panel_type];
5ceb0f9b 590
6aa23e65 591 dev_priv->vbt.edp.pps = *edp_pps;
5ceb0f9b 592
e13e2b2c
JN
593 switch (edp_link_params->rate) {
594 case EDP_RATE_1_62:
6aa23e65 595 dev_priv->vbt.edp.rate = DP_LINK_BW_1_62;
e13e2b2c
JN
596 break;
597 case EDP_RATE_2_7:
6aa23e65 598 dev_priv->vbt.edp.rate = DP_LINK_BW_2_7;
e13e2b2c
JN
599 break;
600 default:
601 DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n",
602 edp_link_params->rate);
603 break;
604 }
605
9f0e7ff4 606 switch (edp_link_params->lanes) {
e13e2b2c 607 case EDP_LANE_1:
6aa23e65 608 dev_priv->vbt.edp.lanes = 1;
9f0e7ff4 609 break;
e13e2b2c 610 case EDP_LANE_2:
6aa23e65 611 dev_priv->vbt.edp.lanes = 2;
9f0e7ff4 612 break;
e13e2b2c 613 case EDP_LANE_4:
6aa23e65 614 dev_priv->vbt.edp.lanes = 4;
9f0e7ff4 615 break;
e13e2b2c
JN
616 default:
617 DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n",
618 edp_link_params->lanes);
619 break;
9f0e7ff4 620 }
e13e2b2c 621
9f0e7ff4 622 switch (edp_link_params->preemphasis) {
e13e2b2c 623 case EDP_PREEMPHASIS_NONE:
6aa23e65 624 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
9f0e7ff4 625 break;
e13e2b2c 626 case EDP_PREEMPHASIS_3_5dB:
6aa23e65 627 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
9f0e7ff4 628 break;
e13e2b2c 629 case EDP_PREEMPHASIS_6dB:
6aa23e65 630 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
9f0e7ff4 631 break;
e13e2b2c 632 case EDP_PREEMPHASIS_9_5dB:
6aa23e65 633 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
9f0e7ff4 634 break;
e13e2b2c
JN
635 default:
636 DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
637 edp_link_params->preemphasis);
638 break;
9f0e7ff4 639 }
e13e2b2c 640
9f0e7ff4 641 switch (edp_link_params->vswing) {
e13e2b2c 642 case EDP_VSWING_0_4V:
6aa23e65 643 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
9f0e7ff4 644 break;
e13e2b2c 645 case EDP_VSWING_0_6V:
6aa23e65 646 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
9f0e7ff4 647 break;
e13e2b2c 648 case EDP_VSWING_0_8V:
6aa23e65 649 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
9f0e7ff4 650 break;
e13e2b2c 651 case EDP_VSWING_1_2V:
6aa23e65 652 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
9f0e7ff4 653 break;
e13e2b2c
JN
654 default:
655 DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
656 edp_link_params->vswing);
657 break;
9f0e7ff4 658 }
9a57f5bb
SJ
659
660 if (bdb->version >= 173) {
0ede0141 661 u8 vswing;
9a57f5bb 662
9e458034 663 /* Don't read from VBT if module parameter has valid value*/
4f044a88
MW
664 if (i915_modparams.edp_vswing) {
665 dev_priv->vbt.edp.low_vswing =
666 i915_modparams.edp_vswing == 1;
9e458034
SJ
667 } else {
668 vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
06411f08 669 dev_priv->vbt.edp.low_vswing = vswing == 0;
9e458034 670 }
9a57f5bb 671 }
500a8cc4
ZW
672}
673
bfd7ebda 674static void
dcb58a40 675parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
bfd7ebda 676{
e8ef3b4c
JN
677 const struct bdb_psr *psr;
678 const struct psr_table *psr_table;
3e845c7a 679 int panel_type = dev_priv->vbt.panel_type;
bfd7ebda
RV
680
681 psr = find_section(bdb, BDB_PSR);
682 if (!psr) {
683 DRM_DEBUG_KMS("No PSR BDB found.\n");
684 return;
685 }
686
687 psr_table = &psr->psr_table[panel_type];
688
689 dev_priv->vbt.psr.full_link = psr_table->full_link;
690 dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
691
692 /* Allowed VBT values goes from 0 to 15 */
693 dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
694 psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
695
696 switch (psr_table->lines_to_wait) {
697 case 0:
698 dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
699 break;
700 case 1:
701 dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
702 break;
703 case 2:
704 dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
705 break;
706 case 3:
707 dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
708 break;
709 default:
710 DRM_DEBUG_KMS("VBT has unknown PSR lines to wait %u\n",
711 psr_table->lines_to_wait);
712 break;
713 }
714
77312ae8
VN
715 /*
716 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
717 * Old decimal value is wake up time in multiples of 100 us.
718 */
0fdb3f75
VN
719 if (bdb->version >= 205 &&
720 (IS_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) ||
721 INTEL_GEN(dev_priv) >= 10)) {
77312ae8
VN
722 switch (psr_table->tp1_wakeup_time) {
723 case 0:
724 dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
725 break;
726 case 1:
727 dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
728 break;
729 case 3:
730 dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
731 break;
732 default:
733 DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
734 psr_table->tp1_wakeup_time);
735 /* fallthrough */
736 case 2:
737 dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
738 break;
739 }
740
741 switch (psr_table->tp2_tp3_wakeup_time) {
742 case 0:
743 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
744 break;
745 case 1:
746 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
747 break;
748 case 3:
c238ad62 749 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 0;
77312ae8
VN
750 break;
751 default:
752 DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
753 psr_table->tp2_tp3_wakeup_time);
754 /* fallthrough */
755 case 2:
756 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
757 break;
758 }
759 } else {
760 dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
761 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
762 }
bfd7ebda
RV
763}
764
46e58320
MC
765static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
766 u16 version, enum port port)
767{
768 if (!dev_priv->vbt.dsi.config->dual_link || version < 197) {
769 dev_priv->vbt.dsi.bl_ports = BIT(port);
770 if (dev_priv->vbt.dsi.config->cabc_supported)
771 dev_priv->vbt.dsi.cabc_ports = BIT(port);
772
46e58320
MC
773 return;
774 }
775
776 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
777 case DL_DCS_PORT_A:
778 dev_priv->vbt.dsi.bl_ports = BIT(PORT_A);
779 break;
780 case DL_DCS_PORT_C:
781 dev_priv->vbt.dsi.bl_ports = BIT(PORT_C);
782 break;
783 default:
784 case DL_DCS_PORT_A_AND_C:
785 dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
786 break;
787 }
788
789 if (!dev_priv->vbt.dsi.config->cabc_supported)
790 return;
791
792 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
793 case DL_DCS_PORT_A:
794 dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A);
795 break;
796 case DL_DCS_PORT_C:
797 dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C);
798 break;
799 default:
800 case DL_DCS_PORT_A_AND_C:
801 dev_priv->vbt.dsi.cabc_ports =
802 BIT(PORT_A) | BIT(PORT_C);
803 break;
804 }
805}
806
d17c5443 807static void
0f8689f5
JN
808parse_mipi_config(struct drm_i915_private *dev_priv,
809 const struct bdb_header *bdb)
d17c5443 810{
e8ef3b4c 811 const struct bdb_mipi_config *start;
e8ef3b4c
JN
812 const struct mipi_config *config;
813 const struct mipi_pps_data *pps;
3e845c7a 814 int panel_type = dev_priv->vbt.panel_type;
46e58320 815 enum port port;
d3b542fc 816
3e6bd011 817 /* parse MIPI blocks only if LFP type is MIPI */
46e58320 818 if (!intel_bios_is_dsi_present(dev_priv, &port))
3e6bd011
SK
819 return;
820
d3b542fc
SK
821 /* Initialize this to undefined indicating no generic MIPI support */
822 dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
823
824 /* Block #40 is already parsed and panel_fixed_mode is
825 * stored in dev_priv->lfp_lvds_vbt_mode
826 * resuse this when needed
827 */
d17c5443 828
d3b542fc
SK
829 /* Parse #52 for panel index used from panel_type already
830 * parsed
831 */
832 start = find_section(bdb, BDB_MIPI_CONFIG);
833 if (!start) {
834 DRM_DEBUG_KMS("No MIPI config BDB found");
d17c5443
SK
835 return;
836 }
837
d3b542fc
SK
838 DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n",
839 panel_type);
840
841 /*
842 * get hold of the correct configuration block and pps data as per
843 * the panel_type as index
844 */
845 config = &start->config[panel_type];
846 pps = &start->pps[panel_type];
847
848 /* store as of now full data. Trim when we realise all is not needed */
849 dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
850 if (!dev_priv->vbt.dsi.config)
851 return;
852
853 dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
854 if (!dev_priv->vbt.dsi.pps) {
855 kfree(dev_priv->vbt.dsi.config);
856 return;
857 }
858
46e58320 859 parse_dsi_backlight_ports(dev_priv, bdb->version, port);
9f7c5b17 860
c1cd5b24
VS
861 /* FIXME is the 90 vs. 270 correct? */
862 switch (config->rotation) {
863 case ENABLE_ROTATION_0:
864 /*
865 * Most (all?) VBTs claim 0 degrees despite having
866 * an upside down panel, thus we do not trust this.
867 */
868 dev_priv->vbt.dsi.orientation =
869 DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
870 break;
871 case ENABLE_ROTATION_90:
872 dev_priv->vbt.dsi.orientation =
873 DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;
874 break;
875 case ENABLE_ROTATION_180:
876 dev_priv->vbt.dsi.orientation =
877 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
878 break;
879 case ENABLE_ROTATION_270:
880 dev_priv->vbt.dsi.orientation =
881 DRM_MODE_PANEL_ORIENTATION_LEFT_UP;
882 break;
883 }
884
d3b542fc 885 /* We have mandatory mipi config blocks. Initialize as generic panel */
ea9a6baf 886 dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
0f8689f5
JN
887}
888
5db72099
JN
889/* Find the sequence block and size for the given panel. */
890static const u8 *
891find_panel_sequence_block(const struct bdb_mipi_sequence *sequence,
2a33d934 892 u16 panel_id, u32 *seq_size)
5db72099
JN
893{
894 u32 total = get_blocksize(sequence);
895 const u8 *data = &sequence->data[0];
896 u8 current_id;
2a33d934
JN
897 u32 current_size;
898 int header_size = sequence->version >= 3 ? 5 : 3;
5db72099
JN
899 int index = 0;
900 int i;
901
2a33d934
JN
902 /* skip new block size */
903 if (sequence->version >= 3)
904 data += 4;
905
906 for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) {
907 if (index + header_size > total) {
908 DRM_ERROR("Invalid sequence block (header)\n");
909 return NULL;
910 }
911
5db72099 912 current_id = *(data + index);
2a33d934
JN
913 if (sequence->version >= 3)
914 current_size = *((const u32 *)(data + index + 1));
915 else
916 current_size = *((const u16 *)(data + index + 1));
5db72099 917
2a33d934 918 index += header_size;
5db72099
JN
919
920 if (index + current_size > total) {
921 DRM_ERROR("Invalid sequence block\n");
922 return NULL;
923 }
924
925 if (current_id == panel_id) {
926 *seq_size = current_size;
927 return data + index;
928 }
929
930 index += current_size;
931 }
932
933 DRM_ERROR("Sequence block detected but no valid configuration\n");
934
935 return NULL;
936}
937
8d3ed2f3
JN
938static int goto_next_sequence(const u8 *data, int index, int total)
939{
940 u16 len;
941
942 /* Skip Sequence Byte. */
943 for (index = index + 1; index < total; index += len) {
944 u8 operation_byte = *(data + index);
945 index++;
946
947 switch (operation_byte) {
948 case MIPI_SEQ_ELEM_END:
949 return index;
950 case MIPI_SEQ_ELEM_SEND_PKT:
951 if (index + 4 > total)
952 return 0;
953
954 len = *((const u16 *)(data + index + 2)) + 4;
955 break;
956 case MIPI_SEQ_ELEM_DELAY:
957 len = 4;
958 break;
959 case MIPI_SEQ_ELEM_GPIO:
960 len = 2;
961 break;
f4d64936
JN
962 case MIPI_SEQ_ELEM_I2C:
963 if (index + 7 > total)
964 return 0;
965 len = *(data + index + 6) + 7;
966 break;
8d3ed2f3
JN
967 default:
968 DRM_ERROR("Unknown operation byte\n");
969 return 0;
970 }
971 }
972
973 return 0;
974}
975
2a33d934
JN
976static int goto_next_sequence_v3(const u8 *data, int index, int total)
977{
978 int seq_end;
979 u16 len;
6765bd6d 980 u32 size_of_sequence;
2a33d934
JN
981
982 /*
983 * Could skip sequence based on Size of Sequence alone, but also do some
984 * checking on the structure.
985 */
986 if (total < 5) {
987 DRM_ERROR("Too small sequence size\n");
988 return 0;
989 }
990
6765bd6d
JN
991 /* Skip Sequence Byte. */
992 index++;
993
994 /*
995 * Size of Sequence. Excludes the Sequence Byte and the size itself,
996 * includes MIPI_SEQ_ELEM_END byte, excludes the final MIPI_SEQ_END
997 * byte.
998 */
0ede0141 999 size_of_sequence = *((const u32 *)(data + index));
6765bd6d
JN
1000 index += 4;
1001
1002 seq_end = index + size_of_sequence;
2a33d934
JN
1003 if (seq_end > total) {
1004 DRM_ERROR("Invalid sequence size\n");
1005 return 0;
1006 }
1007
6765bd6d 1008 for (; index < total; index += len) {
2a33d934
JN
1009 u8 operation_byte = *(data + index);
1010 index++;
1011
1012 if (operation_byte == MIPI_SEQ_ELEM_END) {
1013 if (index != seq_end) {
1014 DRM_ERROR("Invalid element structure\n");
1015 return 0;
1016 }
1017 return index;
1018 }
1019
1020 len = *(data + index);
1021 index++;
1022
1023 /*
1024 * FIXME: Would be nice to check elements like for v1/v2 in
1025 * goto_next_sequence() above.
1026 */
1027 switch (operation_byte) {
1028 case MIPI_SEQ_ELEM_SEND_PKT:
1029 case MIPI_SEQ_ELEM_DELAY:
1030 case MIPI_SEQ_ELEM_GPIO:
1031 case MIPI_SEQ_ELEM_I2C:
1032 case MIPI_SEQ_ELEM_SPI:
1033 case MIPI_SEQ_ELEM_PMIC:
1034 break;
1035 default:
1036 DRM_ERROR("Unknown operation byte %u\n",
1037 operation_byte);
1038 break;
1039 }
1040 }
1041
1042 return 0;
1043}
1044
fb38e7ad
HG
1045/*
1046 * Get len of pre-fixed deassert fragment from a v1 init OTP sequence,
1047 * skip all delay + gpio operands and stop at the first DSI packet op.
1048 */
1049static int get_init_otp_deassert_fragment_len(struct drm_i915_private *dev_priv)
1050{
1051 const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
1052 int index, len;
1053
1054 if (WARN_ON(!data || dev_priv->vbt.dsi.seq_version != 1))
1055 return 0;
1056
1057 /* index = 1 to skip sequence byte */
1058 for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) {
1059 switch (data[index]) {
1060 case MIPI_SEQ_ELEM_SEND_PKT:
1061 return index == 1 ? 0 : index;
1062 case MIPI_SEQ_ELEM_DELAY:
1063 len = 5; /* 1 byte for operand + uint32 */
1064 break;
1065 case MIPI_SEQ_ELEM_GPIO:
1066 len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */
1067 break;
1068 default:
1069 return 0;
1070 }
1071 }
1072
1073 return 0;
1074}
1075
1076/*
1077 * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence.
1078 * The deassert must be done before calling intel_dsi_device_ready, so for
1079 * these devices we split the init OTP sequence into a deassert sequence and
1080 * the actual init OTP part.
1081 */
1082static void fixup_mipi_sequences(struct drm_i915_private *dev_priv)
1083{
1084 u8 *init_otp;
1085 int len;
1086
1087 /* Limit this to VLV for now. */
1088 if (!IS_VALLEYVIEW(dev_priv))
1089 return;
1090
1091 /* Limit this to v1 vid-mode sequences */
1092 if (dev_priv->vbt.dsi.config->is_cmd_mode ||
1093 dev_priv->vbt.dsi.seq_version != 1)
1094 return;
1095
1096 /* Only do this if there are otp and assert seqs and no deassert seq */
1097 if (!dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] ||
1098 !dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] ||
1099 dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET])
1100 return;
1101
1102 /* The deassert-sequence ends at the first DSI packet */
1103 len = get_init_otp_deassert_fragment_len(dev_priv);
1104 if (!len)
1105 return;
1106
1107 DRM_DEBUG_KMS("Using init OTP fragment to deassert reset\n");
1108
1109 /* Copy the fragment, update seq byte and terminate it */
1110 init_otp = (u8 *)dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
1111 dev_priv->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL);
1112 if (!dev_priv->vbt.dsi.deassert_seq)
1113 return;
1114 dev_priv->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET;
1115 dev_priv->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END;
1116 /* Use the copy for deassert */
1117 dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] =
1118 dev_priv->vbt.dsi.deassert_seq;
1119 /* Replace the last byte of the fragment with init OTP seq byte */
1120 init_otp[len - 1] = MIPI_SEQ_INIT_OTP;
1121 /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */
1122 dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1;
1123}
1124
0f8689f5
JN
1125static void
1126parse_mipi_sequence(struct drm_i915_private *dev_priv,
1127 const struct bdb_header *bdb)
1128{
3e845c7a 1129 int panel_type = dev_priv->vbt.panel_type;
0f8689f5
JN
1130 const struct bdb_mipi_sequence *sequence;
1131 const u8 *seq_data;
2a33d934 1132 u32 seq_size;
0f8689f5 1133 u8 *data;
8d3ed2f3 1134 int index = 0;
0f8689f5
JN
1135
1136 /* Only our generic panel driver uses the sequence block. */
1137 if (dev_priv->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID)
1138 return;
d3b542fc 1139
d3b542fc
SK
1140 sequence = find_section(bdb, BDB_MIPI_SEQUENCE);
1141 if (!sequence) {
1142 DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n");
1143 return;
1144 }
1145
cd67d226 1146 /* Fail gracefully for forward incompatible sequence block. */
2a33d934
JN
1147 if (sequence->version >= 4) {
1148 DRM_ERROR("Unable to parse MIPI Sequence Block v%u\n",
1149 sequence->version);
cd67d226
JN
1150 return;
1151 }
1152
2a33d934 1153 DRM_DEBUG_DRIVER("Found MIPI sequence block v%u\n", sequence->version);
d3b542fc 1154
5db72099
JN
1155 seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size);
1156 if (!seq_data)
d3b542fc 1157 return;
d3b542fc 1158
8d3ed2f3
JN
1159 data = kmemdup(seq_data, seq_size, GFP_KERNEL);
1160 if (!data)
d3b542fc
SK
1161 return;
1162
8d3ed2f3
JN
1163 /* Parse the sequences, store pointers to each sequence. */
1164 for (;;) {
1165 u8 seq_id = *(data + index);
1166 if (seq_id == MIPI_SEQ_END)
1167 break;
d3b542fc 1168
8d3ed2f3
JN
1169 if (seq_id >= MIPI_SEQ_MAX) {
1170 DRM_ERROR("Unknown sequence %u\n", seq_id);
d3b542fc
SK
1171 goto err;
1172 }
1173
4b4f497e
JN
1174 /* Log about presence of sequences we won't run. */
1175 if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF)
1176 DRM_DEBUG_KMS("Unsupported sequence %u\n", seq_id);
1177
8d3ed2f3 1178 dev_priv->vbt.dsi.sequence[seq_id] = data + index;
d3b542fc 1179
2a33d934
JN
1180 if (sequence->version >= 3)
1181 index = goto_next_sequence_v3(data, index, seq_size);
1182 else
1183 index = goto_next_sequence(data, index, seq_size);
8d3ed2f3
JN
1184 if (!index) {
1185 DRM_ERROR("Invalid sequence %u\n", seq_id);
d3b542fc
SK
1186 goto err;
1187 }
d3b542fc
SK
1188 }
1189
8d3ed2f3
JN
1190 dev_priv->vbt.dsi.data = data;
1191 dev_priv->vbt.dsi.size = seq_size;
1192 dev_priv->vbt.dsi.seq_version = sequence->version;
1193
fb38e7ad
HG
1194 fixup_mipi_sequences(dev_priv);
1195
8d3ed2f3 1196 DRM_DEBUG_DRIVER("MIPI related VBT parsing complete\n");
d3b542fc 1197 return;
d3b542fc 1198
8d3ed2f3
JN
1199err:
1200 kfree(data);
ed3b6679 1201 memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence));
d17c5443
SK
1202}
1203
75067dde
AK
1204static u8 translate_iboost(u8 val)
1205{
1206 static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */
1207
1208 if (val >= ARRAY_SIZE(mapping)) {
1209 DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val);
1210 return 0;
1211 }
1212 return mapping[val];
1213}
1214
9454fa87
VS
1215static void sanitize_ddc_pin(struct drm_i915_private *dev_priv,
1216 enum port port)
1217{
1218 const struct ddi_vbt_port_info *info =
1219 &dev_priv->vbt.ddi_port_info[port];
1220 enum port p;
1221
1222 if (!info->alternate_ddc_pin)
1223 return;
1224
1225 for_each_port_masked(p, (1 << port) - 1) {
1226 struct ddi_vbt_port_info *i = &dev_priv->vbt.ddi_port_info[p];
1227
1228 if (info->alternate_ddc_pin != i->alternate_ddc_pin)
1229 continue;
1230
1231 DRM_DEBUG_KMS("port %c trying to use the same DDC pin (0x%x) as port %c, "
1232 "disabling port %c DVI/HDMI support\n",
1233 port_name(p), i->alternate_ddc_pin,
1234 port_name(port), port_name(p));
1235
1236 /*
1237 * If we have multiple ports supposedly sharing the
1238 * pin, then dvi/hdmi couldn't exist on the shared
1239 * port. Otherwise they share the same ddc bin and
1240 * system couldn't communicate with them separately.
1241 *
1242 * Due to parsing the ports in alphabetical order,
1243 * a higher port will always clobber a lower one.
1244 */
1245 i->supports_dvi = false;
1246 i->supports_hdmi = false;
1247 i->alternate_ddc_pin = 0;
1248 }
1249}
1250
1251static void sanitize_aux_ch(struct drm_i915_private *dev_priv,
1252 enum port port)
1253{
1254 const struct ddi_vbt_port_info *info =
1255 &dev_priv->vbt.ddi_port_info[port];
1256 enum port p;
1257
1258 if (!info->alternate_aux_channel)
1259 return;
1260
1261 for_each_port_masked(p, (1 << port) - 1) {
1262 struct ddi_vbt_port_info *i = &dev_priv->vbt.ddi_port_info[p];
1263
1264 if (info->alternate_aux_channel != i->alternate_aux_channel)
1265 continue;
1266
1267 DRM_DEBUG_KMS("port %c trying to use the same AUX CH (0x%x) as port %c, "
1268 "disabling port %c DP support\n",
1269 port_name(p), i->alternate_aux_channel,
1270 port_name(port), port_name(p));
1271
1272 /*
1273 * If we have multiple ports supposedlt sharing the
1274 * aux channel, then DP couldn't exist on the shared
1275 * port. Otherwise they share the same aux channel
1276 * and system couldn't communicate with them separately.
1277 *
1278 * Due to parsing the ports in alphabetical order,
1279 * a higher port will always clobber a lower one.
1280 */
1281 i->supports_dp = false;
1282 i->alternate_aux_channel = 0;
1283 }
1284}
1285
9c3b2689 1286static const u8 cnp_ddc_pin_map[] = {
3393ce1e 1287 [0] = 0, /* N/A */
9c3b2689
RV
1288 [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT,
1289 [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT,
1290 [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP, /* sic */
1291 [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */
1292};
1293
3937eb1a
RS
1294static const u8 icp_ddc_pin_map[] = {
1295 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
1296 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
1297 [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
1298 [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
1299 [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
1300 [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
1301};
1302
9c3b2689
RV
1303static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
1304{
3937eb1a
RS
1305 const u8 *ddc_pin_map;
1306 int n_entries;
1307
1308 if (HAS_PCH_ICP(dev_priv)) {
1309 ddc_pin_map = icp_ddc_pin_map;
1310 n_entries = ARRAY_SIZE(icp_ddc_pin_map);
1311 } else if (HAS_PCH_CNP(dev_priv)) {
1312 ddc_pin_map = cnp_ddc_pin_map;
1313 n_entries = ARRAY_SIZE(cnp_ddc_pin_map);
1314 } else {
1315 /* Assuming direct map */
1316 return vbt_pin;
a8e6f388 1317 }
9c3b2689 1318
3937eb1a
RS
1319 if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0)
1320 return ddc_pin_map[vbt_pin];
1321
1322 DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n",
1323 vbt_pin);
1324 return 0;
9c3b2689
RV
1325}
1326
6acab15a 1327static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
0ead5f81 1328 u8 bdb_version)
6acab15a 1329{
cc998589 1330 struct child_device_config *it, *child = NULL;
6acab15a 1331 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
6acab15a 1332 int i, j;
554d6af5 1333 bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
6acab15a 1334 /* Each DDI port can have more than one value on the "DVO Port" field,
b5273d72
JN
1335 * so look for all the possible values for each port.
1336 */
2800e4c2
RV
1337 int dvo_ports[][3] = {
1338 {DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
1339 {DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
1340 {DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
1341 {DVO_PORT_HDMID, DVO_PORT_DPD, -1},
1342 {DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
841b5ed7 1343 {DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
6acab15a
PZ
1344 };
1345
b5273d72
JN
1346 /*
1347 * Find the first child device to reference the port, report if more
1348 * than one found.
1349 */
6acab15a
PZ
1350 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1351 it = dev_priv->vbt.child_dev + i;
1352
2800e4c2 1353 for (j = 0; j < 3; j++) {
6acab15a
PZ
1354 if (dvo_ports[port][j] == -1)
1355 break;
1356
cc998589 1357 if (it->dvo_port == dvo_ports[port][j]) {
6acab15a 1358 if (child) {
b5273d72 1359 DRM_DEBUG_KMS("More than one child device for port %c in VBT, using the first.\n",
6acab15a 1360 port_name(port));
b5273d72
JN
1361 } else {
1362 child = it;
6acab15a 1363 }
6acab15a
PZ
1364 }
1365 }
1366 }
1367 if (!child)
1368 return;
1369
cc998589
JN
1370 is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
1371 is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
1372 is_crt = child->device_type & DEVICE_TYPE_ANALOG_OUTPUT;
1373 is_hdmi = is_dvi && (child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
1374 is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
554d6af5 1375
2ba7d7e0
JN
1376 if (port == PORT_A && is_dvi) {
1377 DRM_DEBUG_KMS("VBT claims port A supports DVI%s, ignoring\n",
1378 is_hdmi ? "/HDMI" : "");
1379 is_dvi = false;
1380 is_hdmi = false;
1381 }
1382
311a2094
PZ
1383 info->supports_dvi = is_dvi;
1384 info->supports_hdmi = is_hdmi;
1385 info->supports_dp = is_dp;
a98d9c1d 1386 info->supports_edp = is_edp;
311a2094 1387
38b3416f
ID
1388 if (bdb_version >= 195)
1389 info->supports_typec_usb = child->dp_usb_type_c;
1390
1391 if (bdb_version >= 209)
1392 info->supports_tbt = child->tbt;
1393
1394 DRM_DEBUG_KMS("Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d TCUSB:%d TBT:%d\n",
1395 port_name(port), is_dp, is_hdmi, is_dvi, is_edp, is_crt,
1396 info->supports_typec_usb, info->supports_tbt);
554d6af5
PZ
1397
1398 if (is_edp && is_dvi)
1399 DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n",
1400 port_name(port));
1401 if (is_crt && port != PORT_E)
1402 DRM_DEBUG_KMS("Port %c is analog\n", port_name(port));
1403 if (is_crt && (is_dvi || is_dp))
1404 DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n",
1405 port_name(port));
1406 if (is_dvi && (port == PORT_A || port == PORT_E))
9b13494c 1407 DRM_DEBUG_KMS("Port %c is TMDS compatible\n", port_name(port));
554d6af5
PZ
1408 if (!is_dvi && !is_dp && !is_crt)
1409 DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n",
1410 port_name(port));
1411 if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E))
1412 DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port));
6bf19e7c
PZ
1413
1414 if (is_dvi) {
e53a1058
JN
1415 u8 ddc_pin;
1416
f212bf9a
JN
1417 ddc_pin = map_ddc_pin(dev_priv, child->ddc_pin);
1418 if (intel_gmbus_is_valid_pin(dev_priv, ddc_pin)) {
1419 info->alternate_ddc_pin = ddc_pin;
1420 sanitize_ddc_pin(dev_priv, port);
1421 } else {
1422 DRM_DEBUG_KMS("Port %c has invalid DDC pin %d, "
1423 "sticking to defaults\n",
1424 port_name(port), ddc_pin);
1425 }
6bf19e7c
PZ
1426 }
1427
1428 if (is_dp) {
e53a1058 1429 info->alternate_aux_channel = child->aux_channel;
9454fa87
VS
1430
1431 sanitize_aux_ch(dev_priv, port);
6bf19e7c
PZ
1432 }
1433
0ead5f81 1434 if (bdb_version >= 158) {
6acab15a 1435 /* The VBT HDMI level shift values match the table we have. */
e53a1058 1436 u8 hdmi_level_shift = child->hdmi_level_shifter_value;
ce4dd49e
DL
1437 DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
1438 port_name(port),
1439 hdmi_level_shift);
1440 info->hdmi_level_shift = hdmi_level_shift;
6acab15a 1441 }
75067dde 1442
d6038611
VS
1443 if (bdb_version >= 204) {
1444 int max_tmds_clock;
1445
1446 switch (child->hdmi_max_data_rate) {
1447 default:
1448 MISSING_CASE(child->hdmi_max_data_rate);
1449 /* fall through */
1450 case HDMI_MAX_DATA_RATE_PLATFORM:
1451 max_tmds_clock = 0;
1452 break;
1453 case HDMI_MAX_DATA_RATE_297:
1454 max_tmds_clock = 297000;
1455 break;
1456 case HDMI_MAX_DATA_RATE_165:
1457 max_tmds_clock = 165000;
1458 break;
1459 }
1460
1461 if (max_tmds_clock)
1462 DRM_DEBUG_KMS("VBT HDMI max TMDS clock for port %c: %d kHz\n",
1463 port_name(port), max_tmds_clock);
1464 info->max_tmds_clock = max_tmds_clock;
1465 }
1466
75067dde 1467 /* Parse the I_boost config for SKL and above */
0ead5f81 1468 if (bdb_version >= 196 && child->iboost) {
f22bb358 1469 info->dp_boost_level = translate_iboost(child->dp_iboost_level);
75067dde
AK
1470 DRM_DEBUG_KMS("VBT (e)DP boost level for port %c: %d\n",
1471 port_name(port), info->dp_boost_level);
f22bb358 1472 info->hdmi_boost_level = translate_iboost(child->hdmi_iboost_level);
75067dde
AK
1473 DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n",
1474 port_name(port), info->hdmi_boost_level);
1475 }
99b91bda
JN
1476
1477 /* DP max link rate for CNL+ */
1478 if (bdb_version >= 216) {
1479 switch (child->dp_max_link_rate) {
1480 default:
1481 case VBT_DP_MAX_LINK_RATE_HBR3:
1482 info->dp_max_link_rate = 810000;
1483 break;
1484 case VBT_DP_MAX_LINK_RATE_HBR2:
1485 info->dp_max_link_rate = 540000;
1486 break;
1487 case VBT_DP_MAX_LINK_RATE_HBR:
1488 info->dp_max_link_rate = 270000;
1489 break;
1490 case VBT_DP_MAX_LINK_RATE_LBR:
1491 info->dp_max_link_rate = 162000;
1492 break;
1493 }
1494 DRM_DEBUG_KMS("VBT DP max link rate for port %c: %d\n",
1495 port_name(port), info->dp_max_link_rate);
1496 }
6acab15a
PZ
1497}
1498
0ead5f81 1499static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
6acab15a 1500{
6acab15a
PZ
1501 enum port port;
1502
348e4058 1503 if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
6acab15a
PZ
1504 return;
1505
1506 if (!dev_priv->vbt.child_dev_num)
1507 return;
1508
0ead5f81 1509 if (bdb_version < 155)
6acab15a
PZ
1510 return;
1511
1512 for (port = PORT_A; port < I915_MAX_PORTS; port++)
0ead5f81 1513 parse_ddi_port(dev_priv, port, bdb_version);
6acab15a
PZ
1514}
1515
6363ee6f 1516static void
b3ca1f43
JN
1517parse_general_definitions(struct drm_i915_private *dev_priv,
1518 const struct bdb_header *bdb)
6363ee6f 1519{
e192839e
JN
1520 const struct bdb_general_definitions *defs;
1521 const struct child_device_config *child;
6363ee6f 1522 int i, child_device_num, count;
e2d6cf7f
DW
1523 u8 expected_size;
1524 u16 block_size;
b3ca1f43 1525 int bus_pin;
6363ee6f 1526
e192839e
JN
1527 defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
1528 if (!defs) {
44834a67 1529 DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
6363ee6f
ZY
1530 return;
1531 }
b3ca1f43
JN
1532
1533 block_size = get_blocksize(defs);
1534 if (block_size < sizeof(*defs)) {
1535 DRM_DEBUG_KMS("General definitions block too small (%u)\n",
1536 block_size);
1537 return;
1538 }
1539
1540 bus_pin = defs->crt_ddc_gmbus_pin;
1541 DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
1542 if (intel_gmbus_is_valid_pin(dev_priv, bus_pin))
1543 dev_priv->vbt.crt_ddc_pin = bus_pin;
1544
7244f309
VS
1545 if (bdb->version < 106) {
1546 expected_size = 22;
fa05178c 1547 } else if (bdb->version < 111) {
52b69c84
VS
1548 expected_size = 27;
1549 } else if (bdb->version < 195) {
21907e72 1550 expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE;
e2d6cf7f
DW
1551 } else if (bdb->version == 195) {
1552 expected_size = 37;
c4fb60b9 1553 } else if (bdb->version <= 215) {
e2d6cf7f 1554 expected_size = 38;
c4fb60b9
JN
1555 } else if (bdb->version <= 216) {
1556 expected_size = 39;
e2d6cf7f 1557 } else {
c4fb60b9
JN
1558 expected_size = sizeof(*child);
1559 BUILD_BUG_ON(sizeof(*child) < 39);
e2d6cf7f
DW
1560 DRM_DEBUG_DRIVER("Expected child device config size for VBT version %u not known; assuming %u\n",
1561 bdb->version, expected_size);
1562 }
1563
e2d6cf7f 1564 /* Flag an error for unexpected size, but continue anyway. */
e192839e 1565 if (defs->child_dev_size != expected_size)
e2d6cf7f 1566 DRM_ERROR("Unexpected child device config size %u (expected %u for VBT version %u)\n",
e192839e 1567 defs->child_dev_size, expected_size, bdb->version);
e2d6cf7f 1568
52b69c84 1569 /* The legacy sized child device config is the minimum we need. */
e192839e 1570 if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) {
52b69c84 1571 DRM_DEBUG_KMS("Child device config size %u is too small.\n",
e192839e 1572 defs->child_dev_size);
52b69c84
VS
1573 return;
1574 }
1575
6363ee6f 1576 /* get the number of child device */
e192839e 1577 child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size;
6363ee6f
ZY
1578 count = 0;
1579 /* get the number of child device that is present */
1580 for (i = 0; i < child_device_num; i++) {
e192839e 1581 child = child_device_ptr(defs, i);
53f6b243 1582 if (!child->device_type)
6363ee6f 1583 continue;
6363ee6f
ZY
1584 count++;
1585 }
1586 if (!count) {
0206e353 1587 DRM_DEBUG_KMS("no child dev is parsed from VBT\n");
6363ee6f
ZY
1588 return;
1589 }
e192839e 1590 dev_priv->vbt.child_dev = kcalloc(count, sizeof(*child), GFP_KERNEL);
41aa3448 1591 if (!dev_priv->vbt.child_dev) {
6363ee6f
ZY
1592 DRM_DEBUG_KMS("No memory space for child device\n");
1593 return;
1594 }
1595
41aa3448 1596 dev_priv->vbt.child_dev_num = count;
6363ee6f
ZY
1597 count = 0;
1598 for (i = 0; i < child_device_num; i++) {
e192839e 1599 child = child_device_ptr(defs, i);
53f6b243 1600 if (!child->device_type)
6363ee6f 1601 continue;
3e6bd011 1602
e2d6cf7f
DW
1603 /*
1604 * Copy as much as we know (sizeof) and is available
1605 * (child_dev_size) of the child device. Accessing the data must
1606 * depend on VBT version.
1607 */
127704f5 1608 memcpy(dev_priv->vbt.child_dev + count, child,
e192839e 1609 min_t(size_t, defs->child_dev_size, sizeof(*child)));
127704f5 1610 count++;
6363ee6f 1611 }
6363ee6f 1612}
44834a67 1613
bb1d1329 1614/* Common defaults which may be overridden by VBT. */
6a04002b
SQ
1615static void
1616init_vbt_defaults(struct drm_i915_private *dev_priv)
1617{
6acab15a 1618 enum port port;
9a4114ff 1619
988c7015 1620 dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
6a04002b 1621
56c4b63a
JN
1622 /* Default to having backlight */
1623 dev_priv->vbt.backlight.present = true;
1624
6a04002b 1625 /* LFP panel data */
41aa3448 1626 dev_priv->vbt.lvds_dither = 1;
6a04002b
SQ
1627
1628 /* SDVO panel data */
41aa3448 1629 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
6a04002b
SQ
1630
1631 /* general features */
41aa3448
RV
1632 dev_priv->vbt.int_tv_support = 1;
1633 dev_priv->vbt.int_crt_support = 1;
9a4114ff 1634
5255e2f8
VS
1635 /* driver features */
1636 dev_priv->vbt.int_lvds_support = 1;
1637
9a4114ff 1638 /* Default to using SSC */
41aa3448 1639 dev_priv->vbt.lvds_use_ssc = 1;
f69e5156
DL
1640 /*
1641 * Core/SandyBridge/IvyBridge use alternative (120MHz) reference
1642 * clock for LVDS.
1643 */
98f3a1dc
JN
1644 dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev_priv,
1645 !HAS_PCH_SPLIT(dev_priv));
e91e941b 1646 DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq);
6acab15a
PZ
1647
1648 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
311a2094
PZ
1649 struct ddi_vbt_port_info *info =
1650 &dev_priv->vbt.ddi_port_info[port];
1651
ce4dd49e 1652 info->hdmi_level_shift = HDMI_LEVEL_SHIFT_UNKNOWN;
bb1d1329
JN
1653 }
1654}
1655
1656/* Defaults to initialize only if there is no VBT. */
1657static void
1658init_vbt_missing_defaults(struct drm_i915_private *dev_priv)
1659{
1660 enum port port;
1661
1662 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
1663 struct ddi_vbt_port_info *info =
1664 &dev_priv->vbt.ddi_port_info[port];
311a2094 1665
828ccb31
ID
1666 /*
1667 * VBT has the TypeC mode (native,TBT/USB) and we don't want
1668 * to detect it.
1669 */
1670 if (intel_port_is_tc(dev_priv, port))
1671 continue;
1672
311a2094
PZ
1673 info->supports_dvi = (port != PORT_A && port != PORT_E);
1674 info->supports_hdmi = info->supports_dvi;
1675 info->supports_dp = (port != PORT_E);
2131bc0c 1676 info->supports_edp = (port == PORT_A);
6acab15a 1677 }
6a04002b
SQ
1678}
1679
caf37fa4
JN
1680static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt)
1681{
1682 const void *_vbt = vbt;
1683
1684 return _vbt + vbt->bdb_offset;
1685}
1686
f0067a31
JN
1687/**
1688 * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT
1689 * @buf: pointer to a buffer to validate
1690 * @size: size of the buffer
1691 *
1692 * Returns true on valid VBT.
1693 */
1694bool intel_bios_is_valid_vbt(const void *buf, size_t size)
3dd4e846 1695{
f0067a31 1696 const struct vbt_header *vbt = buf;
dcb58a40 1697 const struct bdb_header *bdb;
3dd4e846 1698
caf37fa4 1699 if (!vbt)
f0067a31 1700 return false;
caf37fa4 1701
f0067a31 1702 if (sizeof(struct vbt_header) > size) {
3dd4e846 1703 DRM_DEBUG_DRIVER("VBT header incomplete\n");
f0067a31 1704 return false;
3dd4e846
CW
1705 }
1706
1707 if (memcmp(vbt->signature, "$VBT", 4)) {
1708 DRM_DEBUG_DRIVER("VBT invalid signature\n");
f0067a31 1709 return false;
3dd4e846
CW
1710 }
1711
e8f9ae9b
CW
1712 if (range_overflows_t(size_t,
1713 vbt->bdb_offset,
1714 sizeof(struct bdb_header),
1715 size)) {
3dd4e846 1716 DRM_DEBUG_DRIVER("BDB header incomplete\n");
f0067a31 1717 return false;
3dd4e846
CW
1718 }
1719
caf37fa4 1720 bdb = get_bdb_header(vbt);
e8f9ae9b 1721 if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) {
3dd4e846 1722 DRM_DEBUG_DRIVER("BDB incomplete\n");
f0067a31 1723 return false;
3dd4e846
CW
1724 }
1725
caf37fa4 1726 return vbt;
3dd4e846
CW
1727}
1728
caf37fa4 1729static const struct vbt_header *find_vbt(void __iomem *bios, size_t size)
b34a991a 1730{
b34a991a
JN
1731 size_t i;
1732
1733 /* Scour memory looking for the VBT signature. */
1734 for (i = 0; i + 4 < size; i++) {
f0067a31 1735 void *vbt;
115719fc 1736
f0067a31
JN
1737 if (ioread32(bios + i) != *((const u32 *) "$VBT"))
1738 continue;
1739
1740 /*
1741 * This is the one place where we explicitly discard the address
1742 * space (__iomem) of the BIOS/VBT.
1743 */
1744 vbt = (void __force *) bios + i;
1745 if (intel_bios_is_valid_vbt(vbt, size - i))
1746 return vbt;
1747
1748 break;
b34a991a
JN
1749 }
1750
f0067a31 1751 return NULL;
b34a991a
JN
1752}
1753
79e53945 1754/**
8b8e1a89 1755 * intel_bios_init - find VBT and initialize settings from the BIOS
dd97950a 1756 * @dev_priv: i915 device instance
79e53945 1757 *
66578857
JN
1758 * Parse and initialize settings from the Video BIOS Tables (VBT). If the VBT
1759 * was not found in ACPI OpRegion, try to find it in PCI ROM first. Also
1760 * initialize some defaults if the VBT is not present at all.
79e53945 1761 */
66578857 1762void intel_bios_init(struct drm_i915_private *dev_priv)
79e53945 1763{
91c8a326 1764 struct pci_dev *pdev = dev_priv->drm.pdev;
f0067a31 1765 const struct vbt_header *vbt = dev_priv->opregion.vbt;
caf37fa4 1766 const struct bdb_header *bdb;
44834a67
CW
1767 u8 __iomem *bios = NULL;
1768
e1bf094b 1769 if (!HAS_DISPLAY(dev_priv)) {
66578857
JN
1770 DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n");
1771 return;
1772 }
ab5c608b 1773
6a04002b 1774 init_vbt_defaults(dev_priv);
f899fc64 1775
66578857 1776 /* If the OpRegion does not have VBT, look in PCI ROM. */
f0067a31 1777 if (!vbt) {
b34a991a 1778 size_t size;
79e53945 1779
44834a67
CW
1780 bios = pci_map_rom(pdev, &size);
1781 if (!bios)
66578857 1782 goto out;
44834a67 1783
caf37fa4 1784 vbt = find_vbt(bios, size);
66578857
JN
1785 if (!vbt)
1786 goto out;
e2051c44
JN
1787
1788 DRM_DEBUG_KMS("Found valid VBT in PCI ROM\n");
44834a67 1789 }
79e53945 1790
caf37fa4
JN
1791 bdb = get_bdb_header(vbt);
1792
3556dd40
JN
1793 DRM_DEBUG_KMS("VBT signature \"%.*s\", BDB version %d\n",
1794 (int)sizeof(vbt->signature), vbt->signature, bdb->version);
e2051c44 1795
79e53945
JB
1796 /* Grab useful general definitions */
1797 parse_general_features(dev_priv, bdb);
db545019 1798 parse_general_definitions(dev_priv, bdb);
88631706 1799 parse_lfp_panel_data(dev_priv, bdb);
f00076d2 1800 parse_lfp_backlight(dev_priv, bdb);
88631706 1801 parse_sdvo_panel_data(dev_priv, bdb);
32f9d658 1802 parse_driver_features(dev_priv, bdb);
500a8cc4 1803 parse_edp(dev_priv, bdb);
bfd7ebda 1804 parse_psr(dev_priv, bdb);
0f8689f5
JN
1805 parse_mipi_config(dev_priv, bdb);
1806 parse_mipi_sequence(dev_priv, bdb);
0ebdabe6
JN
1807
1808 /* Further processing on pre-parsed data */
0ead5f81
JN
1809 parse_sdvo_device_mapping(dev_priv, bdb->version);
1810 parse_ddi_ports(dev_priv, bdb->version);
32f9d658 1811
66578857 1812out:
bb1d1329 1813 if (!vbt) {
66578857 1814 DRM_INFO("Failed to find VBIOS tables (VBT)\n");
bb1d1329
JN
1815 init_vbt_missing_defaults(dev_priv);
1816 }
66578857 1817
44834a67
CW
1818 if (bios)
1819 pci_unmap_rom(pdev, bios);
79e53945 1820}
3bdd14d5 1821
785f076b
HG
1822/**
1823 * intel_bios_cleanup - Free any resources allocated by intel_bios_init()
1824 * @dev_priv: i915 device instance
1825 */
1826void intel_bios_cleanup(struct drm_i915_private *dev_priv)
1827{
1828 kfree(dev_priv->vbt.child_dev);
1829 dev_priv->vbt.child_dev = NULL;
1830 dev_priv->vbt.child_dev_num = 0;
1831 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1832 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1833 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1834 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
e1b86c85
HG
1835 kfree(dev_priv->vbt.dsi.data);
1836 dev_priv->vbt.dsi.data = NULL;
1837 kfree(dev_priv->vbt.dsi.pps);
1838 dev_priv->vbt.dsi.pps = NULL;
1839 kfree(dev_priv->vbt.dsi.config);
1840 dev_priv->vbt.dsi.config = NULL;
fb38e7ad
HG
1841 kfree(dev_priv->vbt.dsi.deassert_seq);
1842 dev_priv->vbt.dsi.deassert_seq = NULL;
785f076b
HG
1843}
1844
3bdd14d5
JN
1845/**
1846 * intel_bios_is_tv_present - is integrated TV present in VBT
1847 * @dev_priv: i915 device instance
1848 *
1849 * Return true if TV is present. If no child devices were parsed from VBT,
1850 * assume TV is present.
1851 */
1852bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv)
1853{
cc998589 1854 const struct child_device_config *child;
3bdd14d5
JN
1855 int i;
1856
1857 if (!dev_priv->vbt.int_tv_support)
1858 return false;
1859
1860 if (!dev_priv->vbt.child_dev_num)
1861 return true;
1862
1863 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
cc998589 1864 child = dev_priv->vbt.child_dev + i;
3bdd14d5
JN
1865 /*
1866 * If the device type is not TV, continue.
1867 */
cc998589 1868 switch (child->device_type) {
3bdd14d5
JN
1869 case DEVICE_TYPE_INT_TV:
1870 case DEVICE_TYPE_TV:
1871 case DEVICE_TYPE_TV_SVIDEO_COMPOSITE:
1872 break;
1873 default:
1874 continue;
1875 }
1876 /* Only when the addin_offset is non-zero, it is regarded
1877 * as present.
1878 */
cc998589 1879 if (child->addin_offset)
3bdd14d5
JN
1880 return true;
1881 }
1882
1883 return false;
1884}
5a69d13d
JN
1885
1886/**
1887 * intel_bios_is_lvds_present - is LVDS present in VBT
1888 * @dev_priv: i915 device instance
1889 * @i2c_pin: i2c pin for LVDS if present
1890 *
1891 * Return true if LVDS is present. If no child devices were parsed from VBT,
1892 * assume LVDS is present.
1893 */
1894bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin)
1895{
cc998589 1896 const struct child_device_config *child;
5a69d13d
JN
1897 int i;
1898
1899 if (!dev_priv->vbt.child_dev_num)
1900 return true;
1901
1902 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
cc998589 1903 child = dev_priv->vbt.child_dev + i;
5a69d13d
JN
1904
1905 /* If the device type is not LFP, continue.
1906 * We have to check both the new identifiers as well as the
1907 * old for compatibility with some BIOSes.
1908 */
1909 if (child->device_type != DEVICE_TYPE_INT_LFP &&
1910 child->device_type != DEVICE_TYPE_LFP)
1911 continue;
1912
1913 if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin))
1914 *i2c_pin = child->i2c_pin;
1915
1916 /* However, we cannot trust the BIOS writers to populate
1917 * the VBT correctly. Since LVDS requires additional
1918 * information from AIM blocks, a non-zero addin offset is
1919 * a good indicator that the LVDS is actually present.
1920 */
1921 if (child->addin_offset)
1922 return true;
1923
1924 /* But even then some BIOS writers perform some black magic
1925 * and instantiate the device without reference to any
1926 * additional data. Trust that if the VBT was written into
1927 * the OpRegion then they have validated the LVDS's existence.
1928 */
1929 if (dev_priv->opregion.vbt)
1930 return true;
1931 }
1932
1933 return false;
1934}
951d9efe 1935
22f35042
VS
1936/**
1937 * intel_bios_is_port_present - is the specified digital port present
1938 * @dev_priv: i915 device instance
1939 * @port: port to check
1940 *
1941 * Return true if the device in %port is present.
1942 */
1943bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port)
1944{
cc998589 1945 const struct child_device_config *child;
22f35042
VS
1946 static const struct {
1947 u16 dp, hdmi;
1948 } port_mapping[] = {
1949 [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
1950 [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
1951 [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
1952 [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
841b5ed7 1953 [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
22f35042
VS
1954 };
1955 int i;
1956
e9d49bb7
ID
1957 if (HAS_DDI(dev_priv)) {
1958 const struct ddi_vbt_port_info *port_info =
1959 &dev_priv->vbt.ddi_port_info[port];
1960
1961 return port_info->supports_dp ||
1962 port_info->supports_dvi ||
1963 port_info->supports_hdmi;
1964 }
1965
22f35042
VS
1966 /* FIXME maybe deal with port A as well? */
1967 if (WARN_ON(port == PORT_A) || port >= ARRAY_SIZE(port_mapping))
1968 return false;
1969
1970 if (!dev_priv->vbt.child_dev_num)
1971 return false;
1972
1973 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
cc998589
JN
1974 child = dev_priv->vbt.child_dev + i;
1975
1976 if ((child->dvo_port == port_mapping[port].dp ||
1977 child->dvo_port == port_mapping[port].hdmi) &&
1978 (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING |
1979 DEVICE_TYPE_DISPLAYPORT_OUTPUT)))
22f35042
VS
1980 return true;
1981 }
1982
1983 return false;
1984}
1985
951d9efe
JN
1986/**
1987 * intel_bios_is_port_edp - is the device in given port eDP
1988 * @dev_priv: i915 device instance
1989 * @port: port to check
1990 *
1991 * Return true if the device in %port is eDP.
1992 */
1993bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
1994{
cc998589 1995 const struct child_device_config *child;
951d9efe
JN
1996 static const short port_mapping[] = {
1997 [PORT_B] = DVO_PORT_DPB,
1998 [PORT_C] = DVO_PORT_DPC,
1999 [PORT_D] = DVO_PORT_DPD,
2000 [PORT_E] = DVO_PORT_DPE,
841b5ed7 2001 [PORT_F] = DVO_PORT_DPF,
951d9efe
JN
2002 };
2003 int i;
2004
a98d9c1d
ID
2005 if (HAS_DDI(dev_priv))
2006 return dev_priv->vbt.ddi_port_info[port].supports_edp;
2007
951d9efe
JN
2008 if (!dev_priv->vbt.child_dev_num)
2009 return false;
2010
2011 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
cc998589 2012 child = dev_priv->vbt.child_dev + i;
951d9efe 2013
cc998589
JN
2014 if (child->dvo_port == port_mapping[port] &&
2015 (child->device_type & DEVICE_TYPE_eDP_BITS) ==
951d9efe
JN
2016 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
2017 return true;
2018 }
2019
2020 return false;
2021}
7137aec1 2022
cc998589 2023static bool child_dev_is_dp_dual_mode(const struct child_device_config *child,
7a17995a 2024 enum port port)
d6199256
VS
2025{
2026 static const struct {
2027 u16 dp, hdmi;
2028 } port_mapping[] = {
2029 /*
2030 * Buggy VBTs may declare DP ports as having
2031 * HDMI type dvo_port :( So let's check both.
2032 */
2033 [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
2034 [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
2035 [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
2036 [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
841b5ed7 2037 [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
d6199256 2038 };
d6199256
VS
2039
2040 if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
2041 return false;
2042
cc998589 2043 if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) !=
7a17995a 2044 (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS))
d6199256
VS
2045 return false;
2046
cc998589 2047 if (child->dvo_port == port_mapping[port].dp)
7a17995a
VS
2048 return true;
2049
2050 /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */
cc998589
JN
2051 if (child->dvo_port == port_mapping[port].hdmi &&
2052 child->aux_channel != 0)
7a17995a
VS
2053 return true;
2054
2055 return false;
2056}
2057
2058bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv,
2059 enum port port)
2060{
cc998589 2061 const struct child_device_config *child;
7a17995a
VS
2062 int i;
2063
d6199256 2064 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
cc998589 2065 child = dev_priv->vbt.child_dev + i;
d6199256 2066
cc998589 2067 if (child_dev_is_dp_dual_mode(child, port))
d6199256
VS
2068 return true;
2069 }
2070
2071 return false;
2072}
2073
7137aec1
JN
2074/**
2075 * intel_bios_is_dsi_present - is DSI present in VBT
2076 * @dev_priv: i915 device instance
2077 * @port: port for DSI if present
2078 *
2079 * Return true if DSI is present, and return the port in %port.
2080 */
2081bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
2082 enum port *port)
2083{
cc998589 2084 const struct child_device_config *child;
7137aec1
JN
2085 u8 dvo_port;
2086 int i;
2087
2088 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
cc998589 2089 child = dev_priv->vbt.child_dev + i;
7137aec1 2090
cc998589 2091 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
7137aec1
JN
2092 continue;
2093
cc998589 2094 dvo_port = child->dvo_port;
7137aec1 2095
bf4d57ff
MC
2096 if (dvo_port == DVO_PORT_MIPIA ||
2097 (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||
2098 (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {
7caaef33
JN
2099 if (port)
2100 *port = dvo_port - DVO_PORT_MIPIA;
7137aec1 2101 return true;
bf4d57ff
MC
2102 } else if (dvo_port == DVO_PORT_MIPIB ||
2103 dvo_port == DVO_PORT_MIPIC ||
2104 dvo_port == DVO_PORT_MIPID) {
7137aec1
JN
2105 DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n",
2106 port_name(dvo_port - DVO_PORT_MIPIA));
7137aec1
JN
2107 }
2108 }
2109
2110 return false;
2111}
d252bf68
SS
2112
2113/**
2114 * intel_bios_is_port_hpd_inverted - is HPD inverted for %port
2115 * @dev_priv: i915 device instance
2116 * @port: port to check
2117 *
2118 * Return true if HPD should be inverted for %port.
2119 */
2120bool
2121intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
2122 enum port port)
2123{
cc998589 2124 const struct child_device_config *child;
d252bf68
SS
2125 int i;
2126
cc3f90f0 2127 if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
d252bf68
SS
2128 return false;
2129
2130 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
cc998589
JN
2131 child = dev_priv->vbt.child_dev + i;
2132
2133 if (!child->hpd_invert)
d252bf68
SS
2134 continue;
2135
cc998589 2136 switch (child->dvo_port) {
d252bf68
SS
2137 case DVO_PORT_DPA:
2138 case DVO_PORT_HDMIA:
2139 if (port == PORT_A)
2140 return true;
2141 break;
2142 case DVO_PORT_DPB:
2143 case DVO_PORT_HDMIB:
2144 if (port == PORT_B)
2145 return true;
2146 break;
2147 case DVO_PORT_DPC:
2148 case DVO_PORT_HDMIC:
2149 if (port == PORT_C)
2150 return true;
2151 break;
2152 default:
2153 break;
2154 }
2155 }
2156
2157 return false;
2158}
6389dd83
SS
2159
2160/**
2161 * intel_bios_is_lspcon_present - if LSPCON is attached on %port
2162 * @dev_priv: i915 device instance
2163 * @port: port to check
2164 *
2165 * Return true if LSPCON is present on this port
2166 */
2167bool
2168intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
2169 enum port port)
2170{
cc998589 2171 const struct child_device_config *child;
6389dd83
SS
2172 int i;
2173
2174 if (!HAS_LSPCON(dev_priv))
2175 return false;
2176
2177 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
cc998589
JN
2178 child = dev_priv->vbt.child_dev + i;
2179
2180 if (!child->lspcon)
6389dd83
SS
2181 continue;
2182
cc998589 2183 switch (child->dvo_port) {
6389dd83
SS
2184 case DVO_PORT_DPA:
2185 case DVO_PORT_HDMIA:
2186 if (port == PORT_A)
2187 return true;
2188 break;
2189 case DVO_PORT_DPB:
2190 case DVO_PORT_HDMIB:
2191 if (port == PORT_B)
2192 return true;
2193 break;
2194 case DVO_PORT_DPC:
2195 case DVO_PORT_HDMIC:
2196 if (port == PORT_C)
2197 return true;
2198 break;
2199 case DVO_PORT_DPD:
2200 case DVO_PORT_HDMID:
2201 if (port == PORT_D)
2202 return true;
2203 break;
841b5ed7
RV
2204 case DVO_PORT_DPF:
2205 case DVO_PORT_HDMIF:
2206 if (port == PORT_F)
2207 return true;
2208 break;
6389dd83
SS
2209 default:
2210 break;
2211 }
2212 }
2213
2214 return false;
2215}
15d248ae 2216
39053089
JN
2217enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
2218 enum port port)
15d248ae
ID
2219{
2220 const struct ddi_vbt_port_info *info =
2221 &dev_priv->vbt.ddi_port_info[port];
2222 enum aux_ch aux_ch;
2223
2224 if (!info->alternate_aux_channel) {
2225 aux_ch = (enum aux_ch)port;
2226
2227 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
2228 aux_ch_name(aux_ch), port_name(port));
2229 return aux_ch;
2230 }
2231
2232 switch (info->alternate_aux_channel) {
2233 case DP_AUX_A:
2234 aux_ch = AUX_CH_A;
2235 break;
2236 case DP_AUX_B:
2237 aux_ch = AUX_CH_B;
2238 break;
2239 case DP_AUX_C:
2240 aux_ch = AUX_CH_C;
2241 break;
2242 case DP_AUX_D:
2243 aux_ch = AUX_CH_D;
2244 break;
2245 case DP_AUX_E:
2246 aux_ch = AUX_CH_E;
2247 break;
2248 case DP_AUX_F:
2249 aux_ch = AUX_CH_F;
2250 break;
2251 default:
2252 MISSING_CASE(info->alternate_aux_channel);
2253 aux_ch = AUX_CH_A;
2254 break;
2255 }
2256
2257 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
2258 aux_ch_name(aux_ch), port_name(port));
2259
2260 return aux_ch;
2261}