Commit | Line | Data |
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7c10a2b5 JN |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
58fddc28 ID |
25 | #include <linux/component.h> |
26 | #include <drm/i915_component.h> | |
27 | #include "intel_drv.h" | |
7c10a2b5 JN |
28 | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/drm_edid.h> | |
7c10a2b5 JN |
31 | #include "i915_drv.h" |
32 | ||
28855d2a JN |
33 | /** |
34 | * DOC: High Definition Audio over HDMI and Display Port | |
35 | * | |
36 | * The graphics and audio drivers together support High Definition Audio over | |
37 | * HDMI and Display Port. The audio programming sequences are divided into audio | |
38 | * codec and controller enable and disable sequences. The graphics driver | |
39 | * handles the audio codec sequences, while the audio driver handles the audio | |
40 | * controller sequences. | |
41 | * | |
42 | * The disable sequences must be performed before disabling the transcoder or | |
43 | * port. The enable sequences may only be performed after enabling the | |
3e6da4a9 JN |
44 | * transcoder and port, and after completed link training. Therefore the audio |
45 | * enable/disable sequences are part of the modeset sequence. | |
28855d2a JN |
46 | * |
47 | * The codec and controller sequences could be done either parallel or serial, | |
48 | * but generally the ELDV/PD change in the codec sequence indicates to the audio | |
49 | * driver that the controller sequence should start. Indeed, most of the | |
50 | * co-operation between the graphics and audio drivers is handled via audio | |
51 | * related registers. (The notable exception is the power management, not | |
52 | * covered here.) | |
cb422619 | 53 | * |
62cacc79 DV |
54 | * The struct &i915_audio_component is used to interact between the graphics |
55 | * and audio drivers. The struct &i915_audio_component_ops @ops in it is | |
cb422619 | 56 | * defined in graphics driver and called in audio driver. The |
62cacc79 | 57 | * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. |
28855d2a JN |
58 | */ |
59 | ||
6014ac12 LY |
60 | /* DP N/M table */ |
61 | #define LC_540M 540000 | |
62 | #define LC_270M 270000 | |
63 | #define LC_162M 162000 | |
64 | ||
65 | struct dp_aud_n_m { | |
66 | int sample_rate; | |
67 | int clock; | |
68 | u16 m; | |
69 | u16 n; | |
70 | }; | |
71 | ||
72 | /* Values according to DP 1.4 Table 2-104 */ | |
73 | static const struct dp_aud_n_m dp_aud_n_m[] = { | |
74 | { 32000, LC_162M, 1024, 10125 }, | |
75 | { 44100, LC_162M, 784, 5625 }, | |
76 | { 48000, LC_162M, 512, 3375 }, | |
77 | { 64000, LC_162M, 2048, 10125 }, | |
78 | { 88200, LC_162M, 1568, 5625 }, | |
79 | { 96000, LC_162M, 1024, 3375 }, | |
80 | { 128000, LC_162M, 4096, 10125 }, | |
81 | { 176400, LC_162M, 3136, 5625 }, | |
82 | { 192000, LC_162M, 2048, 3375 }, | |
83 | { 32000, LC_270M, 1024, 16875 }, | |
84 | { 44100, LC_270M, 784, 9375 }, | |
85 | { 48000, LC_270M, 512, 5625 }, | |
86 | { 64000, LC_270M, 2048, 16875 }, | |
87 | { 88200, LC_270M, 1568, 9375 }, | |
88 | { 96000, LC_270M, 1024, 5625 }, | |
89 | { 128000, LC_270M, 4096, 16875 }, | |
90 | { 176400, LC_270M, 3136, 9375 }, | |
91 | { 192000, LC_270M, 2048, 5625 }, | |
92 | { 32000, LC_540M, 1024, 33750 }, | |
93 | { 44100, LC_540M, 784, 18750 }, | |
94 | { 48000, LC_540M, 512, 11250 }, | |
95 | { 64000, LC_540M, 2048, 33750 }, | |
96 | { 88200, LC_540M, 1568, 18750 }, | |
97 | { 96000, LC_540M, 1024, 11250 }, | |
98 | { 128000, LC_540M, 4096, 33750 }, | |
99 | { 176400, LC_540M, 3136, 18750 }, | |
100 | { 192000, LC_540M, 2048, 11250 }, | |
101 | }; | |
102 | ||
103 | static const struct dp_aud_n_m * | |
104 | audio_config_dp_get_n_m(struct intel_crtc *intel_crtc, int rate) | |
105 | { | |
106 | int i; | |
107 | ||
108 | for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) { | |
109 | if (rate == dp_aud_n_m[i].sample_rate && | |
110 | intel_crtc->config->port_clock == dp_aud_n_m[i].clock) | |
111 | return &dp_aud_n_m[i]; | |
112 | } | |
113 | ||
114 | return NULL; | |
115 | } | |
116 | ||
87fcb2ad | 117 | static const struct { |
7c10a2b5 JN |
118 | int clock; |
119 | u32 config; | |
120 | } hdmi_audio_clock[] = { | |
606bb5e0 | 121 | { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
7c10a2b5 JN |
122 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
123 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
606bb5e0 | 124 | { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
7c10a2b5 | 125 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
606bb5e0 VS |
126 | { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
127 | { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7c10a2b5 | 128 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
606bb5e0 | 129 | { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
7c10a2b5 JN |
130 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
131 | }; | |
132 | ||
4a21ef7d LY |
133 | /* HDMI N/CTS table */ |
134 | #define TMDS_297M 297000 | |
606bb5e0 | 135 | #define TMDS_296M 296703 |
4a21ef7d LY |
136 | static const struct { |
137 | int sample_rate; | |
138 | int clock; | |
139 | int n; | |
140 | int cts; | |
9eeb7304 | 141 | } hdmi_aud_ncts[] = { |
4a21ef7d LY |
142 | { 44100, TMDS_296M, 4459, 234375 }, |
143 | { 44100, TMDS_297M, 4704, 247500 }, | |
144 | { 48000, TMDS_296M, 5824, 281250 }, | |
145 | { 48000, TMDS_297M, 5120, 247500 }, | |
146 | { 32000, TMDS_296M, 5824, 421875 }, | |
147 | { 32000, TMDS_297M, 3072, 222750 }, | |
148 | { 88200, TMDS_296M, 8918, 234375 }, | |
149 | { 88200, TMDS_297M, 9408, 247500 }, | |
150 | { 96000, TMDS_296M, 11648, 281250 }, | |
151 | { 96000, TMDS_297M, 10240, 247500 }, | |
152 | { 176400, TMDS_296M, 17836, 234375 }, | |
153 | { 176400, TMDS_297M, 18816, 247500 }, | |
154 | { 192000, TMDS_296M, 23296, 281250 }, | |
155 | { 192000, TMDS_297M, 20480, 247500 }, | |
156 | }; | |
157 | ||
7c10a2b5 | 158 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
5e7234c9 | 159 | static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode) |
7c10a2b5 JN |
160 | { |
161 | int i; | |
162 | ||
163 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
aad941d5 | 164 | if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) |
7c10a2b5 JN |
165 | break; |
166 | } | |
167 | ||
168 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
5e7234c9 | 169 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", |
aad941d5 | 170 | adjusted_mode->crtc_clock); |
7c10a2b5 JN |
171 | i = 1; |
172 | } | |
173 | ||
174 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
175 | hdmi_audio_clock[i].clock, | |
176 | hdmi_audio_clock[i].config); | |
177 | ||
178 | return hdmi_audio_clock[i].config; | |
179 | } | |
180 | ||
9eeb7304 JN |
181 | static int audio_config_hdmi_get_n(const struct drm_display_mode *adjusted_mode, |
182 | int rate) | |
4a21ef7d LY |
183 | { |
184 | int i; | |
185 | ||
9eeb7304 JN |
186 | for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) { |
187 | if (rate == hdmi_aud_ncts[i].sample_rate && | |
188 | adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) { | |
189 | return hdmi_aud_ncts[i].n; | |
4a21ef7d LY |
190 | } |
191 | } | |
192 | return 0; | |
193 | } | |
194 | ||
7c10a2b5 | 195 | static bool intel_eld_uptodate(struct drm_connector *connector, |
f0f59a00 VS |
196 | i915_reg_t reg_eldv, uint32_t bits_eldv, |
197 | i915_reg_t reg_elda, uint32_t bits_elda, | |
198 | i915_reg_t reg_edid) | |
7c10a2b5 | 199 | { |
fac5e23e | 200 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
7c10a2b5 | 201 | uint8_t *eld = connector->eld; |
f9f682ae JN |
202 | uint32_t tmp; |
203 | int i; | |
7c10a2b5 | 204 | |
f9f682ae JN |
205 | tmp = I915_READ(reg_eldv); |
206 | tmp &= bits_eldv; | |
7c10a2b5 | 207 | |
f9f682ae | 208 | if (!tmp) |
7c10a2b5 JN |
209 | return false; |
210 | ||
f9f682ae JN |
211 | tmp = I915_READ(reg_elda); |
212 | tmp &= ~bits_elda; | |
213 | I915_WRITE(reg_elda, tmp); | |
7c10a2b5 | 214 | |
938fd8aa | 215 | for (i = 0; i < drm_eld_size(eld) / 4; i++) |
7c10a2b5 JN |
216 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
217 | return false; | |
218 | ||
219 | return true; | |
220 | } | |
221 | ||
76d8d3e5 JN |
222 | static void g4x_audio_codec_disable(struct intel_encoder *encoder) |
223 | { | |
fac5e23e | 224 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
76d8d3e5 JN |
225 | uint32_t eldv, tmp; |
226 | ||
227 | DRM_DEBUG_KMS("Disable audio codec\n"); | |
228 | ||
229 | tmp = I915_READ(G4X_AUD_VID_DID); | |
230 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
231 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
232 | else | |
233 | eldv = G4X_ELDV_DEVCTG; | |
234 | ||
235 | /* Invalidate ELD */ | |
236 | tmp = I915_READ(G4X_AUD_CNTL_ST); | |
237 | tmp &= ~eldv; | |
238 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
239 | } | |
240 | ||
69bfe1a9 JN |
241 | static void g4x_audio_codec_enable(struct drm_connector *connector, |
242 | struct intel_encoder *encoder, | |
5e7234c9 | 243 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 | 244 | { |
fac5e23e | 245 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
7c10a2b5 JN |
246 | uint8_t *eld = connector->eld; |
247 | uint32_t eldv; | |
f9f682ae JN |
248 | uint32_t tmp; |
249 | int len, i; | |
7c10a2b5 | 250 | |
d5ee08de JN |
251 | DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); |
252 | ||
f9f682ae JN |
253 | tmp = I915_READ(G4X_AUD_VID_DID); |
254 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
7c10a2b5 JN |
255 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
256 | else | |
257 | eldv = G4X_ELDV_DEVCTG; | |
258 | ||
259 | if (intel_eld_uptodate(connector, | |
260 | G4X_AUD_CNTL_ST, eldv, | |
c46f111f | 261 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, |
7c10a2b5 JN |
262 | G4X_HDMIW_HDMIEDID)) |
263 | return; | |
264 | ||
f9f682ae | 265 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
c46f111f | 266 | tmp &= ~(eldv | G4X_ELD_ADDR_MASK); |
f9f682ae JN |
267 | len = (tmp >> 9) & 0x1f; /* ELD buffer size */ |
268 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 | 269 | |
938fd8aa | 270 | len = min(drm_eld_size(eld) / 4, len); |
7c10a2b5 JN |
271 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
272 | for (i = 0; i < len; i++) | |
273 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
274 | ||
f9f682ae JN |
275 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
276 | tmp |= eldv; | |
277 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 JN |
278 | } |
279 | ||
12e87f23 JN |
280 | static void |
281 | hsw_dp_audio_config_update(struct intel_crtc *intel_crtc, enum port port, | |
282 | const struct drm_display_mode *adjusted_mode) | |
283 | { | |
284 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
6014ac12 LY |
285 | struct i915_audio_component *acomp = dev_priv->audio_component; |
286 | int rate = acomp ? acomp->aud_sample_rate[port] : 0; | |
287 | const struct dp_aud_n_m *nm = audio_config_dp_get_n_m(intel_crtc, rate); | |
12e87f23 JN |
288 | enum pipe pipe = intel_crtc->pipe; |
289 | u32 tmp; | |
290 | ||
6014ac12 LY |
291 | if (nm) |
292 | DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n); | |
293 | else | |
294 | DRM_DEBUG_KMS("using automatic Maud, Naud\n"); | |
295 | ||
12e87f23 JN |
296 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
297 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
298 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
299 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
300 | tmp |= AUD_CONFIG_N_VALUE_INDEX; | |
301 | ||
6014ac12 LY |
302 | if (nm) { |
303 | tmp &= ~AUD_CONFIG_N_MASK; | |
304 | tmp |= AUD_CONFIG_N(nm->n); | |
305 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
306 | } | |
307 | ||
12e87f23 | 308 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
6014ac12 LY |
309 | |
310 | tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe)); | |
311 | tmp &= ~AUD_CONFIG_M_MASK; | |
312 | tmp &= ~AUD_M_CTS_M_VALUE_INDEX; | |
313 | tmp &= ~AUD_M_CTS_M_PROG_ENABLE; | |
314 | ||
315 | if (nm) { | |
316 | tmp |= nm->m; | |
317 | tmp |= AUD_M_CTS_M_VALUE_INDEX; | |
318 | tmp |= AUD_M_CTS_M_PROG_ENABLE; | |
319 | } | |
320 | ||
321 | I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp); | |
12e87f23 JN |
322 | } |
323 | ||
324 | static void | |
325 | hsw_hdmi_audio_config_update(struct intel_crtc *intel_crtc, enum port port, | |
326 | const struct drm_display_mode *adjusted_mode) | |
6c26291d JN |
327 | { |
328 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
329 | struct i915_audio_component *acomp = dev_priv->audio_component; | |
3af306d9 | 330 | int rate = acomp ? acomp->aud_sample_rate[port] : 0; |
6c26291d | 331 | enum pipe pipe = intel_crtc->pipe; |
3af306d9 | 332 | int n; |
6c26291d JN |
333 | u32 tmp; |
334 | ||
335 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
336 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
337 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
6c26291d | 338 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
12e87f23 JN |
339 | tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); |
340 | ||
9ca89c44 JN |
341 | n = audio_config_hdmi_get_n(adjusted_mode, rate); |
342 | if (n != 0) { | |
343 | DRM_DEBUG_KMS("using N %d\n", n); | |
344 | ||
345 | tmp &= ~AUD_CONFIG_N_MASK; | |
346 | tmp |= AUD_CONFIG_N(n); | |
347 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
348 | } else { | |
349 | DRM_DEBUG_KMS("using automatic N\n"); | |
6c26291d JN |
350 | } |
351 | ||
352 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
6014ac12 | 353 | |
b9f16ff2 LY |
354 | /* |
355 | * Let's disable "Enable CTS or M Prog bit" | |
356 | * and let HW calculate the value | |
357 | */ | |
6014ac12 | 358 | tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe)); |
b9f16ff2 | 359 | tmp &= ~AUD_M_CTS_M_PROG_ENABLE; |
6014ac12 | 360 | tmp &= ~AUD_M_CTS_M_VALUE_INDEX; |
6014ac12 | 361 | I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp); |
6c26291d JN |
362 | } |
363 | ||
12e87f23 JN |
364 | static void |
365 | hsw_audio_config_update(struct intel_crtc *intel_crtc, enum port port, | |
366 | const struct drm_display_mode *adjusted_mode) | |
367 | { | |
368 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) | |
369 | hsw_dp_audio_config_update(intel_crtc, port, adjusted_mode); | |
370 | else | |
371 | hsw_hdmi_audio_config_update(intel_crtc, port, adjusted_mode); | |
372 | } | |
373 | ||
69bfe1a9 JN |
374 | static void hsw_audio_codec_disable(struct intel_encoder *encoder) |
375 | { | |
fac5e23e | 376 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5fad84a7 JN |
377 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
378 | enum pipe pipe = intel_crtc->pipe; | |
69bfe1a9 JN |
379 | uint32_t tmp; |
380 | ||
5fad84a7 JN |
381 | DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); |
382 | ||
4a21ef7d LY |
383 | mutex_lock(&dev_priv->av_mutex); |
384 | ||
5fad84a7 JN |
385 | /* Disable timestamps */ |
386 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
387 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
388 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
389 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
390 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
2210ce7f | 391 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5fad84a7 JN |
392 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
393 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
394 | ||
395 | /* Invalidate ELD */ | |
69bfe1a9 | 396 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 397 | tmp &= ~AUDIO_ELD_VALID(pipe); |
eb45fa0b | 398 | tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); |
69bfe1a9 | 399 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
4a21ef7d LY |
400 | |
401 | mutex_unlock(&dev_priv->av_mutex); | |
69bfe1a9 JN |
402 | } |
403 | ||
404 | static void hsw_audio_codec_enable(struct drm_connector *connector, | |
d8dee42a | 405 | struct intel_encoder *intel_encoder, |
5e7234c9 | 406 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 | 407 | { |
fac5e23e | 408 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
d8dee42a | 409 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
5fad84a7 | 410 | enum pipe pipe = intel_crtc->pipe; |
d8dee42a | 411 | enum port port = intel_encoder->port; |
5fad84a7 | 412 | const uint8_t *eld = connector->eld; |
f9f682ae JN |
413 | uint32_t tmp; |
414 | int len, i; | |
7c10a2b5 | 415 | |
5fad84a7 | 416 | DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", |
938fd8aa | 417 | pipe_name(pipe), drm_eld_size(eld)); |
7c10a2b5 | 418 | |
4a21ef7d LY |
419 | mutex_lock(&dev_priv->av_mutex); |
420 | ||
5fad84a7 JN |
421 | /* Enable audio presence detect, invalidate ELD */ |
422 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
82910ac6 JN |
423 | tmp |= AUDIO_OUTPUT_ENABLE(pipe); |
424 | tmp &= ~AUDIO_ELD_VALID(pipe); | |
5fad84a7 | 425 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
7c10a2b5 | 426 | |
5fad84a7 JN |
427 | /* |
428 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
429 | * disabled during the mode set. The proper fix would be to push the | |
430 | * rest of the setup into a vblank work item, queued here, but the | |
431 | * infrastructure is not there yet. | |
432 | */ | |
7c10a2b5 | 433 | |
5fad84a7 JN |
434 | /* Reset ELD write address */ |
435 | tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); | |
c46f111f | 436 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
5fad84a7 | 437 | I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); |
7c10a2b5 | 438 | |
5fad84a7 | 439 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
440 | len = min(drm_eld_size(eld), 84); |
441 | for (i = 0; i < len / 4; i++) | |
5fad84a7 | 442 | I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); |
7c10a2b5 | 443 | |
5fad84a7 | 444 | /* ELD valid */ |
69bfe1a9 | 445 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 446 | tmp |= AUDIO_ELD_VALID(pipe); |
69bfe1a9 | 447 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
5fad84a7 JN |
448 | |
449 | /* Enable timestamps */ | |
6c26291d | 450 | hsw_audio_config_update(intel_crtc, port, adjusted_mode); |
4a21ef7d LY |
451 | |
452 | mutex_unlock(&dev_priv->av_mutex); | |
7c10a2b5 JN |
453 | } |
454 | ||
d8dee42a | 455 | static void ilk_audio_codec_disable(struct intel_encoder *intel_encoder) |
495a5bb8 | 456 | { |
d8dee42a PD |
457 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
458 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
495a5bb8 | 459 | enum pipe pipe = intel_crtc->pipe; |
d8dee42a | 460 | enum port port = intel_encoder->port; |
495a5bb8 | 461 | uint32_t tmp, eldv; |
f0f59a00 | 462 | i915_reg_t aud_config, aud_cntrl_st2; |
495a5bb8 JN |
463 | |
464 | DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", | |
465 | port_name(port), pipe_name(pipe)); | |
466 | ||
d3902c3e JN |
467 | if (WARN_ON(port == PORT_A)) |
468 | return; | |
469 | ||
2d1fe073 | 470 | if (HAS_PCH_IBX(dev_priv)) { |
495a5bb8 JN |
471 | aud_config = IBX_AUD_CFG(pipe); |
472 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
666a4537 | 473 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
495a5bb8 JN |
474 | aud_config = VLV_AUD_CFG(pipe); |
475 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
476 | } else { | |
477 | aud_config = CPT_AUD_CFG(pipe); | |
478 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
479 | } | |
480 | ||
481 | /* Disable timestamps */ | |
482 | tmp = I915_READ(aud_config); | |
483 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
484 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
485 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
486 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
2210ce7f | 487 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
495a5bb8 JN |
488 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
489 | I915_WRITE(aud_config, tmp); | |
490 | ||
d3902c3e | 491 | eldv = IBX_ELD_VALID(port); |
495a5bb8 JN |
492 | |
493 | /* Invalidate ELD */ | |
494 | tmp = I915_READ(aud_cntrl_st2); | |
495 | tmp &= ~eldv; | |
496 | I915_WRITE(aud_cntrl_st2, tmp); | |
497 | } | |
498 | ||
69bfe1a9 | 499 | static void ilk_audio_codec_enable(struct drm_connector *connector, |
d8dee42a | 500 | struct intel_encoder *intel_encoder, |
5e7234c9 | 501 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 | 502 | { |
fac5e23e | 503 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
d8dee42a | 504 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
c6bde93b | 505 | enum pipe pipe = intel_crtc->pipe; |
d8dee42a | 506 | enum port port = intel_encoder->port; |
7c10a2b5 | 507 | uint8_t *eld = connector->eld; |
38cb2eca | 508 | uint32_t tmp, eldv; |
f9f682ae | 509 | int len, i; |
f0f59a00 | 510 | i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; |
c6bde93b JN |
511 | |
512 | DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", | |
938fd8aa | 513 | port_name(port), pipe_name(pipe), drm_eld_size(eld)); |
c6bde93b | 514 | |
d3902c3e JN |
515 | if (WARN_ON(port == PORT_A)) |
516 | return; | |
517 | ||
c6bde93b JN |
518 | /* |
519 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
520 | * disabled during the mode set. The proper fix would be to push the | |
521 | * rest of the setup into a vblank work item, queued here, but the | |
522 | * infrastructure is not there yet. | |
523 | */ | |
7c10a2b5 | 524 | |
6e266956 | 525 | if (HAS_PCH_IBX(dev_priv)) { |
7c10a2b5 JN |
526 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
527 | aud_config = IBX_AUD_CFG(pipe); | |
528 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
529 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
920a14b2 TU |
530 | } else if (IS_VALLEYVIEW(dev_priv) || |
531 | IS_CHERRYVIEW(dev_priv)) { | |
7c10a2b5 JN |
532 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
533 | aud_config = VLV_AUD_CFG(pipe); | |
534 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
535 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
536 | } else { | |
537 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); | |
538 | aud_config = CPT_AUD_CFG(pipe); | |
539 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
540 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
541 | } | |
542 | ||
d3902c3e | 543 | eldv = IBX_ELD_VALID(port); |
7c10a2b5 | 544 | |
c6bde93b | 545 | /* Invalidate ELD */ |
f9f682ae JN |
546 | tmp = I915_READ(aud_cntrl_st2); |
547 | tmp &= ~eldv; | |
548 | I915_WRITE(aud_cntrl_st2, tmp); | |
7c10a2b5 | 549 | |
c6bde93b | 550 | /* Reset ELD write address */ |
f9f682ae | 551 | tmp = I915_READ(aud_cntl_st); |
c46f111f | 552 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
f9f682ae | 553 | I915_WRITE(aud_cntl_st, tmp); |
7c10a2b5 | 554 | |
c6bde93b | 555 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
556 | len = min(drm_eld_size(eld), 84); |
557 | for (i = 0; i < len / 4; i++) | |
7c10a2b5 JN |
558 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
559 | ||
c6bde93b | 560 | /* ELD valid */ |
f9f682ae JN |
561 | tmp = I915_READ(aud_cntrl_st2); |
562 | tmp |= eldv; | |
563 | I915_WRITE(aud_cntrl_st2, tmp); | |
c6bde93b JN |
564 | |
565 | /* Enable timestamps */ | |
566 | tmp = I915_READ(aud_config); | |
567 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
568 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
569 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
2210ce7f | 570 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
c6bde93b JN |
571 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
572 | else | |
5e7234c9 | 573 | tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); |
c6bde93b | 574 | I915_WRITE(aud_config, tmp); |
7c10a2b5 JN |
575 | } |
576 | ||
69bfe1a9 JN |
577 | /** |
578 | * intel_audio_codec_enable - Enable the audio codec for HD audio | |
579 | * @intel_encoder: encoder on which to enable audio | |
bbf35e9d ML |
580 | * @crtc_state: pointer to the current crtc state. |
581 | * @conn_state: pointer to the current connector state. | |
69bfe1a9 JN |
582 | * |
583 | * The enable sequences may only be performed after enabling the transcoder and | |
584 | * port, and after completed link training. | |
585 | */ | |
bbf35e9d ML |
586 | void intel_audio_codec_enable(struct intel_encoder *intel_encoder, |
587 | const struct intel_crtc_state *crtc_state, | |
588 | const struct drm_connector_state *conn_state) | |
7c10a2b5 | 589 | { |
33d1e7c6 | 590 | struct drm_encoder *encoder = &intel_encoder->base; |
bbf35e9d | 591 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; |
7c10a2b5 | 592 | struct drm_connector *connector; |
d8dee42a | 593 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
51e1d83c | 594 | struct i915_audio_component *acomp = dev_priv->audio_component; |
d8dee42a | 595 | enum port port = intel_encoder->port; |
bbf35e9d | 596 | enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; |
7c10a2b5 | 597 | |
bbf35e9d ML |
598 | connector = conn_state->connector; |
599 | if (!connector || !connector->eld[0]) | |
7c10a2b5 JN |
600 | return; |
601 | ||
602 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
603 | connector->base.id, | |
604 | connector->name, | |
605 | connector->encoder->base.id, | |
606 | connector->encoder->name); | |
607 | ||
6189b036 JN |
608 | /* ELD Conn_Type */ |
609 | connector->eld[5] &= ~(3 << 2); | |
bbf35e9d | 610 | if (intel_crtc_has_dp_encoder(crtc_state)) |
6189b036 JN |
611 | connector->eld[5] |= (1 << 2); |
612 | ||
124abe07 | 613 | connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; |
7c10a2b5 | 614 | |
69bfe1a9 | 615 | if (dev_priv->display.audio_codec_enable) |
124abe07 VS |
616 | dev_priv->display.audio_codec_enable(connector, intel_encoder, |
617 | adjusted_mode); | |
51e1d83c | 618 | |
cae666ce | 619 | mutex_lock(&dev_priv->av_mutex); |
f1a3acea | 620 | intel_encoder->audio_connector = connector; |
f9318941 | 621 | |
9dfbffcf | 622 | /* referred in audio callbacks */ |
f9318941 | 623 | dev_priv->av_enc_map[pipe] = intel_encoder; |
cae666ce TI |
624 | mutex_unlock(&dev_priv->av_mutex); |
625 | ||
f9318941 PD |
626 | /* audio drivers expect pipe = -1 to indicate Non-MST cases */ |
627 | if (intel_encoder->type != INTEL_OUTPUT_DP_MST) | |
628 | pipe = -1; | |
629 | ||
51e1d83c | 630 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) |
f9318941 PD |
631 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, |
632 | (int) port, (int) pipe); | |
69bfe1a9 JN |
633 | } |
634 | ||
635 | /** | |
636 | * intel_audio_codec_disable - Disable the audio codec for HD audio | |
95d0be61 | 637 | * @intel_encoder: encoder on which to disable audio |
69bfe1a9 JN |
638 | * |
639 | * The disable sequences must be performed before disabling the transcoder or | |
640 | * port. | |
641 | */ | |
51e1d83c | 642 | void intel_audio_codec_disable(struct intel_encoder *intel_encoder) |
69bfe1a9 | 643 | { |
51e1d83c | 644 | struct drm_encoder *encoder = &intel_encoder->base; |
d8dee42a | 645 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
51e1d83c | 646 | struct i915_audio_component *acomp = dev_priv->audio_component; |
d8dee42a | 647 | enum port port = intel_encoder->port; |
f9318941 PD |
648 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
649 | enum pipe pipe = crtc->pipe; | |
69bfe1a9 JN |
650 | |
651 | if (dev_priv->display.audio_codec_disable) | |
51e1d83c DH |
652 | dev_priv->display.audio_codec_disable(intel_encoder); |
653 | ||
cae666ce | 654 | mutex_lock(&dev_priv->av_mutex); |
f1a3acea | 655 | intel_encoder->audio_connector = NULL; |
f9318941 | 656 | dev_priv->av_enc_map[pipe] = NULL; |
cae666ce TI |
657 | mutex_unlock(&dev_priv->av_mutex); |
658 | ||
f9318941 PD |
659 | /* audio drivers expect pipe = -1 to indicate Non-MST cases */ |
660 | if (intel_encoder->type != INTEL_OUTPUT_DP_MST) | |
661 | pipe = -1; | |
662 | ||
51e1d83c | 663 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) |
f9318941 PD |
664 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, |
665 | (int) port, (int) pipe); | |
7c10a2b5 JN |
666 | } |
667 | ||
668 | /** | |
88212941 ID |
669 | * intel_init_audio_hooks - Set up chip specific audio hooks |
670 | * @dev_priv: device private | |
7c10a2b5 | 671 | */ |
88212941 | 672 | void intel_init_audio_hooks(struct drm_i915_private *dev_priv) |
7c10a2b5 | 673 | { |
88212941 | 674 | if (IS_G4X(dev_priv)) { |
69bfe1a9 | 675 | dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; |
76d8d3e5 | 676 | dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; |
88212941 | 677 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
69bfe1a9 | 678 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
495a5bb8 | 679 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
88212941 | 680 | } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) { |
69bfe1a9 JN |
681 | dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; |
682 | dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; | |
88212941 | 683 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
69bfe1a9 | 684 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
495a5bb8 | 685 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
69bfe1a9 | 686 | } |
7c10a2b5 | 687 | } |
58fddc28 | 688 | |
c49d13ee | 689 | static void i915_audio_component_get_power(struct device *kdev) |
58fddc28 | 690 | { |
c49d13ee | 691 | intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO); |
58fddc28 ID |
692 | } |
693 | ||
c49d13ee | 694 | static void i915_audio_component_put_power(struct device *kdev) |
58fddc28 | 695 | { |
c49d13ee | 696 | intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO); |
58fddc28 ID |
697 | } |
698 | ||
c49d13ee | 699 | static void i915_audio_component_codec_wake_override(struct device *kdev, |
632f3ab9 LH |
700 | bool enable) |
701 | { | |
c49d13ee | 702 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
632f3ab9 LH |
703 | u32 tmp; |
704 | ||
ef11bdb3 | 705 | if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) |
632f3ab9 LH |
706 | return; |
707 | ||
c49d13ee | 708 | i915_audio_component_get_power(kdev); |
d838a110 | 709 | |
632f3ab9 LH |
710 | /* |
711 | * Enable/disable generating the codec wake signal, overriding the | |
712 | * internal logic to generate the codec wake to controller. | |
713 | */ | |
714 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
715 | tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; | |
716 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
717 | usleep_range(1000, 1500); | |
718 | ||
719 | if (enable) { | |
720 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
721 | tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; | |
722 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
723 | usleep_range(1000, 1500); | |
724 | } | |
d838a110 | 725 | |
c49d13ee | 726 | i915_audio_component_put_power(kdev); |
632f3ab9 LH |
727 | } |
728 | ||
58fddc28 | 729 | /* Get CDCLK in kHz */ |
c49d13ee | 730 | static int i915_audio_component_get_cdclk_freq(struct device *kdev) |
58fddc28 | 731 | { |
c49d13ee | 732 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
58fddc28 ID |
733 | |
734 | if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) | |
735 | return -ENODEV; | |
736 | ||
1033f92e | 737 | return dev_priv->cdclk_freq; |
58fddc28 ID |
738 | } |
739 | ||
f9318941 PD |
740 | static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, |
741 | int port, int pipe) | |
742 | { | |
743 | ||
744 | if (WARN_ON(pipe >= I915_MAX_PIPES)) | |
745 | return NULL; | |
746 | ||
747 | /* MST */ | |
748 | if (pipe >= 0) | |
749 | return dev_priv->av_enc_map[pipe]; | |
750 | ||
751 | /* Non-MST */ | |
752 | for_each_pipe(dev_priv, pipe) { | |
753 | struct intel_encoder *encoder; | |
754 | ||
755 | encoder = dev_priv->av_enc_map[pipe]; | |
756 | if (encoder == NULL) | |
757 | continue; | |
758 | ||
759 | if (port == encoder->port) | |
760 | return encoder; | |
761 | } | |
762 | ||
763 | return NULL; | |
764 | } | |
765 | ||
766 | static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, | |
767 | int pipe, int rate) | |
4a21ef7d | 768 | { |
c49d13ee | 769 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
4a21ef7d | 770 | struct intel_encoder *intel_encoder; |
4a21ef7d | 771 | struct intel_crtc *crtc; |
8f1ec181 | 772 | struct drm_display_mode *adjusted_mode; |
7e8275c2 | 773 | struct i915_audio_component *acomp = dev_priv->audio_component; |
0bdf5a05 | 774 | int err = 0; |
4a21ef7d | 775 | |
4bd2d6f6 | 776 | if (!HAS_DDI(dev_priv)) |
4a21ef7d LY |
777 | return 0; |
778 | ||
c49d13ee | 779 | i915_audio_component_get_power(kdev); |
4a21ef7d | 780 | mutex_lock(&dev_priv->av_mutex); |
f9318941 | 781 | |
4a21ef7d | 782 | /* 1. get the pipe */ |
f9318941 | 783 | intel_encoder = get_saved_enc(dev_priv, port, pipe); |
0bdf5a05 | 784 | if (!intel_encoder || !intel_encoder->base.crtc || |
6014ac12 LY |
785 | (intel_encoder->type != INTEL_OUTPUT_HDMI && |
786 | intel_encoder->type != INTEL_OUTPUT_DP)) { | |
f9318941 | 787 | DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); |
0bdf5a05 TI |
788 | err = -ENODEV; |
789 | goto unlock; | |
4a21ef7d | 790 | } |
f9318941 PD |
791 | |
792 | /* pipe passed from the audio driver will be -1 for Non-MST case */ | |
0bdf5a05 TI |
793 | crtc = to_intel_crtc(intel_encoder->base.crtc); |
794 | pipe = crtc->pipe; | |
0bdf5a05 | 795 | |
8f1ec181 | 796 | adjusted_mode = &crtc->config->base.adjusted_mode; |
4a21ef7d | 797 | |
7e8275c2 LY |
798 | /* port must be valid now, otherwise the pipe will be invalid */ |
799 | acomp->aud_sample_rate[port] = rate; | |
800 | ||
8f1ec181 | 801 | hsw_audio_config_update(crtc, port, adjusted_mode); |
4a21ef7d | 802 | |
0bdf5a05 | 803 | unlock: |
4a21ef7d | 804 | mutex_unlock(&dev_priv->av_mutex); |
c49d13ee | 805 | i915_audio_component_put_power(kdev); |
0bdf5a05 | 806 | return err; |
4a21ef7d LY |
807 | } |
808 | ||
c49d13ee | 809 | static int i915_audio_component_get_eld(struct device *kdev, int port, |
f9318941 | 810 | int pipe, bool *enabled, |
cae666ce TI |
811 | unsigned char *buf, int max_bytes) |
812 | { | |
c49d13ee | 813 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
cae666ce | 814 | struct intel_encoder *intel_encoder; |
cae666ce TI |
815 | const u8 *eld; |
816 | int ret = -EINVAL; | |
817 | ||
818 | mutex_lock(&dev_priv->av_mutex); | |
f9318941 PD |
819 | |
820 | intel_encoder = get_saved_enc(dev_priv, port, pipe); | |
821 | if (!intel_encoder) { | |
822 | DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); | |
823 | mutex_unlock(&dev_priv->av_mutex); | |
824 | return ret; | |
825 | } | |
826 | ||
827 | ret = 0; | |
828 | *enabled = intel_encoder->audio_connector != NULL; | |
829 | if (*enabled) { | |
830 | eld = intel_encoder->audio_connector->eld; | |
831 | ret = drm_eld_size(eld); | |
832 | memcpy(buf, eld, min(max_bytes, ret)); | |
cae666ce TI |
833 | } |
834 | ||
835 | mutex_unlock(&dev_priv->av_mutex); | |
836 | return ret; | |
4a21ef7d LY |
837 | } |
838 | ||
58fddc28 ID |
839 | static const struct i915_audio_component_ops i915_audio_component_ops = { |
840 | .owner = THIS_MODULE, | |
841 | .get_power = i915_audio_component_get_power, | |
842 | .put_power = i915_audio_component_put_power, | |
632f3ab9 | 843 | .codec_wake_override = i915_audio_component_codec_wake_override, |
58fddc28 | 844 | .get_cdclk_freq = i915_audio_component_get_cdclk_freq, |
4a21ef7d | 845 | .sync_audio_rate = i915_audio_component_sync_audio_rate, |
cae666ce | 846 | .get_eld = i915_audio_component_get_eld, |
58fddc28 ID |
847 | }; |
848 | ||
c49d13ee DW |
849 | static int i915_audio_component_bind(struct device *i915_kdev, |
850 | struct device *hda_kdev, void *data) | |
58fddc28 ID |
851 | { |
852 | struct i915_audio_component *acomp = data; | |
c49d13ee | 853 | struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); |
7e8275c2 | 854 | int i; |
58fddc28 ID |
855 | |
856 | if (WARN_ON(acomp->ops || acomp->dev)) | |
857 | return -EEXIST; | |
858 | ||
91c8a326 | 859 | drm_modeset_lock_all(&dev_priv->drm); |
58fddc28 | 860 | acomp->ops = &i915_audio_component_ops; |
c49d13ee | 861 | acomp->dev = i915_kdev; |
7e8275c2 LY |
862 | BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); |
863 | for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) | |
864 | acomp->aud_sample_rate[i] = 0; | |
51e1d83c | 865 | dev_priv->audio_component = acomp; |
91c8a326 | 866 | drm_modeset_unlock_all(&dev_priv->drm); |
58fddc28 ID |
867 | |
868 | return 0; | |
869 | } | |
870 | ||
c49d13ee DW |
871 | static void i915_audio_component_unbind(struct device *i915_kdev, |
872 | struct device *hda_kdev, void *data) | |
58fddc28 ID |
873 | { |
874 | struct i915_audio_component *acomp = data; | |
c49d13ee | 875 | struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); |
58fddc28 | 876 | |
91c8a326 | 877 | drm_modeset_lock_all(&dev_priv->drm); |
58fddc28 ID |
878 | acomp->ops = NULL; |
879 | acomp->dev = NULL; | |
51e1d83c | 880 | dev_priv->audio_component = NULL; |
91c8a326 | 881 | drm_modeset_unlock_all(&dev_priv->drm); |
58fddc28 ID |
882 | } |
883 | ||
884 | static const struct component_ops i915_audio_component_bind_ops = { | |
885 | .bind = i915_audio_component_bind, | |
886 | .unbind = i915_audio_component_unbind, | |
887 | }; | |
888 | ||
889 | /** | |
890 | * i915_audio_component_init - initialize and register the audio component | |
891 | * @dev_priv: i915 device instance | |
892 | * | |
893 | * This will register with the component framework a child component which | |
894 | * will bind dynamically to the snd_hda_intel driver's corresponding master | |
895 | * component when the latter is registered. During binding the child | |
896 | * initializes an instance of struct i915_audio_component which it receives | |
897 | * from the master. The master can then start to use the interface defined by | |
898 | * this struct. Each side can break the binding at any point by deregistering | |
899 | * its own component after which each side's component unbind callback is | |
900 | * called. | |
901 | * | |
902 | * We ignore any error during registration and continue with reduced | |
903 | * functionality (i.e. without HDMI audio). | |
904 | */ | |
905 | void i915_audio_component_init(struct drm_i915_private *dev_priv) | |
906 | { | |
907 | int ret; | |
908 | ||
91c8a326 | 909 | ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops); |
58fddc28 ID |
910 | if (ret < 0) { |
911 | DRM_ERROR("failed to add audio component (%d)\n", ret); | |
912 | /* continue with reduced functionality */ | |
913 | return; | |
914 | } | |
915 | ||
916 | dev_priv->audio_component_registered = true; | |
917 | } | |
918 | ||
919 | /** | |
920 | * i915_audio_component_cleanup - deregister the audio component | |
921 | * @dev_priv: i915 device instance | |
922 | * | |
923 | * Deregisters the audio component, breaking any existing binding to the | |
924 | * corresponding snd_hda_intel driver's master component. | |
925 | */ | |
926 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) | |
927 | { | |
928 | if (!dev_priv->audio_component_registered) | |
929 | return; | |
930 | ||
91c8a326 | 931 | component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); |
58fddc28 ID |
932 | dev_priv->audio_component_registered = false; |
933 | } | |
eef57324 JA |
934 | |
935 | /** | |
936 | * intel_audio_init() - Initialize the audio driver either using | |
937 | * component framework or using lpe audio bridge | |
938 | * @dev_priv: the i915 drm device private data | |
939 | * | |
940 | */ | |
941 | void intel_audio_init(struct drm_i915_private *dev_priv) | |
942 | { | |
943 | if (intel_lpe_audio_init(dev_priv) < 0) | |
944 | i915_audio_component_init(dev_priv); | |
945 | } | |
946 | ||
947 | /** | |
948 | * intel_audio_deinit() - deinitialize the audio driver | |
949 | * @dev_priv: the i915 drm device private data | |
950 | * | |
951 | */ | |
952 | void intel_audio_deinit(struct drm_i915_private *dev_priv) | |
953 | { | |
954 | if ((dev_priv)->lpe_audio.platdev != NULL) | |
955 | intel_lpe_audio_teardown(dev_priv); | |
956 | else | |
957 | i915_audio_component_cleanup(dev_priv); | |
958 | } |