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7c10a2b5 JN |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
58fddc28 ID |
25 | #include <linux/component.h> |
26 | #include <drm/i915_component.h> | |
27 | #include "intel_drv.h" | |
7c10a2b5 JN |
28 | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/drm_edid.h> | |
7c10a2b5 JN |
31 | #include "i915_drv.h" |
32 | ||
28855d2a JN |
33 | /** |
34 | * DOC: High Definition Audio over HDMI and Display Port | |
35 | * | |
36 | * The graphics and audio drivers together support High Definition Audio over | |
37 | * HDMI and Display Port. The audio programming sequences are divided into audio | |
38 | * codec and controller enable and disable sequences. The graphics driver | |
39 | * handles the audio codec sequences, while the audio driver handles the audio | |
40 | * controller sequences. | |
41 | * | |
42 | * The disable sequences must be performed before disabling the transcoder or | |
43 | * port. The enable sequences may only be performed after enabling the | |
44 | * transcoder and port, and after completed link training. | |
45 | * | |
46 | * The codec and controller sequences could be done either parallel or serial, | |
47 | * but generally the ELDV/PD change in the codec sequence indicates to the audio | |
48 | * driver that the controller sequence should start. Indeed, most of the | |
49 | * co-operation between the graphics and audio drivers is handled via audio | |
50 | * related registers. (The notable exception is the power management, not | |
51 | * covered here.) | |
52 | */ | |
53 | ||
87fcb2ad | 54 | static const struct { |
7c10a2b5 JN |
55 | int clock; |
56 | u32 config; | |
57 | } hdmi_audio_clock[] = { | |
58 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
59 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
60 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
61 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
62 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
63 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
64 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
65 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
66 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
67 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
68 | }; | |
69 | ||
70 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
71 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
72 | { | |
73 | int i; | |
74 | ||
75 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
76 | if (mode->clock == hdmi_audio_clock[i].clock) | |
77 | break; | |
78 | } | |
79 | ||
80 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
81 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
82 | i = 1; | |
83 | } | |
84 | ||
85 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
86 | hdmi_audio_clock[i].clock, | |
87 | hdmi_audio_clock[i].config); | |
88 | ||
89 | return hdmi_audio_clock[i].config; | |
90 | } | |
91 | ||
92 | static bool intel_eld_uptodate(struct drm_connector *connector, | |
93 | int reg_eldv, uint32_t bits_eldv, | |
94 | int reg_elda, uint32_t bits_elda, | |
95 | int reg_edid) | |
96 | { | |
97 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
98 | uint8_t *eld = connector->eld; | |
f9f682ae JN |
99 | uint32_t tmp; |
100 | int i; | |
7c10a2b5 | 101 | |
f9f682ae JN |
102 | tmp = I915_READ(reg_eldv); |
103 | tmp &= bits_eldv; | |
7c10a2b5 | 104 | |
f9f682ae | 105 | if (!tmp) |
7c10a2b5 JN |
106 | return false; |
107 | ||
f9f682ae JN |
108 | tmp = I915_READ(reg_elda); |
109 | tmp &= ~bits_elda; | |
110 | I915_WRITE(reg_elda, tmp); | |
7c10a2b5 | 111 | |
938fd8aa | 112 | for (i = 0; i < drm_eld_size(eld) / 4; i++) |
7c10a2b5 JN |
113 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
114 | return false; | |
115 | ||
116 | return true; | |
117 | } | |
118 | ||
76d8d3e5 JN |
119 | static void g4x_audio_codec_disable(struct intel_encoder *encoder) |
120 | { | |
121 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
122 | uint32_t eldv, tmp; | |
123 | ||
124 | DRM_DEBUG_KMS("Disable audio codec\n"); | |
125 | ||
126 | tmp = I915_READ(G4X_AUD_VID_DID); | |
127 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
128 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
129 | else | |
130 | eldv = G4X_ELDV_DEVCTG; | |
131 | ||
132 | /* Invalidate ELD */ | |
133 | tmp = I915_READ(G4X_AUD_CNTL_ST); | |
134 | tmp &= ~eldv; | |
135 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
136 | } | |
137 | ||
69bfe1a9 JN |
138 | static void g4x_audio_codec_enable(struct drm_connector *connector, |
139 | struct intel_encoder *encoder, | |
140 | struct drm_display_mode *mode) | |
7c10a2b5 JN |
141 | { |
142 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
143 | uint8_t *eld = connector->eld; | |
144 | uint32_t eldv; | |
f9f682ae JN |
145 | uint32_t tmp; |
146 | int len, i; | |
7c10a2b5 | 147 | |
d5ee08de JN |
148 | DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); |
149 | ||
f9f682ae JN |
150 | tmp = I915_READ(G4X_AUD_VID_DID); |
151 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
7c10a2b5 JN |
152 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
153 | else | |
154 | eldv = G4X_ELDV_DEVCTG; | |
155 | ||
156 | if (intel_eld_uptodate(connector, | |
157 | G4X_AUD_CNTL_ST, eldv, | |
c46f111f | 158 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, |
7c10a2b5 JN |
159 | G4X_HDMIW_HDMIEDID)) |
160 | return; | |
161 | ||
f9f682ae | 162 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
c46f111f | 163 | tmp &= ~(eldv | G4X_ELD_ADDR_MASK); |
f9f682ae JN |
164 | len = (tmp >> 9) & 0x1f; /* ELD buffer size */ |
165 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 | 166 | |
938fd8aa | 167 | len = min(drm_eld_size(eld) / 4, len); |
7c10a2b5 JN |
168 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
169 | for (i = 0; i < len; i++) | |
170 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
171 | ||
f9f682ae JN |
172 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
173 | tmp |= eldv; | |
174 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 JN |
175 | } |
176 | ||
69bfe1a9 JN |
177 | static void hsw_audio_codec_disable(struct intel_encoder *encoder) |
178 | { | |
5fad84a7 JN |
179 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
180 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
181 | enum pipe pipe = intel_crtc->pipe; | |
69bfe1a9 JN |
182 | uint32_t tmp; |
183 | ||
5fad84a7 JN |
184 | DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); |
185 | ||
186 | /* Disable timestamps */ | |
187 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
188 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
189 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
190 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
191 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
192 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
193 | tmp |= AUD_CONFIG_N_VALUE_INDEX; | |
194 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
195 | ||
196 | /* Invalidate ELD */ | |
69bfe1a9 | 197 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 198 | tmp &= ~AUDIO_ELD_VALID(pipe); |
eb45fa0b | 199 | tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); |
69bfe1a9 JN |
200 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
201 | } | |
202 | ||
203 | static void hsw_audio_codec_enable(struct drm_connector *connector, | |
204 | struct intel_encoder *encoder, | |
205 | struct drm_display_mode *mode) | |
7c10a2b5 JN |
206 | { |
207 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
820d2d77 | 208 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5fad84a7 JN |
209 | enum pipe pipe = intel_crtc->pipe; |
210 | const uint8_t *eld = connector->eld; | |
f9f682ae JN |
211 | uint32_t tmp; |
212 | int len, i; | |
7c10a2b5 | 213 | |
5fad84a7 | 214 | DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", |
938fd8aa | 215 | pipe_name(pipe), drm_eld_size(eld)); |
7c10a2b5 | 216 | |
5fad84a7 JN |
217 | /* Enable audio presence detect, invalidate ELD */ |
218 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
82910ac6 JN |
219 | tmp |= AUDIO_OUTPUT_ENABLE(pipe); |
220 | tmp &= ~AUDIO_ELD_VALID(pipe); | |
5fad84a7 | 221 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
7c10a2b5 | 222 | |
5fad84a7 JN |
223 | /* |
224 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
225 | * disabled during the mode set. The proper fix would be to push the | |
226 | * rest of the setup into a vblank work item, queued here, but the | |
227 | * infrastructure is not there yet. | |
228 | */ | |
7c10a2b5 | 229 | |
5fad84a7 JN |
230 | /* Reset ELD write address */ |
231 | tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); | |
c46f111f | 232 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
5fad84a7 | 233 | I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); |
7c10a2b5 | 234 | |
5fad84a7 | 235 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
236 | len = min(drm_eld_size(eld), 84); |
237 | for (i = 0; i < len / 4; i++) | |
5fad84a7 | 238 | I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); |
7c10a2b5 | 239 | |
5fad84a7 | 240 | /* ELD valid */ |
69bfe1a9 | 241 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 242 | tmp |= AUDIO_ELD_VALID(pipe); |
69bfe1a9 | 243 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
5fad84a7 JN |
244 | |
245 | /* Enable timestamps */ | |
246 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
247 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
248 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
249 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
250 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
251 | tmp |= AUD_CONFIG_N_VALUE_INDEX; | |
252 | else | |
253 | tmp |= audio_config_hdmi_pixel_clock(mode); | |
254 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
7c10a2b5 JN |
255 | } |
256 | ||
495a5bb8 JN |
257 | static void ilk_audio_codec_disable(struct intel_encoder *encoder) |
258 | { | |
259 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
260 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
261 | struct intel_digital_port *intel_dig_port = | |
262 | enc_to_dig_port(&encoder->base); | |
263 | enum port port = intel_dig_port->port; | |
264 | enum pipe pipe = intel_crtc->pipe; | |
265 | uint32_t tmp, eldv; | |
266 | int aud_config; | |
267 | int aud_cntrl_st2; | |
268 | ||
269 | DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", | |
270 | port_name(port), pipe_name(pipe)); | |
271 | ||
d3902c3e JN |
272 | if (WARN_ON(port == PORT_A)) |
273 | return; | |
274 | ||
495a5bb8 JN |
275 | if (HAS_PCH_IBX(dev_priv->dev)) { |
276 | aud_config = IBX_AUD_CFG(pipe); | |
277 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
278 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
279 | aud_config = VLV_AUD_CFG(pipe); | |
280 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
281 | } else { | |
282 | aud_config = CPT_AUD_CFG(pipe); | |
283 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
284 | } | |
285 | ||
286 | /* Disable timestamps */ | |
287 | tmp = I915_READ(aud_config); | |
288 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
289 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
290 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
291 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
292 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
293 | tmp |= AUD_CONFIG_N_VALUE_INDEX; | |
294 | I915_WRITE(aud_config, tmp); | |
295 | ||
d3902c3e | 296 | eldv = IBX_ELD_VALID(port); |
495a5bb8 JN |
297 | |
298 | /* Invalidate ELD */ | |
299 | tmp = I915_READ(aud_cntrl_st2); | |
300 | tmp &= ~eldv; | |
301 | I915_WRITE(aud_cntrl_st2, tmp); | |
302 | } | |
303 | ||
69bfe1a9 JN |
304 | static void ilk_audio_codec_enable(struct drm_connector *connector, |
305 | struct intel_encoder *encoder, | |
306 | struct drm_display_mode *mode) | |
7c10a2b5 JN |
307 | { |
308 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
820d2d77 | 309 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
c6bde93b JN |
310 | struct intel_digital_port *intel_dig_port = |
311 | enc_to_dig_port(&encoder->base); | |
312 | enum port port = intel_dig_port->port; | |
313 | enum pipe pipe = intel_crtc->pipe; | |
7c10a2b5 JN |
314 | uint8_t *eld = connector->eld; |
315 | uint32_t eldv; | |
f9f682ae JN |
316 | uint32_t tmp; |
317 | int len, i; | |
7c10a2b5 JN |
318 | int hdmiw_hdmiedid; |
319 | int aud_config; | |
320 | int aud_cntl_st; | |
321 | int aud_cntrl_st2; | |
c6bde93b JN |
322 | |
323 | DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", | |
938fd8aa | 324 | port_name(port), pipe_name(pipe), drm_eld_size(eld)); |
c6bde93b | 325 | |
d3902c3e JN |
326 | if (WARN_ON(port == PORT_A)) |
327 | return; | |
328 | ||
c6bde93b JN |
329 | /* |
330 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
331 | * disabled during the mode set. The proper fix would be to push the | |
332 | * rest of the setup into a vblank work item, queued here, but the | |
333 | * infrastructure is not there yet. | |
334 | */ | |
7c10a2b5 JN |
335 | |
336 | if (HAS_PCH_IBX(connector->dev)) { | |
337 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); | |
338 | aud_config = IBX_AUD_CFG(pipe); | |
339 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
340 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
341 | } else if (IS_VALLEYVIEW(connector->dev)) { | |
342 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
343 | aud_config = VLV_AUD_CFG(pipe); | |
344 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
345 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
346 | } else { | |
347 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); | |
348 | aud_config = CPT_AUD_CFG(pipe); | |
349 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
350 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
351 | } | |
352 | ||
d3902c3e | 353 | eldv = IBX_ELD_VALID(port); |
7c10a2b5 | 354 | |
c6bde93b | 355 | /* Invalidate ELD */ |
f9f682ae JN |
356 | tmp = I915_READ(aud_cntrl_st2); |
357 | tmp &= ~eldv; | |
358 | I915_WRITE(aud_cntrl_st2, tmp); | |
7c10a2b5 | 359 | |
c6bde93b | 360 | /* Reset ELD write address */ |
f9f682ae | 361 | tmp = I915_READ(aud_cntl_st); |
c46f111f | 362 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
f9f682ae | 363 | I915_WRITE(aud_cntl_st, tmp); |
7c10a2b5 | 364 | |
c6bde93b | 365 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
366 | len = min(drm_eld_size(eld), 84); |
367 | for (i = 0; i < len / 4; i++) | |
7c10a2b5 JN |
368 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
369 | ||
c6bde93b | 370 | /* ELD valid */ |
f9f682ae JN |
371 | tmp = I915_READ(aud_cntrl_st2); |
372 | tmp |= eldv; | |
373 | I915_WRITE(aud_cntrl_st2, tmp); | |
c6bde93b JN |
374 | |
375 | /* Enable timestamps */ | |
376 | tmp = I915_READ(aud_config); | |
377 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
378 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
379 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
380 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
381 | tmp |= AUD_CONFIG_N_VALUE_INDEX; | |
382 | else | |
383 | tmp |= audio_config_hdmi_pixel_clock(mode); | |
384 | I915_WRITE(aud_config, tmp); | |
7c10a2b5 JN |
385 | } |
386 | ||
69bfe1a9 JN |
387 | /** |
388 | * intel_audio_codec_enable - Enable the audio codec for HD audio | |
389 | * @intel_encoder: encoder on which to enable audio | |
390 | * | |
391 | * The enable sequences may only be performed after enabling the transcoder and | |
392 | * port, and after completed link training. | |
393 | */ | |
394 | void intel_audio_codec_enable(struct intel_encoder *intel_encoder) | |
7c10a2b5 | 395 | { |
33d1e7c6 JN |
396 | struct drm_encoder *encoder = &intel_encoder->base; |
397 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 398 | struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
7c10a2b5 JN |
399 | struct drm_connector *connector; |
400 | struct drm_device *dev = encoder->dev; | |
401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
51e1d83c DH |
402 | struct i915_audio_component *acomp = dev_priv->audio_component; |
403 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); | |
404 | enum port port = intel_dig_port->port; | |
7c10a2b5 JN |
405 | |
406 | connector = drm_select_eld(encoder, mode); | |
407 | if (!connector) | |
408 | return; | |
409 | ||
410 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
411 | connector->base.id, | |
412 | connector->name, | |
413 | connector->encoder->base.id, | |
414 | connector->encoder->name); | |
415 | ||
6189b036 JN |
416 | /* ELD Conn_Type */ |
417 | connector->eld[5] &= ~(3 << 2); | |
418 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
419 | connector->eld[5] |= (1 << 2); | |
420 | ||
7c10a2b5 JN |
421 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
422 | ||
69bfe1a9 JN |
423 | if (dev_priv->display.audio_codec_enable) |
424 | dev_priv->display.audio_codec_enable(connector, intel_encoder, mode); | |
51e1d83c DH |
425 | |
426 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) | |
427 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port, 0); | |
69bfe1a9 JN |
428 | } |
429 | ||
430 | /** | |
431 | * intel_audio_codec_disable - Disable the audio codec for HD audio | |
432 | * @encoder: encoder on which to disable audio | |
433 | * | |
434 | * The disable sequences must be performed before disabling the transcoder or | |
435 | * port. | |
436 | */ | |
51e1d83c | 437 | void intel_audio_codec_disable(struct intel_encoder *intel_encoder) |
69bfe1a9 | 438 | { |
51e1d83c DH |
439 | struct drm_encoder *encoder = &intel_encoder->base; |
440 | struct drm_device *dev = encoder->dev; | |
69bfe1a9 | 441 | struct drm_i915_private *dev_priv = dev->dev_private; |
51e1d83c DH |
442 | struct i915_audio_component *acomp = dev_priv->audio_component; |
443 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); | |
444 | enum port port = intel_dig_port->port; | |
69bfe1a9 JN |
445 | |
446 | if (dev_priv->display.audio_codec_disable) | |
51e1d83c DH |
447 | dev_priv->display.audio_codec_disable(intel_encoder); |
448 | ||
449 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) | |
450 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port, 0); | |
7c10a2b5 JN |
451 | } |
452 | ||
453 | /** | |
454 | * intel_init_audio - Set up chip specific audio functions | |
455 | * @dev: drm device | |
456 | */ | |
457 | void intel_init_audio(struct drm_device *dev) | |
458 | { | |
459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
460 | ||
69bfe1a9 JN |
461 | if (IS_G4X(dev)) { |
462 | dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; | |
76d8d3e5 | 463 | dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; |
69bfe1a9 JN |
464 | } else if (IS_VALLEYVIEW(dev)) { |
465 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; | |
495a5bb8 | 466 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
69bfe1a9 JN |
467 | } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) { |
468 | dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; | |
469 | dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; | |
470 | } else if (HAS_PCH_SPLIT(dev)) { | |
471 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; | |
495a5bb8 | 472 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
69bfe1a9 | 473 | } |
7c10a2b5 | 474 | } |
58fddc28 ID |
475 | |
476 | static void i915_audio_component_get_power(struct device *dev) | |
477 | { | |
478 | intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO); | |
479 | } | |
480 | ||
481 | static void i915_audio_component_put_power(struct device *dev) | |
482 | { | |
483 | intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO); | |
484 | } | |
485 | ||
632f3ab9 LH |
486 | static void i915_audio_component_codec_wake_override(struct device *dev, |
487 | bool enable) | |
488 | { | |
489 | struct drm_i915_private *dev_priv = dev_to_i915(dev); | |
490 | u32 tmp; | |
491 | ||
492 | if (!IS_SKYLAKE(dev_priv)) | |
493 | return; | |
494 | ||
495 | /* | |
496 | * Enable/disable generating the codec wake signal, overriding the | |
497 | * internal logic to generate the codec wake to controller. | |
498 | */ | |
499 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
500 | tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; | |
501 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
502 | usleep_range(1000, 1500); | |
503 | ||
504 | if (enable) { | |
505 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
506 | tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; | |
507 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
508 | usleep_range(1000, 1500); | |
509 | } | |
510 | } | |
511 | ||
58fddc28 ID |
512 | /* Get CDCLK in kHz */ |
513 | static int i915_audio_component_get_cdclk_freq(struct device *dev) | |
514 | { | |
515 | struct drm_i915_private *dev_priv = dev_to_i915(dev); | |
516 | int ret; | |
517 | ||
518 | if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) | |
519 | return -ENODEV; | |
520 | ||
521 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); | |
1652d19e VS |
522 | ret = dev_priv->display.get_display_clock_speed(dev_priv->dev); |
523 | ||
58fddc28 ID |
524 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
525 | ||
526 | return ret; | |
527 | } | |
528 | ||
529 | static const struct i915_audio_component_ops i915_audio_component_ops = { | |
530 | .owner = THIS_MODULE, | |
531 | .get_power = i915_audio_component_get_power, | |
532 | .put_power = i915_audio_component_put_power, | |
632f3ab9 | 533 | .codec_wake_override = i915_audio_component_codec_wake_override, |
58fddc28 ID |
534 | .get_cdclk_freq = i915_audio_component_get_cdclk_freq, |
535 | }; | |
536 | ||
537 | static int i915_audio_component_bind(struct device *i915_dev, | |
538 | struct device *hda_dev, void *data) | |
539 | { | |
540 | struct i915_audio_component *acomp = data; | |
51e1d83c | 541 | struct drm_i915_private *dev_priv = dev_to_i915(i915_dev); |
58fddc28 ID |
542 | |
543 | if (WARN_ON(acomp->ops || acomp->dev)) | |
544 | return -EEXIST; | |
545 | ||
546 | acomp->ops = &i915_audio_component_ops; | |
547 | acomp->dev = i915_dev; | |
51e1d83c | 548 | dev_priv->audio_component = acomp; |
58fddc28 ID |
549 | |
550 | return 0; | |
551 | } | |
552 | ||
553 | static void i915_audio_component_unbind(struct device *i915_dev, | |
554 | struct device *hda_dev, void *data) | |
555 | { | |
556 | struct i915_audio_component *acomp = data; | |
51e1d83c | 557 | struct drm_i915_private *dev_priv = dev_to_i915(i915_dev); |
58fddc28 ID |
558 | |
559 | acomp->ops = NULL; | |
560 | acomp->dev = NULL; | |
51e1d83c | 561 | dev_priv->audio_component = NULL; |
58fddc28 ID |
562 | } |
563 | ||
564 | static const struct component_ops i915_audio_component_bind_ops = { | |
565 | .bind = i915_audio_component_bind, | |
566 | .unbind = i915_audio_component_unbind, | |
567 | }; | |
568 | ||
569 | /** | |
570 | * i915_audio_component_init - initialize and register the audio component | |
571 | * @dev_priv: i915 device instance | |
572 | * | |
573 | * This will register with the component framework a child component which | |
574 | * will bind dynamically to the snd_hda_intel driver's corresponding master | |
575 | * component when the latter is registered. During binding the child | |
576 | * initializes an instance of struct i915_audio_component which it receives | |
577 | * from the master. The master can then start to use the interface defined by | |
578 | * this struct. Each side can break the binding at any point by deregistering | |
579 | * its own component after which each side's component unbind callback is | |
580 | * called. | |
581 | * | |
582 | * We ignore any error during registration and continue with reduced | |
583 | * functionality (i.e. without HDMI audio). | |
584 | */ | |
585 | void i915_audio_component_init(struct drm_i915_private *dev_priv) | |
586 | { | |
587 | int ret; | |
588 | ||
589 | ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops); | |
590 | if (ret < 0) { | |
591 | DRM_ERROR("failed to add audio component (%d)\n", ret); | |
592 | /* continue with reduced functionality */ | |
593 | return; | |
594 | } | |
595 | ||
596 | dev_priv->audio_component_registered = true; | |
597 | } | |
598 | ||
599 | /** | |
600 | * i915_audio_component_cleanup - deregister the audio component | |
601 | * @dev_priv: i915 device instance | |
602 | * | |
603 | * Deregisters the audio component, breaking any existing binding to the | |
604 | * corresponding snd_hda_intel driver's master component. | |
605 | */ | |
606 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) | |
607 | { | |
608 | if (!dev_priv->audio_component_registered) | |
609 | return; | |
610 | ||
611 | component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops); | |
612 | dev_priv->audio_component_registered = false; | |
613 | } |