Commit | Line | Data |
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7c10a2b5 JN |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
58fddc28 ID |
25 | #include <linux/component.h> |
26 | #include <drm/i915_component.h> | |
27 | #include "intel_drv.h" | |
7c10a2b5 JN |
28 | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/drm_edid.h> | |
7c10a2b5 JN |
31 | #include "i915_drv.h" |
32 | ||
28855d2a JN |
33 | /** |
34 | * DOC: High Definition Audio over HDMI and Display Port | |
35 | * | |
36 | * The graphics and audio drivers together support High Definition Audio over | |
37 | * HDMI and Display Port. The audio programming sequences are divided into audio | |
38 | * codec and controller enable and disable sequences. The graphics driver | |
39 | * handles the audio codec sequences, while the audio driver handles the audio | |
40 | * controller sequences. | |
41 | * | |
42 | * The disable sequences must be performed before disabling the transcoder or | |
43 | * port. The enable sequences may only be performed after enabling the | |
3e6da4a9 JN |
44 | * transcoder and port, and after completed link training. Therefore the audio |
45 | * enable/disable sequences are part of the modeset sequence. | |
28855d2a JN |
46 | * |
47 | * The codec and controller sequences could be done either parallel or serial, | |
48 | * but generally the ELDV/PD change in the codec sequence indicates to the audio | |
49 | * driver that the controller sequence should start. Indeed, most of the | |
50 | * co-operation between the graphics and audio drivers is handled via audio | |
51 | * related registers. (The notable exception is the power management, not | |
52 | * covered here.) | |
cb422619 LY |
53 | * |
54 | * The struct i915_audio_component is used to interact between the graphics | |
55 | * and audio drivers. The struct i915_audio_component_ops *ops in it is | |
56 | * defined in graphics driver and called in audio driver. The | |
57 | * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver. | |
28855d2a JN |
58 | */ |
59 | ||
87fcb2ad | 60 | static const struct { |
7c10a2b5 JN |
61 | int clock; |
62 | u32 config; | |
63 | } hdmi_audio_clock[] = { | |
606bb5e0 | 64 | { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
7c10a2b5 JN |
65 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
66 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
606bb5e0 | 67 | { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
7c10a2b5 | 68 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
606bb5e0 VS |
69 | { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
70 | { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7c10a2b5 | 71 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
606bb5e0 | 72 | { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
7c10a2b5 JN |
73 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
74 | }; | |
75 | ||
4a21ef7d LY |
76 | /* HDMI N/CTS table */ |
77 | #define TMDS_297M 297000 | |
606bb5e0 | 78 | #define TMDS_296M 296703 |
4a21ef7d LY |
79 | static const struct { |
80 | int sample_rate; | |
81 | int clock; | |
82 | int n; | |
83 | int cts; | |
84 | } aud_ncts[] = { | |
85 | { 44100, TMDS_296M, 4459, 234375 }, | |
86 | { 44100, TMDS_297M, 4704, 247500 }, | |
87 | { 48000, TMDS_296M, 5824, 281250 }, | |
88 | { 48000, TMDS_297M, 5120, 247500 }, | |
89 | { 32000, TMDS_296M, 5824, 421875 }, | |
90 | { 32000, TMDS_297M, 3072, 222750 }, | |
91 | { 88200, TMDS_296M, 8918, 234375 }, | |
92 | { 88200, TMDS_297M, 9408, 247500 }, | |
93 | { 96000, TMDS_296M, 11648, 281250 }, | |
94 | { 96000, TMDS_297M, 10240, 247500 }, | |
95 | { 176400, TMDS_296M, 17836, 234375 }, | |
96 | { 176400, TMDS_297M, 18816, 247500 }, | |
97 | { 192000, TMDS_296M, 23296, 281250 }, | |
98 | { 192000, TMDS_297M, 20480, 247500 }, | |
99 | }; | |
100 | ||
7c10a2b5 | 101 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
5e7234c9 | 102 | static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode) |
7c10a2b5 JN |
103 | { |
104 | int i; | |
105 | ||
106 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
aad941d5 | 107 | if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) |
7c10a2b5 JN |
108 | break; |
109 | } | |
110 | ||
111 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
5e7234c9 | 112 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", |
aad941d5 | 113 | adjusted_mode->crtc_clock); |
7c10a2b5 JN |
114 | i = 1; |
115 | } | |
116 | ||
117 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
118 | hdmi_audio_clock[i].clock, | |
119 | hdmi_audio_clock[i].config); | |
120 | ||
121 | return hdmi_audio_clock[i].config; | |
122 | } | |
123 | ||
4a21ef7d LY |
124 | static int audio_config_get_n(const struct drm_display_mode *mode, int rate) |
125 | { | |
126 | int i; | |
127 | ||
128 | for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) { | |
129 | if ((rate == aud_ncts[i].sample_rate) && | |
130 | (mode->clock == aud_ncts[i].clock)) { | |
131 | return aud_ncts[i].n; | |
132 | } | |
133 | } | |
134 | return 0; | |
135 | } | |
136 | ||
7e8275c2 LY |
137 | static uint32_t audio_config_setup_n_reg(int n, uint32_t val) |
138 | { | |
139 | int n_low, n_up; | |
140 | uint32_t tmp = val; | |
141 | ||
142 | n_low = n & 0xfff; | |
143 | n_up = (n >> 12) & 0xff; | |
144 | tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK); | |
145 | tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) | | |
146 | (n_low << AUD_CONFIG_LOWER_N_SHIFT) | | |
147 | AUD_CONFIG_N_PROG_ENABLE); | |
148 | return tmp; | |
149 | } | |
150 | ||
7c10a2b5 | 151 | static bool intel_eld_uptodate(struct drm_connector *connector, |
f0f59a00 VS |
152 | i915_reg_t reg_eldv, uint32_t bits_eldv, |
153 | i915_reg_t reg_elda, uint32_t bits_elda, | |
154 | i915_reg_t reg_edid) | |
7c10a2b5 | 155 | { |
fac5e23e | 156 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
7c10a2b5 | 157 | uint8_t *eld = connector->eld; |
f9f682ae JN |
158 | uint32_t tmp; |
159 | int i; | |
7c10a2b5 | 160 | |
f9f682ae JN |
161 | tmp = I915_READ(reg_eldv); |
162 | tmp &= bits_eldv; | |
7c10a2b5 | 163 | |
f9f682ae | 164 | if (!tmp) |
7c10a2b5 JN |
165 | return false; |
166 | ||
f9f682ae JN |
167 | tmp = I915_READ(reg_elda); |
168 | tmp &= ~bits_elda; | |
169 | I915_WRITE(reg_elda, tmp); | |
7c10a2b5 | 170 | |
938fd8aa | 171 | for (i = 0; i < drm_eld_size(eld) / 4; i++) |
7c10a2b5 JN |
172 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
173 | return false; | |
174 | ||
175 | return true; | |
176 | } | |
177 | ||
76d8d3e5 JN |
178 | static void g4x_audio_codec_disable(struct intel_encoder *encoder) |
179 | { | |
fac5e23e | 180 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
76d8d3e5 JN |
181 | uint32_t eldv, tmp; |
182 | ||
183 | DRM_DEBUG_KMS("Disable audio codec\n"); | |
184 | ||
185 | tmp = I915_READ(G4X_AUD_VID_DID); | |
186 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
187 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
188 | else | |
189 | eldv = G4X_ELDV_DEVCTG; | |
190 | ||
191 | /* Invalidate ELD */ | |
192 | tmp = I915_READ(G4X_AUD_CNTL_ST); | |
193 | tmp &= ~eldv; | |
194 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
195 | } | |
196 | ||
69bfe1a9 JN |
197 | static void g4x_audio_codec_enable(struct drm_connector *connector, |
198 | struct intel_encoder *encoder, | |
5e7234c9 | 199 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 | 200 | { |
fac5e23e | 201 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
7c10a2b5 JN |
202 | uint8_t *eld = connector->eld; |
203 | uint32_t eldv; | |
f9f682ae JN |
204 | uint32_t tmp; |
205 | int len, i; | |
7c10a2b5 | 206 | |
d5ee08de JN |
207 | DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); |
208 | ||
f9f682ae JN |
209 | tmp = I915_READ(G4X_AUD_VID_DID); |
210 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
7c10a2b5 JN |
211 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
212 | else | |
213 | eldv = G4X_ELDV_DEVCTG; | |
214 | ||
215 | if (intel_eld_uptodate(connector, | |
216 | G4X_AUD_CNTL_ST, eldv, | |
c46f111f | 217 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, |
7c10a2b5 JN |
218 | G4X_HDMIW_HDMIEDID)) |
219 | return; | |
220 | ||
f9f682ae | 221 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
c46f111f | 222 | tmp &= ~(eldv | G4X_ELD_ADDR_MASK); |
f9f682ae JN |
223 | len = (tmp >> 9) & 0x1f; /* ELD buffer size */ |
224 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 | 225 | |
938fd8aa | 226 | len = min(drm_eld_size(eld) / 4, len); |
7c10a2b5 JN |
227 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
228 | for (i = 0; i < len; i++) | |
229 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
230 | ||
f9f682ae JN |
231 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
232 | tmp |= eldv; | |
233 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 JN |
234 | } |
235 | ||
12e87f23 JN |
236 | static void |
237 | hsw_dp_audio_config_update(struct intel_crtc *intel_crtc, enum port port, | |
238 | const struct drm_display_mode *adjusted_mode) | |
239 | { | |
240 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
241 | enum pipe pipe = intel_crtc->pipe; | |
242 | u32 tmp; | |
243 | ||
244 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
245 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
246 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
247 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
248 | tmp |= AUD_CONFIG_N_VALUE_INDEX; | |
249 | ||
250 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
251 | } | |
252 | ||
253 | static void | |
254 | hsw_hdmi_audio_config_update(struct intel_crtc *intel_crtc, enum port port, | |
255 | const struct drm_display_mode *adjusted_mode) | |
6c26291d JN |
256 | { |
257 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
258 | struct i915_audio_component *acomp = dev_priv->audio_component; | |
3af306d9 | 259 | int rate = acomp ? acomp->aud_sample_rate[port] : 0; |
6c26291d | 260 | enum pipe pipe = intel_crtc->pipe; |
3af306d9 | 261 | int n; |
6c26291d JN |
262 | u32 tmp; |
263 | ||
264 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
265 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
266 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
6c26291d | 267 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
12e87f23 JN |
268 | tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); |
269 | ||
270 | if (adjusted_mode->clock == TMDS_296M || | |
271 | adjusted_mode->clock == TMDS_297M) { | |
6c26291d JN |
272 | n = audio_config_get_n(adjusted_mode, rate); |
273 | if (n != 0) | |
274 | tmp = audio_config_setup_n_reg(n, tmp); | |
275 | else | |
276 | DRM_DEBUG_KMS("no suitable N value is found\n"); | |
277 | } | |
278 | ||
279 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
280 | } | |
281 | ||
12e87f23 JN |
282 | static void |
283 | hsw_audio_config_update(struct intel_crtc *intel_crtc, enum port port, | |
284 | const struct drm_display_mode *adjusted_mode) | |
285 | { | |
286 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) | |
287 | hsw_dp_audio_config_update(intel_crtc, port, adjusted_mode); | |
288 | else | |
289 | hsw_hdmi_audio_config_update(intel_crtc, port, adjusted_mode); | |
290 | } | |
291 | ||
69bfe1a9 JN |
292 | static void hsw_audio_codec_disable(struct intel_encoder *encoder) |
293 | { | |
fac5e23e | 294 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5fad84a7 JN |
295 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
296 | enum pipe pipe = intel_crtc->pipe; | |
69bfe1a9 JN |
297 | uint32_t tmp; |
298 | ||
5fad84a7 JN |
299 | DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); |
300 | ||
4a21ef7d LY |
301 | mutex_lock(&dev_priv->av_mutex); |
302 | ||
5fad84a7 JN |
303 | /* Disable timestamps */ |
304 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
305 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
306 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
307 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
308 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
2210ce7f | 309 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5fad84a7 JN |
310 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
311 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
312 | ||
313 | /* Invalidate ELD */ | |
69bfe1a9 | 314 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 315 | tmp &= ~AUDIO_ELD_VALID(pipe); |
eb45fa0b | 316 | tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); |
69bfe1a9 | 317 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
4a21ef7d LY |
318 | |
319 | mutex_unlock(&dev_priv->av_mutex); | |
69bfe1a9 JN |
320 | } |
321 | ||
322 | static void hsw_audio_codec_enable(struct drm_connector *connector, | |
d8dee42a | 323 | struct intel_encoder *intel_encoder, |
5e7234c9 | 324 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 | 325 | { |
fac5e23e | 326 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
d8dee42a | 327 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
5fad84a7 | 328 | enum pipe pipe = intel_crtc->pipe; |
d8dee42a | 329 | enum port port = intel_encoder->port; |
5fad84a7 | 330 | const uint8_t *eld = connector->eld; |
f9f682ae JN |
331 | uint32_t tmp; |
332 | int len, i; | |
7c10a2b5 | 333 | |
5fad84a7 | 334 | DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", |
938fd8aa | 335 | pipe_name(pipe), drm_eld_size(eld)); |
7c10a2b5 | 336 | |
4a21ef7d LY |
337 | mutex_lock(&dev_priv->av_mutex); |
338 | ||
5fad84a7 JN |
339 | /* Enable audio presence detect, invalidate ELD */ |
340 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
82910ac6 JN |
341 | tmp |= AUDIO_OUTPUT_ENABLE(pipe); |
342 | tmp &= ~AUDIO_ELD_VALID(pipe); | |
5fad84a7 | 343 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
7c10a2b5 | 344 | |
5fad84a7 JN |
345 | /* |
346 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
347 | * disabled during the mode set. The proper fix would be to push the | |
348 | * rest of the setup into a vblank work item, queued here, but the | |
349 | * infrastructure is not there yet. | |
350 | */ | |
7c10a2b5 | 351 | |
5fad84a7 JN |
352 | /* Reset ELD write address */ |
353 | tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); | |
c46f111f | 354 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
5fad84a7 | 355 | I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); |
7c10a2b5 | 356 | |
5fad84a7 | 357 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
358 | len = min(drm_eld_size(eld), 84); |
359 | for (i = 0; i < len / 4; i++) | |
5fad84a7 | 360 | I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); |
7c10a2b5 | 361 | |
5fad84a7 | 362 | /* ELD valid */ |
69bfe1a9 | 363 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 364 | tmp |= AUDIO_ELD_VALID(pipe); |
69bfe1a9 | 365 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
5fad84a7 JN |
366 | |
367 | /* Enable timestamps */ | |
6c26291d | 368 | hsw_audio_config_update(intel_crtc, port, adjusted_mode); |
4a21ef7d LY |
369 | |
370 | mutex_unlock(&dev_priv->av_mutex); | |
7c10a2b5 JN |
371 | } |
372 | ||
d8dee42a | 373 | static void ilk_audio_codec_disable(struct intel_encoder *intel_encoder) |
495a5bb8 | 374 | { |
d8dee42a PD |
375 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
376 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
495a5bb8 | 377 | enum pipe pipe = intel_crtc->pipe; |
d8dee42a | 378 | enum port port = intel_encoder->port; |
495a5bb8 | 379 | uint32_t tmp, eldv; |
f0f59a00 | 380 | i915_reg_t aud_config, aud_cntrl_st2; |
495a5bb8 JN |
381 | |
382 | DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", | |
383 | port_name(port), pipe_name(pipe)); | |
384 | ||
d3902c3e JN |
385 | if (WARN_ON(port == PORT_A)) |
386 | return; | |
387 | ||
2d1fe073 | 388 | if (HAS_PCH_IBX(dev_priv)) { |
495a5bb8 JN |
389 | aud_config = IBX_AUD_CFG(pipe); |
390 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
666a4537 | 391 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
495a5bb8 JN |
392 | aud_config = VLV_AUD_CFG(pipe); |
393 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
394 | } else { | |
395 | aud_config = CPT_AUD_CFG(pipe); | |
396 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
397 | } | |
398 | ||
399 | /* Disable timestamps */ | |
400 | tmp = I915_READ(aud_config); | |
401 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
402 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
403 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
404 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
2210ce7f | 405 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
495a5bb8 JN |
406 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
407 | I915_WRITE(aud_config, tmp); | |
408 | ||
d3902c3e | 409 | eldv = IBX_ELD_VALID(port); |
495a5bb8 JN |
410 | |
411 | /* Invalidate ELD */ | |
412 | tmp = I915_READ(aud_cntrl_st2); | |
413 | tmp &= ~eldv; | |
414 | I915_WRITE(aud_cntrl_st2, tmp); | |
415 | } | |
416 | ||
69bfe1a9 | 417 | static void ilk_audio_codec_enable(struct drm_connector *connector, |
d8dee42a | 418 | struct intel_encoder *intel_encoder, |
5e7234c9 | 419 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 | 420 | { |
fac5e23e | 421 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
d8dee42a | 422 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
c6bde93b | 423 | enum pipe pipe = intel_crtc->pipe; |
d8dee42a | 424 | enum port port = intel_encoder->port; |
7c10a2b5 | 425 | uint8_t *eld = connector->eld; |
38cb2eca | 426 | uint32_t tmp, eldv; |
f9f682ae | 427 | int len, i; |
f0f59a00 | 428 | i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; |
c6bde93b JN |
429 | |
430 | DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", | |
938fd8aa | 431 | port_name(port), pipe_name(pipe), drm_eld_size(eld)); |
c6bde93b | 432 | |
d3902c3e JN |
433 | if (WARN_ON(port == PORT_A)) |
434 | return; | |
435 | ||
c6bde93b JN |
436 | /* |
437 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
438 | * disabled during the mode set. The proper fix would be to push the | |
439 | * rest of the setup into a vblank work item, queued here, but the | |
440 | * infrastructure is not there yet. | |
441 | */ | |
7c10a2b5 JN |
442 | |
443 | if (HAS_PCH_IBX(connector->dev)) { | |
444 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); | |
445 | aud_config = IBX_AUD_CFG(pipe); | |
446 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
447 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
666a4537 WB |
448 | } else if (IS_VALLEYVIEW(connector->dev) || |
449 | IS_CHERRYVIEW(connector->dev)) { | |
7c10a2b5 JN |
450 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
451 | aud_config = VLV_AUD_CFG(pipe); | |
452 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
453 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
454 | } else { | |
455 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); | |
456 | aud_config = CPT_AUD_CFG(pipe); | |
457 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
458 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
459 | } | |
460 | ||
d3902c3e | 461 | eldv = IBX_ELD_VALID(port); |
7c10a2b5 | 462 | |
c6bde93b | 463 | /* Invalidate ELD */ |
f9f682ae JN |
464 | tmp = I915_READ(aud_cntrl_st2); |
465 | tmp &= ~eldv; | |
466 | I915_WRITE(aud_cntrl_st2, tmp); | |
7c10a2b5 | 467 | |
c6bde93b | 468 | /* Reset ELD write address */ |
f9f682ae | 469 | tmp = I915_READ(aud_cntl_st); |
c46f111f | 470 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
f9f682ae | 471 | I915_WRITE(aud_cntl_st, tmp); |
7c10a2b5 | 472 | |
c6bde93b | 473 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
474 | len = min(drm_eld_size(eld), 84); |
475 | for (i = 0; i < len / 4; i++) | |
7c10a2b5 JN |
476 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
477 | ||
c6bde93b | 478 | /* ELD valid */ |
f9f682ae JN |
479 | tmp = I915_READ(aud_cntrl_st2); |
480 | tmp |= eldv; | |
481 | I915_WRITE(aud_cntrl_st2, tmp); | |
c6bde93b JN |
482 | |
483 | /* Enable timestamps */ | |
484 | tmp = I915_READ(aud_config); | |
485 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
486 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
487 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
2210ce7f | 488 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
c6bde93b JN |
489 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
490 | else | |
5e7234c9 | 491 | tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); |
c6bde93b | 492 | I915_WRITE(aud_config, tmp); |
7c10a2b5 JN |
493 | } |
494 | ||
69bfe1a9 JN |
495 | /** |
496 | * intel_audio_codec_enable - Enable the audio codec for HD audio | |
497 | * @intel_encoder: encoder on which to enable audio | |
498 | * | |
499 | * The enable sequences may only be performed after enabling the transcoder and | |
500 | * port, and after completed link training. | |
501 | */ | |
502 | void intel_audio_codec_enable(struct intel_encoder *intel_encoder) | |
7c10a2b5 | 503 | { |
33d1e7c6 JN |
504 | struct drm_encoder *encoder = &intel_encoder->base; |
505 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); | |
7c5f93b0 | 506 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
7c10a2b5 | 507 | struct drm_connector *connector; |
d8dee42a | 508 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
51e1d83c | 509 | struct i915_audio_component *acomp = dev_priv->audio_component; |
d8dee42a | 510 | enum port port = intel_encoder->port; |
f9318941 | 511 | enum pipe pipe = crtc->pipe; |
7c10a2b5 | 512 | |
9e5a3b52 | 513 | connector = drm_select_eld(encoder); |
7c10a2b5 JN |
514 | if (!connector) |
515 | return; | |
516 | ||
517 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
518 | connector->base.id, | |
519 | connector->name, | |
520 | connector->encoder->base.id, | |
521 | connector->encoder->name); | |
522 | ||
6189b036 JN |
523 | /* ELD Conn_Type */ |
524 | connector->eld[5] &= ~(3 << 2); | |
2210ce7f | 525 | if (intel_crtc_has_dp_encoder(crtc->config)) |
6189b036 JN |
526 | connector->eld[5] |= (1 << 2); |
527 | ||
124abe07 | 528 | connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; |
7c10a2b5 | 529 | |
69bfe1a9 | 530 | if (dev_priv->display.audio_codec_enable) |
124abe07 VS |
531 | dev_priv->display.audio_codec_enable(connector, intel_encoder, |
532 | adjusted_mode); | |
51e1d83c | 533 | |
cae666ce | 534 | mutex_lock(&dev_priv->av_mutex); |
f1a3acea | 535 | intel_encoder->audio_connector = connector; |
f9318941 | 536 | |
9dfbffcf | 537 | /* referred in audio callbacks */ |
f9318941 | 538 | dev_priv->av_enc_map[pipe] = intel_encoder; |
cae666ce TI |
539 | mutex_unlock(&dev_priv->av_mutex); |
540 | ||
f9318941 PD |
541 | /* audio drivers expect pipe = -1 to indicate Non-MST cases */ |
542 | if (intel_encoder->type != INTEL_OUTPUT_DP_MST) | |
543 | pipe = -1; | |
544 | ||
51e1d83c | 545 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) |
f9318941 PD |
546 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, |
547 | (int) port, (int) pipe); | |
69bfe1a9 JN |
548 | } |
549 | ||
550 | /** | |
551 | * intel_audio_codec_disable - Disable the audio codec for HD audio | |
95d0be61 | 552 | * @intel_encoder: encoder on which to disable audio |
69bfe1a9 JN |
553 | * |
554 | * The disable sequences must be performed before disabling the transcoder or | |
555 | * port. | |
556 | */ | |
51e1d83c | 557 | void intel_audio_codec_disable(struct intel_encoder *intel_encoder) |
69bfe1a9 | 558 | { |
51e1d83c | 559 | struct drm_encoder *encoder = &intel_encoder->base; |
d8dee42a | 560 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
51e1d83c | 561 | struct i915_audio_component *acomp = dev_priv->audio_component; |
d8dee42a | 562 | enum port port = intel_encoder->port; |
f9318941 PD |
563 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
564 | enum pipe pipe = crtc->pipe; | |
69bfe1a9 JN |
565 | |
566 | if (dev_priv->display.audio_codec_disable) | |
51e1d83c DH |
567 | dev_priv->display.audio_codec_disable(intel_encoder); |
568 | ||
cae666ce | 569 | mutex_lock(&dev_priv->av_mutex); |
f1a3acea | 570 | intel_encoder->audio_connector = NULL; |
f9318941 | 571 | dev_priv->av_enc_map[pipe] = NULL; |
cae666ce TI |
572 | mutex_unlock(&dev_priv->av_mutex); |
573 | ||
f9318941 PD |
574 | /* audio drivers expect pipe = -1 to indicate Non-MST cases */ |
575 | if (intel_encoder->type != INTEL_OUTPUT_DP_MST) | |
576 | pipe = -1; | |
577 | ||
51e1d83c | 578 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) |
f9318941 PD |
579 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, |
580 | (int) port, (int) pipe); | |
7c10a2b5 JN |
581 | } |
582 | ||
583 | /** | |
88212941 ID |
584 | * intel_init_audio_hooks - Set up chip specific audio hooks |
585 | * @dev_priv: device private | |
7c10a2b5 | 586 | */ |
88212941 | 587 | void intel_init_audio_hooks(struct drm_i915_private *dev_priv) |
7c10a2b5 | 588 | { |
88212941 | 589 | if (IS_G4X(dev_priv)) { |
69bfe1a9 | 590 | dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; |
76d8d3e5 | 591 | dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; |
88212941 | 592 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
69bfe1a9 | 593 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
495a5bb8 | 594 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
88212941 | 595 | } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) { |
69bfe1a9 JN |
596 | dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; |
597 | dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; | |
88212941 | 598 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
69bfe1a9 | 599 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
495a5bb8 | 600 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
69bfe1a9 | 601 | } |
7c10a2b5 | 602 | } |
58fddc28 | 603 | |
c49d13ee | 604 | static void i915_audio_component_get_power(struct device *kdev) |
58fddc28 | 605 | { |
c49d13ee | 606 | intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO); |
58fddc28 ID |
607 | } |
608 | ||
c49d13ee | 609 | static void i915_audio_component_put_power(struct device *kdev) |
58fddc28 | 610 | { |
c49d13ee | 611 | intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO); |
58fddc28 ID |
612 | } |
613 | ||
c49d13ee | 614 | static void i915_audio_component_codec_wake_override(struct device *kdev, |
632f3ab9 LH |
615 | bool enable) |
616 | { | |
c49d13ee | 617 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
632f3ab9 LH |
618 | u32 tmp; |
619 | ||
ef11bdb3 | 620 | if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) |
632f3ab9 LH |
621 | return; |
622 | ||
c49d13ee | 623 | i915_audio_component_get_power(kdev); |
d838a110 | 624 | |
632f3ab9 LH |
625 | /* |
626 | * Enable/disable generating the codec wake signal, overriding the | |
627 | * internal logic to generate the codec wake to controller. | |
628 | */ | |
629 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
630 | tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; | |
631 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
632 | usleep_range(1000, 1500); | |
633 | ||
634 | if (enable) { | |
635 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
636 | tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; | |
637 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
638 | usleep_range(1000, 1500); | |
639 | } | |
d838a110 | 640 | |
c49d13ee | 641 | i915_audio_component_put_power(kdev); |
632f3ab9 LH |
642 | } |
643 | ||
58fddc28 | 644 | /* Get CDCLK in kHz */ |
c49d13ee | 645 | static int i915_audio_component_get_cdclk_freq(struct device *kdev) |
58fddc28 | 646 | { |
c49d13ee | 647 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
58fddc28 ID |
648 | |
649 | if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) | |
650 | return -ENODEV; | |
651 | ||
1033f92e | 652 | return dev_priv->cdclk_freq; |
58fddc28 ID |
653 | } |
654 | ||
f9318941 PD |
655 | static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, |
656 | int port, int pipe) | |
657 | { | |
658 | ||
659 | if (WARN_ON(pipe >= I915_MAX_PIPES)) | |
660 | return NULL; | |
661 | ||
662 | /* MST */ | |
663 | if (pipe >= 0) | |
664 | return dev_priv->av_enc_map[pipe]; | |
665 | ||
666 | /* Non-MST */ | |
667 | for_each_pipe(dev_priv, pipe) { | |
668 | struct intel_encoder *encoder; | |
669 | ||
670 | encoder = dev_priv->av_enc_map[pipe]; | |
671 | if (encoder == NULL) | |
672 | continue; | |
673 | ||
674 | if (port == encoder->port) | |
675 | return encoder; | |
676 | } | |
677 | ||
678 | return NULL; | |
679 | } | |
680 | ||
681 | static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, | |
682 | int pipe, int rate) | |
4a21ef7d | 683 | { |
c49d13ee | 684 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
4a21ef7d | 685 | struct intel_encoder *intel_encoder; |
4a21ef7d | 686 | struct intel_crtc *crtc; |
8f1ec181 | 687 | struct drm_display_mode *adjusted_mode; |
7e8275c2 | 688 | struct i915_audio_component *acomp = dev_priv->audio_component; |
0bdf5a05 | 689 | int err = 0; |
4a21ef7d | 690 | |
4bd2d6f6 | 691 | if (!HAS_DDI(dev_priv)) |
4a21ef7d LY |
692 | return 0; |
693 | ||
c49d13ee | 694 | i915_audio_component_get_power(kdev); |
4a21ef7d | 695 | mutex_lock(&dev_priv->av_mutex); |
f9318941 | 696 | |
4a21ef7d | 697 | /* 1. get the pipe */ |
f9318941 | 698 | intel_encoder = get_saved_enc(dev_priv, port, pipe); |
0bdf5a05 TI |
699 | if (!intel_encoder || !intel_encoder->base.crtc || |
700 | intel_encoder->type != INTEL_OUTPUT_HDMI) { | |
f9318941 | 701 | DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); |
0bdf5a05 TI |
702 | err = -ENODEV; |
703 | goto unlock; | |
4a21ef7d | 704 | } |
f9318941 PD |
705 | |
706 | /* pipe passed from the audio driver will be -1 for Non-MST case */ | |
0bdf5a05 TI |
707 | crtc = to_intel_crtc(intel_encoder->base.crtc); |
708 | pipe = crtc->pipe; | |
0bdf5a05 | 709 | |
8f1ec181 | 710 | adjusted_mode = &crtc->config->base.adjusted_mode; |
4a21ef7d | 711 | |
7e8275c2 LY |
712 | /* port must be valid now, otherwise the pipe will be invalid */ |
713 | acomp->aud_sample_rate[port] = rate; | |
714 | ||
8f1ec181 | 715 | hsw_audio_config_update(crtc, port, adjusted_mode); |
4a21ef7d | 716 | |
0bdf5a05 | 717 | unlock: |
4a21ef7d | 718 | mutex_unlock(&dev_priv->av_mutex); |
c49d13ee | 719 | i915_audio_component_put_power(kdev); |
0bdf5a05 | 720 | return err; |
4a21ef7d LY |
721 | } |
722 | ||
c49d13ee | 723 | static int i915_audio_component_get_eld(struct device *kdev, int port, |
f9318941 | 724 | int pipe, bool *enabled, |
cae666ce TI |
725 | unsigned char *buf, int max_bytes) |
726 | { | |
c49d13ee | 727 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
cae666ce | 728 | struct intel_encoder *intel_encoder; |
cae666ce TI |
729 | const u8 *eld; |
730 | int ret = -EINVAL; | |
731 | ||
732 | mutex_lock(&dev_priv->av_mutex); | |
f9318941 PD |
733 | |
734 | intel_encoder = get_saved_enc(dev_priv, port, pipe); | |
735 | if (!intel_encoder) { | |
736 | DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); | |
737 | mutex_unlock(&dev_priv->av_mutex); | |
738 | return ret; | |
739 | } | |
740 | ||
741 | ret = 0; | |
742 | *enabled = intel_encoder->audio_connector != NULL; | |
743 | if (*enabled) { | |
744 | eld = intel_encoder->audio_connector->eld; | |
745 | ret = drm_eld_size(eld); | |
746 | memcpy(buf, eld, min(max_bytes, ret)); | |
cae666ce TI |
747 | } |
748 | ||
749 | mutex_unlock(&dev_priv->av_mutex); | |
750 | return ret; | |
4a21ef7d LY |
751 | } |
752 | ||
58fddc28 ID |
753 | static const struct i915_audio_component_ops i915_audio_component_ops = { |
754 | .owner = THIS_MODULE, | |
755 | .get_power = i915_audio_component_get_power, | |
756 | .put_power = i915_audio_component_put_power, | |
632f3ab9 | 757 | .codec_wake_override = i915_audio_component_codec_wake_override, |
58fddc28 | 758 | .get_cdclk_freq = i915_audio_component_get_cdclk_freq, |
4a21ef7d | 759 | .sync_audio_rate = i915_audio_component_sync_audio_rate, |
cae666ce | 760 | .get_eld = i915_audio_component_get_eld, |
58fddc28 ID |
761 | }; |
762 | ||
c49d13ee DW |
763 | static int i915_audio_component_bind(struct device *i915_kdev, |
764 | struct device *hda_kdev, void *data) | |
58fddc28 ID |
765 | { |
766 | struct i915_audio_component *acomp = data; | |
c49d13ee | 767 | struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); |
7e8275c2 | 768 | int i; |
58fddc28 ID |
769 | |
770 | if (WARN_ON(acomp->ops || acomp->dev)) | |
771 | return -EEXIST; | |
772 | ||
91c8a326 | 773 | drm_modeset_lock_all(&dev_priv->drm); |
58fddc28 | 774 | acomp->ops = &i915_audio_component_ops; |
c49d13ee | 775 | acomp->dev = i915_kdev; |
7e8275c2 LY |
776 | BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); |
777 | for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) | |
778 | acomp->aud_sample_rate[i] = 0; | |
51e1d83c | 779 | dev_priv->audio_component = acomp; |
91c8a326 | 780 | drm_modeset_unlock_all(&dev_priv->drm); |
58fddc28 ID |
781 | |
782 | return 0; | |
783 | } | |
784 | ||
c49d13ee DW |
785 | static void i915_audio_component_unbind(struct device *i915_kdev, |
786 | struct device *hda_kdev, void *data) | |
58fddc28 ID |
787 | { |
788 | struct i915_audio_component *acomp = data; | |
c49d13ee | 789 | struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); |
58fddc28 | 790 | |
91c8a326 | 791 | drm_modeset_lock_all(&dev_priv->drm); |
58fddc28 ID |
792 | acomp->ops = NULL; |
793 | acomp->dev = NULL; | |
51e1d83c | 794 | dev_priv->audio_component = NULL; |
91c8a326 | 795 | drm_modeset_unlock_all(&dev_priv->drm); |
58fddc28 ID |
796 | } |
797 | ||
798 | static const struct component_ops i915_audio_component_bind_ops = { | |
799 | .bind = i915_audio_component_bind, | |
800 | .unbind = i915_audio_component_unbind, | |
801 | }; | |
802 | ||
803 | /** | |
804 | * i915_audio_component_init - initialize and register the audio component | |
805 | * @dev_priv: i915 device instance | |
806 | * | |
807 | * This will register with the component framework a child component which | |
808 | * will bind dynamically to the snd_hda_intel driver's corresponding master | |
809 | * component when the latter is registered. During binding the child | |
810 | * initializes an instance of struct i915_audio_component which it receives | |
811 | * from the master. The master can then start to use the interface defined by | |
812 | * this struct. Each side can break the binding at any point by deregistering | |
813 | * its own component after which each side's component unbind callback is | |
814 | * called. | |
815 | * | |
816 | * We ignore any error during registration and continue with reduced | |
817 | * functionality (i.e. without HDMI audio). | |
818 | */ | |
819 | void i915_audio_component_init(struct drm_i915_private *dev_priv) | |
820 | { | |
821 | int ret; | |
822 | ||
91c8a326 | 823 | ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops); |
58fddc28 ID |
824 | if (ret < 0) { |
825 | DRM_ERROR("failed to add audio component (%d)\n", ret); | |
826 | /* continue with reduced functionality */ | |
827 | return; | |
828 | } | |
829 | ||
830 | dev_priv->audio_component_registered = true; | |
831 | } | |
832 | ||
833 | /** | |
834 | * i915_audio_component_cleanup - deregister the audio component | |
835 | * @dev_priv: i915 device instance | |
836 | * | |
837 | * Deregisters the audio component, breaking any existing binding to the | |
838 | * corresponding snd_hda_intel driver's master component. | |
839 | */ | |
840 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) | |
841 | { | |
842 | if (!dev_priv->audio_component_registered) | |
843 | return; | |
844 | ||
91c8a326 | 845 | component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); |
58fddc28 ID |
846 | dev_priv->audio_component_registered = false; |
847 | } |