Commit | Line | Data |
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7c10a2b5 JN |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
58fddc28 ID |
25 | #include <linux/component.h> |
26 | #include <drm/i915_component.h> | |
27 | #include "intel_drv.h" | |
7c10a2b5 JN |
28 | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/drm_edid.h> | |
7c10a2b5 JN |
31 | #include "i915_drv.h" |
32 | ||
28855d2a JN |
33 | /** |
34 | * DOC: High Definition Audio over HDMI and Display Port | |
35 | * | |
36 | * The graphics and audio drivers together support High Definition Audio over | |
37 | * HDMI and Display Port. The audio programming sequences are divided into audio | |
38 | * codec and controller enable and disable sequences. The graphics driver | |
39 | * handles the audio codec sequences, while the audio driver handles the audio | |
40 | * controller sequences. | |
41 | * | |
42 | * The disable sequences must be performed before disabling the transcoder or | |
43 | * port. The enable sequences may only be performed after enabling the | |
3e6da4a9 JN |
44 | * transcoder and port, and after completed link training. Therefore the audio |
45 | * enable/disable sequences are part of the modeset sequence. | |
28855d2a JN |
46 | * |
47 | * The codec and controller sequences could be done either parallel or serial, | |
48 | * but generally the ELDV/PD change in the codec sequence indicates to the audio | |
49 | * driver that the controller sequence should start. Indeed, most of the | |
50 | * co-operation between the graphics and audio drivers is handled via audio | |
51 | * related registers. (The notable exception is the power management, not | |
52 | * covered here.) | |
cb422619 LY |
53 | * |
54 | * The struct i915_audio_component is used to interact between the graphics | |
55 | * and audio drivers. The struct i915_audio_component_ops *ops in it is | |
56 | * defined in graphics driver and called in audio driver. The | |
57 | * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver. | |
28855d2a JN |
58 | */ |
59 | ||
87fcb2ad | 60 | static const struct { |
7c10a2b5 JN |
61 | int clock; |
62 | u32 config; | |
63 | } hdmi_audio_clock[] = { | |
606bb5e0 | 64 | { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
7c10a2b5 JN |
65 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
66 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
606bb5e0 | 67 | { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
7c10a2b5 | 68 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
606bb5e0 VS |
69 | { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
70 | { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7c10a2b5 | 71 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
606bb5e0 | 72 | { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
7c10a2b5 JN |
73 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
74 | }; | |
75 | ||
4a21ef7d LY |
76 | /* HDMI N/CTS table */ |
77 | #define TMDS_297M 297000 | |
606bb5e0 | 78 | #define TMDS_296M 296703 |
4a21ef7d LY |
79 | static const struct { |
80 | int sample_rate; | |
81 | int clock; | |
82 | int n; | |
83 | int cts; | |
84 | } aud_ncts[] = { | |
85 | { 44100, TMDS_296M, 4459, 234375 }, | |
86 | { 44100, TMDS_297M, 4704, 247500 }, | |
87 | { 48000, TMDS_296M, 5824, 281250 }, | |
88 | { 48000, TMDS_297M, 5120, 247500 }, | |
89 | { 32000, TMDS_296M, 5824, 421875 }, | |
90 | { 32000, TMDS_297M, 3072, 222750 }, | |
91 | { 88200, TMDS_296M, 8918, 234375 }, | |
92 | { 88200, TMDS_297M, 9408, 247500 }, | |
93 | { 96000, TMDS_296M, 11648, 281250 }, | |
94 | { 96000, TMDS_297M, 10240, 247500 }, | |
95 | { 176400, TMDS_296M, 17836, 234375 }, | |
96 | { 176400, TMDS_297M, 18816, 247500 }, | |
97 | { 192000, TMDS_296M, 23296, 281250 }, | |
98 | { 192000, TMDS_297M, 20480, 247500 }, | |
99 | }; | |
100 | ||
7c10a2b5 | 101 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
5e7234c9 | 102 | static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode) |
7c10a2b5 JN |
103 | { |
104 | int i; | |
105 | ||
106 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
aad941d5 | 107 | if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) |
7c10a2b5 JN |
108 | break; |
109 | } | |
110 | ||
111 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
5e7234c9 | 112 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", |
aad941d5 | 113 | adjusted_mode->crtc_clock); |
7c10a2b5 JN |
114 | i = 1; |
115 | } | |
116 | ||
117 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
118 | hdmi_audio_clock[i].clock, | |
119 | hdmi_audio_clock[i].config); | |
120 | ||
121 | return hdmi_audio_clock[i].config; | |
122 | } | |
123 | ||
a7c4efbf LY |
124 | static int audio_config_get_n(const struct drm_display_mode *adjusted_mode, |
125 | int rate) | |
4a21ef7d LY |
126 | { |
127 | int i; | |
128 | ||
129 | for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) { | |
130 | if ((rate == aud_ncts[i].sample_rate) && | |
a7c4efbf | 131 | (adjusted_mode->crtc_clock == aud_ncts[i].clock)) { |
4a21ef7d LY |
132 | return aud_ncts[i].n; |
133 | } | |
134 | } | |
135 | return 0; | |
136 | } | |
137 | ||
7c10a2b5 | 138 | static bool intel_eld_uptodate(struct drm_connector *connector, |
f0f59a00 VS |
139 | i915_reg_t reg_eldv, uint32_t bits_eldv, |
140 | i915_reg_t reg_elda, uint32_t bits_elda, | |
141 | i915_reg_t reg_edid) | |
7c10a2b5 | 142 | { |
fac5e23e | 143 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
7c10a2b5 | 144 | uint8_t *eld = connector->eld; |
f9f682ae JN |
145 | uint32_t tmp; |
146 | int i; | |
7c10a2b5 | 147 | |
f9f682ae JN |
148 | tmp = I915_READ(reg_eldv); |
149 | tmp &= bits_eldv; | |
7c10a2b5 | 150 | |
f9f682ae | 151 | if (!tmp) |
7c10a2b5 JN |
152 | return false; |
153 | ||
f9f682ae JN |
154 | tmp = I915_READ(reg_elda); |
155 | tmp &= ~bits_elda; | |
156 | I915_WRITE(reg_elda, tmp); | |
7c10a2b5 | 157 | |
938fd8aa | 158 | for (i = 0; i < drm_eld_size(eld) / 4; i++) |
7c10a2b5 JN |
159 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
160 | return false; | |
161 | ||
162 | return true; | |
163 | } | |
164 | ||
76d8d3e5 JN |
165 | static void g4x_audio_codec_disable(struct intel_encoder *encoder) |
166 | { | |
fac5e23e | 167 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
76d8d3e5 JN |
168 | uint32_t eldv, tmp; |
169 | ||
170 | DRM_DEBUG_KMS("Disable audio codec\n"); | |
171 | ||
172 | tmp = I915_READ(G4X_AUD_VID_DID); | |
173 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
174 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
175 | else | |
176 | eldv = G4X_ELDV_DEVCTG; | |
177 | ||
178 | /* Invalidate ELD */ | |
179 | tmp = I915_READ(G4X_AUD_CNTL_ST); | |
180 | tmp &= ~eldv; | |
181 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
182 | } | |
183 | ||
69bfe1a9 JN |
184 | static void g4x_audio_codec_enable(struct drm_connector *connector, |
185 | struct intel_encoder *encoder, | |
5e7234c9 | 186 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 | 187 | { |
fac5e23e | 188 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
7c10a2b5 JN |
189 | uint8_t *eld = connector->eld; |
190 | uint32_t eldv; | |
f9f682ae JN |
191 | uint32_t tmp; |
192 | int len, i; | |
7c10a2b5 | 193 | |
d5ee08de JN |
194 | DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); |
195 | ||
f9f682ae JN |
196 | tmp = I915_READ(G4X_AUD_VID_DID); |
197 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
7c10a2b5 JN |
198 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
199 | else | |
200 | eldv = G4X_ELDV_DEVCTG; | |
201 | ||
202 | if (intel_eld_uptodate(connector, | |
203 | G4X_AUD_CNTL_ST, eldv, | |
c46f111f | 204 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, |
7c10a2b5 JN |
205 | G4X_HDMIW_HDMIEDID)) |
206 | return; | |
207 | ||
f9f682ae | 208 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
c46f111f | 209 | tmp &= ~(eldv | G4X_ELD_ADDR_MASK); |
f9f682ae JN |
210 | len = (tmp >> 9) & 0x1f; /* ELD buffer size */ |
211 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 | 212 | |
938fd8aa | 213 | len = min(drm_eld_size(eld) / 4, len); |
7c10a2b5 JN |
214 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
215 | for (i = 0; i < len; i++) | |
216 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
217 | ||
f9f682ae JN |
218 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
219 | tmp |= eldv; | |
220 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 JN |
221 | } |
222 | ||
12e87f23 JN |
223 | static void |
224 | hsw_dp_audio_config_update(struct intel_crtc *intel_crtc, enum port port, | |
225 | const struct drm_display_mode *adjusted_mode) | |
226 | { | |
227 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
228 | enum pipe pipe = intel_crtc->pipe; | |
229 | u32 tmp; | |
230 | ||
231 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
232 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
233 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
234 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
235 | tmp |= AUD_CONFIG_N_VALUE_INDEX; | |
236 | ||
237 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
238 | } | |
239 | ||
240 | static void | |
241 | hsw_hdmi_audio_config_update(struct intel_crtc *intel_crtc, enum port port, | |
242 | const struct drm_display_mode *adjusted_mode) | |
6c26291d JN |
243 | { |
244 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
245 | struct i915_audio_component *acomp = dev_priv->audio_component; | |
3af306d9 | 246 | int rate = acomp ? acomp->aud_sample_rate[port] : 0; |
6c26291d | 247 | enum pipe pipe = intel_crtc->pipe; |
3af306d9 | 248 | int n; |
6c26291d JN |
249 | u32 tmp; |
250 | ||
251 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
252 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
253 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
6c26291d | 254 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
12e87f23 JN |
255 | tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); |
256 | ||
a7c4efbf LY |
257 | if (adjusted_mode->crtc_clock == TMDS_296M || |
258 | adjusted_mode->crtc_clock == TMDS_297M) { | |
6c26291d | 259 | n = audio_config_get_n(adjusted_mode, rate); |
2561389a JN |
260 | if (n != 0) { |
261 | tmp &= ~AUD_CONFIG_N_MASK; | |
262 | tmp |= AUD_CONFIG_N(n); | |
263 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
264 | } else { | |
6c26291d | 265 | DRM_DEBUG_KMS("no suitable N value is found\n"); |
2561389a | 266 | } |
6c26291d JN |
267 | } |
268 | ||
269 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
270 | } | |
271 | ||
12e87f23 JN |
272 | static void |
273 | hsw_audio_config_update(struct intel_crtc *intel_crtc, enum port port, | |
274 | const struct drm_display_mode *adjusted_mode) | |
275 | { | |
276 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) | |
277 | hsw_dp_audio_config_update(intel_crtc, port, adjusted_mode); | |
278 | else | |
279 | hsw_hdmi_audio_config_update(intel_crtc, port, adjusted_mode); | |
280 | } | |
281 | ||
69bfe1a9 JN |
282 | static void hsw_audio_codec_disable(struct intel_encoder *encoder) |
283 | { | |
fac5e23e | 284 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5fad84a7 JN |
285 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
286 | enum pipe pipe = intel_crtc->pipe; | |
69bfe1a9 JN |
287 | uint32_t tmp; |
288 | ||
5fad84a7 JN |
289 | DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); |
290 | ||
4a21ef7d LY |
291 | mutex_lock(&dev_priv->av_mutex); |
292 | ||
5fad84a7 JN |
293 | /* Disable timestamps */ |
294 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
295 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
296 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
297 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
298 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
2210ce7f | 299 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5fad84a7 JN |
300 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
301 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
302 | ||
303 | /* Invalidate ELD */ | |
69bfe1a9 | 304 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 305 | tmp &= ~AUDIO_ELD_VALID(pipe); |
eb45fa0b | 306 | tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); |
69bfe1a9 | 307 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
4a21ef7d LY |
308 | |
309 | mutex_unlock(&dev_priv->av_mutex); | |
69bfe1a9 JN |
310 | } |
311 | ||
312 | static void hsw_audio_codec_enable(struct drm_connector *connector, | |
d8dee42a | 313 | struct intel_encoder *intel_encoder, |
5e7234c9 | 314 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 | 315 | { |
fac5e23e | 316 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
d8dee42a | 317 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
5fad84a7 | 318 | enum pipe pipe = intel_crtc->pipe; |
d8dee42a | 319 | enum port port = intel_encoder->port; |
5fad84a7 | 320 | const uint8_t *eld = connector->eld; |
f9f682ae JN |
321 | uint32_t tmp; |
322 | int len, i; | |
7c10a2b5 | 323 | |
5fad84a7 | 324 | DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", |
938fd8aa | 325 | pipe_name(pipe), drm_eld_size(eld)); |
7c10a2b5 | 326 | |
4a21ef7d LY |
327 | mutex_lock(&dev_priv->av_mutex); |
328 | ||
5fad84a7 JN |
329 | /* Enable audio presence detect, invalidate ELD */ |
330 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
82910ac6 JN |
331 | tmp |= AUDIO_OUTPUT_ENABLE(pipe); |
332 | tmp &= ~AUDIO_ELD_VALID(pipe); | |
5fad84a7 | 333 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
7c10a2b5 | 334 | |
5fad84a7 JN |
335 | /* |
336 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
337 | * disabled during the mode set. The proper fix would be to push the | |
338 | * rest of the setup into a vblank work item, queued here, but the | |
339 | * infrastructure is not there yet. | |
340 | */ | |
7c10a2b5 | 341 | |
5fad84a7 JN |
342 | /* Reset ELD write address */ |
343 | tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); | |
c46f111f | 344 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
5fad84a7 | 345 | I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); |
7c10a2b5 | 346 | |
5fad84a7 | 347 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
348 | len = min(drm_eld_size(eld), 84); |
349 | for (i = 0; i < len / 4; i++) | |
5fad84a7 | 350 | I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); |
7c10a2b5 | 351 | |
5fad84a7 | 352 | /* ELD valid */ |
69bfe1a9 | 353 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 354 | tmp |= AUDIO_ELD_VALID(pipe); |
69bfe1a9 | 355 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
5fad84a7 JN |
356 | |
357 | /* Enable timestamps */ | |
6c26291d | 358 | hsw_audio_config_update(intel_crtc, port, adjusted_mode); |
4a21ef7d LY |
359 | |
360 | mutex_unlock(&dev_priv->av_mutex); | |
7c10a2b5 JN |
361 | } |
362 | ||
d8dee42a | 363 | static void ilk_audio_codec_disable(struct intel_encoder *intel_encoder) |
495a5bb8 | 364 | { |
d8dee42a PD |
365 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
366 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
495a5bb8 | 367 | enum pipe pipe = intel_crtc->pipe; |
d8dee42a | 368 | enum port port = intel_encoder->port; |
495a5bb8 | 369 | uint32_t tmp, eldv; |
f0f59a00 | 370 | i915_reg_t aud_config, aud_cntrl_st2; |
495a5bb8 JN |
371 | |
372 | DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", | |
373 | port_name(port), pipe_name(pipe)); | |
374 | ||
d3902c3e JN |
375 | if (WARN_ON(port == PORT_A)) |
376 | return; | |
377 | ||
2d1fe073 | 378 | if (HAS_PCH_IBX(dev_priv)) { |
495a5bb8 JN |
379 | aud_config = IBX_AUD_CFG(pipe); |
380 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
666a4537 | 381 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
495a5bb8 JN |
382 | aud_config = VLV_AUD_CFG(pipe); |
383 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
384 | } else { | |
385 | aud_config = CPT_AUD_CFG(pipe); | |
386 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
387 | } | |
388 | ||
389 | /* Disable timestamps */ | |
390 | tmp = I915_READ(aud_config); | |
391 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
392 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
393 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
394 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
2210ce7f | 395 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
495a5bb8 JN |
396 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
397 | I915_WRITE(aud_config, tmp); | |
398 | ||
d3902c3e | 399 | eldv = IBX_ELD_VALID(port); |
495a5bb8 JN |
400 | |
401 | /* Invalidate ELD */ | |
402 | tmp = I915_READ(aud_cntrl_st2); | |
403 | tmp &= ~eldv; | |
404 | I915_WRITE(aud_cntrl_st2, tmp); | |
405 | } | |
406 | ||
69bfe1a9 | 407 | static void ilk_audio_codec_enable(struct drm_connector *connector, |
d8dee42a | 408 | struct intel_encoder *intel_encoder, |
5e7234c9 | 409 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 | 410 | { |
fac5e23e | 411 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
d8dee42a | 412 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
c6bde93b | 413 | enum pipe pipe = intel_crtc->pipe; |
d8dee42a | 414 | enum port port = intel_encoder->port; |
7c10a2b5 | 415 | uint8_t *eld = connector->eld; |
38cb2eca | 416 | uint32_t tmp, eldv; |
f9f682ae | 417 | int len, i; |
f0f59a00 | 418 | i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; |
c6bde93b JN |
419 | |
420 | DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", | |
938fd8aa | 421 | port_name(port), pipe_name(pipe), drm_eld_size(eld)); |
c6bde93b | 422 | |
d3902c3e JN |
423 | if (WARN_ON(port == PORT_A)) |
424 | return; | |
425 | ||
c6bde93b JN |
426 | /* |
427 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
428 | * disabled during the mode set. The proper fix would be to push the | |
429 | * rest of the setup into a vblank work item, queued here, but the | |
430 | * infrastructure is not there yet. | |
431 | */ | |
7c10a2b5 JN |
432 | |
433 | if (HAS_PCH_IBX(connector->dev)) { | |
434 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); | |
435 | aud_config = IBX_AUD_CFG(pipe); | |
436 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
437 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
666a4537 WB |
438 | } else if (IS_VALLEYVIEW(connector->dev) || |
439 | IS_CHERRYVIEW(connector->dev)) { | |
7c10a2b5 JN |
440 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
441 | aud_config = VLV_AUD_CFG(pipe); | |
442 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
443 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
444 | } else { | |
445 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); | |
446 | aud_config = CPT_AUD_CFG(pipe); | |
447 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
448 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
449 | } | |
450 | ||
d3902c3e | 451 | eldv = IBX_ELD_VALID(port); |
7c10a2b5 | 452 | |
c6bde93b | 453 | /* Invalidate ELD */ |
f9f682ae JN |
454 | tmp = I915_READ(aud_cntrl_st2); |
455 | tmp &= ~eldv; | |
456 | I915_WRITE(aud_cntrl_st2, tmp); | |
7c10a2b5 | 457 | |
c6bde93b | 458 | /* Reset ELD write address */ |
f9f682ae | 459 | tmp = I915_READ(aud_cntl_st); |
c46f111f | 460 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
f9f682ae | 461 | I915_WRITE(aud_cntl_st, tmp); |
7c10a2b5 | 462 | |
c6bde93b | 463 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
464 | len = min(drm_eld_size(eld), 84); |
465 | for (i = 0; i < len / 4; i++) | |
7c10a2b5 JN |
466 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
467 | ||
c6bde93b | 468 | /* ELD valid */ |
f9f682ae JN |
469 | tmp = I915_READ(aud_cntrl_st2); |
470 | tmp |= eldv; | |
471 | I915_WRITE(aud_cntrl_st2, tmp); | |
c6bde93b JN |
472 | |
473 | /* Enable timestamps */ | |
474 | tmp = I915_READ(aud_config); | |
475 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
476 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
477 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
2210ce7f | 478 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
c6bde93b JN |
479 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
480 | else | |
5e7234c9 | 481 | tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); |
c6bde93b | 482 | I915_WRITE(aud_config, tmp); |
7c10a2b5 JN |
483 | } |
484 | ||
69bfe1a9 JN |
485 | /** |
486 | * intel_audio_codec_enable - Enable the audio codec for HD audio | |
487 | * @intel_encoder: encoder on which to enable audio | |
488 | * | |
489 | * The enable sequences may only be performed after enabling the transcoder and | |
490 | * port, and after completed link training. | |
491 | */ | |
492 | void intel_audio_codec_enable(struct intel_encoder *intel_encoder) | |
7c10a2b5 | 493 | { |
33d1e7c6 JN |
494 | struct drm_encoder *encoder = &intel_encoder->base; |
495 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); | |
7c5f93b0 | 496 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
7c10a2b5 | 497 | struct drm_connector *connector; |
d8dee42a | 498 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
51e1d83c | 499 | struct i915_audio_component *acomp = dev_priv->audio_component; |
d8dee42a | 500 | enum port port = intel_encoder->port; |
f9318941 | 501 | enum pipe pipe = crtc->pipe; |
7c10a2b5 | 502 | |
9e5a3b52 | 503 | connector = drm_select_eld(encoder); |
7c10a2b5 JN |
504 | if (!connector) |
505 | return; | |
506 | ||
507 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
508 | connector->base.id, | |
509 | connector->name, | |
510 | connector->encoder->base.id, | |
511 | connector->encoder->name); | |
512 | ||
6189b036 JN |
513 | /* ELD Conn_Type */ |
514 | connector->eld[5] &= ~(3 << 2); | |
2210ce7f | 515 | if (intel_crtc_has_dp_encoder(crtc->config)) |
6189b036 JN |
516 | connector->eld[5] |= (1 << 2); |
517 | ||
124abe07 | 518 | connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; |
7c10a2b5 | 519 | |
69bfe1a9 | 520 | if (dev_priv->display.audio_codec_enable) |
124abe07 VS |
521 | dev_priv->display.audio_codec_enable(connector, intel_encoder, |
522 | adjusted_mode); | |
51e1d83c | 523 | |
cae666ce | 524 | mutex_lock(&dev_priv->av_mutex); |
f1a3acea | 525 | intel_encoder->audio_connector = connector; |
f9318941 | 526 | |
9dfbffcf | 527 | /* referred in audio callbacks */ |
f9318941 | 528 | dev_priv->av_enc_map[pipe] = intel_encoder; |
cae666ce TI |
529 | mutex_unlock(&dev_priv->av_mutex); |
530 | ||
f9318941 PD |
531 | /* audio drivers expect pipe = -1 to indicate Non-MST cases */ |
532 | if (intel_encoder->type != INTEL_OUTPUT_DP_MST) | |
533 | pipe = -1; | |
534 | ||
51e1d83c | 535 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) |
f9318941 PD |
536 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, |
537 | (int) port, (int) pipe); | |
69bfe1a9 JN |
538 | } |
539 | ||
540 | /** | |
541 | * intel_audio_codec_disable - Disable the audio codec for HD audio | |
95d0be61 | 542 | * @intel_encoder: encoder on which to disable audio |
69bfe1a9 JN |
543 | * |
544 | * The disable sequences must be performed before disabling the transcoder or | |
545 | * port. | |
546 | */ | |
51e1d83c | 547 | void intel_audio_codec_disable(struct intel_encoder *intel_encoder) |
69bfe1a9 | 548 | { |
51e1d83c | 549 | struct drm_encoder *encoder = &intel_encoder->base; |
d8dee42a | 550 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
51e1d83c | 551 | struct i915_audio_component *acomp = dev_priv->audio_component; |
d8dee42a | 552 | enum port port = intel_encoder->port; |
f9318941 PD |
553 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
554 | enum pipe pipe = crtc->pipe; | |
69bfe1a9 JN |
555 | |
556 | if (dev_priv->display.audio_codec_disable) | |
51e1d83c DH |
557 | dev_priv->display.audio_codec_disable(intel_encoder); |
558 | ||
cae666ce | 559 | mutex_lock(&dev_priv->av_mutex); |
f1a3acea | 560 | intel_encoder->audio_connector = NULL; |
f9318941 | 561 | dev_priv->av_enc_map[pipe] = NULL; |
cae666ce TI |
562 | mutex_unlock(&dev_priv->av_mutex); |
563 | ||
f9318941 PD |
564 | /* audio drivers expect pipe = -1 to indicate Non-MST cases */ |
565 | if (intel_encoder->type != INTEL_OUTPUT_DP_MST) | |
566 | pipe = -1; | |
567 | ||
51e1d83c | 568 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) |
f9318941 PD |
569 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, |
570 | (int) port, (int) pipe); | |
7c10a2b5 JN |
571 | } |
572 | ||
573 | /** | |
88212941 ID |
574 | * intel_init_audio_hooks - Set up chip specific audio hooks |
575 | * @dev_priv: device private | |
7c10a2b5 | 576 | */ |
88212941 | 577 | void intel_init_audio_hooks(struct drm_i915_private *dev_priv) |
7c10a2b5 | 578 | { |
88212941 | 579 | if (IS_G4X(dev_priv)) { |
69bfe1a9 | 580 | dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; |
76d8d3e5 | 581 | dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; |
88212941 | 582 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
69bfe1a9 | 583 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
495a5bb8 | 584 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
88212941 | 585 | } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) { |
69bfe1a9 JN |
586 | dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; |
587 | dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; | |
88212941 | 588 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
69bfe1a9 | 589 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
495a5bb8 | 590 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
69bfe1a9 | 591 | } |
7c10a2b5 | 592 | } |
58fddc28 | 593 | |
c49d13ee | 594 | static void i915_audio_component_get_power(struct device *kdev) |
58fddc28 | 595 | { |
c49d13ee | 596 | intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO); |
58fddc28 ID |
597 | } |
598 | ||
c49d13ee | 599 | static void i915_audio_component_put_power(struct device *kdev) |
58fddc28 | 600 | { |
c49d13ee | 601 | intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO); |
58fddc28 ID |
602 | } |
603 | ||
c49d13ee | 604 | static void i915_audio_component_codec_wake_override(struct device *kdev, |
632f3ab9 LH |
605 | bool enable) |
606 | { | |
c49d13ee | 607 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
632f3ab9 LH |
608 | u32 tmp; |
609 | ||
ef11bdb3 | 610 | if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) |
632f3ab9 LH |
611 | return; |
612 | ||
c49d13ee | 613 | i915_audio_component_get_power(kdev); |
d838a110 | 614 | |
632f3ab9 LH |
615 | /* |
616 | * Enable/disable generating the codec wake signal, overriding the | |
617 | * internal logic to generate the codec wake to controller. | |
618 | */ | |
619 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
620 | tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; | |
621 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
622 | usleep_range(1000, 1500); | |
623 | ||
624 | if (enable) { | |
625 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
626 | tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; | |
627 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
628 | usleep_range(1000, 1500); | |
629 | } | |
d838a110 | 630 | |
c49d13ee | 631 | i915_audio_component_put_power(kdev); |
632f3ab9 LH |
632 | } |
633 | ||
58fddc28 | 634 | /* Get CDCLK in kHz */ |
c49d13ee | 635 | static int i915_audio_component_get_cdclk_freq(struct device *kdev) |
58fddc28 | 636 | { |
c49d13ee | 637 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
58fddc28 ID |
638 | |
639 | if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) | |
640 | return -ENODEV; | |
641 | ||
1033f92e | 642 | return dev_priv->cdclk_freq; |
58fddc28 ID |
643 | } |
644 | ||
f9318941 PD |
645 | static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, |
646 | int port, int pipe) | |
647 | { | |
648 | ||
649 | if (WARN_ON(pipe >= I915_MAX_PIPES)) | |
650 | return NULL; | |
651 | ||
652 | /* MST */ | |
653 | if (pipe >= 0) | |
654 | return dev_priv->av_enc_map[pipe]; | |
655 | ||
656 | /* Non-MST */ | |
657 | for_each_pipe(dev_priv, pipe) { | |
658 | struct intel_encoder *encoder; | |
659 | ||
660 | encoder = dev_priv->av_enc_map[pipe]; | |
661 | if (encoder == NULL) | |
662 | continue; | |
663 | ||
664 | if (port == encoder->port) | |
665 | return encoder; | |
666 | } | |
667 | ||
668 | return NULL; | |
669 | } | |
670 | ||
671 | static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, | |
672 | int pipe, int rate) | |
4a21ef7d | 673 | { |
c49d13ee | 674 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
4a21ef7d | 675 | struct intel_encoder *intel_encoder; |
4a21ef7d | 676 | struct intel_crtc *crtc; |
8f1ec181 | 677 | struct drm_display_mode *adjusted_mode; |
7e8275c2 | 678 | struct i915_audio_component *acomp = dev_priv->audio_component; |
0bdf5a05 | 679 | int err = 0; |
4a21ef7d | 680 | |
4bd2d6f6 | 681 | if (!HAS_DDI(dev_priv)) |
4a21ef7d LY |
682 | return 0; |
683 | ||
c49d13ee | 684 | i915_audio_component_get_power(kdev); |
4a21ef7d | 685 | mutex_lock(&dev_priv->av_mutex); |
f9318941 | 686 | |
4a21ef7d | 687 | /* 1. get the pipe */ |
f9318941 | 688 | intel_encoder = get_saved_enc(dev_priv, port, pipe); |
0bdf5a05 TI |
689 | if (!intel_encoder || !intel_encoder->base.crtc || |
690 | intel_encoder->type != INTEL_OUTPUT_HDMI) { | |
f9318941 | 691 | DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); |
0bdf5a05 TI |
692 | err = -ENODEV; |
693 | goto unlock; | |
4a21ef7d | 694 | } |
f9318941 PD |
695 | |
696 | /* pipe passed from the audio driver will be -1 for Non-MST case */ | |
0bdf5a05 TI |
697 | crtc = to_intel_crtc(intel_encoder->base.crtc); |
698 | pipe = crtc->pipe; | |
0bdf5a05 | 699 | |
8f1ec181 | 700 | adjusted_mode = &crtc->config->base.adjusted_mode; |
4a21ef7d | 701 | |
7e8275c2 LY |
702 | /* port must be valid now, otherwise the pipe will be invalid */ |
703 | acomp->aud_sample_rate[port] = rate; | |
704 | ||
8f1ec181 | 705 | hsw_audio_config_update(crtc, port, adjusted_mode); |
4a21ef7d | 706 | |
0bdf5a05 | 707 | unlock: |
4a21ef7d | 708 | mutex_unlock(&dev_priv->av_mutex); |
c49d13ee | 709 | i915_audio_component_put_power(kdev); |
0bdf5a05 | 710 | return err; |
4a21ef7d LY |
711 | } |
712 | ||
c49d13ee | 713 | static int i915_audio_component_get_eld(struct device *kdev, int port, |
f9318941 | 714 | int pipe, bool *enabled, |
cae666ce TI |
715 | unsigned char *buf, int max_bytes) |
716 | { | |
c49d13ee | 717 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
cae666ce | 718 | struct intel_encoder *intel_encoder; |
cae666ce TI |
719 | const u8 *eld; |
720 | int ret = -EINVAL; | |
721 | ||
722 | mutex_lock(&dev_priv->av_mutex); | |
f9318941 PD |
723 | |
724 | intel_encoder = get_saved_enc(dev_priv, port, pipe); | |
725 | if (!intel_encoder) { | |
726 | DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); | |
727 | mutex_unlock(&dev_priv->av_mutex); | |
728 | return ret; | |
729 | } | |
730 | ||
731 | ret = 0; | |
732 | *enabled = intel_encoder->audio_connector != NULL; | |
733 | if (*enabled) { | |
734 | eld = intel_encoder->audio_connector->eld; | |
735 | ret = drm_eld_size(eld); | |
736 | memcpy(buf, eld, min(max_bytes, ret)); | |
cae666ce TI |
737 | } |
738 | ||
739 | mutex_unlock(&dev_priv->av_mutex); | |
740 | return ret; | |
4a21ef7d LY |
741 | } |
742 | ||
58fddc28 ID |
743 | static const struct i915_audio_component_ops i915_audio_component_ops = { |
744 | .owner = THIS_MODULE, | |
745 | .get_power = i915_audio_component_get_power, | |
746 | .put_power = i915_audio_component_put_power, | |
632f3ab9 | 747 | .codec_wake_override = i915_audio_component_codec_wake_override, |
58fddc28 | 748 | .get_cdclk_freq = i915_audio_component_get_cdclk_freq, |
4a21ef7d | 749 | .sync_audio_rate = i915_audio_component_sync_audio_rate, |
cae666ce | 750 | .get_eld = i915_audio_component_get_eld, |
58fddc28 ID |
751 | }; |
752 | ||
c49d13ee DW |
753 | static int i915_audio_component_bind(struct device *i915_kdev, |
754 | struct device *hda_kdev, void *data) | |
58fddc28 ID |
755 | { |
756 | struct i915_audio_component *acomp = data; | |
c49d13ee | 757 | struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); |
7e8275c2 | 758 | int i; |
58fddc28 ID |
759 | |
760 | if (WARN_ON(acomp->ops || acomp->dev)) | |
761 | return -EEXIST; | |
762 | ||
91c8a326 | 763 | drm_modeset_lock_all(&dev_priv->drm); |
58fddc28 | 764 | acomp->ops = &i915_audio_component_ops; |
c49d13ee | 765 | acomp->dev = i915_kdev; |
7e8275c2 LY |
766 | BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); |
767 | for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) | |
768 | acomp->aud_sample_rate[i] = 0; | |
51e1d83c | 769 | dev_priv->audio_component = acomp; |
91c8a326 | 770 | drm_modeset_unlock_all(&dev_priv->drm); |
58fddc28 ID |
771 | |
772 | return 0; | |
773 | } | |
774 | ||
c49d13ee DW |
775 | static void i915_audio_component_unbind(struct device *i915_kdev, |
776 | struct device *hda_kdev, void *data) | |
58fddc28 ID |
777 | { |
778 | struct i915_audio_component *acomp = data; | |
c49d13ee | 779 | struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); |
58fddc28 | 780 | |
91c8a326 | 781 | drm_modeset_lock_all(&dev_priv->drm); |
58fddc28 ID |
782 | acomp->ops = NULL; |
783 | acomp->dev = NULL; | |
51e1d83c | 784 | dev_priv->audio_component = NULL; |
91c8a326 | 785 | drm_modeset_unlock_all(&dev_priv->drm); |
58fddc28 ID |
786 | } |
787 | ||
788 | static const struct component_ops i915_audio_component_bind_ops = { | |
789 | .bind = i915_audio_component_bind, | |
790 | .unbind = i915_audio_component_unbind, | |
791 | }; | |
792 | ||
793 | /** | |
794 | * i915_audio_component_init - initialize and register the audio component | |
795 | * @dev_priv: i915 device instance | |
796 | * | |
797 | * This will register with the component framework a child component which | |
798 | * will bind dynamically to the snd_hda_intel driver's corresponding master | |
799 | * component when the latter is registered. During binding the child | |
800 | * initializes an instance of struct i915_audio_component which it receives | |
801 | * from the master. The master can then start to use the interface defined by | |
802 | * this struct. Each side can break the binding at any point by deregistering | |
803 | * its own component after which each side's component unbind callback is | |
804 | * called. | |
805 | * | |
806 | * We ignore any error during registration and continue with reduced | |
807 | * functionality (i.e. without HDMI audio). | |
808 | */ | |
809 | void i915_audio_component_init(struct drm_i915_private *dev_priv) | |
810 | { | |
811 | int ret; | |
812 | ||
91c8a326 | 813 | ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops); |
58fddc28 ID |
814 | if (ret < 0) { |
815 | DRM_ERROR("failed to add audio component (%d)\n", ret); | |
816 | /* continue with reduced functionality */ | |
817 | return; | |
818 | } | |
819 | ||
820 | dev_priv->audio_component_registered = true; | |
821 | } | |
822 | ||
823 | /** | |
824 | * i915_audio_component_cleanup - deregister the audio component | |
825 | * @dev_priv: i915 device instance | |
826 | * | |
827 | * Deregisters the audio component, breaking any existing binding to the | |
828 | * corresponding snd_hda_intel driver's master component. | |
829 | */ | |
830 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) | |
831 | { | |
832 | if (!dev_priv->audio_component_registered) | |
833 | return; | |
834 | ||
91c8a326 | 835 | component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); |
58fddc28 ID |
836 | dev_priv->audio_component_registered = false; |
837 | } |