Commit | Line | Data |
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7c10a2b5 JN |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
58fddc28 ID |
25 | #include <linux/component.h> |
26 | #include <drm/i915_component.h> | |
46d196ec | 27 | #include <drm/intel_lpe_audio.h> |
58fddc28 | 28 | #include "intel_drv.h" |
7c10a2b5 JN |
29 | |
30 | #include <drm/drmP.h> | |
31 | #include <drm/drm_edid.h> | |
7c10a2b5 JN |
32 | #include "i915_drv.h" |
33 | ||
28855d2a JN |
34 | /** |
35 | * DOC: High Definition Audio over HDMI and Display Port | |
36 | * | |
37 | * The graphics and audio drivers together support High Definition Audio over | |
38 | * HDMI and Display Port. The audio programming sequences are divided into audio | |
39 | * codec and controller enable and disable sequences. The graphics driver | |
40 | * handles the audio codec sequences, while the audio driver handles the audio | |
41 | * controller sequences. | |
42 | * | |
43 | * The disable sequences must be performed before disabling the transcoder or | |
44 | * port. The enable sequences may only be performed after enabling the | |
3e6da4a9 JN |
45 | * transcoder and port, and after completed link training. Therefore the audio |
46 | * enable/disable sequences are part of the modeset sequence. | |
28855d2a JN |
47 | * |
48 | * The codec and controller sequences could be done either parallel or serial, | |
49 | * but generally the ELDV/PD change in the codec sequence indicates to the audio | |
50 | * driver that the controller sequence should start. Indeed, most of the | |
51 | * co-operation between the graphics and audio drivers is handled via audio | |
52 | * related registers. (The notable exception is the power management, not | |
53 | * covered here.) | |
cb422619 | 54 | * |
62cacc79 DV |
55 | * The struct &i915_audio_component is used to interact between the graphics |
56 | * and audio drivers. The struct &i915_audio_component_ops @ops in it is | |
cb422619 | 57 | * defined in graphics driver and called in audio driver. The |
62cacc79 | 58 | * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. |
28855d2a JN |
59 | */ |
60 | ||
6014ac12 LY |
61 | /* DP N/M table */ |
62 | #define LC_540M 540000 | |
63 | #define LC_270M 270000 | |
64 | #define LC_162M 162000 | |
65 | ||
66 | struct dp_aud_n_m { | |
67 | int sample_rate; | |
68 | int clock; | |
69 | u16 m; | |
70 | u16 n; | |
71 | }; | |
72 | ||
73 | /* Values according to DP 1.4 Table 2-104 */ | |
74 | static const struct dp_aud_n_m dp_aud_n_m[] = { | |
75 | { 32000, LC_162M, 1024, 10125 }, | |
76 | { 44100, LC_162M, 784, 5625 }, | |
77 | { 48000, LC_162M, 512, 3375 }, | |
78 | { 64000, LC_162M, 2048, 10125 }, | |
79 | { 88200, LC_162M, 1568, 5625 }, | |
80 | { 96000, LC_162M, 1024, 3375 }, | |
81 | { 128000, LC_162M, 4096, 10125 }, | |
82 | { 176400, LC_162M, 3136, 5625 }, | |
83 | { 192000, LC_162M, 2048, 3375 }, | |
84 | { 32000, LC_270M, 1024, 16875 }, | |
85 | { 44100, LC_270M, 784, 9375 }, | |
86 | { 48000, LC_270M, 512, 5625 }, | |
87 | { 64000, LC_270M, 2048, 16875 }, | |
88 | { 88200, LC_270M, 1568, 9375 }, | |
89 | { 96000, LC_270M, 1024, 5625 }, | |
90 | { 128000, LC_270M, 4096, 16875 }, | |
91 | { 176400, LC_270M, 3136, 9375 }, | |
92 | { 192000, LC_270M, 2048, 5625 }, | |
93 | { 32000, LC_540M, 1024, 33750 }, | |
94 | { 44100, LC_540M, 784, 18750 }, | |
95 | { 48000, LC_540M, 512, 11250 }, | |
96 | { 64000, LC_540M, 2048, 33750 }, | |
97 | { 88200, LC_540M, 1568, 18750 }, | |
98 | { 96000, LC_540M, 1024, 11250 }, | |
99 | { 128000, LC_540M, 4096, 33750 }, | |
100 | { 176400, LC_540M, 3136, 18750 }, | |
101 | { 192000, LC_540M, 2048, 11250 }, | |
102 | }; | |
103 | ||
104 | static const struct dp_aud_n_m * | |
8ec47de2 | 105 | audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) |
6014ac12 LY |
106 | { |
107 | int i; | |
108 | ||
109 | for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) { | |
110 | if (rate == dp_aud_n_m[i].sample_rate && | |
8ec47de2 | 111 | crtc_state->port_clock == dp_aud_n_m[i].clock) |
6014ac12 LY |
112 | return &dp_aud_n_m[i]; |
113 | } | |
114 | ||
115 | return NULL; | |
116 | } | |
117 | ||
87fcb2ad | 118 | static const struct { |
7c10a2b5 JN |
119 | int clock; |
120 | u32 config; | |
121 | } hdmi_audio_clock[] = { | |
606bb5e0 | 122 | { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
7c10a2b5 JN |
123 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
124 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
606bb5e0 | 125 | { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
7c10a2b5 | 126 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
606bb5e0 VS |
127 | { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
128 | { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7c10a2b5 | 129 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
606bb5e0 | 130 | { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
7c10a2b5 JN |
131 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
132 | }; | |
133 | ||
4a21ef7d LY |
134 | /* HDMI N/CTS table */ |
135 | #define TMDS_297M 297000 | |
606bb5e0 | 136 | #define TMDS_296M 296703 |
4a21ef7d LY |
137 | static const struct { |
138 | int sample_rate; | |
139 | int clock; | |
140 | int n; | |
141 | int cts; | |
9eeb7304 | 142 | } hdmi_aud_ncts[] = { |
4a21ef7d LY |
143 | { 44100, TMDS_296M, 4459, 234375 }, |
144 | { 44100, TMDS_297M, 4704, 247500 }, | |
145 | { 48000, TMDS_296M, 5824, 281250 }, | |
146 | { 48000, TMDS_297M, 5120, 247500 }, | |
147 | { 32000, TMDS_296M, 5824, 421875 }, | |
148 | { 32000, TMDS_297M, 3072, 222750 }, | |
149 | { 88200, TMDS_296M, 8918, 234375 }, | |
150 | { 88200, TMDS_297M, 9408, 247500 }, | |
151 | { 96000, TMDS_296M, 11648, 281250 }, | |
152 | { 96000, TMDS_297M, 10240, 247500 }, | |
153 | { 176400, TMDS_296M, 17836, 234375 }, | |
154 | { 176400, TMDS_297M, 18816, 247500 }, | |
155 | { 192000, TMDS_296M, 23296, 281250 }, | |
156 | { 192000, TMDS_297M, 20480, 247500 }, | |
157 | }; | |
158 | ||
7c10a2b5 | 159 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
8ec47de2 | 160 | static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) |
7c10a2b5 | 161 | { |
8ec47de2 VS |
162 | const struct drm_display_mode *adjusted_mode = |
163 | &crtc_state->base.adjusted_mode; | |
7c10a2b5 JN |
164 | int i; |
165 | ||
166 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
aad941d5 | 167 | if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) |
7c10a2b5 JN |
168 | break; |
169 | } | |
170 | ||
171 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
5e7234c9 | 172 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", |
aad941d5 | 173 | adjusted_mode->crtc_clock); |
7c10a2b5 JN |
174 | i = 1; |
175 | } | |
176 | ||
177 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
178 | hdmi_audio_clock[i].clock, | |
179 | hdmi_audio_clock[i].config); | |
180 | ||
181 | return hdmi_audio_clock[i].config; | |
182 | } | |
183 | ||
8ec47de2 | 184 | static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, |
9eeb7304 | 185 | int rate) |
4a21ef7d | 186 | { |
8ec47de2 VS |
187 | const struct drm_display_mode *adjusted_mode = |
188 | &crtc_state->base.adjusted_mode; | |
4a21ef7d LY |
189 | int i; |
190 | ||
9eeb7304 JN |
191 | for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) { |
192 | if (rate == hdmi_aud_ncts[i].sample_rate && | |
193 | adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) { | |
194 | return hdmi_aud_ncts[i].n; | |
4a21ef7d LY |
195 | } |
196 | } | |
197 | return 0; | |
198 | } | |
199 | ||
7c10a2b5 | 200 | static bool intel_eld_uptodate(struct drm_connector *connector, |
f0f59a00 VS |
201 | i915_reg_t reg_eldv, uint32_t bits_eldv, |
202 | i915_reg_t reg_elda, uint32_t bits_elda, | |
203 | i915_reg_t reg_edid) | |
7c10a2b5 | 204 | { |
fac5e23e | 205 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
7c10a2b5 | 206 | uint8_t *eld = connector->eld; |
f9f682ae JN |
207 | uint32_t tmp; |
208 | int i; | |
7c10a2b5 | 209 | |
f9f682ae JN |
210 | tmp = I915_READ(reg_eldv); |
211 | tmp &= bits_eldv; | |
7c10a2b5 | 212 | |
f9f682ae | 213 | if (!tmp) |
7c10a2b5 JN |
214 | return false; |
215 | ||
f9f682ae JN |
216 | tmp = I915_READ(reg_elda); |
217 | tmp &= ~bits_elda; | |
218 | I915_WRITE(reg_elda, tmp); | |
7c10a2b5 | 219 | |
938fd8aa | 220 | for (i = 0; i < drm_eld_size(eld) / 4; i++) |
7c10a2b5 JN |
221 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
222 | return false; | |
223 | ||
224 | return true; | |
225 | } | |
226 | ||
8ec47de2 VS |
227 | static void g4x_audio_codec_disable(struct intel_encoder *encoder, |
228 | const struct intel_crtc_state *old_crtc_state, | |
229 | const struct drm_connector_state *old_conn_state) | |
76d8d3e5 | 230 | { |
fac5e23e | 231 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
76d8d3e5 JN |
232 | uint32_t eldv, tmp; |
233 | ||
234 | DRM_DEBUG_KMS("Disable audio codec\n"); | |
235 | ||
236 | tmp = I915_READ(G4X_AUD_VID_DID); | |
237 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
238 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
239 | else | |
240 | eldv = G4X_ELDV_DEVCTG; | |
241 | ||
242 | /* Invalidate ELD */ | |
243 | tmp = I915_READ(G4X_AUD_CNTL_ST); | |
244 | tmp &= ~eldv; | |
245 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
246 | } | |
247 | ||
8ec47de2 VS |
248 | static void g4x_audio_codec_enable(struct intel_encoder *encoder, |
249 | const struct intel_crtc_state *crtc_state, | |
250 | const struct drm_connector_state *conn_state) | |
7c10a2b5 | 251 | { |
8ec47de2 VS |
252 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
253 | struct drm_connector *connector = conn_state->connector; | |
7c10a2b5 JN |
254 | uint8_t *eld = connector->eld; |
255 | uint32_t eldv; | |
f9f682ae JN |
256 | uint32_t tmp; |
257 | int len, i; | |
7c10a2b5 | 258 | |
d5ee08de JN |
259 | DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); |
260 | ||
f9f682ae JN |
261 | tmp = I915_READ(G4X_AUD_VID_DID); |
262 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
7c10a2b5 JN |
263 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
264 | else | |
265 | eldv = G4X_ELDV_DEVCTG; | |
266 | ||
267 | if (intel_eld_uptodate(connector, | |
268 | G4X_AUD_CNTL_ST, eldv, | |
c46f111f | 269 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, |
7c10a2b5 JN |
270 | G4X_HDMIW_HDMIEDID)) |
271 | return; | |
272 | ||
f9f682ae | 273 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
c46f111f | 274 | tmp &= ~(eldv | G4X_ELD_ADDR_MASK); |
f9f682ae JN |
275 | len = (tmp >> 9) & 0x1f; /* ELD buffer size */ |
276 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 | 277 | |
938fd8aa | 278 | len = min(drm_eld_size(eld) / 4, len); |
7c10a2b5 JN |
279 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
280 | for (i = 0; i < len; i++) | |
281 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
282 | ||
f9f682ae JN |
283 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
284 | tmp |= eldv; | |
285 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 JN |
286 | } |
287 | ||
12e87f23 | 288 | static void |
8ec47de2 VS |
289 | hsw_dp_audio_config_update(struct intel_encoder *encoder, |
290 | const struct intel_crtc_state *crtc_state) | |
12e87f23 | 291 | { |
8ec47de2 | 292 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
6014ac12 | 293 | struct i915_audio_component *acomp = dev_priv->audio_component; |
8ec47de2 VS |
294 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
295 | enum port port = encoder->port; | |
296 | enum pipe pipe = crtc->pipe; | |
297 | const struct dp_aud_n_m *nm; | |
298 | int rate; | |
12e87f23 JN |
299 | u32 tmp; |
300 | ||
8ec47de2 VS |
301 | rate = acomp ? acomp->aud_sample_rate[port] : 0; |
302 | nm = audio_config_dp_get_n_m(crtc_state, rate); | |
6014ac12 LY |
303 | if (nm) |
304 | DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n); | |
305 | else | |
306 | DRM_DEBUG_KMS("using automatic Maud, Naud\n"); | |
307 | ||
12e87f23 JN |
308 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
309 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
310 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
311 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
312 | tmp |= AUD_CONFIG_N_VALUE_INDEX; | |
313 | ||
6014ac12 LY |
314 | if (nm) { |
315 | tmp &= ~AUD_CONFIG_N_MASK; | |
316 | tmp |= AUD_CONFIG_N(nm->n); | |
317 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
318 | } | |
319 | ||
12e87f23 | 320 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
6014ac12 LY |
321 | |
322 | tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe)); | |
323 | tmp &= ~AUD_CONFIG_M_MASK; | |
324 | tmp &= ~AUD_M_CTS_M_VALUE_INDEX; | |
325 | tmp &= ~AUD_M_CTS_M_PROG_ENABLE; | |
326 | ||
327 | if (nm) { | |
328 | tmp |= nm->m; | |
329 | tmp |= AUD_M_CTS_M_VALUE_INDEX; | |
330 | tmp |= AUD_M_CTS_M_PROG_ENABLE; | |
331 | } | |
332 | ||
333 | I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp); | |
12e87f23 JN |
334 | } |
335 | ||
336 | static void | |
8ec47de2 VS |
337 | hsw_hdmi_audio_config_update(struct intel_encoder *encoder, |
338 | const struct intel_crtc_state *crtc_state) | |
6c26291d | 339 | { |
8ec47de2 | 340 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
6c26291d | 341 | struct i915_audio_component *acomp = dev_priv->audio_component; |
8ec47de2 VS |
342 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
343 | enum port port = encoder->port; | |
344 | enum pipe pipe = crtc->pipe; | |
345 | int n, rate; | |
6c26291d JN |
346 | u32 tmp; |
347 | ||
8ec47de2 VS |
348 | rate = acomp ? acomp->aud_sample_rate[port] : 0; |
349 | ||
6c26291d JN |
350 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
351 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
352 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
6c26291d | 353 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
8ec47de2 | 354 | tmp |= audio_config_hdmi_pixel_clock(crtc_state); |
12e87f23 | 355 | |
8ec47de2 | 356 | n = audio_config_hdmi_get_n(crtc_state, rate); |
9ca89c44 JN |
357 | if (n != 0) { |
358 | DRM_DEBUG_KMS("using N %d\n", n); | |
359 | ||
360 | tmp &= ~AUD_CONFIG_N_MASK; | |
361 | tmp |= AUD_CONFIG_N(n); | |
362 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
363 | } else { | |
364 | DRM_DEBUG_KMS("using automatic N\n"); | |
6c26291d JN |
365 | } |
366 | ||
367 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
6014ac12 | 368 | |
b9f16ff2 LY |
369 | /* |
370 | * Let's disable "Enable CTS or M Prog bit" | |
371 | * and let HW calculate the value | |
372 | */ | |
6014ac12 | 373 | tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe)); |
b9f16ff2 | 374 | tmp &= ~AUD_M_CTS_M_PROG_ENABLE; |
6014ac12 | 375 | tmp &= ~AUD_M_CTS_M_VALUE_INDEX; |
6014ac12 | 376 | I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp); |
6c26291d JN |
377 | } |
378 | ||
12e87f23 | 379 | static void |
8ec47de2 VS |
380 | hsw_audio_config_update(struct intel_encoder *encoder, |
381 | const struct intel_crtc_state *crtc_state) | |
12e87f23 | 382 | { |
8ec47de2 VS |
383 | if (intel_crtc_has_dp_encoder(crtc_state)) |
384 | hsw_dp_audio_config_update(encoder, crtc_state); | |
12e87f23 | 385 | else |
8ec47de2 | 386 | hsw_hdmi_audio_config_update(encoder, crtc_state); |
12e87f23 JN |
387 | } |
388 | ||
8ec47de2 VS |
389 | static void hsw_audio_codec_disable(struct intel_encoder *encoder, |
390 | const struct intel_crtc_state *old_crtc_state, | |
391 | const struct drm_connector_state *old_conn_state) | |
69bfe1a9 | 392 | { |
fac5e23e | 393 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
8ec47de2 VS |
394 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
395 | enum pipe pipe = crtc->pipe; | |
69bfe1a9 JN |
396 | uint32_t tmp; |
397 | ||
5fad84a7 JN |
398 | DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); |
399 | ||
4a21ef7d LY |
400 | mutex_lock(&dev_priv->av_mutex); |
401 | ||
5fad84a7 JN |
402 | /* Disable timestamps */ |
403 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
404 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
405 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
406 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
407 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
8ec47de2 | 408 | if (intel_crtc_has_dp_encoder(old_crtc_state)) |
5fad84a7 JN |
409 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
410 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
411 | ||
412 | /* Invalidate ELD */ | |
69bfe1a9 | 413 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 414 | tmp &= ~AUDIO_ELD_VALID(pipe); |
eb45fa0b | 415 | tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); |
69bfe1a9 | 416 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
4a21ef7d LY |
417 | |
418 | mutex_unlock(&dev_priv->av_mutex); | |
69bfe1a9 JN |
419 | } |
420 | ||
8ec47de2 VS |
421 | static void hsw_audio_codec_enable(struct intel_encoder *encoder, |
422 | const struct intel_crtc_state *crtc_state, | |
423 | const struct drm_connector_state *conn_state) | |
7c10a2b5 | 424 | { |
8ec47de2 VS |
425 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
426 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
427 | struct drm_connector *connector = conn_state->connector; | |
428 | enum pipe pipe = crtc->pipe; | |
5fad84a7 | 429 | const uint8_t *eld = connector->eld; |
f9f682ae JN |
430 | uint32_t tmp; |
431 | int len, i; | |
7c10a2b5 | 432 | |
5fad84a7 | 433 | DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", |
938fd8aa | 434 | pipe_name(pipe), drm_eld_size(eld)); |
7c10a2b5 | 435 | |
4a21ef7d LY |
436 | mutex_lock(&dev_priv->av_mutex); |
437 | ||
5fad84a7 JN |
438 | /* Enable audio presence detect, invalidate ELD */ |
439 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
82910ac6 JN |
440 | tmp |= AUDIO_OUTPUT_ENABLE(pipe); |
441 | tmp &= ~AUDIO_ELD_VALID(pipe); | |
5fad84a7 | 442 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
7c10a2b5 | 443 | |
5fad84a7 JN |
444 | /* |
445 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
446 | * disabled during the mode set. The proper fix would be to push the | |
447 | * rest of the setup into a vblank work item, queued here, but the | |
448 | * infrastructure is not there yet. | |
449 | */ | |
7c10a2b5 | 450 | |
5fad84a7 JN |
451 | /* Reset ELD write address */ |
452 | tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); | |
c46f111f | 453 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
5fad84a7 | 454 | I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); |
7c10a2b5 | 455 | |
5fad84a7 | 456 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
457 | len = min(drm_eld_size(eld), 84); |
458 | for (i = 0; i < len / 4; i++) | |
5fad84a7 | 459 | I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); |
7c10a2b5 | 460 | |
5fad84a7 | 461 | /* ELD valid */ |
69bfe1a9 | 462 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 463 | tmp |= AUDIO_ELD_VALID(pipe); |
69bfe1a9 | 464 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
5fad84a7 JN |
465 | |
466 | /* Enable timestamps */ | |
8ec47de2 | 467 | hsw_audio_config_update(encoder, crtc_state); |
4a21ef7d LY |
468 | |
469 | mutex_unlock(&dev_priv->av_mutex); | |
7c10a2b5 JN |
470 | } |
471 | ||
8ec47de2 VS |
472 | static void ilk_audio_codec_disable(struct intel_encoder *encoder, |
473 | const struct intel_crtc_state *old_crtc_state, | |
474 | const struct drm_connector_state *old_conn_state) | |
495a5bb8 | 475 | { |
8ec47de2 VS |
476 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
477 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
478 | enum pipe pipe = crtc->pipe; | |
479 | enum port port = encoder->port; | |
495a5bb8 | 480 | uint32_t tmp, eldv; |
f0f59a00 | 481 | i915_reg_t aud_config, aud_cntrl_st2; |
495a5bb8 JN |
482 | |
483 | DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", | |
484 | port_name(port), pipe_name(pipe)); | |
485 | ||
d3902c3e JN |
486 | if (WARN_ON(port == PORT_A)) |
487 | return; | |
488 | ||
2d1fe073 | 489 | if (HAS_PCH_IBX(dev_priv)) { |
495a5bb8 JN |
490 | aud_config = IBX_AUD_CFG(pipe); |
491 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
666a4537 | 492 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
495a5bb8 JN |
493 | aud_config = VLV_AUD_CFG(pipe); |
494 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
495 | } else { | |
496 | aud_config = CPT_AUD_CFG(pipe); | |
497 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
498 | } | |
499 | ||
500 | /* Disable timestamps */ | |
501 | tmp = I915_READ(aud_config); | |
502 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
503 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
504 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
505 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
8ec47de2 | 506 | if (intel_crtc_has_dp_encoder(old_crtc_state)) |
495a5bb8 JN |
507 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
508 | I915_WRITE(aud_config, tmp); | |
509 | ||
d3902c3e | 510 | eldv = IBX_ELD_VALID(port); |
495a5bb8 JN |
511 | |
512 | /* Invalidate ELD */ | |
513 | tmp = I915_READ(aud_cntrl_st2); | |
514 | tmp &= ~eldv; | |
515 | I915_WRITE(aud_cntrl_st2, tmp); | |
516 | } | |
517 | ||
8ec47de2 VS |
518 | static void ilk_audio_codec_enable(struct intel_encoder *encoder, |
519 | const struct intel_crtc_state *crtc_state, | |
520 | const struct drm_connector_state *conn_state) | |
7c10a2b5 | 521 | { |
8ec47de2 VS |
522 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
523 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
524 | struct drm_connector *connector = conn_state->connector; | |
525 | enum pipe pipe = crtc->pipe; | |
526 | enum port port = encoder->port; | |
7c10a2b5 | 527 | uint8_t *eld = connector->eld; |
38cb2eca | 528 | uint32_t tmp, eldv; |
f9f682ae | 529 | int len, i; |
f0f59a00 | 530 | i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; |
c6bde93b JN |
531 | |
532 | DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", | |
938fd8aa | 533 | port_name(port), pipe_name(pipe), drm_eld_size(eld)); |
c6bde93b | 534 | |
d3902c3e JN |
535 | if (WARN_ON(port == PORT_A)) |
536 | return; | |
537 | ||
c6bde93b JN |
538 | /* |
539 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
540 | * disabled during the mode set. The proper fix would be to push the | |
541 | * rest of the setup into a vblank work item, queued here, but the | |
542 | * infrastructure is not there yet. | |
543 | */ | |
7c10a2b5 | 544 | |
6e266956 | 545 | if (HAS_PCH_IBX(dev_priv)) { |
7c10a2b5 JN |
546 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
547 | aud_config = IBX_AUD_CFG(pipe); | |
548 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
549 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
920a14b2 TU |
550 | } else if (IS_VALLEYVIEW(dev_priv) || |
551 | IS_CHERRYVIEW(dev_priv)) { | |
7c10a2b5 JN |
552 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
553 | aud_config = VLV_AUD_CFG(pipe); | |
554 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
555 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
556 | } else { | |
557 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); | |
558 | aud_config = CPT_AUD_CFG(pipe); | |
559 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
560 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
561 | } | |
562 | ||
d3902c3e | 563 | eldv = IBX_ELD_VALID(port); |
7c10a2b5 | 564 | |
c6bde93b | 565 | /* Invalidate ELD */ |
f9f682ae JN |
566 | tmp = I915_READ(aud_cntrl_st2); |
567 | tmp &= ~eldv; | |
568 | I915_WRITE(aud_cntrl_st2, tmp); | |
7c10a2b5 | 569 | |
c6bde93b | 570 | /* Reset ELD write address */ |
f9f682ae | 571 | tmp = I915_READ(aud_cntl_st); |
c46f111f | 572 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
f9f682ae | 573 | I915_WRITE(aud_cntl_st, tmp); |
7c10a2b5 | 574 | |
c6bde93b | 575 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
576 | len = min(drm_eld_size(eld), 84); |
577 | for (i = 0; i < len / 4; i++) | |
7c10a2b5 JN |
578 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
579 | ||
c6bde93b | 580 | /* ELD valid */ |
f9f682ae JN |
581 | tmp = I915_READ(aud_cntrl_st2); |
582 | tmp |= eldv; | |
583 | I915_WRITE(aud_cntrl_st2, tmp); | |
c6bde93b JN |
584 | |
585 | /* Enable timestamps */ | |
586 | tmp = I915_READ(aud_config); | |
587 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
588 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
589 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
8ec47de2 | 590 | if (intel_crtc_has_dp_encoder(crtc_state)) |
c6bde93b JN |
591 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
592 | else | |
8ec47de2 | 593 | tmp |= audio_config_hdmi_pixel_clock(crtc_state); |
c6bde93b | 594 | I915_WRITE(aud_config, tmp); |
7c10a2b5 JN |
595 | } |
596 | ||
69bfe1a9 JN |
597 | /** |
598 | * intel_audio_codec_enable - Enable the audio codec for HD audio | |
8ec47de2 | 599 | * @encoder: encoder on which to enable audio |
bbf35e9d ML |
600 | * @crtc_state: pointer to the current crtc state. |
601 | * @conn_state: pointer to the current connector state. | |
69bfe1a9 JN |
602 | * |
603 | * The enable sequences may only be performed after enabling the transcoder and | |
604 | * port, and after completed link training. | |
605 | */ | |
8ec47de2 | 606 | void intel_audio_codec_enable(struct intel_encoder *encoder, |
bbf35e9d ML |
607 | const struct intel_crtc_state *crtc_state, |
608 | const struct drm_connector_state *conn_state) | |
7c10a2b5 | 609 | { |
8ec47de2 | 610 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
51e1d83c | 611 | struct i915_audio_component *acomp = dev_priv->audio_component; |
8ec47de2 VS |
612 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
613 | struct drm_connector *connector = conn_state->connector; | |
614 | const struct drm_display_mode *adjusted_mode = | |
615 | &crtc_state->base.adjusted_mode; | |
616 | enum port port = encoder->port; | |
617 | enum pipe pipe = crtc->pipe; | |
7c10a2b5 | 618 | |
8ec47de2 | 619 | if (!connector->eld[0]) |
7c10a2b5 JN |
620 | return; |
621 | ||
622 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
623 | connector->base.id, | |
624 | connector->name, | |
625 | connector->encoder->base.id, | |
626 | connector->encoder->name); | |
627 | ||
124abe07 | 628 | connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; |
7c10a2b5 | 629 | |
69bfe1a9 | 630 | if (dev_priv->display.audio_codec_enable) |
8ec47de2 VS |
631 | dev_priv->display.audio_codec_enable(encoder, |
632 | crtc_state, | |
633 | conn_state); | |
51e1d83c | 634 | |
cae666ce | 635 | mutex_lock(&dev_priv->av_mutex); |
8ec47de2 | 636 | encoder->audio_connector = connector; |
f9318941 | 637 | |
9dfbffcf | 638 | /* referred in audio callbacks */ |
8ec47de2 | 639 | dev_priv->av_enc_map[pipe] = encoder; |
cae666ce TI |
640 | mutex_unlock(&dev_priv->av_mutex); |
641 | ||
9c9191f3 TI |
642 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { |
643 | /* audio drivers expect pipe = -1 to indicate Non-MST cases */ | |
9f846643 | 644 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) |
9c9191f3 | 645 | pipe = -1; |
f9318941 PD |
646 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, |
647 | (int) port, (int) pipe); | |
9c9191f3 TI |
648 | } |
649 | ||
20be551e | 650 | intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld, |
c98ec5ba | 651 | crtc_state->port_clock, |
9f846643 | 652 | intel_crtc_has_dp_encoder(crtc_state)); |
69bfe1a9 JN |
653 | } |
654 | ||
655 | /** | |
656 | * intel_audio_codec_disable - Disable the audio codec for HD audio | |
8ec47de2 | 657 | * @encoder: encoder on which to disable audio |
764b9f2c VS |
658 | * @old_crtc_state: pointer to the old crtc state. |
659 | * @old_conn_state: pointer to the old connector state. | |
69bfe1a9 JN |
660 | * |
661 | * The disable sequences must be performed before disabling the transcoder or | |
662 | * port. | |
663 | */ | |
8ec47de2 VS |
664 | void intel_audio_codec_disable(struct intel_encoder *encoder, |
665 | const struct intel_crtc_state *old_crtc_state, | |
666 | const struct drm_connector_state *old_conn_state) | |
69bfe1a9 | 667 | { |
8ec47de2 | 668 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
51e1d83c | 669 | struct i915_audio_component *acomp = dev_priv->audio_component; |
8ec47de2 VS |
670 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
671 | enum port port = encoder->port; | |
f9318941 | 672 | enum pipe pipe = crtc->pipe; |
69bfe1a9 JN |
673 | |
674 | if (dev_priv->display.audio_codec_disable) | |
8ec47de2 VS |
675 | dev_priv->display.audio_codec_disable(encoder, |
676 | old_crtc_state, | |
677 | old_conn_state); | |
51e1d83c | 678 | |
cae666ce | 679 | mutex_lock(&dev_priv->av_mutex); |
8ec47de2 | 680 | encoder->audio_connector = NULL; |
f9318941 | 681 | dev_priv->av_enc_map[pipe] = NULL; |
cae666ce TI |
682 | mutex_unlock(&dev_priv->av_mutex); |
683 | ||
9c9191f3 TI |
684 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { |
685 | /* audio drivers expect pipe = -1 to indicate Non-MST cases */ | |
9f846643 | 686 | if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) |
9c9191f3 | 687 | pipe = -1; |
f9318941 PD |
688 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, |
689 | (int) port, (int) pipe); | |
9c9191f3 | 690 | } |
46d196ec | 691 | |
20be551e | 692 | intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false); |
7c10a2b5 JN |
693 | } |
694 | ||
695 | /** | |
88212941 ID |
696 | * intel_init_audio_hooks - Set up chip specific audio hooks |
697 | * @dev_priv: device private | |
7c10a2b5 | 698 | */ |
88212941 | 699 | void intel_init_audio_hooks(struct drm_i915_private *dev_priv) |
7c10a2b5 | 700 | { |
88212941 | 701 | if (IS_G4X(dev_priv)) { |
69bfe1a9 | 702 | dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; |
76d8d3e5 | 703 | dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; |
88212941 | 704 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
69bfe1a9 | 705 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
495a5bb8 | 706 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
88212941 | 707 | } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) { |
69bfe1a9 JN |
708 | dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; |
709 | dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; | |
88212941 | 710 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
69bfe1a9 | 711 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
495a5bb8 | 712 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
69bfe1a9 | 713 | } |
7c10a2b5 | 714 | } |
58fddc28 | 715 | |
c49d13ee | 716 | static void i915_audio_component_get_power(struct device *kdev) |
58fddc28 | 717 | { |
c49d13ee | 718 | intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO); |
58fddc28 ID |
719 | } |
720 | ||
c49d13ee | 721 | static void i915_audio_component_put_power(struct device *kdev) |
58fddc28 | 722 | { |
c49d13ee | 723 | intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO); |
58fddc28 ID |
724 | } |
725 | ||
c49d13ee | 726 | static void i915_audio_component_codec_wake_override(struct device *kdev, |
632f3ab9 LH |
727 | bool enable) |
728 | { | |
c49d13ee | 729 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
632f3ab9 LH |
730 | u32 tmp; |
731 | ||
b976dc53 | 732 | if (!IS_GEN9_BC(dev_priv)) |
632f3ab9 LH |
733 | return; |
734 | ||
c49d13ee | 735 | i915_audio_component_get_power(kdev); |
d838a110 | 736 | |
632f3ab9 LH |
737 | /* |
738 | * Enable/disable generating the codec wake signal, overriding the | |
739 | * internal logic to generate the codec wake to controller. | |
740 | */ | |
741 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
742 | tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; | |
743 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
744 | usleep_range(1000, 1500); | |
745 | ||
746 | if (enable) { | |
747 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
748 | tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; | |
749 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
750 | usleep_range(1000, 1500); | |
751 | } | |
d838a110 | 752 | |
c49d13ee | 753 | i915_audio_component_put_power(kdev); |
632f3ab9 LH |
754 | } |
755 | ||
58fddc28 | 756 | /* Get CDCLK in kHz */ |
c49d13ee | 757 | static int i915_audio_component_get_cdclk_freq(struct device *kdev) |
58fddc28 | 758 | { |
c49d13ee | 759 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
58fddc28 ID |
760 | |
761 | if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) | |
762 | return -ENODEV; | |
763 | ||
49cd97a3 | 764 | return dev_priv->cdclk.hw.cdclk; |
58fddc28 ID |
765 | } |
766 | ||
31613268 LY |
767 | /* |
768 | * get the intel_encoder according to the parameter port and pipe | |
769 | * intel_encoder is saved by the index of pipe | |
770 | * MST & (pipe >= 0): return the av_enc_map[pipe], | |
771 | * when port is matched | |
772 | * MST & (pipe < 0): this is invalid | |
773 | * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry) | |
774 | * will get the right intel_encoder with port matched | |
775 | * Non-MST & (pipe < 0): get the right intel_encoder with port matched | |
776 | */ | |
f9318941 PD |
777 | static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, |
778 | int port, int pipe) | |
779 | { | |
31613268 | 780 | struct intel_encoder *encoder; |
f9318941 | 781 | |
f9318941 | 782 | /* MST */ |
31613268 | 783 | if (pipe >= 0) { |
72a6d72c JN |
784 | if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map))) |
785 | return NULL; | |
786 | ||
31613268 LY |
787 | encoder = dev_priv->av_enc_map[pipe]; |
788 | /* | |
789 | * when bootup, audio driver may not know it is | |
790 | * MST or not. So it will poll all the port & pipe | |
791 | * combinations | |
792 | */ | |
793 | if (encoder != NULL && encoder->port == port && | |
794 | encoder->type == INTEL_OUTPUT_DP_MST) | |
795 | return encoder; | |
796 | } | |
f9318941 PD |
797 | |
798 | /* Non-MST */ | |
31613268 LY |
799 | if (pipe > 0) |
800 | return NULL; | |
f9318941 | 801 | |
31613268 | 802 | for_each_pipe(dev_priv, pipe) { |
f9318941 PD |
803 | encoder = dev_priv->av_enc_map[pipe]; |
804 | if (encoder == NULL) | |
805 | continue; | |
806 | ||
31613268 LY |
807 | if (encoder->type == INTEL_OUTPUT_DP_MST) |
808 | continue; | |
809 | ||
f9318941 PD |
810 | if (port == encoder->port) |
811 | return encoder; | |
812 | } | |
813 | ||
814 | return NULL; | |
815 | } | |
816 | ||
817 | static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, | |
818 | int pipe, int rate) | |
4a21ef7d | 819 | { |
c49d13ee | 820 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
7e8275c2 | 821 | struct i915_audio_component *acomp = dev_priv->audio_component; |
8ec47de2 VS |
822 | struct intel_encoder *encoder; |
823 | struct intel_crtc *crtc; | |
0bdf5a05 | 824 | int err = 0; |
4a21ef7d | 825 | |
4bd2d6f6 | 826 | if (!HAS_DDI(dev_priv)) |
4a21ef7d LY |
827 | return 0; |
828 | ||
c49d13ee | 829 | i915_audio_component_get_power(kdev); |
4a21ef7d | 830 | mutex_lock(&dev_priv->av_mutex); |
f9318941 | 831 | |
4a21ef7d | 832 | /* 1. get the pipe */ |
8ec47de2 VS |
833 | encoder = get_saved_enc(dev_priv, port, pipe); |
834 | if (!encoder || !encoder->base.crtc) { | |
f9318941 | 835 | DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); |
0bdf5a05 TI |
836 | err = -ENODEV; |
837 | goto unlock; | |
4a21ef7d | 838 | } |
f9318941 | 839 | |
8ec47de2 | 840 | crtc = to_intel_crtc(encoder->base.crtc); |
4a21ef7d | 841 | |
7e8275c2 LY |
842 | /* port must be valid now, otherwise the pipe will be invalid */ |
843 | acomp->aud_sample_rate[port] = rate; | |
844 | ||
8ec47de2 | 845 | hsw_audio_config_update(encoder, crtc->config); |
4a21ef7d | 846 | |
0bdf5a05 | 847 | unlock: |
4a21ef7d | 848 | mutex_unlock(&dev_priv->av_mutex); |
c49d13ee | 849 | i915_audio_component_put_power(kdev); |
0bdf5a05 | 850 | return err; |
4a21ef7d LY |
851 | } |
852 | ||
c49d13ee | 853 | static int i915_audio_component_get_eld(struct device *kdev, int port, |
f9318941 | 854 | int pipe, bool *enabled, |
cae666ce TI |
855 | unsigned char *buf, int max_bytes) |
856 | { | |
c49d13ee | 857 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
cae666ce | 858 | struct intel_encoder *intel_encoder; |
cae666ce TI |
859 | const u8 *eld; |
860 | int ret = -EINVAL; | |
861 | ||
862 | mutex_lock(&dev_priv->av_mutex); | |
f9318941 PD |
863 | |
864 | intel_encoder = get_saved_enc(dev_priv, port, pipe); | |
865 | if (!intel_encoder) { | |
866 | DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); | |
867 | mutex_unlock(&dev_priv->av_mutex); | |
868 | return ret; | |
869 | } | |
870 | ||
871 | ret = 0; | |
872 | *enabled = intel_encoder->audio_connector != NULL; | |
873 | if (*enabled) { | |
874 | eld = intel_encoder->audio_connector->eld; | |
875 | ret = drm_eld_size(eld); | |
876 | memcpy(buf, eld, min(max_bytes, ret)); | |
cae666ce TI |
877 | } |
878 | ||
879 | mutex_unlock(&dev_priv->av_mutex); | |
880 | return ret; | |
4a21ef7d LY |
881 | } |
882 | ||
58fddc28 ID |
883 | static const struct i915_audio_component_ops i915_audio_component_ops = { |
884 | .owner = THIS_MODULE, | |
885 | .get_power = i915_audio_component_get_power, | |
886 | .put_power = i915_audio_component_put_power, | |
632f3ab9 | 887 | .codec_wake_override = i915_audio_component_codec_wake_override, |
58fddc28 | 888 | .get_cdclk_freq = i915_audio_component_get_cdclk_freq, |
4a21ef7d | 889 | .sync_audio_rate = i915_audio_component_sync_audio_rate, |
cae666ce | 890 | .get_eld = i915_audio_component_get_eld, |
58fddc28 ID |
891 | }; |
892 | ||
c49d13ee DW |
893 | static int i915_audio_component_bind(struct device *i915_kdev, |
894 | struct device *hda_kdev, void *data) | |
58fddc28 ID |
895 | { |
896 | struct i915_audio_component *acomp = data; | |
c49d13ee | 897 | struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); |
7e8275c2 | 898 | int i; |
58fddc28 ID |
899 | |
900 | if (WARN_ON(acomp->ops || acomp->dev)) | |
901 | return -EEXIST; | |
902 | ||
91c8a326 | 903 | drm_modeset_lock_all(&dev_priv->drm); |
58fddc28 | 904 | acomp->ops = &i915_audio_component_ops; |
c49d13ee | 905 | acomp->dev = i915_kdev; |
7e8275c2 LY |
906 | BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); |
907 | for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) | |
908 | acomp->aud_sample_rate[i] = 0; | |
51e1d83c | 909 | dev_priv->audio_component = acomp; |
91c8a326 | 910 | drm_modeset_unlock_all(&dev_priv->drm); |
58fddc28 ID |
911 | |
912 | return 0; | |
913 | } | |
914 | ||
c49d13ee DW |
915 | static void i915_audio_component_unbind(struct device *i915_kdev, |
916 | struct device *hda_kdev, void *data) | |
58fddc28 ID |
917 | { |
918 | struct i915_audio_component *acomp = data; | |
c49d13ee | 919 | struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); |
58fddc28 | 920 | |
91c8a326 | 921 | drm_modeset_lock_all(&dev_priv->drm); |
58fddc28 ID |
922 | acomp->ops = NULL; |
923 | acomp->dev = NULL; | |
51e1d83c | 924 | dev_priv->audio_component = NULL; |
91c8a326 | 925 | drm_modeset_unlock_all(&dev_priv->drm); |
58fddc28 ID |
926 | } |
927 | ||
928 | static const struct component_ops i915_audio_component_bind_ops = { | |
929 | .bind = i915_audio_component_bind, | |
930 | .unbind = i915_audio_component_unbind, | |
931 | }; | |
932 | ||
933 | /** | |
934 | * i915_audio_component_init - initialize and register the audio component | |
935 | * @dev_priv: i915 device instance | |
936 | * | |
937 | * This will register with the component framework a child component which | |
938 | * will bind dynamically to the snd_hda_intel driver's corresponding master | |
939 | * component when the latter is registered. During binding the child | |
940 | * initializes an instance of struct i915_audio_component which it receives | |
941 | * from the master. The master can then start to use the interface defined by | |
942 | * this struct. Each side can break the binding at any point by deregistering | |
943 | * its own component after which each side's component unbind callback is | |
944 | * called. | |
945 | * | |
946 | * We ignore any error during registration and continue with reduced | |
947 | * functionality (i.e. without HDMI audio). | |
948 | */ | |
949 | void i915_audio_component_init(struct drm_i915_private *dev_priv) | |
950 | { | |
951 | int ret; | |
952 | ||
10810944 EW |
953 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
954 | return; | |
955 | ||
91c8a326 | 956 | ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops); |
58fddc28 ID |
957 | if (ret < 0) { |
958 | DRM_ERROR("failed to add audio component (%d)\n", ret); | |
959 | /* continue with reduced functionality */ | |
960 | return; | |
961 | } | |
962 | ||
963 | dev_priv->audio_component_registered = true; | |
964 | } | |
965 | ||
966 | /** | |
967 | * i915_audio_component_cleanup - deregister the audio component | |
968 | * @dev_priv: i915 device instance | |
969 | * | |
970 | * Deregisters the audio component, breaking any existing binding to the | |
971 | * corresponding snd_hda_intel driver's master component. | |
972 | */ | |
973 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) | |
974 | { | |
975 | if (!dev_priv->audio_component_registered) | |
976 | return; | |
977 | ||
91c8a326 | 978 | component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); |
58fddc28 ID |
979 | dev_priv->audio_component_registered = false; |
980 | } | |
eef57324 JA |
981 | |
982 | /** | |
983 | * intel_audio_init() - Initialize the audio driver either using | |
984 | * component framework or using lpe audio bridge | |
985 | * @dev_priv: the i915 drm device private data | |
986 | * | |
987 | */ | |
988 | void intel_audio_init(struct drm_i915_private *dev_priv) | |
989 | { | |
990 | if (intel_lpe_audio_init(dev_priv) < 0) | |
991 | i915_audio_component_init(dev_priv); | |
992 | } | |
993 | ||
994 | /** | |
995 | * intel_audio_deinit() - deinitialize the audio driver | |
996 | * @dev_priv: the i915 drm device private data | |
997 | * | |
998 | */ | |
999 | void intel_audio_deinit(struct drm_i915_private *dev_priv) | |
1000 | { | |
1001 | if ((dev_priv)->lpe_audio.platdev != NULL) | |
1002 | intel_lpe_audio_teardown(dev_priv); | |
1003 | else | |
1004 | i915_audio_component_cleanup(dev_priv); | |
1005 | } |