[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_vgpu.c

/*
 * Copyright(c) 2011-2015 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include "intel_drv.h"
#include "i915_vgpu.h"

/**
 * DOC: Intel GVT-g guest support
 *
 * Intel GVT-g is a graphics virtualization technology which shares the
 * GPU among multiple virtual machines on a time-sharing basis. Each
 * virtual machine is presented a virtual GPU (vGPU), which has equivalent
 * features as the underlying physical GPU (pGPU), so i915 driver can run
 * seamlessly in a virtual machine. This file provides vGPU specific
 * optimizations when running in a virtual machine, to reduce the complexity
 * of vGPU emulation and to improve the overall performance.
 *
 * A primary function introduced here is so-called "address space ballooning"
 * technique. Intel GVT-g partitions global graphics memory among multiple VMs,
 * so each VM can directly access a portion of the memory without hypervisor's
 * intervention, e.g. filling textures or queuing commands. However with the
 * partitioning an unmodified i915 driver would assume a smaller graphics
 * memory starting from address ZERO, then requires vGPU emulation module to
 * translate the graphics address between 'guest view' and 'host view', for
 * all registers and command opcodes which contain a graphics memory address.
 * To reduce the complexity, Intel GVT-g introduces "address space ballooning",
 * by telling the exact partitioning knowledge to each guest i915 driver, which
 * then reserves and prevents non-allocated portions from allocation. Thus vGPU
 * emulation module only needs to scan and validate graphics addresses without
 * complexity of address translation.
 *
 */

/**
 * i915_check_vgpu - detect virtual GPU
 * @dev_priv: i915 device private
 *
 * This function is called at the initialization stage, to detect whether
 * running on a vGPU.
 */
void i915_check_vgpu(struct drm_i915_private *dev_priv)
{
	struct intel_uncore *uncore = &dev_priv->uncore;
	u64 magic;
	u16 version_major;

	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);

	magic = __raw_uncore_read64(uncore, vgtif_reg(magic));
	if (magic != VGT_MAGIC)
		return;

	version_major = __raw_uncore_read16(uncore, vgtif_reg(version_major));
	if (version_major < VGT_VERSION_MAJOR) {
		DRM_INFO("VGT interface version mismatch!\n");
		return;
	}

	dev_priv->vgpu.caps = __raw_uncore_read32(uncore, vgtif_reg(vgt_caps));

	dev_priv->vgpu.active = true;
	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
}

bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
{
	return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT;
}

struct _balloon_info_ {
	/*
	 * There are up to 2 regions per mappable/unmappable graphic
	 * memory that might be ballooned. Here, index 0/1 is for mappable
	 * graphic memory, 2/3 for unmappable graphic memory.
	 */
	struct drm_mm_node space[4];
};

static struct _balloon_info_ bl_info;

static void vgt_deballoon_space(struct i915_ggtt *ggtt,
				struct drm_mm_node *node)
{
	if (!drm_mm_node_allocated(node))
		return;

	DRM_DEBUG_DRIVER("deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n",
			 node->start,
			 node->start + node->size,
			 node->size / 1024);

	ggtt->vm.reserved -= node->size;
	drm_mm_remove_node(node);
}

/**
 * intel_vgt_deballoon - deballoon reserved graphics address trunks
 * @dev_priv: i915 device private data
 *
 * This function is called to deallocate the ballooned-out graphic memory, when
 * driver is unloaded or when ballooning fails.
 */
void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
{
	int i;

	if (!intel_vgpu_active(dev_priv))
		return;

	DRM_DEBUG("VGT deballoon.\n");

	for (i = 0; i < 4; i++)
		vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
}

static int vgt_balloon_space(struct i915_ggtt *ggtt,
			     struct drm_mm_node *node,
			     unsigned long start, unsigned long end)
{
	unsigned long size = end - start;
	int ret;

	if (start >= end)
		return -EINVAL;

	DRM_INFO("balloon space: range [ 0x%lx - 0x%lx ] %lu KiB.\n",
		 start, end, size / 1024);
	ret = i915_gem_gtt_reserve(&ggtt->vm, node,
				   size, start, I915_COLOR_UNEVICTABLE,
				   0);
	if (!ret)
		ggtt->vm.reserved += size;

	return ret;
}

/**
 * intel_vgt_balloon - balloon out reserved graphics address trunks
 * @dev_priv: i915 device private data
 *
 * This function is called at the initialization stage, to balloon out the
 * graphic address space allocated to other vGPUs, by marking these spaces as
 * reserved. The ballooning related knowledge(starting address and size of
 * the mappable/unmappable graphic memory) is described in the vgt_if structure
 * in a reserved mmio range.
 *
 * To give an example, the drawing below depicts one typical scenario after
 * ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned
 * out each for the mappable and the non-mappable part. From the vGPU1 point of
 * view, the total size is the same as the physical one, with the start address
 * of its graphic space being zero. Yet there are some portions ballooned out(
 * the shadow part, which are marked as reserved by drm allocator). From the
 * host point of view, the graphic address space is partitioned by multiple
 * vGPUs in different VMs. ::
 *
 *                         vGPU1 view         Host view
 *              0 ------> +-----------+     +-----------+
 *                ^       |###########|     |   vGPU3   |
 *                |       |###########|     +-----------+
 *                |       |###########|     |   vGPU2   |
 *                |       +-----------+     +-----------+
 *         mappable GM    | available | ==> |   vGPU1   |
 *                |       +-----------+     +-----------+
 *                |       |###########|     |           |
 *                v       |###########|     |   Host    |
 *                +=======+===========+     +===========+
 *                ^       |###########|     |   vGPU3   |
 *                |       |###########|     +-----------+
 *                |       |###########|     |   vGPU2   |
 *                |       +-----------+     +-----------+
 *       unmappable GM    | available | ==> |   vGPU1   |
 *                |       +-----------+     +-----------+
 *                |       |###########|     |           |
 *                |       |###########|     |   Host    |
 *                v       |###########|     |           |
 *  total GM size ------> +-----------+     +-----------+
 *
 * Returns:
 * zero on success, non-zero if configuration invalid or ballooning failed
 */
int intel_vgt_balloon(struct drm_i915_private *dev_priv)
{
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
	unsigned long ggtt_end = ggtt->vm.total;

	unsigned long mappable_base, mappable_size, mappable_end;
	unsigned long unmappable_base, unmappable_size, unmappable_end;
	int ret;

	if (!intel_vgpu_active(dev_priv))
		return 0;

	mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
	mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
	unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
	unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));

	mappable_end = mappable_base + mappable_size;
	unmappable_end = unmappable_base + unmappable_size;

	DRM_INFO("VGT ballooning configuration:\n");
	DRM_INFO("Mappable graphic memory: base 0x%lx size %ldKiB\n",
		 mappable_base, mappable_size / 1024);
	DRM_INFO("Unmappable graphic memory: base 0x%lx size %ldKiB\n",
		 unmappable_base, unmappable_size / 1024);

	if (mappable_end > ggtt->mappable_end ||
	    unmappable_base < ggtt->mappable_end ||
	    unmappable_end > ggtt_end) {
		DRM_ERROR("Invalid ballooning configuration!\n");
		return -EINVAL;
	}

	/* Unmappable graphic memory ballooning */
	if (unmappable_base > ggtt->mappable_end) {
		ret = vgt_balloon_space(ggtt, &bl_info.space[2],
					ggtt->mappable_end, unmappable_base);

		if (ret)
			goto err;
	}

	if (unmappable_end < ggtt_end) {
		ret = vgt_balloon_space(ggtt, &bl_info.space[3],
					unmappable_end, ggtt_end);
		if (ret)
			goto err_upon_mappable;
	}

	/* Mappable graphic memory ballooning */
	if (mappable_base) {
		ret = vgt_balloon_space(ggtt, &bl_info.space[0],
					0, mappable_base);

		if (ret)
			goto err_upon_unmappable;
	}

	if (mappable_end < ggtt->mappable_end) {
		ret = vgt_balloon_space(ggtt, &bl_info.space[1],
					mappable_end, ggtt->mappable_end);

		if (ret)
			goto err_below_mappable;
	}

	DRM_INFO("VGT balloon successfully\n");
	return 0;

err_below_mappable:
	vgt_deballoon_space(ggtt, &bl_info.space[0]);
err_upon_unmappable:
	vgt_deballoon_space(ggtt, &bl_info.space[3]);
err_upon_mappable:
	vgt_deballoon_space(ggtt, &bl_info.space[2]);
err:
	DRM_ERROR("VGT balloon fail\n");
	return ret;
}
Commit	Line	Data
cf9d2890 YZ	1	/*
	2	* Copyright(c) 2011-2015 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*/
	23
	24	#include "intel_drv.h"
	25	#include "i915_vgpu.h"
	26
	27	/**
	28	* DOC: Intel GVT-g guest support
	29	*
	30	* Intel GVT-g is a graphics virtualization technology which shares the
	31	* GPU among multiple virtual machines on a time-sharing basis. Each
	32	* virtual machine is presented a virtual GPU (vGPU), which has equivalent
	33	* features as the underlying physical GPU (pGPU), so i915 driver can run
	34	* seamlessly in a virtual machine. This file provides vGPU specific
	35	* optimizations when running in a virtual machine, to reduce the complexity
	36	* of vGPU emulation and to improve the overall performance.
	37	*
	38	* A primary function introduced here is so-called "address space ballooning"
	39	* technique. Intel GVT-g partitions global graphics memory among multiple VMs,
	40	* so each VM can directly access a portion of the memory without hypervisor's
	41	* intervention, e.g. filling textures or queuing commands. However with the
	42	* partitioning an unmodified i915 driver would assume a smaller graphics
	43	* memory starting from address ZERO, then requires vGPU emulation module to
	44	* translate the graphics address between 'guest view' and 'host view', for
	45	* all registers and command opcodes which contain a graphics memory address.
	46	* To reduce the complexity, Intel GVT-g introduces "address space ballooning",
	47	* by telling the exact partitioning knowledge to each guest i915 driver, which
	48	* then reserves and prevents non-allocated portions from allocation. Thus vGPU
	49	* emulation module only needs to scan and validate graphics addresses without
	50	* complexity of address translation.
	51	*
	52	*/
	53
	54	/**
	55	* i915_check_vgpu - detect virtual GPU
14bb2c11	56	* @dev_priv: i915 device private
cf9d2890 YZ	57	*
	58	* This function is called at the initialization stage, to detect whether
	59	* running on a vGPU.
	60	*/
dc97997a	61	void i915_check_vgpu(struct drm_i915_private *dev_priv)
cf9d2890	62	{
6ebc9692	63	struct intel_uncore *uncore = &dev_priv->uncore;
0c8792d0 ZW	64	u64 magic;
0c8792d0 ZW	65	u16 version_major;
cf9d2890 YZ	66
	67	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
	68
6cc5ca76	69	magic = __raw_uncore_read64(uncore, vgtif_reg(magic));
cf9d2890 YZ	70	if (magic != VGT_MAGIC)
	71	return;
	72
6cc5ca76	73	version_major = __raw_uncore_read16(uncore, vgtif_reg(version_major));
0c8792d0	74	if (version_major < VGT_VERSION_MAJOR) {
cf9d2890 YZ	75	DRM_INFO("VGT interface version mismatch!\n");
	76	return;
	77	}
	78
6cc5ca76	79	dev_priv->vgpu.caps = __raw_uncore_read32(uncore, vgtif_reg(vgt_caps));
8a4ab66f	80
cf9d2890 YZ	81	dev_priv->vgpu.active = true;
	82	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
	83	}
5dda8fa3	84
ca6ac684	85	bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
8a4ab66f	86	{
ca6ac684	87	return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT;
8a4ab66f TZ	88	}
8a4ab66f TZ	89
5dda8fa3 YZ	90	struct _balloon_info_ {
	91	/*
	92	* There are up to 2 regions per mappable/unmappable graphic
	93	* memory that might be ballooned. Here, index 0/1 is for mappable
	94	* graphic memory, 2/3 for unmappable graphic memory.
	95	*/
	96	struct drm_mm_node space[4];
	97	};
	98
	99	static struct _balloon_info_ bl_info;
	100
ff8f7975 WL	101	static void vgt_deballoon_space(struct i915_ggtt *ggtt,
	102	struct drm_mm_node *node)
	103	{
0a3dfbb5 XZ	104	if (!drm_mm_node_allocated(node))
	105	return;
	106
ff8f7975 WL	107	DRM_DEBUG_DRIVER("deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n",
	108	node->start,
	109	node->start + node->size,
	110	node->size / 1024);
	111
82ad6443	112	ggtt->vm.reserved -= node->size;
ff8f7975 WL	113	drm_mm_remove_node(node);
	114	}
	115
5dda8fa3 YZ	116	/**
5dda8fa3 YZ	117	* intel_vgt_deballoon - deballoon reserved graphics address trunks
62f90b38	118	* @dev_priv: i915 device private data
5dda8fa3 YZ	119	*
	120	* This function is called to deallocate the ballooned-out graphic memory, when
	121	* driver is unloaded or when ballooning fails.
	122	*/
b02d22a3	123	void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
5dda8fa3 YZ	124	{
	125	int i;
	126
b02d22a3 ZW	127	if (!intel_vgpu_active(dev_priv))
	128	return;
	129
5dda8fa3 YZ	130	DRM_DEBUG("VGT deballoon.\n");
5dda8fa3 YZ	131
ff8f7975 WL	132	for (i = 0; i < 4; i++)
ff8f7975 WL	133	vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
5dda8fa3 YZ	134	}
5dda8fa3 YZ	135
625d988a	136	static int vgt_balloon_space(struct i915_ggtt *ggtt,
5dda8fa3 YZ	137	struct drm_mm_node *node,
	138	unsigned long start, unsigned long end)
	139	{
	140	unsigned long size = end - start;
ff8f7975	141	int ret;
5dda8fa3	142
b368f533	143	if (start >= end)
5dda8fa3 YZ	144	return -EINVAL;
	145
	146	DRM_INFO("balloon space: range [ 0x%lx - 0x%lx ] %lu KiB.\n",
	147	start, end, size / 1024);
82ad6443	148	ret = i915_gem_gtt_reserve(&ggtt->vm, node,
ff8f7975 WL	149	size, start, I915_COLOR_UNEVICTABLE,
	150	0);
	151	if (!ret)
82ad6443	152	ggtt->vm.reserved += size;
ff8f7975 WL	153
ff8f7975 WL	154	return ret;
5dda8fa3 YZ	155	}
	156
	157	/**
	158	* intel_vgt_balloon - balloon out reserved graphics address trunks
62f90b38	159	* @dev_priv: i915 device private data
5dda8fa3 YZ	160	*
	161	* This function is called at the initialization stage, to balloon out the
	162	* graphic address space allocated to other vGPUs, by marking these spaces as
	163	* reserved. The ballooning related knowledge(starting address and size of
	164	* the mappable/unmappable graphic memory) is described in the vgt_if structure
	165	* in a reserved mmio range.
	166	*
	167	* To give an example, the drawing below depicts one typical scenario after
	168	* ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned
	169	* out each for the mappable and the non-mappable part. From the vGPU1 point of
	170	* view, the total size is the same as the physical one, with the start address
	171	* of its graphic space being zero. Yet there are some portions ballooned out(
	172	* the shadow part, which are marked as reserved by drm allocator). From the
	173	* host point of view, the graphic address space is partitioned by multiple
da5335b8	174	* vGPUs in different VMs. ::
5dda8fa3	175	*
62cacc79 DV	176	* vGPU1 view Host view
	177	* 0 ------> +-----------+ +-----------+
	178	* ^ \|###########\| \| vGPU3 \|
	179	* \| \|###########\| +-----------+
	180	* \| \|###########\| \| vGPU2 \|
	181	* \| +-----------+ +-----------+
	182	* mappable GM \| available \| ==> \| vGPU1 \|
	183	* \| +-----------+ +-----------+
	184	* \| \|###########\| \| \|
	185	* v \|###########\| \| Host \|
	186	* +=======+===========+ +===========+
	187	* ^ \|###########\| \| vGPU3 \|
	188	* \| \|###########\| +-----------+
	189	* \| \|###########\| \| vGPU2 \|
	190	* \| +-----------+ +-----------+
	191	* unmappable GM \| available \| ==> \| vGPU1 \|
	192	* \| +-----------+ +-----------+
	193	* \| \|###########\| \| \|
	194	* \| \|###########\| \| Host \|
	195	* v \|###########\| \| \|
	196	* total GM size ------> +-----------+ +-----------+
5dda8fa3 YZ	197	*
	198	* Returns:
	199	* zero on success, non-zero if configuration invalid or ballooning failed
	200	*/
b02d22a3	201	int intel_vgt_balloon(struct drm_i915_private *dev_priv)
5dda8fa3	202	{
72e96d64	203	struct i915_ggtt *ggtt = &dev_priv->ggtt;
82ad6443	204	unsigned long ggtt_end = ggtt->vm.total;
5dda8fa3 YZ	205
	206	unsigned long mappable_base, mappable_size, mappable_end;
	207	unsigned long unmappable_base, unmappable_size, unmappable_end;
	208	int ret;
	209
b02d22a3 ZW	210	if (!intel_vgpu_active(dev_priv))
	211	return 0;
	212
5dda8fa3 YZ	213	mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
	214	mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
	215	unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
	216	unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
	217
	218	mappable_end = mappable_base + mappable_size;
	219	unmappable_end = unmappable_base + unmappable_size;
	220
	221	DRM_INFO("VGT ballooning configuration:\n");
	222	DRM_INFO("Mappable graphic memory: base 0x%lx size %ldKiB\n",
	223	mappable_base, mappable_size / 1024);
	224	DRM_INFO("Unmappable graphic memory: base 0x%lx size %ldKiB\n",
	225	unmappable_base, unmappable_size / 1024);
	226
381b943b	227	if (mappable_end > ggtt->mappable_end \|\|
72e96d64 JL	228	unmappable_base < ggtt->mappable_end \|\|
72e96d64 JL	229	unmappable_end > ggtt_end) {
5dda8fa3 YZ	230	DRM_ERROR("Invalid ballooning configuration!\n");
	231	return -EINVAL;
	232	}
	233
	234	/* Unmappable graphic memory ballooning */
72e96d64	235	if (unmappable_base > ggtt->mappable_end) {
625d988a CW	236	ret = vgt_balloon_space(ggtt, &bl_info.space[2],
625d988a CW	237	ggtt->mappable_end, unmappable_base);
5dda8fa3 YZ	238
	239	if (ret)
	240	goto err;
	241	}
	242
fa7e8b55	243	if (unmappable_end < ggtt_end) {
625d988a	244	ret = vgt_balloon_space(ggtt, &bl_info.space[3],
fa7e8b55	245	unmappable_end, ggtt_end);
5dda8fa3	246	if (ret)
ff8f7975	247	goto err_upon_mappable;
5dda8fa3 YZ	248	}
	249
	250	/* Mappable graphic memory ballooning */
381b943b	251	if (mappable_base) {
625d988a	252	ret = vgt_balloon_space(ggtt, &bl_info.space[0],
381b943b	253	0, mappable_base);
5dda8fa3 YZ	254
5dda8fa3 YZ	255	if (ret)
ff8f7975	256	goto err_upon_unmappable;
5dda8fa3 YZ	257	}
5dda8fa3 YZ	258
72e96d64	259	if (mappable_end < ggtt->mappable_end) {
625d988a CW	260	ret = vgt_balloon_space(ggtt, &bl_info.space[1],
625d988a CW	261	mappable_end, ggtt->mappable_end);
5dda8fa3 YZ	262
5dda8fa3 YZ	263	if (ret)
ff8f7975	264	goto err_below_mappable;
5dda8fa3 YZ	265	}
	266
	267	DRM_INFO("VGT balloon successfully\n");
	268	return 0;
	269
ff8f7975 WL	270	err_below_mappable:
	271	vgt_deballoon_space(ggtt, &bl_info.space[0]);
	272	err_upon_unmappable:
	273	vgt_deballoon_space(ggtt, &bl_info.space[3]);
	274	err_upon_mappable:
	275	vgt_deballoon_space(ggtt, &bl_info.space[2]);
5dda8fa3 YZ	276	err:
5dda8fa3 YZ	277	DRM_ERROR("VGT balloon fail\n");
5dda8fa3 YZ	278	return ret;
5dda8fa3 YZ	279	}