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05235c53 CW |
1 | /* |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
b52992c0 | 25 | #include <linux/dma-fence-array.h> |
3136deb7 | 26 | #include <linux/dma-fence-chain.h> |
e8861964 CW |
27 | #include <linux/irq_work.h> |
28 | #include <linux/prefetch.h> | |
e6017571 IM |
29 | #include <linux/sched.h> |
30 | #include <linux/sched/clock.h> | |
f361bf4a | 31 | #include <linux/sched/signal.h> |
fa545cbf | 32 | |
10be98a7 | 33 | #include "gem/i915_gem_context.h" |
b3786b29 | 34 | #include "gt/intel_breadcrumbs.h" |
10be98a7 | 35 | #include "gt/intel_context.h" |
45233ab2 | 36 | #include "gt/intel_gpu_commands.h" |
2871ea85 | 37 | #include "gt/intel_ring.h" |
3e7abf81 | 38 | #include "gt/intel_rps.h" |
10be98a7 | 39 | |
21950ee7 | 40 | #include "i915_active.h" |
696173b0 | 41 | #include "i915_drv.h" |
103b76ee | 42 | #include "i915_globals.h" |
a09d9a80 | 43 | #include "i915_trace.h" |
696173b0 | 44 | #include "intel_pm.h" |
05235c53 | 45 | |
e8861964 | 46 | struct execute_cb { |
e8861964 CW |
47 | struct irq_work work; |
48 | struct i915_sw_fence *fence; | |
f71e01a7 CW |
49 | void (*hook)(struct i915_request *rq, struct dma_fence *signal); |
50 | struct i915_request *signal; | |
e8861964 CW |
51 | }; |
52 | ||
32eb6bcf | 53 | static struct i915_global_request { |
103b76ee | 54 | struct i915_global base; |
32eb6bcf | 55 | struct kmem_cache *slab_requests; |
e8861964 | 56 | struct kmem_cache *slab_execute_cbs; |
32eb6bcf CW |
57 | } global; |
58 | ||
f54d1867 | 59 | static const char *i915_fence_get_driver_name(struct dma_fence *fence) |
04769652 | 60 | { |
5a833995 | 61 | return dev_name(to_request(fence)->engine->i915->drm.dev); |
04769652 CW |
62 | } |
63 | ||
f54d1867 | 64 | static const char *i915_fence_get_timeline_name(struct dma_fence *fence) |
04769652 | 65 | { |
9f3ccd40 CW |
66 | const struct i915_gem_context *ctx; |
67 | ||
e61e0f51 CW |
68 | /* |
69 | * The timeline struct (as part of the ppgtt underneath a context) | |
05506b5b CW |
70 | * may be freed when the request is no longer in use by the GPU. |
71 | * We could extend the life of a context to beyond that of all | |
72 | * fences, possibly keeping the hw resource around indefinitely, | |
73 | * or we just give them a false name. Since | |
74 | * dma_fence_ops.get_timeline_name is a debug feature, the occasional | |
75 | * lie seems justifiable. | |
76 | */ | |
77 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
78 | return "signaled"; | |
79 | ||
6a8679c0 | 80 | ctx = i915_request_gem_context(to_request(fence)); |
9f3ccd40 CW |
81 | if (!ctx) |
82 | return "[" DRIVER_NAME "]"; | |
83 | ||
84 | return ctx->name; | |
04769652 CW |
85 | } |
86 | ||
f54d1867 | 87 | static bool i915_fence_signaled(struct dma_fence *fence) |
04769652 | 88 | { |
e61e0f51 | 89 | return i915_request_completed(to_request(fence)); |
04769652 CW |
90 | } |
91 | ||
f54d1867 | 92 | static bool i915_fence_enable_signaling(struct dma_fence *fence) |
04769652 | 93 | { |
52c0fdb2 | 94 | return i915_request_enable_breadcrumb(to_request(fence)); |
04769652 CW |
95 | } |
96 | ||
f54d1867 | 97 | static signed long i915_fence_wait(struct dma_fence *fence, |
04769652 | 98 | bool interruptible, |
e95433c7 | 99 | signed long timeout) |
04769652 | 100 | { |
62eb3c24 CW |
101 | return i915_request_wait(to_request(fence), |
102 | interruptible | I915_WAIT_PRIORITY, | |
103 | timeout); | |
04769652 CW |
104 | } |
105 | ||
43acd651 CW |
106 | struct kmem_cache *i915_request_slab_cache(void) |
107 | { | |
108 | return global.slab_requests; | |
109 | } | |
110 | ||
f54d1867 | 111 | static void i915_fence_release(struct dma_fence *fence) |
04769652 | 112 | { |
e61e0f51 | 113 | struct i915_request *rq = to_request(fence); |
04769652 | 114 | |
e61e0f51 CW |
115 | /* |
116 | * The request is put onto a RCU freelist (i.e. the address | |
fc158405 CW |
117 | * is immediately reused), mark the fences as being freed now. |
118 | * Otherwise the debugobjects for the fences are only marked as | |
119 | * freed when the slab cache itself is freed, and so we would get | |
120 | * caught trying to reuse dead objects. | |
121 | */ | |
e61e0f51 | 122 | i915_sw_fence_fini(&rq->submit); |
0c441cb6 | 123 | i915_sw_fence_fini(&rq->semaphore); |
fc158405 | 124 | |
32a4605b CW |
125 | /* |
126 | * Keep one request on each engine for reserved use under mempressure | |
127 | * | |
128 | * We do not hold a reference to the engine here and so have to be | |
129 | * very careful in what rq->engine we poke. The virtual engine is | |
130 | * referenced via the rq->context and we released that ref during | |
131 | * i915_request_retire(), ergo we must not dereference a virtual | |
132 | * engine here. Not that we would want to, as the only consumer of | |
133 | * the reserved engine->request_pool is the power management parking, | |
134 | * which must-not-fail, and that is only run on the physical engines. | |
135 | * | |
136 | * Since the request must have been executed to be have completed, | |
137 | * we know that it will have been processed by the HW and will | |
138 | * not be unsubmitted again, so rq->engine and rq->execution_mask | |
139 | * at this point is stable. rq->execution_mask will be a single | |
140 | * bit if the last and _only_ engine it could execution on was a | |
141 | * physical engine, if it's multiple bits then it started on and | |
142 | * could still be on a virtual engine. Thus if the mask is not a | |
143 | * power-of-two we assume that rq->engine may still be a virtual | |
144 | * engine and so a dangling invalid pointer that we cannot dereference | |
145 | * | |
146 | * For example, consider the flow of a bonded request through a virtual | |
147 | * engine. The request is created with a wide engine mask (all engines | |
148 | * that we might execute on). On processing the bond, the request mask | |
149 | * is reduced to one or more engines. If the request is subsequently | |
150 | * bound to a single engine, it will then be constrained to only | |
151 | * execute on that engine and never returned to the virtual engine | |
152 | * after timeslicing away, see __unwind_incomplete_requests(). Thus we | |
153 | * know that if the rq->execution_mask is a single bit, rq->engine | |
154 | * can be a physical engine with the exact corresponding mask. | |
155 | */ | |
156 | if (is_power_of_2(rq->execution_mask) && | |
157 | !cmpxchg(&rq->engine->request_pool, NULL, rq)) | |
43acd651 CW |
158 | return; |
159 | ||
32eb6bcf | 160 | kmem_cache_free(global.slab_requests, rq); |
04769652 CW |
161 | } |
162 | ||
f54d1867 | 163 | const struct dma_fence_ops i915_fence_ops = { |
04769652 CW |
164 | .get_driver_name = i915_fence_get_driver_name, |
165 | .get_timeline_name = i915_fence_get_timeline_name, | |
166 | .enable_signaling = i915_fence_enable_signaling, | |
167 | .signaled = i915_fence_signaled, | |
168 | .wait = i915_fence_wait, | |
169 | .release = i915_fence_release, | |
04769652 CW |
170 | }; |
171 | ||
b87b6c0d CW |
172 | static void irq_execute_cb(struct irq_work *wrk) |
173 | { | |
174 | struct execute_cb *cb = container_of(wrk, typeof(*cb), work); | |
175 | ||
176 | i915_sw_fence_complete(cb->fence); | |
177 | kmem_cache_free(global.slab_execute_cbs, cb); | |
178 | } | |
179 | ||
180 | static void irq_execute_cb_hook(struct irq_work *wrk) | |
181 | { | |
182 | struct execute_cb *cb = container_of(wrk, typeof(*cb), work); | |
183 | ||
184 | cb->hook(container_of(cb->fence, struct i915_request, submit), | |
185 | &cb->signal->fence); | |
186 | i915_request_put(cb->signal); | |
187 | ||
188 | irq_execute_cb(wrk); | |
189 | } | |
190 | ||
2e4c6c1a CW |
191 | static __always_inline void |
192 | __notify_execute_cb(struct i915_request *rq, bool (*fn)(struct irq_work *wrk)) | |
b87b6c0d | 193 | { |
fc0e1270 | 194 | struct execute_cb *cb, *cn; |
b87b6c0d | 195 | |
fc0e1270 | 196 | if (llist_empty(&rq->execute_cb)) |
b87b6c0d CW |
197 | return; |
198 | ||
2e4c6c1a CW |
199 | llist_for_each_entry_safe(cb, cn, |
200 | llist_del_all(&rq->execute_cb), | |
7a9f50a0 | 201 | work.node.llist) |
2e4c6c1a CW |
202 | fn(&cb->work); |
203 | } | |
b87b6c0d | 204 | |
2e4c6c1a CW |
205 | static void __notify_execute_cb_irq(struct i915_request *rq) |
206 | { | |
207 | __notify_execute_cb(rq, irq_work_queue); | |
208 | } | |
209 | ||
210 | static bool irq_work_imm(struct irq_work *wrk) | |
211 | { | |
212 | wrk->func(wrk); | |
213 | return false; | |
214 | } | |
215 | ||
216 | static void __notify_execute_cb_imm(struct i915_request *rq) | |
217 | { | |
218 | __notify_execute_cb(rq, irq_work_imm); | |
b87b6c0d CW |
219 | } |
220 | ||
e61e0f51 | 221 | static void free_capture_list(struct i915_request *request) |
b0fd47ad | 222 | { |
e61e0f51 | 223 | struct i915_capture_list *capture; |
b0fd47ad | 224 | |
67a3acaa | 225 | capture = fetch_and_zero(&request->capture_list); |
b0fd47ad | 226 | while (capture) { |
e61e0f51 | 227 | struct i915_capture_list *next = capture->next; |
b0fd47ad CW |
228 | |
229 | kfree(capture); | |
230 | capture = next; | |
231 | } | |
232 | } | |
233 | ||
89dd019a CW |
234 | static void __i915_request_fill(struct i915_request *rq, u8 val) |
235 | { | |
236 | void *vaddr = rq->ring->vaddr; | |
237 | u32 head; | |
238 | ||
239 | head = rq->infix; | |
240 | if (rq->postfix < head) { | |
241 | memset(vaddr + head, val, rq->ring->size - head); | |
242 | head = 0; | |
243 | } | |
244 | memset(vaddr + head, val, rq->postfix - head); | |
245 | } | |
246 | ||
37fa0de3 CW |
247 | static void remove_from_engine(struct i915_request *rq) |
248 | { | |
249 | struct intel_engine_cs *engine, *locked; | |
250 | ||
251 | /* | |
252 | * Virtual engines complicate acquiring the engine timeline lock, | |
253 | * as their rq->engine pointer is not stable until under that | |
254 | * engine lock. The simple ploy we use is to take the lock then | |
255 | * check that the rq still belongs to the newly locked engine. | |
256 | */ | |
257 | locked = READ_ONCE(rq->engine); | |
1dfffa00 | 258 | spin_lock_irq(&locked->active.lock); |
37fa0de3 CW |
259 | while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) { |
260 | spin_unlock(&locked->active.lock); | |
261 | spin_lock(&engine->active.lock); | |
262 | locked = engine; | |
263 | } | |
67a3acaa | 264 | list_del_init(&rq->sched.link); |
2e4c6c1a | 265 | |
b4a9a149 CW |
266 | clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); |
267 | clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags); | |
2e4c6c1a CW |
268 | |
269 | /* Prevent further __await_execution() registering a cb, then flush */ | |
270 | set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags); | |
271 | ||
1dfffa00 | 272 | spin_unlock_irq(&locked->active.lock); |
2e4c6c1a CW |
273 | |
274 | __notify_execute_cb_imm(rq); | |
37fa0de3 CW |
275 | } |
276 | ||
66101975 | 277 | bool i915_request_retire(struct i915_request *rq) |
05235c53 | 278 | { |
9db0c5ca CW |
279 | if (!i915_request_completed(rq)) |
280 | return false; | |
d9b13c4d | 281 | |
639f2f24 | 282 | RQ_TRACE(rq, "\n"); |
4c7d62c6 | 283 | |
9db0c5ca CW |
284 | GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); |
285 | trace_i915_request_retire(rq); | |
2e4c6c1a | 286 | i915_request_mark_complete(rq); |
80b204bc | 287 | |
e5dadff4 CW |
288 | /* |
289 | * We know the GPU must have read the request to have | |
290 | * sent us the seqno + interrupt, so use the position | |
291 | * of tail of the request to update the last known position | |
292 | * of the GPU head. | |
293 | * | |
294 | * Note this requires that we are always called in request | |
295 | * completion order. | |
296 | */ | |
d19d71fc CW |
297 | GEM_BUG_ON(!list_is_first(&rq->link, |
298 | &i915_request_timeline(rq)->requests)); | |
89dd019a CW |
299 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) |
300 | /* Poison before we release our space in the ring */ | |
301 | __i915_request_fill(rq, POISON_FREE); | |
e5dadff4 | 302 | rq->ring->head = rq->postfix; |
b0fd47ad | 303 | |
e2300560 CW |
304 | if (!i915_request_signaled(rq)) { |
305 | spin_lock_irq(&rq->lock); | |
9db0c5ca | 306 | dma_fence_signal_locked(&rq->fence); |
e2300560 CW |
307 | spin_unlock_irq(&rq->lock); |
308 | } | |
c18636f7 | 309 | |
4e5c8a99 | 310 | if (test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags)) |
3e7abf81 | 311 | atomic_dec(&rq->engine->gt->rps.num_waiters); |
c18636f7 CW |
312 | |
313 | /* | |
314 | * We only loosely track inflight requests across preemption, | |
315 | * and so we may find ourselves attempting to retire a _completed_ | |
316 | * request that we have removed from the HW and put back on a run | |
317 | * queue. | |
318 | * | |
319 | * As we set I915_FENCE_FLAG_ACTIVE on the request, this should be | |
320 | * after removing the breadcrumb and signaling it, so that we do not | |
321 | * inadvertently attach the breadcrumb to a completed request. | |
322 | */ | |
b8e2bd98 CW |
323 | if (!list_empty(&rq->sched.link)) |
324 | remove_from_engine(rq); | |
fc0e1270 | 325 | GEM_BUG_ON(!llist_empty(&rq->execute_cb)); |
52d7f16e | 326 | |
dff2a11b | 327 | __list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */ |
9db0c5ca | 328 | |
9f3ccd40 CW |
329 | intel_context_exit(rq->context); |
330 | intel_context_unpin(rq->context); | |
75d0a7f3 | 331 | |
9db0c5ca CW |
332 | free_capture_list(rq); |
333 | i915_sched_node_fini(&rq->sched); | |
334 | i915_request_put(rq); | |
335 | ||
336 | return true; | |
05235c53 CW |
337 | } |
338 | ||
e61e0f51 | 339 | void i915_request_retire_upto(struct i915_request *rq) |
05235c53 | 340 | { |
d19d71fc | 341 | struct intel_timeline * const tl = i915_request_timeline(rq); |
e61e0f51 | 342 | struct i915_request *tmp; |
05235c53 | 343 | |
639f2f24 | 344 | RQ_TRACE(rq, "\n"); |
b887d615 | 345 | |
e61e0f51 | 346 | GEM_BUG_ON(!i915_request_completed(rq)); |
4ffd6e0c | 347 | |
05235c53 | 348 | do { |
e5dadff4 | 349 | tmp = list_first_entry(&tl->requests, typeof(*tmp), link); |
9db0c5ca | 350 | } while (i915_request_retire(tmp) && tmp != rq); |
05235c53 CW |
351 | } |
352 | ||
b55230e5 CW |
353 | static struct i915_request * const * |
354 | __engine_active(struct intel_engine_cs *engine) | |
355 | { | |
356 | return READ_ONCE(engine->execlists.active); | |
357 | } | |
358 | ||
359 | static bool __request_in_flight(const struct i915_request *signal) | |
360 | { | |
361 | struct i915_request * const *port, *rq; | |
362 | bool inflight = false; | |
363 | ||
364 | if (!i915_request_is_ready(signal)) | |
365 | return false; | |
366 | ||
367 | /* | |
368 | * Even if we have unwound the request, it may still be on | |
369 | * the GPU (preempt-to-busy). If that request is inside an | |
370 | * unpreemptible critical section, it will not be removed. Some | |
371 | * GPU functions may even be stuck waiting for the paired request | |
372 | * (__await_execution) to be submitted and cannot be preempted | |
373 | * until the bond is executing. | |
374 | * | |
375 | * As we know that there are always preemption points between | |
376 | * requests, we know that only the currently executing request | |
377 | * may be still active even though we have cleared the flag. | |
b4d9145b | 378 | * However, we can't rely on our tracking of ELSP[0] to know |
b55230e5 CW |
379 | * which request is currently active and so maybe stuck, as |
380 | * the tracking maybe an event behind. Instead assume that | |
381 | * if the context is still inflight, then it is still active | |
382 | * even if the active flag has been cleared. | |
b4d9145b CW |
383 | * |
384 | * To further complicate matters, if there a pending promotion, the HW | |
385 | * may either perform a context switch to the second inflight execlists, | |
386 | * or it may switch to the pending set of execlists. In the case of the | |
387 | * latter, it may send the ACK and we process the event copying the | |
388 | * pending[] over top of inflight[], _overwriting_ our *active. Since | |
389 | * this implies the HW is arbitrating and not struck in *active, we do | |
390 | * not worry about complete accuracy, but we do require no read/write | |
391 | * tearing of the pointer [the read of the pointer must be valid, even | |
392 | * as the array is being overwritten, for which we require the writes | |
393 | * to avoid tearing.] | |
394 | * | |
395 | * Note that the read of *execlists->active may race with the promotion | |
396 | * of execlists->pending[] to execlists->inflight[], overwritting | |
397 | * the value at *execlists->active. This is fine. The promotion implies | |
398 | * that we received an ACK from the HW, and so the context is not | |
399 | * stuck -- if we do not see ourselves in *active, the inflight status | |
400 | * is valid. If instead we see ourselves being copied into *active, | |
401 | * we are inflight and may signal the callback. | |
b55230e5 CW |
402 | */ |
403 | if (!intel_context_inflight(signal->context)) | |
404 | return false; | |
405 | ||
406 | rcu_read_lock(); | |
b4d9145b CW |
407 | for (port = __engine_active(signal->engine); |
408 | (rq = READ_ONCE(*port)); /* may race with promotion of pending[] */ | |
409 | port++) { | |
b55230e5 CW |
410 | if (rq->context == signal->context) { |
411 | inflight = i915_seqno_passed(rq->fence.seqno, | |
412 | signal->fence.seqno); | |
413 | break; | |
414 | } | |
415 | } | |
416 | rcu_read_unlock(); | |
417 | ||
418 | return inflight; | |
419 | } | |
420 | ||
e8861964 | 421 | static int |
c81471f5 CW |
422 | __await_execution(struct i915_request *rq, |
423 | struct i915_request *signal, | |
424 | void (*hook)(struct i915_request *rq, | |
425 | struct dma_fence *signal), | |
426 | gfp_t gfp) | |
e8861964 CW |
427 | { |
428 | struct execute_cb *cb; | |
429 | ||
f71e01a7 CW |
430 | if (i915_request_is_active(signal)) { |
431 | if (hook) | |
432 | hook(rq, &signal->fence); | |
e8861964 | 433 | return 0; |
f71e01a7 | 434 | } |
e8861964 CW |
435 | |
436 | cb = kmem_cache_alloc(global.slab_execute_cbs, gfp); | |
437 | if (!cb) | |
438 | return -ENOMEM; | |
439 | ||
440 | cb->fence = &rq->submit; | |
441 | i915_sw_fence_await(cb->fence); | |
442 | init_irq_work(&cb->work, irq_execute_cb); | |
443 | ||
f71e01a7 CW |
444 | if (hook) { |
445 | cb->hook = hook; | |
446 | cb->signal = i915_request_get(signal); | |
447 | cb->work.func = irq_execute_cb_hook; | |
448 | } | |
449 | ||
2e4c6c1a CW |
450 | /* |
451 | * Register the callback first, then see if the signaler is already | |
452 | * active. This ensures that if we race with the | |
453 | * __notify_execute_cb from i915_request_submit() and we are not | |
454 | * included in that list, we get a second bite of the cherry and | |
455 | * execute it ourselves. After this point, a future | |
456 | * i915_request_submit() will notify us. | |
457 | * | |
458 | * In i915_request_retire() we set the ACTIVE bit on a completed | |
459 | * request (then flush the execute_cb). So by registering the | |
460 | * callback first, then checking the ACTIVE bit, we serialise with | |
461 | * the completed/retired request. | |
462 | */ | |
7a9f50a0 | 463 | if (llist_add(&cb->work.node.llist, &signal->execute_cb)) { |
2e4c6c1a CW |
464 | if (i915_request_is_active(signal) || |
465 | __request_in_flight(signal)) | |
466 | __notify_execute_cb_imm(signal); | |
e8861964 | 467 | } |
e8861964 CW |
468 | |
469 | return 0; | |
470 | } | |
471 | ||
36e191f0 CW |
472 | static bool fatal_error(int error) |
473 | { | |
474 | switch (error) { | |
475 | case 0: /* not an error! */ | |
476 | case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */ | |
477 | case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */ | |
478 | return false; | |
479 | default: | |
480 | return true; | |
481 | } | |
482 | } | |
483 | ||
484 | void __i915_request_skip(struct i915_request *rq) | |
485 | { | |
486 | GEM_BUG_ON(!fatal_error(rq->fence.error)); | |
487 | ||
488 | if (rq->infix == rq->postfix) | |
489 | return; | |
490 | ||
7904e081 CW |
491 | RQ_TRACE(rq, "error: %d\n", rq->fence.error); |
492 | ||
36e191f0 CW |
493 | /* |
494 | * As this request likely depends on state from the lost | |
495 | * context, clear out all the user operations leaving the | |
496 | * breadcrumb at the end (so we get the fence notifications). | |
497 | */ | |
498 | __i915_request_fill(rq, 0); | |
499 | rq->infix = rq->postfix; | |
500 | } | |
501 | ||
502 | void i915_request_set_error_once(struct i915_request *rq, int error) | |
503 | { | |
504 | int old; | |
505 | ||
506 | GEM_BUG_ON(!IS_ERR_VALUE((long)error)); | |
507 | ||
508 | if (i915_request_signaled(rq)) | |
509 | return; | |
510 | ||
511 | old = READ_ONCE(rq->fence.error); | |
512 | do { | |
513 | if (fatal_error(old)) | |
514 | return; | |
515 | } while (!try_cmpxchg(&rq->fence.error, &old, error)); | |
516 | } | |
517 | ||
baa7c2cd CW |
518 | void i915_request_mark_eio(struct i915_request *rq) |
519 | { | |
520 | if (__i915_request_is_complete(rq)) | |
521 | return; | |
522 | ||
523 | GEM_BUG_ON(i915_request_signaled(rq)); | |
524 | ||
525 | i915_request_set_error_once(rq, -EIO); | |
526 | i915_request_mark_complete(rq); | |
527 | } | |
528 | ||
c0bb487d | 529 | bool __i915_request_submit(struct i915_request *request) |
5590af3e | 530 | { |
73cb9701 | 531 | struct intel_engine_cs *engine = request->engine; |
c0bb487d | 532 | bool result = false; |
5590af3e | 533 | |
639f2f24 | 534 | RQ_TRACE(request, "\n"); |
d9b13c4d | 535 | |
e60a870d | 536 | GEM_BUG_ON(!irqs_disabled()); |
422d7df4 | 537 | lockdep_assert_held(&engine->active.lock); |
e60a870d | 538 | |
c0bb487d CW |
539 | /* |
540 | * With the advent of preempt-to-busy, we frequently encounter | |
541 | * requests that we have unsubmitted from HW, but left running | |
542 | * until the next ack and so have completed in the meantime. On | |
543 | * resubmission of that completed request, we can skip | |
544 | * updating the payload, and execlists can even skip submitting | |
545 | * the request. | |
546 | * | |
547 | * We must remove the request from the caller's priority queue, | |
548 | * and the caller must only call us when the request is in their | |
549 | * priority queue, under the active.lock. This ensures that the | |
550 | * request has *not* yet been retired and we can safely move | |
551 | * the request into the engine->active.list where it will be | |
552 | * dropped upon retiring. (Otherwise if resubmit a *retired* | |
553 | * request, this would be a horrible use-after-free.) | |
554 | */ | |
555 | if (i915_request_completed(request)) | |
556 | goto xfer; | |
557 | ||
36e191f0 CW |
558 | if (unlikely(intel_context_is_banned(request->context))) |
559 | i915_request_set_error_once(request, -EIO); | |
7d442ea7 | 560 | |
36e191f0 CW |
561 | if (unlikely(fatal_error(request->fence.error))) |
562 | __i915_request_skip(request); | |
d9e61b66 | 563 | |
ca6e56f6 CW |
564 | /* |
565 | * Are we using semaphores when the gpu is already saturated? | |
566 | * | |
567 | * Using semaphores incurs a cost in having the GPU poll a | |
568 | * memory location, busywaiting for it to change. The continual | |
569 | * memory reads can have a noticeable impact on the rest of the | |
570 | * system with the extra bus traffic, stalling the cpu as it too | |
571 | * tries to access memory across the bus (perf stat -e bus-cycles). | |
572 | * | |
573 | * If we installed a semaphore on this request and we only submit | |
574 | * the request after the signaler completed, that indicates the | |
575 | * system is overloaded and using semaphores at this time only | |
576 | * increases the amount of work we are doing. If so, we disable | |
577 | * further use of semaphores until we are idle again, whence we | |
578 | * optimistically try again. | |
579 | */ | |
580 | if (request->sched.semaphores && | |
581 | i915_sw_fence_signaled(&request->semaphore)) | |
44d89409 | 582 | engine->saturated |= request->sched.semaphores; |
ca6e56f6 | 583 | |
c0bb487d CW |
584 | engine->emit_fini_breadcrumb(request, |
585 | request->ring->vaddr + request->postfix); | |
b5773a36 | 586 | |
c0bb487d CW |
587 | trace_i915_request_execute(request); |
588 | engine->serial++; | |
589 | result = true; | |
422d7df4 | 590 | |
1d9221e9 | 591 | xfer: |
672c368f | 592 | if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)) { |
c0bb487d | 593 | list_move_tail(&request->sched.link, &engine->active.requests); |
672c368f CW |
594 | clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags); |
595 | } | |
b5773a36 | 596 | |
c18636f7 CW |
597 | /* |
598 | * XXX Rollback bonded-execution on __i915_request_unsubmit()? | |
599 | * | |
600 | * In the future, perhaps when we have an active time-slicing scheduler, | |
601 | * it will be interesting to unsubmit parallel execution and remove | |
602 | * busywaits from the GPU until their master is restarted. This is | |
603 | * quite hairy, we have to carefully rollback the fence and do a | |
604 | * preempt-to-idle cycle on the target engine, all the while the | |
605 | * master execute_cb may refire. | |
606 | */ | |
2e4c6c1a CW |
607 | __notify_execute_cb_irq(request); |
608 | ||
609 | /* We may be recursing from the signal callback of another i915 fence */ | |
5701a66e CW |
610 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) |
611 | i915_request_enable_breadcrumb(request); | |
f2d13290 | 612 | |
c0bb487d | 613 | return result; |
d55ac5bf CW |
614 | } |
615 | ||
e61e0f51 | 616 | void i915_request_submit(struct i915_request *request) |
d55ac5bf CW |
617 | { |
618 | struct intel_engine_cs *engine = request->engine; | |
619 | unsigned long flags; | |
23902e49 | 620 | |
d55ac5bf | 621 | /* Will be called from irq-context when using foreign fences. */ |
422d7df4 | 622 | spin_lock_irqsave(&engine->active.lock, flags); |
d55ac5bf | 623 | |
e61e0f51 | 624 | __i915_request_submit(request); |
d55ac5bf | 625 | |
422d7df4 | 626 | spin_unlock_irqrestore(&engine->active.lock, flags); |
d55ac5bf CW |
627 | } |
628 | ||
e61e0f51 | 629 | void __i915_request_unsubmit(struct i915_request *request) |
d55ac5bf | 630 | { |
d6a2289d | 631 | struct intel_engine_cs *engine = request->engine; |
d55ac5bf | 632 | |
c18636f7 CW |
633 | /* |
634 | * Only unwind in reverse order, required so that the per-context list | |
635 | * is kept in seqno/ring order. | |
636 | */ | |
639f2f24 | 637 | RQ_TRACE(request, "\n"); |
d9b13c4d | 638 | |
e60a870d | 639 | GEM_BUG_ON(!irqs_disabled()); |
422d7df4 | 640 | lockdep_assert_held(&engine->active.lock); |
48bc2a4a | 641 | |
e61e0f51 | 642 | /* |
c18636f7 CW |
643 | * Before we remove this breadcrumb from the signal list, we have |
644 | * to ensure that a concurrent dma_fence_enable_signaling() does not | |
645 | * attach itself. We first mark the request as no longer active and | |
646 | * make sure that is visible to other cores, and then remove the | |
647 | * breadcrumb if attached. | |
d6a2289d | 648 | */ |
c18636f7 CW |
649 | GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)); |
650 | clear_bit_unlock(I915_FENCE_FLAG_ACTIVE, &request->fence.flags); | |
d6a2289d | 651 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) |
52c0fdb2 | 652 | i915_request_cancel_breadcrumb(request); |
b5773a36 | 653 | |
dba5a7f3 | 654 | /* We've already spun, don't charge on resubmitting. */ |
18e4af04 | 655 | if (request->sched.semaphores && i915_request_started(request)) |
dba5a7f3 | 656 | request->sched.semaphores = 0; |
dba5a7f3 | 657 | |
e61e0f51 CW |
658 | /* |
659 | * We don't need to wake_up any waiters on request->execute, they | |
d6a2289d | 660 | * will get woken by any other event or us re-adding this request |
e61e0f51 | 661 | * to the engine timeline (__i915_request_submit()). The waiters |
d6a2289d CW |
662 | * should be quite adapt at finding that the request now has a new |
663 | * global_seqno to the one they went to sleep on. | |
664 | */ | |
665 | } | |
666 | ||
e61e0f51 | 667 | void i915_request_unsubmit(struct i915_request *request) |
d6a2289d CW |
668 | { |
669 | struct intel_engine_cs *engine = request->engine; | |
670 | unsigned long flags; | |
671 | ||
672 | /* Will be called from irq-context when using foreign fences. */ | |
422d7df4 | 673 | spin_lock_irqsave(&engine->active.lock, flags); |
d6a2289d | 674 | |
e61e0f51 | 675 | __i915_request_unsubmit(request); |
d6a2289d | 676 | |
422d7df4 | 677 | spin_unlock_irqrestore(&engine->active.lock, flags); |
5590af3e CW |
678 | } |
679 | ||
23902e49 | 680 | static int __i915_sw_fence_call |
d55ac5bf | 681 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
23902e49 | 682 | { |
e61e0f51 | 683 | struct i915_request *request = |
48bc2a4a | 684 | container_of(fence, typeof(*request), submit); |
48bc2a4a CW |
685 | |
686 | switch (state) { | |
687 | case FENCE_COMPLETE: | |
e61e0f51 | 688 | trace_i915_request_submit(request); |
ef468849 CW |
689 | |
690 | if (unlikely(fence->error)) | |
36e191f0 | 691 | i915_request_set_error_once(request, fence->error); |
ef468849 | 692 | |
af7a8ffa | 693 | /* |
e61e0f51 CW |
694 | * We need to serialize use of the submit_request() callback |
695 | * with its hotplugging performed during an emergency | |
696 | * i915_gem_set_wedged(). We use the RCU mechanism to mark the | |
697 | * critical section in order to force i915_gem_set_wedged() to | |
698 | * wait until the submit_request() is completed before | |
699 | * proceeding. | |
af7a8ffa DV |
700 | */ |
701 | rcu_read_lock(); | |
d55ac5bf | 702 | request->engine->submit_request(request); |
af7a8ffa | 703 | rcu_read_unlock(); |
48bc2a4a CW |
704 | break; |
705 | ||
706 | case FENCE_FREE: | |
e61e0f51 | 707 | i915_request_put(request); |
48bc2a4a CW |
708 | break; |
709 | } | |
710 | ||
23902e49 CW |
711 | return NOTIFY_DONE; |
712 | } | |
713 | ||
b7404c7e CW |
714 | static int __i915_sw_fence_call |
715 | semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) | |
716 | { | |
209df10b | 717 | struct i915_request *rq = container_of(fence, typeof(*rq), semaphore); |
b7404c7e CW |
718 | |
719 | switch (state) { | |
720 | case FENCE_COMPLETE: | |
b7404c7e CW |
721 | break; |
722 | ||
723 | case FENCE_FREE: | |
209df10b | 724 | i915_request_put(rq); |
b7404c7e CW |
725 | break; |
726 | } | |
727 | ||
728 | return NOTIFY_DONE; | |
729 | } | |
730 | ||
e5dadff4 | 731 | static void retire_requests(struct intel_timeline *tl) |
d22ba0cb CW |
732 | { |
733 | struct i915_request *rq, *rn; | |
734 | ||
e5dadff4 | 735 | list_for_each_entry_safe(rq, rn, &tl->requests, link) |
9db0c5ca | 736 | if (!i915_request_retire(rq)) |
d22ba0cb | 737 | break; |
d22ba0cb CW |
738 | } |
739 | ||
740 | static noinline struct i915_request * | |
43acd651 CW |
741 | request_alloc_slow(struct intel_timeline *tl, |
742 | struct i915_request **rsvd, | |
743 | gfp_t gfp) | |
d22ba0cb | 744 | { |
d22ba0cb CW |
745 | struct i915_request *rq; |
746 | ||
43acd651 CW |
747 | /* If we cannot wait, dip into our reserves */ |
748 | if (!gfpflags_allow_blocking(gfp)) { | |
749 | rq = xchg(rsvd, NULL); | |
750 | if (!rq) /* Use the normal failure path for one final WARN */ | |
751 | goto out; | |
d22ba0cb | 752 | |
43acd651 CW |
753 | return rq; |
754 | } | |
755 | ||
756 | if (list_empty(&tl->requests)) | |
2ccdf6a1 CW |
757 | goto out; |
758 | ||
9db0c5ca | 759 | /* Move our oldest request to the slab-cache (if not in use!) */ |
e5dadff4 | 760 | rq = list_first_entry(&tl->requests, typeof(*rq), link); |
9db0c5ca CW |
761 | i915_request_retire(rq); |
762 | ||
763 | rq = kmem_cache_alloc(global.slab_requests, | |
764 | gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); | |
765 | if (rq) | |
766 | return rq; | |
767 | ||
d22ba0cb | 768 | /* Ratelimit ourselves to prevent oom from malicious clients */ |
e5dadff4 | 769 | rq = list_last_entry(&tl->requests, typeof(*rq), link); |
d22ba0cb CW |
770 | cond_synchronize_rcu(rq->rcustate); |
771 | ||
772 | /* Retire our old requests in the hope that we free some */ | |
e5dadff4 | 773 | retire_requests(tl); |
d22ba0cb CW |
774 | |
775 | out: | |
2ccdf6a1 | 776 | return kmem_cache_alloc(global.slab_requests, gfp); |
d22ba0cb CW |
777 | } |
778 | ||
67a3acaa CW |
779 | static void __i915_request_ctor(void *arg) |
780 | { | |
781 | struct i915_request *rq = arg; | |
782 | ||
783 | spin_lock_init(&rq->lock); | |
784 | i915_sched_node_init(&rq->sched); | |
785 | i915_sw_fence_init(&rq->submit, submit_notify); | |
786 | i915_sw_fence_init(&rq->semaphore, semaphore_notify); | |
787 | ||
855e39e6 CW |
788 | dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, 0, 0); |
789 | ||
67a3acaa CW |
790 | rq->capture_list = NULL; |
791 | ||
fc0e1270 | 792 | init_llist_head(&rq->execute_cb); |
67a3acaa CW |
793 | } |
794 | ||
e61e0f51 | 795 | struct i915_request * |
2ccdf6a1 | 796 | __i915_request_create(struct intel_context *ce, gfp_t gfp) |
05235c53 | 797 | { |
75d0a7f3 | 798 | struct intel_timeline *tl = ce->timeline; |
ebece753 CW |
799 | struct i915_request *rq; |
800 | u32 seqno; | |
05235c53 CW |
801 | int ret; |
802 | ||
2ccdf6a1 | 803 | might_sleep_if(gfpflags_allow_blocking(gfp)); |
28176ef4 | 804 | |
2ccdf6a1 CW |
805 | /* Check that the caller provided an already pinned context */ |
806 | __intel_context_pin(ce); | |
9b5f4e5e | 807 | |
e61e0f51 CW |
808 | /* |
809 | * Beware: Dragons be flying overhead. | |
5a198b8c CW |
810 | * |
811 | * We use RCU to look up requests in flight. The lookups may | |
812 | * race with the request being allocated from the slab freelist. | |
813 | * That is the request we are writing to here, may be in the process | |
21950ee7 | 814 | * of being read by __i915_active_request_get_rcu(). As such, |
5a198b8c CW |
815 | * we have to be very careful when overwriting the contents. During |
816 | * the RCU lookup, we change chase the request->engine pointer, | |
65e4760e | 817 | * read the request->global_seqno and increment the reference count. |
5a198b8c CW |
818 | * |
819 | * The reference count is incremented atomically. If it is zero, | |
820 | * the lookup knows the request is unallocated and complete. Otherwise, | |
821 | * it is either still in use, or has been reallocated and reset | |
f54d1867 CW |
822 | * with dma_fence_init(). This increment is safe for release as we |
823 | * check that the request we have a reference to and matches the active | |
5a198b8c CW |
824 | * request. |
825 | * | |
826 | * Before we increment the refcount, we chase the request->engine | |
827 | * pointer. We must not call kmem_cache_zalloc() or else we set | |
828 | * that pointer to NULL and cause a crash during the lookup. If | |
829 | * we see the request is completed (based on the value of the | |
830 | * old engine and seqno), the lookup is complete and reports NULL. | |
831 | * If we decide the request is not completed (new engine or seqno), | |
832 | * then we grab a reference and double check that it is still the | |
833 | * active request - which it won't be and restart the lookup. | |
834 | * | |
835 | * Do not use kmem_cache_zalloc() here! | |
836 | */ | |
32eb6bcf | 837 | rq = kmem_cache_alloc(global.slab_requests, |
2ccdf6a1 | 838 | gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); |
e61e0f51 | 839 | if (unlikely(!rq)) { |
43acd651 | 840 | rq = request_alloc_slow(tl, &ce->engine->request_pool, gfp); |
e61e0f51 | 841 | if (!rq) { |
31c70f97 CW |
842 | ret = -ENOMEM; |
843 | goto err_unreserve; | |
844 | } | |
28176ef4 | 845 | } |
05235c53 | 846 | |
9f3ccd40 | 847 | rq->context = ce; |
2ccdf6a1 | 848 | rq->engine = ce->engine; |
1fc44d9b | 849 | rq->ring = ce->ring; |
89b6d183 | 850 | rq->execution_mask = ce->engine->mask; |
d19d71fc | 851 | |
855e39e6 CW |
852 | kref_init(&rq->fence.refcount); |
853 | rq->fence.flags = 0; | |
854 | rq->fence.error = 0; | |
855 | INIT_LIST_HEAD(&rq->fence.cb_list); | |
856 | ||
857 | ret = intel_timeline_get_seqno(tl, rq, &seqno); | |
858 | if (ret) | |
859 | goto err_free; | |
860 | ||
861 | rq->fence.context = tl->fence_context; | |
862 | rq->fence.seqno = seqno; | |
863 | ||
85bedbf1 CW |
864 | RCU_INIT_POINTER(rq->timeline, tl); |
865 | RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline); | |
ebece753 | 866 | rq->hwsp_seqno = tl->hwsp_seqno; |
1eaa251b | 867 | GEM_BUG_ON(i915_request_completed(rq)); |
d19d71fc | 868 | |
ebece753 | 869 | rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */ |
73cb9701 | 870 | |
48bc2a4a | 871 | /* We bump the ref for the fence chain */ |
67a3acaa CW |
872 | i915_sw_fence_reinit(&i915_request_get(rq)->submit); |
873 | i915_sw_fence_reinit(&i915_request_get(rq)->semaphore); | |
5590af3e | 874 | |
67a3acaa | 875 | i915_sched_node_reinit(&rq->sched); |
52e54209 | 876 | |
67a3acaa | 877 | /* No zalloc, everything must be cleared after use */ |
e61e0f51 | 878 | rq->batch = NULL; |
67a3acaa | 879 | GEM_BUG_ON(rq->capture_list); |
fc0e1270 | 880 | GEM_BUG_ON(!llist_empty(&rq->execute_cb)); |
2ccdf6a1 | 881 | |
05235c53 CW |
882 | /* |
883 | * Reserve space in the ring buffer for all the commands required to | |
884 | * eventually emit this request. This is to guarantee that the | |
e61e0f51 | 885 | * i915_request_add() call can't fail. Note that the reserve may need |
05235c53 CW |
886 | * to be redone if the request is not actually submitted straight |
887 | * away, e.g. because a GPU scheduler has deferred it. | |
ed2922c0 CW |
888 | * |
889 | * Note that due to how we add reserved_space to intel_ring_begin() | |
890 | * we need to double our request to ensure that if we need to wrap | |
891 | * around inside i915_request_add() there is sufficient space at | |
892 | * the beginning of the ring as well. | |
05235c53 | 893 | */ |
2ccdf6a1 CW |
894 | rq->reserved_space = |
895 | 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32); | |
05235c53 | 896 | |
2113184c CW |
897 | /* |
898 | * Record the position of the start of the request so that | |
d045446d CW |
899 | * should we detect the updated seqno part-way through the |
900 | * GPU processing the request, we never over-estimate the | |
901 | * position of the head. | |
902 | */ | |
e61e0f51 | 903 | rq->head = rq->ring->emit; |
d045446d | 904 | |
2ccdf6a1 | 905 | ret = rq->engine->request_alloc(rq); |
b1c24a61 CW |
906 | if (ret) |
907 | goto err_unwind; | |
2113184c | 908 | |
b3ee09a4 CW |
909 | rq->infix = rq->ring->emit; /* end of header; start of user payload */ |
910 | ||
2ccdf6a1 | 911 | intel_context_mark_active(ce); |
d22d2d07 CW |
912 | list_add_tail_rcu(&rq->link, &tl->requests); |
913 | ||
e61e0f51 | 914 | return rq; |
05235c53 | 915 | |
b1c24a61 | 916 | err_unwind: |
1fc44d9b | 917 | ce->ring->emit = rq->head; |
b1c24a61 | 918 | |
1618bdb8 | 919 | /* Make sure we didn't add ourselves to external state before freeing */ |
0c7112a0 CW |
920 | GEM_BUG_ON(!list_empty(&rq->sched.signalers_list)); |
921 | GEM_BUG_ON(!list_empty(&rq->sched.waiters_list)); | |
1618bdb8 | 922 | |
ebece753 | 923 | err_free: |
32eb6bcf | 924 | kmem_cache_free(global.slab_requests, rq); |
28176ef4 | 925 | err_unreserve: |
1fc44d9b | 926 | intel_context_unpin(ce); |
8e637178 | 927 | return ERR_PTR(ret); |
05235c53 CW |
928 | } |
929 | ||
2ccdf6a1 CW |
930 | struct i915_request * |
931 | i915_request_create(struct intel_context *ce) | |
932 | { | |
933 | struct i915_request *rq; | |
e5dadff4 | 934 | struct intel_timeline *tl; |
2ccdf6a1 | 935 | |
e5dadff4 CW |
936 | tl = intel_context_timeline_lock(ce); |
937 | if (IS_ERR(tl)) | |
938 | return ERR_CAST(tl); | |
2ccdf6a1 CW |
939 | |
940 | /* Move our oldest request to the slab-cache (if not in use!) */ | |
e5dadff4 CW |
941 | rq = list_first_entry(&tl->requests, typeof(*rq), link); |
942 | if (!list_is_last(&rq->link, &tl->requests)) | |
2ccdf6a1 CW |
943 | i915_request_retire(rq); |
944 | ||
945 | intel_context_enter(ce); | |
946 | rq = __i915_request_create(ce, GFP_KERNEL); | |
947 | intel_context_exit(ce); /* active reference transferred to request */ | |
948 | if (IS_ERR(rq)) | |
949 | goto err_unlock; | |
950 | ||
951 | /* Check that we do not interrupt ourselves with a new request */ | |
e5dadff4 | 952 | rq->cookie = lockdep_pin_lock(&tl->mutex); |
2ccdf6a1 CW |
953 | |
954 | return rq; | |
955 | ||
956 | err_unlock: | |
e5dadff4 | 957 | intel_context_timeline_unlock(tl); |
2ccdf6a1 CW |
958 | return rq; |
959 | } | |
960 | ||
0d90ccb7 CW |
961 | static int |
962 | i915_request_await_start(struct i915_request *rq, struct i915_request *signal) | |
963 | { | |
6a79d848 CW |
964 | struct dma_fence *fence; |
965 | int err; | |
0d90ccb7 | 966 | |
ab7a6902 CW |
967 | if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline)) |
968 | return 0; | |
6a79d848 | 969 | |
d22d2d07 CW |
970 | if (i915_request_started(signal)) |
971 | return 0; | |
972 | ||
9ddc8ec0 | 973 | fence = NULL; |
6a79d848 | 974 | rcu_read_lock(); |
9ddc8ec0 | 975 | spin_lock_irq(&signal->lock); |
d22d2d07 CW |
976 | do { |
977 | struct list_head *pos = READ_ONCE(signal->link.prev); | |
978 | struct i915_request *prev; | |
979 | ||
980 | /* Confirm signal has not been retired, the link is valid */ | |
981 | if (unlikely(i915_request_started(signal))) | |
982 | break; | |
983 | ||
984 | /* Is signal the earliest request on its timeline? */ | |
985 | if (pos == &rcu_dereference(signal->timeline)->requests) | |
986 | break; | |
0d90ccb7 | 987 | |
9ddc8ec0 CW |
988 | /* |
989 | * Peek at the request before us in the timeline. That | |
990 | * request will only be valid before it is retired, so | |
991 | * after acquiring a reference to it, confirm that it is | |
992 | * still part of the signaler's timeline. | |
993 | */ | |
d22d2d07 CW |
994 | prev = list_entry(pos, typeof(*prev), link); |
995 | if (!i915_request_get_rcu(prev)) | |
996 | break; | |
997 | ||
998 | /* After the strong barrier, confirm prev is still attached */ | |
999 | if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) { | |
1000 | i915_request_put(prev); | |
1001 | break; | |
6a79d848 | 1002 | } |
d22d2d07 CW |
1003 | |
1004 | fence = &prev->fence; | |
1005 | } while (0); | |
9ddc8ec0 CW |
1006 | spin_unlock_irq(&signal->lock); |
1007 | rcu_read_unlock(); | |
1008 | if (!fence) | |
1009 | return 0; | |
6a79d848 CW |
1010 | |
1011 | err = 0; | |
07e9c59d | 1012 | if (!intel_timeline_sync_is_later(i915_request_timeline(rq), fence)) |
6a79d848 CW |
1013 | err = i915_sw_fence_await_dma_fence(&rq->submit, |
1014 | fence, 0, | |
1015 | I915_FENCE_GFP); | |
1016 | dma_fence_put(fence); | |
1017 | ||
1018 | return err; | |
0d90ccb7 CW |
1019 | } |
1020 | ||
ca6e56f6 CW |
1021 | static intel_engine_mask_t |
1022 | already_busywaiting(struct i915_request *rq) | |
1023 | { | |
1024 | /* | |
1025 | * Polling a semaphore causes bus traffic, delaying other users of | |
1026 | * both the GPU and CPU. We want to limit the impact on others, | |
1027 | * while taking advantage of early submission to reduce GPU | |
1028 | * latency. Therefore we restrict ourselves to not using more | |
1029 | * than one semaphore from each source, and not using a semaphore | |
1030 | * if we have detected the engine is saturated (i.e. would not be | |
1031 | * submitted early and cause bus traffic reading an already passed | |
1032 | * semaphore). | |
1033 | * | |
1034 | * See the are-we-too-late? check in __i915_request_submit(). | |
1035 | */ | |
60900add | 1036 | return rq->sched.semaphores | READ_ONCE(rq->engine->saturated); |
ca6e56f6 CW |
1037 | } |
1038 | ||
e8861964 | 1039 | static int |
c81471f5 CW |
1040 | __emit_semaphore_wait(struct i915_request *to, |
1041 | struct i915_request *from, | |
1042 | u32 seqno) | |
e8861964 | 1043 | { |
5a833995 | 1044 | const int has_token = INTEL_GEN(to->engine->i915) >= 12; |
e8861964 | 1045 | u32 hwsp_offset; |
c81471f5 | 1046 | int len, err; |
e8861964 | 1047 | u32 *cs; |
e8861964 | 1048 | |
5a833995 | 1049 | GEM_BUG_ON(INTEL_GEN(to->engine->i915) < 8); |
795d4d7f | 1050 | GEM_BUG_ON(i915_request_has_initial_breadcrumb(to)); |
e8861964 | 1051 | |
c8a0e2ae | 1052 | /* We need to pin the signaler's HWSP until we are finished reading. */ |
c81471f5 CW |
1053 | err = intel_timeline_read_hwsp(from, to, &hwsp_offset); |
1054 | if (err) | |
1055 | return err; | |
e8861964 | 1056 | |
c210e85b CW |
1057 | len = 4; |
1058 | if (has_token) | |
1059 | len += 2; | |
1060 | ||
1061 | cs = intel_ring_begin(to, len); | |
e8861964 CW |
1062 | if (IS_ERR(cs)) |
1063 | return PTR_ERR(cs); | |
1064 | ||
1065 | /* | |
1066 | * Using greater-than-or-equal here means we have to worry | |
1067 | * about seqno wraparound. To side step that issue, we swap | |
1068 | * the timeline HWSP upon wrapping, so that everyone listening | |
1069 | * for the old (pre-wrap) values do not see the much smaller | |
1070 | * (post-wrap) values than they were expecting (and so wait | |
1071 | * forever). | |
1072 | */ | |
c210e85b CW |
1073 | *cs++ = (MI_SEMAPHORE_WAIT | |
1074 | MI_SEMAPHORE_GLOBAL_GTT | | |
1075 | MI_SEMAPHORE_POLL | | |
1076 | MI_SEMAPHORE_SAD_GTE_SDD) + | |
1077 | has_token; | |
c81471f5 | 1078 | *cs++ = seqno; |
e8861964 CW |
1079 | *cs++ = hwsp_offset; |
1080 | *cs++ = 0; | |
c210e85b CW |
1081 | if (has_token) { |
1082 | *cs++ = 0; | |
1083 | *cs++ = MI_NOOP; | |
1084 | } | |
e8861964 CW |
1085 | |
1086 | intel_ring_advance(to, cs); | |
c81471f5 CW |
1087 | return 0; |
1088 | } | |
1089 | ||
1090 | static int | |
1091 | emit_semaphore_wait(struct i915_request *to, | |
1092 | struct i915_request *from, | |
1093 | gfp_t gfp) | |
1094 | { | |
326611dd | 1095 | const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask; |
18e4af04 | 1096 | struct i915_sw_fence *wait = &to->submit; |
326611dd | 1097 | |
f16ccb64 CW |
1098 | if (!intel_context_use_semaphores(to->context)) |
1099 | goto await_fence; | |
1100 | ||
795d4d7f CW |
1101 | if (i915_request_has_initial_breadcrumb(to)) |
1102 | goto await_fence; | |
1103 | ||
f16ccb64 CW |
1104 | if (!rcu_access_pointer(from->hwsp_cacheline)) |
1105 | goto await_fence; | |
1106 | ||
fcae4961 CW |
1107 | /* |
1108 | * If this or its dependents are waiting on an external fence | |
1109 | * that may fail catastrophically, then we want to avoid using | |
1110 | * sempahores as they bypass the fence signaling metadata, and we | |
1111 | * lose the fence->error propagation. | |
1112 | */ | |
1113 | if (from->sched.flags & I915_SCHED_HAS_EXTERNAL_CHAIN) | |
1114 | goto await_fence; | |
1115 | ||
c81471f5 | 1116 | /* Just emit the first semaphore we see as request space is limited. */ |
326611dd | 1117 | if (already_busywaiting(to) & mask) |
c81471f5 CW |
1118 | goto await_fence; |
1119 | ||
1120 | if (i915_request_await_start(to, from) < 0) | |
1121 | goto await_fence; | |
1122 | ||
1123 | /* Only submit our spinner after the signaler is running! */ | |
1124 | if (__await_execution(to, from, NULL, gfp)) | |
1125 | goto await_fence; | |
1126 | ||
1127 | if (__emit_semaphore_wait(to, from, from->fence.seqno)) | |
1128 | goto await_fence; | |
1129 | ||
326611dd | 1130 | to->sched.semaphores |= mask; |
18e4af04 | 1131 | wait = &to->semaphore; |
6a79d848 CW |
1132 | |
1133 | await_fence: | |
18e4af04 | 1134 | return i915_sw_fence_await_dma_fence(wait, |
6a79d848 CW |
1135 | &from->fence, 0, |
1136 | I915_FENCE_GFP); | |
e8861964 CW |
1137 | } |
1138 | ||
ffb0c600 CW |
1139 | static bool intel_timeline_sync_has_start(struct intel_timeline *tl, |
1140 | struct dma_fence *fence) | |
1141 | { | |
1142 | return __intel_timeline_sync_is_later(tl, | |
1143 | fence->context, | |
1144 | fence->seqno - 1); | |
1145 | } | |
1146 | ||
1147 | static int intel_timeline_sync_set_start(struct intel_timeline *tl, | |
1148 | const struct dma_fence *fence) | |
1149 | { | |
1150 | return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1); | |
1151 | } | |
1152 | ||
a2bc4695 | 1153 | static int |
ffb0c600 CW |
1154 | __i915_request_await_execution(struct i915_request *to, |
1155 | struct i915_request *from, | |
1156 | void (*hook)(struct i915_request *rq, | |
1157 | struct dma_fence *signal)) | |
a2bc4695 | 1158 | { |
ffb0c600 | 1159 | int err; |
a2bc4695 | 1160 | |
ffb0c600 | 1161 | GEM_BUG_ON(intel_context_is_barrier(from->context)); |
a2bc4695 | 1162 | |
ffb0c600 CW |
1163 | /* Submit both requests at the same time */ |
1164 | err = __await_execution(to, from, hook, I915_FENCE_GFP); | |
1165 | if (err) | |
1166 | return err; | |
1167 | ||
1168 | /* Squash repeated depenendices to the same timelines */ | |
1169 | if (intel_timeline_sync_has_start(i915_request_timeline(to), | |
1170 | &from->fence)) | |
ade0b0c9 | 1171 | return 0; |
ffb0c600 CW |
1172 | |
1173 | /* | |
1174 | * Wait until the start of this request. | |
1175 | * | |
1176 | * The execution cb fires when we submit the request to HW. But in | |
1177 | * many cases this may be long before the request itself is ready to | |
1178 | * run (consider that we submit 2 requests for the same context, where | |
1179 | * the request of interest is behind an indefinite spinner). So we hook | |
1180 | * up to both to reduce our queues and keep the execution lag minimised | |
1181 | * in the worst case, though we hope that the await_start is elided. | |
1182 | */ | |
1183 | err = i915_request_await_start(to, from); | |
1184 | if (err < 0) | |
1185 | return err; | |
1186 | ||
1187 | /* | |
1188 | * Ensure both start together [after all semaphores in signal] | |
1189 | * | |
1190 | * Now that we are queued to the HW at roughly the same time (thanks | |
1191 | * to the execute cb) and are ready to run at roughly the same time | |
1192 | * (thanks to the await start), our signaler may still be indefinitely | |
1193 | * delayed by waiting on a semaphore from a remote engine. If our | |
1194 | * signaler depends on a semaphore, so indirectly do we, and we do not | |
1195 | * want to start our payload until our signaler also starts theirs. | |
1196 | * So we wait. | |
1197 | * | |
1198 | * However, there is also a second condition for which we need to wait | |
1199 | * for the precise start of the signaler. Consider that the signaler | |
1200 | * was submitted in a chain of requests following another context | |
1201 | * (with just an ordinary intra-engine fence dependency between the | |
1202 | * two). In this case the signaler is queued to HW, but not for | |
1203 | * immediate execution, and so we must wait until it reaches the | |
1204 | * active slot. | |
1205 | */ | |
1206 | if (intel_engine_has_semaphores(to->engine) && | |
1207 | !i915_request_has_initial_breadcrumb(to)) { | |
1208 | err = __emit_semaphore_wait(to, from, from->fence.seqno - 1); | |
1209 | if (err < 0) | |
1210 | return err; | |
24fe5f2a | 1211 | } |
ade0b0c9 | 1212 | |
ffb0c600 | 1213 | /* Couple the dependency tree for PI on this exposed to->fence */ |
52e54209 | 1214 | if (to->engine->schedule) { |
ffb0c600 | 1215 | err = i915_sched_node_add_dependency(&to->sched, |
6b6cd2eb | 1216 | &from->sched, |
ffb0c600 CW |
1217 | I915_DEPENDENCY_WEAK); |
1218 | if (err < 0) | |
1219 | return err; | |
52e54209 CW |
1220 | } |
1221 | ||
ffb0c600 CW |
1222 | return intel_timeline_sync_set_start(i915_request_timeline(to), |
1223 | &from->fence); | |
a2bc4695 CW |
1224 | } |
1225 | ||
fcae4961 CW |
1226 | static void mark_external(struct i915_request *rq) |
1227 | { | |
1228 | /* | |
1229 | * The downside of using semaphores is that we lose metadata passing | |
1230 | * along the signaling chain. This is particularly nasty when we | |
1231 | * need to pass along a fatal error such as EFAULT or EDEADLK. For | |
1232 | * fatal errors we want to scrub the request before it is executed, | |
1233 | * which means that we cannot preload the request onto HW and have | |
1234 | * it wait upon a semaphore. | |
1235 | */ | |
1236 | rq->sched.flags |= I915_SCHED_HAS_EXTERNAL_CHAIN; | |
1237 | } | |
1238 | ||
ac938052 | 1239 | static int |
3136deb7 | 1240 | __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) |
ac938052 | 1241 | { |
fcae4961 | 1242 | mark_external(rq); |
ac938052 | 1243 | return i915_sw_fence_await_dma_fence(&rq->submit, fence, |
5a833995 | 1244 | i915_fence_context_timeout(rq->engine->i915, |
16dc224f | 1245 | fence->context), |
ac938052 CW |
1246 | I915_FENCE_GFP); |
1247 | } | |
1248 | ||
3136deb7 LL |
1249 | static int |
1250 | i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) | |
1251 | { | |
1252 | struct dma_fence *iter; | |
1253 | int err = 0; | |
1254 | ||
1255 | if (!to_dma_fence_chain(fence)) | |
1256 | return __i915_request_await_external(rq, fence); | |
1257 | ||
1258 | dma_fence_chain_for_each(iter, fence) { | |
1259 | struct dma_fence_chain *chain = to_dma_fence_chain(iter); | |
1260 | ||
1261 | if (!dma_fence_is_i915(chain->fence)) { | |
1262 | err = __i915_request_await_external(rq, iter); | |
1263 | break; | |
1264 | } | |
1265 | ||
1266 | err = i915_request_await_dma_fence(rq, chain->fence); | |
1267 | if (err < 0) | |
1268 | break; | |
1269 | } | |
1270 | ||
1271 | dma_fence_put(iter); | |
1272 | return err; | |
1273 | } | |
1274 | ||
b52992c0 | 1275 | int |
ffb0c600 CW |
1276 | i915_request_await_execution(struct i915_request *rq, |
1277 | struct dma_fence *fence, | |
1278 | void (*hook)(struct i915_request *rq, | |
1279 | struct dma_fence *signal)) | |
b52992c0 | 1280 | { |
29ef3fa9 CW |
1281 | struct dma_fence **child = &fence; |
1282 | unsigned int nchild = 1; | |
b52992c0 | 1283 | int ret; |
b52992c0 | 1284 | |
29ef3fa9 CW |
1285 | if (dma_fence_is_array(fence)) { |
1286 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
1287 | ||
ffb0c600 CW |
1288 | /* XXX Error for signal-on-any fence arrays */ |
1289 | ||
29ef3fa9 CW |
1290 | child = array->fences; |
1291 | nchild = array->num_fences; | |
1292 | GEM_BUG_ON(!nchild); | |
1293 | } | |
b52992c0 | 1294 | |
29ef3fa9 CW |
1295 | do { |
1296 | fence = *child++; | |
9e31c1fe CW |
1297 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { |
1298 | i915_sw_fence_set_error_once(&rq->submit, fence->error); | |
29ef3fa9 | 1299 | continue; |
9e31c1fe | 1300 | } |
b52992c0 | 1301 | |
e61e0f51 | 1302 | if (fence->context == rq->fence.context) |
ceae14bd CW |
1303 | continue; |
1304 | ||
ffb0c600 CW |
1305 | /* |
1306 | * We don't squash repeated fence dependencies here as we | |
1307 | * want to run our callback in all cases. | |
1308 | */ | |
47979480 | 1309 | |
29ef3fa9 | 1310 | if (dma_fence_is_i915(fence)) |
ffb0c600 CW |
1311 | ret = __i915_request_await_execution(rq, |
1312 | to_request(fence), | |
1313 | hook); | |
b52992c0 | 1314 | else |
ac938052 | 1315 | ret = i915_request_await_external(rq, fence); |
b52992c0 CW |
1316 | if (ret < 0) |
1317 | return ret; | |
29ef3fa9 | 1318 | } while (--nchild); |
b52992c0 CW |
1319 | |
1320 | return 0; | |
1321 | } | |
1322 | ||
511b6d9a CW |
1323 | static int |
1324 | await_request_submit(struct i915_request *to, struct i915_request *from) | |
1325 | { | |
1326 | /* | |
1327 | * If we are waiting on a virtual engine, then it may be | |
1328 | * constrained to execute on a single engine *prior* to submission. | |
1329 | * When it is submitted, it will be first submitted to the virtual | |
1330 | * engine and then passed to the physical engine. We cannot allow | |
1331 | * the waiter to be submitted immediately to the physical engine | |
1332 | * as it may then bypass the virtual request. | |
1333 | */ | |
1334 | if (to->engine == READ_ONCE(from->engine)) | |
1335 | return i915_sw_fence_await_sw_fence_gfp(&to->submit, | |
1336 | &from->submit, | |
1337 | I915_FENCE_GFP); | |
1338 | else | |
1339 | return __i915_request_await_execution(to, from, NULL); | |
1340 | } | |
1341 | ||
c81471f5 | 1342 | static int |
ffb0c600 | 1343 | i915_request_await_request(struct i915_request *to, struct i915_request *from) |
c81471f5 | 1344 | { |
ffb0c600 | 1345 | int ret; |
f16ccb64 | 1346 | |
ffb0c600 CW |
1347 | GEM_BUG_ON(to == from); |
1348 | GEM_BUG_ON(to->timeline == from->timeline); | |
c81471f5 | 1349 | |
ffb0c600 CW |
1350 | if (i915_request_completed(from)) { |
1351 | i915_sw_fence_set_error_once(&to->submit, from->fence.error); | |
c81471f5 | 1352 | return 0; |
798fa870 CW |
1353 | } |
1354 | ||
c81471f5 | 1355 | if (to->engine->schedule) { |
ffb0c600 | 1356 | ret = i915_sched_node_add_dependency(&to->sched, |
6b6cd2eb | 1357 | &from->sched, |
ffb0c600 CW |
1358 | I915_DEPENDENCY_EXTERNAL); |
1359 | if (ret < 0) | |
1360 | return ret; | |
c81471f5 CW |
1361 | } |
1362 | ||
511b6d9a CW |
1363 | if (is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask))) |
1364 | ret = await_request_submit(to, from); | |
ffb0c600 CW |
1365 | else |
1366 | ret = emit_semaphore_wait(to, from, I915_FENCE_GFP); | |
1367 | if (ret < 0) | |
1368 | return ret; | |
1369 | ||
1370 | return 0; | |
c81471f5 CW |
1371 | } |
1372 | ||
f71e01a7 | 1373 | int |
ffb0c600 | 1374 | i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) |
f71e01a7 CW |
1375 | { |
1376 | struct dma_fence **child = &fence; | |
1377 | unsigned int nchild = 1; | |
1378 | int ret; | |
1379 | ||
ffb0c600 CW |
1380 | /* |
1381 | * Note that if the fence-array was created in signal-on-any mode, | |
1382 | * we should *not* decompose it into its individual fences. However, | |
1383 | * we don't currently store which mode the fence-array is operating | |
1384 | * in. Fortunately, the only user of signal-on-any is private to | |
1385 | * amdgpu and we should not see any incoming fence-array from | |
1386 | * sync-file being in signal-on-any mode. | |
1387 | */ | |
f71e01a7 CW |
1388 | if (dma_fence_is_array(fence)) { |
1389 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
1390 | ||
f71e01a7 CW |
1391 | child = array->fences; |
1392 | nchild = array->num_fences; | |
1393 | GEM_BUG_ON(!nchild); | |
1394 | } | |
1395 | ||
1396 | do { | |
1397 | fence = *child++; | |
9e31c1fe CW |
1398 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { |
1399 | i915_sw_fence_set_error_once(&rq->submit, fence->error); | |
f71e01a7 | 1400 | continue; |
9e31c1fe | 1401 | } |
f71e01a7 | 1402 | |
ffb0c600 CW |
1403 | /* |
1404 | * Requests on the same timeline are explicitly ordered, along | |
1405 | * with their dependencies, by i915_request_add() which ensures | |
1406 | * that requests are submitted in-order through each ring. | |
1407 | */ | |
2045d666 CW |
1408 | if (fence->context == rq->fence.context) |
1409 | continue; | |
1410 | ||
ffb0c600 CW |
1411 | /* Squash repeated waits to the same timelines */ |
1412 | if (fence->context && | |
1413 | intel_timeline_sync_is_later(i915_request_timeline(rq), | |
1414 | fence)) | |
1415 | continue; | |
f71e01a7 CW |
1416 | |
1417 | if (dma_fence_is_i915(fence)) | |
ffb0c600 | 1418 | ret = i915_request_await_request(rq, to_request(fence)); |
f71e01a7 | 1419 | else |
ac938052 | 1420 | ret = i915_request_await_external(rq, fence); |
f71e01a7 CW |
1421 | if (ret < 0) |
1422 | return ret; | |
ffb0c600 CW |
1423 | |
1424 | /* Record the latest fence used against each timeline */ | |
1425 | if (fence->context) | |
1426 | intel_timeline_sync_set(i915_request_timeline(rq), | |
1427 | fence); | |
f71e01a7 CW |
1428 | } while (--nchild); |
1429 | ||
1430 | return 0; | |
1431 | } | |
1432 | ||
a2bc4695 | 1433 | /** |
e61e0f51 | 1434 | * i915_request_await_object - set this request to (async) wait upon a bo |
a2bc4695 CW |
1435 | * @to: request we are wishing to use |
1436 | * @obj: object which may be in use on another ring. | |
d8802126 | 1437 | * @write: whether the wait is on behalf of a writer |
a2bc4695 CW |
1438 | * |
1439 | * This code is meant to abstract object synchronization with the GPU. | |
1440 | * Conceptually we serialise writes between engines inside the GPU. | |
1441 | * We only allow one engine to write into a buffer at any time, but | |
1442 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
1443 | * | |
1444 | * - If there is an outstanding write request to the object, the new | |
1445 | * request must wait for it to complete (either CPU or in hw, requests | |
1446 | * on the same ring will be naturally ordered). | |
1447 | * | |
1448 | * - If we are a write request (pending_write_domain is set), the new | |
1449 | * request must wait for outstanding read requests to complete. | |
1450 | * | |
1451 | * Returns 0 if successful, else propagates up the lower layer error. | |
1452 | */ | |
1453 | int | |
e61e0f51 CW |
1454 | i915_request_await_object(struct i915_request *to, |
1455 | struct drm_i915_gem_object *obj, | |
1456 | bool write) | |
a2bc4695 | 1457 | { |
d07f0e59 CW |
1458 | struct dma_fence *excl; |
1459 | int ret = 0; | |
a2bc4695 CW |
1460 | |
1461 | if (write) { | |
d07f0e59 CW |
1462 | struct dma_fence **shared; |
1463 | unsigned int count, i; | |
1464 | ||
52791eee | 1465 | ret = dma_resv_get_fences_rcu(obj->base.resv, |
d07f0e59 CW |
1466 | &excl, &count, &shared); |
1467 | if (ret) | |
1468 | return ret; | |
1469 | ||
1470 | for (i = 0; i < count; i++) { | |
e61e0f51 | 1471 | ret = i915_request_await_dma_fence(to, shared[i]); |
d07f0e59 CW |
1472 | if (ret) |
1473 | break; | |
1474 | ||
1475 | dma_fence_put(shared[i]); | |
1476 | } | |
1477 | ||
1478 | for (; i < count; i++) | |
1479 | dma_fence_put(shared[i]); | |
1480 | kfree(shared); | |
a2bc4695 | 1481 | } else { |
52791eee | 1482 | excl = dma_resv_get_excl_rcu(obj->base.resv); |
a2bc4695 CW |
1483 | } |
1484 | ||
d07f0e59 CW |
1485 | if (excl) { |
1486 | if (ret == 0) | |
e61e0f51 | 1487 | ret = i915_request_await_dma_fence(to, excl); |
a2bc4695 | 1488 | |
d07f0e59 | 1489 | dma_fence_put(excl); |
a2bc4695 CW |
1490 | } |
1491 | ||
d07f0e59 | 1492 | return ret; |
a2bc4695 CW |
1493 | } |
1494 | ||
ea593dbb CW |
1495 | static struct i915_request * |
1496 | __i915_request_add_to_timeline(struct i915_request *rq) | |
1497 | { | |
d19d71fc | 1498 | struct intel_timeline *timeline = i915_request_timeline(rq); |
ea593dbb CW |
1499 | struct i915_request *prev; |
1500 | ||
1501 | /* | |
1502 | * Dependency tracking and request ordering along the timeline | |
1503 | * is special cased so that we can eliminate redundant ordering | |
1504 | * operations while building the request (we know that the timeline | |
1505 | * itself is ordered, and here we guarantee it). | |
1506 | * | |
1507 | * As we know we will need to emit tracking along the timeline, | |
1508 | * we embed the hooks into our request struct -- at the cost of | |
1509 | * having to have specialised no-allocation interfaces (which will | |
1510 | * be beneficial elsewhere). | |
1511 | * | |
1512 | * A second benefit to open-coding i915_request_await_request is | |
1513 | * that we can apply a slight variant of the rules specialised | |
1514 | * for timelines that jump between engines (such as virtual engines). | |
1515 | * If we consider the case of virtual engine, we must emit a dma-fence | |
1516 | * to prevent scheduling of the second request until the first is | |
1517 | * complete (to maximise our greedy late load balancing) and this | |
1518 | * precludes optimising to use semaphores serialisation of a single | |
1519 | * timeline across engines. | |
1520 | */ | |
b1e3177b CW |
1521 | prev = to_request(__i915_active_fence_set(&timeline->last_request, |
1522 | &rq->fence)); | |
ea593dbb | 1523 | if (prev && !i915_request_completed(prev)) { |
1eaa251b CW |
1524 | /* |
1525 | * The requests are supposed to be kept in order. However, | |
1526 | * we need to be wary in case the timeline->last_request | |
1527 | * is used as a barrier for external modification to this | |
1528 | * context. | |
1529 | */ | |
1530 | GEM_BUG_ON(prev->context == rq->context && | |
1531 | i915_seqno_passed(prev->fence.seqno, | |
1532 | rq->fence.seqno)); | |
1533 | ||
326611dd | 1534 | if (is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask)) |
ea593dbb CW |
1535 | i915_sw_fence_await_sw_fence(&rq->submit, |
1536 | &prev->submit, | |
1537 | &rq->submitq); | |
1538 | else | |
1539 | __i915_sw_fence_await_dma_fence(&rq->submit, | |
1540 | &prev->fence, | |
1541 | &rq->dmaq); | |
1542 | if (rq->engine->schedule) | |
1543 | __i915_sched_node_add_dependency(&rq->sched, | |
1544 | &prev->sched, | |
1545 | &rq->dep, | |
1546 | 0); | |
1547 | } | |
1548 | ||
2ccdf6a1 CW |
1549 | /* |
1550 | * Make sure that no request gazumped us - if it was allocated after | |
1551 | * our i915_request_alloc() and called __i915_request_add() before | |
1552 | * us, the timeline will hold its seqno which is later than ours. | |
1553 | */ | |
ea593dbb | 1554 | GEM_BUG_ON(timeline->seqno != rq->fence.seqno); |
ea593dbb CW |
1555 | |
1556 | return prev; | |
1557 | } | |
1558 | ||
05235c53 CW |
1559 | /* |
1560 | * NB: This function is not allowed to fail. Doing so would mean the the | |
1561 | * request is not being tracked for completion but the work itself is | |
1562 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
1563 | */ | |
2ccdf6a1 | 1564 | struct i915_request *__i915_request_commit(struct i915_request *rq) |
05235c53 | 1565 | { |
2ccdf6a1 CW |
1566 | struct intel_engine_cs *engine = rq->engine; |
1567 | struct intel_ring *ring = rq->ring; | |
73dec95e | 1568 | u32 *cs; |
05235c53 | 1569 | |
639f2f24 | 1570 | RQ_TRACE(rq, "\n"); |
c781c978 | 1571 | |
05235c53 CW |
1572 | /* |
1573 | * To ensure that this call will not fail, space for its emissions | |
1574 | * should already have been reserved in the ring buffer. Let the ring | |
1575 | * know that it is time to use that space up. | |
1576 | */ | |
2ccdf6a1 CW |
1577 | GEM_BUG_ON(rq->reserved_space > ring->space); |
1578 | rq->reserved_space = 0; | |
e5dadff4 | 1579 | rq->emitted_jiffies = jiffies; |
05235c53 | 1580 | |
8ac71d1d CW |
1581 | /* |
1582 | * Record the position of the start of the breadcrumb so that | |
05235c53 CW |
1583 | * should we detect the updated seqno part-way through the |
1584 | * GPU processing the request, we never over-estimate the | |
d045446d | 1585 | * position of the ring's HEAD. |
05235c53 | 1586 | */ |
2ccdf6a1 | 1587 | cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw); |
73dec95e | 1588 | GEM_BUG_ON(IS_ERR(cs)); |
2ccdf6a1 | 1589 | rq->postfix = intel_ring_offset(rq, cs); |
05235c53 | 1590 | |
e5dadff4 | 1591 | return __i915_request_add_to_timeline(rq); |
a79ca656 CW |
1592 | } |
1593 | ||
16f2941a CW |
1594 | void __i915_request_queue_bh(struct i915_request *rq) |
1595 | { | |
1596 | i915_sw_fence_commit(&rq->semaphore); | |
1597 | i915_sw_fence_commit(&rq->submit); | |
1598 | } | |
1599 | ||
a79ca656 CW |
1600 | void __i915_request_queue(struct i915_request *rq, |
1601 | const struct i915_sched_attr *attr) | |
1602 | { | |
8ac71d1d CW |
1603 | /* |
1604 | * Let the backend know a new request has arrived that may need | |
0de9136d CW |
1605 | * to adjust the existing execution schedule due to a high priority |
1606 | * request - i.e. we may want to preempt the current request in order | |
1607 | * to run a high priority dependency chain *before* we can execute this | |
1608 | * request. | |
1609 | * | |
1610 | * This is called before the request is ready to run so that we can | |
1611 | * decide whether to preempt the entire chain so that it is ready to | |
1612 | * run at the earliest possible convenience. | |
1613 | */ | |
a79ca656 CW |
1614 | if (attr && rq->engine->schedule) |
1615 | rq->engine->schedule(rq, attr); | |
16f2941a CW |
1616 | |
1617 | local_bh_disable(); | |
1618 | __i915_request_queue_bh(rq); | |
1619 | local_bh_enable(); /* kick tasklets */ | |
2ccdf6a1 CW |
1620 | } |
1621 | ||
1622 | void i915_request_add(struct i915_request *rq) | |
1623 | { | |
d19d71fc | 1624 | struct intel_timeline * const tl = i915_request_timeline(rq); |
e6ba7648 | 1625 | struct i915_sched_attr attr = {}; |
61231f6b | 1626 | struct i915_gem_context *ctx; |
2ccdf6a1 | 1627 | |
e5dadff4 CW |
1628 | lockdep_assert_held(&tl->mutex); |
1629 | lockdep_unpin_lock(&tl->mutex, rq->cookie); | |
2ccdf6a1 CW |
1630 | |
1631 | trace_i915_request_add(rq); | |
61231f6b | 1632 | __i915_request_commit(rq); |
2ccdf6a1 | 1633 | |
61231f6b CW |
1634 | /* XXX placeholder for selftests */ |
1635 | rcu_read_lock(); | |
1636 | ctx = rcu_dereference(rq->context->gem_context); | |
1637 | if (ctx) | |
1638 | attr = ctx->sched; | |
1639 | rcu_read_unlock(); | |
e6ba7648 | 1640 | |
a79ca656 CW |
1641 | __i915_request_queue(rq, &attr); |
1642 | ||
e5dadff4 | 1643 | mutex_unlock(&tl->mutex); |
05235c53 CW |
1644 | } |
1645 | ||
062444bb | 1646 | static unsigned long local_clock_ns(unsigned int *cpu) |
05235c53 CW |
1647 | { |
1648 | unsigned long t; | |
1649 | ||
e61e0f51 CW |
1650 | /* |
1651 | * Cheaply and approximately convert from nanoseconds to microseconds. | |
05235c53 CW |
1652 | * The result and subsequent calculations are also defined in the same |
1653 | * approximate microseconds units. The principal source of timing | |
1654 | * error here is from the simple truncation. | |
1655 | * | |
1656 | * Note that local_clock() is only defined wrt to the current CPU; | |
1657 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1658 | * blocking preemption for the entire busywait, we can detect the CPU | |
1659 | * switch and use that as indicator of system load and a reason to | |
1660 | * stop busywaiting, see busywait_stop(). | |
1661 | */ | |
1662 | *cpu = get_cpu(); | |
062444bb | 1663 | t = local_clock(); |
05235c53 CW |
1664 | put_cpu(); |
1665 | ||
1666 | return t; | |
1667 | } | |
1668 | ||
1669 | static bool busywait_stop(unsigned long timeout, unsigned int cpu) | |
1670 | { | |
1671 | unsigned int this_cpu; | |
1672 | ||
062444bb | 1673 | if (time_after(local_clock_ns(&this_cpu), timeout)) |
05235c53 CW |
1674 | return true; |
1675 | ||
1676 | return this_cpu != cpu; | |
1677 | } | |
1678 | ||
3f6a6f34 | 1679 | static bool __i915_spin_request(struct i915_request * const rq, int state) |
05235c53 | 1680 | { |
062444bb | 1681 | unsigned long timeout_ns; |
52c0fdb2 | 1682 | unsigned int cpu; |
b2f2f0fc CW |
1683 | |
1684 | /* | |
1685 | * Only wait for the request if we know it is likely to complete. | |
1686 | * | |
1687 | * We don't track the timestamps around requests, nor the average | |
1688 | * request length, so we do not have a good indicator that this | |
1689 | * request will complete within the timeout. What we do know is the | |
52c0fdb2 CW |
1690 | * order in which requests are executed by the context and so we can |
1691 | * tell if the request has been started. If the request is not even | |
1692 | * running yet, it is a fair assumption that it will not complete | |
1693 | * within our relatively short timeout. | |
b2f2f0fc | 1694 | */ |
52c0fdb2 | 1695 | if (!i915_request_is_running(rq)) |
b2f2f0fc CW |
1696 | return false; |
1697 | ||
e61e0f51 CW |
1698 | /* |
1699 | * When waiting for high frequency requests, e.g. during synchronous | |
05235c53 CW |
1700 | * rendering split between the CPU and GPU, the finite amount of time |
1701 | * required to set up the irq and wait upon it limits the response | |
1702 | * rate. By busywaiting on the request completion for a short while we | |
1703 | * can service the high frequency waits as quick as possible. However, | |
1704 | * if it is a slow request, we want to sleep as quickly as possible. | |
1705 | * The tradeoff between waiting and sleeping is roughly the time it | |
1706 | * takes to sleep on a request, on the order of a microsecond. | |
1707 | */ | |
1708 | ||
062444bb CW |
1709 | timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns); |
1710 | timeout_ns += local_clock_ns(&cpu); | |
05235c53 | 1711 | do { |
3f6a6f34 | 1712 | if (dma_fence_is_signaled(&rq->fence)) |
52c0fdb2 | 1713 | return true; |
c33ed067 | 1714 | |
05235c53 CW |
1715 | if (signal_pending_state(state, current)) |
1716 | break; | |
1717 | ||
062444bb | 1718 | if (busywait_stop(timeout_ns, cpu)) |
05235c53 CW |
1719 | break; |
1720 | ||
f2f09a4c | 1721 | cpu_relax(); |
05235c53 CW |
1722 | } while (!need_resched()); |
1723 | ||
1724 | return false; | |
1725 | } | |
1726 | ||
52c0fdb2 CW |
1727 | struct request_wait { |
1728 | struct dma_fence_cb cb; | |
1729 | struct task_struct *tsk; | |
1730 | }; | |
1731 | ||
1732 | static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb) | |
1733 | { | |
1734 | struct request_wait *wait = container_of(cb, typeof(*wait), cb); | |
1735 | ||
3f6a6f34 | 1736 | wake_up_process(fetch_and_zero(&wait->tsk)); |
52c0fdb2 CW |
1737 | } |
1738 | ||
05235c53 | 1739 | /** |
e532be89 | 1740 | * i915_request_wait - wait until execution of request has finished |
e61e0f51 | 1741 | * @rq: the request to wait upon |
ea746f36 | 1742 | * @flags: how to wait |
e95433c7 CW |
1743 | * @timeout: how long to wait in jiffies |
1744 | * | |
e532be89 | 1745 | * i915_request_wait() waits for the request to be completed, for a |
e95433c7 CW |
1746 | * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an |
1747 | * unbounded wait). | |
05235c53 | 1748 | * |
e95433c7 CW |
1749 | * Returns the remaining time (in jiffies) if the request completed, which may |
1750 | * be zero or -ETIME if the request is unfinished after the timeout expires. | |
1751 | * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is | |
1752 | * pending before the request completes. | |
05235c53 | 1753 | */ |
e61e0f51 | 1754 | long i915_request_wait(struct i915_request *rq, |
e95433c7 CW |
1755 | unsigned int flags, |
1756 | long timeout) | |
05235c53 | 1757 | { |
ea746f36 CW |
1758 | const int state = flags & I915_WAIT_INTERRUPTIBLE ? |
1759 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
52c0fdb2 | 1760 | struct request_wait wait; |
05235c53 CW |
1761 | |
1762 | might_sleep(); | |
e95433c7 | 1763 | GEM_BUG_ON(timeout < 0); |
05235c53 | 1764 | |
6e4e9708 | 1765 | if (dma_fence_is_signaled(&rq->fence)) |
e95433c7 | 1766 | return timeout; |
05235c53 | 1767 | |
e95433c7 CW |
1768 | if (!timeout) |
1769 | return -ETIME; | |
05235c53 | 1770 | |
e61e0f51 | 1771 | trace_i915_request_wait_begin(rq, flags); |
84383d2e CW |
1772 | |
1773 | /* | |
1774 | * We must never wait on the GPU while holding a lock as we | |
1775 | * may need to perform a GPU reset. So while we don't need to | |
1776 | * serialise wait/reset with an explicit lock, we do want | |
1777 | * lockdep to detect potential dependency cycles. | |
1778 | */ | |
cb823ed9 | 1779 | mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_); |
4680816b | 1780 | |
7ce99d24 CW |
1781 | /* |
1782 | * Optimistic spin before touching IRQs. | |
1783 | * | |
1784 | * We may use a rather large value here to offset the penalty of | |
1785 | * switching away from the active task. Frequently, the client will | |
1786 | * wait upon an old swapbuffer to throttle itself to remain within a | |
1787 | * frame of the gpu. If the client is running in lockstep with the gpu, | |
1788 | * then it should not be waiting long at all, and a sleep now will incur | |
1789 | * extra scheduler latency in producing the next frame. To try to | |
1790 | * avoid adding the cost of enabling/disabling the interrupt to the | |
1791 | * short wait, we first spin to see if the request would have completed | |
1792 | * in the time taken to setup the interrupt. | |
1793 | * | |
1794 | * We need upto 5us to enable the irq, and upto 20us to hide the | |
1795 | * scheduler latency of a context switch, ignoring the secondary | |
1796 | * impacts from a context switch such as cache eviction. | |
1797 | * | |
1798 | * The scheme used for low-latency IO is called "hybrid interrupt | |
1799 | * polling". The suggestion there is to sleep until just before you | |
1800 | * expect to be woken by the device interrupt and then poll for its | |
1801 | * completion. That requires having a good predictor for the request | |
1802 | * duration, which we currently lack. | |
1803 | */ | |
062444bb | 1804 | if (IS_ACTIVE(CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT) && |
3f6a6f34 | 1805 | __i915_spin_request(rq, state)) |
52c0fdb2 | 1806 | goto out; |
541ca6ed | 1807 | |
62eb3c24 CW |
1808 | /* |
1809 | * This client is about to stall waiting for the GPU. In many cases | |
1810 | * this is undesirable and limits the throughput of the system, as | |
1811 | * many clients cannot continue processing user input/output whilst | |
1812 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
1813 | * to the GPU load and thus incurs additional latency for the client. | |
1814 | * We can circumvent that by promoting the GPU frequency to maximum | |
1815 | * before we sleep. This makes the GPU throttle up much more quickly | |
1816 | * (good for benchmarks and user experience, e.g. window animations), | |
1817 | * but at a cost of spending more power processing the workload | |
1818 | * (bad for battery). | |
1819 | */ | |
1840d40a CW |
1820 | if (flags & I915_WAIT_PRIORITY && !i915_request_started(rq)) |
1821 | intel_rps_boost(rq); | |
4680816b | 1822 | |
52c0fdb2 CW |
1823 | wait.tsk = current; |
1824 | if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake)) | |
1825 | goto out; | |
4680816b | 1826 | |
3adee4ac CW |
1827 | /* |
1828 | * Flush the submission tasklet, but only if it may help this request. | |
1829 | * | |
1830 | * We sometimes experience some latency between the HW interrupts and | |
1831 | * tasklet execution (mostly due to ksoftirqd latency, but it can also | |
1832 | * be due to lazy CS events), so lets run the tasklet manually if there | |
1833 | * is a chance it may submit this request. If the request is not ready | |
1834 | * to run, as it is waiting for other fences to be signaled, flushing | |
1835 | * the tasklet is busy work without any advantage for this client. | |
1836 | * | |
1837 | * If the HW is being lazy, this is the last chance before we go to | |
1838 | * sleep to catch any pending events. We will check periodically in | |
1839 | * the heartbeat to flush the submission tasklets as a last resort | |
1840 | * for unhappy HW. | |
1841 | */ | |
1842 | if (i915_request_is_ready(rq)) | |
5ec17c76 | 1843 | __intel_engine_flush_submission(rq->engine, false); |
3adee4ac | 1844 | |
52c0fdb2 CW |
1845 | for (;;) { |
1846 | set_current_state(state); | |
05235c53 | 1847 | |
3f6a6f34 | 1848 | if (dma_fence_is_signaled(&rq->fence)) |
52c0fdb2 | 1849 | break; |
05235c53 | 1850 | |
05235c53 | 1851 | if (signal_pending_state(state, current)) { |
e95433c7 | 1852 | timeout = -ERESTARTSYS; |
05235c53 CW |
1853 | break; |
1854 | } | |
1855 | ||
e95433c7 CW |
1856 | if (!timeout) { |
1857 | timeout = -ETIME; | |
05235c53 CW |
1858 | break; |
1859 | } | |
1860 | ||
e95433c7 | 1861 | timeout = io_schedule_timeout(timeout); |
05235c53 | 1862 | } |
a49625f9 | 1863 | __set_current_state(TASK_RUNNING); |
05235c53 | 1864 | |
3f6a6f34 CW |
1865 | if (READ_ONCE(wait.tsk)) |
1866 | dma_fence_remove_callback(&rq->fence, &wait.cb); | |
1867 | GEM_BUG_ON(!list_empty(&wait.cb.node)); | |
52c0fdb2 CW |
1868 | |
1869 | out: | |
5facae4f | 1870 | mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_); |
52c0fdb2 | 1871 | trace_i915_request_wait_end(rq); |
e95433c7 | 1872 | return timeout; |
05235c53 | 1873 | } |
4b8de8e6 | 1874 | |
1f0e785a CW |
1875 | static int print_sched_attr(const struct i915_sched_attr *attr, |
1876 | char *buf, int x, int len) | |
1877 | { | |
1878 | if (attr->priority == I915_PRIORITY_INVALID) | |
1879 | return x; | |
1880 | ||
1881 | x += snprintf(buf + x, len - x, | |
1882 | " prio=%d", attr->priority); | |
1883 | ||
1884 | return x; | |
1885 | } | |
1886 | ||
562675d0 CW |
1887 | static char queue_status(const struct i915_request *rq) |
1888 | { | |
1889 | if (i915_request_is_active(rq)) | |
1890 | return 'E'; | |
1891 | ||
1892 | if (i915_request_is_ready(rq)) | |
1893 | return intel_engine_is_virtual(rq->engine) ? 'V' : 'R'; | |
1894 | ||
1895 | return 'U'; | |
1896 | } | |
1897 | ||
1898 | static const char *run_status(const struct i915_request *rq) | |
1899 | { | |
1900 | if (i915_request_completed(rq)) | |
1901 | return "!"; | |
1902 | ||
1903 | if (i915_request_started(rq)) | |
1904 | return "*"; | |
1905 | ||
1906 | if (!i915_sw_fence_signaled(&rq->semaphore)) | |
1907 | return "&"; | |
1908 | ||
1909 | return ""; | |
1910 | } | |
1911 | ||
1912 | static const char *fence_status(const struct i915_request *rq) | |
1913 | { | |
1914 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags)) | |
1915 | return "+"; | |
1916 | ||
1917 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) | |
1918 | return "-"; | |
1919 | ||
1920 | return ""; | |
1921 | } | |
1922 | ||
1f0e785a CW |
1923 | void i915_request_show(struct drm_printer *m, |
1924 | const struct i915_request *rq, | |
562675d0 CW |
1925 | const char *prefix, |
1926 | int indent) | |
1f0e785a CW |
1927 | { |
1928 | const char *name = rq->fence.ops->get_timeline_name((struct dma_fence *)&rq->fence); | |
1929 | char buf[80] = ""; | |
1930 | int x = 0; | |
1931 | ||
562675d0 CW |
1932 | /* |
1933 | * The prefix is used to show the queue status, for which we use | |
1934 | * the following flags: | |
1935 | * | |
1936 | * U [Unready] | |
1937 | * - initial status upon being submitted by the user | |
1938 | * | |
1939 | * - the request is not ready for execution as it is waiting | |
1940 | * for external fences | |
1941 | * | |
1942 | * R [Ready] | |
1943 | * - all fences the request was waiting on have been signaled, | |
1944 | * and the request is now ready for execution and will be | |
1945 | * in a backend queue | |
1946 | * | |
1947 | * - a ready request may still need to wait on semaphores | |
1948 | * [internal fences] | |
1949 | * | |
1950 | * V [Ready/virtual] | |
1951 | * - same as ready, but queued over multiple backends | |
1952 | * | |
1953 | * E [Executing] | |
1954 | * - the request has been transferred from the backend queue and | |
1955 | * submitted for execution on HW | |
1956 | * | |
1957 | * - a completed request may still be regarded as executing, its | |
1958 | * status may not be updated until it is retired and removed | |
1959 | * from the lists | |
1960 | */ | |
1961 | ||
1f0e785a CW |
1962 | x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf)); |
1963 | ||
562675d0 CW |
1964 | drm_printf(m, "%s%.*s%c %llx:%lld%s%s %s @ %dms: %s\n", |
1965 | prefix, indent, " ", | |
1966 | queue_status(rq), | |
1f0e785a | 1967 | rq->fence.context, rq->fence.seqno, |
562675d0 CW |
1968 | run_status(rq), |
1969 | fence_status(rq), | |
1f0e785a CW |
1970 | buf, |
1971 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), | |
1972 | name); | |
1973 | } | |
1974 | ||
c835c550 CW |
1975 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
1976 | #include "selftests/mock_request.c" | |
e61e0f51 | 1977 | #include "selftests/i915_request.c" |
c835c550 | 1978 | #endif |
32eb6bcf | 1979 | |
103b76ee CW |
1980 | static void i915_global_request_shrink(void) |
1981 | { | |
103b76ee CW |
1982 | kmem_cache_shrink(global.slab_execute_cbs); |
1983 | kmem_cache_shrink(global.slab_requests); | |
1984 | } | |
1985 | ||
1986 | static void i915_global_request_exit(void) | |
1987 | { | |
103b76ee CW |
1988 | kmem_cache_destroy(global.slab_execute_cbs); |
1989 | kmem_cache_destroy(global.slab_requests); | |
1990 | } | |
1991 | ||
1992 | static struct i915_global_request global = { { | |
1993 | .shrink = i915_global_request_shrink, | |
1994 | .exit = i915_global_request_exit, | |
1995 | } }; | |
1996 | ||
32eb6bcf CW |
1997 | int __init i915_global_request_init(void) |
1998 | { | |
67a3acaa CW |
1999 | global.slab_requests = |
2000 | kmem_cache_create("i915_request", | |
2001 | sizeof(struct i915_request), | |
2002 | __alignof__(struct i915_request), | |
2003 | SLAB_HWCACHE_ALIGN | | |
2004 | SLAB_RECLAIM_ACCOUNT | | |
2005 | SLAB_TYPESAFE_BY_RCU, | |
2006 | __i915_request_ctor); | |
32eb6bcf CW |
2007 | if (!global.slab_requests) |
2008 | return -ENOMEM; | |
2009 | ||
e8861964 CW |
2010 | global.slab_execute_cbs = KMEM_CACHE(execute_cb, |
2011 | SLAB_HWCACHE_ALIGN | | |
2012 | SLAB_RECLAIM_ACCOUNT | | |
2013 | SLAB_TYPESAFE_BY_RCU); | |
2014 | if (!global.slab_execute_cbs) | |
2015 | goto err_requests; | |
2016 | ||
103b76ee | 2017 | i915_global_register(&global.base); |
32eb6bcf CW |
2018 | return 0; |
2019 | ||
2020 | err_requests: | |
2021 | kmem_cache_destroy(global.slab_requests); | |
2022 | return -ENOMEM; | |
2023 | } |