Commit | Line | Data |
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05235c53 CW |
1 | /* |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
b52992c0 | 25 | #include <linux/dma-fence-array.h> |
e8861964 CW |
26 | #include <linux/irq_work.h> |
27 | #include <linux/prefetch.h> | |
e6017571 IM |
28 | #include <linux/sched.h> |
29 | #include <linux/sched/clock.h> | |
f361bf4a | 30 | #include <linux/sched/signal.h> |
fa545cbf | 31 | |
10be98a7 CW |
32 | #include "gem/i915_gem_context.h" |
33 | #include "gt/intel_context.h" | |
34 | ||
21950ee7 | 35 | #include "i915_active.h" |
696173b0 | 36 | #include "i915_drv.h" |
103b76ee | 37 | #include "i915_globals.h" |
a09d9a80 | 38 | #include "i915_trace.h" |
696173b0 | 39 | #include "intel_pm.h" |
05235c53 | 40 | |
e8861964 CW |
41 | struct execute_cb { |
42 | struct list_head link; | |
43 | struct irq_work work; | |
44 | struct i915_sw_fence *fence; | |
f71e01a7 CW |
45 | void (*hook)(struct i915_request *rq, struct dma_fence *signal); |
46 | struct i915_request *signal; | |
e8861964 CW |
47 | }; |
48 | ||
32eb6bcf | 49 | static struct i915_global_request { |
103b76ee | 50 | struct i915_global base; |
32eb6bcf CW |
51 | struct kmem_cache *slab_requests; |
52 | struct kmem_cache *slab_dependencies; | |
e8861964 | 53 | struct kmem_cache *slab_execute_cbs; |
32eb6bcf CW |
54 | } global; |
55 | ||
f54d1867 | 56 | static const char *i915_fence_get_driver_name(struct dma_fence *fence) |
04769652 CW |
57 | { |
58 | return "i915"; | |
59 | } | |
60 | ||
f54d1867 | 61 | static const char *i915_fence_get_timeline_name(struct dma_fence *fence) |
04769652 | 62 | { |
e61e0f51 CW |
63 | /* |
64 | * The timeline struct (as part of the ppgtt underneath a context) | |
05506b5b CW |
65 | * may be freed when the request is no longer in use by the GPU. |
66 | * We could extend the life of a context to beyond that of all | |
67 | * fences, possibly keeping the hw resource around indefinitely, | |
68 | * or we just give them a false name. Since | |
69 | * dma_fence_ops.get_timeline_name is a debug feature, the occasional | |
70 | * lie seems justifiable. | |
71 | */ | |
72 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
73 | return "signaled"; | |
74 | ||
4daffb66 | 75 | return to_request(fence)->gem_context->name ?: "[i915]"; |
04769652 CW |
76 | } |
77 | ||
f54d1867 | 78 | static bool i915_fence_signaled(struct dma_fence *fence) |
04769652 | 79 | { |
e61e0f51 | 80 | return i915_request_completed(to_request(fence)); |
04769652 CW |
81 | } |
82 | ||
f54d1867 | 83 | static bool i915_fence_enable_signaling(struct dma_fence *fence) |
04769652 | 84 | { |
52c0fdb2 | 85 | return i915_request_enable_breadcrumb(to_request(fence)); |
04769652 CW |
86 | } |
87 | ||
f54d1867 | 88 | static signed long i915_fence_wait(struct dma_fence *fence, |
04769652 | 89 | bool interruptible, |
e95433c7 | 90 | signed long timeout) |
04769652 | 91 | { |
62eb3c24 CW |
92 | return i915_request_wait(to_request(fence), |
93 | interruptible | I915_WAIT_PRIORITY, | |
94 | timeout); | |
04769652 CW |
95 | } |
96 | ||
f54d1867 | 97 | static void i915_fence_release(struct dma_fence *fence) |
04769652 | 98 | { |
e61e0f51 | 99 | struct i915_request *rq = to_request(fence); |
04769652 | 100 | |
e61e0f51 CW |
101 | /* |
102 | * The request is put onto a RCU freelist (i.e. the address | |
fc158405 CW |
103 | * is immediately reused), mark the fences as being freed now. |
104 | * Otherwise the debugobjects for the fences are only marked as | |
105 | * freed when the slab cache itself is freed, and so we would get | |
106 | * caught trying to reuse dead objects. | |
107 | */ | |
e61e0f51 | 108 | i915_sw_fence_fini(&rq->submit); |
0c441cb6 | 109 | i915_sw_fence_fini(&rq->semaphore); |
fc158405 | 110 | |
32eb6bcf | 111 | kmem_cache_free(global.slab_requests, rq); |
04769652 CW |
112 | } |
113 | ||
f54d1867 | 114 | const struct dma_fence_ops i915_fence_ops = { |
04769652 CW |
115 | .get_driver_name = i915_fence_get_driver_name, |
116 | .get_timeline_name = i915_fence_get_timeline_name, | |
117 | .enable_signaling = i915_fence_enable_signaling, | |
118 | .signaled = i915_fence_signaled, | |
119 | .wait = i915_fence_wait, | |
120 | .release = i915_fence_release, | |
04769652 CW |
121 | }; |
122 | ||
b87b6c0d CW |
123 | static void irq_execute_cb(struct irq_work *wrk) |
124 | { | |
125 | struct execute_cb *cb = container_of(wrk, typeof(*cb), work); | |
126 | ||
127 | i915_sw_fence_complete(cb->fence); | |
128 | kmem_cache_free(global.slab_execute_cbs, cb); | |
129 | } | |
130 | ||
131 | static void irq_execute_cb_hook(struct irq_work *wrk) | |
132 | { | |
133 | struct execute_cb *cb = container_of(wrk, typeof(*cb), work); | |
134 | ||
135 | cb->hook(container_of(cb->fence, struct i915_request, submit), | |
136 | &cb->signal->fence); | |
137 | i915_request_put(cb->signal); | |
138 | ||
139 | irq_execute_cb(wrk); | |
140 | } | |
141 | ||
142 | static void __notify_execute_cb(struct i915_request *rq) | |
143 | { | |
144 | struct execute_cb *cb; | |
145 | ||
146 | lockdep_assert_held(&rq->lock); | |
147 | ||
148 | if (list_empty(&rq->execute_cb)) | |
149 | return; | |
150 | ||
151 | list_for_each_entry(cb, &rq->execute_cb, link) | |
152 | irq_work_queue(&cb->work); | |
153 | ||
154 | /* | |
155 | * XXX Rollback on __i915_request_unsubmit() | |
156 | * | |
157 | * In the future, perhaps when we have an active time-slicing scheduler, | |
158 | * it will be interesting to unsubmit parallel execution and remove | |
159 | * busywaits from the GPU until their master is restarted. This is | |
160 | * quite hairy, we have to carefully rollback the fence and do a | |
161 | * preempt-to-idle cycle on the target engine, all the while the | |
162 | * master execute_cb may refire. | |
163 | */ | |
164 | INIT_LIST_HEAD(&rq->execute_cb); | |
165 | } | |
166 | ||
05235c53 | 167 | static inline void |
e61e0f51 | 168 | i915_request_remove_from_client(struct i915_request *request) |
05235c53 | 169 | { |
c8659efa | 170 | struct drm_i915_file_private *file_priv; |
05235c53 | 171 | |
c8659efa | 172 | file_priv = request->file_priv; |
05235c53 CW |
173 | if (!file_priv) |
174 | return; | |
175 | ||
176 | spin_lock(&file_priv->mm.lock); | |
c8659efa CW |
177 | if (request->file_priv) { |
178 | list_del(&request->client_link); | |
179 | request->file_priv = NULL; | |
180 | } | |
05235c53 | 181 | spin_unlock(&file_priv->mm.lock); |
05235c53 CW |
182 | } |
183 | ||
e61e0f51 | 184 | static void advance_ring(struct i915_request *request) |
cbb60b4b | 185 | { |
b887d615 | 186 | struct intel_ring *ring = request->ring; |
cbb60b4b CW |
187 | unsigned int tail; |
188 | ||
e61e0f51 CW |
189 | /* |
190 | * We know the GPU must have read the request to have | |
cbb60b4b CW |
191 | * sent us the seqno + interrupt, so use the position |
192 | * of tail of the request to update the last known position | |
193 | * of the GPU head. | |
194 | * | |
195 | * Note this requires that we are always called in request | |
196 | * completion order. | |
197 | */ | |
b887d615 CW |
198 | GEM_BUG_ON(!list_is_first(&request->ring_link, &ring->request_list)); |
199 | if (list_is_last(&request->ring_link, &ring->request_list)) { | |
e61e0f51 CW |
200 | /* |
201 | * We may race here with execlists resubmitting this request | |
e6ba9992 CW |
202 | * as we retire it. The resubmission will move the ring->tail |
203 | * forwards (to request->wa_tail). We either read the | |
204 | * current value that was written to hw, or the value that | |
205 | * is just about to be. Either works, if we miss the last two | |
206 | * noops - they are safe to be replayed on a reset. | |
207 | */ | |
36620032 | 208 | tail = READ_ONCE(request->tail); |
643b450a | 209 | list_del(&ring->active_link); |
e6ba9992 | 210 | } else { |
cbb60b4b | 211 | tail = request->postfix; |
e6ba9992 | 212 | } |
b887d615 | 213 | list_del_init(&request->ring_link); |
cbb60b4b | 214 | |
b887d615 | 215 | ring->head = tail; |
cbb60b4b CW |
216 | } |
217 | ||
e61e0f51 | 218 | static void free_capture_list(struct i915_request *request) |
b0fd47ad | 219 | { |
e61e0f51 | 220 | struct i915_capture_list *capture; |
b0fd47ad CW |
221 | |
222 | capture = request->capture_list; | |
223 | while (capture) { | |
e61e0f51 | 224 | struct i915_capture_list *next = capture->next; |
b0fd47ad CW |
225 | |
226 | kfree(capture); | |
227 | capture = next; | |
228 | } | |
229 | } | |
230 | ||
9db0c5ca | 231 | static bool i915_request_retire(struct i915_request *rq) |
05235c53 | 232 | { |
21950ee7 | 233 | struct i915_active_request *active, *next; |
fa545cbf | 234 | |
9db0c5ca CW |
235 | lockdep_assert_held(&rq->i915->drm.struct_mutex); |
236 | if (!i915_request_completed(rq)) | |
237 | return false; | |
d9b13c4d | 238 | |
9db0c5ca CW |
239 | GEM_TRACE("%s fence %llx:%lld, current %d\n", |
240 | rq->engine->name, | |
241 | rq->fence.context, rq->fence.seqno, | |
242 | hwsp_seqno(rq)); | |
4c7d62c6 | 243 | |
9db0c5ca CW |
244 | GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); |
245 | trace_i915_request_retire(rq); | |
80b204bc | 246 | |
9db0c5ca | 247 | advance_ring(rq); |
b0fd47ad | 248 | |
e61e0f51 CW |
249 | /* |
250 | * Walk through the active list, calling retire on each. This allows | |
fa545cbf CW |
251 | * objects to track their GPU activity and mark themselves as idle |
252 | * when their *last* active request is completed (updating state | |
253 | * tracking lists for eviction, active references for GEM, etc). | |
254 | * | |
255 | * As the ->retire() may free the node, we decouple it first and | |
256 | * pass along the auxiliary information (to avoid dereferencing | |
257 | * the node after the callback). | |
258 | */ | |
9db0c5ca | 259 | list_for_each_entry_safe(active, next, &rq->active_list, link) { |
e61e0f51 CW |
260 | /* |
261 | * In microbenchmarks or focusing upon time inside the kernel, | |
fa545cbf CW |
262 | * we may spend an inordinate amount of time simply handling |
263 | * the retirement of requests and processing their callbacks. | |
264 | * Of which, this loop itself is particularly hot due to the | |
21950ee7 CW |
265 | * cache misses when jumping around the list of |
266 | * i915_active_request. So we try to keep this loop as | |
267 | * streamlined as possible and also prefetch the next | |
268 | * i915_active_request to try and hide the likely cache miss. | |
fa545cbf CW |
269 | */ |
270 | prefetchw(next); | |
271 | ||
272 | INIT_LIST_HEAD(&active->link); | |
0eafec6d | 273 | RCU_INIT_POINTER(active->request, NULL); |
fa545cbf | 274 | |
9db0c5ca | 275 | active->retire(active, rq); |
fa545cbf CW |
276 | } |
277 | ||
9db0c5ca | 278 | local_irq_disable(); |
05235c53 | 279 | |
22b7a426 CW |
280 | /* |
281 | * We only loosely track inflight requests across preemption, | |
282 | * and so we may find ourselves attempting to retire a _completed_ | |
283 | * request that we have removed from the HW and put back on a run | |
284 | * queue. | |
285 | */ | |
422d7df4 CW |
286 | spin_lock(&rq->engine->active.lock); |
287 | list_del(&rq->sched.link); | |
288 | spin_unlock(&rq->engine->active.lock); | |
52e54209 | 289 | |
9db0c5ca CW |
290 | spin_lock(&rq->lock); |
291 | i915_request_mark_complete(rq); | |
292 | if (!i915_request_signaled(rq)) | |
293 | dma_fence_signal_locked(&rq->fence); | |
294 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) | |
295 | i915_request_cancel_breadcrumb(rq); | |
2a98f4e6 | 296 | if (i915_request_has_waitboost(rq)) { |
9db0c5ca CW |
297 | GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters)); |
298 | atomic_dec(&rq->i915->gt_pm.rps.num_waiters); | |
299 | } | |
b87b6c0d CW |
300 | if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags)) { |
301 | set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags); | |
302 | __notify_execute_cb(rq); | |
303 | } | |
304 | GEM_BUG_ON(!list_empty(&rq->execute_cb)); | |
9db0c5ca CW |
305 | spin_unlock(&rq->lock); |
306 | ||
307 | local_irq_enable(); | |
52d7f16e | 308 | |
9db0c5ca | 309 | i915_request_remove_from_client(rq); |
422d7df4 | 310 | list_del(&rq->link); |
9db0c5ca | 311 | |
75d0a7f3 CW |
312 | intel_context_exit(rq->hw_context); |
313 | intel_context_unpin(rq->hw_context); | |
314 | ||
9db0c5ca CW |
315 | free_capture_list(rq); |
316 | i915_sched_node_fini(&rq->sched); | |
317 | i915_request_put(rq); | |
318 | ||
319 | return true; | |
05235c53 CW |
320 | } |
321 | ||
e61e0f51 | 322 | void i915_request_retire_upto(struct i915_request *rq) |
05235c53 | 323 | { |
b887d615 | 324 | struct intel_ring *ring = rq->ring; |
e61e0f51 | 325 | struct i915_request *tmp; |
05235c53 | 326 | |
b300fde8 | 327 | GEM_TRACE("%s fence %llx:%lld, current %d\n", |
b887d615 CW |
328 | rq->engine->name, |
329 | rq->fence.context, rq->fence.seqno, | |
8892f477 | 330 | hwsp_seqno(rq)); |
b887d615 | 331 | |
e61e0f51 CW |
332 | lockdep_assert_held(&rq->i915->drm.struct_mutex); |
333 | GEM_BUG_ON(!i915_request_completed(rq)); | |
4ffd6e0c | 334 | |
b887d615 | 335 | if (list_empty(&rq->ring_link)) |
e95433c7 | 336 | return; |
05235c53 CW |
337 | |
338 | do { | |
b887d615 CW |
339 | tmp = list_first_entry(&ring->request_list, |
340 | typeof(*tmp), ring_link); | |
9db0c5ca | 341 | } while (i915_request_retire(tmp) && tmp != rq); |
05235c53 CW |
342 | } |
343 | ||
e8861964 | 344 | static int |
f71e01a7 CW |
345 | __i915_request_await_execution(struct i915_request *rq, |
346 | struct i915_request *signal, | |
347 | void (*hook)(struct i915_request *rq, | |
348 | struct dma_fence *signal), | |
349 | gfp_t gfp) | |
e8861964 CW |
350 | { |
351 | struct execute_cb *cb; | |
352 | ||
f71e01a7 CW |
353 | if (i915_request_is_active(signal)) { |
354 | if (hook) | |
355 | hook(rq, &signal->fence); | |
e8861964 | 356 | return 0; |
f71e01a7 | 357 | } |
e8861964 CW |
358 | |
359 | cb = kmem_cache_alloc(global.slab_execute_cbs, gfp); | |
360 | if (!cb) | |
361 | return -ENOMEM; | |
362 | ||
363 | cb->fence = &rq->submit; | |
364 | i915_sw_fence_await(cb->fence); | |
365 | init_irq_work(&cb->work, irq_execute_cb); | |
366 | ||
f71e01a7 CW |
367 | if (hook) { |
368 | cb->hook = hook; | |
369 | cb->signal = i915_request_get(signal); | |
370 | cb->work.func = irq_execute_cb_hook; | |
371 | } | |
372 | ||
e8861964 CW |
373 | spin_lock_irq(&signal->lock); |
374 | if (i915_request_is_active(signal)) { | |
f71e01a7 CW |
375 | if (hook) { |
376 | hook(rq, &signal->fence); | |
377 | i915_request_put(signal); | |
378 | } | |
e8861964 CW |
379 | i915_sw_fence_complete(cb->fence); |
380 | kmem_cache_free(global.slab_execute_cbs, cb); | |
381 | } else { | |
382 | list_add_tail(&cb->link, &signal->execute_cb); | |
383 | } | |
384 | spin_unlock_irq(&signal->lock); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
e61e0f51 | 389 | void __i915_request_submit(struct i915_request *request) |
5590af3e | 390 | { |
73cb9701 | 391 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 392 | |
422d7df4 | 393 | GEM_TRACE("%s fence %llx:%lld, current %d\n", |
e7702760 | 394 | engine->name, |
d9b13c4d | 395 | request->fence.context, request->fence.seqno, |
8892f477 | 396 | hwsp_seqno(request)); |
d9b13c4d | 397 | |
e60a870d | 398 | GEM_BUG_ON(!irqs_disabled()); |
422d7df4 | 399 | lockdep_assert_held(&engine->active.lock); |
e60a870d | 400 | |
d9e61b66 CW |
401 | if (i915_gem_context_is_banned(request->gem_context)) |
402 | i915_request_skip(request, -EIO); | |
403 | ||
ca6e56f6 CW |
404 | /* |
405 | * Are we using semaphores when the gpu is already saturated? | |
406 | * | |
407 | * Using semaphores incurs a cost in having the GPU poll a | |
408 | * memory location, busywaiting for it to change. The continual | |
409 | * memory reads can have a noticeable impact on the rest of the | |
410 | * system with the extra bus traffic, stalling the cpu as it too | |
411 | * tries to access memory across the bus (perf stat -e bus-cycles). | |
412 | * | |
413 | * If we installed a semaphore on this request and we only submit | |
414 | * the request after the signaler completed, that indicates the | |
415 | * system is overloaded and using semaphores at this time only | |
416 | * increases the amount of work we are doing. If so, we disable | |
417 | * further use of semaphores until we are idle again, whence we | |
418 | * optimistically try again. | |
419 | */ | |
420 | if (request->sched.semaphores && | |
421 | i915_sw_fence_signaled(&request->semaphore)) | |
44d89409 | 422 | engine->saturated |= request->sched.semaphores; |
ca6e56f6 | 423 | |
f2d13290 CW |
424 | /* We may be recursing from the signal callback of another i915 fence */ |
425 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
b5773a36 | 426 | |
422d7df4 CW |
427 | list_move_tail(&request->sched.link, &engine->active.requests); |
428 | ||
52c0fdb2 CW |
429 | GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)); |
430 | set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags); | |
b5773a36 | 431 | |
52c0fdb2 | 432 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) && |
0152b3b3 | 433 | !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) && |
52c0fdb2 CW |
434 | !i915_request_enable_breadcrumb(request)) |
435 | intel_engine_queue_breadcrumbs(engine); | |
b5773a36 | 436 | |
e8861964 CW |
437 | __notify_execute_cb(request); |
438 | ||
f2d13290 CW |
439 | spin_unlock(&request->lock); |
440 | ||
85474441 CW |
441 | engine->emit_fini_breadcrumb(request, |
442 | request->ring->vaddr + request->postfix); | |
5590af3e | 443 | |
79ffac85 CW |
444 | engine->serial++; |
445 | ||
e61e0f51 | 446 | trace_i915_request_execute(request); |
d55ac5bf CW |
447 | } |
448 | ||
e61e0f51 | 449 | void i915_request_submit(struct i915_request *request) |
d55ac5bf CW |
450 | { |
451 | struct intel_engine_cs *engine = request->engine; | |
452 | unsigned long flags; | |
23902e49 | 453 | |
d55ac5bf | 454 | /* Will be called from irq-context when using foreign fences. */ |
422d7df4 | 455 | spin_lock_irqsave(&engine->active.lock, flags); |
d55ac5bf | 456 | |
e61e0f51 | 457 | __i915_request_submit(request); |
d55ac5bf | 458 | |
422d7df4 | 459 | spin_unlock_irqrestore(&engine->active.lock, flags); |
d55ac5bf CW |
460 | } |
461 | ||
e61e0f51 | 462 | void __i915_request_unsubmit(struct i915_request *request) |
d55ac5bf | 463 | { |
d6a2289d | 464 | struct intel_engine_cs *engine = request->engine; |
d55ac5bf | 465 | |
b300fde8 | 466 | GEM_TRACE("%s fence %llx:%lld, current %d\n", |
e7702760 | 467 | engine->name, |
d9b13c4d | 468 | request->fence.context, request->fence.seqno, |
8892f477 | 469 | hwsp_seqno(request)); |
d9b13c4d | 470 | |
e60a870d | 471 | GEM_BUG_ON(!irqs_disabled()); |
422d7df4 | 472 | lockdep_assert_held(&engine->active.lock); |
48bc2a4a | 473 | |
e61e0f51 CW |
474 | /* |
475 | * Only unwind in reverse order, required so that the per-context list | |
d6a2289d CW |
476 | * is kept in seqno/ring order. |
477 | */ | |
80b204bc | 478 | |
d6a2289d CW |
479 | /* We may be recursing from the signal callback of another i915 fence */ |
480 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
b5773a36 | 481 | |
d6a2289d | 482 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) |
52c0fdb2 | 483 | i915_request_cancel_breadcrumb(request); |
b5773a36 | 484 | |
52c0fdb2 CW |
485 | GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)); |
486 | clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags); | |
b5773a36 | 487 | |
d6a2289d CW |
488 | spin_unlock(&request->lock); |
489 | ||
dba5a7f3 CW |
490 | /* We've already spun, don't charge on resubmitting. */ |
491 | if (request->sched.semaphores && i915_request_started(request)) { | |
492 | request->sched.attr.priority |= I915_PRIORITY_NOSEMAPHORE; | |
493 | request->sched.semaphores = 0; | |
494 | } | |
495 | ||
e61e0f51 CW |
496 | /* |
497 | * We don't need to wake_up any waiters on request->execute, they | |
d6a2289d | 498 | * will get woken by any other event or us re-adding this request |
e61e0f51 | 499 | * to the engine timeline (__i915_request_submit()). The waiters |
d6a2289d CW |
500 | * should be quite adapt at finding that the request now has a new |
501 | * global_seqno to the one they went to sleep on. | |
502 | */ | |
503 | } | |
504 | ||
e61e0f51 | 505 | void i915_request_unsubmit(struct i915_request *request) |
d6a2289d CW |
506 | { |
507 | struct intel_engine_cs *engine = request->engine; | |
508 | unsigned long flags; | |
509 | ||
510 | /* Will be called from irq-context when using foreign fences. */ | |
422d7df4 | 511 | spin_lock_irqsave(&engine->active.lock, flags); |
d6a2289d | 512 | |
e61e0f51 | 513 | __i915_request_unsubmit(request); |
d6a2289d | 514 | |
422d7df4 | 515 | spin_unlock_irqrestore(&engine->active.lock, flags); |
5590af3e CW |
516 | } |
517 | ||
23902e49 | 518 | static int __i915_sw_fence_call |
d55ac5bf | 519 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
23902e49 | 520 | { |
e61e0f51 | 521 | struct i915_request *request = |
48bc2a4a | 522 | container_of(fence, typeof(*request), submit); |
48bc2a4a CW |
523 | |
524 | switch (state) { | |
525 | case FENCE_COMPLETE: | |
e61e0f51 | 526 | trace_i915_request_submit(request); |
af7a8ffa | 527 | /* |
e61e0f51 CW |
528 | * We need to serialize use of the submit_request() callback |
529 | * with its hotplugging performed during an emergency | |
530 | * i915_gem_set_wedged(). We use the RCU mechanism to mark the | |
531 | * critical section in order to force i915_gem_set_wedged() to | |
532 | * wait until the submit_request() is completed before | |
533 | * proceeding. | |
af7a8ffa DV |
534 | */ |
535 | rcu_read_lock(); | |
d55ac5bf | 536 | request->engine->submit_request(request); |
af7a8ffa | 537 | rcu_read_unlock(); |
48bc2a4a CW |
538 | break; |
539 | ||
540 | case FENCE_FREE: | |
e61e0f51 | 541 | i915_request_put(request); |
48bc2a4a CW |
542 | break; |
543 | } | |
544 | ||
23902e49 CW |
545 | return NOTIFY_DONE; |
546 | } | |
547 | ||
b7404c7e CW |
548 | static int __i915_sw_fence_call |
549 | semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) | |
550 | { | |
551 | struct i915_request *request = | |
552 | container_of(fence, typeof(*request), semaphore); | |
553 | ||
554 | switch (state) { | |
555 | case FENCE_COMPLETE: | |
17db337f | 556 | i915_schedule_bump_priority(request, I915_PRIORITY_NOSEMAPHORE); |
b7404c7e CW |
557 | break; |
558 | ||
559 | case FENCE_FREE: | |
560 | i915_request_put(request); | |
561 | break; | |
562 | } | |
563 | ||
564 | return NOTIFY_DONE; | |
565 | } | |
566 | ||
d22ba0cb CW |
567 | static void ring_retire_requests(struct intel_ring *ring) |
568 | { | |
569 | struct i915_request *rq, *rn; | |
570 | ||
9db0c5ca CW |
571 | list_for_each_entry_safe(rq, rn, &ring->request_list, ring_link) |
572 | if (!i915_request_retire(rq)) | |
d22ba0cb | 573 | break; |
d22ba0cb CW |
574 | } |
575 | ||
576 | static noinline struct i915_request * | |
2ccdf6a1 | 577 | request_alloc_slow(struct intel_context *ce, gfp_t gfp) |
d22ba0cb CW |
578 | { |
579 | struct intel_ring *ring = ce->ring; | |
580 | struct i915_request *rq; | |
581 | ||
582 | if (list_empty(&ring->request_list)) | |
583 | goto out; | |
584 | ||
2ccdf6a1 CW |
585 | if (!gfpflags_allow_blocking(gfp)) |
586 | goto out; | |
587 | ||
9db0c5ca CW |
588 | /* Move our oldest request to the slab-cache (if not in use!) */ |
589 | rq = list_first_entry(&ring->request_list, typeof(*rq), ring_link); | |
590 | i915_request_retire(rq); | |
591 | ||
592 | rq = kmem_cache_alloc(global.slab_requests, | |
593 | gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); | |
594 | if (rq) | |
595 | return rq; | |
596 | ||
d22ba0cb CW |
597 | /* Ratelimit ourselves to prevent oom from malicious clients */ |
598 | rq = list_last_entry(&ring->request_list, typeof(*rq), ring_link); | |
599 | cond_synchronize_rcu(rq->rcustate); | |
600 | ||
601 | /* Retire our old requests in the hope that we free some */ | |
602 | ring_retire_requests(ring); | |
603 | ||
604 | out: | |
2ccdf6a1 | 605 | return kmem_cache_alloc(global.slab_requests, gfp); |
d22ba0cb CW |
606 | } |
607 | ||
e61e0f51 | 608 | struct i915_request * |
2ccdf6a1 | 609 | __i915_request_create(struct intel_context *ce, gfp_t gfp) |
05235c53 | 610 | { |
75d0a7f3 | 611 | struct intel_timeline *tl = ce->timeline; |
ebece753 CW |
612 | struct i915_request *rq; |
613 | u32 seqno; | |
05235c53 CW |
614 | int ret; |
615 | ||
2ccdf6a1 | 616 | might_sleep_if(gfpflags_allow_blocking(gfp)); |
28176ef4 | 617 | |
2ccdf6a1 CW |
618 | /* Check that the caller provided an already pinned context */ |
619 | __intel_context_pin(ce); | |
9b5f4e5e | 620 | |
e61e0f51 CW |
621 | /* |
622 | * Beware: Dragons be flying overhead. | |
5a198b8c CW |
623 | * |
624 | * We use RCU to look up requests in flight. The lookups may | |
625 | * race with the request being allocated from the slab freelist. | |
626 | * That is the request we are writing to here, may be in the process | |
21950ee7 | 627 | * of being read by __i915_active_request_get_rcu(). As such, |
5a198b8c CW |
628 | * we have to be very careful when overwriting the contents. During |
629 | * the RCU lookup, we change chase the request->engine pointer, | |
65e4760e | 630 | * read the request->global_seqno and increment the reference count. |
5a198b8c CW |
631 | * |
632 | * The reference count is incremented atomically. If it is zero, | |
633 | * the lookup knows the request is unallocated and complete. Otherwise, | |
634 | * it is either still in use, or has been reallocated and reset | |
f54d1867 CW |
635 | * with dma_fence_init(). This increment is safe for release as we |
636 | * check that the request we have a reference to and matches the active | |
5a198b8c CW |
637 | * request. |
638 | * | |
639 | * Before we increment the refcount, we chase the request->engine | |
640 | * pointer. We must not call kmem_cache_zalloc() or else we set | |
641 | * that pointer to NULL and cause a crash during the lookup. If | |
642 | * we see the request is completed (based on the value of the | |
643 | * old engine and seqno), the lookup is complete and reports NULL. | |
644 | * If we decide the request is not completed (new engine or seqno), | |
645 | * then we grab a reference and double check that it is still the | |
646 | * active request - which it won't be and restart the lookup. | |
647 | * | |
648 | * Do not use kmem_cache_zalloc() here! | |
649 | */ | |
32eb6bcf | 650 | rq = kmem_cache_alloc(global.slab_requests, |
2ccdf6a1 | 651 | gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); |
e61e0f51 | 652 | if (unlikely(!rq)) { |
2ccdf6a1 | 653 | rq = request_alloc_slow(ce, gfp); |
e61e0f51 | 654 | if (!rq) { |
31c70f97 CW |
655 | ret = -ENOMEM; |
656 | goto err_unreserve; | |
657 | } | |
28176ef4 | 658 | } |
05235c53 | 659 | |
f0c02c1b | 660 | ret = intel_timeline_get_seqno(tl, rq, &seqno); |
ebece753 CW |
661 | if (ret) |
662 | goto err_free; | |
663 | ||
2ccdf6a1 | 664 | rq->i915 = ce->engine->i915; |
1fc44d9b | 665 | rq->hw_context = ce; |
2ccdf6a1 CW |
666 | rq->gem_context = ce->gem_context; |
667 | rq->engine = ce->engine; | |
1fc44d9b | 668 | rq->ring = ce->ring; |
ebece753 | 669 | rq->timeline = tl; |
ebece753 CW |
670 | rq->hwsp_seqno = tl->hwsp_seqno; |
671 | rq->hwsp_cacheline = tl->hwsp_cacheline; | |
672 | rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */ | |
73cb9701 | 673 | |
e61e0f51 | 674 | spin_lock_init(&rq->lock); |
ebece753 CW |
675 | dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, |
676 | tl->fence_context, seqno); | |
04769652 | 677 | |
48bc2a4a | 678 | /* We bump the ref for the fence chain */ |
e61e0f51 | 679 | i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify); |
b7404c7e | 680 | i915_sw_fence_init(&i915_request_get(rq)->semaphore, semaphore_notify); |
5590af3e | 681 | |
0c7112a0 | 682 | i915_sched_node_init(&rq->sched); |
52e54209 | 683 | |
5a198b8c | 684 | /* No zalloc, must clear what we need by hand */ |
e61e0f51 CW |
685 | rq->file_priv = NULL; |
686 | rq->batch = NULL; | |
687 | rq->capture_list = NULL; | |
2a98f4e6 | 688 | rq->flags = 0; |
78e41ddd | 689 | rq->execution_mask = ALL_ENGINES; |
5a198b8c | 690 | |
2ccdf6a1 CW |
691 | INIT_LIST_HEAD(&rq->active_list); |
692 | INIT_LIST_HEAD(&rq->execute_cb); | |
693 | ||
05235c53 CW |
694 | /* |
695 | * Reserve space in the ring buffer for all the commands required to | |
696 | * eventually emit this request. This is to guarantee that the | |
e61e0f51 | 697 | * i915_request_add() call can't fail. Note that the reserve may need |
05235c53 CW |
698 | * to be redone if the request is not actually submitted straight |
699 | * away, e.g. because a GPU scheduler has deferred it. | |
ed2922c0 CW |
700 | * |
701 | * Note that due to how we add reserved_space to intel_ring_begin() | |
702 | * we need to double our request to ensure that if we need to wrap | |
703 | * around inside i915_request_add() there is sufficient space at | |
704 | * the beginning of the ring as well. | |
05235c53 | 705 | */ |
2ccdf6a1 CW |
706 | rq->reserved_space = |
707 | 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32); | |
05235c53 | 708 | |
2113184c CW |
709 | /* |
710 | * Record the position of the start of the request so that | |
d045446d CW |
711 | * should we detect the updated seqno part-way through the |
712 | * GPU processing the request, we never over-estimate the | |
713 | * position of the head. | |
714 | */ | |
e61e0f51 | 715 | rq->head = rq->ring->emit; |
d045446d | 716 | |
2ccdf6a1 | 717 | ret = rq->engine->request_alloc(rq); |
b1c24a61 CW |
718 | if (ret) |
719 | goto err_unwind; | |
2113184c | 720 | |
b3ee09a4 CW |
721 | rq->infix = rq->ring->emit; /* end of header; start of user payload */ |
722 | ||
2ccdf6a1 | 723 | intel_context_mark_active(ce); |
e61e0f51 | 724 | return rq; |
05235c53 | 725 | |
b1c24a61 | 726 | err_unwind: |
1fc44d9b | 727 | ce->ring->emit = rq->head; |
b1c24a61 | 728 | |
1618bdb8 | 729 | /* Make sure we didn't add ourselves to external state before freeing */ |
e61e0f51 | 730 | GEM_BUG_ON(!list_empty(&rq->active_list)); |
0c7112a0 CW |
731 | GEM_BUG_ON(!list_empty(&rq->sched.signalers_list)); |
732 | GEM_BUG_ON(!list_empty(&rq->sched.waiters_list)); | |
1618bdb8 | 733 | |
ebece753 | 734 | err_free: |
32eb6bcf | 735 | kmem_cache_free(global.slab_requests, rq); |
28176ef4 | 736 | err_unreserve: |
1fc44d9b | 737 | intel_context_unpin(ce); |
8e637178 | 738 | return ERR_PTR(ret); |
05235c53 CW |
739 | } |
740 | ||
2ccdf6a1 CW |
741 | struct i915_request * |
742 | i915_request_create(struct intel_context *ce) | |
743 | { | |
744 | struct i915_request *rq; | |
f4d57d83 | 745 | int err; |
2ccdf6a1 | 746 | |
f4d57d83 CW |
747 | err = intel_context_timeline_lock(ce); |
748 | if (err) | |
749 | return ERR_PTR(err); | |
2ccdf6a1 CW |
750 | |
751 | /* Move our oldest request to the slab-cache (if not in use!) */ | |
752 | rq = list_first_entry(&ce->ring->request_list, typeof(*rq), ring_link); | |
9db0c5ca | 753 | if (!list_is_last(&rq->ring_link, &ce->ring->request_list)) |
2ccdf6a1 CW |
754 | i915_request_retire(rq); |
755 | ||
756 | intel_context_enter(ce); | |
757 | rq = __i915_request_create(ce, GFP_KERNEL); | |
758 | intel_context_exit(ce); /* active reference transferred to request */ | |
759 | if (IS_ERR(rq)) | |
760 | goto err_unlock; | |
761 | ||
762 | /* Check that we do not interrupt ourselves with a new request */ | |
75d0a7f3 | 763 | rq->cookie = lockdep_pin_lock(&ce->timeline->mutex); |
2ccdf6a1 CW |
764 | |
765 | return rq; | |
766 | ||
767 | err_unlock: | |
768 | intel_context_timeline_unlock(ce); | |
769 | return rq; | |
770 | } | |
771 | ||
0d90ccb7 CW |
772 | static int |
773 | i915_request_await_start(struct i915_request *rq, struct i915_request *signal) | |
774 | { | |
775 | if (list_is_first(&signal->ring_link, &signal->ring->request_list)) | |
776 | return 0; | |
777 | ||
778 | signal = list_prev_entry(signal, ring_link); | |
f0c02c1b | 779 | if (intel_timeline_sync_is_later(rq->timeline, &signal->fence)) |
0d90ccb7 CW |
780 | return 0; |
781 | ||
782 | return i915_sw_fence_await_dma_fence(&rq->submit, | |
783 | &signal->fence, 0, | |
784 | I915_FENCE_GFP); | |
785 | } | |
786 | ||
ca6e56f6 CW |
787 | static intel_engine_mask_t |
788 | already_busywaiting(struct i915_request *rq) | |
789 | { | |
790 | /* | |
791 | * Polling a semaphore causes bus traffic, delaying other users of | |
792 | * both the GPU and CPU. We want to limit the impact on others, | |
793 | * while taking advantage of early submission to reduce GPU | |
794 | * latency. Therefore we restrict ourselves to not using more | |
795 | * than one semaphore from each source, and not using a semaphore | |
796 | * if we have detected the engine is saturated (i.e. would not be | |
797 | * submitted early and cause bus traffic reading an already passed | |
798 | * semaphore). | |
799 | * | |
800 | * See the are-we-too-late? check in __i915_request_submit(). | |
801 | */ | |
44d89409 | 802 | return rq->sched.semaphores | rq->engine->saturated; |
ca6e56f6 CW |
803 | } |
804 | ||
e8861964 CW |
805 | static int |
806 | emit_semaphore_wait(struct i915_request *to, | |
807 | struct i915_request *from, | |
808 | gfp_t gfp) | |
809 | { | |
810 | u32 hwsp_offset; | |
811 | u32 *cs; | |
812 | int err; | |
813 | ||
814 | GEM_BUG_ON(!from->timeline->has_initial_breadcrumb); | |
815 | GEM_BUG_ON(INTEL_GEN(to->i915) < 8); | |
816 | ||
7881e605 | 817 | /* Just emit the first semaphore we see as request space is limited. */ |
ca6e56f6 | 818 | if (already_busywaiting(to) & from->engine->mask) |
7881e605 CW |
819 | return i915_sw_fence_await_dma_fence(&to->submit, |
820 | &from->fence, 0, | |
821 | I915_FENCE_GFP); | |
822 | ||
0d90ccb7 CW |
823 | err = i915_request_await_start(to, from); |
824 | if (err < 0) | |
825 | return err; | |
826 | ||
c8a0e2ae | 827 | /* Only submit our spinner after the signaler is running! */ |
f71e01a7 | 828 | err = __i915_request_await_execution(to, from, NULL, gfp); |
e8861964 CW |
829 | if (err) |
830 | return err; | |
831 | ||
c8a0e2ae | 832 | /* We need to pin the signaler's HWSP until we are finished reading. */ |
f0c02c1b | 833 | err = intel_timeline_read_hwsp(from, to, &hwsp_offset); |
e8861964 CW |
834 | if (err) |
835 | return err; | |
836 | ||
837 | cs = intel_ring_begin(to, 4); | |
838 | if (IS_ERR(cs)) | |
839 | return PTR_ERR(cs); | |
840 | ||
841 | /* | |
842 | * Using greater-than-or-equal here means we have to worry | |
843 | * about seqno wraparound. To side step that issue, we swap | |
844 | * the timeline HWSP upon wrapping, so that everyone listening | |
845 | * for the old (pre-wrap) values do not see the much smaller | |
846 | * (post-wrap) values than they were expecting (and so wait | |
847 | * forever). | |
848 | */ | |
849 | *cs++ = MI_SEMAPHORE_WAIT | | |
850 | MI_SEMAPHORE_GLOBAL_GTT | | |
851 | MI_SEMAPHORE_POLL | | |
852 | MI_SEMAPHORE_SAD_GTE_SDD; | |
853 | *cs++ = from->fence.seqno; | |
854 | *cs++ = hwsp_offset; | |
855 | *cs++ = 0; | |
856 | ||
857 | intel_ring_advance(to, cs); | |
7881e605 CW |
858 | to->sched.semaphores |= from->engine->mask; |
859 | to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN; | |
e8861964 CW |
860 | return 0; |
861 | } | |
862 | ||
a2bc4695 | 863 | static int |
e61e0f51 | 864 | i915_request_await_request(struct i915_request *to, struct i915_request *from) |
a2bc4695 | 865 | { |
85e17f59 | 866 | int ret; |
a2bc4695 CW |
867 | |
868 | GEM_BUG_ON(to == from); | |
ceae14bd | 869 | GEM_BUG_ON(to->timeline == from->timeline); |
a2bc4695 | 870 | |
e61e0f51 | 871 | if (i915_request_completed(from)) |
ade0b0c9 CW |
872 | return 0; |
873 | ||
52e54209 | 874 | if (to->engine->schedule) { |
32eb6bcf | 875 | ret = i915_sched_node_add_dependency(&to->sched, &from->sched); |
52e54209 CW |
876 | if (ret < 0) |
877 | return ret; | |
878 | } | |
879 | ||
73cb9701 CW |
880 | if (to->engine == from->engine) { |
881 | ret = i915_sw_fence_await_sw_fence_gfp(&to->submit, | |
882 | &from->submit, | |
2abe2f84 | 883 | I915_FENCE_GFP); |
e8861964 CW |
884 | } else if (intel_engine_has_semaphores(to->engine) && |
885 | to->gem_context->sched.priority >= I915_PRIORITY_NORMAL) { | |
886 | ret = emit_semaphore_wait(to, from, I915_FENCE_GFP); | |
6faf5916 CW |
887 | } else { |
888 | ret = i915_sw_fence_await_dma_fence(&to->submit, | |
889 | &from->fence, 0, | |
890 | I915_FENCE_GFP); | |
a2bc4695 | 891 | } |
17db337f CW |
892 | if (ret < 0) |
893 | return ret; | |
894 | ||
895 | if (to->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN) { | |
896 | ret = i915_sw_fence_await_dma_fence(&to->semaphore, | |
897 | &from->fence, 0, | |
898 | I915_FENCE_GFP); | |
899 | if (ret < 0) | |
900 | return ret; | |
901 | } | |
a2bc4695 | 902 | |
17db337f | 903 | return 0; |
a2bc4695 CW |
904 | } |
905 | ||
b52992c0 | 906 | int |
e61e0f51 | 907 | i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) |
b52992c0 | 908 | { |
29ef3fa9 CW |
909 | struct dma_fence **child = &fence; |
910 | unsigned int nchild = 1; | |
b52992c0 | 911 | int ret; |
b52992c0 | 912 | |
e61e0f51 CW |
913 | /* |
914 | * Note that if the fence-array was created in signal-on-any mode, | |
b52992c0 CW |
915 | * we should *not* decompose it into its individual fences. However, |
916 | * we don't currently store which mode the fence-array is operating | |
917 | * in. Fortunately, the only user of signal-on-any is private to | |
918 | * amdgpu and we should not see any incoming fence-array from | |
919 | * sync-file being in signal-on-any mode. | |
920 | */ | |
29ef3fa9 CW |
921 | if (dma_fence_is_array(fence)) { |
922 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
923 | ||
924 | child = array->fences; | |
925 | nchild = array->num_fences; | |
926 | GEM_BUG_ON(!nchild); | |
927 | } | |
b52992c0 | 928 | |
29ef3fa9 CW |
929 | do { |
930 | fence = *child++; | |
931 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
932 | continue; | |
b52992c0 | 933 | |
ceae14bd CW |
934 | /* |
935 | * Requests on the same timeline are explicitly ordered, along | |
e61e0f51 | 936 | * with their dependencies, by i915_request_add() which ensures |
ceae14bd CW |
937 | * that requests are submitted in-order through each ring. |
938 | */ | |
e61e0f51 | 939 | if (fence->context == rq->fence.context) |
ceae14bd CW |
940 | continue; |
941 | ||
47979480 | 942 | /* Squash repeated waits to the same timelines */ |
e61e0f51 | 943 | if (fence->context != rq->i915->mm.unordered_timeline && |
f0c02c1b | 944 | intel_timeline_sync_is_later(rq->timeline, fence)) |
47979480 CW |
945 | continue; |
946 | ||
29ef3fa9 | 947 | if (dma_fence_is_i915(fence)) |
e61e0f51 | 948 | ret = i915_request_await_request(rq, to_request(fence)); |
b52992c0 | 949 | else |
e61e0f51 | 950 | ret = i915_sw_fence_await_dma_fence(&rq->submit, fence, |
29ef3fa9 | 951 | I915_FENCE_TIMEOUT, |
2abe2f84 | 952 | I915_FENCE_GFP); |
b52992c0 CW |
953 | if (ret < 0) |
954 | return ret; | |
47979480 CW |
955 | |
956 | /* Record the latest fence used against each timeline */ | |
e61e0f51 | 957 | if (fence->context != rq->i915->mm.unordered_timeline) |
f0c02c1b | 958 | intel_timeline_sync_set(rq->timeline, fence); |
29ef3fa9 | 959 | } while (--nchild); |
b52992c0 CW |
960 | |
961 | return 0; | |
962 | } | |
963 | ||
f71e01a7 CW |
964 | int |
965 | i915_request_await_execution(struct i915_request *rq, | |
966 | struct dma_fence *fence, | |
967 | void (*hook)(struct i915_request *rq, | |
968 | struct dma_fence *signal)) | |
969 | { | |
970 | struct dma_fence **child = &fence; | |
971 | unsigned int nchild = 1; | |
972 | int ret; | |
973 | ||
974 | if (dma_fence_is_array(fence)) { | |
975 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
976 | ||
977 | /* XXX Error for signal-on-any fence arrays */ | |
978 | ||
979 | child = array->fences; | |
980 | nchild = array->num_fences; | |
981 | GEM_BUG_ON(!nchild); | |
982 | } | |
983 | ||
984 | do { | |
985 | fence = *child++; | |
986 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
987 | continue; | |
988 | ||
989 | /* | |
990 | * We don't squash repeated fence dependencies here as we | |
991 | * want to run our callback in all cases. | |
992 | */ | |
993 | ||
994 | if (dma_fence_is_i915(fence)) | |
995 | ret = __i915_request_await_execution(rq, | |
996 | to_request(fence), | |
997 | hook, | |
998 | I915_FENCE_GFP); | |
999 | else | |
1000 | ret = i915_sw_fence_await_dma_fence(&rq->submit, fence, | |
1001 | I915_FENCE_TIMEOUT, | |
1002 | GFP_KERNEL); | |
1003 | if (ret < 0) | |
1004 | return ret; | |
1005 | } while (--nchild); | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
a2bc4695 | 1010 | /** |
e61e0f51 | 1011 | * i915_request_await_object - set this request to (async) wait upon a bo |
a2bc4695 CW |
1012 | * @to: request we are wishing to use |
1013 | * @obj: object which may be in use on another ring. | |
d8802126 | 1014 | * @write: whether the wait is on behalf of a writer |
a2bc4695 CW |
1015 | * |
1016 | * This code is meant to abstract object synchronization with the GPU. | |
1017 | * Conceptually we serialise writes between engines inside the GPU. | |
1018 | * We only allow one engine to write into a buffer at any time, but | |
1019 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
1020 | * | |
1021 | * - If there is an outstanding write request to the object, the new | |
1022 | * request must wait for it to complete (either CPU or in hw, requests | |
1023 | * on the same ring will be naturally ordered). | |
1024 | * | |
1025 | * - If we are a write request (pending_write_domain is set), the new | |
1026 | * request must wait for outstanding read requests to complete. | |
1027 | * | |
1028 | * Returns 0 if successful, else propagates up the lower layer error. | |
1029 | */ | |
1030 | int | |
e61e0f51 CW |
1031 | i915_request_await_object(struct i915_request *to, |
1032 | struct drm_i915_gem_object *obj, | |
1033 | bool write) | |
a2bc4695 | 1034 | { |
d07f0e59 CW |
1035 | struct dma_fence *excl; |
1036 | int ret = 0; | |
a2bc4695 CW |
1037 | |
1038 | if (write) { | |
d07f0e59 CW |
1039 | struct dma_fence **shared; |
1040 | unsigned int count, i; | |
1041 | ||
ef78f7b1 | 1042 | ret = reservation_object_get_fences_rcu(obj->base.resv, |
d07f0e59 CW |
1043 | &excl, &count, &shared); |
1044 | if (ret) | |
1045 | return ret; | |
1046 | ||
1047 | for (i = 0; i < count; i++) { | |
e61e0f51 | 1048 | ret = i915_request_await_dma_fence(to, shared[i]); |
d07f0e59 CW |
1049 | if (ret) |
1050 | break; | |
1051 | ||
1052 | dma_fence_put(shared[i]); | |
1053 | } | |
1054 | ||
1055 | for (; i < count; i++) | |
1056 | dma_fence_put(shared[i]); | |
1057 | kfree(shared); | |
a2bc4695 | 1058 | } else { |
ef78f7b1 | 1059 | excl = reservation_object_get_excl_rcu(obj->base.resv); |
a2bc4695 CW |
1060 | } |
1061 | ||
d07f0e59 CW |
1062 | if (excl) { |
1063 | if (ret == 0) | |
e61e0f51 | 1064 | ret = i915_request_await_dma_fence(to, excl); |
a2bc4695 | 1065 | |
d07f0e59 | 1066 | dma_fence_put(excl); |
a2bc4695 CW |
1067 | } |
1068 | ||
d07f0e59 | 1069 | return ret; |
a2bc4695 CW |
1070 | } |
1071 | ||
6dd7526f CW |
1072 | void i915_request_skip(struct i915_request *rq, int error) |
1073 | { | |
1074 | void *vaddr = rq->ring->vaddr; | |
1075 | u32 head; | |
1076 | ||
1077 | GEM_BUG_ON(!IS_ERR_VALUE((long)error)); | |
1078 | dma_fence_set_error(&rq->fence, error); | |
1079 | ||
1080 | /* | |
1081 | * As this request likely depends on state from the lost | |
1082 | * context, clear out all the user operations leaving the | |
1083 | * breadcrumb at the end (so we get the fence notifications). | |
1084 | */ | |
1085 | head = rq->infix; | |
1086 | if (rq->postfix < head) { | |
1087 | memset(vaddr + head, 0, rq->ring->size - head); | |
1088 | head = 0; | |
1089 | } | |
1090 | memset(vaddr + head, 0, rq->postfix - head); | |
1091 | } | |
1092 | ||
ea593dbb CW |
1093 | static struct i915_request * |
1094 | __i915_request_add_to_timeline(struct i915_request *rq) | |
1095 | { | |
f0c02c1b | 1096 | struct intel_timeline *timeline = rq->timeline; |
ea593dbb CW |
1097 | struct i915_request *prev; |
1098 | ||
1099 | /* | |
1100 | * Dependency tracking and request ordering along the timeline | |
1101 | * is special cased so that we can eliminate redundant ordering | |
1102 | * operations while building the request (we know that the timeline | |
1103 | * itself is ordered, and here we guarantee it). | |
1104 | * | |
1105 | * As we know we will need to emit tracking along the timeline, | |
1106 | * we embed the hooks into our request struct -- at the cost of | |
1107 | * having to have specialised no-allocation interfaces (which will | |
1108 | * be beneficial elsewhere). | |
1109 | * | |
1110 | * A second benefit to open-coding i915_request_await_request is | |
1111 | * that we can apply a slight variant of the rules specialised | |
1112 | * for timelines that jump between engines (such as virtual engines). | |
1113 | * If we consider the case of virtual engine, we must emit a dma-fence | |
1114 | * to prevent scheduling of the second request until the first is | |
1115 | * complete (to maximise our greedy late load balancing) and this | |
1116 | * precludes optimising to use semaphores serialisation of a single | |
1117 | * timeline across engines. | |
1118 | */ | |
2ccdf6a1 | 1119 | prev = rcu_dereference_protected(timeline->last_request.request, 1); |
ea593dbb CW |
1120 | if (prev && !i915_request_completed(prev)) { |
1121 | if (is_power_of_2(prev->engine->mask | rq->engine->mask)) | |
1122 | i915_sw_fence_await_sw_fence(&rq->submit, | |
1123 | &prev->submit, | |
1124 | &rq->submitq); | |
1125 | else | |
1126 | __i915_sw_fence_await_dma_fence(&rq->submit, | |
1127 | &prev->fence, | |
1128 | &rq->dmaq); | |
1129 | if (rq->engine->schedule) | |
1130 | __i915_sched_node_add_dependency(&rq->sched, | |
1131 | &prev->sched, | |
1132 | &rq->dep, | |
1133 | 0); | |
1134 | } | |
1135 | ||
ea593dbb | 1136 | list_add_tail(&rq->link, &timeline->requests); |
ea593dbb | 1137 | |
2ccdf6a1 CW |
1138 | /* |
1139 | * Make sure that no request gazumped us - if it was allocated after | |
1140 | * our i915_request_alloc() and called __i915_request_add() before | |
1141 | * us, the timeline will hold its seqno which is later than ours. | |
1142 | */ | |
ea593dbb CW |
1143 | GEM_BUG_ON(timeline->seqno != rq->fence.seqno); |
1144 | __i915_active_request_set(&timeline->last_request, rq); | |
1145 | ||
1146 | return prev; | |
1147 | } | |
1148 | ||
05235c53 CW |
1149 | /* |
1150 | * NB: This function is not allowed to fail. Doing so would mean the the | |
1151 | * request is not being tracked for completion but the work itself is | |
1152 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
1153 | */ | |
2ccdf6a1 | 1154 | struct i915_request *__i915_request_commit(struct i915_request *rq) |
05235c53 | 1155 | { |
2ccdf6a1 CW |
1156 | struct intel_engine_cs *engine = rq->engine; |
1157 | struct intel_ring *ring = rq->ring; | |
e61e0f51 | 1158 | struct i915_request *prev; |
73dec95e | 1159 | u32 *cs; |
05235c53 | 1160 | |
dd847a70 | 1161 | GEM_TRACE("%s fence %llx:%lld\n", |
2ccdf6a1 | 1162 | engine->name, rq->fence.context, rq->fence.seqno); |
c781c978 | 1163 | |
05235c53 CW |
1164 | /* |
1165 | * To ensure that this call will not fail, space for its emissions | |
1166 | * should already have been reserved in the ring buffer. Let the ring | |
1167 | * know that it is time to use that space up. | |
1168 | */ | |
2ccdf6a1 CW |
1169 | GEM_BUG_ON(rq->reserved_space > ring->space); |
1170 | rq->reserved_space = 0; | |
05235c53 | 1171 | |
8ac71d1d CW |
1172 | /* |
1173 | * Record the position of the start of the breadcrumb so that | |
05235c53 CW |
1174 | * should we detect the updated seqno part-way through the |
1175 | * GPU processing the request, we never over-estimate the | |
d045446d | 1176 | * position of the ring's HEAD. |
05235c53 | 1177 | */ |
2ccdf6a1 | 1178 | cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw); |
73dec95e | 1179 | GEM_BUG_ON(IS_ERR(cs)); |
2ccdf6a1 | 1180 | rq->postfix = intel_ring_offset(rq, cs); |
05235c53 | 1181 | |
2ccdf6a1 | 1182 | prev = __i915_request_add_to_timeline(rq); |
f2d13290 | 1183 | |
2ccdf6a1 CW |
1184 | list_add_tail(&rq->ring_link, &ring->request_list); |
1185 | if (list_is_first(&rq->ring_link, &ring->request_list)) | |
1186 | list_add(&ring->active_link, &rq->i915->gt.active_rings); | |
2ccdf6a1 | 1187 | rq->emitted_jiffies = jiffies; |
0f25dff6 | 1188 | |
a79ca656 CW |
1189 | return prev; |
1190 | } | |
1191 | ||
1192 | void __i915_request_queue(struct i915_request *rq, | |
1193 | const struct i915_sched_attr *attr) | |
1194 | { | |
8ac71d1d CW |
1195 | /* |
1196 | * Let the backend know a new request has arrived that may need | |
0de9136d CW |
1197 | * to adjust the existing execution schedule due to a high priority |
1198 | * request - i.e. we may want to preempt the current request in order | |
1199 | * to run a high priority dependency chain *before* we can execute this | |
1200 | * request. | |
1201 | * | |
1202 | * This is called before the request is ready to run so that we can | |
1203 | * decide whether to preempt the entire chain so that it is ready to | |
1204 | * run at the earliest possible convenience. | |
1205 | */ | |
2ccdf6a1 | 1206 | i915_sw_fence_commit(&rq->semaphore); |
a79ca656 CW |
1207 | if (attr && rq->engine->schedule) |
1208 | rq->engine->schedule(rq, attr); | |
2ccdf6a1 | 1209 | i915_sw_fence_commit(&rq->submit); |
2ccdf6a1 CW |
1210 | } |
1211 | ||
1212 | void i915_request_add(struct i915_request *rq) | |
1213 | { | |
a79ca656 | 1214 | struct i915_sched_attr attr = rq->gem_context->sched; |
2ccdf6a1 CW |
1215 | struct i915_request *prev; |
1216 | ||
1217 | lockdep_assert_held(&rq->timeline->mutex); | |
1218 | lockdep_unpin_lock(&rq->timeline->mutex, rq->cookie); | |
1219 | ||
1220 | trace_i915_request_add(rq); | |
1221 | ||
1222 | prev = __i915_request_commit(rq); | |
1223 | ||
a79ca656 CW |
1224 | /* |
1225 | * Boost actual workloads past semaphores! | |
1226 | * | |
1227 | * With semaphores we spin on one engine waiting for another, | |
1228 | * simply to reduce the latency of starting our work when | |
1229 | * the signaler completes. However, if there is any other | |
1230 | * work that we could be doing on this engine instead, that | |
1231 | * is better utilisation and will reduce the overall duration | |
1232 | * of the current work. To avoid PI boosting a semaphore | |
1233 | * far in the distance past over useful work, we keep a history | |
1234 | * of any semaphore use along our dependency chain. | |
1235 | */ | |
1236 | if (!(rq->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN)) | |
1237 | attr.priority |= I915_PRIORITY_NOSEMAPHORE; | |
1238 | ||
1239 | /* | |
1240 | * Boost priorities to new clients (new request flows). | |
1241 | * | |
1242 | * Allow interactive/synchronous clients to jump ahead of | |
1243 | * the bulk clients. (FQ_CODEL) | |
1244 | */ | |
1245 | if (list_empty(&rq->sched.signalers_list)) | |
1246 | attr.priority |= I915_PRIORITY_WAIT; | |
1247 | ||
62520e33 | 1248 | local_bh_disable(); |
a79ca656 | 1249 | __i915_request_queue(rq, &attr); |
62520e33 | 1250 | local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ |
a79ca656 | 1251 | |
c22b355f CW |
1252 | /* |
1253 | * In typical scenarios, we do not expect the previous request on | |
1254 | * the timeline to be still tracked by timeline->last_request if it | |
1255 | * has been completed. If the completed request is still here, that | |
1256 | * implies that request retirement is a long way behind submission, | |
1257 | * suggesting that we haven't been retiring frequently enough from | |
1258 | * the combination of retire-before-alloc, waiters and the background | |
1259 | * retirement worker. So if the last request on this timeline was | |
1260 | * already completed, do a catch up pass, flushing the retirement queue | |
1261 | * up to this client. Since we have now moved the heaviest operations | |
1262 | * during retirement onto secondary workers, such as freeing objects | |
1263 | * or contexts, retiring a bunch of requests is mostly list management | |
1264 | * (and cache misses), and so we should not be overly penalizing this | |
1265 | * client by performing excess work, though we may still performing | |
1266 | * work on behalf of others -- but instead we should benefit from | |
1267 | * improved resource management. (Well, that's the theory at least.) | |
1268 | */ | |
e61e0f51 CW |
1269 | if (prev && i915_request_completed(prev)) |
1270 | i915_request_retire_upto(prev); | |
3ef71149 | 1271 | |
2ccdf6a1 | 1272 | mutex_unlock(&rq->timeline->mutex); |
05235c53 CW |
1273 | } |
1274 | ||
1275 | static unsigned long local_clock_us(unsigned int *cpu) | |
1276 | { | |
1277 | unsigned long t; | |
1278 | ||
e61e0f51 CW |
1279 | /* |
1280 | * Cheaply and approximately convert from nanoseconds to microseconds. | |
05235c53 CW |
1281 | * The result and subsequent calculations are also defined in the same |
1282 | * approximate microseconds units. The principal source of timing | |
1283 | * error here is from the simple truncation. | |
1284 | * | |
1285 | * Note that local_clock() is only defined wrt to the current CPU; | |
1286 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1287 | * blocking preemption for the entire busywait, we can detect the CPU | |
1288 | * switch and use that as indicator of system load and a reason to | |
1289 | * stop busywaiting, see busywait_stop(). | |
1290 | */ | |
1291 | *cpu = get_cpu(); | |
1292 | t = local_clock() >> 10; | |
1293 | put_cpu(); | |
1294 | ||
1295 | return t; | |
1296 | } | |
1297 | ||
1298 | static bool busywait_stop(unsigned long timeout, unsigned int cpu) | |
1299 | { | |
1300 | unsigned int this_cpu; | |
1301 | ||
1302 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
1303 | return true; | |
1304 | ||
1305 | return this_cpu != cpu; | |
1306 | } | |
1307 | ||
52c0fdb2 CW |
1308 | static bool __i915_spin_request(const struct i915_request * const rq, |
1309 | int state, unsigned long timeout_us) | |
05235c53 | 1310 | { |
52c0fdb2 | 1311 | unsigned int cpu; |
b2f2f0fc CW |
1312 | |
1313 | /* | |
1314 | * Only wait for the request if we know it is likely to complete. | |
1315 | * | |
1316 | * We don't track the timestamps around requests, nor the average | |
1317 | * request length, so we do not have a good indicator that this | |
1318 | * request will complete within the timeout. What we do know is the | |
52c0fdb2 CW |
1319 | * order in which requests are executed by the context and so we can |
1320 | * tell if the request has been started. If the request is not even | |
1321 | * running yet, it is a fair assumption that it will not complete | |
1322 | * within our relatively short timeout. | |
b2f2f0fc | 1323 | */ |
52c0fdb2 | 1324 | if (!i915_request_is_running(rq)) |
b2f2f0fc CW |
1325 | return false; |
1326 | ||
e61e0f51 CW |
1327 | /* |
1328 | * When waiting for high frequency requests, e.g. during synchronous | |
05235c53 CW |
1329 | * rendering split between the CPU and GPU, the finite amount of time |
1330 | * required to set up the irq and wait upon it limits the response | |
1331 | * rate. By busywaiting on the request completion for a short while we | |
1332 | * can service the high frequency waits as quick as possible. However, | |
1333 | * if it is a slow request, we want to sleep as quickly as possible. | |
1334 | * The tradeoff between waiting and sleeping is roughly the time it | |
1335 | * takes to sleep on a request, on the order of a microsecond. | |
1336 | */ | |
1337 | ||
1338 | timeout_us += local_clock_us(&cpu); | |
1339 | do { | |
52c0fdb2 CW |
1340 | if (i915_request_completed(rq)) |
1341 | return true; | |
c33ed067 | 1342 | |
05235c53 CW |
1343 | if (signal_pending_state(state, current)) |
1344 | break; | |
1345 | ||
1346 | if (busywait_stop(timeout_us, cpu)) | |
1347 | break; | |
1348 | ||
f2f09a4c | 1349 | cpu_relax(); |
05235c53 CW |
1350 | } while (!need_resched()); |
1351 | ||
1352 | return false; | |
1353 | } | |
1354 | ||
52c0fdb2 CW |
1355 | struct request_wait { |
1356 | struct dma_fence_cb cb; | |
1357 | struct task_struct *tsk; | |
1358 | }; | |
1359 | ||
1360 | static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb) | |
1361 | { | |
1362 | struct request_wait *wait = container_of(cb, typeof(*wait), cb); | |
1363 | ||
1364 | wake_up_process(wait->tsk); | |
1365 | } | |
1366 | ||
05235c53 | 1367 | /** |
e532be89 | 1368 | * i915_request_wait - wait until execution of request has finished |
e61e0f51 | 1369 | * @rq: the request to wait upon |
ea746f36 | 1370 | * @flags: how to wait |
e95433c7 CW |
1371 | * @timeout: how long to wait in jiffies |
1372 | * | |
e532be89 | 1373 | * i915_request_wait() waits for the request to be completed, for a |
e95433c7 CW |
1374 | * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an |
1375 | * unbounded wait). | |
05235c53 | 1376 | * |
e95433c7 CW |
1377 | * Returns the remaining time (in jiffies) if the request completed, which may |
1378 | * be zero or -ETIME if the request is unfinished after the timeout expires. | |
1379 | * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is | |
1380 | * pending before the request completes. | |
05235c53 | 1381 | */ |
e61e0f51 | 1382 | long i915_request_wait(struct i915_request *rq, |
e95433c7 CW |
1383 | unsigned int flags, |
1384 | long timeout) | |
05235c53 | 1385 | { |
ea746f36 CW |
1386 | const int state = flags & I915_WAIT_INTERRUPTIBLE ? |
1387 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
52c0fdb2 | 1388 | struct request_wait wait; |
05235c53 CW |
1389 | |
1390 | might_sleep(); | |
e95433c7 | 1391 | GEM_BUG_ON(timeout < 0); |
05235c53 | 1392 | |
6e4e9708 | 1393 | if (dma_fence_is_signaled(&rq->fence)) |
e95433c7 | 1394 | return timeout; |
05235c53 | 1395 | |
e95433c7 CW |
1396 | if (!timeout) |
1397 | return -ETIME; | |
05235c53 | 1398 | |
e61e0f51 | 1399 | trace_i915_request_wait_begin(rq, flags); |
84383d2e CW |
1400 | |
1401 | /* | |
1402 | * We must never wait on the GPU while holding a lock as we | |
1403 | * may need to perform a GPU reset. So while we don't need to | |
1404 | * serialise wait/reset with an explicit lock, we do want | |
1405 | * lockdep to detect potential dependency cycles. | |
1406 | */ | |
cb823ed9 | 1407 | mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_); |
4680816b | 1408 | |
7ce99d24 CW |
1409 | /* |
1410 | * Optimistic spin before touching IRQs. | |
1411 | * | |
1412 | * We may use a rather large value here to offset the penalty of | |
1413 | * switching away from the active task. Frequently, the client will | |
1414 | * wait upon an old swapbuffer to throttle itself to remain within a | |
1415 | * frame of the gpu. If the client is running in lockstep with the gpu, | |
1416 | * then it should not be waiting long at all, and a sleep now will incur | |
1417 | * extra scheduler latency in producing the next frame. To try to | |
1418 | * avoid adding the cost of enabling/disabling the interrupt to the | |
1419 | * short wait, we first spin to see if the request would have completed | |
1420 | * in the time taken to setup the interrupt. | |
1421 | * | |
1422 | * We need upto 5us to enable the irq, and upto 20us to hide the | |
1423 | * scheduler latency of a context switch, ignoring the secondary | |
1424 | * impacts from a context switch such as cache eviction. | |
1425 | * | |
1426 | * The scheme used for low-latency IO is called "hybrid interrupt | |
1427 | * polling". The suggestion there is to sleep until just before you | |
1428 | * expect to be woken by the device interrupt and then poll for its | |
1429 | * completion. That requires having a good predictor for the request | |
1430 | * duration, which we currently lack. | |
1431 | */ | |
1432 | if (CONFIG_DRM_I915_SPIN_REQUEST && | |
6e4e9708 CW |
1433 | __i915_spin_request(rq, state, CONFIG_DRM_I915_SPIN_REQUEST)) { |
1434 | dma_fence_signal(&rq->fence); | |
52c0fdb2 | 1435 | goto out; |
6e4e9708 | 1436 | } |
541ca6ed | 1437 | |
62eb3c24 CW |
1438 | /* |
1439 | * This client is about to stall waiting for the GPU. In many cases | |
1440 | * this is undesirable and limits the throughput of the system, as | |
1441 | * many clients cannot continue processing user input/output whilst | |
1442 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
1443 | * to the GPU load and thus incurs additional latency for the client. | |
1444 | * We can circumvent that by promoting the GPU frequency to maximum | |
1445 | * before we sleep. This makes the GPU throttle up much more quickly | |
1446 | * (good for benchmarks and user experience, e.g. window animations), | |
1447 | * but at a cost of spending more power processing the workload | |
1448 | * (bad for battery). | |
1449 | */ | |
1450 | if (flags & I915_WAIT_PRIORITY) { | |
1451 | if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6) | |
1452 | gen6_rps_boost(rq); | |
52c0fdb2 | 1453 | i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT); |
62eb3c24 | 1454 | } |
4680816b | 1455 | |
52c0fdb2 CW |
1456 | wait.tsk = current; |
1457 | if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake)) | |
1458 | goto out; | |
4680816b | 1459 | |
52c0fdb2 CW |
1460 | for (;;) { |
1461 | set_current_state(state); | |
05235c53 | 1462 | |
ce94bef9 CW |
1463 | if (i915_request_completed(rq)) { |
1464 | dma_fence_signal(&rq->fence); | |
52c0fdb2 | 1465 | break; |
ce94bef9 | 1466 | } |
05235c53 | 1467 | |
05235c53 | 1468 | if (signal_pending_state(state, current)) { |
e95433c7 | 1469 | timeout = -ERESTARTSYS; |
05235c53 CW |
1470 | break; |
1471 | } | |
1472 | ||
e95433c7 CW |
1473 | if (!timeout) { |
1474 | timeout = -ETIME; | |
05235c53 CW |
1475 | break; |
1476 | } | |
1477 | ||
e95433c7 | 1478 | timeout = io_schedule_timeout(timeout); |
05235c53 | 1479 | } |
a49625f9 | 1480 | __set_current_state(TASK_RUNNING); |
05235c53 | 1481 | |
52c0fdb2 CW |
1482 | dma_fence_remove_callback(&rq->fence, &wait.cb); |
1483 | ||
1484 | out: | |
cb823ed9 | 1485 | mutex_release(&rq->engine->gt->reset.mutex.dep_map, 0, _THIS_IP_); |
52c0fdb2 | 1486 | trace_i915_request_wait_end(rq); |
e95433c7 | 1487 | return timeout; |
05235c53 | 1488 | } |
4b8de8e6 | 1489 | |
79ffac85 | 1490 | bool i915_retire_requests(struct drm_i915_private *i915) |
4b8de8e6 | 1491 | { |
643b450a | 1492 | struct intel_ring *ring, *tmp; |
4b8de8e6 | 1493 | |
e61e0f51 | 1494 | lockdep_assert_held(&i915->drm.struct_mutex); |
4b8de8e6 | 1495 | |
65baf0ef CW |
1496 | list_for_each_entry_safe(ring, tmp, |
1497 | &i915->gt.active_rings, active_link) { | |
1498 | intel_ring_get(ring); /* last rq holds reference! */ | |
b887d615 | 1499 | ring_retire_requests(ring); |
65baf0ef CW |
1500 | intel_ring_put(ring); |
1501 | } | |
79ffac85 CW |
1502 | |
1503 | return !list_empty(&i915->gt.active_rings); | |
4b8de8e6 | 1504 | } |
c835c550 CW |
1505 | |
1506 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
1507 | #include "selftests/mock_request.c" | |
e61e0f51 | 1508 | #include "selftests/i915_request.c" |
c835c550 | 1509 | #endif |
32eb6bcf | 1510 | |
103b76ee CW |
1511 | static void i915_global_request_shrink(void) |
1512 | { | |
1513 | kmem_cache_shrink(global.slab_dependencies); | |
1514 | kmem_cache_shrink(global.slab_execute_cbs); | |
1515 | kmem_cache_shrink(global.slab_requests); | |
1516 | } | |
1517 | ||
1518 | static void i915_global_request_exit(void) | |
1519 | { | |
1520 | kmem_cache_destroy(global.slab_dependencies); | |
1521 | kmem_cache_destroy(global.slab_execute_cbs); | |
1522 | kmem_cache_destroy(global.slab_requests); | |
1523 | } | |
1524 | ||
1525 | static struct i915_global_request global = { { | |
1526 | .shrink = i915_global_request_shrink, | |
1527 | .exit = i915_global_request_exit, | |
1528 | } }; | |
1529 | ||
32eb6bcf CW |
1530 | int __init i915_global_request_init(void) |
1531 | { | |
1532 | global.slab_requests = KMEM_CACHE(i915_request, | |
1533 | SLAB_HWCACHE_ALIGN | | |
1534 | SLAB_RECLAIM_ACCOUNT | | |
1535 | SLAB_TYPESAFE_BY_RCU); | |
1536 | if (!global.slab_requests) | |
1537 | return -ENOMEM; | |
1538 | ||
e8861964 CW |
1539 | global.slab_execute_cbs = KMEM_CACHE(execute_cb, |
1540 | SLAB_HWCACHE_ALIGN | | |
1541 | SLAB_RECLAIM_ACCOUNT | | |
1542 | SLAB_TYPESAFE_BY_RCU); | |
1543 | if (!global.slab_execute_cbs) | |
1544 | goto err_requests; | |
1545 | ||
32eb6bcf CW |
1546 | global.slab_dependencies = KMEM_CACHE(i915_dependency, |
1547 | SLAB_HWCACHE_ALIGN | | |
1548 | SLAB_RECLAIM_ACCOUNT); | |
1549 | if (!global.slab_dependencies) | |
e8861964 | 1550 | goto err_execute_cbs; |
32eb6bcf | 1551 | |
103b76ee | 1552 | i915_global_register(&global.base); |
32eb6bcf CW |
1553 | return 0; |
1554 | ||
e8861964 CW |
1555 | err_execute_cbs: |
1556 | kmem_cache_destroy(global.slab_execute_cbs); | |
32eb6bcf CW |
1557 | err_requests: |
1558 | kmem_cache_destroy(global.slab_requests); | |
1559 | return -ENOMEM; | |
1560 | } |