Commit | Line | Data |
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05235c53 CW |
1 | /* |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
b52992c0 | 25 | #include <linux/dma-fence-array.h> |
e8861964 CW |
26 | #include <linux/irq_work.h> |
27 | #include <linux/prefetch.h> | |
e6017571 IM |
28 | #include <linux/sched.h> |
29 | #include <linux/sched/clock.h> | |
f361bf4a | 30 | #include <linux/sched/signal.h> |
fa545cbf | 31 | |
10be98a7 CW |
32 | #include "gem/i915_gem_context.h" |
33 | #include "gt/intel_context.h" | |
34 | ||
21950ee7 | 35 | #include "i915_active.h" |
696173b0 | 36 | #include "i915_drv.h" |
103b76ee | 37 | #include "i915_globals.h" |
a09d9a80 | 38 | #include "i915_trace.h" |
696173b0 | 39 | #include "intel_pm.h" |
05235c53 | 40 | |
e8861964 CW |
41 | struct execute_cb { |
42 | struct list_head link; | |
43 | struct irq_work work; | |
44 | struct i915_sw_fence *fence; | |
f71e01a7 CW |
45 | void (*hook)(struct i915_request *rq, struct dma_fence *signal); |
46 | struct i915_request *signal; | |
e8861964 CW |
47 | }; |
48 | ||
32eb6bcf | 49 | static struct i915_global_request { |
103b76ee | 50 | struct i915_global base; |
32eb6bcf CW |
51 | struct kmem_cache *slab_requests; |
52 | struct kmem_cache *slab_dependencies; | |
e8861964 | 53 | struct kmem_cache *slab_execute_cbs; |
32eb6bcf CW |
54 | } global; |
55 | ||
f54d1867 | 56 | static const char *i915_fence_get_driver_name(struct dma_fence *fence) |
04769652 CW |
57 | { |
58 | return "i915"; | |
59 | } | |
60 | ||
f54d1867 | 61 | static const char *i915_fence_get_timeline_name(struct dma_fence *fence) |
04769652 | 62 | { |
e61e0f51 CW |
63 | /* |
64 | * The timeline struct (as part of the ppgtt underneath a context) | |
05506b5b CW |
65 | * may be freed when the request is no longer in use by the GPU. |
66 | * We could extend the life of a context to beyond that of all | |
67 | * fences, possibly keeping the hw resource around indefinitely, | |
68 | * or we just give them a false name. Since | |
69 | * dma_fence_ops.get_timeline_name is a debug feature, the occasional | |
70 | * lie seems justifiable. | |
71 | */ | |
72 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
73 | return "signaled"; | |
74 | ||
4daffb66 | 75 | return to_request(fence)->gem_context->name ?: "[i915]"; |
04769652 CW |
76 | } |
77 | ||
f54d1867 | 78 | static bool i915_fence_signaled(struct dma_fence *fence) |
04769652 | 79 | { |
e61e0f51 | 80 | return i915_request_completed(to_request(fence)); |
04769652 CW |
81 | } |
82 | ||
f54d1867 | 83 | static bool i915_fence_enable_signaling(struct dma_fence *fence) |
04769652 | 84 | { |
52c0fdb2 | 85 | return i915_request_enable_breadcrumb(to_request(fence)); |
04769652 CW |
86 | } |
87 | ||
f54d1867 | 88 | static signed long i915_fence_wait(struct dma_fence *fence, |
04769652 | 89 | bool interruptible, |
e95433c7 | 90 | signed long timeout) |
04769652 | 91 | { |
62eb3c24 CW |
92 | return i915_request_wait(to_request(fence), |
93 | interruptible | I915_WAIT_PRIORITY, | |
94 | timeout); | |
04769652 CW |
95 | } |
96 | ||
f54d1867 | 97 | static void i915_fence_release(struct dma_fence *fence) |
04769652 | 98 | { |
e61e0f51 | 99 | struct i915_request *rq = to_request(fence); |
04769652 | 100 | |
e61e0f51 CW |
101 | /* |
102 | * The request is put onto a RCU freelist (i.e. the address | |
fc158405 CW |
103 | * is immediately reused), mark the fences as being freed now. |
104 | * Otherwise the debugobjects for the fences are only marked as | |
105 | * freed when the slab cache itself is freed, and so we would get | |
106 | * caught trying to reuse dead objects. | |
107 | */ | |
e61e0f51 | 108 | i915_sw_fence_fini(&rq->submit); |
0c441cb6 | 109 | i915_sw_fence_fini(&rq->semaphore); |
fc158405 | 110 | |
32eb6bcf | 111 | kmem_cache_free(global.slab_requests, rq); |
04769652 CW |
112 | } |
113 | ||
f54d1867 | 114 | const struct dma_fence_ops i915_fence_ops = { |
04769652 CW |
115 | .get_driver_name = i915_fence_get_driver_name, |
116 | .get_timeline_name = i915_fence_get_timeline_name, | |
117 | .enable_signaling = i915_fence_enable_signaling, | |
118 | .signaled = i915_fence_signaled, | |
119 | .wait = i915_fence_wait, | |
120 | .release = i915_fence_release, | |
04769652 CW |
121 | }; |
122 | ||
b87b6c0d CW |
123 | static void irq_execute_cb(struct irq_work *wrk) |
124 | { | |
125 | struct execute_cb *cb = container_of(wrk, typeof(*cb), work); | |
126 | ||
127 | i915_sw_fence_complete(cb->fence); | |
128 | kmem_cache_free(global.slab_execute_cbs, cb); | |
129 | } | |
130 | ||
131 | static void irq_execute_cb_hook(struct irq_work *wrk) | |
132 | { | |
133 | struct execute_cb *cb = container_of(wrk, typeof(*cb), work); | |
134 | ||
135 | cb->hook(container_of(cb->fence, struct i915_request, submit), | |
136 | &cb->signal->fence); | |
137 | i915_request_put(cb->signal); | |
138 | ||
139 | irq_execute_cb(wrk); | |
140 | } | |
141 | ||
142 | static void __notify_execute_cb(struct i915_request *rq) | |
143 | { | |
144 | struct execute_cb *cb; | |
145 | ||
146 | lockdep_assert_held(&rq->lock); | |
147 | ||
148 | if (list_empty(&rq->execute_cb)) | |
149 | return; | |
150 | ||
151 | list_for_each_entry(cb, &rq->execute_cb, link) | |
152 | irq_work_queue(&cb->work); | |
153 | ||
154 | /* | |
155 | * XXX Rollback on __i915_request_unsubmit() | |
156 | * | |
157 | * In the future, perhaps when we have an active time-slicing scheduler, | |
158 | * it will be interesting to unsubmit parallel execution and remove | |
159 | * busywaits from the GPU until their master is restarted. This is | |
160 | * quite hairy, we have to carefully rollback the fence and do a | |
161 | * preempt-to-idle cycle on the target engine, all the while the | |
162 | * master execute_cb may refire. | |
163 | */ | |
164 | INIT_LIST_HEAD(&rq->execute_cb); | |
165 | } | |
166 | ||
05235c53 | 167 | static inline void |
44c22f3f | 168 | remove_from_client(struct i915_request *request) |
05235c53 | 169 | { |
c8659efa | 170 | struct drm_i915_file_private *file_priv; |
05235c53 | 171 | |
77715906 | 172 | if (!READ_ONCE(request->file_priv)) |
05235c53 CW |
173 | return; |
174 | ||
77715906 CW |
175 | rcu_read_lock(); |
176 | file_priv = xchg(&request->file_priv, NULL); | |
177 | if (file_priv) { | |
178 | spin_lock(&file_priv->mm.lock); | |
c8659efa | 179 | list_del(&request->client_link); |
77715906 | 180 | spin_unlock(&file_priv->mm.lock); |
c8659efa | 181 | } |
77715906 | 182 | rcu_read_unlock(); |
05235c53 CW |
183 | } |
184 | ||
e61e0f51 | 185 | static void free_capture_list(struct i915_request *request) |
b0fd47ad | 186 | { |
e61e0f51 | 187 | struct i915_capture_list *capture; |
b0fd47ad CW |
188 | |
189 | capture = request->capture_list; | |
190 | while (capture) { | |
e61e0f51 | 191 | struct i915_capture_list *next = capture->next; |
b0fd47ad CW |
192 | |
193 | kfree(capture); | |
194 | capture = next; | |
195 | } | |
196 | } | |
197 | ||
37fa0de3 CW |
198 | static void remove_from_engine(struct i915_request *rq) |
199 | { | |
200 | struct intel_engine_cs *engine, *locked; | |
201 | ||
202 | /* | |
203 | * Virtual engines complicate acquiring the engine timeline lock, | |
204 | * as their rq->engine pointer is not stable until under that | |
205 | * engine lock. The simple ploy we use is to take the lock then | |
206 | * check that the rq still belongs to the newly locked engine. | |
207 | */ | |
208 | locked = READ_ONCE(rq->engine); | |
209 | spin_lock(&locked->active.lock); | |
210 | while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) { | |
211 | spin_unlock(&locked->active.lock); | |
212 | spin_lock(&engine->active.lock); | |
213 | locked = engine; | |
214 | } | |
215 | list_del(&rq->sched.link); | |
216 | spin_unlock(&locked->active.lock); | |
217 | } | |
218 | ||
9db0c5ca | 219 | static bool i915_request_retire(struct i915_request *rq) |
05235c53 | 220 | { |
21950ee7 | 221 | struct i915_active_request *active, *next; |
fa545cbf | 222 | |
9db0c5ca CW |
223 | if (!i915_request_completed(rq)) |
224 | return false; | |
d9b13c4d | 225 | |
9db0c5ca CW |
226 | GEM_TRACE("%s fence %llx:%lld, current %d\n", |
227 | rq->engine->name, | |
228 | rq->fence.context, rq->fence.seqno, | |
229 | hwsp_seqno(rq)); | |
4c7d62c6 | 230 | |
9db0c5ca CW |
231 | GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); |
232 | trace_i915_request_retire(rq); | |
80b204bc | 233 | |
e5dadff4 CW |
234 | /* |
235 | * We know the GPU must have read the request to have | |
236 | * sent us the seqno + interrupt, so use the position | |
237 | * of tail of the request to update the last known position | |
238 | * of the GPU head. | |
239 | * | |
240 | * Note this requires that we are always called in request | |
241 | * completion order. | |
242 | */ | |
d19d71fc CW |
243 | GEM_BUG_ON(!list_is_first(&rq->link, |
244 | &i915_request_timeline(rq)->requests)); | |
e5dadff4 | 245 | rq->ring->head = rq->postfix; |
b0fd47ad | 246 | |
e61e0f51 CW |
247 | /* |
248 | * Walk through the active list, calling retire on each. This allows | |
fa545cbf CW |
249 | * objects to track their GPU activity and mark themselves as idle |
250 | * when their *last* active request is completed (updating state | |
251 | * tracking lists for eviction, active references for GEM, etc). | |
252 | * | |
253 | * As the ->retire() may free the node, we decouple it first and | |
254 | * pass along the auxiliary information (to avoid dereferencing | |
255 | * the node after the callback). | |
256 | */ | |
9db0c5ca | 257 | list_for_each_entry_safe(active, next, &rq->active_list, link) { |
e61e0f51 CW |
258 | /* |
259 | * In microbenchmarks or focusing upon time inside the kernel, | |
fa545cbf CW |
260 | * we may spend an inordinate amount of time simply handling |
261 | * the retirement of requests and processing their callbacks. | |
262 | * Of which, this loop itself is particularly hot due to the | |
21950ee7 CW |
263 | * cache misses when jumping around the list of |
264 | * i915_active_request. So we try to keep this loop as | |
265 | * streamlined as possible and also prefetch the next | |
266 | * i915_active_request to try and hide the likely cache miss. | |
fa545cbf CW |
267 | */ |
268 | prefetchw(next); | |
269 | ||
270 | INIT_LIST_HEAD(&active->link); | |
0eafec6d | 271 | RCU_INIT_POINTER(active->request, NULL); |
fa545cbf | 272 | |
9db0c5ca | 273 | active->retire(active, rq); |
fa545cbf CW |
274 | } |
275 | ||
9db0c5ca | 276 | local_irq_disable(); |
05235c53 | 277 | |
22b7a426 CW |
278 | /* |
279 | * We only loosely track inflight requests across preemption, | |
280 | * and so we may find ourselves attempting to retire a _completed_ | |
281 | * request that we have removed from the HW and put back on a run | |
282 | * queue. | |
283 | */ | |
37fa0de3 | 284 | remove_from_engine(rq); |
52e54209 | 285 | |
9db0c5ca CW |
286 | spin_lock(&rq->lock); |
287 | i915_request_mark_complete(rq); | |
288 | if (!i915_request_signaled(rq)) | |
289 | dma_fence_signal_locked(&rq->fence); | |
290 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) | |
291 | i915_request_cancel_breadcrumb(rq); | |
2a98f4e6 | 292 | if (i915_request_has_waitboost(rq)) { |
9db0c5ca CW |
293 | GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters)); |
294 | atomic_dec(&rq->i915->gt_pm.rps.num_waiters); | |
295 | } | |
b87b6c0d CW |
296 | if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags)) { |
297 | set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags); | |
298 | __notify_execute_cb(rq); | |
299 | } | |
300 | GEM_BUG_ON(!list_empty(&rq->execute_cb)); | |
9db0c5ca CW |
301 | spin_unlock(&rq->lock); |
302 | ||
303 | local_irq_enable(); | |
52d7f16e | 304 | |
44c22f3f | 305 | remove_from_client(rq); |
422d7df4 | 306 | list_del(&rq->link); |
9db0c5ca | 307 | |
75d0a7f3 CW |
308 | intel_context_exit(rq->hw_context); |
309 | intel_context_unpin(rq->hw_context); | |
310 | ||
9db0c5ca CW |
311 | free_capture_list(rq); |
312 | i915_sched_node_fini(&rq->sched); | |
313 | i915_request_put(rq); | |
314 | ||
315 | return true; | |
05235c53 CW |
316 | } |
317 | ||
e61e0f51 | 318 | void i915_request_retire_upto(struct i915_request *rq) |
05235c53 | 319 | { |
d19d71fc | 320 | struct intel_timeline * const tl = i915_request_timeline(rq); |
e61e0f51 | 321 | struct i915_request *tmp; |
05235c53 | 322 | |
b300fde8 | 323 | GEM_TRACE("%s fence %llx:%lld, current %d\n", |
b887d615 CW |
324 | rq->engine->name, |
325 | rq->fence.context, rq->fence.seqno, | |
8892f477 | 326 | hwsp_seqno(rq)); |
b887d615 | 327 | |
e61e0f51 | 328 | GEM_BUG_ON(!i915_request_completed(rq)); |
4ffd6e0c | 329 | |
05235c53 | 330 | do { |
e5dadff4 | 331 | tmp = list_first_entry(&tl->requests, typeof(*tmp), link); |
9db0c5ca | 332 | } while (i915_request_retire(tmp) && tmp != rq); |
05235c53 CW |
333 | } |
334 | ||
e8861964 | 335 | static int |
f71e01a7 CW |
336 | __i915_request_await_execution(struct i915_request *rq, |
337 | struct i915_request *signal, | |
338 | void (*hook)(struct i915_request *rq, | |
339 | struct dma_fence *signal), | |
340 | gfp_t gfp) | |
e8861964 CW |
341 | { |
342 | struct execute_cb *cb; | |
343 | ||
f71e01a7 CW |
344 | if (i915_request_is_active(signal)) { |
345 | if (hook) | |
346 | hook(rq, &signal->fence); | |
e8861964 | 347 | return 0; |
f71e01a7 | 348 | } |
e8861964 CW |
349 | |
350 | cb = kmem_cache_alloc(global.slab_execute_cbs, gfp); | |
351 | if (!cb) | |
352 | return -ENOMEM; | |
353 | ||
354 | cb->fence = &rq->submit; | |
355 | i915_sw_fence_await(cb->fence); | |
356 | init_irq_work(&cb->work, irq_execute_cb); | |
357 | ||
f71e01a7 CW |
358 | if (hook) { |
359 | cb->hook = hook; | |
360 | cb->signal = i915_request_get(signal); | |
361 | cb->work.func = irq_execute_cb_hook; | |
362 | } | |
363 | ||
e8861964 CW |
364 | spin_lock_irq(&signal->lock); |
365 | if (i915_request_is_active(signal)) { | |
f71e01a7 CW |
366 | if (hook) { |
367 | hook(rq, &signal->fence); | |
368 | i915_request_put(signal); | |
369 | } | |
e8861964 CW |
370 | i915_sw_fence_complete(cb->fence); |
371 | kmem_cache_free(global.slab_execute_cbs, cb); | |
372 | } else { | |
373 | list_add_tail(&cb->link, &signal->execute_cb); | |
374 | } | |
375 | spin_unlock_irq(&signal->lock); | |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
c0bb487d | 380 | bool __i915_request_submit(struct i915_request *request) |
5590af3e | 381 | { |
73cb9701 | 382 | struct intel_engine_cs *engine = request->engine; |
c0bb487d | 383 | bool result = false; |
5590af3e | 384 | |
422d7df4 | 385 | GEM_TRACE("%s fence %llx:%lld, current %d\n", |
e7702760 | 386 | engine->name, |
d9b13c4d | 387 | request->fence.context, request->fence.seqno, |
8892f477 | 388 | hwsp_seqno(request)); |
d9b13c4d | 389 | |
e60a870d | 390 | GEM_BUG_ON(!irqs_disabled()); |
422d7df4 | 391 | lockdep_assert_held(&engine->active.lock); |
e60a870d | 392 | |
c0bb487d CW |
393 | /* |
394 | * With the advent of preempt-to-busy, we frequently encounter | |
395 | * requests that we have unsubmitted from HW, but left running | |
396 | * until the next ack and so have completed in the meantime. On | |
397 | * resubmission of that completed request, we can skip | |
398 | * updating the payload, and execlists can even skip submitting | |
399 | * the request. | |
400 | * | |
401 | * We must remove the request from the caller's priority queue, | |
402 | * and the caller must only call us when the request is in their | |
403 | * priority queue, under the active.lock. This ensures that the | |
404 | * request has *not* yet been retired and we can safely move | |
405 | * the request into the engine->active.list where it will be | |
406 | * dropped upon retiring. (Otherwise if resubmit a *retired* | |
407 | * request, this would be a horrible use-after-free.) | |
408 | */ | |
409 | if (i915_request_completed(request)) | |
410 | goto xfer; | |
411 | ||
d9e61b66 CW |
412 | if (i915_gem_context_is_banned(request->gem_context)) |
413 | i915_request_skip(request, -EIO); | |
414 | ||
ca6e56f6 CW |
415 | /* |
416 | * Are we using semaphores when the gpu is already saturated? | |
417 | * | |
418 | * Using semaphores incurs a cost in having the GPU poll a | |
419 | * memory location, busywaiting for it to change. The continual | |
420 | * memory reads can have a noticeable impact on the rest of the | |
421 | * system with the extra bus traffic, stalling the cpu as it too | |
422 | * tries to access memory across the bus (perf stat -e bus-cycles). | |
423 | * | |
424 | * If we installed a semaphore on this request and we only submit | |
425 | * the request after the signaler completed, that indicates the | |
426 | * system is overloaded and using semaphores at this time only | |
427 | * increases the amount of work we are doing. If so, we disable | |
428 | * further use of semaphores until we are idle again, whence we | |
429 | * optimistically try again. | |
430 | */ | |
431 | if (request->sched.semaphores && | |
432 | i915_sw_fence_signaled(&request->semaphore)) | |
44d89409 | 433 | engine->saturated |= request->sched.semaphores; |
ca6e56f6 | 434 | |
c0bb487d CW |
435 | engine->emit_fini_breadcrumb(request, |
436 | request->ring->vaddr + request->postfix); | |
b5773a36 | 437 | |
c0bb487d CW |
438 | trace_i915_request_execute(request); |
439 | engine->serial++; | |
440 | result = true; | |
422d7df4 | 441 | |
c0bb487d CW |
442 | xfer: /* We may be recursing from the signal callback of another i915 fence */ |
443 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
444 | ||
445 | if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)) | |
446 | list_move_tail(&request->sched.link, &engine->active.requests); | |
b5773a36 | 447 | |
52c0fdb2 | 448 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) && |
0152b3b3 | 449 | !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) && |
52c0fdb2 CW |
450 | !i915_request_enable_breadcrumb(request)) |
451 | intel_engine_queue_breadcrumbs(engine); | |
b5773a36 | 452 | |
e8861964 CW |
453 | __notify_execute_cb(request); |
454 | ||
f2d13290 CW |
455 | spin_unlock(&request->lock); |
456 | ||
c0bb487d | 457 | return result; |
d55ac5bf CW |
458 | } |
459 | ||
e61e0f51 | 460 | void i915_request_submit(struct i915_request *request) |
d55ac5bf CW |
461 | { |
462 | struct intel_engine_cs *engine = request->engine; | |
463 | unsigned long flags; | |
23902e49 | 464 | |
d55ac5bf | 465 | /* Will be called from irq-context when using foreign fences. */ |
422d7df4 | 466 | spin_lock_irqsave(&engine->active.lock, flags); |
d55ac5bf | 467 | |
e61e0f51 | 468 | __i915_request_submit(request); |
d55ac5bf | 469 | |
422d7df4 | 470 | spin_unlock_irqrestore(&engine->active.lock, flags); |
d55ac5bf CW |
471 | } |
472 | ||
e61e0f51 | 473 | void __i915_request_unsubmit(struct i915_request *request) |
d55ac5bf | 474 | { |
d6a2289d | 475 | struct intel_engine_cs *engine = request->engine; |
d55ac5bf | 476 | |
b300fde8 | 477 | GEM_TRACE("%s fence %llx:%lld, current %d\n", |
e7702760 | 478 | engine->name, |
d9b13c4d | 479 | request->fence.context, request->fence.seqno, |
8892f477 | 480 | hwsp_seqno(request)); |
d9b13c4d | 481 | |
e60a870d | 482 | GEM_BUG_ON(!irqs_disabled()); |
422d7df4 | 483 | lockdep_assert_held(&engine->active.lock); |
48bc2a4a | 484 | |
e61e0f51 CW |
485 | /* |
486 | * Only unwind in reverse order, required so that the per-context list | |
d6a2289d CW |
487 | * is kept in seqno/ring order. |
488 | */ | |
80b204bc | 489 | |
d6a2289d CW |
490 | /* We may be recursing from the signal callback of another i915 fence */ |
491 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
b5773a36 | 492 | |
d6a2289d | 493 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) |
52c0fdb2 | 494 | i915_request_cancel_breadcrumb(request); |
b5773a36 | 495 | |
52c0fdb2 CW |
496 | GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)); |
497 | clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags); | |
b5773a36 | 498 | |
d6a2289d CW |
499 | spin_unlock(&request->lock); |
500 | ||
dba5a7f3 CW |
501 | /* We've already spun, don't charge on resubmitting. */ |
502 | if (request->sched.semaphores && i915_request_started(request)) { | |
503 | request->sched.attr.priority |= I915_PRIORITY_NOSEMAPHORE; | |
504 | request->sched.semaphores = 0; | |
505 | } | |
506 | ||
e61e0f51 CW |
507 | /* |
508 | * We don't need to wake_up any waiters on request->execute, they | |
d6a2289d | 509 | * will get woken by any other event or us re-adding this request |
e61e0f51 | 510 | * to the engine timeline (__i915_request_submit()). The waiters |
d6a2289d CW |
511 | * should be quite adapt at finding that the request now has a new |
512 | * global_seqno to the one they went to sleep on. | |
513 | */ | |
514 | } | |
515 | ||
e61e0f51 | 516 | void i915_request_unsubmit(struct i915_request *request) |
d6a2289d CW |
517 | { |
518 | struct intel_engine_cs *engine = request->engine; | |
519 | unsigned long flags; | |
520 | ||
521 | /* Will be called from irq-context when using foreign fences. */ | |
422d7df4 | 522 | spin_lock_irqsave(&engine->active.lock, flags); |
d6a2289d | 523 | |
e61e0f51 | 524 | __i915_request_unsubmit(request); |
d6a2289d | 525 | |
422d7df4 | 526 | spin_unlock_irqrestore(&engine->active.lock, flags); |
5590af3e CW |
527 | } |
528 | ||
23902e49 | 529 | static int __i915_sw_fence_call |
d55ac5bf | 530 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
23902e49 | 531 | { |
e61e0f51 | 532 | struct i915_request *request = |
48bc2a4a | 533 | container_of(fence, typeof(*request), submit); |
48bc2a4a CW |
534 | |
535 | switch (state) { | |
536 | case FENCE_COMPLETE: | |
e61e0f51 | 537 | trace_i915_request_submit(request); |
ef468849 CW |
538 | |
539 | if (unlikely(fence->error)) | |
540 | i915_request_skip(request, fence->error); | |
541 | ||
af7a8ffa | 542 | /* |
e61e0f51 CW |
543 | * We need to serialize use of the submit_request() callback |
544 | * with its hotplugging performed during an emergency | |
545 | * i915_gem_set_wedged(). We use the RCU mechanism to mark the | |
546 | * critical section in order to force i915_gem_set_wedged() to | |
547 | * wait until the submit_request() is completed before | |
548 | * proceeding. | |
af7a8ffa DV |
549 | */ |
550 | rcu_read_lock(); | |
d55ac5bf | 551 | request->engine->submit_request(request); |
af7a8ffa | 552 | rcu_read_unlock(); |
48bc2a4a CW |
553 | break; |
554 | ||
555 | case FENCE_FREE: | |
e61e0f51 | 556 | i915_request_put(request); |
48bc2a4a CW |
557 | break; |
558 | } | |
559 | ||
23902e49 CW |
560 | return NOTIFY_DONE; |
561 | } | |
562 | ||
b7404c7e CW |
563 | static int __i915_sw_fence_call |
564 | semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) | |
565 | { | |
566 | struct i915_request *request = | |
567 | container_of(fence, typeof(*request), semaphore); | |
568 | ||
569 | switch (state) { | |
570 | case FENCE_COMPLETE: | |
17db337f | 571 | i915_schedule_bump_priority(request, I915_PRIORITY_NOSEMAPHORE); |
b7404c7e CW |
572 | break; |
573 | ||
574 | case FENCE_FREE: | |
575 | i915_request_put(request); | |
576 | break; | |
577 | } | |
578 | ||
579 | return NOTIFY_DONE; | |
580 | } | |
581 | ||
e5dadff4 | 582 | static void retire_requests(struct intel_timeline *tl) |
d22ba0cb CW |
583 | { |
584 | struct i915_request *rq, *rn; | |
585 | ||
e5dadff4 | 586 | list_for_each_entry_safe(rq, rn, &tl->requests, link) |
9db0c5ca | 587 | if (!i915_request_retire(rq)) |
d22ba0cb | 588 | break; |
d22ba0cb CW |
589 | } |
590 | ||
591 | static noinline struct i915_request * | |
e5dadff4 | 592 | request_alloc_slow(struct intel_timeline *tl, gfp_t gfp) |
d22ba0cb | 593 | { |
d22ba0cb CW |
594 | struct i915_request *rq; |
595 | ||
e5dadff4 | 596 | if (list_empty(&tl->requests)) |
d22ba0cb CW |
597 | goto out; |
598 | ||
2ccdf6a1 CW |
599 | if (!gfpflags_allow_blocking(gfp)) |
600 | goto out; | |
601 | ||
9db0c5ca | 602 | /* Move our oldest request to the slab-cache (if not in use!) */ |
e5dadff4 | 603 | rq = list_first_entry(&tl->requests, typeof(*rq), link); |
9db0c5ca CW |
604 | i915_request_retire(rq); |
605 | ||
606 | rq = kmem_cache_alloc(global.slab_requests, | |
607 | gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); | |
608 | if (rq) | |
609 | return rq; | |
610 | ||
d22ba0cb | 611 | /* Ratelimit ourselves to prevent oom from malicious clients */ |
e5dadff4 | 612 | rq = list_last_entry(&tl->requests, typeof(*rq), link); |
d22ba0cb CW |
613 | cond_synchronize_rcu(rq->rcustate); |
614 | ||
615 | /* Retire our old requests in the hope that we free some */ | |
e5dadff4 | 616 | retire_requests(tl); |
d22ba0cb CW |
617 | |
618 | out: | |
2ccdf6a1 | 619 | return kmem_cache_alloc(global.slab_requests, gfp); |
d22ba0cb CW |
620 | } |
621 | ||
e61e0f51 | 622 | struct i915_request * |
2ccdf6a1 | 623 | __i915_request_create(struct intel_context *ce, gfp_t gfp) |
05235c53 | 624 | { |
75d0a7f3 | 625 | struct intel_timeline *tl = ce->timeline; |
ebece753 CW |
626 | struct i915_request *rq; |
627 | u32 seqno; | |
05235c53 CW |
628 | int ret; |
629 | ||
2ccdf6a1 | 630 | might_sleep_if(gfpflags_allow_blocking(gfp)); |
28176ef4 | 631 | |
2ccdf6a1 CW |
632 | /* Check that the caller provided an already pinned context */ |
633 | __intel_context_pin(ce); | |
9b5f4e5e | 634 | |
e61e0f51 CW |
635 | /* |
636 | * Beware: Dragons be flying overhead. | |
5a198b8c CW |
637 | * |
638 | * We use RCU to look up requests in flight. The lookups may | |
639 | * race with the request being allocated from the slab freelist. | |
640 | * That is the request we are writing to here, may be in the process | |
21950ee7 | 641 | * of being read by __i915_active_request_get_rcu(). As such, |
5a198b8c CW |
642 | * we have to be very careful when overwriting the contents. During |
643 | * the RCU lookup, we change chase the request->engine pointer, | |
65e4760e | 644 | * read the request->global_seqno and increment the reference count. |
5a198b8c CW |
645 | * |
646 | * The reference count is incremented atomically. If it is zero, | |
647 | * the lookup knows the request is unallocated and complete. Otherwise, | |
648 | * it is either still in use, or has been reallocated and reset | |
f54d1867 CW |
649 | * with dma_fence_init(). This increment is safe for release as we |
650 | * check that the request we have a reference to and matches the active | |
5a198b8c CW |
651 | * request. |
652 | * | |
653 | * Before we increment the refcount, we chase the request->engine | |
654 | * pointer. We must not call kmem_cache_zalloc() or else we set | |
655 | * that pointer to NULL and cause a crash during the lookup. If | |
656 | * we see the request is completed (based on the value of the | |
657 | * old engine and seqno), the lookup is complete and reports NULL. | |
658 | * If we decide the request is not completed (new engine or seqno), | |
659 | * then we grab a reference and double check that it is still the | |
660 | * active request - which it won't be and restart the lookup. | |
661 | * | |
662 | * Do not use kmem_cache_zalloc() here! | |
663 | */ | |
32eb6bcf | 664 | rq = kmem_cache_alloc(global.slab_requests, |
2ccdf6a1 | 665 | gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); |
e61e0f51 | 666 | if (unlikely(!rq)) { |
e5dadff4 | 667 | rq = request_alloc_slow(tl, gfp); |
e61e0f51 | 668 | if (!rq) { |
31c70f97 CW |
669 | ret = -ENOMEM; |
670 | goto err_unreserve; | |
671 | } | |
28176ef4 | 672 | } |
05235c53 | 673 | |
f0c02c1b | 674 | ret = intel_timeline_get_seqno(tl, rq, &seqno); |
ebece753 CW |
675 | if (ret) |
676 | goto err_free; | |
677 | ||
2ccdf6a1 | 678 | rq->i915 = ce->engine->i915; |
1fc44d9b | 679 | rq->hw_context = ce; |
2ccdf6a1 CW |
680 | rq->gem_context = ce->gem_context; |
681 | rq->engine = ce->engine; | |
1fc44d9b | 682 | rq->ring = ce->ring; |
d19d71fc CW |
683 | |
684 | rcu_assign_pointer(rq->timeline, tl); | |
ebece753 CW |
685 | rq->hwsp_seqno = tl->hwsp_seqno; |
686 | rq->hwsp_cacheline = tl->hwsp_cacheline; | |
d19d71fc | 687 | |
ebece753 | 688 | rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */ |
73cb9701 | 689 | |
e61e0f51 | 690 | spin_lock_init(&rq->lock); |
ebece753 CW |
691 | dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, |
692 | tl->fence_context, seqno); | |
04769652 | 693 | |
48bc2a4a | 694 | /* We bump the ref for the fence chain */ |
e61e0f51 | 695 | i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify); |
b7404c7e | 696 | i915_sw_fence_init(&i915_request_get(rq)->semaphore, semaphore_notify); |
5590af3e | 697 | |
0c7112a0 | 698 | i915_sched_node_init(&rq->sched); |
52e54209 | 699 | |
5a198b8c | 700 | /* No zalloc, must clear what we need by hand */ |
e61e0f51 CW |
701 | rq->file_priv = NULL; |
702 | rq->batch = NULL; | |
703 | rq->capture_list = NULL; | |
2a98f4e6 | 704 | rq->flags = 0; |
78e41ddd | 705 | rq->execution_mask = ALL_ENGINES; |
5a198b8c | 706 | |
2ccdf6a1 CW |
707 | INIT_LIST_HEAD(&rq->active_list); |
708 | INIT_LIST_HEAD(&rq->execute_cb); | |
709 | ||
05235c53 CW |
710 | /* |
711 | * Reserve space in the ring buffer for all the commands required to | |
712 | * eventually emit this request. This is to guarantee that the | |
e61e0f51 | 713 | * i915_request_add() call can't fail. Note that the reserve may need |
05235c53 CW |
714 | * to be redone if the request is not actually submitted straight |
715 | * away, e.g. because a GPU scheduler has deferred it. | |
ed2922c0 CW |
716 | * |
717 | * Note that due to how we add reserved_space to intel_ring_begin() | |
718 | * we need to double our request to ensure that if we need to wrap | |
719 | * around inside i915_request_add() there is sufficient space at | |
720 | * the beginning of the ring as well. | |
05235c53 | 721 | */ |
2ccdf6a1 CW |
722 | rq->reserved_space = |
723 | 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32); | |
05235c53 | 724 | |
2113184c CW |
725 | /* |
726 | * Record the position of the start of the request so that | |
d045446d CW |
727 | * should we detect the updated seqno part-way through the |
728 | * GPU processing the request, we never over-estimate the | |
729 | * position of the head. | |
730 | */ | |
e61e0f51 | 731 | rq->head = rq->ring->emit; |
d045446d | 732 | |
2ccdf6a1 | 733 | ret = rq->engine->request_alloc(rq); |
b1c24a61 CW |
734 | if (ret) |
735 | goto err_unwind; | |
2113184c | 736 | |
b3ee09a4 CW |
737 | rq->infix = rq->ring->emit; /* end of header; start of user payload */ |
738 | ||
2ccdf6a1 | 739 | intel_context_mark_active(ce); |
e61e0f51 | 740 | return rq; |
05235c53 | 741 | |
b1c24a61 | 742 | err_unwind: |
1fc44d9b | 743 | ce->ring->emit = rq->head; |
b1c24a61 | 744 | |
1618bdb8 | 745 | /* Make sure we didn't add ourselves to external state before freeing */ |
e61e0f51 | 746 | GEM_BUG_ON(!list_empty(&rq->active_list)); |
0c7112a0 CW |
747 | GEM_BUG_ON(!list_empty(&rq->sched.signalers_list)); |
748 | GEM_BUG_ON(!list_empty(&rq->sched.waiters_list)); | |
1618bdb8 | 749 | |
ebece753 | 750 | err_free: |
32eb6bcf | 751 | kmem_cache_free(global.slab_requests, rq); |
28176ef4 | 752 | err_unreserve: |
1fc44d9b | 753 | intel_context_unpin(ce); |
8e637178 | 754 | return ERR_PTR(ret); |
05235c53 CW |
755 | } |
756 | ||
2ccdf6a1 CW |
757 | struct i915_request * |
758 | i915_request_create(struct intel_context *ce) | |
759 | { | |
760 | struct i915_request *rq; | |
e5dadff4 | 761 | struct intel_timeline *tl; |
2ccdf6a1 | 762 | |
e5dadff4 CW |
763 | tl = intel_context_timeline_lock(ce); |
764 | if (IS_ERR(tl)) | |
765 | return ERR_CAST(tl); | |
2ccdf6a1 CW |
766 | |
767 | /* Move our oldest request to the slab-cache (if not in use!) */ | |
e5dadff4 CW |
768 | rq = list_first_entry(&tl->requests, typeof(*rq), link); |
769 | if (!list_is_last(&rq->link, &tl->requests)) | |
2ccdf6a1 CW |
770 | i915_request_retire(rq); |
771 | ||
772 | intel_context_enter(ce); | |
773 | rq = __i915_request_create(ce, GFP_KERNEL); | |
774 | intel_context_exit(ce); /* active reference transferred to request */ | |
775 | if (IS_ERR(rq)) | |
776 | goto err_unlock; | |
777 | ||
778 | /* Check that we do not interrupt ourselves with a new request */ | |
e5dadff4 | 779 | rq->cookie = lockdep_pin_lock(&tl->mutex); |
2ccdf6a1 CW |
780 | |
781 | return rq; | |
782 | ||
783 | err_unlock: | |
e5dadff4 | 784 | intel_context_timeline_unlock(tl); |
2ccdf6a1 CW |
785 | return rq; |
786 | } | |
787 | ||
0d90ccb7 CW |
788 | static int |
789 | i915_request_await_start(struct i915_request *rq, struct i915_request *signal) | |
790 | { | |
6a79d848 CW |
791 | struct intel_timeline *tl; |
792 | struct dma_fence *fence; | |
793 | int err; | |
0d90ccb7 | 794 | |
6a79d848 CW |
795 | GEM_BUG_ON(i915_request_timeline(rq) == |
796 | rcu_access_pointer(signal->timeline)); | |
797 | ||
798 | rcu_read_lock(); | |
799 | tl = rcu_dereference(signal->timeline); | |
800 | if (i915_request_started(signal) || !kref_get_unless_zero(&tl->kref)) | |
801 | tl = NULL; | |
802 | rcu_read_unlock(); | |
803 | if (!tl) /* already started or maybe even completed */ | |
0d90ccb7 CW |
804 | return 0; |
805 | ||
6a79d848 CW |
806 | fence = ERR_PTR(-EBUSY); |
807 | if (mutex_trylock(&tl->mutex)) { | |
808 | fence = NULL; | |
809 | if (!i915_request_started(signal) && | |
810 | !list_is_first(&signal->link, &tl->requests)) { | |
811 | signal = list_prev_entry(signal, link); | |
812 | fence = dma_fence_get(&signal->fence); | |
813 | } | |
814 | mutex_unlock(&tl->mutex); | |
815 | } | |
816 | intel_timeline_put(tl); | |
817 | if (IS_ERR_OR_NULL(fence)) | |
818 | return PTR_ERR_OR_ZERO(fence); | |
819 | ||
820 | err = 0; | |
821 | if (intel_timeline_sync_is_later(i915_request_timeline(rq), fence)) | |
822 | err = i915_sw_fence_await_dma_fence(&rq->submit, | |
823 | fence, 0, | |
824 | I915_FENCE_GFP); | |
825 | dma_fence_put(fence); | |
826 | ||
827 | return err; | |
0d90ccb7 CW |
828 | } |
829 | ||
ca6e56f6 CW |
830 | static intel_engine_mask_t |
831 | already_busywaiting(struct i915_request *rq) | |
832 | { | |
833 | /* | |
834 | * Polling a semaphore causes bus traffic, delaying other users of | |
835 | * both the GPU and CPU. We want to limit the impact on others, | |
836 | * while taking advantage of early submission to reduce GPU | |
837 | * latency. Therefore we restrict ourselves to not using more | |
838 | * than one semaphore from each source, and not using a semaphore | |
839 | * if we have detected the engine is saturated (i.e. would not be | |
840 | * submitted early and cause bus traffic reading an already passed | |
841 | * semaphore). | |
842 | * | |
843 | * See the are-we-too-late? check in __i915_request_submit(). | |
844 | */ | |
44d89409 | 845 | return rq->sched.semaphores | rq->engine->saturated; |
ca6e56f6 CW |
846 | } |
847 | ||
e8861964 CW |
848 | static int |
849 | emit_semaphore_wait(struct i915_request *to, | |
850 | struct i915_request *from, | |
851 | gfp_t gfp) | |
852 | { | |
c210e85b | 853 | const int has_token = INTEL_GEN(to->i915) >= 12; |
e8861964 | 854 | u32 hwsp_offset; |
c210e85b | 855 | int len; |
e8861964 | 856 | u32 *cs; |
e8861964 | 857 | |
e8861964 CW |
858 | GEM_BUG_ON(INTEL_GEN(to->i915) < 8); |
859 | ||
7881e605 | 860 | /* Just emit the first semaphore we see as request space is limited. */ |
ca6e56f6 | 861 | if (already_busywaiting(to) & from->engine->mask) |
6a79d848 | 862 | goto await_fence; |
7881e605 | 863 | |
6a79d848 CW |
864 | if (i915_request_await_start(to, from) < 0) |
865 | goto await_fence; | |
0d90ccb7 | 866 | |
c8a0e2ae | 867 | /* Only submit our spinner after the signaler is running! */ |
6a79d848 CW |
868 | if (__i915_request_await_execution(to, from, NULL, gfp)) |
869 | goto await_fence; | |
e8861964 | 870 | |
c8a0e2ae | 871 | /* We need to pin the signaler's HWSP until we are finished reading. */ |
6a79d848 CW |
872 | if (intel_timeline_read_hwsp(from, to, &hwsp_offset)) |
873 | goto await_fence; | |
e8861964 | 874 | |
c210e85b CW |
875 | len = 4; |
876 | if (has_token) | |
877 | len += 2; | |
878 | ||
879 | cs = intel_ring_begin(to, len); | |
e8861964 CW |
880 | if (IS_ERR(cs)) |
881 | return PTR_ERR(cs); | |
882 | ||
883 | /* | |
884 | * Using greater-than-or-equal here means we have to worry | |
885 | * about seqno wraparound. To side step that issue, we swap | |
886 | * the timeline HWSP upon wrapping, so that everyone listening | |
887 | * for the old (pre-wrap) values do not see the much smaller | |
888 | * (post-wrap) values than they were expecting (and so wait | |
889 | * forever). | |
890 | */ | |
c210e85b CW |
891 | *cs++ = (MI_SEMAPHORE_WAIT | |
892 | MI_SEMAPHORE_GLOBAL_GTT | | |
893 | MI_SEMAPHORE_POLL | | |
894 | MI_SEMAPHORE_SAD_GTE_SDD) + | |
895 | has_token; | |
e8861964 CW |
896 | *cs++ = from->fence.seqno; |
897 | *cs++ = hwsp_offset; | |
898 | *cs++ = 0; | |
c210e85b CW |
899 | if (has_token) { |
900 | *cs++ = 0; | |
901 | *cs++ = MI_NOOP; | |
902 | } | |
e8861964 CW |
903 | |
904 | intel_ring_advance(to, cs); | |
7881e605 CW |
905 | to->sched.semaphores |= from->engine->mask; |
906 | to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN; | |
e8861964 | 907 | return 0; |
6a79d848 CW |
908 | |
909 | await_fence: | |
910 | return i915_sw_fence_await_dma_fence(&to->submit, | |
911 | &from->fence, 0, | |
912 | I915_FENCE_GFP); | |
e8861964 CW |
913 | } |
914 | ||
a2bc4695 | 915 | static int |
e61e0f51 | 916 | i915_request_await_request(struct i915_request *to, struct i915_request *from) |
a2bc4695 | 917 | { |
85e17f59 | 918 | int ret; |
a2bc4695 CW |
919 | |
920 | GEM_BUG_ON(to == from); | |
ceae14bd | 921 | GEM_BUG_ON(to->timeline == from->timeline); |
a2bc4695 | 922 | |
e61e0f51 | 923 | if (i915_request_completed(from)) |
ade0b0c9 CW |
924 | return 0; |
925 | ||
52e54209 | 926 | if (to->engine->schedule) { |
32eb6bcf | 927 | ret = i915_sched_node_add_dependency(&to->sched, &from->sched); |
52e54209 CW |
928 | if (ret < 0) |
929 | return ret; | |
930 | } | |
931 | ||
73cb9701 CW |
932 | if (to->engine == from->engine) { |
933 | ret = i915_sw_fence_await_sw_fence_gfp(&to->submit, | |
934 | &from->submit, | |
2abe2f84 | 935 | I915_FENCE_GFP); |
e8861964 CW |
936 | } else if (intel_engine_has_semaphores(to->engine) && |
937 | to->gem_context->sched.priority >= I915_PRIORITY_NORMAL) { | |
938 | ret = emit_semaphore_wait(to, from, I915_FENCE_GFP); | |
6faf5916 CW |
939 | } else { |
940 | ret = i915_sw_fence_await_dma_fence(&to->submit, | |
941 | &from->fence, 0, | |
942 | I915_FENCE_GFP); | |
a2bc4695 | 943 | } |
17db337f CW |
944 | if (ret < 0) |
945 | return ret; | |
946 | ||
947 | if (to->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN) { | |
948 | ret = i915_sw_fence_await_dma_fence(&to->semaphore, | |
949 | &from->fence, 0, | |
950 | I915_FENCE_GFP); | |
951 | if (ret < 0) | |
952 | return ret; | |
953 | } | |
a2bc4695 | 954 | |
17db337f | 955 | return 0; |
a2bc4695 CW |
956 | } |
957 | ||
b52992c0 | 958 | int |
e61e0f51 | 959 | i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) |
b52992c0 | 960 | { |
29ef3fa9 CW |
961 | struct dma_fence **child = &fence; |
962 | unsigned int nchild = 1; | |
b52992c0 | 963 | int ret; |
b52992c0 | 964 | |
e61e0f51 CW |
965 | /* |
966 | * Note that if the fence-array was created in signal-on-any mode, | |
b52992c0 CW |
967 | * we should *not* decompose it into its individual fences. However, |
968 | * we don't currently store which mode the fence-array is operating | |
969 | * in. Fortunately, the only user of signal-on-any is private to | |
970 | * amdgpu and we should not see any incoming fence-array from | |
971 | * sync-file being in signal-on-any mode. | |
972 | */ | |
29ef3fa9 CW |
973 | if (dma_fence_is_array(fence)) { |
974 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
975 | ||
976 | child = array->fences; | |
977 | nchild = array->num_fences; | |
978 | GEM_BUG_ON(!nchild); | |
979 | } | |
b52992c0 | 980 | |
29ef3fa9 CW |
981 | do { |
982 | fence = *child++; | |
983 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
984 | continue; | |
b52992c0 | 985 | |
ceae14bd CW |
986 | /* |
987 | * Requests on the same timeline are explicitly ordered, along | |
e61e0f51 | 988 | * with their dependencies, by i915_request_add() which ensures |
ceae14bd CW |
989 | * that requests are submitted in-order through each ring. |
990 | */ | |
e61e0f51 | 991 | if (fence->context == rq->fence.context) |
ceae14bd CW |
992 | continue; |
993 | ||
47979480 | 994 | /* Squash repeated waits to the same timelines */ |
cc337560 | 995 | if (fence->context && |
d19d71fc CW |
996 | intel_timeline_sync_is_later(i915_request_timeline(rq), |
997 | fence)) | |
47979480 CW |
998 | continue; |
999 | ||
29ef3fa9 | 1000 | if (dma_fence_is_i915(fence)) |
e61e0f51 | 1001 | ret = i915_request_await_request(rq, to_request(fence)); |
b52992c0 | 1002 | else |
e61e0f51 | 1003 | ret = i915_sw_fence_await_dma_fence(&rq->submit, fence, |
0f7dc620 | 1004 | fence->context ? I915_FENCE_TIMEOUT : 0, |
2abe2f84 | 1005 | I915_FENCE_GFP); |
b52992c0 CW |
1006 | if (ret < 0) |
1007 | return ret; | |
47979480 CW |
1008 | |
1009 | /* Record the latest fence used against each timeline */ | |
cc337560 | 1010 | if (fence->context) |
d19d71fc CW |
1011 | intel_timeline_sync_set(i915_request_timeline(rq), |
1012 | fence); | |
29ef3fa9 | 1013 | } while (--nchild); |
b52992c0 CW |
1014 | |
1015 | return 0; | |
1016 | } | |
1017 | ||
f71e01a7 CW |
1018 | int |
1019 | i915_request_await_execution(struct i915_request *rq, | |
1020 | struct dma_fence *fence, | |
1021 | void (*hook)(struct i915_request *rq, | |
1022 | struct dma_fence *signal)) | |
1023 | { | |
1024 | struct dma_fence **child = &fence; | |
1025 | unsigned int nchild = 1; | |
1026 | int ret; | |
1027 | ||
1028 | if (dma_fence_is_array(fence)) { | |
1029 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
1030 | ||
1031 | /* XXX Error for signal-on-any fence arrays */ | |
1032 | ||
1033 | child = array->fences; | |
1034 | nchild = array->num_fences; | |
1035 | GEM_BUG_ON(!nchild); | |
1036 | } | |
1037 | ||
1038 | do { | |
1039 | fence = *child++; | |
1040 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
1041 | continue; | |
1042 | ||
1043 | /* | |
1044 | * We don't squash repeated fence dependencies here as we | |
1045 | * want to run our callback in all cases. | |
1046 | */ | |
1047 | ||
1048 | if (dma_fence_is_i915(fence)) | |
1049 | ret = __i915_request_await_execution(rq, | |
1050 | to_request(fence), | |
1051 | hook, | |
1052 | I915_FENCE_GFP); | |
1053 | else | |
1054 | ret = i915_sw_fence_await_dma_fence(&rq->submit, fence, | |
1055 | I915_FENCE_TIMEOUT, | |
1056 | GFP_KERNEL); | |
1057 | if (ret < 0) | |
1058 | return ret; | |
1059 | } while (--nchild); | |
1060 | ||
1061 | return 0; | |
1062 | } | |
1063 | ||
a2bc4695 | 1064 | /** |
e61e0f51 | 1065 | * i915_request_await_object - set this request to (async) wait upon a bo |
a2bc4695 CW |
1066 | * @to: request we are wishing to use |
1067 | * @obj: object which may be in use on another ring. | |
d8802126 | 1068 | * @write: whether the wait is on behalf of a writer |
a2bc4695 CW |
1069 | * |
1070 | * This code is meant to abstract object synchronization with the GPU. | |
1071 | * Conceptually we serialise writes between engines inside the GPU. | |
1072 | * We only allow one engine to write into a buffer at any time, but | |
1073 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
1074 | * | |
1075 | * - If there is an outstanding write request to the object, the new | |
1076 | * request must wait for it to complete (either CPU or in hw, requests | |
1077 | * on the same ring will be naturally ordered). | |
1078 | * | |
1079 | * - If we are a write request (pending_write_domain is set), the new | |
1080 | * request must wait for outstanding read requests to complete. | |
1081 | * | |
1082 | * Returns 0 if successful, else propagates up the lower layer error. | |
1083 | */ | |
1084 | int | |
e61e0f51 CW |
1085 | i915_request_await_object(struct i915_request *to, |
1086 | struct drm_i915_gem_object *obj, | |
1087 | bool write) | |
a2bc4695 | 1088 | { |
d07f0e59 CW |
1089 | struct dma_fence *excl; |
1090 | int ret = 0; | |
a2bc4695 CW |
1091 | |
1092 | if (write) { | |
d07f0e59 CW |
1093 | struct dma_fence **shared; |
1094 | unsigned int count, i; | |
1095 | ||
52791eee | 1096 | ret = dma_resv_get_fences_rcu(obj->base.resv, |
d07f0e59 CW |
1097 | &excl, &count, &shared); |
1098 | if (ret) | |
1099 | return ret; | |
1100 | ||
1101 | for (i = 0; i < count; i++) { | |
e61e0f51 | 1102 | ret = i915_request_await_dma_fence(to, shared[i]); |
d07f0e59 CW |
1103 | if (ret) |
1104 | break; | |
1105 | ||
1106 | dma_fence_put(shared[i]); | |
1107 | } | |
1108 | ||
1109 | for (; i < count; i++) | |
1110 | dma_fence_put(shared[i]); | |
1111 | kfree(shared); | |
a2bc4695 | 1112 | } else { |
52791eee | 1113 | excl = dma_resv_get_excl_rcu(obj->base.resv); |
a2bc4695 CW |
1114 | } |
1115 | ||
d07f0e59 CW |
1116 | if (excl) { |
1117 | if (ret == 0) | |
e61e0f51 | 1118 | ret = i915_request_await_dma_fence(to, excl); |
a2bc4695 | 1119 | |
d07f0e59 | 1120 | dma_fence_put(excl); |
a2bc4695 CW |
1121 | } |
1122 | ||
d07f0e59 | 1123 | return ret; |
a2bc4695 CW |
1124 | } |
1125 | ||
6dd7526f CW |
1126 | void i915_request_skip(struct i915_request *rq, int error) |
1127 | { | |
1128 | void *vaddr = rq->ring->vaddr; | |
1129 | u32 head; | |
1130 | ||
1131 | GEM_BUG_ON(!IS_ERR_VALUE((long)error)); | |
1132 | dma_fence_set_error(&rq->fence, error); | |
1133 | ||
ef468849 CW |
1134 | if (rq->infix == rq->postfix) |
1135 | return; | |
1136 | ||
6dd7526f CW |
1137 | /* |
1138 | * As this request likely depends on state from the lost | |
1139 | * context, clear out all the user operations leaving the | |
1140 | * breadcrumb at the end (so we get the fence notifications). | |
1141 | */ | |
1142 | head = rq->infix; | |
1143 | if (rq->postfix < head) { | |
1144 | memset(vaddr + head, 0, rq->ring->size - head); | |
1145 | head = 0; | |
1146 | } | |
1147 | memset(vaddr + head, 0, rq->postfix - head); | |
ef468849 | 1148 | rq->infix = rq->postfix; |
6dd7526f CW |
1149 | } |
1150 | ||
ea593dbb CW |
1151 | static struct i915_request * |
1152 | __i915_request_add_to_timeline(struct i915_request *rq) | |
1153 | { | |
d19d71fc | 1154 | struct intel_timeline *timeline = i915_request_timeline(rq); |
ea593dbb CW |
1155 | struct i915_request *prev; |
1156 | ||
1157 | /* | |
1158 | * Dependency tracking and request ordering along the timeline | |
1159 | * is special cased so that we can eliminate redundant ordering | |
1160 | * operations while building the request (we know that the timeline | |
1161 | * itself is ordered, and here we guarantee it). | |
1162 | * | |
1163 | * As we know we will need to emit tracking along the timeline, | |
1164 | * we embed the hooks into our request struct -- at the cost of | |
1165 | * having to have specialised no-allocation interfaces (which will | |
1166 | * be beneficial elsewhere). | |
1167 | * | |
1168 | * A second benefit to open-coding i915_request_await_request is | |
1169 | * that we can apply a slight variant of the rules specialised | |
1170 | * for timelines that jump between engines (such as virtual engines). | |
1171 | * If we consider the case of virtual engine, we must emit a dma-fence | |
1172 | * to prevent scheduling of the second request until the first is | |
1173 | * complete (to maximise our greedy late load balancing) and this | |
1174 | * precludes optimising to use semaphores serialisation of a single | |
1175 | * timeline across engines. | |
1176 | */ | |
6c69a454 CW |
1177 | prev = rcu_dereference_protected(timeline->last_request.request, |
1178 | lockdep_is_held(&timeline->mutex)); | |
ea593dbb CW |
1179 | if (prev && !i915_request_completed(prev)) { |
1180 | if (is_power_of_2(prev->engine->mask | rq->engine->mask)) | |
1181 | i915_sw_fence_await_sw_fence(&rq->submit, | |
1182 | &prev->submit, | |
1183 | &rq->submitq); | |
1184 | else | |
1185 | __i915_sw_fence_await_dma_fence(&rq->submit, | |
1186 | &prev->fence, | |
1187 | &rq->dmaq); | |
1188 | if (rq->engine->schedule) | |
1189 | __i915_sched_node_add_dependency(&rq->sched, | |
1190 | &prev->sched, | |
1191 | &rq->dep, | |
1192 | 0); | |
1193 | } | |
1194 | ||
ea593dbb | 1195 | list_add_tail(&rq->link, &timeline->requests); |
ea593dbb | 1196 | |
2ccdf6a1 CW |
1197 | /* |
1198 | * Make sure that no request gazumped us - if it was allocated after | |
1199 | * our i915_request_alloc() and called __i915_request_add() before | |
1200 | * us, the timeline will hold its seqno which is later than ours. | |
1201 | */ | |
ea593dbb CW |
1202 | GEM_BUG_ON(timeline->seqno != rq->fence.seqno); |
1203 | __i915_active_request_set(&timeline->last_request, rq); | |
1204 | ||
1205 | return prev; | |
1206 | } | |
1207 | ||
05235c53 CW |
1208 | /* |
1209 | * NB: This function is not allowed to fail. Doing so would mean the the | |
1210 | * request is not being tracked for completion but the work itself is | |
1211 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
1212 | */ | |
2ccdf6a1 | 1213 | struct i915_request *__i915_request_commit(struct i915_request *rq) |
05235c53 | 1214 | { |
2ccdf6a1 CW |
1215 | struct intel_engine_cs *engine = rq->engine; |
1216 | struct intel_ring *ring = rq->ring; | |
73dec95e | 1217 | u32 *cs; |
05235c53 | 1218 | |
dd847a70 | 1219 | GEM_TRACE("%s fence %llx:%lld\n", |
2ccdf6a1 | 1220 | engine->name, rq->fence.context, rq->fence.seqno); |
c781c978 | 1221 | |
05235c53 CW |
1222 | /* |
1223 | * To ensure that this call will not fail, space for its emissions | |
1224 | * should already have been reserved in the ring buffer. Let the ring | |
1225 | * know that it is time to use that space up. | |
1226 | */ | |
2ccdf6a1 CW |
1227 | GEM_BUG_ON(rq->reserved_space > ring->space); |
1228 | rq->reserved_space = 0; | |
e5dadff4 | 1229 | rq->emitted_jiffies = jiffies; |
05235c53 | 1230 | |
8ac71d1d CW |
1231 | /* |
1232 | * Record the position of the start of the breadcrumb so that | |
05235c53 CW |
1233 | * should we detect the updated seqno part-way through the |
1234 | * GPU processing the request, we never over-estimate the | |
d045446d | 1235 | * position of the ring's HEAD. |
05235c53 | 1236 | */ |
2ccdf6a1 | 1237 | cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw); |
73dec95e | 1238 | GEM_BUG_ON(IS_ERR(cs)); |
2ccdf6a1 | 1239 | rq->postfix = intel_ring_offset(rq, cs); |
05235c53 | 1240 | |
e5dadff4 | 1241 | return __i915_request_add_to_timeline(rq); |
a79ca656 CW |
1242 | } |
1243 | ||
1244 | void __i915_request_queue(struct i915_request *rq, | |
1245 | const struct i915_sched_attr *attr) | |
1246 | { | |
8ac71d1d CW |
1247 | /* |
1248 | * Let the backend know a new request has arrived that may need | |
0de9136d CW |
1249 | * to adjust the existing execution schedule due to a high priority |
1250 | * request - i.e. we may want to preempt the current request in order | |
1251 | * to run a high priority dependency chain *before* we can execute this | |
1252 | * request. | |
1253 | * | |
1254 | * This is called before the request is ready to run so that we can | |
1255 | * decide whether to preempt the entire chain so that it is ready to | |
1256 | * run at the earliest possible convenience. | |
1257 | */ | |
2ccdf6a1 | 1258 | i915_sw_fence_commit(&rq->semaphore); |
a79ca656 CW |
1259 | if (attr && rq->engine->schedule) |
1260 | rq->engine->schedule(rq, attr); | |
2ccdf6a1 | 1261 | i915_sw_fence_commit(&rq->submit); |
2ccdf6a1 CW |
1262 | } |
1263 | ||
1264 | void i915_request_add(struct i915_request *rq) | |
1265 | { | |
a79ca656 | 1266 | struct i915_sched_attr attr = rq->gem_context->sched; |
d19d71fc | 1267 | struct intel_timeline * const tl = i915_request_timeline(rq); |
2ccdf6a1 CW |
1268 | struct i915_request *prev; |
1269 | ||
e5dadff4 CW |
1270 | lockdep_assert_held(&tl->mutex); |
1271 | lockdep_unpin_lock(&tl->mutex, rq->cookie); | |
2ccdf6a1 CW |
1272 | |
1273 | trace_i915_request_add(rq); | |
1274 | ||
1275 | prev = __i915_request_commit(rq); | |
1276 | ||
a79ca656 CW |
1277 | /* |
1278 | * Boost actual workloads past semaphores! | |
1279 | * | |
1280 | * With semaphores we spin on one engine waiting for another, | |
1281 | * simply to reduce the latency of starting our work when | |
1282 | * the signaler completes. However, if there is any other | |
1283 | * work that we could be doing on this engine instead, that | |
1284 | * is better utilisation and will reduce the overall duration | |
1285 | * of the current work. To avoid PI boosting a semaphore | |
1286 | * far in the distance past over useful work, we keep a history | |
1287 | * of any semaphore use along our dependency chain. | |
1288 | */ | |
1289 | if (!(rq->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN)) | |
1290 | attr.priority |= I915_PRIORITY_NOSEMAPHORE; | |
1291 | ||
1292 | /* | |
1293 | * Boost priorities to new clients (new request flows). | |
1294 | * | |
1295 | * Allow interactive/synchronous clients to jump ahead of | |
1296 | * the bulk clients. (FQ_CODEL) | |
1297 | */ | |
1298 | if (list_empty(&rq->sched.signalers_list)) | |
1299 | attr.priority |= I915_PRIORITY_WAIT; | |
1300 | ||
62520e33 | 1301 | local_bh_disable(); |
a79ca656 | 1302 | __i915_request_queue(rq, &attr); |
62520e33 | 1303 | local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ |
a79ca656 | 1304 | |
c22b355f CW |
1305 | /* |
1306 | * In typical scenarios, we do not expect the previous request on | |
1307 | * the timeline to be still tracked by timeline->last_request if it | |
1308 | * has been completed. If the completed request is still here, that | |
1309 | * implies that request retirement is a long way behind submission, | |
1310 | * suggesting that we haven't been retiring frequently enough from | |
1311 | * the combination of retire-before-alloc, waiters and the background | |
1312 | * retirement worker. So if the last request on this timeline was | |
1313 | * already completed, do a catch up pass, flushing the retirement queue | |
1314 | * up to this client. Since we have now moved the heaviest operations | |
1315 | * during retirement onto secondary workers, such as freeing objects | |
1316 | * or contexts, retiring a bunch of requests is mostly list management | |
1317 | * (and cache misses), and so we should not be overly penalizing this | |
1318 | * client by performing excess work, though we may still performing | |
1319 | * work on behalf of others -- but instead we should benefit from | |
1320 | * improved resource management. (Well, that's the theory at least.) | |
1321 | */ | |
d19d71fc CW |
1322 | if (prev && |
1323 | i915_request_completed(prev) && | |
1324 | rcu_access_pointer(prev->timeline) == tl) | |
e61e0f51 | 1325 | i915_request_retire_upto(prev); |
3ef71149 | 1326 | |
e5dadff4 | 1327 | mutex_unlock(&tl->mutex); |
05235c53 CW |
1328 | } |
1329 | ||
1330 | static unsigned long local_clock_us(unsigned int *cpu) | |
1331 | { | |
1332 | unsigned long t; | |
1333 | ||
e61e0f51 CW |
1334 | /* |
1335 | * Cheaply and approximately convert from nanoseconds to microseconds. | |
05235c53 CW |
1336 | * The result and subsequent calculations are also defined in the same |
1337 | * approximate microseconds units. The principal source of timing | |
1338 | * error here is from the simple truncation. | |
1339 | * | |
1340 | * Note that local_clock() is only defined wrt to the current CPU; | |
1341 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1342 | * blocking preemption for the entire busywait, we can detect the CPU | |
1343 | * switch and use that as indicator of system load and a reason to | |
1344 | * stop busywaiting, see busywait_stop(). | |
1345 | */ | |
1346 | *cpu = get_cpu(); | |
1347 | t = local_clock() >> 10; | |
1348 | put_cpu(); | |
1349 | ||
1350 | return t; | |
1351 | } | |
1352 | ||
1353 | static bool busywait_stop(unsigned long timeout, unsigned int cpu) | |
1354 | { | |
1355 | unsigned int this_cpu; | |
1356 | ||
1357 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
1358 | return true; | |
1359 | ||
1360 | return this_cpu != cpu; | |
1361 | } | |
1362 | ||
52c0fdb2 CW |
1363 | static bool __i915_spin_request(const struct i915_request * const rq, |
1364 | int state, unsigned long timeout_us) | |
05235c53 | 1365 | { |
52c0fdb2 | 1366 | unsigned int cpu; |
b2f2f0fc CW |
1367 | |
1368 | /* | |
1369 | * Only wait for the request if we know it is likely to complete. | |
1370 | * | |
1371 | * We don't track the timestamps around requests, nor the average | |
1372 | * request length, so we do not have a good indicator that this | |
1373 | * request will complete within the timeout. What we do know is the | |
52c0fdb2 CW |
1374 | * order in which requests are executed by the context and so we can |
1375 | * tell if the request has been started. If the request is not even | |
1376 | * running yet, it is a fair assumption that it will not complete | |
1377 | * within our relatively short timeout. | |
b2f2f0fc | 1378 | */ |
52c0fdb2 | 1379 | if (!i915_request_is_running(rq)) |
b2f2f0fc CW |
1380 | return false; |
1381 | ||
e61e0f51 CW |
1382 | /* |
1383 | * When waiting for high frequency requests, e.g. during synchronous | |
05235c53 CW |
1384 | * rendering split between the CPU and GPU, the finite amount of time |
1385 | * required to set up the irq and wait upon it limits the response | |
1386 | * rate. By busywaiting on the request completion for a short while we | |
1387 | * can service the high frequency waits as quick as possible. However, | |
1388 | * if it is a slow request, we want to sleep as quickly as possible. | |
1389 | * The tradeoff between waiting and sleeping is roughly the time it | |
1390 | * takes to sleep on a request, on the order of a microsecond. | |
1391 | */ | |
1392 | ||
1393 | timeout_us += local_clock_us(&cpu); | |
1394 | do { | |
52c0fdb2 CW |
1395 | if (i915_request_completed(rq)) |
1396 | return true; | |
c33ed067 | 1397 | |
05235c53 CW |
1398 | if (signal_pending_state(state, current)) |
1399 | break; | |
1400 | ||
1401 | if (busywait_stop(timeout_us, cpu)) | |
1402 | break; | |
1403 | ||
f2f09a4c | 1404 | cpu_relax(); |
05235c53 CW |
1405 | } while (!need_resched()); |
1406 | ||
1407 | return false; | |
1408 | } | |
1409 | ||
52c0fdb2 CW |
1410 | struct request_wait { |
1411 | struct dma_fence_cb cb; | |
1412 | struct task_struct *tsk; | |
1413 | }; | |
1414 | ||
1415 | static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb) | |
1416 | { | |
1417 | struct request_wait *wait = container_of(cb, typeof(*wait), cb); | |
1418 | ||
1419 | wake_up_process(wait->tsk); | |
1420 | } | |
1421 | ||
05235c53 | 1422 | /** |
e532be89 | 1423 | * i915_request_wait - wait until execution of request has finished |
e61e0f51 | 1424 | * @rq: the request to wait upon |
ea746f36 | 1425 | * @flags: how to wait |
e95433c7 CW |
1426 | * @timeout: how long to wait in jiffies |
1427 | * | |
e532be89 | 1428 | * i915_request_wait() waits for the request to be completed, for a |
e95433c7 CW |
1429 | * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an |
1430 | * unbounded wait). | |
05235c53 | 1431 | * |
e95433c7 CW |
1432 | * Returns the remaining time (in jiffies) if the request completed, which may |
1433 | * be zero or -ETIME if the request is unfinished after the timeout expires. | |
1434 | * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is | |
1435 | * pending before the request completes. | |
05235c53 | 1436 | */ |
e61e0f51 | 1437 | long i915_request_wait(struct i915_request *rq, |
e95433c7 CW |
1438 | unsigned int flags, |
1439 | long timeout) | |
05235c53 | 1440 | { |
ea746f36 CW |
1441 | const int state = flags & I915_WAIT_INTERRUPTIBLE ? |
1442 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
52c0fdb2 | 1443 | struct request_wait wait; |
05235c53 CW |
1444 | |
1445 | might_sleep(); | |
e95433c7 | 1446 | GEM_BUG_ON(timeout < 0); |
05235c53 | 1447 | |
6e4e9708 | 1448 | if (dma_fence_is_signaled(&rq->fence)) |
e95433c7 | 1449 | return timeout; |
05235c53 | 1450 | |
e95433c7 CW |
1451 | if (!timeout) |
1452 | return -ETIME; | |
05235c53 | 1453 | |
e61e0f51 | 1454 | trace_i915_request_wait_begin(rq, flags); |
84383d2e CW |
1455 | |
1456 | /* | |
1457 | * We must never wait on the GPU while holding a lock as we | |
1458 | * may need to perform a GPU reset. So while we don't need to | |
1459 | * serialise wait/reset with an explicit lock, we do want | |
1460 | * lockdep to detect potential dependency cycles. | |
1461 | */ | |
cb823ed9 | 1462 | mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_); |
4680816b | 1463 | |
7ce99d24 CW |
1464 | /* |
1465 | * Optimistic spin before touching IRQs. | |
1466 | * | |
1467 | * We may use a rather large value here to offset the penalty of | |
1468 | * switching away from the active task. Frequently, the client will | |
1469 | * wait upon an old swapbuffer to throttle itself to remain within a | |
1470 | * frame of the gpu. If the client is running in lockstep with the gpu, | |
1471 | * then it should not be waiting long at all, and a sleep now will incur | |
1472 | * extra scheduler latency in producing the next frame. To try to | |
1473 | * avoid adding the cost of enabling/disabling the interrupt to the | |
1474 | * short wait, we first spin to see if the request would have completed | |
1475 | * in the time taken to setup the interrupt. | |
1476 | * | |
1477 | * We need upto 5us to enable the irq, and upto 20us to hide the | |
1478 | * scheduler latency of a context switch, ignoring the secondary | |
1479 | * impacts from a context switch such as cache eviction. | |
1480 | * | |
1481 | * The scheme used for low-latency IO is called "hybrid interrupt | |
1482 | * polling". The suggestion there is to sleep until just before you | |
1483 | * expect to be woken by the device interrupt and then poll for its | |
1484 | * completion. That requires having a good predictor for the request | |
1485 | * duration, which we currently lack. | |
1486 | */ | |
1487 | if (CONFIG_DRM_I915_SPIN_REQUEST && | |
6e4e9708 CW |
1488 | __i915_spin_request(rq, state, CONFIG_DRM_I915_SPIN_REQUEST)) { |
1489 | dma_fence_signal(&rq->fence); | |
52c0fdb2 | 1490 | goto out; |
6e4e9708 | 1491 | } |
541ca6ed | 1492 | |
62eb3c24 CW |
1493 | /* |
1494 | * This client is about to stall waiting for the GPU. In many cases | |
1495 | * this is undesirable and limits the throughput of the system, as | |
1496 | * many clients cannot continue processing user input/output whilst | |
1497 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
1498 | * to the GPU load and thus incurs additional latency for the client. | |
1499 | * We can circumvent that by promoting the GPU frequency to maximum | |
1500 | * before we sleep. This makes the GPU throttle up much more quickly | |
1501 | * (good for benchmarks and user experience, e.g. window animations), | |
1502 | * but at a cost of spending more power processing the workload | |
1503 | * (bad for battery). | |
1504 | */ | |
1505 | if (flags & I915_WAIT_PRIORITY) { | |
1506 | if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6) | |
1507 | gen6_rps_boost(rq); | |
52c0fdb2 | 1508 | i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT); |
62eb3c24 | 1509 | } |
4680816b | 1510 | |
52c0fdb2 CW |
1511 | wait.tsk = current; |
1512 | if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake)) | |
1513 | goto out; | |
4680816b | 1514 | |
52c0fdb2 CW |
1515 | for (;;) { |
1516 | set_current_state(state); | |
05235c53 | 1517 | |
ce94bef9 CW |
1518 | if (i915_request_completed(rq)) { |
1519 | dma_fence_signal(&rq->fence); | |
52c0fdb2 | 1520 | break; |
ce94bef9 | 1521 | } |
05235c53 | 1522 | |
05235c53 | 1523 | if (signal_pending_state(state, current)) { |
e95433c7 | 1524 | timeout = -ERESTARTSYS; |
05235c53 CW |
1525 | break; |
1526 | } | |
1527 | ||
e95433c7 CW |
1528 | if (!timeout) { |
1529 | timeout = -ETIME; | |
05235c53 CW |
1530 | break; |
1531 | } | |
1532 | ||
e95433c7 | 1533 | timeout = io_schedule_timeout(timeout); |
05235c53 | 1534 | } |
a49625f9 | 1535 | __set_current_state(TASK_RUNNING); |
05235c53 | 1536 | |
52c0fdb2 CW |
1537 | dma_fence_remove_callback(&rq->fence, &wait.cb); |
1538 | ||
1539 | out: | |
cb823ed9 | 1540 | mutex_release(&rq->engine->gt->reset.mutex.dep_map, 0, _THIS_IP_); |
52c0fdb2 | 1541 | trace_i915_request_wait_end(rq); |
e95433c7 | 1542 | return timeout; |
05235c53 | 1543 | } |
4b8de8e6 | 1544 | |
79ffac85 | 1545 | bool i915_retire_requests(struct drm_i915_private *i915) |
4b8de8e6 | 1546 | { |
e5dadff4 CW |
1547 | struct intel_gt_timelines *timelines = &i915->gt.timelines; |
1548 | struct intel_timeline *tl, *tn; | |
6dcb85a0 | 1549 | unsigned long flags; |
e5dadff4 CW |
1550 | LIST_HEAD(free); |
1551 | ||
6dcb85a0 | 1552 | spin_lock_irqsave(&timelines->lock, flags); |
e5dadff4 CW |
1553 | list_for_each_entry_safe(tl, tn, &timelines->active_list, link) { |
1554 | if (!mutex_trylock(&tl->mutex)) | |
1555 | continue; | |
4b8de8e6 | 1556 | |
e5dadff4 CW |
1557 | intel_timeline_get(tl); |
1558 | GEM_BUG_ON(!tl->active_count); | |
1559 | tl->active_count++; /* pin the list element */ | |
6dcb85a0 | 1560 | spin_unlock_irqrestore(&timelines->lock, flags); |
4b8de8e6 | 1561 | |
e5dadff4 CW |
1562 | retire_requests(tl); |
1563 | ||
6dcb85a0 | 1564 | spin_lock_irqsave(&timelines->lock, flags); |
e5dadff4 CW |
1565 | |
1566 | /* Resume iteration after dropping lock */ | |
1567 | list_safe_reset_next(tl, tn, link); | |
1568 | if (!--tl->active_count) | |
1569 | list_del(&tl->link); | |
1570 | ||
1571 | mutex_unlock(&tl->mutex); | |
1572 | ||
1573 | /* Defer the final release to after the spinlock */ | |
1574 | if (refcount_dec_and_test(&tl->kref.refcount)) { | |
1575 | GEM_BUG_ON(tl->active_count); | |
1576 | list_add(&tl->link, &free); | |
1577 | } | |
65baf0ef | 1578 | } |
6dcb85a0 | 1579 | spin_unlock_irqrestore(&timelines->lock, flags); |
e5dadff4 CW |
1580 | |
1581 | list_for_each_entry_safe(tl, tn, &free, link) | |
1582 | __intel_timeline_free(&tl->kref); | |
79ffac85 | 1583 | |
e5dadff4 | 1584 | return !list_empty(&timelines->active_list); |
4b8de8e6 | 1585 | } |
c835c550 CW |
1586 | |
1587 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
1588 | #include "selftests/mock_request.c" | |
e61e0f51 | 1589 | #include "selftests/i915_request.c" |
c835c550 | 1590 | #endif |
32eb6bcf | 1591 | |
103b76ee CW |
1592 | static void i915_global_request_shrink(void) |
1593 | { | |
1594 | kmem_cache_shrink(global.slab_dependencies); | |
1595 | kmem_cache_shrink(global.slab_execute_cbs); | |
1596 | kmem_cache_shrink(global.slab_requests); | |
1597 | } | |
1598 | ||
1599 | static void i915_global_request_exit(void) | |
1600 | { | |
1601 | kmem_cache_destroy(global.slab_dependencies); | |
1602 | kmem_cache_destroy(global.slab_execute_cbs); | |
1603 | kmem_cache_destroy(global.slab_requests); | |
1604 | } | |
1605 | ||
1606 | static struct i915_global_request global = { { | |
1607 | .shrink = i915_global_request_shrink, | |
1608 | .exit = i915_global_request_exit, | |
1609 | } }; | |
1610 | ||
32eb6bcf CW |
1611 | int __init i915_global_request_init(void) |
1612 | { | |
1613 | global.slab_requests = KMEM_CACHE(i915_request, | |
1614 | SLAB_HWCACHE_ALIGN | | |
1615 | SLAB_RECLAIM_ACCOUNT | | |
1616 | SLAB_TYPESAFE_BY_RCU); | |
1617 | if (!global.slab_requests) | |
1618 | return -ENOMEM; | |
1619 | ||
e8861964 CW |
1620 | global.slab_execute_cbs = KMEM_CACHE(execute_cb, |
1621 | SLAB_HWCACHE_ALIGN | | |
1622 | SLAB_RECLAIM_ACCOUNT | | |
1623 | SLAB_TYPESAFE_BY_RCU); | |
1624 | if (!global.slab_execute_cbs) | |
1625 | goto err_requests; | |
1626 | ||
32eb6bcf CW |
1627 | global.slab_dependencies = KMEM_CACHE(i915_dependency, |
1628 | SLAB_HWCACHE_ALIGN | | |
1629 | SLAB_RECLAIM_ACCOUNT); | |
1630 | if (!global.slab_dependencies) | |
e8861964 | 1631 | goto err_execute_cbs; |
32eb6bcf | 1632 | |
103b76ee | 1633 | i915_global_register(&global.base); |
32eb6bcf CW |
1634 | return 0; |
1635 | ||
e8861964 CW |
1636 | err_execute_cbs: |
1637 | kmem_cache_destroy(global.slab_execute_cbs); | |
32eb6bcf CW |
1638 | err_requests: |
1639 | kmem_cache_destroy(global.slab_requests); | |
1640 | return -ENOMEM; | |
1641 | } |