Commit | Line | Data |
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05235c53 CW |
1 | /* |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
b52992c0 | 25 | #include <linux/dma-fence-array.h> |
3136deb7 | 26 | #include <linux/dma-fence-chain.h> |
e8861964 CW |
27 | #include <linux/irq_work.h> |
28 | #include <linux/prefetch.h> | |
e6017571 IM |
29 | #include <linux/sched.h> |
30 | #include <linux/sched/clock.h> | |
f361bf4a | 31 | #include <linux/sched/signal.h> |
fa545cbf | 32 | |
10be98a7 CW |
33 | #include "gem/i915_gem_context.h" |
34 | #include "gt/intel_context.h" | |
2871ea85 | 35 | #include "gt/intel_ring.h" |
3e7abf81 | 36 | #include "gt/intel_rps.h" |
10be98a7 | 37 | |
21950ee7 | 38 | #include "i915_active.h" |
696173b0 | 39 | #include "i915_drv.h" |
103b76ee | 40 | #include "i915_globals.h" |
a09d9a80 | 41 | #include "i915_trace.h" |
696173b0 | 42 | #include "intel_pm.h" |
05235c53 | 43 | |
e8861964 | 44 | struct execute_cb { |
e8861964 CW |
45 | struct irq_work work; |
46 | struct i915_sw_fence *fence; | |
f71e01a7 CW |
47 | void (*hook)(struct i915_request *rq, struct dma_fence *signal); |
48 | struct i915_request *signal; | |
e8861964 CW |
49 | }; |
50 | ||
32eb6bcf | 51 | static struct i915_global_request { |
103b76ee | 52 | struct i915_global base; |
32eb6bcf | 53 | struct kmem_cache *slab_requests; |
e8861964 | 54 | struct kmem_cache *slab_execute_cbs; |
32eb6bcf CW |
55 | } global; |
56 | ||
f54d1867 | 57 | static const char *i915_fence_get_driver_name(struct dma_fence *fence) |
04769652 | 58 | { |
5a833995 | 59 | return dev_name(to_request(fence)->engine->i915->drm.dev); |
04769652 CW |
60 | } |
61 | ||
f54d1867 | 62 | static const char *i915_fence_get_timeline_name(struct dma_fence *fence) |
04769652 | 63 | { |
9f3ccd40 CW |
64 | const struct i915_gem_context *ctx; |
65 | ||
e61e0f51 CW |
66 | /* |
67 | * The timeline struct (as part of the ppgtt underneath a context) | |
05506b5b CW |
68 | * may be freed when the request is no longer in use by the GPU. |
69 | * We could extend the life of a context to beyond that of all | |
70 | * fences, possibly keeping the hw resource around indefinitely, | |
71 | * or we just give them a false name. Since | |
72 | * dma_fence_ops.get_timeline_name is a debug feature, the occasional | |
73 | * lie seems justifiable. | |
74 | */ | |
75 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
76 | return "signaled"; | |
77 | ||
6a8679c0 | 78 | ctx = i915_request_gem_context(to_request(fence)); |
9f3ccd40 CW |
79 | if (!ctx) |
80 | return "[" DRIVER_NAME "]"; | |
81 | ||
82 | return ctx->name; | |
04769652 CW |
83 | } |
84 | ||
f54d1867 | 85 | static bool i915_fence_signaled(struct dma_fence *fence) |
04769652 | 86 | { |
e61e0f51 | 87 | return i915_request_completed(to_request(fence)); |
04769652 CW |
88 | } |
89 | ||
f54d1867 | 90 | static bool i915_fence_enable_signaling(struct dma_fence *fence) |
04769652 | 91 | { |
52c0fdb2 | 92 | return i915_request_enable_breadcrumb(to_request(fence)); |
04769652 CW |
93 | } |
94 | ||
f54d1867 | 95 | static signed long i915_fence_wait(struct dma_fence *fence, |
04769652 | 96 | bool interruptible, |
e95433c7 | 97 | signed long timeout) |
04769652 | 98 | { |
62eb3c24 CW |
99 | return i915_request_wait(to_request(fence), |
100 | interruptible | I915_WAIT_PRIORITY, | |
101 | timeout); | |
04769652 CW |
102 | } |
103 | ||
43acd651 CW |
104 | struct kmem_cache *i915_request_slab_cache(void) |
105 | { | |
106 | return global.slab_requests; | |
107 | } | |
108 | ||
f54d1867 | 109 | static void i915_fence_release(struct dma_fence *fence) |
04769652 | 110 | { |
e61e0f51 | 111 | struct i915_request *rq = to_request(fence); |
04769652 | 112 | |
e61e0f51 CW |
113 | /* |
114 | * The request is put onto a RCU freelist (i.e. the address | |
fc158405 CW |
115 | * is immediately reused), mark the fences as being freed now. |
116 | * Otherwise the debugobjects for the fences are only marked as | |
117 | * freed when the slab cache itself is freed, and so we would get | |
118 | * caught trying to reuse dead objects. | |
119 | */ | |
e61e0f51 | 120 | i915_sw_fence_fini(&rq->submit); |
0c441cb6 | 121 | i915_sw_fence_fini(&rq->semaphore); |
fc158405 | 122 | |
32a4605b CW |
123 | /* |
124 | * Keep one request on each engine for reserved use under mempressure | |
125 | * | |
126 | * We do not hold a reference to the engine here and so have to be | |
127 | * very careful in what rq->engine we poke. The virtual engine is | |
128 | * referenced via the rq->context and we released that ref during | |
129 | * i915_request_retire(), ergo we must not dereference a virtual | |
130 | * engine here. Not that we would want to, as the only consumer of | |
131 | * the reserved engine->request_pool is the power management parking, | |
132 | * which must-not-fail, and that is only run on the physical engines. | |
133 | * | |
134 | * Since the request must have been executed to be have completed, | |
135 | * we know that it will have been processed by the HW and will | |
136 | * not be unsubmitted again, so rq->engine and rq->execution_mask | |
137 | * at this point is stable. rq->execution_mask will be a single | |
138 | * bit if the last and _only_ engine it could execution on was a | |
139 | * physical engine, if it's multiple bits then it started on and | |
140 | * could still be on a virtual engine. Thus if the mask is not a | |
141 | * power-of-two we assume that rq->engine may still be a virtual | |
142 | * engine and so a dangling invalid pointer that we cannot dereference | |
143 | * | |
144 | * For example, consider the flow of a bonded request through a virtual | |
145 | * engine. The request is created with a wide engine mask (all engines | |
146 | * that we might execute on). On processing the bond, the request mask | |
147 | * is reduced to one or more engines. If the request is subsequently | |
148 | * bound to a single engine, it will then be constrained to only | |
149 | * execute on that engine and never returned to the virtual engine | |
150 | * after timeslicing away, see __unwind_incomplete_requests(). Thus we | |
151 | * know that if the rq->execution_mask is a single bit, rq->engine | |
152 | * can be a physical engine with the exact corresponding mask. | |
153 | */ | |
154 | if (is_power_of_2(rq->execution_mask) && | |
155 | !cmpxchg(&rq->engine->request_pool, NULL, rq)) | |
43acd651 CW |
156 | return; |
157 | ||
32eb6bcf | 158 | kmem_cache_free(global.slab_requests, rq); |
04769652 CW |
159 | } |
160 | ||
f54d1867 | 161 | const struct dma_fence_ops i915_fence_ops = { |
04769652 CW |
162 | .get_driver_name = i915_fence_get_driver_name, |
163 | .get_timeline_name = i915_fence_get_timeline_name, | |
164 | .enable_signaling = i915_fence_enable_signaling, | |
165 | .signaled = i915_fence_signaled, | |
166 | .wait = i915_fence_wait, | |
167 | .release = i915_fence_release, | |
04769652 CW |
168 | }; |
169 | ||
b87b6c0d CW |
170 | static void irq_execute_cb(struct irq_work *wrk) |
171 | { | |
172 | struct execute_cb *cb = container_of(wrk, typeof(*cb), work); | |
173 | ||
174 | i915_sw_fence_complete(cb->fence); | |
175 | kmem_cache_free(global.slab_execute_cbs, cb); | |
176 | } | |
177 | ||
178 | static void irq_execute_cb_hook(struct irq_work *wrk) | |
179 | { | |
180 | struct execute_cb *cb = container_of(wrk, typeof(*cb), work); | |
181 | ||
182 | cb->hook(container_of(cb->fence, struct i915_request, submit), | |
183 | &cb->signal->fence); | |
184 | i915_request_put(cb->signal); | |
185 | ||
186 | irq_execute_cb(wrk); | |
187 | } | |
188 | ||
189 | static void __notify_execute_cb(struct i915_request *rq) | |
190 | { | |
fc0e1270 | 191 | struct execute_cb *cb, *cn; |
b87b6c0d CW |
192 | |
193 | lockdep_assert_held(&rq->lock); | |
194 | ||
98b7067a | 195 | GEM_BUG_ON(!i915_request_is_active(rq)); |
fc0e1270 | 196 | if (llist_empty(&rq->execute_cb)) |
b87b6c0d CW |
197 | return; |
198 | ||
fc0e1270 | 199 | llist_for_each_entry_safe(cb, cn, rq->execute_cb.first, work.llnode) |
b87b6c0d CW |
200 | irq_work_queue(&cb->work); |
201 | ||
202 | /* | |
203 | * XXX Rollback on __i915_request_unsubmit() | |
204 | * | |
205 | * In the future, perhaps when we have an active time-slicing scheduler, | |
206 | * it will be interesting to unsubmit parallel execution and remove | |
207 | * busywaits from the GPU until their master is restarted. This is | |
208 | * quite hairy, we have to carefully rollback the fence and do a | |
209 | * preempt-to-idle cycle on the target engine, all the while the | |
210 | * master execute_cb may refire. | |
211 | */ | |
fc0e1270 | 212 | init_llist_head(&rq->execute_cb); |
b87b6c0d CW |
213 | } |
214 | ||
e61e0f51 | 215 | static void free_capture_list(struct i915_request *request) |
b0fd47ad | 216 | { |
e61e0f51 | 217 | struct i915_capture_list *capture; |
b0fd47ad | 218 | |
67a3acaa | 219 | capture = fetch_and_zero(&request->capture_list); |
b0fd47ad | 220 | while (capture) { |
e61e0f51 | 221 | struct i915_capture_list *next = capture->next; |
b0fd47ad CW |
222 | |
223 | kfree(capture); | |
224 | capture = next; | |
225 | } | |
226 | } | |
227 | ||
89dd019a CW |
228 | static void __i915_request_fill(struct i915_request *rq, u8 val) |
229 | { | |
230 | void *vaddr = rq->ring->vaddr; | |
231 | u32 head; | |
232 | ||
233 | head = rq->infix; | |
234 | if (rq->postfix < head) { | |
235 | memset(vaddr + head, val, rq->ring->size - head); | |
236 | head = 0; | |
237 | } | |
238 | memset(vaddr + head, val, rq->postfix - head); | |
239 | } | |
240 | ||
37fa0de3 CW |
241 | static void remove_from_engine(struct i915_request *rq) |
242 | { | |
243 | struct intel_engine_cs *engine, *locked; | |
244 | ||
245 | /* | |
246 | * Virtual engines complicate acquiring the engine timeline lock, | |
247 | * as their rq->engine pointer is not stable until under that | |
248 | * engine lock. The simple ploy we use is to take the lock then | |
249 | * check that the rq still belongs to the newly locked engine. | |
250 | */ | |
251 | locked = READ_ONCE(rq->engine); | |
1dfffa00 | 252 | spin_lock_irq(&locked->active.lock); |
37fa0de3 CW |
253 | while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) { |
254 | spin_unlock(&locked->active.lock); | |
255 | spin_lock(&engine->active.lock); | |
256 | locked = engine; | |
257 | } | |
67a3acaa | 258 | list_del_init(&rq->sched.link); |
b4a9a149 CW |
259 | clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); |
260 | clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags); | |
1dfffa00 | 261 | spin_unlock_irq(&locked->active.lock); |
37fa0de3 CW |
262 | } |
263 | ||
66101975 | 264 | bool i915_request_retire(struct i915_request *rq) |
05235c53 | 265 | { |
9db0c5ca CW |
266 | if (!i915_request_completed(rq)) |
267 | return false; | |
d9b13c4d | 268 | |
639f2f24 | 269 | RQ_TRACE(rq, "\n"); |
4c7d62c6 | 270 | |
9db0c5ca CW |
271 | GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); |
272 | trace_i915_request_retire(rq); | |
80b204bc | 273 | |
e5dadff4 CW |
274 | /* |
275 | * We know the GPU must have read the request to have | |
276 | * sent us the seqno + interrupt, so use the position | |
277 | * of tail of the request to update the last known position | |
278 | * of the GPU head. | |
279 | * | |
280 | * Note this requires that we are always called in request | |
281 | * completion order. | |
282 | */ | |
d19d71fc CW |
283 | GEM_BUG_ON(!list_is_first(&rq->link, |
284 | &i915_request_timeline(rq)->requests)); | |
89dd019a CW |
285 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) |
286 | /* Poison before we release our space in the ring */ | |
287 | __i915_request_fill(rq, POISON_FREE); | |
e5dadff4 | 288 | rq->ring->head = rq->postfix; |
b0fd47ad | 289 | |
22b7a426 CW |
290 | /* |
291 | * We only loosely track inflight requests across preemption, | |
292 | * and so we may find ourselves attempting to retire a _completed_ | |
293 | * request that we have removed from the HW and put back on a run | |
294 | * queue. | |
295 | */ | |
37fa0de3 | 296 | remove_from_engine(rq); |
52e54209 | 297 | |
1dfffa00 | 298 | spin_lock_irq(&rq->lock); |
9db0c5ca CW |
299 | i915_request_mark_complete(rq); |
300 | if (!i915_request_signaled(rq)) | |
301 | dma_fence_signal_locked(&rq->fence); | |
302 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) | |
303 | i915_request_cancel_breadcrumb(rq); | |
2a98f4e6 | 304 | if (i915_request_has_waitboost(rq)) { |
3e7abf81 AS |
305 | GEM_BUG_ON(!atomic_read(&rq->engine->gt->rps.num_waiters)); |
306 | atomic_dec(&rq->engine->gt->rps.num_waiters); | |
9db0c5ca | 307 | } |
b87b6c0d CW |
308 | if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags)) { |
309 | set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags); | |
310 | __notify_execute_cb(rq); | |
311 | } | |
fc0e1270 | 312 | GEM_BUG_ON(!llist_empty(&rq->execute_cb)); |
1dfffa00 | 313 | spin_unlock_irq(&rq->lock); |
52d7f16e | 314 | |
dff2a11b | 315 | __list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */ |
9db0c5ca | 316 | |
9f3ccd40 CW |
317 | intel_context_exit(rq->context); |
318 | intel_context_unpin(rq->context); | |
75d0a7f3 | 319 | |
9db0c5ca CW |
320 | free_capture_list(rq); |
321 | i915_sched_node_fini(&rq->sched); | |
322 | i915_request_put(rq); | |
323 | ||
324 | return true; | |
05235c53 CW |
325 | } |
326 | ||
e61e0f51 | 327 | void i915_request_retire_upto(struct i915_request *rq) |
05235c53 | 328 | { |
d19d71fc | 329 | struct intel_timeline * const tl = i915_request_timeline(rq); |
e61e0f51 | 330 | struct i915_request *tmp; |
05235c53 | 331 | |
639f2f24 | 332 | RQ_TRACE(rq, "\n"); |
b887d615 | 333 | |
e61e0f51 | 334 | GEM_BUG_ON(!i915_request_completed(rq)); |
4ffd6e0c | 335 | |
05235c53 | 336 | do { |
e5dadff4 | 337 | tmp = list_first_entry(&tl->requests, typeof(*tmp), link); |
9db0c5ca | 338 | } while (i915_request_retire(tmp) && tmp != rq); |
05235c53 CW |
339 | } |
340 | ||
fc0e1270 CW |
341 | static void __llist_add(struct llist_node *node, struct llist_head *head) |
342 | { | |
343 | node->next = head->first; | |
344 | head->first = node; | |
345 | } | |
346 | ||
b55230e5 CW |
347 | static struct i915_request * const * |
348 | __engine_active(struct intel_engine_cs *engine) | |
349 | { | |
350 | return READ_ONCE(engine->execlists.active); | |
351 | } | |
352 | ||
353 | static bool __request_in_flight(const struct i915_request *signal) | |
354 | { | |
355 | struct i915_request * const *port, *rq; | |
356 | bool inflight = false; | |
357 | ||
358 | if (!i915_request_is_ready(signal)) | |
359 | return false; | |
360 | ||
361 | /* | |
362 | * Even if we have unwound the request, it may still be on | |
363 | * the GPU (preempt-to-busy). If that request is inside an | |
364 | * unpreemptible critical section, it will not be removed. Some | |
365 | * GPU functions may even be stuck waiting for the paired request | |
366 | * (__await_execution) to be submitted and cannot be preempted | |
367 | * until the bond is executing. | |
368 | * | |
369 | * As we know that there are always preemption points between | |
370 | * requests, we know that only the currently executing request | |
371 | * may be still active even though we have cleared the flag. | |
372 | * However, we can't rely on our tracking of ELSP[0] to known | |
373 | * which request is currently active and so maybe stuck, as | |
374 | * the tracking maybe an event behind. Instead assume that | |
375 | * if the context is still inflight, then it is still active | |
376 | * even if the active flag has been cleared. | |
377 | */ | |
378 | if (!intel_context_inflight(signal->context)) | |
379 | return false; | |
380 | ||
381 | rcu_read_lock(); | |
382 | for (port = __engine_active(signal->engine); (rq = *port); port++) { | |
383 | if (rq->context == signal->context) { | |
384 | inflight = i915_seqno_passed(rq->fence.seqno, | |
385 | signal->fence.seqno); | |
386 | break; | |
387 | } | |
388 | } | |
389 | rcu_read_unlock(); | |
390 | ||
391 | return inflight; | |
392 | } | |
393 | ||
e8861964 | 394 | static int |
c81471f5 CW |
395 | __await_execution(struct i915_request *rq, |
396 | struct i915_request *signal, | |
397 | void (*hook)(struct i915_request *rq, | |
398 | struct dma_fence *signal), | |
399 | gfp_t gfp) | |
e8861964 CW |
400 | { |
401 | struct execute_cb *cb; | |
402 | ||
f71e01a7 CW |
403 | if (i915_request_is_active(signal)) { |
404 | if (hook) | |
405 | hook(rq, &signal->fence); | |
e8861964 | 406 | return 0; |
f71e01a7 | 407 | } |
e8861964 CW |
408 | |
409 | cb = kmem_cache_alloc(global.slab_execute_cbs, gfp); | |
410 | if (!cb) | |
411 | return -ENOMEM; | |
412 | ||
413 | cb->fence = &rq->submit; | |
414 | i915_sw_fence_await(cb->fence); | |
415 | init_irq_work(&cb->work, irq_execute_cb); | |
416 | ||
f71e01a7 CW |
417 | if (hook) { |
418 | cb->hook = hook; | |
419 | cb->signal = i915_request_get(signal); | |
420 | cb->work.func = irq_execute_cb_hook; | |
421 | } | |
422 | ||
e8861964 | 423 | spin_lock_irq(&signal->lock); |
b55230e5 | 424 | if (i915_request_is_active(signal) || __request_in_flight(signal)) { |
f71e01a7 CW |
425 | if (hook) { |
426 | hook(rq, &signal->fence); | |
427 | i915_request_put(signal); | |
428 | } | |
e8861964 CW |
429 | i915_sw_fence_complete(cb->fence); |
430 | kmem_cache_free(global.slab_execute_cbs, cb); | |
431 | } else { | |
fc0e1270 | 432 | __llist_add(&cb->work.llnode, &signal->execute_cb); |
e8861964 CW |
433 | } |
434 | spin_unlock_irq(&signal->lock); | |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
36e191f0 CW |
439 | static bool fatal_error(int error) |
440 | { | |
441 | switch (error) { | |
442 | case 0: /* not an error! */ | |
443 | case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */ | |
444 | case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */ | |
445 | return false; | |
446 | default: | |
447 | return true; | |
448 | } | |
449 | } | |
450 | ||
451 | void __i915_request_skip(struct i915_request *rq) | |
452 | { | |
453 | GEM_BUG_ON(!fatal_error(rq->fence.error)); | |
454 | ||
455 | if (rq->infix == rq->postfix) | |
456 | return; | |
457 | ||
458 | /* | |
459 | * As this request likely depends on state from the lost | |
460 | * context, clear out all the user operations leaving the | |
461 | * breadcrumb at the end (so we get the fence notifications). | |
462 | */ | |
463 | __i915_request_fill(rq, 0); | |
464 | rq->infix = rq->postfix; | |
465 | } | |
466 | ||
467 | void i915_request_set_error_once(struct i915_request *rq, int error) | |
468 | { | |
469 | int old; | |
470 | ||
471 | GEM_BUG_ON(!IS_ERR_VALUE((long)error)); | |
472 | ||
473 | if (i915_request_signaled(rq)) | |
474 | return; | |
475 | ||
476 | old = READ_ONCE(rq->fence.error); | |
477 | do { | |
478 | if (fatal_error(old)) | |
479 | return; | |
480 | } while (!try_cmpxchg(&rq->fence.error, &old, error)); | |
481 | } | |
482 | ||
c0bb487d | 483 | bool __i915_request_submit(struct i915_request *request) |
5590af3e | 484 | { |
73cb9701 | 485 | struct intel_engine_cs *engine = request->engine; |
c0bb487d | 486 | bool result = false; |
5590af3e | 487 | |
639f2f24 | 488 | RQ_TRACE(request, "\n"); |
d9b13c4d | 489 | |
e60a870d | 490 | GEM_BUG_ON(!irqs_disabled()); |
422d7df4 | 491 | lockdep_assert_held(&engine->active.lock); |
e60a870d | 492 | |
c0bb487d CW |
493 | /* |
494 | * With the advent of preempt-to-busy, we frequently encounter | |
495 | * requests that we have unsubmitted from HW, but left running | |
496 | * until the next ack and so have completed in the meantime. On | |
497 | * resubmission of that completed request, we can skip | |
498 | * updating the payload, and execlists can even skip submitting | |
499 | * the request. | |
500 | * | |
501 | * We must remove the request from the caller's priority queue, | |
502 | * and the caller must only call us when the request is in their | |
503 | * priority queue, under the active.lock. This ensures that the | |
504 | * request has *not* yet been retired and we can safely move | |
505 | * the request into the engine->active.list where it will be | |
506 | * dropped upon retiring. (Otherwise if resubmit a *retired* | |
507 | * request, this would be a horrible use-after-free.) | |
508 | */ | |
509 | if (i915_request_completed(request)) | |
510 | goto xfer; | |
511 | ||
36e191f0 CW |
512 | if (unlikely(intel_context_is_banned(request->context))) |
513 | i915_request_set_error_once(request, -EIO); | |
514 | if (unlikely(fatal_error(request->fence.error))) | |
515 | __i915_request_skip(request); | |
d9e61b66 | 516 | |
ca6e56f6 CW |
517 | /* |
518 | * Are we using semaphores when the gpu is already saturated? | |
519 | * | |
520 | * Using semaphores incurs a cost in having the GPU poll a | |
521 | * memory location, busywaiting for it to change. The continual | |
522 | * memory reads can have a noticeable impact on the rest of the | |
523 | * system with the extra bus traffic, stalling the cpu as it too | |
524 | * tries to access memory across the bus (perf stat -e bus-cycles). | |
525 | * | |
526 | * If we installed a semaphore on this request and we only submit | |
527 | * the request after the signaler completed, that indicates the | |
528 | * system is overloaded and using semaphores at this time only | |
529 | * increases the amount of work we are doing. If so, we disable | |
530 | * further use of semaphores until we are idle again, whence we | |
531 | * optimistically try again. | |
532 | */ | |
533 | if (request->sched.semaphores && | |
534 | i915_sw_fence_signaled(&request->semaphore)) | |
44d89409 | 535 | engine->saturated |= request->sched.semaphores; |
ca6e56f6 | 536 | |
c0bb487d CW |
537 | engine->emit_fini_breadcrumb(request, |
538 | request->ring->vaddr + request->postfix); | |
b5773a36 | 539 | |
c0bb487d CW |
540 | trace_i915_request_execute(request); |
541 | engine->serial++; | |
542 | result = true; | |
422d7df4 | 543 | |
1d9221e9 | 544 | xfer: |
672c368f | 545 | if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)) { |
c0bb487d | 546 | list_move_tail(&request->sched.link, &engine->active.requests); |
672c368f CW |
547 | clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags); |
548 | } | |
b5773a36 | 549 | |
1d9221e9 CW |
550 | /* We may be recursing from the signal callback of another i915 fence */ |
551 | if (!i915_request_signaled(request)) { | |
552 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
b5773a36 | 553 | |
1d9221e9 CW |
554 | __notify_execute_cb(request); |
555 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, | |
556 | &request->fence.flags) && | |
557 | !i915_request_enable_breadcrumb(request)) | |
558 | intel_engine_signal_breadcrumbs(engine); | |
559 | ||
560 | spin_unlock(&request->lock); | |
561 | GEM_BUG_ON(!llist_empty(&request->execute_cb)); | |
562 | } | |
f2d13290 | 563 | |
c0bb487d | 564 | return result; |
d55ac5bf CW |
565 | } |
566 | ||
e61e0f51 | 567 | void i915_request_submit(struct i915_request *request) |
d55ac5bf CW |
568 | { |
569 | struct intel_engine_cs *engine = request->engine; | |
570 | unsigned long flags; | |
23902e49 | 571 | |
d55ac5bf | 572 | /* Will be called from irq-context when using foreign fences. */ |
422d7df4 | 573 | spin_lock_irqsave(&engine->active.lock, flags); |
d55ac5bf | 574 | |
e61e0f51 | 575 | __i915_request_submit(request); |
d55ac5bf | 576 | |
422d7df4 | 577 | spin_unlock_irqrestore(&engine->active.lock, flags); |
d55ac5bf CW |
578 | } |
579 | ||
e61e0f51 | 580 | void __i915_request_unsubmit(struct i915_request *request) |
d55ac5bf | 581 | { |
d6a2289d | 582 | struct intel_engine_cs *engine = request->engine; |
d55ac5bf | 583 | |
639f2f24 | 584 | RQ_TRACE(request, "\n"); |
d9b13c4d | 585 | |
e60a870d | 586 | GEM_BUG_ON(!irqs_disabled()); |
422d7df4 | 587 | lockdep_assert_held(&engine->active.lock); |
48bc2a4a | 588 | |
e61e0f51 CW |
589 | /* |
590 | * Only unwind in reverse order, required so that the per-context list | |
d6a2289d CW |
591 | * is kept in seqno/ring order. |
592 | */ | |
80b204bc | 593 | |
d6a2289d CW |
594 | /* We may be recursing from the signal callback of another i915 fence */ |
595 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
b5773a36 | 596 | |
d6a2289d | 597 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) |
52c0fdb2 | 598 | i915_request_cancel_breadcrumb(request); |
b5773a36 | 599 | |
52c0fdb2 CW |
600 | GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)); |
601 | clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags); | |
b5773a36 | 602 | |
d6a2289d CW |
603 | spin_unlock(&request->lock); |
604 | ||
dba5a7f3 | 605 | /* We've already spun, don't charge on resubmitting. */ |
18e4af04 | 606 | if (request->sched.semaphores && i915_request_started(request)) |
dba5a7f3 | 607 | request->sched.semaphores = 0; |
dba5a7f3 | 608 | |
e61e0f51 CW |
609 | /* |
610 | * We don't need to wake_up any waiters on request->execute, they | |
d6a2289d | 611 | * will get woken by any other event or us re-adding this request |
e61e0f51 | 612 | * to the engine timeline (__i915_request_submit()). The waiters |
d6a2289d CW |
613 | * should be quite adapt at finding that the request now has a new |
614 | * global_seqno to the one they went to sleep on. | |
615 | */ | |
616 | } | |
617 | ||
e61e0f51 | 618 | void i915_request_unsubmit(struct i915_request *request) |
d6a2289d CW |
619 | { |
620 | struct intel_engine_cs *engine = request->engine; | |
621 | unsigned long flags; | |
622 | ||
623 | /* Will be called from irq-context when using foreign fences. */ | |
422d7df4 | 624 | spin_lock_irqsave(&engine->active.lock, flags); |
d6a2289d | 625 | |
e61e0f51 | 626 | __i915_request_unsubmit(request); |
d6a2289d | 627 | |
422d7df4 | 628 | spin_unlock_irqrestore(&engine->active.lock, flags); |
5590af3e CW |
629 | } |
630 | ||
23902e49 | 631 | static int __i915_sw_fence_call |
d55ac5bf | 632 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
23902e49 | 633 | { |
e61e0f51 | 634 | struct i915_request *request = |
48bc2a4a | 635 | container_of(fence, typeof(*request), submit); |
48bc2a4a CW |
636 | |
637 | switch (state) { | |
638 | case FENCE_COMPLETE: | |
e61e0f51 | 639 | trace_i915_request_submit(request); |
ef468849 CW |
640 | |
641 | if (unlikely(fence->error)) | |
36e191f0 | 642 | i915_request_set_error_once(request, fence->error); |
ef468849 | 643 | |
af7a8ffa | 644 | /* |
e61e0f51 CW |
645 | * We need to serialize use of the submit_request() callback |
646 | * with its hotplugging performed during an emergency | |
647 | * i915_gem_set_wedged(). We use the RCU mechanism to mark the | |
648 | * critical section in order to force i915_gem_set_wedged() to | |
649 | * wait until the submit_request() is completed before | |
650 | * proceeding. | |
af7a8ffa DV |
651 | */ |
652 | rcu_read_lock(); | |
d55ac5bf | 653 | request->engine->submit_request(request); |
af7a8ffa | 654 | rcu_read_unlock(); |
48bc2a4a CW |
655 | break; |
656 | ||
657 | case FENCE_FREE: | |
e61e0f51 | 658 | i915_request_put(request); |
48bc2a4a CW |
659 | break; |
660 | } | |
661 | ||
23902e49 CW |
662 | return NOTIFY_DONE; |
663 | } | |
664 | ||
b7404c7e CW |
665 | static int __i915_sw_fence_call |
666 | semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) | |
667 | { | |
209df10b | 668 | struct i915_request *rq = container_of(fence, typeof(*rq), semaphore); |
b7404c7e CW |
669 | |
670 | switch (state) { | |
671 | case FENCE_COMPLETE: | |
b7404c7e CW |
672 | break; |
673 | ||
674 | case FENCE_FREE: | |
209df10b | 675 | i915_request_put(rq); |
b7404c7e CW |
676 | break; |
677 | } | |
678 | ||
679 | return NOTIFY_DONE; | |
680 | } | |
681 | ||
e5dadff4 | 682 | static void retire_requests(struct intel_timeline *tl) |
d22ba0cb CW |
683 | { |
684 | struct i915_request *rq, *rn; | |
685 | ||
e5dadff4 | 686 | list_for_each_entry_safe(rq, rn, &tl->requests, link) |
9db0c5ca | 687 | if (!i915_request_retire(rq)) |
d22ba0cb | 688 | break; |
d22ba0cb CW |
689 | } |
690 | ||
691 | static noinline struct i915_request * | |
43acd651 CW |
692 | request_alloc_slow(struct intel_timeline *tl, |
693 | struct i915_request **rsvd, | |
694 | gfp_t gfp) | |
d22ba0cb | 695 | { |
d22ba0cb CW |
696 | struct i915_request *rq; |
697 | ||
43acd651 CW |
698 | /* If we cannot wait, dip into our reserves */ |
699 | if (!gfpflags_allow_blocking(gfp)) { | |
700 | rq = xchg(rsvd, NULL); | |
701 | if (!rq) /* Use the normal failure path for one final WARN */ | |
702 | goto out; | |
d22ba0cb | 703 | |
43acd651 CW |
704 | return rq; |
705 | } | |
706 | ||
707 | if (list_empty(&tl->requests)) | |
2ccdf6a1 CW |
708 | goto out; |
709 | ||
9db0c5ca | 710 | /* Move our oldest request to the slab-cache (if not in use!) */ |
e5dadff4 | 711 | rq = list_first_entry(&tl->requests, typeof(*rq), link); |
9db0c5ca CW |
712 | i915_request_retire(rq); |
713 | ||
714 | rq = kmem_cache_alloc(global.slab_requests, | |
715 | gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); | |
716 | if (rq) | |
717 | return rq; | |
718 | ||
d22ba0cb | 719 | /* Ratelimit ourselves to prevent oom from malicious clients */ |
e5dadff4 | 720 | rq = list_last_entry(&tl->requests, typeof(*rq), link); |
d22ba0cb CW |
721 | cond_synchronize_rcu(rq->rcustate); |
722 | ||
723 | /* Retire our old requests in the hope that we free some */ | |
e5dadff4 | 724 | retire_requests(tl); |
d22ba0cb CW |
725 | |
726 | out: | |
2ccdf6a1 | 727 | return kmem_cache_alloc(global.slab_requests, gfp); |
d22ba0cb CW |
728 | } |
729 | ||
67a3acaa CW |
730 | static void __i915_request_ctor(void *arg) |
731 | { | |
732 | struct i915_request *rq = arg; | |
733 | ||
734 | spin_lock_init(&rq->lock); | |
735 | i915_sched_node_init(&rq->sched); | |
736 | i915_sw_fence_init(&rq->submit, submit_notify); | |
737 | i915_sw_fence_init(&rq->semaphore, semaphore_notify); | |
738 | ||
855e39e6 CW |
739 | dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, 0, 0); |
740 | ||
67a3acaa CW |
741 | rq->capture_list = NULL; |
742 | ||
fc0e1270 | 743 | init_llist_head(&rq->execute_cb); |
67a3acaa CW |
744 | } |
745 | ||
e61e0f51 | 746 | struct i915_request * |
2ccdf6a1 | 747 | __i915_request_create(struct intel_context *ce, gfp_t gfp) |
05235c53 | 748 | { |
75d0a7f3 | 749 | struct intel_timeline *tl = ce->timeline; |
ebece753 CW |
750 | struct i915_request *rq; |
751 | u32 seqno; | |
05235c53 CW |
752 | int ret; |
753 | ||
2ccdf6a1 | 754 | might_sleep_if(gfpflags_allow_blocking(gfp)); |
28176ef4 | 755 | |
2ccdf6a1 CW |
756 | /* Check that the caller provided an already pinned context */ |
757 | __intel_context_pin(ce); | |
9b5f4e5e | 758 | |
e61e0f51 CW |
759 | /* |
760 | * Beware: Dragons be flying overhead. | |
5a198b8c CW |
761 | * |
762 | * We use RCU to look up requests in flight. The lookups may | |
763 | * race with the request being allocated from the slab freelist. | |
764 | * That is the request we are writing to here, may be in the process | |
21950ee7 | 765 | * of being read by __i915_active_request_get_rcu(). As such, |
5a198b8c CW |
766 | * we have to be very careful when overwriting the contents. During |
767 | * the RCU lookup, we change chase the request->engine pointer, | |
65e4760e | 768 | * read the request->global_seqno and increment the reference count. |
5a198b8c CW |
769 | * |
770 | * The reference count is incremented atomically. If it is zero, | |
771 | * the lookup knows the request is unallocated and complete. Otherwise, | |
772 | * it is either still in use, or has been reallocated and reset | |
f54d1867 CW |
773 | * with dma_fence_init(). This increment is safe for release as we |
774 | * check that the request we have a reference to and matches the active | |
5a198b8c CW |
775 | * request. |
776 | * | |
777 | * Before we increment the refcount, we chase the request->engine | |
778 | * pointer. We must not call kmem_cache_zalloc() or else we set | |
779 | * that pointer to NULL and cause a crash during the lookup. If | |
780 | * we see the request is completed (based on the value of the | |
781 | * old engine and seqno), the lookup is complete and reports NULL. | |
782 | * If we decide the request is not completed (new engine or seqno), | |
783 | * then we grab a reference and double check that it is still the | |
784 | * active request - which it won't be and restart the lookup. | |
785 | * | |
786 | * Do not use kmem_cache_zalloc() here! | |
787 | */ | |
32eb6bcf | 788 | rq = kmem_cache_alloc(global.slab_requests, |
2ccdf6a1 | 789 | gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); |
e61e0f51 | 790 | if (unlikely(!rq)) { |
43acd651 | 791 | rq = request_alloc_slow(tl, &ce->engine->request_pool, gfp); |
e61e0f51 | 792 | if (!rq) { |
31c70f97 CW |
793 | ret = -ENOMEM; |
794 | goto err_unreserve; | |
795 | } | |
28176ef4 | 796 | } |
05235c53 | 797 | |
9f3ccd40 | 798 | rq->context = ce; |
2ccdf6a1 | 799 | rq->engine = ce->engine; |
1fc44d9b | 800 | rq->ring = ce->ring; |
89b6d183 | 801 | rq->execution_mask = ce->engine->mask; |
d19d71fc | 802 | |
855e39e6 CW |
803 | kref_init(&rq->fence.refcount); |
804 | rq->fence.flags = 0; | |
805 | rq->fence.error = 0; | |
806 | INIT_LIST_HEAD(&rq->fence.cb_list); | |
807 | ||
808 | ret = intel_timeline_get_seqno(tl, rq, &seqno); | |
809 | if (ret) | |
810 | goto err_free; | |
811 | ||
812 | rq->fence.context = tl->fence_context; | |
813 | rq->fence.seqno = seqno; | |
814 | ||
85bedbf1 CW |
815 | RCU_INIT_POINTER(rq->timeline, tl); |
816 | RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline); | |
ebece753 | 817 | rq->hwsp_seqno = tl->hwsp_seqno; |
1eaa251b | 818 | GEM_BUG_ON(i915_request_completed(rq)); |
d19d71fc | 819 | |
ebece753 | 820 | rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */ |
73cb9701 | 821 | |
48bc2a4a | 822 | /* We bump the ref for the fence chain */ |
67a3acaa CW |
823 | i915_sw_fence_reinit(&i915_request_get(rq)->submit); |
824 | i915_sw_fence_reinit(&i915_request_get(rq)->semaphore); | |
5590af3e | 825 | |
67a3acaa | 826 | i915_sched_node_reinit(&rq->sched); |
52e54209 | 827 | |
67a3acaa | 828 | /* No zalloc, everything must be cleared after use */ |
e61e0f51 | 829 | rq->batch = NULL; |
67a3acaa | 830 | GEM_BUG_ON(rq->capture_list); |
fc0e1270 | 831 | GEM_BUG_ON(!llist_empty(&rq->execute_cb)); |
2ccdf6a1 | 832 | |
05235c53 CW |
833 | /* |
834 | * Reserve space in the ring buffer for all the commands required to | |
835 | * eventually emit this request. This is to guarantee that the | |
e61e0f51 | 836 | * i915_request_add() call can't fail. Note that the reserve may need |
05235c53 CW |
837 | * to be redone if the request is not actually submitted straight |
838 | * away, e.g. because a GPU scheduler has deferred it. | |
ed2922c0 CW |
839 | * |
840 | * Note that due to how we add reserved_space to intel_ring_begin() | |
841 | * we need to double our request to ensure that if we need to wrap | |
842 | * around inside i915_request_add() there is sufficient space at | |
843 | * the beginning of the ring as well. | |
05235c53 | 844 | */ |
2ccdf6a1 CW |
845 | rq->reserved_space = |
846 | 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32); | |
05235c53 | 847 | |
2113184c CW |
848 | /* |
849 | * Record the position of the start of the request so that | |
d045446d CW |
850 | * should we detect the updated seqno part-way through the |
851 | * GPU processing the request, we never over-estimate the | |
852 | * position of the head. | |
853 | */ | |
e61e0f51 | 854 | rq->head = rq->ring->emit; |
d045446d | 855 | |
2ccdf6a1 | 856 | ret = rq->engine->request_alloc(rq); |
b1c24a61 CW |
857 | if (ret) |
858 | goto err_unwind; | |
2113184c | 859 | |
b3ee09a4 CW |
860 | rq->infix = rq->ring->emit; /* end of header; start of user payload */ |
861 | ||
2ccdf6a1 | 862 | intel_context_mark_active(ce); |
d22d2d07 CW |
863 | list_add_tail_rcu(&rq->link, &tl->requests); |
864 | ||
e61e0f51 | 865 | return rq; |
05235c53 | 866 | |
b1c24a61 | 867 | err_unwind: |
1fc44d9b | 868 | ce->ring->emit = rq->head; |
b1c24a61 | 869 | |
1618bdb8 | 870 | /* Make sure we didn't add ourselves to external state before freeing */ |
0c7112a0 CW |
871 | GEM_BUG_ON(!list_empty(&rq->sched.signalers_list)); |
872 | GEM_BUG_ON(!list_empty(&rq->sched.waiters_list)); | |
1618bdb8 | 873 | |
ebece753 | 874 | err_free: |
32eb6bcf | 875 | kmem_cache_free(global.slab_requests, rq); |
28176ef4 | 876 | err_unreserve: |
1fc44d9b | 877 | intel_context_unpin(ce); |
8e637178 | 878 | return ERR_PTR(ret); |
05235c53 CW |
879 | } |
880 | ||
2ccdf6a1 CW |
881 | struct i915_request * |
882 | i915_request_create(struct intel_context *ce) | |
883 | { | |
884 | struct i915_request *rq; | |
e5dadff4 | 885 | struct intel_timeline *tl; |
2ccdf6a1 | 886 | |
e5dadff4 CW |
887 | tl = intel_context_timeline_lock(ce); |
888 | if (IS_ERR(tl)) | |
889 | return ERR_CAST(tl); | |
2ccdf6a1 CW |
890 | |
891 | /* Move our oldest request to the slab-cache (if not in use!) */ | |
e5dadff4 CW |
892 | rq = list_first_entry(&tl->requests, typeof(*rq), link); |
893 | if (!list_is_last(&rq->link, &tl->requests)) | |
2ccdf6a1 CW |
894 | i915_request_retire(rq); |
895 | ||
896 | intel_context_enter(ce); | |
897 | rq = __i915_request_create(ce, GFP_KERNEL); | |
898 | intel_context_exit(ce); /* active reference transferred to request */ | |
899 | if (IS_ERR(rq)) | |
900 | goto err_unlock; | |
901 | ||
902 | /* Check that we do not interrupt ourselves with a new request */ | |
e5dadff4 | 903 | rq->cookie = lockdep_pin_lock(&tl->mutex); |
2ccdf6a1 CW |
904 | |
905 | return rq; | |
906 | ||
907 | err_unlock: | |
e5dadff4 | 908 | intel_context_timeline_unlock(tl); |
2ccdf6a1 CW |
909 | return rq; |
910 | } | |
911 | ||
0d90ccb7 CW |
912 | static int |
913 | i915_request_await_start(struct i915_request *rq, struct i915_request *signal) | |
914 | { | |
6a79d848 CW |
915 | struct dma_fence *fence; |
916 | int err; | |
0d90ccb7 | 917 | |
ab7a6902 CW |
918 | if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline)) |
919 | return 0; | |
6a79d848 | 920 | |
d22d2d07 CW |
921 | if (i915_request_started(signal)) |
922 | return 0; | |
923 | ||
9ddc8ec0 | 924 | fence = NULL; |
6a79d848 | 925 | rcu_read_lock(); |
9ddc8ec0 | 926 | spin_lock_irq(&signal->lock); |
d22d2d07 CW |
927 | do { |
928 | struct list_head *pos = READ_ONCE(signal->link.prev); | |
929 | struct i915_request *prev; | |
930 | ||
931 | /* Confirm signal has not been retired, the link is valid */ | |
932 | if (unlikely(i915_request_started(signal))) | |
933 | break; | |
934 | ||
935 | /* Is signal the earliest request on its timeline? */ | |
936 | if (pos == &rcu_dereference(signal->timeline)->requests) | |
937 | break; | |
0d90ccb7 | 938 | |
9ddc8ec0 CW |
939 | /* |
940 | * Peek at the request before us in the timeline. That | |
941 | * request will only be valid before it is retired, so | |
942 | * after acquiring a reference to it, confirm that it is | |
943 | * still part of the signaler's timeline. | |
944 | */ | |
d22d2d07 CW |
945 | prev = list_entry(pos, typeof(*prev), link); |
946 | if (!i915_request_get_rcu(prev)) | |
947 | break; | |
948 | ||
949 | /* After the strong barrier, confirm prev is still attached */ | |
950 | if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) { | |
951 | i915_request_put(prev); | |
952 | break; | |
6a79d848 | 953 | } |
d22d2d07 CW |
954 | |
955 | fence = &prev->fence; | |
956 | } while (0); | |
9ddc8ec0 CW |
957 | spin_unlock_irq(&signal->lock); |
958 | rcu_read_unlock(); | |
959 | if (!fence) | |
960 | return 0; | |
6a79d848 CW |
961 | |
962 | err = 0; | |
07e9c59d | 963 | if (!intel_timeline_sync_is_later(i915_request_timeline(rq), fence)) |
6a79d848 CW |
964 | err = i915_sw_fence_await_dma_fence(&rq->submit, |
965 | fence, 0, | |
966 | I915_FENCE_GFP); | |
967 | dma_fence_put(fence); | |
968 | ||
969 | return err; | |
0d90ccb7 CW |
970 | } |
971 | ||
ca6e56f6 CW |
972 | static intel_engine_mask_t |
973 | already_busywaiting(struct i915_request *rq) | |
974 | { | |
975 | /* | |
976 | * Polling a semaphore causes bus traffic, delaying other users of | |
977 | * both the GPU and CPU. We want to limit the impact on others, | |
978 | * while taking advantage of early submission to reduce GPU | |
979 | * latency. Therefore we restrict ourselves to not using more | |
980 | * than one semaphore from each source, and not using a semaphore | |
981 | * if we have detected the engine is saturated (i.e. would not be | |
982 | * submitted early and cause bus traffic reading an already passed | |
983 | * semaphore). | |
984 | * | |
985 | * See the are-we-too-late? check in __i915_request_submit(). | |
986 | */ | |
60900add | 987 | return rq->sched.semaphores | READ_ONCE(rq->engine->saturated); |
ca6e56f6 CW |
988 | } |
989 | ||
e8861964 | 990 | static int |
c81471f5 CW |
991 | __emit_semaphore_wait(struct i915_request *to, |
992 | struct i915_request *from, | |
993 | u32 seqno) | |
e8861964 | 994 | { |
5a833995 | 995 | const int has_token = INTEL_GEN(to->engine->i915) >= 12; |
e8861964 | 996 | u32 hwsp_offset; |
c81471f5 | 997 | int len, err; |
e8861964 | 998 | u32 *cs; |
e8861964 | 999 | |
5a833995 | 1000 | GEM_BUG_ON(INTEL_GEN(to->engine->i915) < 8); |
795d4d7f | 1001 | GEM_BUG_ON(i915_request_has_initial_breadcrumb(to)); |
e8861964 | 1002 | |
c8a0e2ae | 1003 | /* We need to pin the signaler's HWSP until we are finished reading. */ |
c81471f5 CW |
1004 | err = intel_timeline_read_hwsp(from, to, &hwsp_offset); |
1005 | if (err) | |
1006 | return err; | |
e8861964 | 1007 | |
c210e85b CW |
1008 | len = 4; |
1009 | if (has_token) | |
1010 | len += 2; | |
1011 | ||
1012 | cs = intel_ring_begin(to, len); | |
e8861964 CW |
1013 | if (IS_ERR(cs)) |
1014 | return PTR_ERR(cs); | |
1015 | ||
1016 | /* | |
1017 | * Using greater-than-or-equal here means we have to worry | |
1018 | * about seqno wraparound. To side step that issue, we swap | |
1019 | * the timeline HWSP upon wrapping, so that everyone listening | |
1020 | * for the old (pre-wrap) values do not see the much smaller | |
1021 | * (post-wrap) values than they were expecting (and so wait | |
1022 | * forever). | |
1023 | */ | |
c210e85b CW |
1024 | *cs++ = (MI_SEMAPHORE_WAIT | |
1025 | MI_SEMAPHORE_GLOBAL_GTT | | |
1026 | MI_SEMAPHORE_POLL | | |
1027 | MI_SEMAPHORE_SAD_GTE_SDD) + | |
1028 | has_token; | |
c81471f5 | 1029 | *cs++ = seqno; |
e8861964 CW |
1030 | *cs++ = hwsp_offset; |
1031 | *cs++ = 0; | |
c210e85b CW |
1032 | if (has_token) { |
1033 | *cs++ = 0; | |
1034 | *cs++ = MI_NOOP; | |
1035 | } | |
e8861964 CW |
1036 | |
1037 | intel_ring_advance(to, cs); | |
c81471f5 CW |
1038 | return 0; |
1039 | } | |
1040 | ||
1041 | static int | |
1042 | emit_semaphore_wait(struct i915_request *to, | |
1043 | struct i915_request *from, | |
1044 | gfp_t gfp) | |
1045 | { | |
326611dd | 1046 | const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask; |
18e4af04 | 1047 | struct i915_sw_fence *wait = &to->submit; |
326611dd | 1048 | |
f16ccb64 CW |
1049 | if (!intel_context_use_semaphores(to->context)) |
1050 | goto await_fence; | |
1051 | ||
795d4d7f CW |
1052 | if (i915_request_has_initial_breadcrumb(to)) |
1053 | goto await_fence; | |
1054 | ||
f16ccb64 CW |
1055 | if (!rcu_access_pointer(from->hwsp_cacheline)) |
1056 | goto await_fence; | |
1057 | ||
fcae4961 CW |
1058 | /* |
1059 | * If this or its dependents are waiting on an external fence | |
1060 | * that may fail catastrophically, then we want to avoid using | |
1061 | * sempahores as they bypass the fence signaling metadata, and we | |
1062 | * lose the fence->error propagation. | |
1063 | */ | |
1064 | if (from->sched.flags & I915_SCHED_HAS_EXTERNAL_CHAIN) | |
1065 | goto await_fence; | |
1066 | ||
c81471f5 | 1067 | /* Just emit the first semaphore we see as request space is limited. */ |
326611dd | 1068 | if (already_busywaiting(to) & mask) |
c81471f5 CW |
1069 | goto await_fence; |
1070 | ||
1071 | if (i915_request_await_start(to, from) < 0) | |
1072 | goto await_fence; | |
1073 | ||
1074 | /* Only submit our spinner after the signaler is running! */ | |
1075 | if (__await_execution(to, from, NULL, gfp)) | |
1076 | goto await_fence; | |
1077 | ||
1078 | if (__emit_semaphore_wait(to, from, from->fence.seqno)) | |
1079 | goto await_fence; | |
1080 | ||
326611dd | 1081 | to->sched.semaphores |= mask; |
18e4af04 | 1082 | wait = &to->semaphore; |
6a79d848 CW |
1083 | |
1084 | await_fence: | |
18e4af04 | 1085 | return i915_sw_fence_await_dma_fence(wait, |
6a79d848 CW |
1086 | &from->fence, 0, |
1087 | I915_FENCE_GFP); | |
e8861964 CW |
1088 | } |
1089 | ||
ffb0c600 CW |
1090 | static bool intel_timeline_sync_has_start(struct intel_timeline *tl, |
1091 | struct dma_fence *fence) | |
1092 | { | |
1093 | return __intel_timeline_sync_is_later(tl, | |
1094 | fence->context, | |
1095 | fence->seqno - 1); | |
1096 | } | |
1097 | ||
1098 | static int intel_timeline_sync_set_start(struct intel_timeline *tl, | |
1099 | const struct dma_fence *fence) | |
1100 | { | |
1101 | return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1); | |
1102 | } | |
1103 | ||
a2bc4695 | 1104 | static int |
ffb0c600 CW |
1105 | __i915_request_await_execution(struct i915_request *to, |
1106 | struct i915_request *from, | |
1107 | void (*hook)(struct i915_request *rq, | |
1108 | struct dma_fence *signal)) | |
a2bc4695 | 1109 | { |
ffb0c600 | 1110 | int err; |
a2bc4695 | 1111 | |
ffb0c600 | 1112 | GEM_BUG_ON(intel_context_is_barrier(from->context)); |
a2bc4695 | 1113 | |
ffb0c600 CW |
1114 | /* Submit both requests at the same time */ |
1115 | err = __await_execution(to, from, hook, I915_FENCE_GFP); | |
1116 | if (err) | |
1117 | return err; | |
1118 | ||
1119 | /* Squash repeated depenendices to the same timelines */ | |
1120 | if (intel_timeline_sync_has_start(i915_request_timeline(to), | |
1121 | &from->fence)) | |
ade0b0c9 | 1122 | return 0; |
ffb0c600 CW |
1123 | |
1124 | /* | |
1125 | * Wait until the start of this request. | |
1126 | * | |
1127 | * The execution cb fires when we submit the request to HW. But in | |
1128 | * many cases this may be long before the request itself is ready to | |
1129 | * run (consider that we submit 2 requests for the same context, where | |
1130 | * the request of interest is behind an indefinite spinner). So we hook | |
1131 | * up to both to reduce our queues and keep the execution lag minimised | |
1132 | * in the worst case, though we hope that the await_start is elided. | |
1133 | */ | |
1134 | err = i915_request_await_start(to, from); | |
1135 | if (err < 0) | |
1136 | return err; | |
1137 | ||
1138 | /* | |
1139 | * Ensure both start together [after all semaphores in signal] | |
1140 | * | |
1141 | * Now that we are queued to the HW at roughly the same time (thanks | |
1142 | * to the execute cb) and are ready to run at roughly the same time | |
1143 | * (thanks to the await start), our signaler may still be indefinitely | |
1144 | * delayed by waiting on a semaphore from a remote engine. If our | |
1145 | * signaler depends on a semaphore, so indirectly do we, and we do not | |
1146 | * want to start our payload until our signaler also starts theirs. | |
1147 | * So we wait. | |
1148 | * | |
1149 | * However, there is also a second condition for which we need to wait | |
1150 | * for the precise start of the signaler. Consider that the signaler | |
1151 | * was submitted in a chain of requests following another context | |
1152 | * (with just an ordinary intra-engine fence dependency between the | |
1153 | * two). In this case the signaler is queued to HW, but not for | |
1154 | * immediate execution, and so we must wait until it reaches the | |
1155 | * active slot. | |
1156 | */ | |
1157 | if (intel_engine_has_semaphores(to->engine) && | |
1158 | !i915_request_has_initial_breadcrumb(to)) { | |
1159 | err = __emit_semaphore_wait(to, from, from->fence.seqno - 1); | |
1160 | if (err < 0) | |
1161 | return err; | |
24fe5f2a | 1162 | } |
ade0b0c9 | 1163 | |
ffb0c600 | 1164 | /* Couple the dependency tree for PI on this exposed to->fence */ |
52e54209 | 1165 | if (to->engine->schedule) { |
ffb0c600 | 1166 | err = i915_sched_node_add_dependency(&to->sched, |
6b6cd2eb | 1167 | &from->sched, |
ffb0c600 CW |
1168 | I915_DEPENDENCY_WEAK); |
1169 | if (err < 0) | |
1170 | return err; | |
52e54209 CW |
1171 | } |
1172 | ||
ffb0c600 CW |
1173 | return intel_timeline_sync_set_start(i915_request_timeline(to), |
1174 | &from->fence); | |
a2bc4695 CW |
1175 | } |
1176 | ||
fcae4961 CW |
1177 | static void mark_external(struct i915_request *rq) |
1178 | { | |
1179 | /* | |
1180 | * The downside of using semaphores is that we lose metadata passing | |
1181 | * along the signaling chain. This is particularly nasty when we | |
1182 | * need to pass along a fatal error such as EFAULT or EDEADLK. For | |
1183 | * fatal errors we want to scrub the request before it is executed, | |
1184 | * which means that we cannot preload the request onto HW and have | |
1185 | * it wait upon a semaphore. | |
1186 | */ | |
1187 | rq->sched.flags |= I915_SCHED_HAS_EXTERNAL_CHAIN; | |
1188 | } | |
1189 | ||
ac938052 | 1190 | static int |
3136deb7 | 1191 | __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) |
ac938052 | 1192 | { |
fcae4961 | 1193 | mark_external(rq); |
ac938052 | 1194 | return i915_sw_fence_await_dma_fence(&rq->submit, fence, |
5a833995 | 1195 | i915_fence_context_timeout(rq->engine->i915, |
16dc224f | 1196 | fence->context), |
ac938052 CW |
1197 | I915_FENCE_GFP); |
1198 | } | |
1199 | ||
3136deb7 LL |
1200 | static int |
1201 | i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) | |
1202 | { | |
1203 | struct dma_fence *iter; | |
1204 | int err = 0; | |
1205 | ||
1206 | if (!to_dma_fence_chain(fence)) | |
1207 | return __i915_request_await_external(rq, fence); | |
1208 | ||
1209 | dma_fence_chain_for_each(iter, fence) { | |
1210 | struct dma_fence_chain *chain = to_dma_fence_chain(iter); | |
1211 | ||
1212 | if (!dma_fence_is_i915(chain->fence)) { | |
1213 | err = __i915_request_await_external(rq, iter); | |
1214 | break; | |
1215 | } | |
1216 | ||
1217 | err = i915_request_await_dma_fence(rq, chain->fence); | |
1218 | if (err < 0) | |
1219 | break; | |
1220 | } | |
1221 | ||
1222 | dma_fence_put(iter); | |
1223 | return err; | |
1224 | } | |
1225 | ||
b52992c0 | 1226 | int |
ffb0c600 CW |
1227 | i915_request_await_execution(struct i915_request *rq, |
1228 | struct dma_fence *fence, | |
1229 | void (*hook)(struct i915_request *rq, | |
1230 | struct dma_fence *signal)) | |
b52992c0 | 1231 | { |
29ef3fa9 CW |
1232 | struct dma_fence **child = &fence; |
1233 | unsigned int nchild = 1; | |
b52992c0 | 1234 | int ret; |
b52992c0 | 1235 | |
29ef3fa9 CW |
1236 | if (dma_fence_is_array(fence)) { |
1237 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
1238 | ||
ffb0c600 CW |
1239 | /* XXX Error for signal-on-any fence arrays */ |
1240 | ||
29ef3fa9 CW |
1241 | child = array->fences; |
1242 | nchild = array->num_fences; | |
1243 | GEM_BUG_ON(!nchild); | |
1244 | } | |
b52992c0 | 1245 | |
29ef3fa9 CW |
1246 | do { |
1247 | fence = *child++; | |
9e31c1fe CW |
1248 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { |
1249 | i915_sw_fence_set_error_once(&rq->submit, fence->error); | |
29ef3fa9 | 1250 | continue; |
9e31c1fe | 1251 | } |
b52992c0 | 1252 | |
e61e0f51 | 1253 | if (fence->context == rq->fence.context) |
ceae14bd CW |
1254 | continue; |
1255 | ||
ffb0c600 CW |
1256 | /* |
1257 | * We don't squash repeated fence dependencies here as we | |
1258 | * want to run our callback in all cases. | |
1259 | */ | |
47979480 | 1260 | |
29ef3fa9 | 1261 | if (dma_fence_is_i915(fence)) |
ffb0c600 CW |
1262 | ret = __i915_request_await_execution(rq, |
1263 | to_request(fence), | |
1264 | hook); | |
b52992c0 | 1265 | else |
ac938052 | 1266 | ret = i915_request_await_external(rq, fence); |
b52992c0 CW |
1267 | if (ret < 0) |
1268 | return ret; | |
29ef3fa9 | 1269 | } while (--nchild); |
b52992c0 CW |
1270 | |
1271 | return 0; | |
1272 | } | |
1273 | ||
511b6d9a CW |
1274 | static int |
1275 | await_request_submit(struct i915_request *to, struct i915_request *from) | |
1276 | { | |
1277 | /* | |
1278 | * If we are waiting on a virtual engine, then it may be | |
1279 | * constrained to execute on a single engine *prior* to submission. | |
1280 | * When it is submitted, it will be first submitted to the virtual | |
1281 | * engine and then passed to the physical engine. We cannot allow | |
1282 | * the waiter to be submitted immediately to the physical engine | |
1283 | * as it may then bypass the virtual request. | |
1284 | */ | |
1285 | if (to->engine == READ_ONCE(from->engine)) | |
1286 | return i915_sw_fence_await_sw_fence_gfp(&to->submit, | |
1287 | &from->submit, | |
1288 | I915_FENCE_GFP); | |
1289 | else | |
1290 | return __i915_request_await_execution(to, from, NULL); | |
1291 | } | |
1292 | ||
c81471f5 | 1293 | static int |
ffb0c600 | 1294 | i915_request_await_request(struct i915_request *to, struct i915_request *from) |
c81471f5 | 1295 | { |
ffb0c600 | 1296 | int ret; |
f16ccb64 | 1297 | |
ffb0c600 CW |
1298 | GEM_BUG_ON(to == from); |
1299 | GEM_BUG_ON(to->timeline == from->timeline); | |
c81471f5 | 1300 | |
ffb0c600 CW |
1301 | if (i915_request_completed(from)) { |
1302 | i915_sw_fence_set_error_once(&to->submit, from->fence.error); | |
c81471f5 | 1303 | return 0; |
798fa870 CW |
1304 | } |
1305 | ||
c81471f5 | 1306 | if (to->engine->schedule) { |
ffb0c600 | 1307 | ret = i915_sched_node_add_dependency(&to->sched, |
6b6cd2eb | 1308 | &from->sched, |
ffb0c600 CW |
1309 | I915_DEPENDENCY_EXTERNAL); |
1310 | if (ret < 0) | |
1311 | return ret; | |
c81471f5 CW |
1312 | } |
1313 | ||
511b6d9a CW |
1314 | if (is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask))) |
1315 | ret = await_request_submit(to, from); | |
ffb0c600 CW |
1316 | else |
1317 | ret = emit_semaphore_wait(to, from, I915_FENCE_GFP); | |
1318 | if (ret < 0) | |
1319 | return ret; | |
1320 | ||
1321 | return 0; | |
c81471f5 CW |
1322 | } |
1323 | ||
f71e01a7 | 1324 | int |
ffb0c600 | 1325 | i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) |
f71e01a7 CW |
1326 | { |
1327 | struct dma_fence **child = &fence; | |
1328 | unsigned int nchild = 1; | |
1329 | int ret; | |
1330 | ||
ffb0c600 CW |
1331 | /* |
1332 | * Note that if the fence-array was created in signal-on-any mode, | |
1333 | * we should *not* decompose it into its individual fences. However, | |
1334 | * we don't currently store which mode the fence-array is operating | |
1335 | * in. Fortunately, the only user of signal-on-any is private to | |
1336 | * amdgpu and we should not see any incoming fence-array from | |
1337 | * sync-file being in signal-on-any mode. | |
1338 | */ | |
f71e01a7 CW |
1339 | if (dma_fence_is_array(fence)) { |
1340 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
1341 | ||
f71e01a7 CW |
1342 | child = array->fences; |
1343 | nchild = array->num_fences; | |
1344 | GEM_BUG_ON(!nchild); | |
1345 | } | |
1346 | ||
1347 | do { | |
1348 | fence = *child++; | |
9e31c1fe CW |
1349 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { |
1350 | i915_sw_fence_set_error_once(&rq->submit, fence->error); | |
f71e01a7 | 1351 | continue; |
9e31c1fe | 1352 | } |
f71e01a7 | 1353 | |
ffb0c600 CW |
1354 | /* |
1355 | * Requests on the same timeline are explicitly ordered, along | |
1356 | * with their dependencies, by i915_request_add() which ensures | |
1357 | * that requests are submitted in-order through each ring. | |
1358 | */ | |
2045d666 CW |
1359 | if (fence->context == rq->fence.context) |
1360 | continue; | |
1361 | ||
ffb0c600 CW |
1362 | /* Squash repeated waits to the same timelines */ |
1363 | if (fence->context && | |
1364 | intel_timeline_sync_is_later(i915_request_timeline(rq), | |
1365 | fence)) | |
1366 | continue; | |
f71e01a7 CW |
1367 | |
1368 | if (dma_fence_is_i915(fence)) | |
ffb0c600 | 1369 | ret = i915_request_await_request(rq, to_request(fence)); |
f71e01a7 | 1370 | else |
ac938052 | 1371 | ret = i915_request_await_external(rq, fence); |
f71e01a7 CW |
1372 | if (ret < 0) |
1373 | return ret; | |
ffb0c600 CW |
1374 | |
1375 | /* Record the latest fence used against each timeline */ | |
1376 | if (fence->context) | |
1377 | intel_timeline_sync_set(i915_request_timeline(rq), | |
1378 | fence); | |
f71e01a7 CW |
1379 | } while (--nchild); |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
a2bc4695 | 1384 | /** |
e61e0f51 | 1385 | * i915_request_await_object - set this request to (async) wait upon a bo |
a2bc4695 CW |
1386 | * @to: request we are wishing to use |
1387 | * @obj: object which may be in use on another ring. | |
d8802126 | 1388 | * @write: whether the wait is on behalf of a writer |
a2bc4695 CW |
1389 | * |
1390 | * This code is meant to abstract object synchronization with the GPU. | |
1391 | * Conceptually we serialise writes between engines inside the GPU. | |
1392 | * We only allow one engine to write into a buffer at any time, but | |
1393 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
1394 | * | |
1395 | * - If there is an outstanding write request to the object, the new | |
1396 | * request must wait for it to complete (either CPU or in hw, requests | |
1397 | * on the same ring will be naturally ordered). | |
1398 | * | |
1399 | * - If we are a write request (pending_write_domain is set), the new | |
1400 | * request must wait for outstanding read requests to complete. | |
1401 | * | |
1402 | * Returns 0 if successful, else propagates up the lower layer error. | |
1403 | */ | |
1404 | int | |
e61e0f51 CW |
1405 | i915_request_await_object(struct i915_request *to, |
1406 | struct drm_i915_gem_object *obj, | |
1407 | bool write) | |
a2bc4695 | 1408 | { |
d07f0e59 CW |
1409 | struct dma_fence *excl; |
1410 | int ret = 0; | |
a2bc4695 CW |
1411 | |
1412 | if (write) { | |
d07f0e59 CW |
1413 | struct dma_fence **shared; |
1414 | unsigned int count, i; | |
1415 | ||
52791eee | 1416 | ret = dma_resv_get_fences_rcu(obj->base.resv, |
d07f0e59 CW |
1417 | &excl, &count, &shared); |
1418 | if (ret) | |
1419 | return ret; | |
1420 | ||
1421 | for (i = 0; i < count; i++) { | |
e61e0f51 | 1422 | ret = i915_request_await_dma_fence(to, shared[i]); |
d07f0e59 CW |
1423 | if (ret) |
1424 | break; | |
1425 | ||
1426 | dma_fence_put(shared[i]); | |
1427 | } | |
1428 | ||
1429 | for (; i < count; i++) | |
1430 | dma_fence_put(shared[i]); | |
1431 | kfree(shared); | |
a2bc4695 | 1432 | } else { |
52791eee | 1433 | excl = dma_resv_get_excl_rcu(obj->base.resv); |
a2bc4695 CW |
1434 | } |
1435 | ||
d07f0e59 CW |
1436 | if (excl) { |
1437 | if (ret == 0) | |
e61e0f51 | 1438 | ret = i915_request_await_dma_fence(to, excl); |
a2bc4695 | 1439 | |
d07f0e59 | 1440 | dma_fence_put(excl); |
a2bc4695 CW |
1441 | } |
1442 | ||
d07f0e59 | 1443 | return ret; |
a2bc4695 CW |
1444 | } |
1445 | ||
ea593dbb CW |
1446 | static struct i915_request * |
1447 | __i915_request_add_to_timeline(struct i915_request *rq) | |
1448 | { | |
d19d71fc | 1449 | struct intel_timeline *timeline = i915_request_timeline(rq); |
ea593dbb CW |
1450 | struct i915_request *prev; |
1451 | ||
1452 | /* | |
1453 | * Dependency tracking and request ordering along the timeline | |
1454 | * is special cased so that we can eliminate redundant ordering | |
1455 | * operations while building the request (we know that the timeline | |
1456 | * itself is ordered, and here we guarantee it). | |
1457 | * | |
1458 | * As we know we will need to emit tracking along the timeline, | |
1459 | * we embed the hooks into our request struct -- at the cost of | |
1460 | * having to have specialised no-allocation interfaces (which will | |
1461 | * be beneficial elsewhere). | |
1462 | * | |
1463 | * A second benefit to open-coding i915_request_await_request is | |
1464 | * that we can apply a slight variant of the rules specialised | |
1465 | * for timelines that jump between engines (such as virtual engines). | |
1466 | * If we consider the case of virtual engine, we must emit a dma-fence | |
1467 | * to prevent scheduling of the second request until the first is | |
1468 | * complete (to maximise our greedy late load balancing) and this | |
1469 | * precludes optimising to use semaphores serialisation of a single | |
1470 | * timeline across engines. | |
1471 | */ | |
b1e3177b CW |
1472 | prev = to_request(__i915_active_fence_set(&timeline->last_request, |
1473 | &rq->fence)); | |
ea593dbb | 1474 | if (prev && !i915_request_completed(prev)) { |
1eaa251b CW |
1475 | /* |
1476 | * The requests are supposed to be kept in order. However, | |
1477 | * we need to be wary in case the timeline->last_request | |
1478 | * is used as a barrier for external modification to this | |
1479 | * context. | |
1480 | */ | |
1481 | GEM_BUG_ON(prev->context == rq->context && | |
1482 | i915_seqno_passed(prev->fence.seqno, | |
1483 | rq->fence.seqno)); | |
1484 | ||
326611dd | 1485 | if (is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask)) |
ea593dbb CW |
1486 | i915_sw_fence_await_sw_fence(&rq->submit, |
1487 | &prev->submit, | |
1488 | &rq->submitq); | |
1489 | else | |
1490 | __i915_sw_fence_await_dma_fence(&rq->submit, | |
1491 | &prev->fence, | |
1492 | &rq->dmaq); | |
1493 | if (rq->engine->schedule) | |
1494 | __i915_sched_node_add_dependency(&rq->sched, | |
1495 | &prev->sched, | |
1496 | &rq->dep, | |
1497 | 0); | |
1498 | } | |
1499 | ||
2ccdf6a1 CW |
1500 | /* |
1501 | * Make sure that no request gazumped us - if it was allocated after | |
1502 | * our i915_request_alloc() and called __i915_request_add() before | |
1503 | * us, the timeline will hold its seqno which is later than ours. | |
1504 | */ | |
ea593dbb | 1505 | GEM_BUG_ON(timeline->seqno != rq->fence.seqno); |
ea593dbb CW |
1506 | |
1507 | return prev; | |
1508 | } | |
1509 | ||
05235c53 CW |
1510 | /* |
1511 | * NB: This function is not allowed to fail. Doing so would mean the the | |
1512 | * request is not being tracked for completion but the work itself is | |
1513 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
1514 | */ | |
2ccdf6a1 | 1515 | struct i915_request *__i915_request_commit(struct i915_request *rq) |
05235c53 | 1516 | { |
2ccdf6a1 CW |
1517 | struct intel_engine_cs *engine = rq->engine; |
1518 | struct intel_ring *ring = rq->ring; | |
73dec95e | 1519 | u32 *cs; |
05235c53 | 1520 | |
639f2f24 | 1521 | RQ_TRACE(rq, "\n"); |
c781c978 | 1522 | |
05235c53 CW |
1523 | /* |
1524 | * To ensure that this call will not fail, space for its emissions | |
1525 | * should already have been reserved in the ring buffer. Let the ring | |
1526 | * know that it is time to use that space up. | |
1527 | */ | |
2ccdf6a1 CW |
1528 | GEM_BUG_ON(rq->reserved_space > ring->space); |
1529 | rq->reserved_space = 0; | |
e5dadff4 | 1530 | rq->emitted_jiffies = jiffies; |
05235c53 | 1531 | |
8ac71d1d CW |
1532 | /* |
1533 | * Record the position of the start of the breadcrumb so that | |
05235c53 CW |
1534 | * should we detect the updated seqno part-way through the |
1535 | * GPU processing the request, we never over-estimate the | |
d045446d | 1536 | * position of the ring's HEAD. |
05235c53 | 1537 | */ |
2ccdf6a1 | 1538 | cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw); |
73dec95e | 1539 | GEM_BUG_ON(IS_ERR(cs)); |
2ccdf6a1 | 1540 | rq->postfix = intel_ring_offset(rq, cs); |
05235c53 | 1541 | |
e5dadff4 | 1542 | return __i915_request_add_to_timeline(rq); |
a79ca656 CW |
1543 | } |
1544 | ||
1545 | void __i915_request_queue(struct i915_request *rq, | |
1546 | const struct i915_sched_attr *attr) | |
1547 | { | |
8ac71d1d CW |
1548 | /* |
1549 | * Let the backend know a new request has arrived that may need | |
0de9136d CW |
1550 | * to adjust the existing execution schedule due to a high priority |
1551 | * request - i.e. we may want to preempt the current request in order | |
1552 | * to run a high priority dependency chain *before* we can execute this | |
1553 | * request. | |
1554 | * | |
1555 | * This is called before the request is ready to run so that we can | |
1556 | * decide whether to preempt the entire chain so that it is ready to | |
1557 | * run at the earliest possible convenience. | |
1558 | */ | |
a79ca656 CW |
1559 | if (attr && rq->engine->schedule) |
1560 | rq->engine->schedule(rq, attr); | |
209df10b | 1561 | i915_sw_fence_commit(&rq->semaphore); |
2ccdf6a1 | 1562 | i915_sw_fence_commit(&rq->submit); |
2ccdf6a1 CW |
1563 | } |
1564 | ||
1565 | void i915_request_add(struct i915_request *rq) | |
1566 | { | |
d19d71fc | 1567 | struct intel_timeline * const tl = i915_request_timeline(rq); |
e6ba7648 | 1568 | struct i915_sched_attr attr = {}; |
61231f6b | 1569 | struct i915_gem_context *ctx; |
2ccdf6a1 | 1570 | |
e5dadff4 CW |
1571 | lockdep_assert_held(&tl->mutex); |
1572 | lockdep_unpin_lock(&tl->mutex, rq->cookie); | |
2ccdf6a1 CW |
1573 | |
1574 | trace_i915_request_add(rq); | |
61231f6b | 1575 | __i915_request_commit(rq); |
2ccdf6a1 | 1576 | |
61231f6b CW |
1577 | /* XXX placeholder for selftests */ |
1578 | rcu_read_lock(); | |
1579 | ctx = rcu_dereference(rq->context->gem_context); | |
1580 | if (ctx) | |
1581 | attr = ctx->sched; | |
1582 | rcu_read_unlock(); | |
e6ba7648 | 1583 | |
a79ca656 CW |
1584 | __i915_request_queue(rq, &attr); |
1585 | ||
e5dadff4 | 1586 | mutex_unlock(&tl->mutex); |
05235c53 CW |
1587 | } |
1588 | ||
062444bb | 1589 | static unsigned long local_clock_ns(unsigned int *cpu) |
05235c53 CW |
1590 | { |
1591 | unsigned long t; | |
1592 | ||
e61e0f51 CW |
1593 | /* |
1594 | * Cheaply and approximately convert from nanoseconds to microseconds. | |
05235c53 CW |
1595 | * The result and subsequent calculations are also defined in the same |
1596 | * approximate microseconds units. The principal source of timing | |
1597 | * error here is from the simple truncation. | |
1598 | * | |
1599 | * Note that local_clock() is only defined wrt to the current CPU; | |
1600 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1601 | * blocking preemption for the entire busywait, we can detect the CPU | |
1602 | * switch and use that as indicator of system load and a reason to | |
1603 | * stop busywaiting, see busywait_stop(). | |
1604 | */ | |
1605 | *cpu = get_cpu(); | |
062444bb | 1606 | t = local_clock(); |
05235c53 CW |
1607 | put_cpu(); |
1608 | ||
1609 | return t; | |
1610 | } | |
1611 | ||
1612 | static bool busywait_stop(unsigned long timeout, unsigned int cpu) | |
1613 | { | |
1614 | unsigned int this_cpu; | |
1615 | ||
062444bb | 1616 | if (time_after(local_clock_ns(&this_cpu), timeout)) |
05235c53 CW |
1617 | return true; |
1618 | ||
1619 | return this_cpu != cpu; | |
1620 | } | |
1621 | ||
3f6a6f34 | 1622 | static bool __i915_spin_request(struct i915_request * const rq, int state) |
05235c53 | 1623 | { |
062444bb | 1624 | unsigned long timeout_ns; |
52c0fdb2 | 1625 | unsigned int cpu; |
b2f2f0fc CW |
1626 | |
1627 | /* | |
1628 | * Only wait for the request if we know it is likely to complete. | |
1629 | * | |
1630 | * We don't track the timestamps around requests, nor the average | |
1631 | * request length, so we do not have a good indicator that this | |
1632 | * request will complete within the timeout. What we do know is the | |
52c0fdb2 CW |
1633 | * order in which requests are executed by the context and so we can |
1634 | * tell if the request has been started. If the request is not even | |
1635 | * running yet, it is a fair assumption that it will not complete | |
1636 | * within our relatively short timeout. | |
b2f2f0fc | 1637 | */ |
52c0fdb2 | 1638 | if (!i915_request_is_running(rq)) |
b2f2f0fc CW |
1639 | return false; |
1640 | ||
e61e0f51 CW |
1641 | /* |
1642 | * When waiting for high frequency requests, e.g. during synchronous | |
05235c53 CW |
1643 | * rendering split between the CPU and GPU, the finite amount of time |
1644 | * required to set up the irq and wait upon it limits the response | |
1645 | * rate. By busywaiting on the request completion for a short while we | |
1646 | * can service the high frequency waits as quick as possible. However, | |
1647 | * if it is a slow request, we want to sleep as quickly as possible. | |
1648 | * The tradeoff between waiting and sleeping is roughly the time it | |
1649 | * takes to sleep on a request, on the order of a microsecond. | |
1650 | */ | |
1651 | ||
062444bb CW |
1652 | timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns); |
1653 | timeout_ns += local_clock_ns(&cpu); | |
05235c53 | 1654 | do { |
3f6a6f34 | 1655 | if (dma_fence_is_signaled(&rq->fence)) |
52c0fdb2 | 1656 | return true; |
c33ed067 | 1657 | |
05235c53 CW |
1658 | if (signal_pending_state(state, current)) |
1659 | break; | |
1660 | ||
062444bb | 1661 | if (busywait_stop(timeout_ns, cpu)) |
05235c53 CW |
1662 | break; |
1663 | ||
f2f09a4c | 1664 | cpu_relax(); |
05235c53 CW |
1665 | } while (!need_resched()); |
1666 | ||
1667 | return false; | |
1668 | } | |
1669 | ||
52c0fdb2 CW |
1670 | struct request_wait { |
1671 | struct dma_fence_cb cb; | |
1672 | struct task_struct *tsk; | |
1673 | }; | |
1674 | ||
1675 | static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb) | |
1676 | { | |
1677 | struct request_wait *wait = container_of(cb, typeof(*wait), cb); | |
1678 | ||
3f6a6f34 | 1679 | wake_up_process(fetch_and_zero(&wait->tsk)); |
52c0fdb2 CW |
1680 | } |
1681 | ||
05235c53 | 1682 | /** |
e532be89 | 1683 | * i915_request_wait - wait until execution of request has finished |
e61e0f51 | 1684 | * @rq: the request to wait upon |
ea746f36 | 1685 | * @flags: how to wait |
e95433c7 CW |
1686 | * @timeout: how long to wait in jiffies |
1687 | * | |
e532be89 | 1688 | * i915_request_wait() waits for the request to be completed, for a |
e95433c7 CW |
1689 | * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an |
1690 | * unbounded wait). | |
05235c53 | 1691 | * |
e95433c7 CW |
1692 | * Returns the remaining time (in jiffies) if the request completed, which may |
1693 | * be zero or -ETIME if the request is unfinished after the timeout expires. | |
1694 | * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is | |
1695 | * pending before the request completes. | |
05235c53 | 1696 | */ |
e61e0f51 | 1697 | long i915_request_wait(struct i915_request *rq, |
e95433c7 CW |
1698 | unsigned int flags, |
1699 | long timeout) | |
05235c53 | 1700 | { |
ea746f36 CW |
1701 | const int state = flags & I915_WAIT_INTERRUPTIBLE ? |
1702 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
52c0fdb2 | 1703 | struct request_wait wait; |
05235c53 CW |
1704 | |
1705 | might_sleep(); | |
e95433c7 | 1706 | GEM_BUG_ON(timeout < 0); |
05235c53 | 1707 | |
6e4e9708 | 1708 | if (dma_fence_is_signaled(&rq->fence)) |
e95433c7 | 1709 | return timeout; |
05235c53 | 1710 | |
e95433c7 CW |
1711 | if (!timeout) |
1712 | return -ETIME; | |
05235c53 | 1713 | |
e61e0f51 | 1714 | trace_i915_request_wait_begin(rq, flags); |
84383d2e CW |
1715 | |
1716 | /* | |
1717 | * We must never wait on the GPU while holding a lock as we | |
1718 | * may need to perform a GPU reset. So while we don't need to | |
1719 | * serialise wait/reset with an explicit lock, we do want | |
1720 | * lockdep to detect potential dependency cycles. | |
1721 | */ | |
cb823ed9 | 1722 | mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_); |
4680816b | 1723 | |
7ce99d24 CW |
1724 | /* |
1725 | * Optimistic spin before touching IRQs. | |
1726 | * | |
1727 | * We may use a rather large value here to offset the penalty of | |
1728 | * switching away from the active task. Frequently, the client will | |
1729 | * wait upon an old swapbuffer to throttle itself to remain within a | |
1730 | * frame of the gpu. If the client is running in lockstep with the gpu, | |
1731 | * then it should not be waiting long at all, and a sleep now will incur | |
1732 | * extra scheduler latency in producing the next frame. To try to | |
1733 | * avoid adding the cost of enabling/disabling the interrupt to the | |
1734 | * short wait, we first spin to see if the request would have completed | |
1735 | * in the time taken to setup the interrupt. | |
1736 | * | |
1737 | * We need upto 5us to enable the irq, and upto 20us to hide the | |
1738 | * scheduler latency of a context switch, ignoring the secondary | |
1739 | * impacts from a context switch such as cache eviction. | |
1740 | * | |
1741 | * The scheme used for low-latency IO is called "hybrid interrupt | |
1742 | * polling". The suggestion there is to sleep until just before you | |
1743 | * expect to be woken by the device interrupt and then poll for its | |
1744 | * completion. That requires having a good predictor for the request | |
1745 | * duration, which we currently lack. | |
1746 | */ | |
062444bb | 1747 | if (IS_ACTIVE(CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT) && |
3f6a6f34 | 1748 | __i915_spin_request(rq, state)) |
52c0fdb2 | 1749 | goto out; |
541ca6ed | 1750 | |
62eb3c24 CW |
1751 | /* |
1752 | * This client is about to stall waiting for the GPU. In many cases | |
1753 | * this is undesirable and limits the throughput of the system, as | |
1754 | * many clients cannot continue processing user input/output whilst | |
1755 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
1756 | * to the GPU load and thus incurs additional latency for the client. | |
1757 | * We can circumvent that by promoting the GPU frequency to maximum | |
1758 | * before we sleep. This makes the GPU throttle up much more quickly | |
1759 | * (good for benchmarks and user experience, e.g. window animations), | |
1760 | * but at a cost of spending more power processing the workload | |
1761 | * (bad for battery). | |
1762 | */ | |
1840d40a CW |
1763 | if (flags & I915_WAIT_PRIORITY && !i915_request_started(rq)) |
1764 | intel_rps_boost(rq); | |
4680816b | 1765 | |
52c0fdb2 CW |
1766 | wait.tsk = current; |
1767 | if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake)) | |
1768 | goto out; | |
4680816b | 1769 | |
3adee4ac CW |
1770 | /* |
1771 | * Flush the submission tasklet, but only if it may help this request. | |
1772 | * | |
1773 | * We sometimes experience some latency between the HW interrupts and | |
1774 | * tasklet execution (mostly due to ksoftirqd latency, but it can also | |
1775 | * be due to lazy CS events), so lets run the tasklet manually if there | |
1776 | * is a chance it may submit this request. If the request is not ready | |
1777 | * to run, as it is waiting for other fences to be signaled, flushing | |
1778 | * the tasklet is busy work without any advantage for this client. | |
1779 | * | |
1780 | * If the HW is being lazy, this is the last chance before we go to | |
1781 | * sleep to catch any pending events. We will check periodically in | |
1782 | * the heartbeat to flush the submission tasklets as a last resort | |
1783 | * for unhappy HW. | |
1784 | */ | |
1785 | if (i915_request_is_ready(rq)) | |
1786 | intel_engine_flush_submission(rq->engine); | |
1787 | ||
52c0fdb2 CW |
1788 | for (;;) { |
1789 | set_current_state(state); | |
05235c53 | 1790 | |
3f6a6f34 | 1791 | if (dma_fence_is_signaled(&rq->fence)) |
52c0fdb2 | 1792 | break; |
05235c53 | 1793 | |
05235c53 | 1794 | if (signal_pending_state(state, current)) { |
e95433c7 | 1795 | timeout = -ERESTARTSYS; |
05235c53 CW |
1796 | break; |
1797 | } | |
1798 | ||
e95433c7 CW |
1799 | if (!timeout) { |
1800 | timeout = -ETIME; | |
05235c53 CW |
1801 | break; |
1802 | } | |
1803 | ||
e95433c7 | 1804 | timeout = io_schedule_timeout(timeout); |
05235c53 | 1805 | } |
a49625f9 | 1806 | __set_current_state(TASK_RUNNING); |
05235c53 | 1807 | |
3f6a6f34 CW |
1808 | if (READ_ONCE(wait.tsk)) |
1809 | dma_fence_remove_callback(&rq->fence, &wait.cb); | |
1810 | GEM_BUG_ON(!list_empty(&wait.cb.node)); | |
52c0fdb2 CW |
1811 | |
1812 | out: | |
5facae4f | 1813 | mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_); |
52c0fdb2 | 1814 | trace_i915_request_wait_end(rq); |
e95433c7 | 1815 | return timeout; |
05235c53 | 1816 | } |
4b8de8e6 | 1817 | |
c835c550 CW |
1818 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
1819 | #include "selftests/mock_request.c" | |
e61e0f51 | 1820 | #include "selftests/i915_request.c" |
c835c550 | 1821 | #endif |
32eb6bcf | 1822 | |
103b76ee CW |
1823 | static void i915_global_request_shrink(void) |
1824 | { | |
103b76ee CW |
1825 | kmem_cache_shrink(global.slab_execute_cbs); |
1826 | kmem_cache_shrink(global.slab_requests); | |
1827 | } | |
1828 | ||
1829 | static void i915_global_request_exit(void) | |
1830 | { | |
103b76ee CW |
1831 | kmem_cache_destroy(global.slab_execute_cbs); |
1832 | kmem_cache_destroy(global.slab_requests); | |
1833 | } | |
1834 | ||
1835 | static struct i915_global_request global = { { | |
1836 | .shrink = i915_global_request_shrink, | |
1837 | .exit = i915_global_request_exit, | |
1838 | } }; | |
1839 | ||
32eb6bcf CW |
1840 | int __init i915_global_request_init(void) |
1841 | { | |
67a3acaa CW |
1842 | global.slab_requests = |
1843 | kmem_cache_create("i915_request", | |
1844 | sizeof(struct i915_request), | |
1845 | __alignof__(struct i915_request), | |
1846 | SLAB_HWCACHE_ALIGN | | |
1847 | SLAB_RECLAIM_ACCOUNT | | |
1848 | SLAB_TYPESAFE_BY_RCU, | |
1849 | __i915_request_ctor); | |
32eb6bcf CW |
1850 | if (!global.slab_requests) |
1851 | return -ENOMEM; | |
1852 | ||
e8861964 CW |
1853 | global.slab_execute_cbs = KMEM_CACHE(execute_cb, |
1854 | SLAB_HWCACHE_ALIGN | | |
1855 | SLAB_RECLAIM_ACCOUNT | | |
1856 | SLAB_TYPESAFE_BY_RCU); | |
1857 | if (!global.slab_execute_cbs) | |
1858 | goto err_requests; | |
1859 | ||
103b76ee | 1860 | i915_global_register(&global.base); |
32eb6bcf CW |
1861 | return 0; |
1862 | ||
1863 | err_requests: | |
1864 | kmem_cache_destroy(global.slab_requests); | |
1865 | return -ENOMEM; | |
1866 | } |