Commit | Line | Data |
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05235c53 CW |
1 | /* |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
fa545cbf | 25 | #include <linux/prefetch.h> |
b52992c0 | 26 | #include <linux/dma-fence-array.h> |
e6017571 IM |
27 | #include <linux/sched.h> |
28 | #include <linux/sched/clock.h> | |
f361bf4a | 29 | #include <linux/sched/signal.h> |
fa545cbf | 30 | |
05235c53 | 31 | #include "i915_drv.h" |
9f58892e | 32 | #include "i915_reset.h" |
05235c53 | 33 | |
f54d1867 | 34 | static const char *i915_fence_get_driver_name(struct dma_fence *fence) |
04769652 CW |
35 | { |
36 | return "i915"; | |
37 | } | |
38 | ||
f54d1867 | 39 | static const char *i915_fence_get_timeline_name(struct dma_fence *fence) |
04769652 | 40 | { |
e61e0f51 CW |
41 | /* |
42 | * The timeline struct (as part of the ppgtt underneath a context) | |
05506b5b CW |
43 | * may be freed when the request is no longer in use by the GPU. |
44 | * We could extend the life of a context to beyond that of all | |
45 | * fences, possibly keeping the hw resource around indefinitely, | |
46 | * or we just give them a false name. Since | |
47 | * dma_fence_ops.get_timeline_name is a debug feature, the occasional | |
48 | * lie seems justifiable. | |
49 | */ | |
50 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
51 | return "signaled"; | |
52 | ||
a89d1f92 | 53 | return to_request(fence)->timeline->name; |
04769652 CW |
54 | } |
55 | ||
f54d1867 | 56 | static bool i915_fence_signaled(struct dma_fence *fence) |
04769652 | 57 | { |
e61e0f51 | 58 | return i915_request_completed(to_request(fence)); |
04769652 CW |
59 | } |
60 | ||
f54d1867 | 61 | static bool i915_fence_enable_signaling(struct dma_fence *fence) |
04769652 | 62 | { |
6f9ec414 | 63 | return intel_engine_enable_signaling(to_request(fence), true); |
04769652 CW |
64 | } |
65 | ||
f54d1867 | 66 | static signed long i915_fence_wait(struct dma_fence *fence, |
04769652 | 67 | bool interruptible, |
e95433c7 | 68 | signed long timeout) |
04769652 | 69 | { |
e61e0f51 | 70 | return i915_request_wait(to_request(fence), interruptible, timeout); |
04769652 CW |
71 | } |
72 | ||
f54d1867 | 73 | static void i915_fence_release(struct dma_fence *fence) |
04769652 | 74 | { |
e61e0f51 | 75 | struct i915_request *rq = to_request(fence); |
04769652 | 76 | |
e61e0f51 CW |
77 | /* |
78 | * The request is put onto a RCU freelist (i.e. the address | |
fc158405 CW |
79 | * is immediately reused), mark the fences as being freed now. |
80 | * Otherwise the debugobjects for the fences are only marked as | |
81 | * freed when the slab cache itself is freed, and so we would get | |
82 | * caught trying to reuse dead objects. | |
83 | */ | |
e61e0f51 | 84 | i915_sw_fence_fini(&rq->submit); |
fc158405 | 85 | |
e61e0f51 | 86 | kmem_cache_free(rq->i915->requests, rq); |
04769652 CW |
87 | } |
88 | ||
f54d1867 | 89 | const struct dma_fence_ops i915_fence_ops = { |
04769652 CW |
90 | .get_driver_name = i915_fence_get_driver_name, |
91 | .get_timeline_name = i915_fence_get_timeline_name, | |
92 | .enable_signaling = i915_fence_enable_signaling, | |
93 | .signaled = i915_fence_signaled, | |
94 | .wait = i915_fence_wait, | |
95 | .release = i915_fence_release, | |
04769652 CW |
96 | }; |
97 | ||
05235c53 | 98 | static inline void |
e61e0f51 | 99 | i915_request_remove_from_client(struct i915_request *request) |
05235c53 | 100 | { |
c8659efa | 101 | struct drm_i915_file_private *file_priv; |
05235c53 | 102 | |
c8659efa | 103 | file_priv = request->file_priv; |
05235c53 CW |
104 | if (!file_priv) |
105 | return; | |
106 | ||
107 | spin_lock(&file_priv->mm.lock); | |
c8659efa CW |
108 | if (request->file_priv) { |
109 | list_del(&request->client_link); | |
110 | request->file_priv = NULL; | |
111 | } | |
05235c53 | 112 | spin_unlock(&file_priv->mm.lock); |
05235c53 CW |
113 | } |
114 | ||
6faf5916 | 115 | static void reserve_gt(struct drm_i915_private *i915) |
12d3173b | 116 | { |
636918f1 | 117 | if (!i915->gt.active_requests++) |
e4d2006f | 118 | i915_gem_unpark(i915); |
12d3173b CW |
119 | } |
120 | ||
52d7f16e | 121 | static void unreserve_gt(struct drm_i915_private *i915) |
9b6586ae | 122 | { |
b887d615 | 123 | GEM_BUG_ON(!i915->gt.active_requests); |
e4d2006f CW |
124 | if (!--i915->gt.active_requests) |
125 | i915_gem_park(i915); | |
9b6586ae CW |
126 | } |
127 | ||
fa545cbf | 128 | void i915_gem_retire_noop(struct i915_gem_active *active, |
e61e0f51 | 129 | struct i915_request *request) |
fa545cbf CW |
130 | { |
131 | /* Space left intentionally blank */ | |
132 | } | |
133 | ||
e61e0f51 | 134 | static void advance_ring(struct i915_request *request) |
cbb60b4b | 135 | { |
b887d615 | 136 | struct intel_ring *ring = request->ring; |
cbb60b4b CW |
137 | unsigned int tail; |
138 | ||
e61e0f51 CW |
139 | /* |
140 | * We know the GPU must have read the request to have | |
cbb60b4b CW |
141 | * sent us the seqno + interrupt, so use the position |
142 | * of tail of the request to update the last known position | |
143 | * of the GPU head. | |
144 | * | |
145 | * Note this requires that we are always called in request | |
146 | * completion order. | |
147 | */ | |
b887d615 CW |
148 | GEM_BUG_ON(!list_is_first(&request->ring_link, &ring->request_list)); |
149 | if (list_is_last(&request->ring_link, &ring->request_list)) { | |
e61e0f51 CW |
150 | /* |
151 | * We may race here with execlists resubmitting this request | |
e6ba9992 CW |
152 | * as we retire it. The resubmission will move the ring->tail |
153 | * forwards (to request->wa_tail). We either read the | |
154 | * current value that was written to hw, or the value that | |
155 | * is just about to be. Either works, if we miss the last two | |
156 | * noops - they are safe to be replayed on a reset. | |
157 | */ | |
09a4c02e | 158 | GEM_TRACE("marking %s as inactive\n", ring->timeline->name); |
36620032 | 159 | tail = READ_ONCE(request->tail); |
643b450a | 160 | list_del(&ring->active_link); |
e6ba9992 | 161 | } else { |
cbb60b4b | 162 | tail = request->postfix; |
e6ba9992 | 163 | } |
b887d615 | 164 | list_del_init(&request->ring_link); |
cbb60b4b | 165 | |
b887d615 | 166 | ring->head = tail; |
cbb60b4b CW |
167 | } |
168 | ||
e61e0f51 | 169 | static void free_capture_list(struct i915_request *request) |
b0fd47ad | 170 | { |
e61e0f51 | 171 | struct i915_capture_list *capture; |
b0fd47ad CW |
172 | |
173 | capture = request->capture_list; | |
174 | while (capture) { | |
e61e0f51 | 175 | struct i915_capture_list *next = capture->next; |
b0fd47ad CW |
176 | |
177 | kfree(capture); | |
178 | capture = next; | |
179 | } | |
180 | } | |
181 | ||
b887d615 CW |
182 | static void __retire_engine_request(struct intel_engine_cs *engine, |
183 | struct i915_request *rq) | |
184 | { | |
3adac468 | 185 | GEM_TRACE("%s(%s) fence %llx:%lld, global=%d, current %d:%d\n", |
b887d615 CW |
186 | __func__, engine->name, |
187 | rq->fence.context, rq->fence.seqno, | |
188 | rq->global_seqno, | |
3adac468 | 189 | hwsp_seqno(rq), |
b887d615 CW |
190 | intel_engine_get_seqno(engine)); |
191 | ||
192 | GEM_BUG_ON(!i915_request_completed(rq)); | |
193 | ||
194 | local_irq_disable(); | |
195 | ||
a89d1f92 CW |
196 | spin_lock(&engine->timeline.lock); |
197 | GEM_BUG_ON(!list_is_first(&rq->link, &engine->timeline.requests)); | |
b887d615 | 198 | list_del_init(&rq->link); |
a89d1f92 | 199 | spin_unlock(&engine->timeline.lock); |
b887d615 CW |
200 | |
201 | spin_lock(&rq->lock); | |
5013eb8c | 202 | i915_request_mark_complete(rq); |
0e21834e | 203 | if (!i915_request_signaled(rq)) |
b887d615 CW |
204 | dma_fence_signal_locked(&rq->fence); |
205 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) | |
206 | intel_engine_cancel_signaling(rq); | |
207 | if (rq->waitboost) { | |
208 | GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters)); | |
209 | atomic_dec(&rq->i915->gt_pm.rps.num_waiters); | |
210 | } | |
211 | spin_unlock(&rq->lock); | |
212 | ||
213 | local_irq_enable(); | |
214 | ||
215 | /* | |
216 | * The backing object for the context is done after switching to the | |
217 | * *next* context. Therefore we cannot retire the previous context until | |
218 | * the next context has already started running. However, since we | |
219 | * cannot take the required locks at i915_request_submit() we | |
220 | * defer the unpinning of the active context to now, retirement of | |
221 | * the subsequent request. | |
222 | */ | |
223 | if (engine->last_retired_context) | |
1fc44d9b CW |
224 | intel_context_unpin(engine->last_retired_context); |
225 | engine->last_retired_context = rq->hw_context; | |
b887d615 CW |
226 | } |
227 | ||
228 | static void __retire_engine_upto(struct intel_engine_cs *engine, | |
229 | struct i915_request *rq) | |
230 | { | |
231 | struct i915_request *tmp; | |
232 | ||
233 | if (list_empty(&rq->link)) | |
234 | return; | |
235 | ||
236 | do { | |
a89d1f92 | 237 | tmp = list_first_entry(&engine->timeline.requests, |
b887d615 CW |
238 | typeof(*tmp), link); |
239 | ||
240 | GEM_BUG_ON(tmp->engine != engine); | |
241 | __retire_engine_request(engine, tmp); | |
242 | } while (tmp != rq); | |
243 | } | |
244 | ||
e61e0f51 | 245 | static void i915_request_retire(struct i915_request *request) |
05235c53 | 246 | { |
fa545cbf CW |
247 | struct i915_gem_active *active, *next; |
248 | ||
3adac468 | 249 | GEM_TRACE("%s fence %llx:%lld, global=%d, current %d:%d\n", |
b887d615 | 250 | request->engine->name, |
d9b13c4d | 251 | request->fence.context, request->fence.seqno, |
e7702760 | 252 | request->global_seqno, |
3adac468 | 253 | hwsp_seqno(request), |
b887d615 | 254 | intel_engine_get_seqno(request->engine)); |
d9b13c4d | 255 | |
4c7d62c6 | 256 | lockdep_assert_held(&request->i915->drm.struct_mutex); |
48bc2a4a | 257 | GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit)); |
e61e0f51 | 258 | GEM_BUG_ON(!i915_request_completed(request)); |
4c7d62c6 | 259 | |
e61e0f51 | 260 | trace_i915_request_retire(request); |
80b204bc | 261 | |
cbb60b4b | 262 | advance_ring(request); |
b0fd47ad CW |
263 | free_capture_list(request); |
264 | ||
e61e0f51 CW |
265 | /* |
266 | * Walk through the active list, calling retire on each. This allows | |
fa545cbf CW |
267 | * objects to track their GPU activity and mark themselves as idle |
268 | * when their *last* active request is completed (updating state | |
269 | * tracking lists for eviction, active references for GEM, etc). | |
270 | * | |
271 | * As the ->retire() may free the node, we decouple it first and | |
272 | * pass along the auxiliary information (to avoid dereferencing | |
273 | * the node after the callback). | |
274 | */ | |
275 | list_for_each_entry_safe(active, next, &request->active_list, link) { | |
e61e0f51 CW |
276 | /* |
277 | * In microbenchmarks or focusing upon time inside the kernel, | |
fa545cbf CW |
278 | * we may spend an inordinate amount of time simply handling |
279 | * the retirement of requests and processing their callbacks. | |
280 | * Of which, this loop itself is particularly hot due to the | |
281 | * cache misses when jumping around the list of i915_gem_active. | |
282 | * So we try to keep this loop as streamlined as possible and | |
283 | * also prefetch the next i915_gem_active to try and hide | |
284 | * the likely cache miss. | |
285 | */ | |
286 | prefetchw(next); | |
287 | ||
288 | INIT_LIST_HEAD(&active->link); | |
0eafec6d | 289 | RCU_INIT_POINTER(active->request, NULL); |
fa545cbf CW |
290 | |
291 | active->retire(active, request); | |
292 | } | |
293 | ||
e61e0f51 | 294 | i915_request_remove_from_client(request); |
05235c53 | 295 | |
e5e1fc47 | 296 | /* Retirement decays the ban score as it is a sign of ctx progress */ |
4e0d64db | 297 | atomic_dec_if_positive(&request->gem_context->ban_score); |
1fc44d9b | 298 | intel_context_unpin(request->hw_context); |
e5e1fc47 | 299 | |
b887d615 | 300 | __retire_engine_upto(request->engine, request); |
52e54209 | 301 | |
52d7f16e CW |
302 | unreserve_gt(request->i915); |
303 | ||
0c7112a0 | 304 | i915_sched_node_fini(request->i915, &request->sched); |
e61e0f51 | 305 | i915_request_put(request); |
05235c53 CW |
306 | } |
307 | ||
e61e0f51 | 308 | void i915_request_retire_upto(struct i915_request *rq) |
05235c53 | 309 | { |
b887d615 | 310 | struct intel_ring *ring = rq->ring; |
e61e0f51 | 311 | struct i915_request *tmp; |
05235c53 | 312 | |
3adac468 | 313 | GEM_TRACE("%s fence %llx:%lld, global=%d, current %d:%d\n", |
b887d615 CW |
314 | rq->engine->name, |
315 | rq->fence.context, rq->fence.seqno, | |
316 | rq->global_seqno, | |
3adac468 | 317 | hwsp_seqno(rq), |
b887d615 CW |
318 | intel_engine_get_seqno(rq->engine)); |
319 | ||
e61e0f51 CW |
320 | lockdep_assert_held(&rq->i915->drm.struct_mutex); |
321 | GEM_BUG_ON(!i915_request_completed(rq)); | |
4ffd6e0c | 322 | |
b887d615 | 323 | if (list_empty(&rq->ring_link)) |
e95433c7 | 324 | return; |
05235c53 CW |
325 | |
326 | do { | |
b887d615 CW |
327 | tmp = list_first_entry(&ring->request_list, |
328 | typeof(*tmp), ring_link); | |
05235c53 | 329 | |
e61e0f51 CW |
330 | i915_request_retire(tmp); |
331 | } while (tmp != rq); | |
05235c53 CW |
332 | } |
333 | ||
a89d1f92 | 334 | static u32 timeline_get_seqno(struct i915_timeline *tl) |
05235c53 | 335 | { |
85474441 | 336 | return tl->seqno += 1 + tl->has_initial_breadcrumb; |
28176ef4 CW |
337 | } |
338 | ||
4ccfee92 | 339 | static void move_to_timeline(struct i915_request *request, |
a89d1f92 | 340 | struct i915_timeline *timeline) |
4ccfee92 | 341 | { |
a89d1f92 CW |
342 | GEM_BUG_ON(request->timeline == &request->engine->timeline); |
343 | lockdep_assert_held(&request->engine->timeline.lock); | |
4ccfee92 | 344 | |
890fd185 | 345 | spin_lock(&request->timeline->lock); |
4ccfee92 CW |
346 | list_move_tail(&request->link, &timeline->requests); |
347 | spin_unlock(&request->timeline->lock); | |
348 | } | |
349 | ||
f1e9c909 CW |
350 | static u32 next_global_seqno(struct i915_timeline *tl) |
351 | { | |
352 | if (!++tl->seqno) | |
353 | ++tl->seqno; | |
354 | return tl->seqno; | |
355 | } | |
356 | ||
e61e0f51 | 357 | void __i915_request_submit(struct i915_request *request) |
5590af3e | 358 | { |
73cb9701 | 359 | struct intel_engine_cs *engine = request->engine; |
f2d13290 | 360 | u32 seqno; |
5590af3e | 361 | |
3adac468 | 362 | GEM_TRACE("%s fence %llx:%lld -> global=%d, current %d:%d\n", |
e7702760 | 363 | engine->name, |
d9b13c4d | 364 | request->fence.context, request->fence.seqno, |
a89d1f92 | 365 | engine->timeline.seqno + 1, |
3adac468 | 366 | hwsp_seqno(request), |
e7702760 | 367 | intel_engine_get_seqno(engine)); |
d9b13c4d | 368 | |
e60a870d | 369 | GEM_BUG_ON(!irqs_disabled()); |
a89d1f92 | 370 | lockdep_assert_held(&engine->timeline.lock); |
e60a870d | 371 | |
2d453c78 | 372 | GEM_BUG_ON(request->global_seqno); |
5590af3e | 373 | |
f1e9c909 | 374 | seqno = next_global_seqno(&engine->timeline); |
f2d13290 | 375 | GEM_BUG_ON(!seqno); |
97f06158 | 376 | GEM_BUG_ON(intel_engine_signaled(engine, seqno)); |
f2d13290 | 377 | |
f2d13290 CW |
378 | /* We may be recursing from the signal callback of another i915 fence */ |
379 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
380 | request->global_seqno = seqno; | |
381 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) | |
f7b02a52 | 382 | intel_engine_enable_signaling(request, false); |
f2d13290 CW |
383 | spin_unlock(&request->lock); |
384 | ||
85474441 CW |
385 | engine->emit_fini_breadcrumb(request, |
386 | request->ring->vaddr + request->postfix); | |
5590af3e | 387 | |
4ccfee92 | 388 | /* Transfer from per-context onto the global per-engine timeline */ |
a89d1f92 | 389 | move_to_timeline(request, &engine->timeline); |
80b204bc | 390 | |
e61e0f51 | 391 | trace_i915_request_execute(request); |
158863fb | 392 | |
fe49789f | 393 | wake_up_all(&request->execute); |
d55ac5bf CW |
394 | } |
395 | ||
e61e0f51 | 396 | void i915_request_submit(struct i915_request *request) |
d55ac5bf CW |
397 | { |
398 | struct intel_engine_cs *engine = request->engine; | |
399 | unsigned long flags; | |
23902e49 | 400 | |
d55ac5bf | 401 | /* Will be called from irq-context when using foreign fences. */ |
a89d1f92 | 402 | spin_lock_irqsave(&engine->timeline.lock, flags); |
d55ac5bf | 403 | |
e61e0f51 | 404 | __i915_request_submit(request); |
d55ac5bf | 405 | |
a89d1f92 | 406 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
d55ac5bf CW |
407 | } |
408 | ||
e61e0f51 | 409 | void __i915_request_unsubmit(struct i915_request *request) |
d55ac5bf | 410 | { |
d6a2289d | 411 | struct intel_engine_cs *engine = request->engine; |
d55ac5bf | 412 | |
3adac468 | 413 | GEM_TRACE("%s fence %llx:%lld <- global=%d, current %d:%d\n", |
e7702760 | 414 | engine->name, |
d9b13c4d | 415 | request->fence.context, request->fence.seqno, |
e7702760 | 416 | request->global_seqno, |
3adac468 | 417 | hwsp_seqno(request), |
e7702760 | 418 | intel_engine_get_seqno(engine)); |
d9b13c4d | 419 | |
e60a870d | 420 | GEM_BUG_ON(!irqs_disabled()); |
a89d1f92 | 421 | lockdep_assert_held(&engine->timeline.lock); |
48bc2a4a | 422 | |
e61e0f51 CW |
423 | /* |
424 | * Only unwind in reverse order, required so that the per-context list | |
d6a2289d CW |
425 | * is kept in seqno/ring order. |
426 | */ | |
2d453c78 | 427 | GEM_BUG_ON(!request->global_seqno); |
a89d1f92 | 428 | GEM_BUG_ON(request->global_seqno != engine->timeline.seqno); |
97f06158 | 429 | GEM_BUG_ON(intel_engine_has_completed(engine, request->global_seqno)); |
a89d1f92 | 430 | engine->timeline.seqno--; |
80b204bc | 431 | |
d6a2289d CW |
432 | /* We may be recursing from the signal callback of another i915 fence */ |
433 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
434 | request->global_seqno = 0; | |
435 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) | |
436 | intel_engine_cancel_signaling(request); | |
437 | spin_unlock(&request->lock); | |
438 | ||
439 | /* Transfer back from the global per-engine timeline to per-context */ | |
4ccfee92 | 440 | move_to_timeline(request, request->timeline); |
d6a2289d | 441 | |
e61e0f51 CW |
442 | /* |
443 | * We don't need to wake_up any waiters on request->execute, they | |
d6a2289d | 444 | * will get woken by any other event or us re-adding this request |
e61e0f51 | 445 | * to the engine timeline (__i915_request_submit()). The waiters |
d6a2289d CW |
446 | * should be quite adapt at finding that the request now has a new |
447 | * global_seqno to the one they went to sleep on. | |
448 | */ | |
449 | } | |
450 | ||
e61e0f51 | 451 | void i915_request_unsubmit(struct i915_request *request) |
d6a2289d CW |
452 | { |
453 | struct intel_engine_cs *engine = request->engine; | |
454 | unsigned long flags; | |
455 | ||
456 | /* Will be called from irq-context when using foreign fences. */ | |
a89d1f92 | 457 | spin_lock_irqsave(&engine->timeline.lock, flags); |
d6a2289d | 458 | |
e61e0f51 | 459 | __i915_request_unsubmit(request); |
d6a2289d | 460 | |
a89d1f92 | 461 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
5590af3e CW |
462 | } |
463 | ||
23902e49 | 464 | static int __i915_sw_fence_call |
d55ac5bf | 465 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
23902e49 | 466 | { |
e61e0f51 | 467 | struct i915_request *request = |
48bc2a4a | 468 | container_of(fence, typeof(*request), submit); |
48bc2a4a CW |
469 | |
470 | switch (state) { | |
471 | case FENCE_COMPLETE: | |
e61e0f51 | 472 | trace_i915_request_submit(request); |
af7a8ffa | 473 | /* |
e61e0f51 CW |
474 | * We need to serialize use of the submit_request() callback |
475 | * with its hotplugging performed during an emergency | |
476 | * i915_gem_set_wedged(). We use the RCU mechanism to mark the | |
477 | * critical section in order to force i915_gem_set_wedged() to | |
478 | * wait until the submit_request() is completed before | |
479 | * proceeding. | |
af7a8ffa DV |
480 | */ |
481 | rcu_read_lock(); | |
d55ac5bf | 482 | request->engine->submit_request(request); |
af7a8ffa | 483 | rcu_read_unlock(); |
48bc2a4a CW |
484 | break; |
485 | ||
486 | case FENCE_FREE: | |
e61e0f51 | 487 | i915_request_put(request); |
48bc2a4a CW |
488 | break; |
489 | } | |
490 | ||
23902e49 CW |
491 | return NOTIFY_DONE; |
492 | } | |
493 | ||
d22ba0cb CW |
494 | static void ring_retire_requests(struct intel_ring *ring) |
495 | { | |
496 | struct i915_request *rq, *rn; | |
497 | ||
498 | list_for_each_entry_safe(rq, rn, &ring->request_list, ring_link) { | |
499 | if (!i915_request_completed(rq)) | |
500 | break; | |
501 | ||
502 | i915_request_retire(rq); | |
503 | } | |
504 | } | |
505 | ||
506 | static noinline struct i915_request * | |
507 | i915_request_alloc_slow(struct intel_context *ce) | |
508 | { | |
509 | struct intel_ring *ring = ce->ring; | |
510 | struct i915_request *rq; | |
511 | ||
512 | if (list_empty(&ring->request_list)) | |
513 | goto out; | |
514 | ||
515 | /* Ratelimit ourselves to prevent oom from malicious clients */ | |
516 | rq = list_last_entry(&ring->request_list, typeof(*rq), ring_link); | |
517 | cond_synchronize_rcu(rq->rcustate); | |
518 | ||
519 | /* Retire our old requests in the hope that we free some */ | |
520 | ring_retire_requests(ring); | |
521 | ||
522 | out: | |
523 | return kmem_cache_alloc(ce->gem_context->i915->requests, GFP_KERNEL); | |
524 | } | |
525 | ||
8e637178 | 526 | /** |
e61e0f51 | 527 | * i915_request_alloc - allocate a request structure |
8e637178 CW |
528 | * |
529 | * @engine: engine that we wish to issue the request on. | |
530 | * @ctx: context that the request will be associated with. | |
8e637178 CW |
531 | * |
532 | * Returns a pointer to the allocated request if successful, | |
533 | * or an error code if not. | |
534 | */ | |
e61e0f51 CW |
535 | struct i915_request * |
536 | i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx) | |
05235c53 | 537 | { |
e61e0f51 CW |
538 | struct drm_i915_private *i915 = engine->i915; |
539 | struct i915_request *rq; | |
1fc44d9b | 540 | struct intel_context *ce; |
05235c53 CW |
541 | int ret; |
542 | ||
e61e0f51 | 543 | lockdep_assert_held(&i915->drm.struct_mutex); |
28176ef4 | 544 | |
e7af3116 CW |
545 | /* |
546 | * Preempt contexts are reserved for exclusive use to inject a | |
547 | * preemption context switch. They are never to be used for any trivial | |
548 | * request! | |
549 | */ | |
e61e0f51 | 550 | GEM_BUG_ON(ctx == i915->preempt_context); |
e7af3116 | 551 | |
e61e0f51 CW |
552 | /* |
553 | * ABI: Before userspace accesses the GPU (e.g. execbuffer), report | |
6ffb7d07 | 554 | * EIO if the GPU is already wedged. |
05235c53 | 555 | */ |
e61e0f51 | 556 | if (i915_terminally_wedged(&i915->gpu_error)) |
6ffb7d07 | 557 | return ERR_PTR(-EIO); |
05235c53 | 558 | |
e61e0f51 CW |
559 | /* |
560 | * Pinning the contexts may generate requests in order to acquire | |
e8a9c58f CW |
561 | * GGTT space, so do this first before we reserve a seqno for |
562 | * ourselves. | |
563 | */ | |
1fc44d9b CW |
564 | ce = intel_context_pin(ctx, engine); |
565 | if (IS_ERR(ce)) | |
566 | return ERR_CAST(ce); | |
28176ef4 | 567 | |
6faf5916 | 568 | reserve_gt(i915); |
e8a9c58f | 569 | |
b887d615 | 570 | /* Move our oldest request to the slab-cache (if not in use!) */ |
1fc44d9b CW |
571 | rq = list_first_entry(&ce->ring->request_list, typeof(*rq), ring_link); |
572 | if (!list_is_last(&rq->ring_link, &ce->ring->request_list) && | |
7c572e1b | 573 | i915_request_completed(rq)) |
e61e0f51 | 574 | i915_request_retire(rq); |
9b5f4e5e | 575 | |
e61e0f51 CW |
576 | /* |
577 | * Beware: Dragons be flying overhead. | |
5a198b8c CW |
578 | * |
579 | * We use RCU to look up requests in flight. The lookups may | |
580 | * race with the request being allocated from the slab freelist. | |
581 | * That is the request we are writing to here, may be in the process | |
1426f715 | 582 | * of being read by __i915_gem_active_get_rcu(). As such, |
5a198b8c CW |
583 | * we have to be very careful when overwriting the contents. During |
584 | * the RCU lookup, we change chase the request->engine pointer, | |
65e4760e | 585 | * read the request->global_seqno and increment the reference count. |
5a198b8c CW |
586 | * |
587 | * The reference count is incremented atomically. If it is zero, | |
588 | * the lookup knows the request is unallocated and complete. Otherwise, | |
589 | * it is either still in use, or has been reallocated and reset | |
f54d1867 CW |
590 | * with dma_fence_init(). This increment is safe for release as we |
591 | * check that the request we have a reference to and matches the active | |
5a198b8c CW |
592 | * request. |
593 | * | |
594 | * Before we increment the refcount, we chase the request->engine | |
595 | * pointer. We must not call kmem_cache_zalloc() or else we set | |
596 | * that pointer to NULL and cause a crash during the lookup. If | |
597 | * we see the request is completed (based on the value of the | |
598 | * old engine and seqno), the lookup is complete and reports NULL. | |
599 | * If we decide the request is not completed (new engine or seqno), | |
600 | * then we grab a reference and double check that it is still the | |
601 | * active request - which it won't be and restart the lookup. | |
602 | * | |
603 | * Do not use kmem_cache_zalloc() here! | |
604 | */ | |
e61e0f51 CW |
605 | rq = kmem_cache_alloc(i915->requests, |
606 | GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); | |
607 | if (unlikely(!rq)) { | |
d22ba0cb | 608 | rq = i915_request_alloc_slow(ce); |
e61e0f51 | 609 | if (!rq) { |
31c70f97 CW |
610 | ret = -ENOMEM; |
611 | goto err_unreserve; | |
612 | } | |
28176ef4 | 613 | } |
05235c53 | 614 | |
11abf0c5 CW |
615 | rq->rcustate = get_state_synchronize_rcu(); |
616 | ||
65fcb806 CW |
617 | INIT_LIST_HEAD(&rq->active_list); |
618 | rq->i915 = i915; | |
619 | rq->engine = engine; | |
4e0d64db | 620 | rq->gem_context = ctx; |
1fc44d9b CW |
621 | rq->hw_context = ce; |
622 | rq->ring = ce->ring; | |
623 | rq->timeline = ce->ring->timeline; | |
a89d1f92 | 624 | GEM_BUG_ON(rq->timeline == &engine->timeline); |
5013eb8c | 625 | rq->hwsp_seqno = rq->timeline->hwsp_seqno; |
73cb9701 | 626 | |
e61e0f51 CW |
627 | spin_lock_init(&rq->lock); |
628 | dma_fence_init(&rq->fence, | |
f54d1867 | 629 | &i915_fence_ops, |
e61e0f51 CW |
630 | &rq->lock, |
631 | rq->timeline->fence_context, | |
632 | timeline_get_seqno(rq->timeline)); | |
04769652 | 633 | |
48bc2a4a | 634 | /* We bump the ref for the fence chain */ |
e61e0f51 CW |
635 | i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify); |
636 | init_waitqueue_head(&rq->execute); | |
5590af3e | 637 | |
0c7112a0 | 638 | i915_sched_node_init(&rq->sched); |
52e54209 | 639 | |
5a198b8c | 640 | /* No zalloc, must clear what we need by hand */ |
e61e0f51 CW |
641 | rq->global_seqno = 0; |
642 | rq->signaling.wait.seqno = 0; | |
643 | rq->file_priv = NULL; | |
644 | rq->batch = NULL; | |
645 | rq->capture_list = NULL; | |
646 | rq->waitboost = false; | |
5a198b8c | 647 | |
05235c53 CW |
648 | /* |
649 | * Reserve space in the ring buffer for all the commands required to | |
650 | * eventually emit this request. This is to guarantee that the | |
e61e0f51 | 651 | * i915_request_add() call can't fail. Note that the reserve may need |
05235c53 CW |
652 | * to be redone if the request is not actually submitted straight |
653 | * away, e.g. because a GPU scheduler has deferred it. | |
ed2922c0 CW |
654 | * |
655 | * Note that due to how we add reserved_space to intel_ring_begin() | |
656 | * we need to double our request to ensure that if we need to wrap | |
657 | * around inside i915_request_add() there is sufficient space at | |
658 | * the beginning of the ring as well. | |
05235c53 | 659 | */ |
85474441 | 660 | rq->reserved_space = 2 * engine->emit_fini_breadcrumb_dw * sizeof(u32); |
05235c53 | 661 | |
2113184c CW |
662 | /* |
663 | * Record the position of the start of the request so that | |
d045446d CW |
664 | * should we detect the updated seqno part-way through the |
665 | * GPU processing the request, we never over-estimate the | |
666 | * position of the head. | |
667 | */ | |
e61e0f51 | 668 | rq->head = rq->ring->emit; |
d045446d | 669 | |
e61e0f51 | 670 | ret = engine->request_alloc(rq); |
b1c24a61 CW |
671 | if (ret) |
672 | goto err_unwind; | |
2113184c | 673 | |
b887d615 | 674 | /* Keep a second pin for the dual retirement along engine and ring */ |
1fc44d9b | 675 | __intel_context_pin(ce); |
b887d615 | 676 | |
b3ee09a4 CW |
677 | rq->infix = rq->ring->emit; /* end of header; start of user payload */ |
678 | ||
9b6586ae | 679 | /* Check that we didn't interrupt ourselves with a new request */ |
e61e0f51 CW |
680 | GEM_BUG_ON(rq->timeline->seqno != rq->fence.seqno); |
681 | return rq; | |
05235c53 | 682 | |
b1c24a61 | 683 | err_unwind: |
1fc44d9b | 684 | ce->ring->emit = rq->head; |
b1c24a61 | 685 | |
1618bdb8 | 686 | /* Make sure we didn't add ourselves to external state before freeing */ |
e61e0f51 | 687 | GEM_BUG_ON(!list_empty(&rq->active_list)); |
0c7112a0 CW |
688 | GEM_BUG_ON(!list_empty(&rq->sched.signalers_list)); |
689 | GEM_BUG_ON(!list_empty(&rq->sched.waiters_list)); | |
1618bdb8 | 690 | |
e61e0f51 | 691 | kmem_cache_free(i915->requests, rq); |
28176ef4 | 692 | err_unreserve: |
52d7f16e | 693 | unreserve_gt(i915); |
1fc44d9b | 694 | intel_context_unpin(ce); |
8e637178 | 695 | return ERR_PTR(ret); |
05235c53 CW |
696 | } |
697 | ||
a2bc4695 | 698 | static int |
e61e0f51 | 699 | i915_request_await_request(struct i915_request *to, struct i915_request *from) |
a2bc4695 | 700 | { |
85e17f59 | 701 | int ret; |
a2bc4695 CW |
702 | |
703 | GEM_BUG_ON(to == from); | |
ceae14bd | 704 | GEM_BUG_ON(to->timeline == from->timeline); |
a2bc4695 | 705 | |
e61e0f51 | 706 | if (i915_request_completed(from)) |
ade0b0c9 CW |
707 | return 0; |
708 | ||
52e54209 | 709 | if (to->engine->schedule) { |
0c7112a0 CW |
710 | ret = i915_sched_node_add_dependency(to->i915, |
711 | &to->sched, | |
712 | &from->sched); | |
52e54209 CW |
713 | if (ret < 0) |
714 | return ret; | |
715 | } | |
716 | ||
73cb9701 CW |
717 | if (to->engine == from->engine) { |
718 | ret = i915_sw_fence_await_sw_fence_gfp(&to->submit, | |
719 | &from->submit, | |
2abe2f84 | 720 | I915_FENCE_GFP); |
6faf5916 CW |
721 | } else { |
722 | ret = i915_sw_fence_await_dma_fence(&to->submit, | |
723 | &from->fence, 0, | |
724 | I915_FENCE_GFP); | |
a2bc4695 CW |
725 | } |
726 | ||
fc9d4d2b | 727 | return ret < 0 ? ret : 0; |
a2bc4695 CW |
728 | } |
729 | ||
b52992c0 | 730 | int |
e61e0f51 | 731 | i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) |
b52992c0 | 732 | { |
29ef3fa9 CW |
733 | struct dma_fence **child = &fence; |
734 | unsigned int nchild = 1; | |
b52992c0 | 735 | int ret; |
b52992c0 | 736 | |
e61e0f51 CW |
737 | /* |
738 | * Note that if the fence-array was created in signal-on-any mode, | |
b52992c0 CW |
739 | * we should *not* decompose it into its individual fences. However, |
740 | * we don't currently store which mode the fence-array is operating | |
741 | * in. Fortunately, the only user of signal-on-any is private to | |
742 | * amdgpu and we should not see any incoming fence-array from | |
743 | * sync-file being in signal-on-any mode. | |
744 | */ | |
29ef3fa9 CW |
745 | if (dma_fence_is_array(fence)) { |
746 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
747 | ||
748 | child = array->fences; | |
749 | nchild = array->num_fences; | |
750 | GEM_BUG_ON(!nchild); | |
751 | } | |
b52992c0 | 752 | |
29ef3fa9 CW |
753 | do { |
754 | fence = *child++; | |
755 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
756 | continue; | |
b52992c0 | 757 | |
ceae14bd CW |
758 | /* |
759 | * Requests on the same timeline are explicitly ordered, along | |
e61e0f51 | 760 | * with their dependencies, by i915_request_add() which ensures |
ceae14bd CW |
761 | * that requests are submitted in-order through each ring. |
762 | */ | |
e61e0f51 | 763 | if (fence->context == rq->fence.context) |
ceae14bd CW |
764 | continue; |
765 | ||
47979480 | 766 | /* Squash repeated waits to the same timelines */ |
e61e0f51 | 767 | if (fence->context != rq->i915->mm.unordered_timeline && |
a89d1f92 | 768 | i915_timeline_sync_is_later(rq->timeline, fence)) |
47979480 CW |
769 | continue; |
770 | ||
29ef3fa9 | 771 | if (dma_fence_is_i915(fence)) |
e61e0f51 | 772 | ret = i915_request_await_request(rq, to_request(fence)); |
b52992c0 | 773 | else |
e61e0f51 | 774 | ret = i915_sw_fence_await_dma_fence(&rq->submit, fence, |
29ef3fa9 | 775 | I915_FENCE_TIMEOUT, |
2abe2f84 | 776 | I915_FENCE_GFP); |
b52992c0 CW |
777 | if (ret < 0) |
778 | return ret; | |
47979480 CW |
779 | |
780 | /* Record the latest fence used against each timeline */ | |
e61e0f51 | 781 | if (fence->context != rq->i915->mm.unordered_timeline) |
a89d1f92 | 782 | i915_timeline_sync_set(rq->timeline, fence); |
29ef3fa9 | 783 | } while (--nchild); |
b52992c0 CW |
784 | |
785 | return 0; | |
786 | } | |
787 | ||
a2bc4695 | 788 | /** |
e61e0f51 | 789 | * i915_request_await_object - set this request to (async) wait upon a bo |
a2bc4695 CW |
790 | * @to: request we are wishing to use |
791 | * @obj: object which may be in use on another ring. | |
d8802126 | 792 | * @write: whether the wait is on behalf of a writer |
a2bc4695 CW |
793 | * |
794 | * This code is meant to abstract object synchronization with the GPU. | |
795 | * Conceptually we serialise writes between engines inside the GPU. | |
796 | * We only allow one engine to write into a buffer at any time, but | |
797 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
798 | * | |
799 | * - If there is an outstanding write request to the object, the new | |
800 | * request must wait for it to complete (either CPU or in hw, requests | |
801 | * on the same ring will be naturally ordered). | |
802 | * | |
803 | * - If we are a write request (pending_write_domain is set), the new | |
804 | * request must wait for outstanding read requests to complete. | |
805 | * | |
806 | * Returns 0 if successful, else propagates up the lower layer error. | |
807 | */ | |
808 | int | |
e61e0f51 CW |
809 | i915_request_await_object(struct i915_request *to, |
810 | struct drm_i915_gem_object *obj, | |
811 | bool write) | |
a2bc4695 | 812 | { |
d07f0e59 CW |
813 | struct dma_fence *excl; |
814 | int ret = 0; | |
a2bc4695 CW |
815 | |
816 | if (write) { | |
d07f0e59 CW |
817 | struct dma_fence **shared; |
818 | unsigned int count, i; | |
819 | ||
820 | ret = reservation_object_get_fences_rcu(obj->resv, | |
821 | &excl, &count, &shared); | |
822 | if (ret) | |
823 | return ret; | |
824 | ||
825 | for (i = 0; i < count; i++) { | |
e61e0f51 | 826 | ret = i915_request_await_dma_fence(to, shared[i]); |
d07f0e59 CW |
827 | if (ret) |
828 | break; | |
829 | ||
830 | dma_fence_put(shared[i]); | |
831 | } | |
832 | ||
833 | for (; i < count; i++) | |
834 | dma_fence_put(shared[i]); | |
835 | kfree(shared); | |
a2bc4695 | 836 | } else { |
d07f0e59 | 837 | excl = reservation_object_get_excl_rcu(obj->resv); |
a2bc4695 CW |
838 | } |
839 | ||
d07f0e59 CW |
840 | if (excl) { |
841 | if (ret == 0) | |
e61e0f51 | 842 | ret = i915_request_await_dma_fence(to, excl); |
a2bc4695 | 843 | |
d07f0e59 | 844 | dma_fence_put(excl); |
a2bc4695 CW |
845 | } |
846 | ||
d07f0e59 | 847 | return ret; |
a2bc4695 CW |
848 | } |
849 | ||
6dd7526f CW |
850 | void i915_request_skip(struct i915_request *rq, int error) |
851 | { | |
852 | void *vaddr = rq->ring->vaddr; | |
853 | u32 head; | |
854 | ||
855 | GEM_BUG_ON(!IS_ERR_VALUE((long)error)); | |
856 | dma_fence_set_error(&rq->fence, error); | |
857 | ||
858 | /* | |
859 | * As this request likely depends on state from the lost | |
860 | * context, clear out all the user operations leaving the | |
861 | * breadcrumb at the end (so we get the fence notifications). | |
862 | */ | |
863 | head = rq->infix; | |
864 | if (rq->postfix < head) { | |
865 | memset(vaddr + head, 0, rq->ring->size - head); | |
866 | head = 0; | |
867 | } | |
868 | memset(vaddr + head, 0, rq->postfix - head); | |
869 | } | |
870 | ||
05235c53 CW |
871 | /* |
872 | * NB: This function is not allowed to fail. Doing so would mean the the | |
873 | * request is not being tracked for completion but the work itself is | |
874 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
875 | */ | |
697b9a87 | 876 | void i915_request_add(struct i915_request *request) |
05235c53 | 877 | { |
95b2ab56 | 878 | struct intel_engine_cs *engine = request->engine; |
a89d1f92 | 879 | struct i915_timeline *timeline = request->timeline; |
1fc44d9b | 880 | struct intel_ring *ring = request->ring; |
e61e0f51 | 881 | struct i915_request *prev; |
73dec95e | 882 | u32 *cs; |
05235c53 | 883 | |
dd847a70 | 884 | GEM_TRACE("%s fence %llx:%lld\n", |
d9b13c4d CW |
885 | engine->name, request->fence.context, request->fence.seqno); |
886 | ||
4c7d62c6 | 887 | lockdep_assert_held(&request->i915->drm.struct_mutex); |
e61e0f51 | 888 | trace_i915_request_add(request); |
0f25dff6 | 889 | |
8ac71d1d CW |
890 | /* |
891 | * Make sure that no request gazumped us - if it was allocated after | |
e61e0f51 | 892 | * our i915_request_alloc() and called __i915_request_add() before |
c781c978 CW |
893 | * us, the timeline will hold its seqno which is later than ours. |
894 | */ | |
9b6586ae | 895 | GEM_BUG_ON(timeline->seqno != request->fence.seqno); |
c781c978 | 896 | |
05235c53 CW |
897 | /* |
898 | * To ensure that this call will not fail, space for its emissions | |
899 | * should already have been reserved in the ring buffer. Let the ring | |
900 | * know that it is time to use that space up. | |
901 | */ | |
ed2922c0 | 902 | GEM_BUG_ON(request->reserved_space > request->ring->space); |
05235c53 | 903 | request->reserved_space = 0; |
05235c53 | 904 | |
8ac71d1d CW |
905 | /* |
906 | * Record the position of the start of the breadcrumb so that | |
05235c53 CW |
907 | * should we detect the updated seqno part-way through the |
908 | * GPU processing the request, we never over-estimate the | |
d045446d | 909 | * position of the ring's HEAD. |
05235c53 | 910 | */ |
85474441 | 911 | cs = intel_ring_begin(request, engine->emit_fini_breadcrumb_dw); |
73dec95e TU |
912 | GEM_BUG_ON(IS_ERR(cs)); |
913 | request->postfix = intel_ring_offset(request, cs); | |
05235c53 | 914 | |
8ac71d1d CW |
915 | /* |
916 | * Seal the request and mark it as pending execution. Note that | |
0f25dff6 CW |
917 | * we may inspect this state, without holding any locks, during |
918 | * hangcheck. Hence we apply the barrier to ensure that we do not | |
919 | * see a more recent value in the hws than we are tracking. | |
920 | */ | |
0a046a0e | 921 | |
73cb9701 | 922 | prev = i915_gem_active_raw(&timeline->last_request, |
0a046a0e | 923 | &request->i915->drm.struct_mutex); |
e61e0f51 | 924 | if (prev && !i915_request_completed(prev)) { |
0a046a0e CW |
925 | i915_sw_fence_await_sw_fence(&request->submit, &prev->submit, |
926 | &request->submitq); | |
52e54209 | 927 | if (engine->schedule) |
0c7112a0 CW |
928 | __i915_sched_node_add_dependency(&request->sched, |
929 | &prev->sched, | |
930 | &request->dep, | |
931 | 0); | |
52e54209 | 932 | } |
0a046a0e | 933 | |
80b204bc | 934 | spin_lock_irq(&timeline->lock); |
f2d13290 | 935 | list_add_tail(&request->link, &timeline->requests); |
80b204bc CW |
936 | spin_unlock_irq(&timeline->lock); |
937 | ||
9b6586ae | 938 | GEM_BUG_ON(timeline->seqno != request->fence.seqno); |
73cb9701 | 939 | i915_gem_active_set(&timeline->last_request, request); |
f2d13290 | 940 | |
0f25dff6 | 941 | list_add_tail(&request->ring_link, &ring->request_list); |
09a4c02e CW |
942 | if (list_is_first(&request->ring_link, &ring->request_list)) { |
943 | GEM_TRACE("marking %s as active\n", ring->timeline->name); | |
643b450a | 944 | list_add(&ring->active_link, &request->i915->gt.active_rings); |
09a4c02e | 945 | } |
f2d13290 | 946 | request->emitted_jiffies = jiffies; |
0f25dff6 | 947 | |
8ac71d1d CW |
948 | /* |
949 | * Let the backend know a new request has arrived that may need | |
0de9136d CW |
950 | * to adjust the existing execution schedule due to a high priority |
951 | * request - i.e. we may want to preempt the current request in order | |
952 | * to run a high priority dependency chain *before* we can execute this | |
953 | * request. | |
954 | * | |
955 | * This is called before the request is ready to run so that we can | |
956 | * decide whether to preempt the entire chain so that it is ready to | |
957 | * run at the earliest possible convenience. | |
958 | */ | |
71ace7ca CW |
959 | local_bh_disable(); |
960 | rcu_read_lock(); /* RCU serialisation for set-wedged protection */ | |
b16c7651 CW |
961 | if (engine->schedule) { |
962 | struct i915_sched_attr attr = request->gem_context->sched; | |
963 | ||
964 | /* | |
965 | * Boost priorities to new clients (new request flows). | |
966 | * | |
967 | * Allow interactive/synchronous clients to jump ahead of | |
968 | * the bulk clients. (FQ_CODEL) | |
969 | */ | |
970 | if (!prev || i915_request_completed(prev)) | |
971 | attr.priority |= I915_PRIORITY_NEWCLIENT; | |
972 | ||
973 | engine->schedule(request, &attr); | |
974 | } | |
47650db0 | 975 | rcu_read_unlock(); |
5590af3e CW |
976 | i915_sw_fence_commit(&request->submit); |
977 | local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ | |
c22b355f CW |
978 | |
979 | /* | |
980 | * In typical scenarios, we do not expect the previous request on | |
981 | * the timeline to be still tracked by timeline->last_request if it | |
982 | * has been completed. If the completed request is still here, that | |
983 | * implies that request retirement is a long way behind submission, | |
984 | * suggesting that we haven't been retiring frequently enough from | |
985 | * the combination of retire-before-alloc, waiters and the background | |
986 | * retirement worker. So if the last request on this timeline was | |
987 | * already completed, do a catch up pass, flushing the retirement queue | |
988 | * up to this client. Since we have now moved the heaviest operations | |
989 | * during retirement onto secondary workers, such as freeing objects | |
990 | * or contexts, retiring a bunch of requests is mostly list management | |
991 | * (and cache misses), and so we should not be overly penalizing this | |
992 | * client by performing excess work, though we may still performing | |
993 | * work on behalf of others -- but instead we should benefit from | |
994 | * improved resource management. (Well, that's the theory at least.) | |
995 | */ | |
e61e0f51 CW |
996 | if (prev && i915_request_completed(prev)) |
997 | i915_request_retire_upto(prev); | |
05235c53 CW |
998 | } |
999 | ||
1000 | static unsigned long local_clock_us(unsigned int *cpu) | |
1001 | { | |
1002 | unsigned long t; | |
1003 | ||
e61e0f51 CW |
1004 | /* |
1005 | * Cheaply and approximately convert from nanoseconds to microseconds. | |
05235c53 CW |
1006 | * The result and subsequent calculations are also defined in the same |
1007 | * approximate microseconds units. The principal source of timing | |
1008 | * error here is from the simple truncation. | |
1009 | * | |
1010 | * Note that local_clock() is only defined wrt to the current CPU; | |
1011 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1012 | * blocking preemption for the entire busywait, we can detect the CPU | |
1013 | * switch and use that as indicator of system load and a reason to | |
1014 | * stop busywaiting, see busywait_stop(). | |
1015 | */ | |
1016 | *cpu = get_cpu(); | |
1017 | t = local_clock() >> 10; | |
1018 | put_cpu(); | |
1019 | ||
1020 | return t; | |
1021 | } | |
1022 | ||
1023 | static bool busywait_stop(unsigned long timeout, unsigned int cpu) | |
1024 | { | |
1025 | unsigned int this_cpu; | |
1026 | ||
1027 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
1028 | return true; | |
1029 | ||
1030 | return this_cpu != cpu; | |
1031 | } | |
1032 | ||
e61e0f51 | 1033 | static bool __i915_spin_request(const struct i915_request *rq, |
b2f2f0fc | 1034 | u32 seqno, int state, unsigned long timeout_us) |
05235c53 | 1035 | { |
e61e0f51 | 1036 | struct intel_engine_cs *engine = rq->engine; |
c33ed067 | 1037 | unsigned int irq, cpu; |
05235c53 | 1038 | |
b2f2f0fc CW |
1039 | GEM_BUG_ON(!seqno); |
1040 | ||
1041 | /* | |
1042 | * Only wait for the request if we know it is likely to complete. | |
1043 | * | |
1044 | * We don't track the timestamps around requests, nor the average | |
1045 | * request length, so we do not have a good indicator that this | |
1046 | * request will complete within the timeout. What we do know is the | |
1047 | * order in which requests are executed by the engine and so we can | |
1048 | * tell if the request has started. If the request hasn't started yet, | |
1049 | * it is a fair assumption that it will not complete within our | |
1050 | * relatively short timeout. | |
1051 | */ | |
97f06158 | 1052 | if (!intel_engine_has_started(engine, seqno)) |
b2f2f0fc CW |
1053 | return false; |
1054 | ||
e61e0f51 CW |
1055 | /* |
1056 | * When waiting for high frequency requests, e.g. during synchronous | |
05235c53 CW |
1057 | * rendering split between the CPU and GPU, the finite amount of time |
1058 | * required to set up the irq and wait upon it limits the response | |
1059 | * rate. By busywaiting on the request completion for a short while we | |
1060 | * can service the high frequency waits as quick as possible. However, | |
1061 | * if it is a slow request, we want to sleep as quickly as possible. | |
1062 | * The tradeoff between waiting and sleeping is roughly the time it | |
1063 | * takes to sleep on a request, on the order of a microsecond. | |
1064 | */ | |
1065 | ||
78796877 | 1066 | irq = READ_ONCE(engine->breadcrumbs.irq_count); |
05235c53 CW |
1067 | timeout_us += local_clock_us(&cpu); |
1068 | do { | |
97f06158 | 1069 | if (intel_engine_has_completed(engine, seqno)) |
e61e0f51 | 1070 | return seqno == i915_request_global_seqno(rq); |
05235c53 | 1071 | |
e61e0f51 CW |
1072 | /* |
1073 | * Seqno are meant to be ordered *before* the interrupt. If | |
c33ed067 CW |
1074 | * we see an interrupt without a corresponding seqno advance, |
1075 | * assume we won't see one in the near future but require | |
1076 | * the engine->seqno_barrier() to fixup coherency. | |
1077 | */ | |
78796877 | 1078 | if (READ_ONCE(engine->breadcrumbs.irq_count) != irq) |
c33ed067 CW |
1079 | break; |
1080 | ||
05235c53 CW |
1081 | if (signal_pending_state(state, current)) |
1082 | break; | |
1083 | ||
1084 | if (busywait_stop(timeout_us, cpu)) | |
1085 | break; | |
1086 | ||
f2f09a4c | 1087 | cpu_relax(); |
05235c53 CW |
1088 | } while (!need_resched()); |
1089 | ||
1090 | return false; | |
1091 | } | |
1092 | ||
1093 | /** | |
e532be89 | 1094 | * i915_request_wait - wait until execution of request has finished |
e61e0f51 | 1095 | * @rq: the request to wait upon |
ea746f36 | 1096 | * @flags: how to wait |
e95433c7 CW |
1097 | * @timeout: how long to wait in jiffies |
1098 | * | |
e532be89 | 1099 | * i915_request_wait() waits for the request to be completed, for a |
e95433c7 CW |
1100 | * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an |
1101 | * unbounded wait). | |
05235c53 | 1102 | * |
e95433c7 CW |
1103 | * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED |
1104 | * in via the flags, and vice versa if the struct_mutex is not held, the caller | |
1105 | * must not specify that the wait is locked. | |
05235c53 | 1106 | * |
e95433c7 CW |
1107 | * Returns the remaining time (in jiffies) if the request completed, which may |
1108 | * be zero or -ETIME if the request is unfinished after the timeout expires. | |
1109 | * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is | |
1110 | * pending before the request completes. | |
05235c53 | 1111 | */ |
e61e0f51 | 1112 | long i915_request_wait(struct i915_request *rq, |
e95433c7 CW |
1113 | unsigned int flags, |
1114 | long timeout) | |
05235c53 | 1115 | { |
ea746f36 CW |
1116 | const int state = flags & I915_WAIT_INTERRUPTIBLE ? |
1117 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
a49625f9 | 1118 | DEFINE_WAIT_FUNC(exec, default_wake_function); |
05235c53 | 1119 | struct intel_wait wait; |
05235c53 CW |
1120 | |
1121 | might_sleep(); | |
e95433c7 | 1122 | GEM_BUG_ON(timeout < 0); |
05235c53 | 1123 | |
e61e0f51 | 1124 | if (i915_request_completed(rq)) |
e95433c7 | 1125 | return timeout; |
05235c53 | 1126 | |
e95433c7 CW |
1127 | if (!timeout) |
1128 | return -ETIME; | |
05235c53 | 1129 | |
e61e0f51 | 1130 | trace_i915_request_wait_begin(rq, flags); |
e61e0f51 | 1131 | add_wait_queue(&rq->execute, &exec); |
e3be4079 | 1132 | intel_wait_init(&wait); |
e9eaf82d CW |
1133 | if (flags & I915_WAIT_PRIORITY) |
1134 | i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT); | |
754c9fd5 | 1135 | |
d6a2289d | 1136 | restart: |
0f2f61d4 CW |
1137 | do { |
1138 | set_current_state(state); | |
e61e0f51 | 1139 | if (intel_wait_update_request(&wait, rq)) |
0f2f61d4 | 1140 | break; |
541ca6ed | 1141 | |
0f2f61d4 CW |
1142 | if (signal_pending_state(state, current)) { |
1143 | timeout = -ERESTARTSYS; | |
4680816b | 1144 | goto complete; |
0f2f61d4 | 1145 | } |
4680816b | 1146 | |
0f2f61d4 CW |
1147 | if (!timeout) { |
1148 | timeout = -ETIME; | |
1149 | goto complete; | |
1150 | } | |
541ca6ed | 1151 | |
0f2f61d4 CW |
1152 | timeout = io_schedule_timeout(timeout); |
1153 | } while (1); | |
4680816b | 1154 | |
0f2f61d4 | 1155 | GEM_BUG_ON(!intel_wait_has_seqno(&wait)); |
e61e0f51 | 1156 | GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); |
4680816b | 1157 | |
437c3087 | 1158 | /* Optimistic short spin before touching IRQs */ |
e61e0f51 | 1159 | if (__i915_spin_request(rq, wait.seqno, state, 5)) |
05235c53 CW |
1160 | goto complete; |
1161 | ||
1162 | set_current_state(state); | |
e61e0f51 CW |
1163 | if (intel_engine_add_wait(rq->engine, &wait)) |
1164 | /* | |
1165 | * In order to check that we haven't missed the interrupt | |
05235c53 CW |
1166 | * as we enabled it, we need to kick ourselves to do a |
1167 | * coherent check on the seqno before we sleep. | |
1168 | */ | |
1169 | goto wakeup; | |
1170 | ||
1171 | for (;;) { | |
1172 | if (signal_pending_state(state, current)) { | |
e95433c7 | 1173 | timeout = -ERESTARTSYS; |
05235c53 CW |
1174 | break; |
1175 | } | |
1176 | ||
e95433c7 CW |
1177 | if (!timeout) { |
1178 | timeout = -ETIME; | |
05235c53 CW |
1179 | break; |
1180 | } | |
1181 | ||
e95433c7 CW |
1182 | timeout = io_schedule_timeout(timeout); |
1183 | ||
754c9fd5 | 1184 | if (intel_wait_complete(&wait) && |
e61e0f51 | 1185 | intel_wait_check_request(&wait, rq)) |
05235c53 CW |
1186 | break; |
1187 | ||
1188 | set_current_state(state); | |
1189 | ||
1190 | wakeup: | |
1216e3c3 | 1191 | if (i915_request_completed(rq)) |
05235c53 CW |
1192 | break; |
1193 | ||
1194 | /* Only spin if we know the GPU is processing this request */ | |
e61e0f51 | 1195 | if (__i915_spin_request(rq, wait.seqno, state, 2)) |
05235c53 | 1196 | break; |
d6a2289d | 1197 | |
e61e0f51 CW |
1198 | if (!intel_wait_check_request(&wait, rq)) { |
1199 | intel_engine_remove_wait(rq->engine, &wait); | |
d6a2289d CW |
1200 | goto restart; |
1201 | } | |
05235c53 | 1202 | } |
05235c53 | 1203 | |
e61e0f51 | 1204 | intel_engine_remove_wait(rq->engine, &wait); |
05235c53 | 1205 | complete: |
a49625f9 | 1206 | __set_current_state(TASK_RUNNING); |
e61e0f51 CW |
1207 | remove_wait_queue(&rq->execute, &exec); |
1208 | trace_i915_request_wait_end(rq); | |
05235c53 | 1209 | |
e95433c7 | 1210 | return timeout; |
05235c53 | 1211 | } |
4b8de8e6 | 1212 | |
e61e0f51 | 1213 | void i915_retire_requests(struct drm_i915_private *i915) |
4b8de8e6 | 1214 | { |
643b450a | 1215 | struct intel_ring *ring, *tmp; |
4b8de8e6 | 1216 | |
e61e0f51 | 1217 | lockdep_assert_held(&i915->drm.struct_mutex); |
4b8de8e6 | 1218 | |
e61e0f51 | 1219 | if (!i915->gt.active_requests) |
4b8de8e6 CW |
1220 | return; |
1221 | ||
643b450a | 1222 | list_for_each_entry_safe(ring, tmp, &i915->gt.active_rings, active_link) |
b887d615 | 1223 | ring_retire_requests(ring); |
4b8de8e6 | 1224 | } |
c835c550 CW |
1225 | |
1226 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
1227 | #include "selftests/mock_request.c" | |
e61e0f51 | 1228 | #include "selftests/i915_request.c" |
c835c550 | 1229 | #endif |