Commit | Line | Data |
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05235c53 CW |
1 | /* |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
fa545cbf | 25 | #include <linux/prefetch.h> |
b52992c0 | 26 | #include <linux/dma-fence-array.h> |
e6017571 IM |
27 | #include <linux/sched.h> |
28 | #include <linux/sched/clock.h> | |
f361bf4a | 29 | #include <linux/sched/signal.h> |
fa545cbf | 30 | |
05235c53 CW |
31 | #include "i915_drv.h" |
32 | ||
f54d1867 | 33 | static const char *i915_fence_get_driver_name(struct dma_fence *fence) |
04769652 CW |
34 | { |
35 | return "i915"; | |
36 | } | |
37 | ||
f54d1867 | 38 | static const char *i915_fence_get_timeline_name(struct dma_fence *fence) |
04769652 | 39 | { |
e61e0f51 CW |
40 | /* |
41 | * The timeline struct (as part of the ppgtt underneath a context) | |
05506b5b CW |
42 | * may be freed when the request is no longer in use by the GPU. |
43 | * We could extend the life of a context to beyond that of all | |
44 | * fences, possibly keeping the hw resource around indefinitely, | |
45 | * or we just give them a false name. Since | |
46 | * dma_fence_ops.get_timeline_name is a debug feature, the occasional | |
47 | * lie seems justifiable. | |
48 | */ | |
49 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
50 | return "signaled"; | |
51 | ||
a89d1f92 | 52 | return to_request(fence)->timeline->name; |
04769652 CW |
53 | } |
54 | ||
f54d1867 | 55 | static bool i915_fence_signaled(struct dma_fence *fence) |
04769652 | 56 | { |
e61e0f51 | 57 | return i915_request_completed(to_request(fence)); |
04769652 CW |
58 | } |
59 | ||
f54d1867 | 60 | static bool i915_fence_enable_signaling(struct dma_fence *fence) |
04769652 | 61 | { |
6f9ec414 | 62 | return intel_engine_enable_signaling(to_request(fence), true); |
04769652 CW |
63 | } |
64 | ||
f54d1867 | 65 | static signed long i915_fence_wait(struct dma_fence *fence, |
04769652 | 66 | bool interruptible, |
e95433c7 | 67 | signed long timeout) |
04769652 | 68 | { |
e61e0f51 | 69 | return i915_request_wait(to_request(fence), interruptible, timeout); |
04769652 CW |
70 | } |
71 | ||
f54d1867 | 72 | static void i915_fence_release(struct dma_fence *fence) |
04769652 | 73 | { |
e61e0f51 | 74 | struct i915_request *rq = to_request(fence); |
04769652 | 75 | |
e61e0f51 CW |
76 | /* |
77 | * The request is put onto a RCU freelist (i.e. the address | |
fc158405 CW |
78 | * is immediately reused), mark the fences as being freed now. |
79 | * Otherwise the debugobjects for the fences are only marked as | |
80 | * freed when the slab cache itself is freed, and so we would get | |
81 | * caught trying to reuse dead objects. | |
82 | */ | |
e61e0f51 | 83 | i915_sw_fence_fini(&rq->submit); |
fc158405 | 84 | |
e61e0f51 | 85 | kmem_cache_free(rq->i915->requests, rq); |
04769652 CW |
86 | } |
87 | ||
f54d1867 | 88 | const struct dma_fence_ops i915_fence_ops = { |
04769652 CW |
89 | .get_driver_name = i915_fence_get_driver_name, |
90 | .get_timeline_name = i915_fence_get_timeline_name, | |
91 | .enable_signaling = i915_fence_enable_signaling, | |
92 | .signaled = i915_fence_signaled, | |
93 | .wait = i915_fence_wait, | |
94 | .release = i915_fence_release, | |
04769652 CW |
95 | }; |
96 | ||
05235c53 | 97 | static inline void |
e61e0f51 | 98 | i915_request_remove_from_client(struct i915_request *request) |
05235c53 | 99 | { |
c8659efa | 100 | struct drm_i915_file_private *file_priv; |
05235c53 | 101 | |
c8659efa | 102 | file_priv = request->file_priv; |
05235c53 CW |
103 | if (!file_priv) |
104 | return; | |
105 | ||
106 | spin_lock(&file_priv->mm.lock); | |
c8659efa CW |
107 | if (request->file_priv) { |
108 | list_del(&request->client_link); | |
109 | request->file_priv = NULL; | |
110 | } | |
05235c53 | 111 | spin_unlock(&file_priv->mm.lock); |
05235c53 CW |
112 | } |
113 | ||
52e54209 CW |
114 | static struct i915_dependency * |
115 | i915_dependency_alloc(struct drm_i915_private *i915) | |
116 | { | |
117 | return kmem_cache_alloc(i915->dependencies, GFP_KERNEL); | |
118 | } | |
119 | ||
120 | static void | |
121 | i915_dependency_free(struct drm_i915_private *i915, | |
122 | struct i915_dependency *dep) | |
123 | { | |
124 | kmem_cache_free(i915->dependencies, dep); | |
125 | } | |
126 | ||
127 | static void | |
0c7112a0 CW |
128 | __i915_sched_node_add_dependency(struct i915_sched_node *node, |
129 | struct i915_sched_node *signal, | |
130 | struct i915_dependency *dep, | |
131 | unsigned long flags) | |
52e54209 | 132 | { |
20311bd3 | 133 | INIT_LIST_HEAD(&dep->dfs_link); |
52e54209 | 134 | list_add(&dep->wait_link, &signal->waiters_list); |
0c7112a0 | 135 | list_add(&dep->signal_link, &node->signalers_list); |
52e54209 CW |
136 | dep->signaler = signal; |
137 | dep->flags = flags; | |
138 | } | |
139 | ||
140 | static int | |
0c7112a0 CW |
141 | i915_sched_node_add_dependency(struct drm_i915_private *i915, |
142 | struct i915_sched_node *node, | |
143 | struct i915_sched_node *signal) | |
52e54209 CW |
144 | { |
145 | struct i915_dependency *dep; | |
146 | ||
147 | dep = i915_dependency_alloc(i915); | |
148 | if (!dep) | |
149 | return -ENOMEM; | |
150 | ||
0c7112a0 CW |
151 | __i915_sched_node_add_dependency(node, signal, dep, |
152 | I915_DEPENDENCY_ALLOC); | |
52e54209 CW |
153 | return 0; |
154 | } | |
155 | ||
156 | static void | |
0c7112a0 CW |
157 | i915_sched_node_fini(struct drm_i915_private *i915, |
158 | struct i915_sched_node *node) | |
52e54209 | 159 | { |
0c7112a0 | 160 | struct i915_dependency *dep, *tmp; |
52e54209 | 161 | |
0c7112a0 | 162 | GEM_BUG_ON(!list_empty(&node->link)); |
20311bd3 | 163 | |
83cc84c5 CW |
164 | /* |
165 | * Everyone we depended upon (the fences we wait to be signaled) | |
52e54209 CW |
166 | * should retire before us and remove themselves from our list. |
167 | * However, retirement is run independently on each timeline and | |
168 | * so we may be called out-of-order. | |
169 | */ | |
0c7112a0 CW |
170 | list_for_each_entry_safe(dep, tmp, &node->signalers_list, signal_link) { |
171 | GEM_BUG_ON(!i915_sched_node_signaled(dep->signaler)); | |
83cc84c5 CW |
172 | GEM_BUG_ON(!list_empty(&dep->dfs_link)); |
173 | ||
52e54209 CW |
174 | list_del(&dep->wait_link); |
175 | if (dep->flags & I915_DEPENDENCY_ALLOC) | |
176 | i915_dependency_free(i915, dep); | |
177 | } | |
178 | ||
179 | /* Remove ourselves from everyone who depends upon us */ | |
0c7112a0 CW |
180 | list_for_each_entry_safe(dep, tmp, &node->waiters_list, wait_link) { |
181 | GEM_BUG_ON(dep->signaler != node); | |
83cc84c5 CW |
182 | GEM_BUG_ON(!list_empty(&dep->dfs_link)); |
183 | ||
52e54209 CW |
184 | list_del(&dep->signal_link); |
185 | if (dep->flags & I915_DEPENDENCY_ALLOC) | |
186 | i915_dependency_free(i915, dep); | |
187 | } | |
188 | } | |
189 | ||
190 | static void | |
0c7112a0 | 191 | i915_sched_node_init(struct i915_sched_node *node) |
52e54209 | 192 | { |
0c7112a0 CW |
193 | INIT_LIST_HEAD(&node->signalers_list); |
194 | INIT_LIST_HEAD(&node->waiters_list); | |
195 | INIT_LIST_HEAD(&node->link); | |
b7268c5e | 196 | node->attr.priority = I915_PRIORITY_INVALID; |
52e54209 CW |
197 | } |
198 | ||
12d3173b CW |
199 | static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno) |
200 | { | |
12d3173b | 201 | struct intel_engine_cs *engine; |
a89d1f92 | 202 | struct i915_timeline *timeline; |
12d3173b CW |
203 | enum intel_engine_id id; |
204 | int ret; | |
205 | ||
206 | /* Carefully retire all requests without writing to the rings */ | |
207 | ret = i915_gem_wait_for_idle(i915, | |
208 | I915_WAIT_INTERRUPTIBLE | | |
209 | I915_WAIT_LOCKED); | |
210 | if (ret) | |
211 | return ret; | |
212 | ||
d9b13c4d CW |
213 | GEM_BUG_ON(i915->gt.active_requests); |
214 | ||
12d3173b CW |
215 | /* If the seqno wraps around, we need to clear the breadcrumb rbtree */ |
216 | for_each_engine(engine, i915, id) { | |
e7702760 CW |
217 | GEM_TRACE("%s seqno %d (current %d) -> %d\n", |
218 | engine->name, | |
a89d1f92 | 219 | engine->timeline.seqno, |
e7702760 CW |
220 | intel_engine_get_seqno(engine), |
221 | seqno); | |
d9b13c4d | 222 | |
a89d1f92 | 223 | if (!i915_seqno_passed(seqno, engine->timeline.seqno)) { |
f41d19be CW |
224 | /* Flush any waiters before we reuse the seqno */ |
225 | intel_engine_disarm_breadcrumbs(engine); | |
ea491b23 | 226 | intel_engine_init_hangcheck(engine); |
93eef7d6 | 227 | GEM_BUG_ON(!list_empty(&engine->breadcrumbs.signals)); |
12d3173b CW |
228 | } |
229 | ||
4d53568c CW |
230 | /* Check we are idle before we fiddle with hw state! */ |
231 | GEM_BUG_ON(!intel_engine_is_idle(engine)); | |
a89d1f92 | 232 | GEM_BUG_ON(i915_gem_active_isset(&engine->timeline.last_request)); |
4d53568c | 233 | |
12d3173b | 234 | /* Finally reset hw state */ |
12d3173b | 235 | intel_engine_init_global_seqno(engine, seqno); |
a89d1f92 | 236 | engine->timeline.seqno = seqno; |
12d3173b CW |
237 | } |
238 | ||
a89d1f92 CW |
239 | list_for_each_entry(timeline, &i915->gt.timelines, link) |
240 | memset(timeline->global_sync, 0, sizeof(timeline->global_sync)); | |
241 | ||
52d7f16e | 242 | i915->gt.request_serial = seqno; |
a89d1f92 | 243 | |
12d3173b CW |
244 | return 0; |
245 | } | |
246 | ||
247 | int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno) | |
248 | { | |
e61e0f51 | 249 | struct drm_i915_private *i915 = to_i915(dev); |
12d3173b | 250 | |
e61e0f51 | 251 | lockdep_assert_held(&i915->drm.struct_mutex); |
12d3173b CW |
252 | |
253 | if (seqno == 0) | |
254 | return -EINVAL; | |
255 | ||
e61e0f51 CW |
256 | /* HWS page needs to be set less than what we will inject to ring */ |
257 | return reset_all_global_seqno(i915, seqno - 1); | |
12d3173b CW |
258 | } |
259 | ||
52d7f16e | 260 | static int reserve_gt(struct drm_i915_private *i915) |
636918f1 | 261 | { |
12d3173b CW |
262 | int ret; |
263 | ||
52d7f16e CW |
264 | /* |
265 | * Reservation is fine until we may need to wrap around | |
266 | * | |
267 | * By incrementing the serial for every request, we know that no | |
268 | * individual engine may exceed that serial (as each is reset to 0 | |
269 | * on any wrap). This protects even the most pessimistic of migrations | |
270 | * of every request from all engines onto just one. | |
271 | */ | |
272 | while (unlikely(++i915->gt.request_serial == 0)) { | |
636918f1 CW |
273 | ret = reset_all_global_seqno(i915, 0); |
274 | if (ret) { | |
52d7f16e | 275 | i915->gt.request_serial--; |
636918f1 CW |
276 | return ret; |
277 | } | |
12d3173b CW |
278 | } |
279 | ||
636918f1 | 280 | if (!i915->gt.active_requests++) |
e4d2006f | 281 | i915_gem_unpark(i915); |
636918f1 | 282 | |
12d3173b CW |
283 | return 0; |
284 | } | |
285 | ||
52d7f16e | 286 | static void unreserve_gt(struct drm_i915_private *i915) |
9b6586ae | 287 | { |
b887d615 | 288 | GEM_BUG_ON(!i915->gt.active_requests); |
e4d2006f CW |
289 | if (!--i915->gt.active_requests) |
290 | i915_gem_park(i915); | |
9b6586ae CW |
291 | } |
292 | ||
fa545cbf | 293 | void i915_gem_retire_noop(struct i915_gem_active *active, |
e61e0f51 | 294 | struct i915_request *request) |
fa545cbf CW |
295 | { |
296 | /* Space left intentionally blank */ | |
297 | } | |
298 | ||
e61e0f51 | 299 | static void advance_ring(struct i915_request *request) |
cbb60b4b | 300 | { |
b887d615 | 301 | struct intel_ring *ring = request->ring; |
cbb60b4b CW |
302 | unsigned int tail; |
303 | ||
e61e0f51 CW |
304 | /* |
305 | * We know the GPU must have read the request to have | |
cbb60b4b CW |
306 | * sent us the seqno + interrupt, so use the position |
307 | * of tail of the request to update the last known position | |
308 | * of the GPU head. | |
309 | * | |
310 | * Note this requires that we are always called in request | |
311 | * completion order. | |
312 | */ | |
b887d615 CW |
313 | GEM_BUG_ON(!list_is_first(&request->ring_link, &ring->request_list)); |
314 | if (list_is_last(&request->ring_link, &ring->request_list)) { | |
e61e0f51 CW |
315 | /* |
316 | * We may race here with execlists resubmitting this request | |
e6ba9992 CW |
317 | * as we retire it. The resubmission will move the ring->tail |
318 | * forwards (to request->wa_tail). We either read the | |
319 | * current value that was written to hw, or the value that | |
320 | * is just about to be. Either works, if we miss the last two | |
321 | * noops - they are safe to be replayed on a reset. | |
322 | */ | |
36620032 | 323 | tail = READ_ONCE(request->tail); |
643b450a | 324 | list_del(&ring->active_link); |
e6ba9992 | 325 | } else { |
cbb60b4b | 326 | tail = request->postfix; |
e6ba9992 | 327 | } |
b887d615 | 328 | list_del_init(&request->ring_link); |
cbb60b4b | 329 | |
b887d615 | 330 | ring->head = tail; |
cbb60b4b CW |
331 | } |
332 | ||
e61e0f51 | 333 | static void free_capture_list(struct i915_request *request) |
b0fd47ad | 334 | { |
e61e0f51 | 335 | struct i915_capture_list *capture; |
b0fd47ad CW |
336 | |
337 | capture = request->capture_list; | |
338 | while (capture) { | |
e61e0f51 | 339 | struct i915_capture_list *next = capture->next; |
b0fd47ad CW |
340 | |
341 | kfree(capture); | |
342 | capture = next; | |
343 | } | |
344 | } | |
345 | ||
b887d615 CW |
346 | static void __retire_engine_request(struct intel_engine_cs *engine, |
347 | struct i915_request *rq) | |
348 | { | |
349 | GEM_TRACE("%s(%s) fence %llx:%d, global=%d, current %d\n", | |
350 | __func__, engine->name, | |
351 | rq->fence.context, rq->fence.seqno, | |
352 | rq->global_seqno, | |
353 | intel_engine_get_seqno(engine)); | |
354 | ||
355 | GEM_BUG_ON(!i915_request_completed(rq)); | |
356 | ||
357 | local_irq_disable(); | |
358 | ||
a89d1f92 CW |
359 | spin_lock(&engine->timeline.lock); |
360 | GEM_BUG_ON(!list_is_first(&rq->link, &engine->timeline.requests)); | |
b887d615 | 361 | list_del_init(&rq->link); |
a89d1f92 | 362 | spin_unlock(&engine->timeline.lock); |
b887d615 CW |
363 | |
364 | spin_lock(&rq->lock); | |
365 | if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags)) | |
366 | dma_fence_signal_locked(&rq->fence); | |
367 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) | |
368 | intel_engine_cancel_signaling(rq); | |
369 | if (rq->waitboost) { | |
370 | GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters)); | |
371 | atomic_dec(&rq->i915->gt_pm.rps.num_waiters); | |
372 | } | |
373 | spin_unlock(&rq->lock); | |
374 | ||
375 | local_irq_enable(); | |
376 | ||
377 | /* | |
378 | * The backing object for the context is done after switching to the | |
379 | * *next* context. Therefore we cannot retire the previous context until | |
380 | * the next context has already started running. However, since we | |
381 | * cannot take the required locks at i915_request_submit() we | |
382 | * defer the unpinning of the active context to now, retirement of | |
383 | * the subsequent request. | |
384 | */ | |
385 | if (engine->last_retired_context) | |
386 | intel_context_unpin(engine->last_retired_context, engine); | |
387 | engine->last_retired_context = rq->ctx; | |
388 | } | |
389 | ||
390 | static void __retire_engine_upto(struct intel_engine_cs *engine, | |
391 | struct i915_request *rq) | |
392 | { | |
393 | struct i915_request *tmp; | |
394 | ||
395 | if (list_empty(&rq->link)) | |
396 | return; | |
397 | ||
398 | do { | |
a89d1f92 | 399 | tmp = list_first_entry(&engine->timeline.requests, |
b887d615 CW |
400 | typeof(*tmp), link); |
401 | ||
402 | GEM_BUG_ON(tmp->engine != engine); | |
403 | __retire_engine_request(engine, tmp); | |
404 | } while (tmp != rq); | |
405 | } | |
406 | ||
e61e0f51 | 407 | static void i915_request_retire(struct i915_request *request) |
05235c53 | 408 | { |
fa545cbf CW |
409 | struct i915_gem_active *active, *next; |
410 | ||
0c5c7df3 | 411 | GEM_TRACE("%s fence %llx:%d, global=%d, current %d\n", |
b887d615 | 412 | request->engine->name, |
d9b13c4d | 413 | request->fence.context, request->fence.seqno, |
e7702760 | 414 | request->global_seqno, |
b887d615 | 415 | intel_engine_get_seqno(request->engine)); |
d9b13c4d | 416 | |
4c7d62c6 | 417 | lockdep_assert_held(&request->i915->drm.struct_mutex); |
48bc2a4a | 418 | GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit)); |
e61e0f51 | 419 | GEM_BUG_ON(!i915_request_completed(request)); |
4c7d62c6 | 420 | |
e61e0f51 | 421 | trace_i915_request_retire(request); |
80b204bc | 422 | |
cbb60b4b | 423 | advance_ring(request); |
b0fd47ad CW |
424 | free_capture_list(request); |
425 | ||
e61e0f51 CW |
426 | /* |
427 | * Walk through the active list, calling retire on each. This allows | |
fa545cbf CW |
428 | * objects to track their GPU activity and mark themselves as idle |
429 | * when their *last* active request is completed (updating state | |
430 | * tracking lists for eviction, active references for GEM, etc). | |
431 | * | |
432 | * As the ->retire() may free the node, we decouple it first and | |
433 | * pass along the auxiliary information (to avoid dereferencing | |
434 | * the node after the callback). | |
435 | */ | |
436 | list_for_each_entry_safe(active, next, &request->active_list, link) { | |
e61e0f51 CW |
437 | /* |
438 | * In microbenchmarks or focusing upon time inside the kernel, | |
fa545cbf CW |
439 | * we may spend an inordinate amount of time simply handling |
440 | * the retirement of requests and processing their callbacks. | |
441 | * Of which, this loop itself is particularly hot due to the | |
442 | * cache misses when jumping around the list of i915_gem_active. | |
443 | * So we try to keep this loop as streamlined as possible and | |
444 | * also prefetch the next i915_gem_active to try and hide | |
445 | * the likely cache miss. | |
446 | */ | |
447 | prefetchw(next); | |
448 | ||
449 | INIT_LIST_HEAD(&active->link); | |
0eafec6d | 450 | RCU_INIT_POINTER(active->request, NULL); |
fa545cbf CW |
451 | |
452 | active->retire(active, request); | |
453 | } | |
454 | ||
e61e0f51 | 455 | i915_request_remove_from_client(request); |
05235c53 | 456 | |
e5e1fc47 | 457 | /* Retirement decays the ban score as it is a sign of ctx progress */ |
77b25a97 | 458 | atomic_dec_if_positive(&request->ctx->ban_score); |
b887d615 | 459 | intel_context_unpin(request->ctx, request->engine); |
e5e1fc47 | 460 | |
b887d615 | 461 | __retire_engine_upto(request->engine, request); |
52e54209 | 462 | |
52d7f16e CW |
463 | unreserve_gt(request->i915); |
464 | ||
0c7112a0 | 465 | i915_sched_node_fini(request->i915, &request->sched); |
e61e0f51 | 466 | i915_request_put(request); |
05235c53 CW |
467 | } |
468 | ||
e61e0f51 | 469 | void i915_request_retire_upto(struct i915_request *rq) |
05235c53 | 470 | { |
b887d615 | 471 | struct intel_ring *ring = rq->ring; |
e61e0f51 | 472 | struct i915_request *tmp; |
05235c53 | 473 | |
b887d615 CW |
474 | GEM_TRACE("%s fence %llx:%d, global=%d, current %d\n", |
475 | rq->engine->name, | |
476 | rq->fence.context, rq->fence.seqno, | |
477 | rq->global_seqno, | |
478 | intel_engine_get_seqno(rq->engine)); | |
479 | ||
e61e0f51 CW |
480 | lockdep_assert_held(&rq->i915->drm.struct_mutex); |
481 | GEM_BUG_ON(!i915_request_completed(rq)); | |
4ffd6e0c | 482 | |
b887d615 | 483 | if (list_empty(&rq->ring_link)) |
e95433c7 | 484 | return; |
05235c53 CW |
485 | |
486 | do { | |
b887d615 CW |
487 | tmp = list_first_entry(&ring->request_list, |
488 | typeof(*tmp), ring_link); | |
05235c53 | 489 | |
e61e0f51 CW |
490 | i915_request_retire(tmp); |
491 | } while (tmp != rq); | |
05235c53 CW |
492 | } |
493 | ||
a89d1f92 | 494 | static u32 timeline_get_seqno(struct i915_timeline *tl) |
05235c53 | 495 | { |
9b6586ae | 496 | return ++tl->seqno; |
28176ef4 CW |
497 | } |
498 | ||
4ccfee92 | 499 | static void move_to_timeline(struct i915_request *request, |
a89d1f92 | 500 | struct i915_timeline *timeline) |
4ccfee92 | 501 | { |
a89d1f92 CW |
502 | GEM_BUG_ON(request->timeline == &request->engine->timeline); |
503 | lockdep_assert_held(&request->engine->timeline.lock); | |
4ccfee92 CW |
504 | |
505 | spin_lock(&request->timeline->lock); | |
506 | list_move_tail(&request->link, &timeline->requests); | |
507 | spin_unlock(&request->timeline->lock); | |
508 | } | |
509 | ||
e61e0f51 | 510 | void __i915_request_submit(struct i915_request *request) |
5590af3e | 511 | { |
73cb9701 | 512 | struct intel_engine_cs *engine = request->engine; |
f2d13290 | 513 | u32 seqno; |
5590af3e | 514 | |
0c5c7df3 | 515 | GEM_TRACE("%s fence %llx:%d -> global=%d, current %d\n", |
e7702760 | 516 | engine->name, |
d9b13c4d | 517 | request->fence.context, request->fence.seqno, |
a89d1f92 | 518 | engine->timeline.seqno + 1, |
e7702760 | 519 | intel_engine_get_seqno(engine)); |
d9b13c4d | 520 | |
e60a870d | 521 | GEM_BUG_ON(!irqs_disabled()); |
a89d1f92 | 522 | lockdep_assert_held(&engine->timeline.lock); |
e60a870d | 523 | |
2d453c78 | 524 | GEM_BUG_ON(request->global_seqno); |
5590af3e | 525 | |
a89d1f92 | 526 | seqno = timeline_get_seqno(&engine->timeline); |
f2d13290 CW |
527 | GEM_BUG_ON(!seqno); |
528 | GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno)); | |
529 | ||
f2d13290 CW |
530 | /* We may be recursing from the signal callback of another i915 fence */ |
531 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
532 | request->global_seqno = seqno; | |
533 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) | |
f7b02a52 | 534 | intel_engine_enable_signaling(request, false); |
f2d13290 CW |
535 | spin_unlock(&request->lock); |
536 | ||
caddfe71 CW |
537 | engine->emit_breadcrumb(request, |
538 | request->ring->vaddr + request->postfix); | |
5590af3e | 539 | |
4ccfee92 | 540 | /* Transfer from per-context onto the global per-engine timeline */ |
a89d1f92 | 541 | move_to_timeline(request, &engine->timeline); |
80b204bc | 542 | |
e61e0f51 | 543 | trace_i915_request_execute(request); |
158863fb | 544 | |
fe49789f | 545 | wake_up_all(&request->execute); |
d55ac5bf CW |
546 | } |
547 | ||
e61e0f51 | 548 | void i915_request_submit(struct i915_request *request) |
d55ac5bf CW |
549 | { |
550 | struct intel_engine_cs *engine = request->engine; | |
551 | unsigned long flags; | |
23902e49 | 552 | |
d55ac5bf | 553 | /* Will be called from irq-context when using foreign fences. */ |
a89d1f92 | 554 | spin_lock_irqsave(&engine->timeline.lock, flags); |
d55ac5bf | 555 | |
e61e0f51 | 556 | __i915_request_submit(request); |
d55ac5bf | 557 | |
a89d1f92 | 558 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
d55ac5bf CW |
559 | } |
560 | ||
e61e0f51 | 561 | void __i915_request_unsubmit(struct i915_request *request) |
d55ac5bf | 562 | { |
d6a2289d | 563 | struct intel_engine_cs *engine = request->engine; |
d55ac5bf | 564 | |
0c5c7df3 | 565 | GEM_TRACE("%s fence %llx:%d <- global=%d, current %d\n", |
e7702760 | 566 | engine->name, |
d9b13c4d | 567 | request->fence.context, request->fence.seqno, |
e7702760 CW |
568 | request->global_seqno, |
569 | intel_engine_get_seqno(engine)); | |
d9b13c4d | 570 | |
e60a870d | 571 | GEM_BUG_ON(!irqs_disabled()); |
a89d1f92 | 572 | lockdep_assert_held(&engine->timeline.lock); |
48bc2a4a | 573 | |
e61e0f51 CW |
574 | /* |
575 | * Only unwind in reverse order, required so that the per-context list | |
d6a2289d CW |
576 | * is kept in seqno/ring order. |
577 | */ | |
2d453c78 | 578 | GEM_BUG_ON(!request->global_seqno); |
a89d1f92 | 579 | GEM_BUG_ON(request->global_seqno != engine->timeline.seqno); |
c7cc144d CW |
580 | GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), |
581 | request->global_seqno)); | |
a89d1f92 | 582 | engine->timeline.seqno--; |
80b204bc | 583 | |
d6a2289d CW |
584 | /* We may be recursing from the signal callback of another i915 fence */ |
585 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
586 | request->global_seqno = 0; | |
587 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) | |
588 | intel_engine_cancel_signaling(request); | |
589 | spin_unlock(&request->lock); | |
590 | ||
591 | /* Transfer back from the global per-engine timeline to per-context */ | |
4ccfee92 | 592 | move_to_timeline(request, request->timeline); |
d6a2289d | 593 | |
e61e0f51 CW |
594 | /* |
595 | * We don't need to wake_up any waiters on request->execute, they | |
d6a2289d | 596 | * will get woken by any other event or us re-adding this request |
e61e0f51 | 597 | * to the engine timeline (__i915_request_submit()). The waiters |
d6a2289d CW |
598 | * should be quite adapt at finding that the request now has a new |
599 | * global_seqno to the one they went to sleep on. | |
600 | */ | |
601 | } | |
602 | ||
e61e0f51 | 603 | void i915_request_unsubmit(struct i915_request *request) |
d6a2289d CW |
604 | { |
605 | struct intel_engine_cs *engine = request->engine; | |
606 | unsigned long flags; | |
607 | ||
608 | /* Will be called from irq-context when using foreign fences. */ | |
a89d1f92 | 609 | spin_lock_irqsave(&engine->timeline.lock, flags); |
d6a2289d | 610 | |
e61e0f51 | 611 | __i915_request_unsubmit(request); |
d6a2289d | 612 | |
a89d1f92 | 613 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
5590af3e CW |
614 | } |
615 | ||
23902e49 | 616 | static int __i915_sw_fence_call |
d55ac5bf | 617 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
23902e49 | 618 | { |
e61e0f51 | 619 | struct i915_request *request = |
48bc2a4a | 620 | container_of(fence, typeof(*request), submit); |
48bc2a4a CW |
621 | |
622 | switch (state) { | |
623 | case FENCE_COMPLETE: | |
e61e0f51 | 624 | trace_i915_request_submit(request); |
af7a8ffa | 625 | /* |
e61e0f51 CW |
626 | * We need to serialize use of the submit_request() callback |
627 | * with its hotplugging performed during an emergency | |
628 | * i915_gem_set_wedged(). We use the RCU mechanism to mark the | |
629 | * critical section in order to force i915_gem_set_wedged() to | |
630 | * wait until the submit_request() is completed before | |
631 | * proceeding. | |
af7a8ffa DV |
632 | */ |
633 | rcu_read_lock(); | |
d55ac5bf | 634 | request->engine->submit_request(request); |
af7a8ffa | 635 | rcu_read_unlock(); |
48bc2a4a CW |
636 | break; |
637 | ||
638 | case FENCE_FREE: | |
e61e0f51 | 639 | i915_request_put(request); |
48bc2a4a CW |
640 | break; |
641 | } | |
642 | ||
23902e49 CW |
643 | return NOTIFY_DONE; |
644 | } | |
645 | ||
8e637178 | 646 | /** |
e61e0f51 | 647 | * i915_request_alloc - allocate a request structure |
8e637178 CW |
648 | * |
649 | * @engine: engine that we wish to issue the request on. | |
650 | * @ctx: context that the request will be associated with. | |
8e637178 CW |
651 | * |
652 | * Returns a pointer to the allocated request if successful, | |
653 | * or an error code if not. | |
654 | */ | |
e61e0f51 CW |
655 | struct i915_request * |
656 | i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx) | |
05235c53 | 657 | { |
e61e0f51 CW |
658 | struct drm_i915_private *i915 = engine->i915; |
659 | struct i915_request *rq; | |
266a240b | 660 | struct intel_ring *ring; |
05235c53 CW |
661 | int ret; |
662 | ||
e61e0f51 | 663 | lockdep_assert_held(&i915->drm.struct_mutex); |
28176ef4 | 664 | |
e7af3116 CW |
665 | /* |
666 | * Preempt contexts are reserved for exclusive use to inject a | |
667 | * preemption context switch. They are never to be used for any trivial | |
668 | * request! | |
669 | */ | |
e61e0f51 | 670 | GEM_BUG_ON(ctx == i915->preempt_context); |
e7af3116 | 671 | |
e61e0f51 CW |
672 | /* |
673 | * ABI: Before userspace accesses the GPU (e.g. execbuffer), report | |
6ffb7d07 | 674 | * EIO if the GPU is already wedged. |
05235c53 | 675 | */ |
e61e0f51 | 676 | if (i915_terminally_wedged(&i915->gpu_error)) |
6ffb7d07 | 677 | return ERR_PTR(-EIO); |
05235c53 | 678 | |
e61e0f51 CW |
679 | /* |
680 | * Pinning the contexts may generate requests in order to acquire | |
e8a9c58f CW |
681 | * GGTT space, so do this first before we reserve a seqno for |
682 | * ourselves. | |
683 | */ | |
ab82a063 | 684 | ring = intel_context_pin(ctx, engine); |
266a240b CW |
685 | if (IS_ERR(ring)) |
686 | return ERR_CAST(ring); | |
687 | GEM_BUG_ON(!ring); | |
28176ef4 | 688 | |
52d7f16e | 689 | ret = reserve_gt(i915); |
e8a9c58f CW |
690 | if (ret) |
691 | goto err_unpin; | |
692 | ||
3fef5cda CW |
693 | ret = intel_ring_wait_for_space(ring, MIN_SPACE_FOR_ADD_REQUEST); |
694 | if (ret) | |
695 | goto err_unreserve; | |
696 | ||
b887d615 | 697 | /* Move our oldest request to the slab-cache (if not in use!) */ |
7c572e1b CW |
698 | rq = list_first_entry(&ring->request_list, typeof(*rq), ring_link); |
699 | if (!list_is_last(&rq->ring_link, &ring->request_list) && | |
700 | i915_request_completed(rq)) | |
e61e0f51 | 701 | i915_request_retire(rq); |
9b5f4e5e | 702 | |
e61e0f51 CW |
703 | /* |
704 | * Beware: Dragons be flying overhead. | |
5a198b8c CW |
705 | * |
706 | * We use RCU to look up requests in flight. The lookups may | |
707 | * race with the request being allocated from the slab freelist. | |
708 | * That is the request we are writing to here, may be in the process | |
1426f715 | 709 | * of being read by __i915_gem_active_get_rcu(). As such, |
5a198b8c CW |
710 | * we have to be very careful when overwriting the contents. During |
711 | * the RCU lookup, we change chase the request->engine pointer, | |
65e4760e | 712 | * read the request->global_seqno and increment the reference count. |
5a198b8c CW |
713 | * |
714 | * The reference count is incremented atomically. If it is zero, | |
715 | * the lookup knows the request is unallocated and complete. Otherwise, | |
716 | * it is either still in use, or has been reallocated and reset | |
f54d1867 CW |
717 | * with dma_fence_init(). This increment is safe for release as we |
718 | * check that the request we have a reference to and matches the active | |
5a198b8c CW |
719 | * request. |
720 | * | |
721 | * Before we increment the refcount, we chase the request->engine | |
722 | * pointer. We must not call kmem_cache_zalloc() or else we set | |
723 | * that pointer to NULL and cause a crash during the lookup. If | |
724 | * we see the request is completed (based on the value of the | |
725 | * old engine and seqno), the lookup is complete and reports NULL. | |
726 | * If we decide the request is not completed (new engine or seqno), | |
727 | * then we grab a reference and double check that it is still the | |
728 | * active request - which it won't be and restart the lookup. | |
729 | * | |
730 | * Do not use kmem_cache_zalloc() here! | |
731 | */ | |
e61e0f51 CW |
732 | rq = kmem_cache_alloc(i915->requests, |
733 | GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); | |
734 | if (unlikely(!rq)) { | |
31c70f97 | 735 | /* Ratelimit ourselves to prevent oom from malicious clients */ |
e61e0f51 | 736 | ret = i915_gem_wait_for_idle(i915, |
31c70f97 CW |
737 | I915_WAIT_LOCKED | |
738 | I915_WAIT_INTERRUPTIBLE); | |
739 | if (ret) | |
740 | goto err_unreserve; | |
741 | ||
f0111b04 CW |
742 | /* |
743 | * We've forced the client to stall and catch up with whatever | |
744 | * backlog there might have been. As we are assuming that we | |
745 | * caused the mempressure, now is an opportune time to | |
746 | * recover as much memory from the request pool as is possible. | |
747 | * Having already penalized the client to stall, we spend | |
748 | * a little extra time to re-optimise page allocation. | |
749 | */ | |
e61e0f51 | 750 | kmem_cache_shrink(i915->requests); |
f0111b04 CW |
751 | rcu_barrier(); /* Recover the TYPESAFE_BY_RCU pages */ |
752 | ||
e61e0f51 CW |
753 | rq = kmem_cache_alloc(i915->requests, GFP_KERNEL); |
754 | if (!rq) { | |
31c70f97 CW |
755 | ret = -ENOMEM; |
756 | goto err_unreserve; | |
757 | } | |
28176ef4 | 758 | } |
05235c53 | 759 | |
65fcb806 CW |
760 | INIT_LIST_HEAD(&rq->active_list); |
761 | rq->i915 = i915; | |
762 | rq->engine = engine; | |
763 | rq->ctx = ctx; | |
764 | rq->ring = ring; | |
765 | rq->timeline = ring->timeline; | |
a89d1f92 | 766 | GEM_BUG_ON(rq->timeline == &engine->timeline); |
73cb9701 | 767 | |
e61e0f51 CW |
768 | spin_lock_init(&rq->lock); |
769 | dma_fence_init(&rq->fence, | |
f54d1867 | 770 | &i915_fence_ops, |
e61e0f51 CW |
771 | &rq->lock, |
772 | rq->timeline->fence_context, | |
773 | timeline_get_seqno(rq->timeline)); | |
04769652 | 774 | |
48bc2a4a | 775 | /* We bump the ref for the fence chain */ |
e61e0f51 CW |
776 | i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify); |
777 | init_waitqueue_head(&rq->execute); | |
5590af3e | 778 | |
0c7112a0 | 779 | i915_sched_node_init(&rq->sched); |
52e54209 | 780 | |
5a198b8c | 781 | /* No zalloc, must clear what we need by hand */ |
e61e0f51 CW |
782 | rq->global_seqno = 0; |
783 | rq->signaling.wait.seqno = 0; | |
784 | rq->file_priv = NULL; | |
785 | rq->batch = NULL; | |
786 | rq->capture_list = NULL; | |
787 | rq->waitboost = false; | |
5a198b8c | 788 | |
05235c53 CW |
789 | /* |
790 | * Reserve space in the ring buffer for all the commands required to | |
791 | * eventually emit this request. This is to guarantee that the | |
e61e0f51 | 792 | * i915_request_add() call can't fail. Note that the reserve may need |
05235c53 CW |
793 | * to be redone if the request is not actually submitted straight |
794 | * away, e.g. because a GPU scheduler has deferred it. | |
795 | */ | |
e61e0f51 CW |
796 | rq->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; |
797 | GEM_BUG_ON(rq->reserved_space < engine->emit_breadcrumb_sz); | |
05235c53 | 798 | |
2113184c CW |
799 | /* |
800 | * Record the position of the start of the request so that | |
d045446d CW |
801 | * should we detect the updated seqno part-way through the |
802 | * GPU processing the request, we never over-estimate the | |
803 | * position of the head. | |
804 | */ | |
e61e0f51 | 805 | rq->head = rq->ring->emit; |
d045446d | 806 | |
2113184c | 807 | /* Unconditionally invalidate GPU caches and TLBs. */ |
e61e0f51 | 808 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); |
2113184c | 809 | if (ret) |
b1c24a61 | 810 | goto err_unwind; |
2113184c | 811 | |
e61e0f51 | 812 | ret = engine->request_alloc(rq); |
b1c24a61 CW |
813 | if (ret) |
814 | goto err_unwind; | |
2113184c | 815 | |
b887d615 CW |
816 | /* Keep a second pin for the dual retirement along engine and ring */ |
817 | __intel_context_pin(rq->ctx, engine); | |
818 | ||
9b6586ae | 819 | /* Check that we didn't interrupt ourselves with a new request */ |
e61e0f51 CW |
820 | GEM_BUG_ON(rq->timeline->seqno != rq->fence.seqno); |
821 | return rq; | |
05235c53 | 822 | |
b1c24a61 | 823 | err_unwind: |
e61e0f51 | 824 | rq->ring->emit = rq->head; |
b1c24a61 | 825 | |
1618bdb8 | 826 | /* Make sure we didn't add ourselves to external state before freeing */ |
e61e0f51 | 827 | GEM_BUG_ON(!list_empty(&rq->active_list)); |
0c7112a0 CW |
828 | GEM_BUG_ON(!list_empty(&rq->sched.signalers_list)); |
829 | GEM_BUG_ON(!list_empty(&rq->sched.waiters_list)); | |
1618bdb8 | 830 | |
e61e0f51 | 831 | kmem_cache_free(i915->requests, rq); |
28176ef4 | 832 | err_unreserve: |
52d7f16e | 833 | unreserve_gt(i915); |
e8a9c58f | 834 | err_unpin: |
ab82a063 | 835 | intel_context_unpin(ctx, engine); |
8e637178 | 836 | return ERR_PTR(ret); |
05235c53 CW |
837 | } |
838 | ||
a2bc4695 | 839 | static int |
e61e0f51 | 840 | i915_request_await_request(struct i915_request *to, struct i915_request *from) |
a2bc4695 | 841 | { |
85e17f59 | 842 | int ret; |
a2bc4695 CW |
843 | |
844 | GEM_BUG_ON(to == from); | |
ceae14bd | 845 | GEM_BUG_ON(to->timeline == from->timeline); |
a2bc4695 | 846 | |
e61e0f51 | 847 | if (i915_request_completed(from)) |
ade0b0c9 CW |
848 | return 0; |
849 | ||
52e54209 | 850 | if (to->engine->schedule) { |
0c7112a0 CW |
851 | ret = i915_sched_node_add_dependency(to->i915, |
852 | &to->sched, | |
853 | &from->sched); | |
52e54209 CW |
854 | if (ret < 0) |
855 | return ret; | |
856 | } | |
857 | ||
73cb9701 CW |
858 | if (to->engine == from->engine) { |
859 | ret = i915_sw_fence_await_sw_fence_gfp(&to->submit, | |
860 | &from->submit, | |
2abe2f84 | 861 | I915_FENCE_GFP); |
73cb9701 CW |
862 | return ret < 0 ? ret : 0; |
863 | } | |
864 | ||
6b567085 CW |
865 | if (to->engine->semaphore.sync_to) { |
866 | u32 seqno; | |
65e4760e | 867 | |
6b567085 | 868 | GEM_BUG_ON(!from->engine->semaphore.signal); |
fc9d4d2b | 869 | |
e61e0f51 | 870 | seqno = i915_request_global_seqno(from); |
6b567085 | 871 | if (!seqno) |
fc9d4d2b | 872 | goto await_dma_fence; |
49f08598 | 873 | |
fc9d4d2b CW |
874 | if (seqno <= to->timeline->global_sync[from->engine->id]) |
875 | return 0; | |
876 | ||
877 | trace_i915_gem_ring_sync_to(to, from); | |
a2bc4695 CW |
878 | ret = to->engine->semaphore.sync_to(to, from); |
879 | if (ret) | |
880 | return ret; | |
fc9d4d2b CW |
881 | |
882 | to->timeline->global_sync[from->engine->id] = seqno; | |
6b567085 | 883 | return 0; |
a2bc4695 CW |
884 | } |
885 | ||
fc9d4d2b CW |
886 | await_dma_fence: |
887 | ret = i915_sw_fence_await_dma_fence(&to->submit, | |
888 | &from->fence, 0, | |
2abe2f84 | 889 | I915_FENCE_GFP); |
fc9d4d2b | 890 | return ret < 0 ? ret : 0; |
a2bc4695 CW |
891 | } |
892 | ||
b52992c0 | 893 | int |
e61e0f51 | 894 | i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) |
b52992c0 | 895 | { |
29ef3fa9 CW |
896 | struct dma_fence **child = &fence; |
897 | unsigned int nchild = 1; | |
b52992c0 | 898 | int ret; |
b52992c0 | 899 | |
e61e0f51 CW |
900 | /* |
901 | * Note that if the fence-array was created in signal-on-any mode, | |
b52992c0 CW |
902 | * we should *not* decompose it into its individual fences. However, |
903 | * we don't currently store which mode the fence-array is operating | |
904 | * in. Fortunately, the only user of signal-on-any is private to | |
905 | * amdgpu and we should not see any incoming fence-array from | |
906 | * sync-file being in signal-on-any mode. | |
907 | */ | |
29ef3fa9 CW |
908 | if (dma_fence_is_array(fence)) { |
909 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
910 | ||
911 | child = array->fences; | |
912 | nchild = array->num_fences; | |
913 | GEM_BUG_ON(!nchild); | |
914 | } | |
b52992c0 | 915 | |
29ef3fa9 CW |
916 | do { |
917 | fence = *child++; | |
918 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
919 | continue; | |
b52992c0 | 920 | |
ceae14bd CW |
921 | /* |
922 | * Requests on the same timeline are explicitly ordered, along | |
e61e0f51 | 923 | * with their dependencies, by i915_request_add() which ensures |
ceae14bd CW |
924 | * that requests are submitted in-order through each ring. |
925 | */ | |
e61e0f51 | 926 | if (fence->context == rq->fence.context) |
ceae14bd CW |
927 | continue; |
928 | ||
47979480 | 929 | /* Squash repeated waits to the same timelines */ |
e61e0f51 | 930 | if (fence->context != rq->i915->mm.unordered_timeline && |
a89d1f92 | 931 | i915_timeline_sync_is_later(rq->timeline, fence)) |
47979480 CW |
932 | continue; |
933 | ||
29ef3fa9 | 934 | if (dma_fence_is_i915(fence)) |
e61e0f51 | 935 | ret = i915_request_await_request(rq, to_request(fence)); |
b52992c0 | 936 | else |
e61e0f51 | 937 | ret = i915_sw_fence_await_dma_fence(&rq->submit, fence, |
29ef3fa9 | 938 | I915_FENCE_TIMEOUT, |
2abe2f84 | 939 | I915_FENCE_GFP); |
b52992c0 CW |
940 | if (ret < 0) |
941 | return ret; | |
47979480 CW |
942 | |
943 | /* Record the latest fence used against each timeline */ | |
e61e0f51 | 944 | if (fence->context != rq->i915->mm.unordered_timeline) |
a89d1f92 | 945 | i915_timeline_sync_set(rq->timeline, fence); |
29ef3fa9 | 946 | } while (--nchild); |
b52992c0 CW |
947 | |
948 | return 0; | |
949 | } | |
950 | ||
a2bc4695 | 951 | /** |
e61e0f51 | 952 | * i915_request_await_object - set this request to (async) wait upon a bo |
a2bc4695 CW |
953 | * @to: request we are wishing to use |
954 | * @obj: object which may be in use on another ring. | |
d8802126 | 955 | * @write: whether the wait is on behalf of a writer |
a2bc4695 CW |
956 | * |
957 | * This code is meant to abstract object synchronization with the GPU. | |
958 | * Conceptually we serialise writes between engines inside the GPU. | |
959 | * We only allow one engine to write into a buffer at any time, but | |
960 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
961 | * | |
962 | * - If there is an outstanding write request to the object, the new | |
963 | * request must wait for it to complete (either CPU or in hw, requests | |
964 | * on the same ring will be naturally ordered). | |
965 | * | |
966 | * - If we are a write request (pending_write_domain is set), the new | |
967 | * request must wait for outstanding read requests to complete. | |
968 | * | |
969 | * Returns 0 if successful, else propagates up the lower layer error. | |
970 | */ | |
971 | int | |
e61e0f51 CW |
972 | i915_request_await_object(struct i915_request *to, |
973 | struct drm_i915_gem_object *obj, | |
974 | bool write) | |
a2bc4695 | 975 | { |
d07f0e59 CW |
976 | struct dma_fence *excl; |
977 | int ret = 0; | |
a2bc4695 CW |
978 | |
979 | if (write) { | |
d07f0e59 CW |
980 | struct dma_fence **shared; |
981 | unsigned int count, i; | |
982 | ||
983 | ret = reservation_object_get_fences_rcu(obj->resv, | |
984 | &excl, &count, &shared); | |
985 | if (ret) | |
986 | return ret; | |
987 | ||
988 | for (i = 0; i < count; i++) { | |
e61e0f51 | 989 | ret = i915_request_await_dma_fence(to, shared[i]); |
d07f0e59 CW |
990 | if (ret) |
991 | break; | |
992 | ||
993 | dma_fence_put(shared[i]); | |
994 | } | |
995 | ||
996 | for (; i < count; i++) | |
997 | dma_fence_put(shared[i]); | |
998 | kfree(shared); | |
a2bc4695 | 999 | } else { |
d07f0e59 | 1000 | excl = reservation_object_get_excl_rcu(obj->resv); |
a2bc4695 CW |
1001 | } |
1002 | ||
d07f0e59 CW |
1003 | if (excl) { |
1004 | if (ret == 0) | |
e61e0f51 | 1005 | ret = i915_request_await_dma_fence(to, excl); |
a2bc4695 | 1006 | |
d07f0e59 | 1007 | dma_fence_put(excl); |
a2bc4695 CW |
1008 | } |
1009 | ||
d07f0e59 | 1010 | return ret; |
a2bc4695 CW |
1011 | } |
1012 | ||
05235c53 CW |
1013 | /* |
1014 | * NB: This function is not allowed to fail. Doing so would mean the the | |
1015 | * request is not being tracked for completion but the work itself is | |
1016 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
1017 | */ | |
e61e0f51 | 1018 | void __i915_request_add(struct i915_request *request, bool flush_caches) |
05235c53 | 1019 | { |
95b2ab56 CW |
1020 | struct intel_engine_cs *engine = request->engine; |
1021 | struct intel_ring *ring = request->ring; | |
a89d1f92 | 1022 | struct i915_timeline *timeline = request->timeline; |
e61e0f51 | 1023 | struct i915_request *prev; |
73dec95e | 1024 | u32 *cs; |
caddfe71 | 1025 | int err; |
05235c53 | 1026 | |
d9b13c4d CW |
1027 | GEM_TRACE("%s fence %llx:%d\n", |
1028 | engine->name, request->fence.context, request->fence.seqno); | |
1029 | ||
4c7d62c6 | 1030 | lockdep_assert_held(&request->i915->drm.struct_mutex); |
e61e0f51 | 1031 | trace_i915_request_add(request); |
0f25dff6 | 1032 | |
8ac71d1d CW |
1033 | /* |
1034 | * Make sure that no request gazumped us - if it was allocated after | |
e61e0f51 | 1035 | * our i915_request_alloc() and called __i915_request_add() before |
c781c978 CW |
1036 | * us, the timeline will hold its seqno which is later than ours. |
1037 | */ | |
9b6586ae | 1038 | GEM_BUG_ON(timeline->seqno != request->fence.seqno); |
c781c978 | 1039 | |
05235c53 CW |
1040 | /* |
1041 | * To ensure that this call will not fail, space for its emissions | |
1042 | * should already have been reserved in the ring buffer. Let the ring | |
1043 | * know that it is time to use that space up. | |
1044 | */ | |
05235c53 CW |
1045 | request->reserved_space = 0; |
1046 | ||
1047 | /* | |
1048 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1049 | * after having emitted the batchbuffer command. Hence we need to fix | |
1050 | * things up similar to emitting the lazy request. The difference here | |
1051 | * is that the flush _must_ happen before the next request, no matter | |
1052 | * what. | |
1053 | */ | |
1054 | if (flush_caches) { | |
caddfe71 | 1055 | err = engine->emit_flush(request, EMIT_FLUSH); |
c7fe7d25 | 1056 | |
05235c53 | 1057 | /* Not allowed to fail! */ |
caddfe71 | 1058 | WARN(err, "engine->emit_flush() failed: %d!\n", err); |
05235c53 CW |
1059 | } |
1060 | ||
8ac71d1d CW |
1061 | /* |
1062 | * Record the position of the start of the breadcrumb so that | |
05235c53 CW |
1063 | * should we detect the updated seqno part-way through the |
1064 | * GPU processing the request, we never over-estimate the | |
d045446d | 1065 | * position of the ring's HEAD. |
05235c53 | 1066 | */ |
73dec95e TU |
1067 | cs = intel_ring_begin(request, engine->emit_breadcrumb_sz); |
1068 | GEM_BUG_ON(IS_ERR(cs)); | |
1069 | request->postfix = intel_ring_offset(request, cs); | |
05235c53 | 1070 | |
8ac71d1d CW |
1071 | /* |
1072 | * Seal the request and mark it as pending execution. Note that | |
0f25dff6 CW |
1073 | * we may inspect this state, without holding any locks, during |
1074 | * hangcheck. Hence we apply the barrier to ensure that we do not | |
1075 | * see a more recent value in the hws than we are tracking. | |
1076 | */ | |
0a046a0e | 1077 | |
73cb9701 | 1078 | prev = i915_gem_active_raw(&timeline->last_request, |
0a046a0e | 1079 | &request->i915->drm.struct_mutex); |
e61e0f51 | 1080 | if (prev && !i915_request_completed(prev)) { |
0a046a0e CW |
1081 | i915_sw_fence_await_sw_fence(&request->submit, &prev->submit, |
1082 | &request->submitq); | |
52e54209 | 1083 | if (engine->schedule) |
0c7112a0 CW |
1084 | __i915_sched_node_add_dependency(&request->sched, |
1085 | &prev->sched, | |
1086 | &request->dep, | |
1087 | 0); | |
52e54209 | 1088 | } |
0a046a0e | 1089 | |
80b204bc | 1090 | spin_lock_irq(&timeline->lock); |
f2d13290 | 1091 | list_add_tail(&request->link, &timeline->requests); |
80b204bc CW |
1092 | spin_unlock_irq(&timeline->lock); |
1093 | ||
9b6586ae | 1094 | GEM_BUG_ON(timeline->seqno != request->fence.seqno); |
73cb9701 | 1095 | i915_gem_active_set(&timeline->last_request, request); |
f2d13290 | 1096 | |
0f25dff6 | 1097 | list_add_tail(&request->ring_link, &ring->request_list); |
643b450a CW |
1098 | if (list_is_first(&request->ring_link, &ring->request_list)) |
1099 | list_add(&ring->active_link, &request->i915->gt.active_rings); | |
f2d13290 | 1100 | request->emitted_jiffies = jiffies; |
0f25dff6 | 1101 | |
8ac71d1d CW |
1102 | /* |
1103 | * Let the backend know a new request has arrived that may need | |
0de9136d CW |
1104 | * to adjust the existing execution schedule due to a high priority |
1105 | * request - i.e. we may want to preempt the current request in order | |
1106 | * to run a high priority dependency chain *before* we can execute this | |
1107 | * request. | |
1108 | * | |
1109 | * This is called before the request is ready to run so that we can | |
1110 | * decide whether to preempt the entire chain so that it is ready to | |
1111 | * run at the earliest possible convenience. | |
1112 | */ | |
47650db0 | 1113 | rcu_read_lock(); |
0de9136d | 1114 | if (engine->schedule) |
b7268c5e | 1115 | engine->schedule(request, &request->ctx->sched); |
47650db0 | 1116 | rcu_read_unlock(); |
0de9136d | 1117 | |
5590af3e CW |
1118 | local_bh_disable(); |
1119 | i915_sw_fence_commit(&request->submit); | |
1120 | local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ | |
c22b355f CW |
1121 | |
1122 | /* | |
1123 | * In typical scenarios, we do not expect the previous request on | |
1124 | * the timeline to be still tracked by timeline->last_request if it | |
1125 | * has been completed. If the completed request is still here, that | |
1126 | * implies that request retirement is a long way behind submission, | |
1127 | * suggesting that we haven't been retiring frequently enough from | |
1128 | * the combination of retire-before-alloc, waiters and the background | |
1129 | * retirement worker. So if the last request on this timeline was | |
1130 | * already completed, do a catch up pass, flushing the retirement queue | |
1131 | * up to this client. Since we have now moved the heaviest operations | |
1132 | * during retirement onto secondary workers, such as freeing objects | |
1133 | * or contexts, retiring a bunch of requests is mostly list management | |
1134 | * (and cache misses), and so we should not be overly penalizing this | |
1135 | * client by performing excess work, though we may still performing | |
1136 | * work on behalf of others -- but instead we should benefit from | |
1137 | * improved resource management. (Well, that's the theory at least.) | |
1138 | */ | |
e61e0f51 CW |
1139 | if (prev && i915_request_completed(prev)) |
1140 | i915_request_retire_upto(prev); | |
05235c53 CW |
1141 | } |
1142 | ||
1143 | static unsigned long local_clock_us(unsigned int *cpu) | |
1144 | { | |
1145 | unsigned long t; | |
1146 | ||
e61e0f51 CW |
1147 | /* |
1148 | * Cheaply and approximately convert from nanoseconds to microseconds. | |
05235c53 CW |
1149 | * The result and subsequent calculations are also defined in the same |
1150 | * approximate microseconds units. The principal source of timing | |
1151 | * error here is from the simple truncation. | |
1152 | * | |
1153 | * Note that local_clock() is only defined wrt to the current CPU; | |
1154 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1155 | * blocking preemption for the entire busywait, we can detect the CPU | |
1156 | * switch and use that as indicator of system load and a reason to | |
1157 | * stop busywaiting, see busywait_stop(). | |
1158 | */ | |
1159 | *cpu = get_cpu(); | |
1160 | t = local_clock() >> 10; | |
1161 | put_cpu(); | |
1162 | ||
1163 | return t; | |
1164 | } | |
1165 | ||
1166 | static bool busywait_stop(unsigned long timeout, unsigned int cpu) | |
1167 | { | |
1168 | unsigned int this_cpu; | |
1169 | ||
1170 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
1171 | return true; | |
1172 | ||
1173 | return this_cpu != cpu; | |
1174 | } | |
1175 | ||
e61e0f51 | 1176 | static bool __i915_spin_request(const struct i915_request *rq, |
b2f2f0fc | 1177 | u32 seqno, int state, unsigned long timeout_us) |
05235c53 | 1178 | { |
e61e0f51 | 1179 | struct intel_engine_cs *engine = rq->engine; |
c33ed067 | 1180 | unsigned int irq, cpu; |
05235c53 | 1181 | |
b2f2f0fc CW |
1182 | GEM_BUG_ON(!seqno); |
1183 | ||
1184 | /* | |
1185 | * Only wait for the request if we know it is likely to complete. | |
1186 | * | |
1187 | * We don't track the timestamps around requests, nor the average | |
1188 | * request length, so we do not have a good indicator that this | |
1189 | * request will complete within the timeout. What we do know is the | |
1190 | * order in which requests are executed by the engine and so we can | |
1191 | * tell if the request has started. If the request hasn't started yet, | |
1192 | * it is a fair assumption that it will not complete within our | |
1193 | * relatively short timeout. | |
1194 | */ | |
1195 | if (!i915_seqno_passed(intel_engine_get_seqno(engine), seqno - 1)) | |
1196 | return false; | |
1197 | ||
e61e0f51 CW |
1198 | /* |
1199 | * When waiting for high frequency requests, e.g. during synchronous | |
05235c53 CW |
1200 | * rendering split between the CPU and GPU, the finite amount of time |
1201 | * required to set up the irq and wait upon it limits the response | |
1202 | * rate. By busywaiting on the request completion for a short while we | |
1203 | * can service the high frequency waits as quick as possible. However, | |
1204 | * if it is a slow request, we want to sleep as quickly as possible. | |
1205 | * The tradeoff between waiting and sleeping is roughly the time it | |
1206 | * takes to sleep on a request, on the order of a microsecond. | |
1207 | */ | |
1208 | ||
c33ed067 | 1209 | irq = atomic_read(&engine->irq_count); |
05235c53 CW |
1210 | timeout_us += local_clock_us(&cpu); |
1211 | do { | |
b2f2f0fc | 1212 | if (i915_seqno_passed(intel_engine_get_seqno(engine), seqno)) |
e61e0f51 | 1213 | return seqno == i915_request_global_seqno(rq); |
05235c53 | 1214 | |
e61e0f51 CW |
1215 | /* |
1216 | * Seqno are meant to be ordered *before* the interrupt. If | |
c33ed067 CW |
1217 | * we see an interrupt without a corresponding seqno advance, |
1218 | * assume we won't see one in the near future but require | |
1219 | * the engine->seqno_barrier() to fixup coherency. | |
1220 | */ | |
1221 | if (atomic_read(&engine->irq_count) != irq) | |
1222 | break; | |
1223 | ||
05235c53 CW |
1224 | if (signal_pending_state(state, current)) |
1225 | break; | |
1226 | ||
1227 | if (busywait_stop(timeout_us, cpu)) | |
1228 | break; | |
1229 | ||
f2f09a4c | 1230 | cpu_relax(); |
05235c53 CW |
1231 | } while (!need_resched()); |
1232 | ||
1233 | return false; | |
1234 | } | |
1235 | ||
e61e0f51 | 1236 | static bool __i915_wait_request_check_and_reset(struct i915_request *request) |
4680816b | 1237 | { |
d0667e9c CW |
1238 | struct i915_gpu_error *error = &request->i915->gpu_error; |
1239 | ||
1240 | if (likely(!i915_reset_handoff(error))) | |
e0705114 | 1241 | return false; |
4680816b | 1242 | |
e0705114 | 1243 | __set_current_state(TASK_RUNNING); |
d0667e9c | 1244 | i915_reset(request->i915, error->stalled_mask, error->reason); |
e0705114 | 1245 | return true; |
4680816b CW |
1246 | } |
1247 | ||
05235c53 | 1248 | /** |
e532be89 | 1249 | * i915_request_wait - wait until execution of request has finished |
e61e0f51 | 1250 | * @rq: the request to wait upon |
ea746f36 | 1251 | * @flags: how to wait |
e95433c7 CW |
1252 | * @timeout: how long to wait in jiffies |
1253 | * | |
e532be89 | 1254 | * i915_request_wait() waits for the request to be completed, for a |
e95433c7 CW |
1255 | * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an |
1256 | * unbounded wait). | |
05235c53 | 1257 | * |
e95433c7 CW |
1258 | * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED |
1259 | * in via the flags, and vice versa if the struct_mutex is not held, the caller | |
1260 | * must not specify that the wait is locked. | |
05235c53 | 1261 | * |
e95433c7 CW |
1262 | * Returns the remaining time (in jiffies) if the request completed, which may |
1263 | * be zero or -ETIME if the request is unfinished after the timeout expires. | |
1264 | * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is | |
1265 | * pending before the request completes. | |
05235c53 | 1266 | */ |
e61e0f51 | 1267 | long i915_request_wait(struct i915_request *rq, |
e95433c7 CW |
1268 | unsigned int flags, |
1269 | long timeout) | |
05235c53 | 1270 | { |
ea746f36 CW |
1271 | const int state = flags & I915_WAIT_INTERRUPTIBLE ? |
1272 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
e61e0f51 | 1273 | wait_queue_head_t *errq = &rq->i915->gpu_error.wait_queue; |
a49625f9 CW |
1274 | DEFINE_WAIT_FUNC(reset, default_wake_function); |
1275 | DEFINE_WAIT_FUNC(exec, default_wake_function); | |
05235c53 | 1276 | struct intel_wait wait; |
05235c53 CW |
1277 | |
1278 | might_sleep(); | |
22dd3bb9 | 1279 | #if IS_ENABLED(CONFIG_LOCKDEP) |
e95433c7 | 1280 | GEM_BUG_ON(debug_locks && |
e61e0f51 | 1281 | !!lockdep_is_held(&rq->i915->drm.struct_mutex) != |
22dd3bb9 CW |
1282 | !!(flags & I915_WAIT_LOCKED)); |
1283 | #endif | |
e95433c7 | 1284 | GEM_BUG_ON(timeout < 0); |
05235c53 | 1285 | |
e61e0f51 | 1286 | if (i915_request_completed(rq)) |
e95433c7 | 1287 | return timeout; |
05235c53 | 1288 | |
e95433c7 CW |
1289 | if (!timeout) |
1290 | return -ETIME; | |
05235c53 | 1291 | |
e61e0f51 | 1292 | trace_i915_request_wait_begin(rq, flags); |
05235c53 | 1293 | |
e61e0f51 | 1294 | add_wait_queue(&rq->execute, &exec); |
7de53bf7 CW |
1295 | if (flags & I915_WAIT_LOCKED) |
1296 | add_wait_queue(errq, &reset); | |
1297 | ||
e61e0f51 | 1298 | intel_wait_init(&wait, rq); |
754c9fd5 | 1299 | |
d6a2289d | 1300 | restart: |
0f2f61d4 CW |
1301 | do { |
1302 | set_current_state(state); | |
e61e0f51 | 1303 | if (intel_wait_update_request(&wait, rq)) |
0f2f61d4 | 1304 | break; |
541ca6ed | 1305 | |
0f2f61d4 | 1306 | if (flags & I915_WAIT_LOCKED && |
e61e0f51 | 1307 | __i915_wait_request_check_and_reset(rq)) |
0f2f61d4 | 1308 | continue; |
05235c53 | 1309 | |
0f2f61d4 CW |
1310 | if (signal_pending_state(state, current)) { |
1311 | timeout = -ERESTARTSYS; | |
4680816b | 1312 | goto complete; |
0f2f61d4 | 1313 | } |
4680816b | 1314 | |
0f2f61d4 CW |
1315 | if (!timeout) { |
1316 | timeout = -ETIME; | |
1317 | goto complete; | |
1318 | } | |
541ca6ed | 1319 | |
0f2f61d4 CW |
1320 | timeout = io_schedule_timeout(timeout); |
1321 | } while (1); | |
4680816b | 1322 | |
0f2f61d4 | 1323 | GEM_BUG_ON(!intel_wait_has_seqno(&wait)); |
e61e0f51 | 1324 | GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); |
4680816b | 1325 | |
437c3087 | 1326 | /* Optimistic short spin before touching IRQs */ |
e61e0f51 | 1327 | if (__i915_spin_request(rq, wait.seqno, state, 5)) |
05235c53 CW |
1328 | goto complete; |
1329 | ||
1330 | set_current_state(state); | |
e61e0f51 CW |
1331 | if (intel_engine_add_wait(rq->engine, &wait)) |
1332 | /* | |
1333 | * In order to check that we haven't missed the interrupt | |
05235c53 CW |
1334 | * as we enabled it, we need to kick ourselves to do a |
1335 | * coherent check on the seqno before we sleep. | |
1336 | */ | |
1337 | goto wakeup; | |
1338 | ||
24f417ec | 1339 | if (flags & I915_WAIT_LOCKED) |
e61e0f51 | 1340 | __i915_wait_request_check_and_reset(rq); |
24f417ec | 1341 | |
05235c53 CW |
1342 | for (;;) { |
1343 | if (signal_pending_state(state, current)) { | |
e95433c7 | 1344 | timeout = -ERESTARTSYS; |
05235c53 CW |
1345 | break; |
1346 | } | |
1347 | ||
e95433c7 CW |
1348 | if (!timeout) { |
1349 | timeout = -ETIME; | |
05235c53 CW |
1350 | break; |
1351 | } | |
1352 | ||
e95433c7 CW |
1353 | timeout = io_schedule_timeout(timeout); |
1354 | ||
754c9fd5 | 1355 | if (intel_wait_complete(&wait) && |
e61e0f51 | 1356 | intel_wait_check_request(&wait, rq)) |
05235c53 CW |
1357 | break; |
1358 | ||
1359 | set_current_state(state); | |
1360 | ||
1361 | wakeup: | |
e61e0f51 CW |
1362 | /* |
1363 | * Carefully check if the request is complete, giving time | |
05235c53 CW |
1364 | * for the seqno to be visible following the interrupt. |
1365 | * We also have to check in case we are kicked by the GPU | |
1366 | * reset in order to drop the struct_mutex. | |
1367 | */ | |
e61e0f51 | 1368 | if (__i915_request_irq_complete(rq)) |
05235c53 CW |
1369 | break; |
1370 | ||
e61e0f51 CW |
1371 | /* |
1372 | * If the GPU is hung, and we hold the lock, reset the GPU | |
221fe799 CW |
1373 | * and then check for completion. On a full reset, the engine's |
1374 | * HW seqno will be advanced passed us and we are complete. | |
1375 | * If we do a partial reset, we have to wait for the GPU to | |
1376 | * resume and update the breadcrumb. | |
1377 | * | |
1378 | * If we don't hold the mutex, we can just wait for the worker | |
1379 | * to come along and update the breadcrumb (either directly | |
1380 | * itself, or indirectly by recovering the GPU). | |
1381 | */ | |
1382 | if (flags & I915_WAIT_LOCKED && | |
e61e0f51 | 1383 | __i915_wait_request_check_and_reset(rq)) |
221fe799 | 1384 | continue; |
221fe799 | 1385 | |
05235c53 | 1386 | /* Only spin if we know the GPU is processing this request */ |
e61e0f51 | 1387 | if (__i915_spin_request(rq, wait.seqno, state, 2)) |
05235c53 | 1388 | break; |
d6a2289d | 1389 | |
e61e0f51 CW |
1390 | if (!intel_wait_check_request(&wait, rq)) { |
1391 | intel_engine_remove_wait(rq->engine, &wait); | |
d6a2289d CW |
1392 | goto restart; |
1393 | } | |
05235c53 | 1394 | } |
05235c53 | 1395 | |
e61e0f51 | 1396 | intel_engine_remove_wait(rq->engine, &wait); |
05235c53 | 1397 | complete: |
a49625f9 | 1398 | __set_current_state(TASK_RUNNING); |
7de53bf7 CW |
1399 | if (flags & I915_WAIT_LOCKED) |
1400 | remove_wait_queue(errq, &reset); | |
e61e0f51 CW |
1401 | remove_wait_queue(&rq->execute, &exec); |
1402 | trace_i915_request_wait_end(rq); | |
05235c53 | 1403 | |
e95433c7 | 1404 | return timeout; |
05235c53 | 1405 | } |
4b8de8e6 | 1406 | |
b887d615 | 1407 | static void ring_retire_requests(struct intel_ring *ring) |
4b8de8e6 | 1408 | { |
e61e0f51 | 1409 | struct i915_request *request, *next; |
4b8de8e6 | 1410 | |
73cb9701 | 1411 | list_for_each_entry_safe(request, next, |
b887d615 CW |
1412 | &ring->request_list, ring_link) { |
1413 | if (!i915_request_completed(request)) | |
754c9fd5 | 1414 | break; |
4b8de8e6 | 1415 | |
e61e0f51 | 1416 | i915_request_retire(request); |
b887d615 | 1417 | } |
4b8de8e6 CW |
1418 | } |
1419 | ||
e61e0f51 | 1420 | void i915_retire_requests(struct drm_i915_private *i915) |
4b8de8e6 | 1421 | { |
643b450a | 1422 | struct intel_ring *ring, *tmp; |
4b8de8e6 | 1423 | |
e61e0f51 | 1424 | lockdep_assert_held(&i915->drm.struct_mutex); |
4b8de8e6 | 1425 | |
e61e0f51 | 1426 | if (!i915->gt.active_requests) |
4b8de8e6 CW |
1427 | return; |
1428 | ||
643b450a | 1429 | list_for_each_entry_safe(ring, tmp, &i915->gt.active_rings, active_link) |
b887d615 | 1430 | ring_retire_requests(ring); |
4b8de8e6 | 1431 | } |
c835c550 CW |
1432 | |
1433 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
1434 | #include "selftests/mock_request.c" | |
e61e0f51 | 1435 | #include "selftests/i915_request.c" |
c835c550 | 1436 | #endif |