Commit | Line | Data |
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05235c53 CW |
1 | /* |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
b52992c0 | 25 | #include <linux/dma-fence-array.h> |
3136deb7 | 26 | #include <linux/dma-fence-chain.h> |
e8861964 CW |
27 | #include <linux/irq_work.h> |
28 | #include <linux/prefetch.h> | |
e6017571 IM |
29 | #include <linux/sched.h> |
30 | #include <linux/sched/clock.h> | |
f361bf4a | 31 | #include <linux/sched/signal.h> |
8581fd40 | 32 | #include <linux/sched/mm.h> |
fa545cbf | 33 | |
10be98a7 | 34 | #include "gem/i915_gem_context.h" |
b3786b29 | 35 | #include "gt/intel_breadcrumbs.h" |
10be98a7 | 36 | #include "gt/intel_context.h" |
38b237ea CW |
37 | #include "gt/intel_engine.h" |
38 | #include "gt/intel_engine_heartbeat.h" | |
202b1f4c | 39 | #include "gt/intel_engine_regs.h" |
45233ab2 | 40 | #include "gt/intel_gpu_commands.h" |
38b237ea | 41 | #include "gt/intel_reset.h" |
2871ea85 | 42 | #include "gt/intel_ring.h" |
3e7abf81 | 43 | #include "gt/intel_rps.h" |
10be98a7 | 44 | |
21950ee7 | 45 | #include "i915_active.h" |
ff1e93e9 | 46 | #include "i915_config.h" |
63cf4cad | 47 | #include "i915_deps.h" |
24524e3f | 48 | #include "i915_driver.h" |
696173b0 | 49 | #include "i915_drv.h" |
a09d9a80 | 50 | #include "i915_trace.h" |
05235c53 | 51 | |
e8861964 | 52 | struct execute_cb { |
e8861964 CW |
53 | struct irq_work work; |
54 | struct i915_sw_fence *fence; | |
f71e01a7 | 55 | struct i915_request *signal; |
e8861964 CW |
56 | }; |
57 | ||
47514ac7 DV |
58 | static struct kmem_cache *slab_requests; |
59 | static struct kmem_cache *slab_execute_cbs; | |
32eb6bcf | 60 | |
f54d1867 | 61 | static const char *i915_fence_get_driver_name(struct dma_fence *fence) |
04769652 | 62 | { |
7307e91b | 63 | return dev_name(to_request(fence)->i915->drm.dev); |
04769652 CW |
64 | } |
65 | ||
f54d1867 | 66 | static const char *i915_fence_get_timeline_name(struct dma_fence *fence) |
04769652 | 67 | { |
9f3ccd40 CW |
68 | const struct i915_gem_context *ctx; |
69 | ||
e61e0f51 CW |
70 | /* |
71 | * The timeline struct (as part of the ppgtt underneath a context) | |
05506b5b CW |
72 | * may be freed when the request is no longer in use by the GPU. |
73 | * We could extend the life of a context to beyond that of all | |
74 | * fences, possibly keeping the hw resource around indefinitely, | |
75 | * or we just give them a false name. Since | |
76 | * dma_fence_ops.get_timeline_name is a debug feature, the occasional | |
77 | * lie seems justifiable. | |
78 | */ | |
79 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
80 | return "signaled"; | |
81 | ||
6a8679c0 | 82 | ctx = i915_request_gem_context(to_request(fence)); |
9f3ccd40 CW |
83 | if (!ctx) |
84 | return "[" DRIVER_NAME "]"; | |
85 | ||
86 | return ctx->name; | |
04769652 CW |
87 | } |
88 | ||
f54d1867 | 89 | static bool i915_fence_signaled(struct dma_fence *fence) |
04769652 | 90 | { |
e61e0f51 | 91 | return i915_request_completed(to_request(fence)); |
04769652 CW |
92 | } |
93 | ||
f54d1867 | 94 | static bool i915_fence_enable_signaling(struct dma_fence *fence) |
04769652 | 95 | { |
52c0fdb2 | 96 | return i915_request_enable_breadcrumb(to_request(fence)); |
04769652 CW |
97 | } |
98 | ||
f54d1867 | 99 | static signed long i915_fence_wait(struct dma_fence *fence, |
04769652 | 100 | bool interruptible, |
e95433c7 | 101 | signed long timeout) |
04769652 | 102 | { |
7e2e69ed ML |
103 | return i915_request_wait_timeout(to_request(fence), |
104 | interruptible | I915_WAIT_PRIORITY, | |
105 | timeout); | |
04769652 CW |
106 | } |
107 | ||
43acd651 CW |
108 | struct kmem_cache *i915_request_slab_cache(void) |
109 | { | |
47514ac7 | 110 | return slab_requests; |
43acd651 CW |
111 | } |
112 | ||
f54d1867 | 113 | static void i915_fence_release(struct dma_fence *fence) |
04769652 | 114 | { |
e61e0f51 | 115 | struct i915_request *rq = to_request(fence); |
04769652 | 116 | |
ee242ca7 MB |
117 | GEM_BUG_ON(rq->guc_prio != GUC_PRIO_INIT && |
118 | rq->guc_prio != GUC_PRIO_FINI); | |
119 | ||
ff20afc4 | 120 | i915_request_free_capture_list(fetch_and_zero(&rq->capture_list)); |
60dc43d1 TH |
121 | if (rq->batch_res) { |
122 | i915_vma_resource_put(rq->batch_res); | |
123 | rq->batch_res = NULL; | |
124 | } | |
ff20afc4 | 125 | |
e61e0f51 CW |
126 | /* |
127 | * The request is put onto a RCU freelist (i.e. the address | |
fc158405 CW |
128 | * is immediately reused), mark the fences as being freed now. |
129 | * Otherwise the debugobjects for the fences are only marked as | |
130 | * freed when the slab cache itself is freed, and so we would get | |
131 | * caught trying to reuse dead objects. | |
132 | */ | |
e61e0f51 | 133 | i915_sw_fence_fini(&rq->submit); |
0c441cb6 | 134 | i915_sw_fence_fini(&rq->semaphore); |
fc158405 | 135 | |
32a4605b | 136 | /* |
5eefc530 | 137 | * Keep one request on each engine for reserved use under mempressure. |
bcb9aa45 NV |
138 | * |
139 | * We do not hold a reference to the engine here and so have to be | |
140 | * very careful in what rq->engine we poke. The virtual engine is | |
141 | * referenced via the rq->context and we released that ref during | |
142 | * i915_request_retire(), ergo we must not dereference a virtual | |
143 | * engine here. Not that we would want to, as the only consumer of | |
144 | * the reserved engine->request_pool is the power management parking, | |
145 | * which must-not-fail, and that is only run on the physical engines. | |
146 | * | |
147 | * Since the request must have been executed to be have completed, | |
148 | * we know that it will have been processed by the HW and will | |
149 | * not be unsubmitted again, so rq->engine and rq->execution_mask | |
150 | * at this point is stable. rq->execution_mask will be a single | |
151 | * bit if the last and _only_ engine it could execution on was a | |
152 | * physical engine, if it's multiple bits then it started on and | |
153 | * could still be on a virtual engine. Thus if the mask is not a | |
154 | * power-of-two we assume that rq->engine may still be a virtual | |
155 | * engine and so a dangling invalid pointer that we cannot dereference | |
156 | * | |
157 | * For example, consider the flow of a bonded request through a virtual | |
158 | * engine. The request is created with a wide engine mask (all engines | |
159 | * that we might execute on). On processing the bond, the request mask | |
160 | * is reduced to one or more engines. If the request is subsequently | |
161 | * bound to a single engine, it will then be constrained to only | |
162 | * execute on that engine and never returned to the virtual engine | |
163 | * after timeslicing away, see __unwind_incomplete_requests(). Thus we | |
164 | * know that if the rq->execution_mask is a single bit, rq->engine | |
165 | * can be a physical engine with the exact corresponding mask. | |
32a4605b | 166 | */ |
5eefc530 | 167 | if (is_power_of_2(rq->execution_mask) && |
bcb9aa45 | 168 | !cmpxchg(&rq->engine->request_pool, NULL, rq)) |
43acd651 CW |
169 | return; |
170 | ||
47514ac7 | 171 | kmem_cache_free(slab_requests, rq); |
04769652 CW |
172 | } |
173 | ||
f54d1867 | 174 | const struct dma_fence_ops i915_fence_ops = { |
04769652 CW |
175 | .get_driver_name = i915_fence_get_driver_name, |
176 | .get_timeline_name = i915_fence_get_timeline_name, | |
177 | .enable_signaling = i915_fence_enable_signaling, | |
178 | .signaled = i915_fence_signaled, | |
179 | .wait = i915_fence_wait, | |
180 | .release = i915_fence_release, | |
04769652 CW |
181 | }; |
182 | ||
b87b6c0d CW |
183 | static void irq_execute_cb(struct irq_work *wrk) |
184 | { | |
185 | struct execute_cb *cb = container_of(wrk, typeof(*cb), work); | |
186 | ||
187 | i915_sw_fence_complete(cb->fence); | |
47514ac7 | 188 | kmem_cache_free(slab_execute_cbs, cb); |
b87b6c0d CW |
189 | } |
190 | ||
2e4c6c1a CW |
191 | static __always_inline void |
192 | __notify_execute_cb(struct i915_request *rq, bool (*fn)(struct irq_work *wrk)) | |
b87b6c0d | 193 | { |
fc0e1270 | 194 | struct execute_cb *cb, *cn; |
b87b6c0d | 195 | |
fc0e1270 | 196 | if (llist_empty(&rq->execute_cb)) |
b87b6c0d CW |
197 | return; |
198 | ||
2e4c6c1a CW |
199 | llist_for_each_entry_safe(cb, cn, |
200 | llist_del_all(&rq->execute_cb), | |
7a9f50a0 | 201 | work.node.llist) |
2e4c6c1a CW |
202 | fn(&cb->work); |
203 | } | |
b87b6c0d | 204 | |
2e4c6c1a CW |
205 | static void __notify_execute_cb_irq(struct i915_request *rq) |
206 | { | |
207 | __notify_execute_cb(rq, irq_work_queue); | |
208 | } | |
209 | ||
210 | static bool irq_work_imm(struct irq_work *wrk) | |
211 | { | |
212 | wrk->func(wrk); | |
213 | return false; | |
214 | } | |
215 | ||
d1cee2d3 | 216 | void i915_request_notify_execute_cb_imm(struct i915_request *rq) |
2e4c6c1a CW |
217 | { |
218 | __notify_execute_cb(rq, irq_work_imm); | |
b87b6c0d CW |
219 | } |
220 | ||
89dd019a CW |
221 | static void __i915_request_fill(struct i915_request *rq, u8 val) |
222 | { | |
223 | void *vaddr = rq->ring->vaddr; | |
224 | u32 head; | |
225 | ||
226 | head = rq->infix; | |
227 | if (rq->postfix < head) { | |
228 | memset(vaddr + head, val, rq->ring->size - head); | |
229 | head = 0; | |
230 | } | |
231 | memset(vaddr + head, val, rq->postfix - head); | |
232 | } | |
233 | ||
7dbc19da TU |
234 | /** |
235 | * i915_request_active_engine | |
236 | * @rq: request to inspect | |
237 | * @active: pointer in which to return the active engine | |
238 | * | |
239 | * Fills the currently active engine to the @active pointer if the request | |
240 | * is active and still not completed. | |
241 | * | |
242 | * Returns true if request was active or false otherwise. | |
243 | */ | |
244 | bool | |
245 | i915_request_active_engine(struct i915_request *rq, | |
246 | struct intel_engine_cs **active) | |
247 | { | |
248 | struct intel_engine_cs *engine, *locked; | |
249 | bool ret = false; | |
250 | ||
251 | /* | |
252 | * Serialise with __i915_request_submit() so that it sees | |
253 | * is-banned?, or we know the request is already inflight. | |
254 | * | |
255 | * Note that rq->engine is unstable, and so we double | |
256 | * check that we have acquired the lock on the final engine. | |
257 | */ | |
258 | locked = READ_ONCE(rq->engine); | |
349a2bc5 | 259 | spin_lock_irq(&locked->sched_engine->lock); |
7dbc19da | 260 | while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) { |
349a2bc5 | 261 | spin_unlock(&locked->sched_engine->lock); |
7dbc19da | 262 | locked = engine; |
349a2bc5 | 263 | spin_lock(&locked->sched_engine->lock); |
7dbc19da TU |
264 | } |
265 | ||
266 | if (i915_request_is_active(rq)) { | |
267 | if (!__i915_request_is_complete(rq)) | |
268 | *active = locked; | |
269 | ret = true; | |
270 | } | |
271 | ||
349a2bc5 | 272 | spin_unlock_irq(&locked->sched_engine->lock); |
7dbc19da TU |
273 | |
274 | return ret; | |
275 | } | |
276 | ||
9b4d0598 TU |
277 | static void __rq_init_watchdog(struct i915_request *rq) |
278 | { | |
279 | rq->watchdog.timer.function = NULL; | |
280 | } | |
281 | ||
282 | static enum hrtimer_restart __rq_watchdog_expired(struct hrtimer *hrtimer) | |
283 | { | |
284 | struct i915_request *rq = | |
285 | container_of(hrtimer, struct i915_request, watchdog.timer); | |
286 | struct intel_gt *gt = rq->engine->gt; | |
287 | ||
288 | if (!i915_request_completed(rq)) { | |
289 | if (llist_add(&rq->watchdog.link, >->watchdog.list)) | |
848a4e5c | 290 | queue_work(gt->i915->unordered_wq, >->watchdog.work); |
9b4d0598 TU |
291 | } else { |
292 | i915_request_put(rq); | |
293 | } | |
294 | ||
295 | return HRTIMER_NORESTART; | |
296 | } | |
297 | ||
298 | static void __rq_arm_watchdog(struct i915_request *rq) | |
299 | { | |
300 | struct i915_request_watchdog *wdg = &rq->watchdog; | |
301 | struct intel_context *ce = rq->context; | |
302 | ||
303 | if (!ce->watchdog.timeout_us) | |
304 | return; | |
305 | ||
f7c37977 TU |
306 | i915_request_get(rq); |
307 | ||
9b4d0598 TU |
308 | hrtimer_init(&wdg->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); |
309 | wdg->timer.function = __rq_watchdog_expired; | |
310 | hrtimer_start_range_ns(&wdg->timer, | |
311 | ns_to_ktime(ce->watchdog.timeout_us * | |
312 | NSEC_PER_USEC), | |
313 | NSEC_PER_MSEC, | |
314 | HRTIMER_MODE_REL); | |
9b4d0598 TU |
315 | } |
316 | ||
317 | static void __rq_cancel_watchdog(struct i915_request *rq) | |
318 | { | |
319 | struct i915_request_watchdog *wdg = &rq->watchdog; | |
320 | ||
321 | if (wdg->timer.function && hrtimer_try_to_cancel(&wdg->timer) > 0) | |
322 | i915_request_put(rq); | |
323 | } | |
324 | ||
ff20afc4 TH |
325 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
326 | ||
327 | /** | |
328 | * i915_request_free_capture_list - Free a capture list | |
329 | * @capture: Pointer to the first list item or NULL | |
330 | * | |
331 | */ | |
332 | void i915_request_free_capture_list(struct i915_capture_list *capture) | |
333 | { | |
334 | while (capture) { | |
335 | struct i915_capture_list *next = capture->next; | |
336 | ||
60dc43d1 | 337 | i915_vma_resource_put(capture->vma_res); |
40aa583e | 338 | kfree(capture); |
ff20afc4 TH |
339 | capture = next; |
340 | } | |
341 | } | |
342 | ||
343 | #define assert_capture_list_is_null(_rq) GEM_BUG_ON((_rq)->capture_list) | |
344 | ||
345 | #define clear_capture_list(_rq) ((_rq)->capture_list = NULL) | |
346 | ||
347 | #else | |
348 | ||
349 | #define i915_request_free_capture_list(_a) do {} while (0) | |
350 | ||
351 | #define assert_capture_list_is_null(_a) do {} while (0) | |
352 | ||
353 | #define clear_capture_list(_rq) do {} while (0) | |
354 | ||
355 | #endif | |
356 | ||
66101975 | 357 | bool i915_request_retire(struct i915_request *rq) |
05235c53 | 358 | { |
163433e5 | 359 | if (!__i915_request_is_complete(rq)) |
9db0c5ca | 360 | return false; |
d9b13c4d | 361 | |
639f2f24 | 362 | RQ_TRACE(rq, "\n"); |
4c7d62c6 | 363 | |
9db0c5ca CW |
364 | GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); |
365 | trace_i915_request_retire(rq); | |
2e4c6c1a | 366 | i915_request_mark_complete(rq); |
80b204bc | 367 | |
9b4d0598 TU |
368 | __rq_cancel_watchdog(rq); |
369 | ||
e5dadff4 CW |
370 | /* |
371 | * We know the GPU must have read the request to have | |
372 | * sent us the seqno + interrupt, so use the position | |
373 | * of tail of the request to update the last known position | |
374 | * of the GPU head. | |
375 | * | |
376 | * Note this requires that we are always called in request | |
377 | * completion order. | |
378 | */ | |
d19d71fc CW |
379 | GEM_BUG_ON(!list_is_first(&rq->link, |
380 | &i915_request_timeline(rq)->requests)); | |
89dd019a CW |
381 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) |
382 | /* Poison before we release our space in the ring */ | |
383 | __i915_request_fill(rq, POISON_FREE); | |
e5dadff4 | 384 | rq->ring->head = rq->postfix; |
b0fd47ad | 385 | |
e2300560 CW |
386 | if (!i915_request_signaled(rq)) { |
387 | spin_lock_irq(&rq->lock); | |
9db0c5ca | 388 | dma_fence_signal_locked(&rq->fence); |
e2300560 CW |
389 | spin_unlock_irq(&rq->lock); |
390 | } | |
c18636f7 | 391 | |
4e5c8a99 | 392 | if (test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags)) |
493043fe | 393 | intel_rps_dec_waiters(&rq->engine->gt->rps); |
c18636f7 CW |
394 | |
395 | /* | |
396 | * We only loosely track inflight requests across preemption, | |
397 | * and so we may find ourselves attempting to retire a _completed_ | |
398 | * request that we have removed from the HW and put back on a run | |
399 | * queue. | |
400 | * | |
401 | * As we set I915_FENCE_FLAG_ACTIVE on the request, this should be | |
402 | * after removing the breadcrumb and signaling it, so that we do not | |
403 | * inadvertently attach the breadcrumb to a completed request. | |
404 | */ | |
d1cee2d3 | 405 | rq->engine->remove_active_request(rq); |
fc0e1270 | 406 | GEM_BUG_ON(!llist_empty(&rq->execute_cb)); |
52d7f16e | 407 | |
dff2a11b | 408 | __list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */ |
9db0c5ca | 409 | |
9f3ccd40 CW |
410 | intel_context_exit(rq->context); |
411 | intel_context_unpin(rq->context); | |
75d0a7f3 | 412 | |
9db0c5ca CW |
413 | i915_sched_node_fini(&rq->sched); |
414 | i915_request_put(rq); | |
415 | ||
416 | return true; | |
05235c53 CW |
417 | } |
418 | ||
e61e0f51 | 419 | void i915_request_retire_upto(struct i915_request *rq) |
05235c53 | 420 | { |
d19d71fc | 421 | struct intel_timeline * const tl = i915_request_timeline(rq); |
e61e0f51 | 422 | struct i915_request *tmp; |
05235c53 | 423 | |
639f2f24 | 424 | RQ_TRACE(rq, "\n"); |
163433e5 | 425 | GEM_BUG_ON(!__i915_request_is_complete(rq)); |
4ffd6e0c | 426 | |
05235c53 | 427 | do { |
e5dadff4 | 428 | tmp = list_first_entry(&tl->requests, typeof(*tmp), link); |
38d5ec43 | 429 | GEM_BUG_ON(!i915_request_completed(tmp)); |
9db0c5ca | 430 | } while (i915_request_retire(tmp) && tmp != rq); |
05235c53 CW |
431 | } |
432 | ||
b55230e5 CW |
433 | static struct i915_request * const * |
434 | __engine_active(struct intel_engine_cs *engine) | |
435 | { | |
436 | return READ_ONCE(engine->execlists.active); | |
437 | } | |
438 | ||
439 | static bool __request_in_flight(const struct i915_request *signal) | |
440 | { | |
441 | struct i915_request * const *port, *rq; | |
442 | bool inflight = false; | |
443 | ||
444 | if (!i915_request_is_ready(signal)) | |
445 | return false; | |
446 | ||
447 | /* | |
448 | * Even if we have unwound the request, it may still be on | |
449 | * the GPU (preempt-to-busy). If that request is inside an | |
450 | * unpreemptible critical section, it will not be removed. Some | |
451 | * GPU functions may even be stuck waiting for the paired request | |
452 | * (__await_execution) to be submitted and cannot be preempted | |
453 | * until the bond is executing. | |
454 | * | |
455 | * As we know that there are always preemption points between | |
456 | * requests, we know that only the currently executing request | |
457 | * may be still active even though we have cleared the flag. | |
b4d9145b | 458 | * However, we can't rely on our tracking of ELSP[0] to know |
b55230e5 CW |
459 | * which request is currently active and so maybe stuck, as |
460 | * the tracking maybe an event behind. Instead assume that | |
461 | * if the context is still inflight, then it is still active | |
462 | * even if the active flag has been cleared. | |
b4d9145b CW |
463 | * |
464 | * To further complicate matters, if there a pending promotion, the HW | |
465 | * may either perform a context switch to the second inflight execlists, | |
466 | * or it may switch to the pending set of execlists. In the case of the | |
467 | * latter, it may send the ACK and we process the event copying the | |
468 | * pending[] over top of inflight[], _overwriting_ our *active. Since | |
469 | * this implies the HW is arbitrating and not struck in *active, we do | |
470 | * not worry about complete accuracy, but we do require no read/write | |
471 | * tearing of the pointer [the read of the pointer must be valid, even | |
472 | * as the array is being overwritten, for which we require the writes | |
473 | * to avoid tearing.] | |
474 | * | |
475 | * Note that the read of *execlists->active may race with the promotion | |
476 | * of execlists->pending[] to execlists->inflight[], overwritting | |
477 | * the value at *execlists->active. This is fine. The promotion implies | |
478 | * that we received an ACK from the HW, and so the context is not | |
479 | * stuck -- if we do not see ourselves in *active, the inflight status | |
480 | * is valid. If instead we see ourselves being copied into *active, | |
481 | * we are inflight and may signal the callback. | |
b55230e5 CW |
482 | */ |
483 | if (!intel_context_inflight(signal->context)) | |
484 | return false; | |
485 | ||
486 | rcu_read_lock(); | |
b4d9145b CW |
487 | for (port = __engine_active(signal->engine); |
488 | (rq = READ_ONCE(*port)); /* may race with promotion of pending[] */ | |
489 | port++) { | |
b55230e5 CW |
490 | if (rq->context == signal->context) { |
491 | inflight = i915_seqno_passed(rq->fence.seqno, | |
492 | signal->fence.seqno); | |
493 | break; | |
494 | } | |
495 | } | |
496 | rcu_read_unlock(); | |
497 | ||
498 | return inflight; | |
499 | } | |
500 | ||
e8861964 | 501 | static int |
c81471f5 CW |
502 | __await_execution(struct i915_request *rq, |
503 | struct i915_request *signal, | |
c81471f5 | 504 | gfp_t gfp) |
e8861964 CW |
505 | { |
506 | struct execute_cb *cb; | |
507 | ||
5ac545b8 | 508 | if (i915_request_is_active(signal)) |
e8861964 CW |
509 | return 0; |
510 | ||
47514ac7 | 511 | cb = kmem_cache_alloc(slab_execute_cbs, gfp); |
e8861964 CW |
512 | if (!cb) |
513 | return -ENOMEM; | |
514 | ||
515 | cb->fence = &rq->submit; | |
516 | i915_sw_fence_await(cb->fence); | |
517 | init_irq_work(&cb->work, irq_execute_cb); | |
518 | ||
2e4c6c1a CW |
519 | /* |
520 | * Register the callback first, then see if the signaler is already | |
521 | * active. This ensures that if we race with the | |
522 | * __notify_execute_cb from i915_request_submit() and we are not | |
523 | * included in that list, we get a second bite of the cherry and | |
524 | * execute it ourselves. After this point, a future | |
525 | * i915_request_submit() will notify us. | |
526 | * | |
527 | * In i915_request_retire() we set the ACTIVE bit on a completed | |
528 | * request (then flush the execute_cb). So by registering the | |
529 | * callback first, then checking the ACTIVE bit, we serialise with | |
530 | * the completed/retired request. | |
531 | */ | |
7a9f50a0 | 532 | if (llist_add(&cb->work.node.llist, &signal->execute_cb)) { |
2e4c6c1a CW |
533 | if (i915_request_is_active(signal) || |
534 | __request_in_flight(signal)) | |
d1cee2d3 | 535 | i915_request_notify_execute_cb_imm(signal); |
e8861964 | 536 | } |
e8861964 CW |
537 | |
538 | return 0; | |
539 | } | |
540 | ||
36e191f0 CW |
541 | static bool fatal_error(int error) |
542 | { | |
543 | switch (error) { | |
544 | case 0: /* not an error! */ | |
545 | case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */ | |
546 | case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */ | |
547 | return false; | |
548 | default: | |
549 | return true; | |
550 | } | |
551 | } | |
552 | ||
553 | void __i915_request_skip(struct i915_request *rq) | |
554 | { | |
555 | GEM_BUG_ON(!fatal_error(rq->fence.error)); | |
556 | ||
557 | if (rq->infix == rq->postfix) | |
558 | return; | |
559 | ||
7904e081 CW |
560 | RQ_TRACE(rq, "error: %d\n", rq->fence.error); |
561 | ||
36e191f0 CW |
562 | /* |
563 | * As this request likely depends on state from the lost | |
564 | * context, clear out all the user operations leaving the | |
565 | * breadcrumb at the end (so we get the fence notifications). | |
566 | */ | |
567 | __i915_request_fill(rq, 0); | |
568 | rq->infix = rq->postfix; | |
569 | } | |
570 | ||
38b237ea | 571 | bool i915_request_set_error_once(struct i915_request *rq, int error) |
36e191f0 CW |
572 | { |
573 | int old; | |
574 | ||
575 | GEM_BUG_ON(!IS_ERR_VALUE((long)error)); | |
576 | ||
577 | if (i915_request_signaled(rq)) | |
38b237ea | 578 | return false; |
36e191f0 CW |
579 | |
580 | old = READ_ONCE(rq->fence.error); | |
581 | do { | |
582 | if (fatal_error(old)) | |
38b237ea | 583 | return false; |
36e191f0 | 584 | } while (!try_cmpxchg(&rq->fence.error, &old, error)); |
38b237ea CW |
585 | |
586 | return true; | |
36e191f0 CW |
587 | } |
588 | ||
c10e4a79 | 589 | struct i915_request *i915_request_mark_eio(struct i915_request *rq) |
baa7c2cd CW |
590 | { |
591 | if (__i915_request_is_complete(rq)) | |
c10e4a79 | 592 | return NULL; |
baa7c2cd CW |
593 | |
594 | GEM_BUG_ON(i915_request_signaled(rq)); | |
595 | ||
c10e4a79 CW |
596 | /* As soon as the request is completed, it may be retired */ |
597 | rq = i915_request_get(rq); | |
598 | ||
baa7c2cd CW |
599 | i915_request_set_error_once(rq, -EIO); |
600 | i915_request_mark_complete(rq); | |
c10e4a79 CW |
601 | |
602 | return rq; | |
baa7c2cd CW |
603 | } |
604 | ||
c0bb487d | 605 | bool __i915_request_submit(struct i915_request *request) |
5590af3e | 606 | { |
73cb9701 | 607 | struct intel_engine_cs *engine = request->engine; |
c0bb487d | 608 | bool result = false; |
5590af3e | 609 | |
639f2f24 | 610 | RQ_TRACE(request, "\n"); |
d9b13c4d | 611 | |
e60a870d | 612 | GEM_BUG_ON(!irqs_disabled()); |
349a2bc5 | 613 | lockdep_assert_held(&engine->sched_engine->lock); |
e60a870d | 614 | |
c0bb487d CW |
615 | /* |
616 | * With the advent of preempt-to-busy, we frequently encounter | |
617 | * requests that we have unsubmitted from HW, but left running | |
618 | * until the next ack and so have completed in the meantime. On | |
619 | * resubmission of that completed request, we can skip | |
620 | * updating the payload, and execlists can even skip submitting | |
621 | * the request. | |
622 | * | |
623 | * We must remove the request from the caller's priority queue, | |
624 | * and the caller must only call us when the request is in their | |
349a2bc5 | 625 | * priority queue, under the sched_engine->lock. This ensures that the |
c0bb487d CW |
626 | * request has *not* yet been retired and we can safely move |
627 | * the request into the engine->active.list where it will be | |
628 | * dropped upon retiring. (Otherwise if resubmit a *retired* | |
629 | * request, this would be a horrible use-after-free.) | |
630 | */ | |
9736387a CW |
631 | if (__i915_request_is_complete(request)) { |
632 | list_del_init(&request->sched.link); | |
633 | goto active; | |
634 | } | |
c0bb487d | 635 | |
45c64ecf | 636 | if (unlikely(!intel_context_is_schedulable(request->context))) |
36e191f0 | 637 | i915_request_set_error_once(request, -EIO); |
7d442ea7 | 638 | |
36e191f0 CW |
639 | if (unlikely(fatal_error(request->fence.error))) |
640 | __i915_request_skip(request); | |
d9e61b66 | 641 | |
ca6e56f6 CW |
642 | /* |
643 | * Are we using semaphores when the gpu is already saturated? | |
644 | * | |
645 | * Using semaphores incurs a cost in having the GPU poll a | |
646 | * memory location, busywaiting for it to change. The continual | |
647 | * memory reads can have a noticeable impact on the rest of the | |
648 | * system with the extra bus traffic, stalling the cpu as it too | |
649 | * tries to access memory across the bus (perf stat -e bus-cycles). | |
650 | * | |
651 | * If we installed a semaphore on this request and we only submit | |
652 | * the request after the signaler completed, that indicates the | |
653 | * system is overloaded and using semaphores at this time only | |
654 | * increases the amount of work we are doing. If so, we disable | |
655 | * further use of semaphores until we are idle again, whence we | |
656 | * optimistically try again. | |
657 | */ | |
658 | if (request->sched.semaphores && | |
659 | i915_sw_fence_signaled(&request->semaphore)) | |
44d89409 | 660 | engine->saturated |= request->sched.semaphores; |
ca6e56f6 | 661 | |
c0bb487d CW |
662 | engine->emit_fini_breadcrumb(request, |
663 | request->ring->vaddr + request->postfix); | |
b5773a36 | 664 | |
c0bb487d | 665 | trace_i915_request_execute(request); |
96d3e0e1 JH |
666 | if (engine->bump_serial) |
667 | engine->bump_serial(engine); | |
668 | else | |
669 | engine->serial++; | |
670 | ||
c0bb487d | 671 | result = true; |
422d7df4 | 672 | |
9736387a | 673 | GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)); |
d1cee2d3 | 674 | engine->add_active_request(request); |
9736387a CW |
675 | active: |
676 | clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags); | |
677 | set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags); | |
b5773a36 | 678 | |
c18636f7 CW |
679 | /* |
680 | * XXX Rollback bonded-execution on __i915_request_unsubmit()? | |
681 | * | |
682 | * In the future, perhaps when we have an active time-slicing scheduler, | |
683 | * it will be interesting to unsubmit parallel execution and remove | |
684 | * busywaits from the GPU until their master is restarted. This is | |
685 | * quite hairy, we have to carefully rollback the fence and do a | |
686 | * preempt-to-idle cycle on the target engine, all the while the | |
687 | * master execute_cb may refire. | |
688 | */ | |
2e4c6c1a CW |
689 | __notify_execute_cb_irq(request); |
690 | ||
691 | /* We may be recursing from the signal callback of another i915 fence */ | |
5701a66e CW |
692 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) |
693 | i915_request_enable_breadcrumb(request); | |
f2d13290 | 694 | |
c0bb487d | 695 | return result; |
d55ac5bf CW |
696 | } |
697 | ||
e61e0f51 | 698 | void i915_request_submit(struct i915_request *request) |
d55ac5bf CW |
699 | { |
700 | struct intel_engine_cs *engine = request->engine; | |
701 | unsigned long flags; | |
23902e49 | 702 | |
d55ac5bf | 703 | /* Will be called from irq-context when using foreign fences. */ |
349a2bc5 | 704 | spin_lock_irqsave(&engine->sched_engine->lock, flags); |
d55ac5bf | 705 | |
e61e0f51 | 706 | __i915_request_submit(request); |
d55ac5bf | 707 | |
349a2bc5 | 708 | spin_unlock_irqrestore(&engine->sched_engine->lock, flags); |
d55ac5bf CW |
709 | } |
710 | ||
e61e0f51 | 711 | void __i915_request_unsubmit(struct i915_request *request) |
d55ac5bf | 712 | { |
d6a2289d | 713 | struct intel_engine_cs *engine = request->engine; |
d55ac5bf | 714 | |
c18636f7 CW |
715 | /* |
716 | * Only unwind in reverse order, required so that the per-context list | |
717 | * is kept in seqno/ring order. | |
718 | */ | |
639f2f24 | 719 | RQ_TRACE(request, "\n"); |
d9b13c4d | 720 | |
e60a870d | 721 | GEM_BUG_ON(!irqs_disabled()); |
349a2bc5 | 722 | lockdep_assert_held(&engine->sched_engine->lock); |
48bc2a4a | 723 | |
e61e0f51 | 724 | /* |
c18636f7 CW |
725 | * Before we remove this breadcrumb from the signal list, we have |
726 | * to ensure that a concurrent dma_fence_enable_signaling() does not | |
727 | * attach itself. We first mark the request as no longer active and | |
728 | * make sure that is visible to other cores, and then remove the | |
729 | * breadcrumb if attached. | |
d6a2289d | 730 | */ |
c18636f7 CW |
731 | GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)); |
732 | clear_bit_unlock(I915_FENCE_FLAG_ACTIVE, &request->fence.flags); | |
d6a2289d | 733 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) |
52c0fdb2 | 734 | i915_request_cancel_breadcrumb(request); |
b5773a36 | 735 | |
dba5a7f3 | 736 | /* We've already spun, don't charge on resubmitting. */ |
163433e5 | 737 | if (request->sched.semaphores && __i915_request_has_started(request)) |
dba5a7f3 | 738 | request->sched.semaphores = 0; |
dba5a7f3 | 739 | |
e61e0f51 CW |
740 | /* |
741 | * We don't need to wake_up any waiters on request->execute, they | |
d6a2289d | 742 | * will get woken by any other event or us re-adding this request |
e61e0f51 | 743 | * to the engine timeline (__i915_request_submit()). The waiters |
d6a2289d CW |
744 | * should be quite adapt at finding that the request now has a new |
745 | * global_seqno to the one they went to sleep on. | |
746 | */ | |
747 | } | |
748 | ||
e61e0f51 | 749 | void i915_request_unsubmit(struct i915_request *request) |
d6a2289d CW |
750 | { |
751 | struct intel_engine_cs *engine = request->engine; | |
752 | unsigned long flags; | |
753 | ||
754 | /* Will be called from irq-context when using foreign fences. */ | |
349a2bc5 | 755 | spin_lock_irqsave(&engine->sched_engine->lock, flags); |
d6a2289d | 756 | |
e61e0f51 | 757 | __i915_request_unsubmit(request); |
d6a2289d | 758 | |
349a2bc5 | 759 | spin_unlock_irqrestore(&engine->sched_engine->lock, flags); |
5590af3e CW |
760 | } |
761 | ||
38b237ea CW |
762 | void i915_request_cancel(struct i915_request *rq, int error) |
763 | { | |
764 | if (!i915_request_set_error_once(rq, error)) | |
765 | return; | |
766 | ||
767 | set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags); | |
768 | ||
62eaf0ae | 769 | intel_context_cancel_request(rq->context, rq); |
38b237ea CW |
770 | } |
771 | ||
44505168 | 772 | static int |
d55ac5bf | 773 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
23902e49 | 774 | { |
e61e0f51 | 775 | struct i915_request *request = |
48bc2a4a | 776 | container_of(fence, typeof(*request), submit); |
48bc2a4a CW |
777 | |
778 | switch (state) { | |
779 | case FENCE_COMPLETE: | |
e61e0f51 | 780 | trace_i915_request_submit(request); |
ef468849 CW |
781 | |
782 | if (unlikely(fence->error)) | |
36e191f0 | 783 | i915_request_set_error_once(request, fence->error); |
9b4d0598 TU |
784 | else |
785 | __rq_arm_watchdog(request); | |
ef468849 | 786 | |
af7a8ffa | 787 | /* |
e61e0f51 CW |
788 | * We need to serialize use of the submit_request() callback |
789 | * with its hotplugging performed during an emergency | |
790 | * i915_gem_set_wedged(). We use the RCU mechanism to mark the | |
791 | * critical section in order to force i915_gem_set_wedged() to | |
792 | * wait until the submit_request() is completed before | |
793 | * proceeding. | |
af7a8ffa DV |
794 | */ |
795 | rcu_read_lock(); | |
d55ac5bf | 796 | request->engine->submit_request(request); |
af7a8ffa | 797 | rcu_read_unlock(); |
48bc2a4a CW |
798 | break; |
799 | ||
800 | case FENCE_FREE: | |
e61e0f51 | 801 | i915_request_put(request); |
48bc2a4a CW |
802 | break; |
803 | } | |
804 | ||
23902e49 CW |
805 | return NOTIFY_DONE; |
806 | } | |
807 | ||
44505168 | 808 | static int |
b7404c7e CW |
809 | semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
810 | { | |
209df10b | 811 | struct i915_request *rq = container_of(fence, typeof(*rq), semaphore); |
b7404c7e CW |
812 | |
813 | switch (state) { | |
814 | case FENCE_COMPLETE: | |
b7404c7e CW |
815 | break; |
816 | ||
817 | case FENCE_FREE: | |
209df10b | 818 | i915_request_put(rq); |
b7404c7e CW |
819 | break; |
820 | } | |
821 | ||
822 | return NOTIFY_DONE; | |
823 | } | |
824 | ||
e5dadff4 | 825 | static void retire_requests(struct intel_timeline *tl) |
d22ba0cb CW |
826 | { |
827 | struct i915_request *rq, *rn; | |
828 | ||
e5dadff4 | 829 | list_for_each_entry_safe(rq, rn, &tl->requests, link) |
9db0c5ca | 830 | if (!i915_request_retire(rq)) |
d22ba0cb | 831 | break; |
d22ba0cb CW |
832 | } |
833 | ||
834 | static noinline struct i915_request * | |
43acd651 CW |
835 | request_alloc_slow(struct intel_timeline *tl, |
836 | struct i915_request **rsvd, | |
837 | gfp_t gfp) | |
d22ba0cb | 838 | { |
d22ba0cb CW |
839 | struct i915_request *rq; |
840 | ||
43acd651 CW |
841 | /* If we cannot wait, dip into our reserves */ |
842 | if (!gfpflags_allow_blocking(gfp)) { | |
843 | rq = xchg(rsvd, NULL); | |
844 | if (!rq) /* Use the normal failure path for one final WARN */ | |
845 | goto out; | |
d22ba0cb | 846 | |
43acd651 CW |
847 | return rq; |
848 | } | |
849 | ||
850 | if (list_empty(&tl->requests)) | |
2ccdf6a1 CW |
851 | goto out; |
852 | ||
9db0c5ca | 853 | /* Move our oldest request to the slab-cache (if not in use!) */ |
e5dadff4 | 854 | rq = list_first_entry(&tl->requests, typeof(*rq), link); |
9db0c5ca CW |
855 | i915_request_retire(rq); |
856 | ||
47514ac7 | 857 | rq = kmem_cache_alloc(slab_requests, |
9db0c5ca CW |
858 | gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); |
859 | if (rq) | |
860 | return rq; | |
861 | ||
d22ba0cb | 862 | /* Ratelimit ourselves to prevent oom from malicious clients */ |
e5dadff4 | 863 | rq = list_last_entry(&tl->requests, typeof(*rq), link); |
d22ba0cb CW |
864 | cond_synchronize_rcu(rq->rcustate); |
865 | ||
866 | /* Retire our old requests in the hope that we free some */ | |
e5dadff4 | 867 | retire_requests(tl); |
d22ba0cb CW |
868 | |
869 | out: | |
47514ac7 | 870 | return kmem_cache_alloc(slab_requests, gfp); |
d22ba0cb CW |
871 | } |
872 | ||
67a3acaa CW |
873 | static void __i915_request_ctor(void *arg) |
874 | { | |
875 | struct i915_request *rq = arg; | |
876 | ||
877 | spin_lock_init(&rq->lock); | |
878 | i915_sched_node_init(&rq->sched); | |
879 | i915_sw_fence_init(&rq->submit, submit_notify); | |
880 | i915_sw_fence_init(&rq->semaphore, semaphore_notify); | |
881 | ||
ff20afc4 | 882 | clear_capture_list(rq); |
60dc43d1 | 883 | rq->batch_res = NULL; |
67a3acaa | 884 | |
fc0e1270 | 885 | init_llist_head(&rq->execute_cb); |
67a3acaa CW |
886 | } |
887 | ||
ff20afc4 TH |
888 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
889 | #define clear_batch_ptr(_rq) ((_rq)->batch = NULL) | |
890 | #else | |
891 | #define clear_batch_ptr(_a) do {} while (0) | |
892 | #endif | |
893 | ||
e61e0f51 | 894 | struct i915_request * |
2ccdf6a1 | 895 | __i915_request_create(struct intel_context *ce, gfp_t gfp) |
05235c53 | 896 | { |
75d0a7f3 | 897 | struct intel_timeline *tl = ce->timeline; |
ebece753 CW |
898 | struct i915_request *rq; |
899 | u32 seqno; | |
05235c53 CW |
900 | int ret; |
901 | ||
0333ec88 | 902 | might_alloc(gfp); |
28176ef4 | 903 | |
2ccdf6a1 CW |
904 | /* Check that the caller provided an already pinned context */ |
905 | __intel_context_pin(ce); | |
9b5f4e5e | 906 | |
e61e0f51 CW |
907 | /* |
908 | * Beware: Dragons be flying overhead. | |
5a198b8c CW |
909 | * |
910 | * We use RCU to look up requests in flight. The lookups may | |
911 | * race with the request being allocated from the slab freelist. | |
912 | * That is the request we are writing to here, may be in the process | |
21950ee7 | 913 | * of being read by __i915_active_request_get_rcu(). As such, |
5a198b8c CW |
914 | * we have to be very careful when overwriting the contents. During |
915 | * the RCU lookup, we change chase the request->engine pointer, | |
65e4760e | 916 | * read the request->global_seqno and increment the reference count. |
5a198b8c CW |
917 | * |
918 | * The reference count is incremented atomically. If it is zero, | |
919 | * the lookup knows the request is unallocated and complete. Otherwise, | |
920 | * it is either still in use, or has been reallocated and reset | |
f54d1867 CW |
921 | * with dma_fence_init(). This increment is safe for release as we |
922 | * check that the request we have a reference to and matches the active | |
5a198b8c CW |
923 | * request. |
924 | * | |
925 | * Before we increment the refcount, we chase the request->engine | |
926 | * pointer. We must not call kmem_cache_zalloc() or else we set | |
927 | * that pointer to NULL and cause a crash during the lookup. If | |
928 | * we see the request is completed (based on the value of the | |
929 | * old engine and seqno), the lookup is complete and reports NULL. | |
930 | * If we decide the request is not completed (new engine or seqno), | |
931 | * then we grab a reference and double check that it is still the | |
932 | * active request - which it won't be and restart the lookup. | |
933 | * | |
934 | * Do not use kmem_cache_zalloc() here! | |
935 | */ | |
47514ac7 | 936 | rq = kmem_cache_alloc(slab_requests, |
2ccdf6a1 | 937 | gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); |
e61e0f51 | 938 | if (unlikely(!rq)) { |
43acd651 | 939 | rq = request_alloc_slow(tl, &ce->engine->request_pool, gfp); |
e61e0f51 | 940 | if (!rq) { |
31c70f97 CW |
941 | ret = -ENOMEM; |
942 | goto err_unreserve; | |
943 | } | |
28176ef4 | 944 | } |
05235c53 | 945 | |
bcb9aa45 | 946 | rq->context = ce; |
2ccdf6a1 | 947 | rq->engine = ce->engine; |
1fc44d9b | 948 | rq->ring = ce->ring; |
89b6d183 | 949 | rq->execution_mask = ce->engine->mask; |
7307e91b | 950 | rq->i915 = ce->engine->i915; |
d19d71fc | 951 | |
855e39e6 CW |
952 | ret = intel_timeline_get_seqno(tl, rq, &seqno); |
953 | if (ret) | |
954 | goto err_free; | |
955 | ||
be988eae MA |
956 | dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, |
957 | tl->fence_context, seqno); | |
855e39e6 | 958 | |
85bedbf1 | 959 | RCU_INIT_POINTER(rq->timeline, tl); |
ebece753 | 960 | rq->hwsp_seqno = tl->hwsp_seqno; |
163433e5 | 961 | GEM_BUG_ON(__i915_request_is_complete(rq)); |
d19d71fc | 962 | |
ebece753 | 963 | rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */ |
73cb9701 | 964 | |
ee242ca7 MB |
965 | rq->guc_prio = GUC_PRIO_INIT; |
966 | ||
48bc2a4a | 967 | /* We bump the ref for the fence chain */ |
67a3acaa CW |
968 | i915_sw_fence_reinit(&i915_request_get(rq)->submit); |
969 | i915_sw_fence_reinit(&i915_request_get(rq)->semaphore); | |
5590af3e | 970 | |
67a3acaa | 971 | i915_sched_node_reinit(&rq->sched); |
52e54209 | 972 | |
67a3acaa | 973 | /* No zalloc, everything must be cleared after use */ |
ff20afc4 | 974 | clear_batch_ptr(rq); |
9b4d0598 | 975 | __rq_init_watchdog(rq); |
ff20afc4 | 976 | assert_capture_list_is_null(rq); |
fc0e1270 | 977 | GEM_BUG_ON(!llist_empty(&rq->execute_cb)); |
60dc43d1 | 978 | GEM_BUG_ON(rq->batch_res); |
2ccdf6a1 | 979 | |
05235c53 CW |
980 | /* |
981 | * Reserve space in the ring buffer for all the commands required to | |
982 | * eventually emit this request. This is to guarantee that the | |
e61e0f51 | 983 | * i915_request_add() call can't fail. Note that the reserve may need |
05235c53 CW |
984 | * to be redone if the request is not actually submitted straight |
985 | * away, e.g. because a GPU scheduler has deferred it. | |
ed2922c0 CW |
986 | * |
987 | * Note that due to how we add reserved_space to intel_ring_begin() | |
988 | * we need to double our request to ensure that if we need to wrap | |
989 | * around inside i915_request_add() there is sufficient space at | |
990 | * the beginning of the ring as well. | |
05235c53 | 991 | */ |
2ccdf6a1 CW |
992 | rq->reserved_space = |
993 | 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32); | |
05235c53 | 994 | |
2113184c CW |
995 | /* |
996 | * Record the position of the start of the request so that | |
d045446d CW |
997 | * should we detect the updated seqno part-way through the |
998 | * GPU processing the request, we never over-estimate the | |
999 | * position of the head. | |
1000 | */ | |
e61e0f51 | 1001 | rq->head = rq->ring->emit; |
d045446d | 1002 | |
2ccdf6a1 | 1003 | ret = rq->engine->request_alloc(rq); |
b1c24a61 CW |
1004 | if (ret) |
1005 | goto err_unwind; | |
2113184c | 1006 | |
b3ee09a4 CW |
1007 | rq->infix = rq->ring->emit; /* end of header; start of user payload */ |
1008 | ||
2ccdf6a1 | 1009 | intel_context_mark_active(ce); |
d22d2d07 CW |
1010 | list_add_tail_rcu(&rq->link, &tl->requests); |
1011 | ||
e61e0f51 | 1012 | return rq; |
05235c53 | 1013 | |
b1c24a61 | 1014 | err_unwind: |
1fc44d9b | 1015 | ce->ring->emit = rq->head; |
b1c24a61 | 1016 | |
1618bdb8 | 1017 | /* Make sure we didn't add ourselves to external state before freeing */ |
0c7112a0 CW |
1018 | GEM_BUG_ON(!list_empty(&rq->sched.signalers_list)); |
1019 | GEM_BUG_ON(!list_empty(&rq->sched.waiters_list)); | |
1618bdb8 | 1020 | |
ebece753 | 1021 | err_free: |
47514ac7 | 1022 | kmem_cache_free(slab_requests, rq); |
28176ef4 | 1023 | err_unreserve: |
1fc44d9b | 1024 | intel_context_unpin(ce); |
8e637178 | 1025 | return ERR_PTR(ret); |
05235c53 CW |
1026 | } |
1027 | ||
2ccdf6a1 CW |
1028 | struct i915_request * |
1029 | i915_request_create(struct intel_context *ce) | |
1030 | { | |
1031 | struct i915_request *rq; | |
e5dadff4 | 1032 | struct intel_timeline *tl; |
2ccdf6a1 | 1033 | |
e5dadff4 CW |
1034 | tl = intel_context_timeline_lock(ce); |
1035 | if (IS_ERR(tl)) | |
1036 | return ERR_CAST(tl); | |
2ccdf6a1 CW |
1037 | |
1038 | /* Move our oldest request to the slab-cache (if not in use!) */ | |
e5dadff4 CW |
1039 | rq = list_first_entry(&tl->requests, typeof(*rq), link); |
1040 | if (!list_is_last(&rq->link, &tl->requests)) | |
2ccdf6a1 CW |
1041 | i915_request_retire(rq); |
1042 | ||
1043 | intel_context_enter(ce); | |
1044 | rq = __i915_request_create(ce, GFP_KERNEL); | |
1045 | intel_context_exit(ce); /* active reference transferred to request */ | |
1046 | if (IS_ERR(rq)) | |
1047 | goto err_unlock; | |
1048 | ||
1049 | /* Check that we do not interrupt ourselves with a new request */ | |
e5dadff4 | 1050 | rq->cookie = lockdep_pin_lock(&tl->mutex); |
2ccdf6a1 CW |
1051 | |
1052 | return rq; | |
1053 | ||
1054 | err_unlock: | |
e5dadff4 | 1055 | intel_context_timeline_unlock(tl); |
2ccdf6a1 CW |
1056 | return rq; |
1057 | } | |
1058 | ||
0d90ccb7 CW |
1059 | static int |
1060 | i915_request_await_start(struct i915_request *rq, struct i915_request *signal) | |
1061 | { | |
6a79d848 CW |
1062 | struct dma_fence *fence; |
1063 | int err; | |
0d90ccb7 | 1064 | |
ab7a6902 CW |
1065 | if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline)) |
1066 | return 0; | |
6a79d848 | 1067 | |
d22d2d07 CW |
1068 | if (i915_request_started(signal)) |
1069 | return 0; | |
1070 | ||
b2fe00bb CW |
1071 | /* |
1072 | * The caller holds a reference on @signal, but we do not serialise | |
1073 | * against it being retired and removed from the lists. | |
1074 | * | |
1075 | * We do not hold a reference to the request before @signal, and | |
1076 | * so must be very careful to ensure that it is not _recycled_ as | |
1077 | * we follow the link backwards. | |
1078 | */ | |
9ddc8ec0 | 1079 | fence = NULL; |
6a79d848 | 1080 | rcu_read_lock(); |
d22d2d07 CW |
1081 | do { |
1082 | struct list_head *pos = READ_ONCE(signal->link.prev); | |
1083 | struct i915_request *prev; | |
1084 | ||
1085 | /* Confirm signal has not been retired, the link is valid */ | |
163433e5 | 1086 | if (unlikely(__i915_request_has_started(signal))) |
d22d2d07 CW |
1087 | break; |
1088 | ||
1089 | /* Is signal the earliest request on its timeline? */ | |
1090 | if (pos == &rcu_dereference(signal->timeline)->requests) | |
1091 | break; | |
0d90ccb7 | 1092 | |
9ddc8ec0 CW |
1093 | /* |
1094 | * Peek at the request before us in the timeline. That | |
1095 | * request will only be valid before it is retired, so | |
1096 | * after acquiring a reference to it, confirm that it is | |
1097 | * still part of the signaler's timeline. | |
1098 | */ | |
d22d2d07 CW |
1099 | prev = list_entry(pos, typeof(*prev), link); |
1100 | if (!i915_request_get_rcu(prev)) | |
1101 | break; | |
1102 | ||
1103 | /* After the strong barrier, confirm prev is still attached */ | |
1104 | if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) { | |
1105 | i915_request_put(prev); | |
1106 | break; | |
6a79d848 | 1107 | } |
d22d2d07 CW |
1108 | |
1109 | fence = &prev->fence; | |
1110 | } while (0); | |
9ddc8ec0 CW |
1111 | rcu_read_unlock(); |
1112 | if (!fence) | |
1113 | return 0; | |
6a79d848 CW |
1114 | |
1115 | err = 0; | |
07e9c59d | 1116 | if (!intel_timeline_sync_is_later(i915_request_timeline(rq), fence)) |
6a79d848 CW |
1117 | err = i915_sw_fence_await_dma_fence(&rq->submit, |
1118 | fence, 0, | |
1119 | I915_FENCE_GFP); | |
1120 | dma_fence_put(fence); | |
1121 | ||
1122 | return err; | |
0d90ccb7 CW |
1123 | } |
1124 | ||
ca6e56f6 CW |
1125 | static intel_engine_mask_t |
1126 | already_busywaiting(struct i915_request *rq) | |
1127 | { | |
1128 | /* | |
1129 | * Polling a semaphore causes bus traffic, delaying other users of | |
1130 | * both the GPU and CPU. We want to limit the impact on others, | |
1131 | * while taking advantage of early submission to reduce GPU | |
1132 | * latency. Therefore we restrict ourselves to not using more | |
1133 | * than one semaphore from each source, and not using a semaphore | |
1134 | * if we have detected the engine is saturated (i.e. would not be | |
1135 | * submitted early and cause bus traffic reading an already passed | |
1136 | * semaphore). | |
1137 | * | |
1138 | * See the are-we-too-late? check in __i915_request_submit(). | |
1139 | */ | |
60900add | 1140 | return rq->sched.semaphores | READ_ONCE(rq->engine->saturated); |
ca6e56f6 CW |
1141 | } |
1142 | ||
e8861964 | 1143 | static int |
c81471f5 CW |
1144 | __emit_semaphore_wait(struct i915_request *to, |
1145 | struct i915_request *from, | |
1146 | u32 seqno) | |
e8861964 | 1147 | { |
651e7d48 | 1148 | const int has_token = GRAPHICS_VER(to->engine->i915) >= 12; |
e8861964 | 1149 | u32 hwsp_offset; |
c81471f5 | 1150 | int len, err; |
e8861964 | 1151 | u32 *cs; |
e8861964 | 1152 | |
651e7d48 | 1153 | GEM_BUG_ON(GRAPHICS_VER(to->engine->i915) < 8); |
795d4d7f | 1154 | GEM_BUG_ON(i915_request_has_initial_breadcrumb(to)); |
e8861964 | 1155 | |
c8a0e2ae | 1156 | /* We need to pin the signaler's HWSP until we are finished reading. */ |
c81471f5 CW |
1157 | err = intel_timeline_read_hwsp(from, to, &hwsp_offset); |
1158 | if (err) | |
1159 | return err; | |
e8861964 | 1160 | |
c210e85b CW |
1161 | len = 4; |
1162 | if (has_token) | |
1163 | len += 2; | |
1164 | ||
1165 | cs = intel_ring_begin(to, len); | |
e8861964 CW |
1166 | if (IS_ERR(cs)) |
1167 | return PTR_ERR(cs); | |
1168 | ||
1169 | /* | |
1170 | * Using greater-than-or-equal here means we have to worry | |
1171 | * about seqno wraparound. To side step that issue, we swap | |
1172 | * the timeline HWSP upon wrapping, so that everyone listening | |
1173 | * for the old (pre-wrap) values do not see the much smaller | |
1174 | * (post-wrap) values than they were expecting (and so wait | |
1175 | * forever). | |
1176 | */ | |
c210e85b CW |
1177 | *cs++ = (MI_SEMAPHORE_WAIT | |
1178 | MI_SEMAPHORE_GLOBAL_GTT | | |
1179 | MI_SEMAPHORE_POLL | | |
1180 | MI_SEMAPHORE_SAD_GTE_SDD) + | |
1181 | has_token; | |
c81471f5 | 1182 | *cs++ = seqno; |
e8861964 CW |
1183 | *cs++ = hwsp_offset; |
1184 | *cs++ = 0; | |
c210e85b CW |
1185 | if (has_token) { |
1186 | *cs++ = 0; | |
1187 | *cs++ = MI_NOOP; | |
1188 | } | |
e8861964 CW |
1189 | |
1190 | intel_ring_advance(to, cs); | |
c81471f5 CW |
1191 | return 0; |
1192 | } | |
1193 | ||
07f82a47 TU |
1194 | static bool |
1195 | can_use_semaphore_wait(struct i915_request *to, struct i915_request *from) | |
1196 | { | |
1197 | return to->engine->gt->ggtt == from->engine->gt->ggtt; | |
1198 | } | |
1199 | ||
c81471f5 CW |
1200 | static int |
1201 | emit_semaphore_wait(struct i915_request *to, | |
1202 | struct i915_request *from, | |
1203 | gfp_t gfp) | |
1204 | { | |
326611dd | 1205 | const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask; |
18e4af04 | 1206 | struct i915_sw_fence *wait = &to->submit; |
326611dd | 1207 | |
07f82a47 TU |
1208 | if (!can_use_semaphore_wait(to, from)) |
1209 | goto await_fence; | |
1210 | ||
f16ccb64 CW |
1211 | if (!intel_context_use_semaphores(to->context)) |
1212 | goto await_fence; | |
1213 | ||
795d4d7f CW |
1214 | if (i915_request_has_initial_breadcrumb(to)) |
1215 | goto await_fence; | |
1216 | ||
fcae4961 CW |
1217 | /* |
1218 | * If this or its dependents are waiting on an external fence | |
1219 | * that may fail catastrophically, then we want to avoid using | |
9bba6b19 | 1220 | * semaphores as they bypass the fence signaling metadata, and we |
fcae4961 CW |
1221 | * lose the fence->error propagation. |
1222 | */ | |
1223 | if (from->sched.flags & I915_SCHED_HAS_EXTERNAL_CHAIN) | |
1224 | goto await_fence; | |
1225 | ||
c81471f5 | 1226 | /* Just emit the first semaphore we see as request space is limited. */ |
326611dd | 1227 | if (already_busywaiting(to) & mask) |
c81471f5 CW |
1228 | goto await_fence; |
1229 | ||
1230 | if (i915_request_await_start(to, from) < 0) | |
1231 | goto await_fence; | |
1232 | ||
1233 | /* Only submit our spinner after the signaler is running! */ | |
5ac545b8 | 1234 | if (__await_execution(to, from, gfp)) |
c81471f5 CW |
1235 | goto await_fence; |
1236 | ||
1237 | if (__emit_semaphore_wait(to, from, from->fence.seqno)) | |
1238 | goto await_fence; | |
1239 | ||
326611dd | 1240 | to->sched.semaphores |= mask; |
18e4af04 | 1241 | wait = &to->semaphore; |
6a79d848 CW |
1242 | |
1243 | await_fence: | |
18e4af04 | 1244 | return i915_sw_fence_await_dma_fence(wait, |
6a79d848 CW |
1245 | &from->fence, 0, |
1246 | I915_FENCE_GFP); | |
e8861964 CW |
1247 | } |
1248 | ||
ffb0c600 CW |
1249 | static bool intel_timeline_sync_has_start(struct intel_timeline *tl, |
1250 | struct dma_fence *fence) | |
1251 | { | |
1252 | return __intel_timeline_sync_is_later(tl, | |
1253 | fence->context, | |
1254 | fence->seqno - 1); | |
1255 | } | |
1256 | ||
1257 | static int intel_timeline_sync_set_start(struct intel_timeline *tl, | |
1258 | const struct dma_fence *fence) | |
1259 | { | |
1260 | return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1); | |
1261 | } | |
1262 | ||
a2bc4695 | 1263 | static int |
ffb0c600 | 1264 | __i915_request_await_execution(struct i915_request *to, |
5ac545b8 | 1265 | struct i915_request *from) |
a2bc4695 | 1266 | { |
ffb0c600 | 1267 | int err; |
a2bc4695 | 1268 | |
ffb0c600 | 1269 | GEM_BUG_ON(intel_context_is_barrier(from->context)); |
a2bc4695 | 1270 | |
ffb0c600 | 1271 | /* Submit both requests at the same time */ |
5ac545b8 | 1272 | err = __await_execution(to, from, I915_FENCE_GFP); |
ffb0c600 CW |
1273 | if (err) |
1274 | return err; | |
1275 | ||
1276 | /* Squash repeated depenendices to the same timelines */ | |
1277 | if (intel_timeline_sync_has_start(i915_request_timeline(to), | |
1278 | &from->fence)) | |
ade0b0c9 | 1279 | return 0; |
ffb0c600 CW |
1280 | |
1281 | /* | |
1282 | * Wait until the start of this request. | |
1283 | * | |
1284 | * The execution cb fires when we submit the request to HW. But in | |
1285 | * many cases this may be long before the request itself is ready to | |
1286 | * run (consider that we submit 2 requests for the same context, where | |
1287 | * the request of interest is behind an indefinite spinner). So we hook | |
1288 | * up to both to reduce our queues and keep the execution lag minimised | |
1289 | * in the worst case, though we hope that the await_start is elided. | |
1290 | */ | |
1291 | err = i915_request_await_start(to, from); | |
1292 | if (err < 0) | |
1293 | return err; | |
1294 | ||
1295 | /* | |
1296 | * Ensure both start together [after all semaphores in signal] | |
1297 | * | |
1298 | * Now that we are queued to the HW at roughly the same time (thanks | |
1299 | * to the execute cb) and are ready to run at roughly the same time | |
1300 | * (thanks to the await start), our signaler may still be indefinitely | |
1301 | * delayed by waiting on a semaphore from a remote engine. If our | |
1302 | * signaler depends on a semaphore, so indirectly do we, and we do not | |
1303 | * want to start our payload until our signaler also starts theirs. | |
1304 | * So we wait. | |
1305 | * | |
1306 | * However, there is also a second condition for which we need to wait | |
1307 | * for the precise start of the signaler. Consider that the signaler | |
1308 | * was submitted in a chain of requests following another context | |
1309 | * (with just an ordinary intra-engine fence dependency between the | |
1310 | * two). In this case the signaler is queued to HW, but not for | |
1311 | * immediate execution, and so we must wait until it reaches the | |
1312 | * active slot. | |
1313 | */ | |
07f82a47 TU |
1314 | if (can_use_semaphore_wait(to, from) && |
1315 | intel_engine_has_semaphores(to->engine) && | |
ffb0c600 CW |
1316 | !i915_request_has_initial_breadcrumb(to)) { |
1317 | err = __emit_semaphore_wait(to, from, from->fence.seqno - 1); | |
1318 | if (err < 0) | |
1319 | return err; | |
24fe5f2a | 1320 | } |
ade0b0c9 | 1321 | |
ffb0c600 | 1322 | /* Couple the dependency tree for PI on this exposed to->fence */ |
3f623e06 | 1323 | if (to->engine->sched_engine->schedule) { |
ffb0c600 | 1324 | err = i915_sched_node_add_dependency(&to->sched, |
6b6cd2eb | 1325 | &from->sched, |
ffb0c600 CW |
1326 | I915_DEPENDENCY_WEAK); |
1327 | if (err < 0) | |
1328 | return err; | |
52e54209 CW |
1329 | } |
1330 | ||
ffb0c600 CW |
1331 | return intel_timeline_sync_set_start(i915_request_timeline(to), |
1332 | &from->fence); | |
a2bc4695 CW |
1333 | } |
1334 | ||
fcae4961 CW |
1335 | static void mark_external(struct i915_request *rq) |
1336 | { | |
1337 | /* | |
1338 | * The downside of using semaphores is that we lose metadata passing | |
1339 | * along the signaling chain. This is particularly nasty when we | |
1340 | * need to pass along a fatal error such as EFAULT or EDEADLK. For | |
1341 | * fatal errors we want to scrub the request before it is executed, | |
1342 | * which means that we cannot preload the request onto HW and have | |
1343 | * it wait upon a semaphore. | |
1344 | */ | |
1345 | rq->sched.flags |= I915_SCHED_HAS_EXTERNAL_CHAIN; | |
1346 | } | |
1347 | ||
ac938052 | 1348 | static int |
3136deb7 | 1349 | __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) |
ac938052 | 1350 | { |
fcae4961 | 1351 | mark_external(rq); |
ac938052 | 1352 | return i915_sw_fence_await_dma_fence(&rq->submit, fence, |
d3f23ab9 | 1353 | i915_fence_context_timeout(rq->i915, |
16dc224f | 1354 | fence->context), |
ac938052 CW |
1355 | I915_FENCE_GFP); |
1356 | } | |
1357 | ||
3136deb7 LL |
1358 | static int |
1359 | i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) | |
1360 | { | |
1361 | struct dma_fence *iter; | |
1362 | int err = 0; | |
1363 | ||
1364 | if (!to_dma_fence_chain(fence)) | |
1365 | return __i915_request_await_external(rq, fence); | |
1366 | ||
1367 | dma_fence_chain_for_each(iter, fence) { | |
1368 | struct dma_fence_chain *chain = to_dma_fence_chain(iter); | |
1369 | ||
1370 | if (!dma_fence_is_i915(chain->fence)) { | |
1371 | err = __i915_request_await_external(rq, iter); | |
1372 | break; | |
1373 | } | |
1374 | ||
1375 | err = i915_request_await_dma_fence(rq, chain->fence); | |
1376 | if (err < 0) | |
1377 | break; | |
1378 | } | |
1379 | ||
1380 | dma_fence_put(iter); | |
1381 | return err; | |
1382 | } | |
1383 | ||
afc76f30 MB |
1384 | static inline bool is_parallel_rq(struct i915_request *rq) |
1385 | { | |
1386 | return intel_context_is_parallel(rq->context); | |
1387 | } | |
1388 | ||
1389 | static inline struct intel_context *request_to_parent(struct i915_request *rq) | |
1390 | { | |
1391 | return intel_context_to_parent(rq->context); | |
1392 | } | |
1393 | ||
1394 | static bool is_same_parallel_context(struct i915_request *to, | |
1395 | struct i915_request *from) | |
1396 | { | |
1397 | if (is_parallel_rq(to)) | |
1398 | return request_to_parent(to) == request_to_parent(from); | |
1399 | ||
1400 | return false; | |
1401 | } | |
1402 | ||
b52992c0 | 1403 | int |
ffb0c600 | 1404 | i915_request_await_execution(struct i915_request *rq, |
5ac545b8 | 1405 | struct dma_fence *fence) |
b52992c0 | 1406 | { |
29ef3fa9 CW |
1407 | struct dma_fence **child = &fence; |
1408 | unsigned int nchild = 1; | |
b52992c0 | 1409 | int ret; |
b52992c0 | 1410 | |
29ef3fa9 CW |
1411 | if (dma_fence_is_array(fence)) { |
1412 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
1413 | ||
ffb0c600 CW |
1414 | /* XXX Error for signal-on-any fence arrays */ |
1415 | ||
29ef3fa9 CW |
1416 | child = array->fences; |
1417 | nchild = array->num_fences; | |
1418 | GEM_BUG_ON(!nchild); | |
1419 | } | |
b52992c0 | 1420 | |
29ef3fa9 CW |
1421 | do { |
1422 | fence = *child++; | |
93a2711c | 1423 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
29ef3fa9 | 1424 | continue; |
b52992c0 | 1425 | |
e61e0f51 | 1426 | if (fence->context == rq->fence.context) |
ceae14bd CW |
1427 | continue; |
1428 | ||
ffb0c600 CW |
1429 | /* |
1430 | * We don't squash repeated fence dependencies here as we | |
1431 | * want to run our callback in all cases. | |
1432 | */ | |
47979480 | 1433 | |
afc76f30 MB |
1434 | if (dma_fence_is_i915(fence)) { |
1435 | if (is_same_parallel_context(rq, to_request(fence))) | |
1436 | continue; | |
ffb0c600 | 1437 | ret = __i915_request_await_execution(rq, |
5ac545b8 | 1438 | to_request(fence)); |
afc76f30 | 1439 | } else { |
ac938052 | 1440 | ret = i915_request_await_external(rq, fence); |
afc76f30 | 1441 | } |
b52992c0 CW |
1442 | if (ret < 0) |
1443 | return ret; | |
29ef3fa9 | 1444 | } while (--nchild); |
b52992c0 CW |
1445 | |
1446 | return 0; | |
1447 | } | |
1448 | ||
511b6d9a CW |
1449 | static int |
1450 | await_request_submit(struct i915_request *to, struct i915_request *from) | |
1451 | { | |
1452 | /* | |
1453 | * If we are waiting on a virtual engine, then it may be | |
1454 | * constrained to execute on a single engine *prior* to submission. | |
1455 | * When it is submitted, it will be first submitted to the virtual | |
1456 | * engine and then passed to the physical engine. We cannot allow | |
1457 | * the waiter to be submitted immediately to the physical engine | |
1458 | * as it may then bypass the virtual request. | |
1459 | */ | |
1460 | if (to->engine == READ_ONCE(from->engine)) | |
1461 | return i915_sw_fence_await_sw_fence_gfp(&to->submit, | |
1462 | &from->submit, | |
1463 | I915_FENCE_GFP); | |
1464 | else | |
5ac545b8 | 1465 | return __i915_request_await_execution(to, from); |
511b6d9a CW |
1466 | } |
1467 | ||
c81471f5 | 1468 | static int |
ffb0c600 | 1469 | i915_request_await_request(struct i915_request *to, struct i915_request *from) |
c81471f5 | 1470 | { |
ffb0c600 | 1471 | int ret; |
f16ccb64 | 1472 | |
ffb0c600 CW |
1473 | GEM_BUG_ON(to == from); |
1474 | GEM_BUG_ON(to->timeline == from->timeline); | |
c81471f5 | 1475 | |
ffb0c600 CW |
1476 | if (i915_request_completed(from)) { |
1477 | i915_sw_fence_set_error_once(&to->submit, from->fence.error); | |
c81471f5 | 1478 | return 0; |
798fa870 CW |
1479 | } |
1480 | ||
3f623e06 | 1481 | if (to->engine->sched_engine->schedule) { |
ffb0c600 | 1482 | ret = i915_sched_node_add_dependency(&to->sched, |
6b6cd2eb | 1483 | &from->sched, |
ffb0c600 CW |
1484 | I915_DEPENDENCY_EXTERNAL); |
1485 | if (ret < 0) | |
1486 | return ret; | |
c81471f5 CW |
1487 | } |
1488 | ||
38d5ec43 MB |
1489 | if (!intel_engine_uses_guc(to->engine) && |
1490 | is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask))) | |
511b6d9a | 1491 | ret = await_request_submit(to, from); |
ffb0c600 CW |
1492 | else |
1493 | ret = emit_semaphore_wait(to, from, I915_FENCE_GFP); | |
1494 | if (ret < 0) | |
1495 | return ret; | |
1496 | ||
1497 | return 0; | |
c81471f5 CW |
1498 | } |
1499 | ||
f71e01a7 | 1500 | int |
ffb0c600 | 1501 | i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) |
f71e01a7 CW |
1502 | { |
1503 | struct dma_fence **child = &fence; | |
1504 | unsigned int nchild = 1; | |
1505 | int ret; | |
1506 | ||
ffb0c600 CW |
1507 | /* |
1508 | * Note that if the fence-array was created in signal-on-any mode, | |
1509 | * we should *not* decompose it into its individual fences. However, | |
1510 | * we don't currently store which mode the fence-array is operating | |
1511 | * in. Fortunately, the only user of signal-on-any is private to | |
1512 | * amdgpu and we should not see any incoming fence-array from | |
1513 | * sync-file being in signal-on-any mode. | |
1514 | */ | |
f71e01a7 CW |
1515 | if (dma_fence_is_array(fence)) { |
1516 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
1517 | ||
f71e01a7 CW |
1518 | child = array->fences; |
1519 | nchild = array->num_fences; | |
1520 | GEM_BUG_ON(!nchild); | |
1521 | } | |
1522 | ||
1523 | do { | |
1524 | fence = *child++; | |
93a2711c | 1525 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
f71e01a7 CW |
1526 | continue; |
1527 | ||
ffb0c600 CW |
1528 | /* |
1529 | * Requests on the same timeline are explicitly ordered, along | |
1530 | * with their dependencies, by i915_request_add() which ensures | |
1531 | * that requests are submitted in-order through each ring. | |
1532 | */ | |
2045d666 CW |
1533 | if (fence->context == rq->fence.context) |
1534 | continue; | |
1535 | ||
ffb0c600 CW |
1536 | /* Squash repeated waits to the same timelines */ |
1537 | if (fence->context && | |
1538 | intel_timeline_sync_is_later(i915_request_timeline(rq), | |
1539 | fence)) | |
1540 | continue; | |
f71e01a7 | 1541 | |
afc76f30 MB |
1542 | if (dma_fence_is_i915(fence)) { |
1543 | if (is_same_parallel_context(rq, to_request(fence))) | |
1544 | continue; | |
ffb0c600 | 1545 | ret = i915_request_await_request(rq, to_request(fence)); |
afc76f30 | 1546 | } else { |
ac938052 | 1547 | ret = i915_request_await_external(rq, fence); |
afc76f30 | 1548 | } |
f71e01a7 CW |
1549 | if (ret < 0) |
1550 | return ret; | |
ffb0c600 CW |
1551 | |
1552 | /* Record the latest fence used against each timeline */ | |
1553 | if (fence->context) | |
1554 | intel_timeline_sync_set(i915_request_timeline(rq), | |
1555 | fence); | |
f71e01a7 CW |
1556 | } while (--nchild); |
1557 | ||
1558 | return 0; | |
1559 | } | |
1560 | ||
11930817 TH |
1561 | /** |
1562 | * i915_request_await_deps - set this request to (async) wait upon a struct | |
1563 | * i915_deps dma_fence collection | |
1564 | * @rq: request we are wishing to use | |
1565 | * @deps: The struct i915_deps containing the dependencies. | |
1566 | * | |
1567 | * Returns 0 if successful, negative error code on error. | |
1568 | */ | |
1569 | int i915_request_await_deps(struct i915_request *rq, const struct i915_deps *deps) | |
1570 | { | |
1571 | int i, err; | |
1572 | ||
1573 | for (i = 0; i < deps->num_deps; ++i) { | |
1574 | err = i915_request_await_dma_fence(rq, deps->fences[i]); | |
1575 | if (err) | |
1576 | return err; | |
1577 | } | |
1578 | ||
1579 | return 0; | |
1580 | } | |
1581 | ||
a2bc4695 | 1582 | /** |
e61e0f51 | 1583 | * i915_request_await_object - set this request to (async) wait upon a bo |
a2bc4695 CW |
1584 | * @to: request we are wishing to use |
1585 | * @obj: object which may be in use on another ring. | |
d8802126 | 1586 | * @write: whether the wait is on behalf of a writer |
a2bc4695 CW |
1587 | * |
1588 | * This code is meant to abstract object synchronization with the GPU. | |
1589 | * Conceptually we serialise writes between engines inside the GPU. | |
1590 | * We only allow one engine to write into a buffer at any time, but | |
1591 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
1592 | * | |
1593 | * - If there is an outstanding write request to the object, the new | |
1594 | * request must wait for it to complete (either CPU or in hw, requests | |
1595 | * on the same ring will be naturally ordered). | |
1596 | * | |
1597 | * - If we are a write request (pending_write_domain is set), the new | |
1598 | * request must wait for outstanding read requests to complete. | |
1599 | * | |
1600 | * Returns 0 if successful, else propagates up the lower layer error. | |
1601 | */ | |
1602 | int | |
e61e0f51 CW |
1603 | i915_request_await_object(struct i915_request *to, |
1604 | struct drm_i915_gem_object *obj, | |
1605 | bool write) | |
a2bc4695 | 1606 | { |
a585070f CK |
1607 | struct dma_resv_iter cursor; |
1608 | struct dma_fence *fence; | |
d07f0e59 | 1609 | int ret = 0; |
a2bc4695 | 1610 | |
7bc80a54 CK |
1611 | dma_resv_for_each_fence(&cursor, obj->base.resv, |
1612 | dma_resv_usage_rw(write), fence) { | |
a585070f | 1613 | ret = i915_request_await_dma_fence(to, fence); |
d07f0e59 | 1614 | if (ret) |
a585070f | 1615 | break; |
a2bc4695 CW |
1616 | } |
1617 | ||
d07f0e59 | 1618 | return ret; |
a2bc4695 CW |
1619 | } |
1620 | ||
e6177ec5 DCS |
1621 | static void i915_request_await_huc(struct i915_request *rq) |
1622 | { | |
1623 | struct intel_huc *huc = &rq->context->engine->gt->uc.huc; | |
1624 | ||
1625 | /* don't stall kernel submissions! */ | |
1626 | if (!rcu_access_pointer(rq->context->gem_context)) | |
1627 | return; | |
1628 | ||
1629 | if (intel_huc_wait_required(huc)) | |
1630 | i915_sw_fence_await_sw_fence(&rq->submit, | |
1631 | &huc->delayed_load.fence, | |
1632 | &rq->hucq); | |
1633 | } | |
1634 | ||
ea593dbb | 1635 | static struct i915_request * |
bc955204 MB |
1636 | __i915_request_ensure_parallel_ordering(struct i915_request *rq, |
1637 | struct intel_timeline *timeline) | |
ea593dbb | 1638 | { |
ea593dbb CW |
1639 | struct i915_request *prev; |
1640 | ||
bc955204 MB |
1641 | GEM_BUG_ON(!is_parallel_rq(rq)); |
1642 | ||
1643 | prev = request_to_parent(rq)->parallel.last_rq; | |
1644 | if (prev) { | |
1645 | if (!__i915_request_is_complete(prev)) { | |
1646 | i915_sw_fence_await_sw_fence(&rq->submit, | |
1647 | &prev->submit, | |
1648 | &rq->submitq); | |
1649 | ||
1650 | if (rq->engine->sched_engine->schedule) | |
1651 | __i915_sched_node_add_dependency(&rq->sched, | |
1652 | &prev->sched, | |
1653 | &rq->dep, | |
1654 | 0); | |
1655 | } | |
1656 | i915_request_put(prev); | |
1657 | } | |
1658 | ||
1659 | request_to_parent(rq)->parallel.last_rq = i915_request_get(rq); | |
1660 | ||
946e047a JK |
1661 | /* |
1662 | * Users have to put a reference potentially got by | |
1663 | * __i915_active_fence_set() to the returned request | |
1664 | * when no longer needed | |
1665 | */ | |
bc955204 MB |
1666 | return to_request(__i915_active_fence_set(&timeline->last_request, |
1667 | &rq->fence)); | |
1668 | } | |
1669 | ||
1670 | static struct i915_request * | |
1671 | __i915_request_ensure_ordering(struct i915_request *rq, | |
1672 | struct intel_timeline *timeline) | |
1673 | { | |
1674 | struct i915_request *prev; | |
1675 | ||
1676 | GEM_BUG_ON(is_parallel_rq(rq)); | |
1677 | ||
b1e3177b CW |
1678 | prev = to_request(__i915_active_fence_set(&timeline->last_request, |
1679 | &rq->fence)); | |
bc955204 | 1680 | |
163433e5 | 1681 | if (prev && !__i915_request_is_complete(prev)) { |
38d5ec43 | 1682 | bool uses_guc = intel_engine_uses_guc(rq->engine); |
bc955204 MB |
1683 | bool pow2 = is_power_of_2(READ_ONCE(prev->engine)->mask | |
1684 | rq->engine->mask); | |
1685 | bool same_context = prev->context == rq->context; | |
38d5ec43 | 1686 | |
1eaa251b CW |
1687 | /* |
1688 | * The requests are supposed to be kept in order. However, | |
1689 | * we need to be wary in case the timeline->last_request | |
1690 | * is used as a barrier for external modification to this | |
1691 | * context. | |
1692 | */ | |
bc955204 | 1693 | GEM_BUG_ON(same_context && |
1eaa251b CW |
1694 | i915_seqno_passed(prev->fence.seqno, |
1695 | rq->fence.seqno)); | |
1696 | ||
bc955204 | 1697 | if ((same_context && uses_guc) || (!uses_guc && pow2)) |
ea593dbb CW |
1698 | i915_sw_fence_await_sw_fence(&rq->submit, |
1699 | &prev->submit, | |
1700 | &rq->submitq); | |
1701 | else | |
1702 | __i915_sw_fence_await_dma_fence(&rq->submit, | |
1703 | &prev->fence, | |
1704 | &rq->dmaq); | |
3f623e06 | 1705 | if (rq->engine->sched_engine->schedule) |
ea593dbb CW |
1706 | __i915_sched_node_add_dependency(&rq->sched, |
1707 | &prev->sched, | |
1708 | &rq->dep, | |
1709 | 0); | |
1710 | } | |
1711 | ||
946e047a JK |
1712 | /* |
1713 | * Users have to put the reference to prev potentially got | |
1714 | * by __i915_active_fence_set() when no longer needed | |
1715 | */ | |
bc955204 MB |
1716 | return prev; |
1717 | } | |
1718 | ||
1719 | static struct i915_request * | |
1720 | __i915_request_add_to_timeline(struct i915_request *rq) | |
1721 | { | |
1722 | struct intel_timeline *timeline = i915_request_timeline(rq); | |
1723 | struct i915_request *prev; | |
1724 | ||
e6177ec5 DCS |
1725 | /* |
1726 | * Media workloads may require HuC, so stall them until HuC loading is | |
1727 | * complete. Note that HuC not being loaded when a user submission | |
1728 | * arrives can only happen when HuC is loaded via GSC and in that case | |
1729 | * we still expect the window between us starting to accept submissions | |
1730 | * and HuC loading completion to be small (a few hundred ms). | |
1731 | */ | |
1732 | if (rq->engine->class == VIDEO_DECODE_CLASS) | |
1733 | i915_request_await_huc(rq); | |
1734 | ||
bc955204 MB |
1735 | /* |
1736 | * Dependency tracking and request ordering along the timeline | |
1737 | * is special cased so that we can eliminate redundant ordering | |
1738 | * operations while building the request (we know that the timeline | |
1739 | * itself is ordered, and here we guarantee it). | |
1740 | * | |
1741 | * As we know we will need to emit tracking along the timeline, | |
1742 | * we embed the hooks into our request struct -- at the cost of | |
1743 | * having to have specialised no-allocation interfaces (which will | |
1744 | * be beneficial elsewhere). | |
1745 | * | |
1746 | * A second benefit to open-coding i915_request_await_request is | |
1747 | * that we can apply a slight variant of the rules specialised | |
1748 | * for timelines that jump between engines (such as virtual engines). | |
1749 | * If we consider the case of virtual engine, we must emit a dma-fence | |
1750 | * to prevent scheduling of the second request until the first is | |
1751 | * complete (to maximise our greedy late load balancing) and this | |
1752 | * precludes optimising to use semaphores serialisation of a single | |
1753 | * timeline across engines. | |
1754 | * | |
1755 | * We do not order parallel submission requests on the timeline as each | |
1756 | * parallel submission context has its own timeline and the ordering | |
1757 | * rules for parallel requests are that they must be submitted in the | |
1758 | * order received from the execbuf IOCTL. So rather than using the | |
1759 | * timeline we store a pointer to last request submitted in the | |
1760 | * relationship in the gem context and insert a submission fence | |
1761 | * between that request and request passed into this function or | |
1762 | * alternatively we use completion fence if gem context has a single | |
1763 | * timeline and this is the first submission of an execbuf IOCTL. | |
1764 | */ | |
1765 | if (likely(!is_parallel_rq(rq))) | |
1766 | prev = __i915_request_ensure_ordering(rq, timeline); | |
1767 | else | |
1768 | prev = __i915_request_ensure_parallel_ordering(rq, timeline); | |
946e047a JK |
1769 | if (prev) |
1770 | i915_request_put(prev); | |
bc955204 | 1771 | |
2ccdf6a1 CW |
1772 | /* |
1773 | * Make sure that no request gazumped us - if it was allocated after | |
1774 | * our i915_request_alloc() and called __i915_request_add() before | |
1775 | * us, the timeline will hold its seqno which is later than ours. | |
1776 | */ | |
ea593dbb | 1777 | GEM_BUG_ON(timeline->seqno != rq->fence.seqno); |
ea593dbb CW |
1778 | |
1779 | return prev; | |
1780 | } | |
1781 | ||
05235c53 CW |
1782 | /* |
1783 | * NB: This function is not allowed to fail. Doing so would mean the the | |
1784 | * request is not being tracked for completion but the work itself is | |
1785 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
1786 | */ | |
2ccdf6a1 | 1787 | struct i915_request *__i915_request_commit(struct i915_request *rq) |
05235c53 | 1788 | { |
2ccdf6a1 CW |
1789 | struct intel_engine_cs *engine = rq->engine; |
1790 | struct intel_ring *ring = rq->ring; | |
73dec95e | 1791 | u32 *cs; |
05235c53 | 1792 | |
639f2f24 | 1793 | RQ_TRACE(rq, "\n"); |
c781c978 | 1794 | |
05235c53 CW |
1795 | /* |
1796 | * To ensure that this call will not fail, space for its emissions | |
1797 | * should already have been reserved in the ring buffer. Let the ring | |
1798 | * know that it is time to use that space up. | |
1799 | */ | |
2ccdf6a1 CW |
1800 | GEM_BUG_ON(rq->reserved_space > ring->space); |
1801 | rq->reserved_space = 0; | |
e5dadff4 | 1802 | rq->emitted_jiffies = jiffies; |
05235c53 | 1803 | |
8ac71d1d CW |
1804 | /* |
1805 | * Record the position of the start of the breadcrumb so that | |
05235c53 CW |
1806 | * should we detect the updated seqno part-way through the |
1807 | * GPU processing the request, we never over-estimate the | |
d045446d | 1808 | * position of the ring's HEAD. |
05235c53 | 1809 | */ |
2ccdf6a1 | 1810 | cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw); |
73dec95e | 1811 | GEM_BUG_ON(IS_ERR(cs)); |
2ccdf6a1 | 1812 | rq->postfix = intel_ring_offset(rq, cs); |
05235c53 | 1813 | |
e5dadff4 | 1814 | return __i915_request_add_to_timeline(rq); |
a79ca656 CW |
1815 | } |
1816 | ||
16f2941a CW |
1817 | void __i915_request_queue_bh(struct i915_request *rq) |
1818 | { | |
1819 | i915_sw_fence_commit(&rq->semaphore); | |
1820 | i915_sw_fence_commit(&rq->submit); | |
1821 | } | |
1822 | ||
a79ca656 CW |
1823 | void __i915_request_queue(struct i915_request *rq, |
1824 | const struct i915_sched_attr *attr) | |
1825 | { | |
8ac71d1d CW |
1826 | /* |
1827 | * Let the backend know a new request has arrived that may need | |
0de9136d CW |
1828 | * to adjust the existing execution schedule due to a high priority |
1829 | * request - i.e. we may want to preempt the current request in order | |
1830 | * to run a high priority dependency chain *before* we can execute this | |
1831 | * request. | |
1832 | * | |
1833 | * This is called before the request is ready to run so that we can | |
1834 | * decide whether to preempt the entire chain so that it is ready to | |
1835 | * run at the earliest possible convenience. | |
1836 | */ | |
3f623e06 MB |
1837 | if (attr && rq->engine->sched_engine->schedule) |
1838 | rq->engine->sched_engine->schedule(rq, attr); | |
16f2941a CW |
1839 | |
1840 | local_bh_disable(); | |
1841 | __i915_request_queue_bh(rq); | |
1842 | local_bh_enable(); /* kick tasklets */ | |
2ccdf6a1 CW |
1843 | } |
1844 | ||
1845 | void i915_request_add(struct i915_request *rq) | |
1846 | { | |
d19d71fc | 1847 | struct intel_timeline * const tl = i915_request_timeline(rq); |
e6ba7648 | 1848 | struct i915_sched_attr attr = {}; |
61231f6b | 1849 | struct i915_gem_context *ctx; |
2ccdf6a1 | 1850 | |
e5dadff4 CW |
1851 | lockdep_assert_held(&tl->mutex); |
1852 | lockdep_unpin_lock(&tl->mutex, rq->cookie); | |
2ccdf6a1 CW |
1853 | |
1854 | trace_i915_request_add(rq); | |
61231f6b | 1855 | __i915_request_commit(rq); |
2ccdf6a1 | 1856 | |
61231f6b CW |
1857 | /* XXX placeholder for selftests */ |
1858 | rcu_read_lock(); | |
1859 | ctx = rcu_dereference(rq->context->gem_context); | |
1860 | if (ctx) | |
1861 | attr = ctx->sched; | |
1862 | rcu_read_unlock(); | |
e6ba7648 | 1863 | |
a79ca656 CW |
1864 | __i915_request_queue(rq, &attr); |
1865 | ||
e5dadff4 | 1866 | mutex_unlock(&tl->mutex); |
05235c53 CW |
1867 | } |
1868 | ||
062444bb | 1869 | static unsigned long local_clock_ns(unsigned int *cpu) |
05235c53 CW |
1870 | { |
1871 | unsigned long t; | |
1872 | ||
e61e0f51 CW |
1873 | /* |
1874 | * Cheaply and approximately convert from nanoseconds to microseconds. | |
05235c53 CW |
1875 | * The result and subsequent calculations are also defined in the same |
1876 | * approximate microseconds units. The principal source of timing | |
1877 | * error here is from the simple truncation. | |
1878 | * | |
1879 | * Note that local_clock() is only defined wrt to the current CPU; | |
1880 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1881 | * blocking preemption for the entire busywait, we can detect the CPU | |
1882 | * switch and use that as indicator of system load and a reason to | |
1883 | * stop busywaiting, see busywait_stop(). | |
1884 | */ | |
1885 | *cpu = get_cpu(); | |
062444bb | 1886 | t = local_clock(); |
05235c53 CW |
1887 | put_cpu(); |
1888 | ||
1889 | return t; | |
1890 | } | |
1891 | ||
1892 | static bool busywait_stop(unsigned long timeout, unsigned int cpu) | |
1893 | { | |
1894 | unsigned int this_cpu; | |
1895 | ||
062444bb | 1896 | if (time_after(local_clock_ns(&this_cpu), timeout)) |
05235c53 CW |
1897 | return true; |
1898 | ||
1899 | return this_cpu != cpu; | |
1900 | } | |
1901 | ||
3f6a6f34 | 1902 | static bool __i915_spin_request(struct i915_request * const rq, int state) |
05235c53 | 1903 | { |
062444bb | 1904 | unsigned long timeout_ns; |
52c0fdb2 | 1905 | unsigned int cpu; |
b2f2f0fc CW |
1906 | |
1907 | /* | |
1908 | * Only wait for the request if we know it is likely to complete. | |
1909 | * | |
1910 | * We don't track the timestamps around requests, nor the average | |
1911 | * request length, so we do not have a good indicator that this | |
1912 | * request will complete within the timeout. What we do know is the | |
52c0fdb2 CW |
1913 | * order in which requests are executed by the context and so we can |
1914 | * tell if the request has been started. If the request is not even | |
1915 | * running yet, it is a fair assumption that it will not complete | |
1916 | * within our relatively short timeout. | |
b2f2f0fc | 1917 | */ |
52c0fdb2 | 1918 | if (!i915_request_is_running(rq)) |
b2f2f0fc CW |
1919 | return false; |
1920 | ||
e61e0f51 CW |
1921 | /* |
1922 | * When waiting for high frequency requests, e.g. during synchronous | |
05235c53 CW |
1923 | * rendering split between the CPU and GPU, the finite amount of time |
1924 | * required to set up the irq and wait upon it limits the response | |
1925 | * rate. By busywaiting on the request completion for a short while we | |
1926 | * can service the high frequency waits as quick as possible. However, | |
1927 | * if it is a slow request, we want to sleep as quickly as possible. | |
1928 | * The tradeoff between waiting and sleeping is roughly the time it | |
1929 | * takes to sleep on a request, on the order of a microsecond. | |
1930 | */ | |
1931 | ||
062444bb CW |
1932 | timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns); |
1933 | timeout_ns += local_clock_ns(&cpu); | |
05235c53 | 1934 | do { |
3f6a6f34 | 1935 | if (dma_fence_is_signaled(&rq->fence)) |
52c0fdb2 | 1936 | return true; |
c33ed067 | 1937 | |
05235c53 CW |
1938 | if (signal_pending_state(state, current)) |
1939 | break; | |
1940 | ||
062444bb | 1941 | if (busywait_stop(timeout_ns, cpu)) |
05235c53 CW |
1942 | break; |
1943 | ||
f2f09a4c | 1944 | cpu_relax(); |
05235c53 CW |
1945 | } while (!need_resched()); |
1946 | ||
1947 | return false; | |
1948 | } | |
1949 | ||
52c0fdb2 CW |
1950 | struct request_wait { |
1951 | struct dma_fence_cb cb; | |
1952 | struct task_struct *tsk; | |
1953 | }; | |
1954 | ||
1955 | static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb) | |
1956 | { | |
1957 | struct request_wait *wait = container_of(cb, typeof(*wait), cb); | |
1958 | ||
3f6a6f34 | 1959 | wake_up_process(fetch_and_zero(&wait->tsk)); |
52c0fdb2 CW |
1960 | } |
1961 | ||
05235c53 | 1962 | /** |
7e2e69ed | 1963 | * i915_request_wait_timeout - wait until execution of request has finished |
e61e0f51 | 1964 | * @rq: the request to wait upon |
ea746f36 | 1965 | * @flags: how to wait |
e95433c7 CW |
1966 | * @timeout: how long to wait in jiffies |
1967 | * | |
7e2e69ed | 1968 | * i915_request_wait_timeout() waits for the request to be completed, for a |
e95433c7 CW |
1969 | * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an |
1970 | * unbounded wait). | |
05235c53 | 1971 | * |
e95433c7 | 1972 | * Returns the remaining time (in jiffies) if the request completed, which may |
7e2e69ed ML |
1973 | * be zero if the request is unfinished after the timeout expires. |
1974 | * If the timeout is 0, it will return 1 if the fence is signaled. | |
1975 | * | |
e95433c7 CW |
1976 | * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is |
1977 | * pending before the request completes. | |
7e2e69ed ML |
1978 | * |
1979 | * NOTE: This function has the same wait semantics as dma-fence. | |
05235c53 | 1980 | */ |
7e2e69ed ML |
1981 | long i915_request_wait_timeout(struct i915_request *rq, |
1982 | unsigned int flags, | |
1983 | long timeout) | |
05235c53 | 1984 | { |
ea746f36 CW |
1985 | const int state = flags & I915_WAIT_INTERRUPTIBLE ? |
1986 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
52c0fdb2 | 1987 | struct request_wait wait; |
05235c53 CW |
1988 | |
1989 | might_sleep(); | |
e95433c7 | 1990 | GEM_BUG_ON(timeout < 0); |
05235c53 | 1991 | |
6e4e9708 | 1992 | if (dma_fence_is_signaled(&rq->fence)) |
7e2e69ed | 1993 | return timeout ?: 1; |
05235c53 | 1994 | |
e95433c7 CW |
1995 | if (!timeout) |
1996 | return -ETIME; | |
05235c53 | 1997 | |
e61e0f51 | 1998 | trace_i915_request_wait_begin(rq, flags); |
84383d2e CW |
1999 | |
2000 | /* | |
2001 | * We must never wait on the GPU while holding a lock as we | |
2002 | * may need to perform a GPU reset. So while we don't need to | |
2003 | * serialise wait/reset with an explicit lock, we do want | |
2004 | * lockdep to detect potential dependency cycles. | |
2005 | */ | |
cb823ed9 | 2006 | mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_); |
4680816b | 2007 | |
7ce99d24 CW |
2008 | /* |
2009 | * Optimistic spin before touching IRQs. | |
2010 | * | |
2011 | * We may use a rather large value here to offset the penalty of | |
2012 | * switching away from the active task. Frequently, the client will | |
2013 | * wait upon an old swapbuffer to throttle itself to remain within a | |
2014 | * frame of the gpu. If the client is running in lockstep with the gpu, | |
2015 | * then it should not be waiting long at all, and a sleep now will incur | |
2016 | * extra scheduler latency in producing the next frame. To try to | |
2017 | * avoid adding the cost of enabling/disabling the interrupt to the | |
2018 | * short wait, we first spin to see if the request would have completed | |
2019 | * in the time taken to setup the interrupt. | |
2020 | * | |
2021 | * We need upto 5us to enable the irq, and upto 20us to hide the | |
2022 | * scheduler latency of a context switch, ignoring the secondary | |
2023 | * impacts from a context switch such as cache eviction. | |
2024 | * | |
2025 | * The scheme used for low-latency IO is called "hybrid interrupt | |
2026 | * polling". The suggestion there is to sleep until just before you | |
2027 | * expect to be woken by the device interrupt and then poll for its | |
2028 | * completion. That requires having a good predictor for the request | |
2029 | * duration, which we currently lack. | |
2030 | */ | |
1a839e01 | 2031 | if (CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT && |
3f6a6f34 | 2032 | __i915_spin_request(rq, state)) |
52c0fdb2 | 2033 | goto out; |
541ca6ed | 2034 | |
62eb3c24 CW |
2035 | /* |
2036 | * This client is about to stall waiting for the GPU. In many cases | |
2037 | * this is undesirable and limits the throughput of the system, as | |
2038 | * many clients cannot continue processing user input/output whilst | |
2039 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
2040 | * to the GPU load and thus incurs additional latency for the client. | |
2041 | * We can circumvent that by promoting the GPU frequency to maximum | |
2042 | * before we sleep. This makes the GPU throttle up much more quickly | |
2043 | * (good for benchmarks and user experience, e.g. window animations), | |
2044 | * but at a cost of spending more power processing the workload | |
2045 | * (bad for battery). | |
2046 | */ | |
1840d40a CW |
2047 | if (flags & I915_WAIT_PRIORITY && !i915_request_started(rq)) |
2048 | intel_rps_boost(rq); | |
4680816b | 2049 | |
52c0fdb2 CW |
2050 | wait.tsk = current; |
2051 | if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake)) | |
2052 | goto out; | |
4680816b | 2053 | |
3adee4ac CW |
2054 | /* |
2055 | * Flush the submission tasklet, but only if it may help this request. | |
2056 | * | |
2057 | * We sometimes experience some latency between the HW interrupts and | |
2058 | * tasklet execution (mostly due to ksoftirqd latency, but it can also | |
2059 | * be due to lazy CS events), so lets run the tasklet manually if there | |
2060 | * is a chance it may submit this request. If the request is not ready | |
2061 | * to run, as it is waiting for other fences to be signaled, flushing | |
2062 | * the tasklet is busy work without any advantage for this client. | |
2063 | * | |
2064 | * If the HW is being lazy, this is the last chance before we go to | |
2065 | * sleep to catch any pending events. We will check periodically in | |
2066 | * the heartbeat to flush the submission tasklets as a last resort | |
2067 | * for unhappy HW. | |
2068 | */ | |
2069 | if (i915_request_is_ready(rq)) | |
5ec17c76 | 2070 | __intel_engine_flush_submission(rq->engine, false); |
3adee4ac | 2071 | |
52c0fdb2 CW |
2072 | for (;;) { |
2073 | set_current_state(state); | |
05235c53 | 2074 | |
3f6a6f34 | 2075 | if (dma_fence_is_signaled(&rq->fence)) |
52c0fdb2 | 2076 | break; |
05235c53 | 2077 | |
05235c53 | 2078 | if (signal_pending_state(state, current)) { |
e95433c7 | 2079 | timeout = -ERESTARTSYS; |
05235c53 CW |
2080 | break; |
2081 | } | |
2082 | ||
e95433c7 CW |
2083 | if (!timeout) { |
2084 | timeout = -ETIME; | |
05235c53 CW |
2085 | break; |
2086 | } | |
2087 | ||
e95433c7 | 2088 | timeout = io_schedule_timeout(timeout); |
05235c53 | 2089 | } |
a49625f9 | 2090 | __set_current_state(TASK_RUNNING); |
05235c53 | 2091 | |
3f6a6f34 CW |
2092 | if (READ_ONCE(wait.tsk)) |
2093 | dma_fence_remove_callback(&rq->fence, &wait.cb); | |
2094 | GEM_BUG_ON(!list_empty(&wait.cb.node)); | |
52c0fdb2 CW |
2095 | |
2096 | out: | |
5facae4f | 2097 | mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_); |
52c0fdb2 | 2098 | trace_i915_request_wait_end(rq); |
e95433c7 | 2099 | return timeout; |
05235c53 | 2100 | } |
4b8de8e6 | 2101 | |
7e2e69ed ML |
2102 | /** |
2103 | * i915_request_wait - wait until execution of request has finished | |
2104 | * @rq: the request to wait upon | |
2105 | * @flags: how to wait | |
2106 | * @timeout: how long to wait in jiffies | |
2107 | * | |
2108 | * i915_request_wait() waits for the request to be completed, for a | |
2109 | * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an | |
2110 | * unbounded wait). | |
2111 | * | |
2112 | * Returns the remaining time (in jiffies) if the request completed, which may | |
2113 | * be zero or -ETIME if the request is unfinished after the timeout expires. | |
2114 | * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is | |
2115 | * pending before the request completes. | |
2116 | * | |
2117 | * NOTE: This function behaves differently from dma-fence wait semantics for | |
2118 | * timeout = 0. It returns 0 on success, and -ETIME if not signaled. | |
2119 | */ | |
2120 | long i915_request_wait(struct i915_request *rq, | |
2121 | unsigned int flags, | |
2122 | long timeout) | |
2123 | { | |
2124 | long ret = i915_request_wait_timeout(rq, flags, timeout); | |
2125 | ||
2126 | if (!ret) | |
2127 | return -ETIME; | |
2128 | ||
2129 | if (ret > 0 && !timeout) | |
2130 | return 0; | |
2131 | ||
2132 | return ret; | |
2133 | } | |
2134 | ||
1f0e785a CW |
2135 | static int print_sched_attr(const struct i915_sched_attr *attr, |
2136 | char *buf, int x, int len) | |
2137 | { | |
2138 | if (attr->priority == I915_PRIORITY_INVALID) | |
2139 | return x; | |
2140 | ||
2141 | x += snprintf(buf + x, len - x, | |
2142 | " prio=%d", attr->priority); | |
2143 | ||
2144 | return x; | |
2145 | } | |
2146 | ||
562675d0 CW |
2147 | static char queue_status(const struct i915_request *rq) |
2148 | { | |
2149 | if (i915_request_is_active(rq)) | |
2150 | return 'E'; | |
2151 | ||
2152 | if (i915_request_is_ready(rq)) | |
2153 | return intel_engine_is_virtual(rq->engine) ? 'V' : 'R'; | |
2154 | ||
2155 | return 'U'; | |
2156 | } | |
2157 | ||
2158 | static const char *run_status(const struct i915_request *rq) | |
2159 | { | |
163433e5 | 2160 | if (__i915_request_is_complete(rq)) |
562675d0 CW |
2161 | return "!"; |
2162 | ||
163433e5 | 2163 | if (__i915_request_has_started(rq)) |
562675d0 CW |
2164 | return "*"; |
2165 | ||
2166 | if (!i915_sw_fence_signaled(&rq->semaphore)) | |
2167 | return "&"; | |
2168 | ||
2169 | return ""; | |
2170 | } | |
2171 | ||
2172 | static const char *fence_status(const struct i915_request *rq) | |
2173 | { | |
2174 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags)) | |
2175 | return "+"; | |
2176 | ||
2177 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) | |
2178 | return "-"; | |
2179 | ||
2180 | return ""; | |
2181 | } | |
2182 | ||
1f0e785a CW |
2183 | void i915_request_show(struct drm_printer *m, |
2184 | const struct i915_request *rq, | |
562675d0 CW |
2185 | const char *prefix, |
2186 | int indent) | |
1f0e785a CW |
2187 | { |
2188 | const char *name = rq->fence.ops->get_timeline_name((struct dma_fence *)&rq->fence); | |
2189 | char buf[80] = ""; | |
2190 | int x = 0; | |
2191 | ||
562675d0 CW |
2192 | /* |
2193 | * The prefix is used to show the queue status, for which we use | |
2194 | * the following flags: | |
2195 | * | |
2196 | * U [Unready] | |
2197 | * - initial status upon being submitted by the user | |
2198 | * | |
2199 | * - the request is not ready for execution as it is waiting | |
2200 | * for external fences | |
2201 | * | |
2202 | * R [Ready] | |
2203 | * - all fences the request was waiting on have been signaled, | |
2204 | * and the request is now ready for execution and will be | |
2205 | * in a backend queue | |
2206 | * | |
2207 | * - a ready request may still need to wait on semaphores | |
2208 | * [internal fences] | |
2209 | * | |
2210 | * V [Ready/virtual] | |
2211 | * - same as ready, but queued over multiple backends | |
2212 | * | |
2213 | * E [Executing] | |
2214 | * - the request has been transferred from the backend queue and | |
2215 | * submitted for execution on HW | |
2216 | * | |
2217 | * - a completed request may still be regarded as executing, its | |
2218 | * status may not be updated until it is retired and removed | |
2219 | * from the lists | |
2220 | */ | |
2221 | ||
1f0e785a CW |
2222 | x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf)); |
2223 | ||
562675d0 CW |
2224 | drm_printf(m, "%s%.*s%c %llx:%lld%s%s %s @ %dms: %s\n", |
2225 | prefix, indent, " ", | |
2226 | queue_status(rq), | |
1f0e785a | 2227 | rq->fence.context, rq->fence.seqno, |
562675d0 CW |
2228 | run_status(rq), |
2229 | fence_status(rq), | |
1f0e785a CW |
2230 | buf, |
2231 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), | |
2232 | name); | |
2233 | } | |
2234 | ||
dc0dad36 JH |
2235 | static bool engine_match_ring(struct intel_engine_cs *engine, struct i915_request *rq) |
2236 | { | |
2237 | u32 ring = ENGINE_READ(engine, RING_START); | |
2238 | ||
2239 | return ring == i915_ggtt_offset(rq->ring->vma); | |
2240 | } | |
2241 | ||
2242 | static bool match_ring(struct i915_request *rq) | |
2243 | { | |
2244 | struct intel_engine_cs *engine; | |
2245 | bool found; | |
2246 | int i; | |
2247 | ||
2248 | if (!intel_engine_is_virtual(rq->engine)) | |
2249 | return engine_match_ring(rq->engine, rq); | |
2250 | ||
2251 | found = false; | |
2252 | i = 0; | |
2253 | while ((engine = intel_engine_get_sibling(rq->engine, i++))) { | |
2254 | found = engine_match_ring(engine, rq); | |
2255 | if (found) | |
2256 | break; | |
2257 | } | |
2258 | ||
2259 | return found; | |
2260 | } | |
2261 | ||
2262 | enum i915_request_state i915_test_request_state(struct i915_request *rq) | |
2263 | { | |
2264 | if (i915_request_completed(rq)) | |
2265 | return I915_REQUEST_COMPLETE; | |
2266 | ||
2267 | if (!i915_request_started(rq)) | |
2268 | return I915_REQUEST_PENDING; | |
2269 | ||
2270 | if (match_ring(rq)) | |
2271 | return I915_REQUEST_ACTIVE; | |
2272 | ||
2273 | return I915_REQUEST_QUEUED; | |
2274 | } | |
2275 | ||
c835c550 CW |
2276 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
2277 | #include "selftests/mock_request.c" | |
e61e0f51 | 2278 | #include "selftests/i915_request.c" |
c835c550 | 2279 | #endif |
32eb6bcf | 2280 | |
47514ac7 | 2281 | void i915_request_module_exit(void) |
103b76ee | 2282 | { |
47514ac7 DV |
2283 | kmem_cache_destroy(slab_execute_cbs); |
2284 | kmem_cache_destroy(slab_requests); | |
103b76ee CW |
2285 | } |
2286 | ||
47514ac7 | 2287 | int __init i915_request_module_init(void) |
32eb6bcf | 2288 | { |
47514ac7 | 2289 | slab_requests = |
67a3acaa CW |
2290 | kmem_cache_create("i915_request", |
2291 | sizeof(struct i915_request), | |
2292 | __alignof__(struct i915_request), | |
2293 | SLAB_HWCACHE_ALIGN | | |
2294 | SLAB_RECLAIM_ACCOUNT | | |
2295 | SLAB_TYPESAFE_BY_RCU, | |
2296 | __i915_request_ctor); | |
47514ac7 | 2297 | if (!slab_requests) |
32eb6bcf CW |
2298 | return -ENOMEM; |
2299 | ||
47514ac7 | 2300 | slab_execute_cbs = KMEM_CACHE(execute_cb, |
e8861964 CW |
2301 | SLAB_HWCACHE_ALIGN | |
2302 | SLAB_RECLAIM_ACCOUNT | | |
2303 | SLAB_TYPESAFE_BY_RCU); | |
47514ac7 | 2304 | if (!slab_execute_cbs) |
e8861964 CW |
2305 | goto err_requests; |
2306 | ||
32eb6bcf CW |
2307 | return 0; |
2308 | ||
2309 | err_requests: | |
47514ac7 | 2310 | kmem_cache_destroy(slab_requests); |
32eb6bcf CW |
2311 | return -ENOMEM; |
2312 | } |