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eec688e1 RB |
1 | /* |
2 | * Copyright © 2015-2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Robert Bragg <robert@sixbynine.org> | |
25 | */ | |
26 | ||
7abbd8d6 RB |
27 | |
28 | /** | |
16d98b31 | 29 | * DOC: i915 Perf Overview |
7abbd8d6 RB |
30 | * |
31 | * Gen graphics supports a large number of performance counters that can help | |
32 | * driver and application developers understand and optimize their use of the | |
33 | * GPU. | |
34 | * | |
35 | * This i915 perf interface enables userspace to configure and open a file | |
36 | * descriptor representing a stream of GPU metrics which can then be read() as | |
37 | * a stream of sample records. | |
38 | * | |
39 | * The interface is particularly suited to exposing buffered metrics that are | |
40 | * captured by DMA from the GPU, unsynchronized with and unrelated to the CPU. | |
41 | * | |
42 | * Streams representing a single context are accessible to applications with a | |
43 | * corresponding drm file descriptor, such that OpenGL can use the interface | |
44 | * without special privileges. Access to system-wide metrics requires root | |
45 | * privileges by default, unless changed via the dev.i915.perf_event_paranoid | |
46 | * sysctl option. | |
47 | * | |
16d98b31 RB |
48 | */ |
49 | ||
50 | /** | |
51 | * DOC: i915 Perf History and Comparison with Core Perf | |
7abbd8d6 RB |
52 | * |
53 | * The interface was initially inspired by the core Perf infrastructure but | |
54 | * some notable differences are: | |
55 | * | |
56 | * i915 perf file descriptors represent a "stream" instead of an "event"; where | |
57 | * a perf event primarily corresponds to a single 64bit value, while a stream | |
58 | * might sample sets of tightly-coupled counters, depending on the | |
59 | * configuration. For example the Gen OA unit isn't designed to support | |
60 | * orthogonal configurations of individual counters; it's configured for a set | |
61 | * of related counters. Samples for an i915 perf stream capturing OA metrics | |
62 | * will include a set of counter values packed in a compact HW specific format. | |
63 | * The OA unit supports a number of different packing formats which can be | |
64 | * selected by the user opening the stream. Perf has support for grouping | |
65 | * events, but each event in the group is configured, validated and | |
66 | * authenticated individually with separate system calls. | |
67 | * | |
68 | * i915 perf stream configurations are provided as an array of u64 (key,value) | |
69 | * pairs, instead of a fixed struct with multiple miscellaneous config members, | |
70 | * interleaved with event-type specific members. | |
71 | * | |
72 | * i915 perf doesn't support exposing metrics via an mmap'd circular buffer. | |
73 | * The supported metrics are being written to memory by the GPU unsynchronized | |
74 | * with the CPU, using HW specific packing formats for counter sets. Sometimes | |
75 | * the constraints on HW configuration require reports to be filtered before it | |
76 | * would be acceptable to expose them to unprivileged applications - to hide | |
77 | * the metrics of other processes/contexts. For these use cases a read() based | |
78 | * interface is a good fit, and provides an opportunity to filter data as it | |
79 | * gets copied from the GPU mapped buffers to userspace buffers. | |
80 | * | |
81 | * | |
16d98b31 RB |
82 | * Issues hit with first prototype based on Core Perf |
83 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
7abbd8d6 RB |
84 | * |
85 | * The first prototype of this driver was based on the core perf | |
86 | * infrastructure, and while we did make that mostly work, with some changes to | |
87 | * perf, we found we were breaking or working around too many assumptions baked | |
88 | * into perf's currently cpu centric design. | |
89 | * | |
90 | * In the end we didn't see a clear benefit to making perf's implementation and | |
91 | * interface more complex by changing design assumptions while we knew we still | |
92 | * wouldn't be able to use any existing perf based userspace tools. | |
93 | * | |
94 | * Also considering the Gen specific nature of the Observability hardware and | |
95 | * how userspace will sometimes need to combine i915 perf OA metrics with | |
96 | * side-band OA data captured via MI_REPORT_PERF_COUNT commands; we're | |
97 | * expecting the interface to be used by a platform specific userspace such as | |
98 | * OpenGL or tools. This is to say; we aren't inherently missing out on having | |
99 | * a standard vendor/architecture agnostic interface by not using perf. | |
100 | * | |
101 | * | |
102 | * For posterity, in case we might re-visit trying to adapt core perf to be | |
103 | * better suited to exposing i915 metrics these were the main pain points we | |
104 | * hit: | |
105 | * | |
106 | * - The perf based OA PMU driver broke some significant design assumptions: | |
107 | * | |
108 | * Existing perf pmus are used for profiling work on a cpu and we were | |
109 | * introducing the idea of _IS_DEVICE pmus with different security | |
110 | * implications, the need to fake cpu-related data (such as user/kernel | |
111 | * registers) to fit with perf's current design, and adding _DEVICE records | |
112 | * as a way to forward device-specific status records. | |
113 | * | |
114 | * The OA unit writes reports of counters into a circular buffer, without | |
115 | * involvement from the CPU, making our PMU driver the first of a kind. | |
116 | * | |
117 | * Given the way we were periodically forward data from the GPU-mapped, OA | |
118 | * buffer to perf's buffer, those bursts of sample writes looked to perf like | |
119 | * we were sampling too fast and so we had to subvert its throttling checks. | |
120 | * | |
121 | * Perf supports groups of counters and allows those to be read via | |
122 | * transactions internally but transactions currently seem designed to be | |
123 | * explicitly initiated from the cpu (say in response to a userspace read()) | |
124 | * and while we could pull a report out of the OA buffer we can't | |
125 | * trigger a report from the cpu on demand. | |
126 | * | |
127 | * Related to being report based; the OA counters are configured in HW as a | |
128 | * set while perf generally expects counter configurations to be orthogonal. | |
129 | * Although counters can be associated with a group leader as they are | |
130 | * opened, there's no clear precedent for being able to provide group-wide | |
131 | * configuration attributes (for example we want to let userspace choose the | |
132 | * OA unit report format used to capture all counters in a set, or specify a | |
133 | * GPU context to filter metrics on). We avoided using perf's grouping | |
134 | * feature and forwarded OA reports to userspace via perf's 'raw' sample | |
135 | * field. This suited our userspace well considering how coupled the counters | |
136 | * are when dealing with normalizing. It would be inconvenient to split | |
137 | * counters up into separate events, only to require userspace to recombine | |
138 | * them. For Mesa it's also convenient to be forwarded raw, periodic reports | |
139 | * for combining with the side-band raw reports it captures using | |
140 | * MI_REPORT_PERF_COUNT commands. | |
141 | * | |
16d98b31 | 142 | * - As a side note on perf's grouping feature; there was also some concern |
7abbd8d6 RB |
143 | * that using PERF_FORMAT_GROUP as a way to pack together counter values |
144 | * would quite drastically inflate our sample sizes, which would likely | |
145 | * lower the effective sampling resolutions we could use when the available | |
146 | * memory bandwidth is limited. | |
147 | * | |
148 | * With the OA unit's report formats, counters are packed together as 32 | |
149 | * or 40bit values, with the largest report size being 256 bytes. | |
150 | * | |
151 | * PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a | |
152 | * documented ordering to the values, implying PERF_FORMAT_ID must also be | |
153 | * used to add a 64bit ID before each value; giving 16 bytes per counter. | |
154 | * | |
155 | * Related to counter orthogonality; we can't time share the OA unit, while | |
156 | * event scheduling is a central design idea within perf for allowing | |
157 | * userspace to open + enable more events than can be configured in HW at any | |
158 | * one time. The OA unit is not designed to allow re-configuration while in | |
159 | * use. We can't reconfigure the OA unit without losing internal OA unit | |
160 | * state which we can't access explicitly to save and restore. Reconfiguring | |
161 | * the OA unit is also relatively slow, involving ~100 register writes. From | |
162 | * userspace Mesa also depends on a stable OA configuration when emitting | |
163 | * MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be | |
164 | * disabled while there are outstanding MI_RPC commands lest we hang the | |
165 | * command streamer. | |
166 | * | |
167 | * The contents of sample records aren't extensible by device drivers (i.e. | |
168 | * the sample_type bits). As an example; Sourab Gupta had been looking to | |
169 | * attach GPU timestamps to our OA samples. We were shoehorning OA reports | |
170 | * into sample records by using the 'raw' field, but it's tricky to pack more | |
171 | * than one thing into this field because events/core.c currently only lets a | |
172 | * pmu give a single raw data pointer plus len which will be copied into the | |
173 | * ring buffer. To include more than the OA report we'd have to copy the | |
174 | * report into an intermediate larger buffer. I'd been considering allowing a | |
175 | * vector of data+len values to be specified for copying the raw data, but | |
176 | * it felt like a kludge to being using the raw field for this purpose. | |
177 | * | |
178 | * - It felt like our perf based PMU was making some technical compromises | |
179 | * just for the sake of using perf: | |
180 | * | |
181 | * perf_event_open() requires events to either relate to a pid or a specific | |
182 | * cpu core, while our device pmu related to neither. Events opened with a | |
183 | * pid will be automatically enabled/disabled according to the scheduling of | |
184 | * that process - so not appropriate for us. When an event is related to a | |
185 | * cpu id, perf ensures pmu methods will be invoked via an inter process | |
186 | * interrupt on that core. To avoid invasive changes our userspace opened OA | |
187 | * perf events for a specific cpu. This was workable but it meant the | |
188 | * majority of the OA driver ran in atomic context, including all OA report | |
189 | * forwarding, which wasn't really necessary in our case and seems to make | |
190 | * our locking requirements somewhat complex as we handled the interaction | |
191 | * with the rest of the i915 driver. | |
192 | */ | |
193 | ||
eec688e1 | 194 | #include <linux/anon_inodes.h> |
d7965152 | 195 | #include <linux/sizes.h> |
f89823c2 | 196 | #include <linux/uuid.h> |
eec688e1 | 197 | |
10be98a7 | 198 | #include "gem/i915_gem_context.h" |
a5efcde6 | 199 | #include "gt/intel_engine_pm.h" |
9a61363a | 200 | #include "gt/intel_engine_user.h" |
daed3e44 | 201 | #include "gt/intel_gt.h" |
112ed2d3 | 202 | #include "gt/intel_lrc_reg.h" |
2871ea85 | 203 | #include "gt/intel_ring.h" |
112ed2d3 | 204 | |
eec688e1 | 205 | #include "i915_drv.h" |
db94e9f1 | 206 | #include "i915_perf.h" |
5ed7a0cf MW |
207 | #include "oa/i915_oa_hsw.h" |
208 | #include "oa/i915_oa_bdw.h" | |
209 | #include "oa/i915_oa_chv.h" | |
210 | #include "oa/i915_oa_sklgt2.h" | |
211 | #include "oa/i915_oa_sklgt3.h" | |
212 | #include "oa/i915_oa_sklgt4.h" | |
213 | #include "oa/i915_oa_bxt.h" | |
214 | #include "oa/i915_oa_kblgt2.h" | |
215 | #include "oa/i915_oa_kblgt3.h" | |
216 | #include "oa/i915_oa_glk.h" | |
217 | #include "oa/i915_oa_cflgt2.h" | |
218 | #include "oa/i915_oa_cflgt3.h" | |
219 | #include "oa/i915_oa_cnl.h" | |
220 | #include "oa/i915_oa_icl.h" | |
00a7f0d7 | 221 | #include "oa/i915_oa_tgl.h" |
d7965152 | 222 | |
fe841686 JL |
223 | /* HW requires this to be a power of two, between 128k and 16M, though driver |
224 | * is currently generally designed assuming the largest 16M size is used such | |
225 | * that the overflow cases are unlikely in normal operation. | |
226 | */ | |
227 | #define OA_BUFFER_SIZE SZ_16M | |
228 | ||
229 | #define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1)) | |
d7965152 | 230 | |
0dd860cf RB |
231 | /** |
232 | * DOC: OA Tail Pointer Race | |
233 | * | |
234 | * There's a HW race condition between OA unit tail pointer register updates and | |
d7965152 | 235 | * writes to memory whereby the tail pointer can sometimes get ahead of what's |
0dd860cf RB |
236 | * been written out to the OA buffer so far (in terms of what's visible to the |
237 | * CPU). | |
238 | * | |
239 | * Although this can be observed explicitly while copying reports to userspace | |
240 | * by checking for a zeroed report-id field in tail reports, we want to account | |
19f81df2 | 241 | * for this earlier, as part of the oa_buffer_check to avoid lots of redundant |
0dd860cf RB |
242 | * read() attempts. |
243 | * | |
244 | * In effect we define a tail pointer for reading that lags the real tail | |
245 | * pointer by at least %OA_TAIL_MARGIN_NSEC nanoseconds, which gives enough | |
246 | * time for the corresponding reports to become visible to the CPU. | |
247 | * | |
248 | * To manage this we actually track two tail pointers: | |
249 | * 1) An 'aging' tail with an associated timestamp that is tracked until we | |
250 | * can trust the corresponding data is visible to the CPU; at which point | |
251 | * it is considered 'aged'. | |
252 | * 2) An 'aged' tail that can be used for read()ing. | |
d7965152 | 253 | * |
0dd860cf | 254 | * The two separate pointers let us decouple read()s from tail pointer aging. |
d7965152 | 255 | * |
0dd860cf | 256 | * The tail pointers are checked and updated at a limited rate within a hrtimer |
a9a08845 | 257 | * callback (the same callback that is used for delivering EPOLLIN events) |
d7965152 | 258 | * |
0dd860cf RB |
259 | * Initially the tails are marked invalid with %INVALID_TAIL_PTR which |
260 | * indicates that an updated tail pointer is needed. | |
261 | * | |
262 | * Most of the implementation details for this workaround are in | |
19f81df2 | 263 | * oa_buffer_check_unlocked() and _append_oa_reports() |
0dd860cf RB |
264 | * |
265 | * Note for posterity: previously the driver used to define an effective tail | |
266 | * pointer that lagged the real pointer by a 'tail margin' measured in bytes | |
267 | * derived from %OA_TAIL_MARGIN_NSEC and the configured sampling frequency. | |
268 | * This was flawed considering that the OA unit may also automatically generate | |
269 | * non-periodic reports (such as on context switch) or the OA unit may be | |
270 | * enabled without any periodic sampling. | |
d7965152 RB |
271 | */ |
272 | #define OA_TAIL_MARGIN_NSEC 100000ULL | |
0dd860cf | 273 | #define INVALID_TAIL_PTR 0xffffffff |
d7965152 RB |
274 | |
275 | /* frequency for checking whether the OA unit has written new reports to the | |
276 | * circular OA buffer... | |
277 | */ | |
278 | #define POLL_FREQUENCY 200 | |
279 | #define POLL_PERIOD (NSEC_PER_SEC / POLL_FREQUENCY) | |
280 | ||
ccdf6341 | 281 | /* for sysctl proc_dointvec_minmax of dev.i915.perf_stream_paranoid */ |
ccdf6341 RB |
282 | static u32 i915_perf_stream_paranoid = true; |
283 | ||
d7965152 RB |
284 | /* The maximum exponent the hardware accepts is 63 (essentially it selects one |
285 | * of the 64bit timestamp bits to trigger reports from) but there's currently | |
286 | * no known use case for sampling as infrequently as once per 47 thousand years. | |
287 | * | |
288 | * Since the timestamps included in OA reports are only 32bits it seems | |
289 | * reasonable to limit the OA exponent where it's still possible to account for | |
290 | * overflow in OA report timestamps. | |
291 | */ | |
292 | #define OA_EXPONENT_MAX 31 | |
293 | ||
294 | #define INVALID_CTX_ID 0xffffffff | |
295 | ||
19f81df2 RB |
296 | /* On Gen8+ automatically triggered OA reports include a 'reason' field... */ |
297 | #define OAREPORT_REASON_MASK 0x3f | |
00a7f0d7 | 298 | #define OAREPORT_REASON_MASK_EXTENDED 0x7f |
19f81df2 RB |
299 | #define OAREPORT_REASON_SHIFT 19 |
300 | #define OAREPORT_REASON_TIMER (1<<0) | |
301 | #define OAREPORT_REASON_CTX_SWITCH (1<<3) | |
302 | #define OAREPORT_REASON_CLK_RATIO (1<<5) | |
303 | ||
d7965152 | 304 | |
00319ba0 RB |
305 | /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate |
306 | * | |
155e941f RB |
307 | * The highest sampling frequency we can theoretically program the OA unit |
308 | * with is always half the timestamp frequency: E.g. 6.25Mhz for Haswell. | |
309 | * | |
310 | * Initialized just before we register the sysctl parameter. | |
00319ba0 | 311 | */ |
155e941f | 312 | static int oa_sample_rate_hard_limit; |
00319ba0 RB |
313 | |
314 | /* Theoretically we can program the OA unit to sample every 160ns but don't | |
315 | * allow that by default unless root... | |
316 | * | |
317 | * The default threshold of 100000Hz is based on perf's similar | |
318 | * kernel.perf_event_max_sample_rate sysctl parameter. | |
319 | */ | |
320 | static u32 i915_oa_max_sample_rate = 100000; | |
321 | ||
d7965152 RB |
322 | /* XXX: beware if future OA HW adds new report formats that the current |
323 | * code assumes all reports have a power-of-two size and ~(size - 1) can | |
324 | * be used as a mask to align the OA tail pointer. | |
325 | */ | |
6ebb6d8e | 326 | static const struct i915_oa_format hsw_oa_formats[I915_OA_FORMAT_MAX] = { |
d7965152 RB |
327 | [I915_OA_FORMAT_A13] = { 0, 64 }, |
328 | [I915_OA_FORMAT_A29] = { 1, 128 }, | |
329 | [I915_OA_FORMAT_A13_B8_C8] = { 2, 128 }, | |
330 | /* A29_B8_C8 Disallowed as 192 bytes doesn't factor into buffer size */ | |
331 | [I915_OA_FORMAT_B4_C8] = { 4, 64 }, | |
332 | [I915_OA_FORMAT_A45_B8_C8] = { 5, 256 }, | |
333 | [I915_OA_FORMAT_B4_C8_A16] = { 6, 128 }, | |
334 | [I915_OA_FORMAT_C4_B8] = { 7, 64 }, | |
335 | }; | |
336 | ||
6ebb6d8e | 337 | static const struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = { |
19f81df2 RB |
338 | [I915_OA_FORMAT_A12] = { 0, 64 }, |
339 | [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 }, | |
340 | [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 }, | |
341 | [I915_OA_FORMAT_C4_B8] = { 7, 64 }, | |
342 | }; | |
343 | ||
00a7f0d7 LL |
344 | static const struct i915_oa_format gen12_oa_formats[I915_OA_FORMAT_MAX] = { |
345 | [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 }, | |
346 | }; | |
347 | ||
d7965152 | 348 | #define SAMPLE_OA_REPORT (1<<0) |
eec688e1 | 349 | |
16d98b31 RB |
350 | /** |
351 | * struct perf_open_properties - for validated properties given to open a stream | |
352 | * @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags | |
353 | * @single_context: Whether a single or all gpu contexts should be monitored | |
9cd20ef7 LL |
354 | * @hold_preemption: Whether the preemption is disabled for the filtered |
355 | * context | |
16d98b31 RB |
356 | * @ctx_handle: A gem ctx handle for use with @single_context |
357 | * @metrics_set: An ID for an OA unit metric set advertised via sysfs | |
358 | * @oa_format: An OA unit HW report format | |
359 | * @oa_periodic: Whether to enable periodic OA unit sampling | |
360 | * @oa_period_exponent: The OA unit sampling period is derived from this | |
9a61363a | 361 | * @engine: The engine (typically rcs0) being monitored by the OA unit |
16d98b31 RB |
362 | * |
363 | * As read_properties_unlocked() enumerates and validates the properties given | |
364 | * to open a stream of metrics the configuration is built up in the structure | |
365 | * which starts out zero initialized. | |
366 | */ | |
eec688e1 RB |
367 | struct perf_open_properties { |
368 | u32 sample_flags; | |
369 | ||
370 | u64 single_context:1; | |
9cd20ef7 | 371 | u64 hold_preemption:1; |
eec688e1 | 372 | u64 ctx_handle; |
d7965152 RB |
373 | |
374 | /* OA sampling state */ | |
375 | int metrics_set; | |
376 | int oa_format; | |
377 | bool oa_periodic; | |
378 | int oa_period_exponent; | |
9a61363a LL |
379 | |
380 | struct intel_engine_cs *engine; | |
d7965152 RB |
381 | }; |
382 | ||
6a45008a LL |
383 | struct i915_oa_config_bo { |
384 | struct llist_node node; | |
385 | ||
386 | struct i915_oa_config *oa_config; | |
387 | struct i915_vma *vma; | |
388 | }; | |
389 | ||
a37f08a8 UNR |
390 | static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer); |
391 | ||
6a45008a | 392 | void i915_oa_config_release(struct kref *ref) |
f89823c2 | 393 | { |
6a45008a LL |
394 | struct i915_oa_config *oa_config = |
395 | container_of(ref, typeof(*oa_config), ref); | |
396 | ||
c2fba936 CW |
397 | kfree(oa_config->flex_regs); |
398 | kfree(oa_config->b_counter_regs); | |
399 | kfree(oa_config->mux_regs); | |
f89823c2 | 400 | |
6a45008a | 401 | kfree_rcu(oa_config, rcu); |
f89823c2 LL |
402 | } |
403 | ||
6a45008a LL |
404 | struct i915_oa_config * |
405 | i915_perf_get_oa_config(struct i915_perf *perf, int metrics_set) | |
f89823c2 | 406 | { |
6a45008a | 407 | struct i915_oa_config *oa_config; |
f89823c2 | 408 | |
6a45008a LL |
409 | rcu_read_lock(); |
410 | if (metrics_set == 1) | |
411 | oa_config = &perf->test_config; | |
f89823c2 | 412 | else |
6a45008a LL |
413 | oa_config = idr_find(&perf->metrics_idr, metrics_set); |
414 | if (oa_config) | |
415 | oa_config = i915_oa_config_get(oa_config); | |
416 | rcu_read_unlock(); | |
f89823c2 | 417 | |
6a45008a LL |
418 | return oa_config; |
419 | } | |
f89823c2 | 420 | |
6a45008a LL |
421 | static void free_oa_config_bo(struct i915_oa_config_bo *oa_bo) |
422 | { | |
423 | i915_oa_config_put(oa_bo->oa_config); | |
424 | i915_vma_put(oa_bo->vma); | |
425 | kfree(oa_bo); | |
f89823c2 LL |
426 | } |
427 | ||
00a7f0d7 LL |
428 | static u32 gen12_oa_hw_tail_read(struct i915_perf_stream *stream) |
429 | { | |
430 | struct intel_uncore *uncore = stream->uncore; | |
431 | ||
432 | return intel_uncore_read(uncore, GEN12_OAG_OATAILPTR) & | |
433 | GEN12_OAG_OATAILPTR_MASK; | |
434 | } | |
435 | ||
a37f08a8 | 436 | static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream) |
19f81df2 | 437 | { |
52111c46 | 438 | struct intel_uncore *uncore = stream->uncore; |
a37f08a8 | 439 | |
8f8b1171 | 440 | return intel_uncore_read(uncore, GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK; |
19f81df2 RB |
441 | } |
442 | ||
a37f08a8 | 443 | static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream) |
19f81df2 | 444 | { |
52111c46 | 445 | struct intel_uncore *uncore = stream->uncore; |
8f8b1171 | 446 | u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1); |
19f81df2 RB |
447 | |
448 | return oastatus1 & GEN7_OASTATUS1_TAIL_MASK; | |
449 | } | |
450 | ||
0dd860cf | 451 | /** |
19f81df2 | 452 | * oa_buffer_check_unlocked - check for data and update tail ptr state |
a37f08a8 | 453 | * @stream: i915 stream instance |
d7965152 | 454 | * |
0dd860cf RB |
455 | * This is either called via fops (for blocking reads in user ctx) or the poll |
456 | * check hrtimer (atomic ctx) to check the OA buffer tail pointer and check | |
457 | * if there is data available for userspace to read. | |
d7965152 | 458 | * |
0dd860cf RB |
459 | * This function is central to providing a workaround for the OA unit tail |
460 | * pointer having a race with respect to what data is visible to the CPU. | |
461 | * It is responsible for reading tail pointers from the hardware and giving | |
462 | * the pointers time to 'age' before they are made available for reading. | |
463 | * (See description of OA_TAIL_MARGIN_NSEC above for further details.) | |
464 | * | |
465 | * Besides returning true when there is data available to read() this function | |
466 | * also has the side effect of updating the oa_buffer.tails[], .aging_timestamp | |
467 | * and .aged_tail_idx state used for reading. | |
468 | * | |
469 | * Note: It's safe to read OA config state here unlocked, assuming that this is | |
470 | * only called while the stream is enabled, while the global OA configuration | |
471 | * can't be modified. | |
472 | * | |
473 | * Returns: %true if the OA buffer contains data, else %false | |
d7965152 | 474 | */ |
a37f08a8 | 475 | static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream) |
d7965152 | 476 | { |
a37f08a8 | 477 | int report_size = stream->oa_buffer.format_size; |
0dd860cf RB |
478 | unsigned long flags; |
479 | unsigned int aged_idx; | |
0dd860cf RB |
480 | u32 head, hw_tail, aged_tail, aging_tail; |
481 | u64 now; | |
482 | ||
483 | /* We have to consider the (unlikely) possibility that read() errors | |
484 | * could result in an OA buffer reset which might reset the head, | |
485 | * tails[] and aged_tail state. | |
486 | */ | |
a37f08a8 | 487 | spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags); |
0dd860cf RB |
488 | |
489 | /* NB: The head we observe here might effectively be a little out of | |
490 | * date (between head and tails[aged_idx].offset if there is currently | |
491 | * a read() in progress. | |
492 | */ | |
a37f08a8 | 493 | head = stream->oa_buffer.head; |
0dd860cf | 494 | |
a37f08a8 UNR |
495 | aged_idx = stream->oa_buffer.aged_tail_idx; |
496 | aged_tail = stream->oa_buffer.tails[aged_idx].offset; | |
497 | aging_tail = stream->oa_buffer.tails[!aged_idx].offset; | |
0dd860cf | 498 | |
8f8b1171 | 499 | hw_tail = stream->perf->ops.oa_hw_tail_read(stream); |
0dd860cf RB |
500 | |
501 | /* The tail pointer increases in 64 byte increments, | |
502 | * not in report_size steps... | |
503 | */ | |
504 | hw_tail &= ~(report_size - 1); | |
505 | ||
506 | now = ktime_get_mono_fast_ns(); | |
507 | ||
4117ebc7 RB |
508 | /* Update the aged tail |
509 | * | |
510 | * Flip the tail pointer available for read()s once the aging tail is | |
511 | * old enough to trust that the corresponding data will be visible to | |
512 | * the CPU... | |
513 | * | |
514 | * Do this before updating the aging pointer in case we may be able to | |
515 | * immediately start aging a new pointer too (if new data has become | |
516 | * available) without needing to wait for a later hrtimer callback. | |
517 | */ | |
518 | if (aging_tail != INVALID_TAIL_PTR && | |
a37f08a8 | 519 | ((now - stream->oa_buffer.aging_timestamp) > |
4117ebc7 | 520 | OA_TAIL_MARGIN_NSEC)) { |
19f81df2 | 521 | |
4117ebc7 | 522 | aged_idx ^= 1; |
a37f08a8 | 523 | stream->oa_buffer.aged_tail_idx = aged_idx; |
4117ebc7 RB |
524 | |
525 | aged_tail = aging_tail; | |
526 | ||
527 | /* Mark that we need a new pointer to start aging... */ | |
a37f08a8 | 528 | stream->oa_buffer.tails[!aged_idx].offset = INVALID_TAIL_PTR; |
4117ebc7 RB |
529 | aging_tail = INVALID_TAIL_PTR; |
530 | } | |
531 | ||
0dd860cf RB |
532 | /* Update the aging tail |
533 | * | |
534 | * We throttle aging tail updates until we have a new tail that | |
535 | * represents >= one report more data than is already available for | |
536 | * reading. This ensures there will be enough data for a successful | |
537 | * read once this new pointer has aged and ensures we will give the new | |
538 | * pointer time to age. | |
539 | */ | |
540 | if (aging_tail == INVALID_TAIL_PTR && | |
541 | (aged_tail == INVALID_TAIL_PTR || | |
542 | OA_TAKEN(hw_tail, aged_tail) >= report_size)) { | |
a37f08a8 | 543 | struct i915_vma *vma = stream->oa_buffer.vma; |
0dd860cf RB |
544 | u32 gtt_offset = i915_ggtt_offset(vma); |
545 | ||
546 | /* Be paranoid and do a bounds check on the pointer read back | |
547 | * from hardware, just in case some spurious hardware condition | |
548 | * could put the tail out of bounds... | |
549 | */ | |
550 | if (hw_tail >= gtt_offset && | |
fe841686 | 551 | hw_tail < (gtt_offset + OA_BUFFER_SIZE)) { |
a37f08a8 | 552 | stream->oa_buffer.tails[!aged_idx].offset = |
0dd860cf | 553 | aging_tail = hw_tail; |
a37f08a8 | 554 | stream->oa_buffer.aging_timestamp = now; |
0dd860cf | 555 | } else { |
00a7f0d7 | 556 | DRM_ERROR("Ignoring spurious out of range OA buffer tail pointer = %x\n", |
0dd860cf RB |
557 | hw_tail); |
558 | } | |
559 | } | |
560 | ||
a37f08a8 | 561 | spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags); |
0dd860cf RB |
562 | |
563 | return aged_tail == INVALID_TAIL_PTR ? | |
564 | false : OA_TAKEN(aged_tail, head) >= report_size; | |
d7965152 RB |
565 | } |
566 | ||
567 | /** | |
16d98b31 RB |
568 | * append_oa_status - Appends a status record to a userspace read() buffer. |
569 | * @stream: An i915-perf stream opened for OA metrics | |
570 | * @buf: destination buffer given by userspace | |
571 | * @count: the number of bytes userspace wants to read | |
572 | * @offset: (inout): the current position for writing into @buf | |
573 | * @type: The kind of status to report to userspace | |
574 | * | |
575 | * Writes a status record (such as `DRM_I915_PERF_RECORD_OA_REPORT_LOST`) | |
576 | * into the userspace read() buffer. | |
577 | * | |
578 | * The @buf @offset will only be updated on success. | |
579 | * | |
580 | * Returns: 0 on success, negative error code on failure. | |
d7965152 RB |
581 | */ |
582 | static int append_oa_status(struct i915_perf_stream *stream, | |
583 | char __user *buf, | |
584 | size_t count, | |
585 | size_t *offset, | |
586 | enum drm_i915_perf_record_type type) | |
587 | { | |
588 | struct drm_i915_perf_record_header header = { type, 0, sizeof(header) }; | |
589 | ||
590 | if ((count - *offset) < header.size) | |
591 | return -ENOSPC; | |
592 | ||
593 | if (copy_to_user(buf + *offset, &header, sizeof(header))) | |
594 | return -EFAULT; | |
595 | ||
596 | (*offset) += header.size; | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | /** | |
16d98b31 RB |
602 | * append_oa_sample - Copies single OA report into userspace read() buffer. |
603 | * @stream: An i915-perf stream opened for OA metrics | |
604 | * @buf: destination buffer given by userspace | |
605 | * @count: the number of bytes userspace wants to read | |
606 | * @offset: (inout): the current position for writing into @buf | |
607 | * @report: A single OA report to (optionally) include as part of the sample | |
608 | * | |
609 | * The contents of a sample are configured through `DRM_I915_PERF_PROP_SAMPLE_*` | |
610 | * properties when opening a stream, tracked as `stream->sample_flags`. This | |
611 | * function copies the requested components of a single sample to the given | |
612 | * read() @buf. | |
613 | * | |
614 | * The @buf @offset will only be updated on success. | |
615 | * | |
616 | * Returns: 0 on success, negative error code on failure. | |
d7965152 RB |
617 | */ |
618 | static int append_oa_sample(struct i915_perf_stream *stream, | |
619 | char __user *buf, | |
620 | size_t count, | |
621 | size_t *offset, | |
622 | const u8 *report) | |
623 | { | |
a37f08a8 | 624 | int report_size = stream->oa_buffer.format_size; |
d7965152 RB |
625 | struct drm_i915_perf_record_header header; |
626 | u32 sample_flags = stream->sample_flags; | |
627 | ||
628 | header.type = DRM_I915_PERF_RECORD_SAMPLE; | |
629 | header.pad = 0; | |
630 | header.size = stream->sample_size; | |
631 | ||
632 | if ((count - *offset) < header.size) | |
633 | return -ENOSPC; | |
634 | ||
635 | buf += *offset; | |
636 | if (copy_to_user(buf, &header, sizeof(header))) | |
637 | return -EFAULT; | |
638 | buf += sizeof(header); | |
639 | ||
640 | if (sample_flags & SAMPLE_OA_REPORT) { | |
641 | if (copy_to_user(buf, report, report_size)) | |
642 | return -EFAULT; | |
643 | } | |
644 | ||
645 | (*offset) += header.size; | |
646 | ||
647 | return 0; | |
648 | } | |
649 | ||
19f81df2 RB |
650 | /** |
651 | * Copies all buffered OA reports into userspace read() buffer. | |
652 | * @stream: An i915-perf stream opened for OA metrics | |
653 | * @buf: destination buffer given by userspace | |
654 | * @count: the number of bytes userspace wants to read | |
655 | * @offset: (inout): the current position for writing into @buf | |
656 | * | |
657 | * Notably any error condition resulting in a short read (-%ENOSPC or | |
658 | * -%EFAULT) will be returned even though one or more records may | |
659 | * have been successfully copied. In this case it's up to the caller | |
660 | * to decide if the error should be squashed before returning to | |
661 | * userspace. | |
662 | * | |
663 | * Note: reports are consumed from the head, and appended to the | |
664 | * tail, so the tail chases the head?... If you think that's mad | |
665 | * and back-to-front you're not alone, but this follows the | |
666 | * Gen PRM naming convention. | |
667 | * | |
668 | * Returns: 0 on success, negative error code on failure. | |
669 | */ | |
670 | static int gen8_append_oa_reports(struct i915_perf_stream *stream, | |
671 | char __user *buf, | |
672 | size_t count, | |
673 | size_t *offset) | |
674 | { | |
52111c46 | 675 | struct intel_uncore *uncore = stream->uncore; |
a37f08a8 UNR |
676 | int report_size = stream->oa_buffer.format_size; |
677 | u8 *oa_buf_base = stream->oa_buffer.vaddr; | |
678 | u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); | |
fe841686 | 679 | u32 mask = (OA_BUFFER_SIZE - 1); |
19f81df2 RB |
680 | size_t start_offset = *offset; |
681 | unsigned long flags; | |
682 | unsigned int aged_tail_idx; | |
683 | u32 head, tail; | |
684 | u32 taken; | |
685 | int ret = 0; | |
686 | ||
687 | if (WARN_ON(!stream->enabled)) | |
688 | return -EIO; | |
689 | ||
a37f08a8 | 690 | spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags); |
19f81df2 | 691 | |
a37f08a8 UNR |
692 | head = stream->oa_buffer.head; |
693 | aged_tail_idx = stream->oa_buffer.aged_tail_idx; | |
694 | tail = stream->oa_buffer.tails[aged_tail_idx].offset; | |
19f81df2 | 695 | |
a37f08a8 | 696 | spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags); |
19f81df2 RB |
697 | |
698 | /* | |
699 | * An invalid tail pointer here means we're still waiting for the poll | |
700 | * hrtimer callback to give us a pointer | |
701 | */ | |
702 | if (tail == INVALID_TAIL_PTR) | |
703 | return -EAGAIN; | |
704 | ||
705 | /* | |
706 | * NB: oa_buffer.head/tail include the gtt_offset which we don't want | |
707 | * while indexing relative to oa_buf_base. | |
708 | */ | |
709 | head -= gtt_offset; | |
710 | tail -= gtt_offset; | |
711 | ||
712 | /* | |
713 | * An out of bounds or misaligned head or tail pointer implies a driver | |
714 | * bug since we validate + align the tail pointers we read from the | |
715 | * hardware and we are in full control of the head pointer which should | |
716 | * only be incremented by multiples of the report size (notably also | |
717 | * all a power of two). | |
718 | */ | |
fe841686 JL |
719 | if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size || |
720 | tail > OA_BUFFER_SIZE || tail % report_size, | |
19f81df2 RB |
721 | "Inconsistent OA buffer pointers: head = %u, tail = %u\n", |
722 | head, tail)) | |
723 | return -EIO; | |
724 | ||
725 | ||
726 | for (/* none */; | |
727 | (taken = OA_TAKEN(tail, head)); | |
728 | head = (head + report_size) & mask) { | |
729 | u8 *report = oa_buf_base + head; | |
730 | u32 *report32 = (void *)report; | |
731 | u32 ctx_id; | |
732 | u32 reason; | |
733 | ||
734 | /* | |
735 | * All the report sizes factor neatly into the buffer | |
736 | * size so we never expect to see a report split | |
737 | * between the beginning and end of the buffer. | |
738 | * | |
739 | * Given the initial alignment check a misalignment | |
740 | * here would imply a driver bug that would result | |
741 | * in an overrun. | |
742 | */ | |
fe841686 | 743 | if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) { |
19f81df2 RB |
744 | DRM_ERROR("Spurious OA head ptr: non-integral report offset\n"); |
745 | break; | |
746 | } | |
747 | ||
748 | /* | |
749 | * The reason field includes flags identifying what | |
750 | * triggered this specific report (mostly timer | |
751 | * triggered or e.g. due to a context switch). | |
752 | * | |
753 | * This field is never expected to be zero so we can | |
754 | * check that the report isn't invalid before copying | |
755 | * it to userspace... | |
756 | */ | |
757 | reason = ((report32[0] >> OAREPORT_REASON_SHIFT) & | |
00a7f0d7 LL |
758 | (IS_GEN(stream->perf->i915, 12) ? |
759 | OAREPORT_REASON_MASK_EXTENDED : | |
760 | OAREPORT_REASON_MASK)); | |
19f81df2 | 761 | if (reason == 0) { |
8f8b1171 | 762 | if (__ratelimit(&stream->perf->spurious_report_rs)) |
19f81df2 RB |
763 | DRM_NOTE("Skipping spurious, invalid OA report\n"); |
764 | continue; | |
765 | } | |
766 | ||
a37f08a8 | 767 | ctx_id = report32[2] & stream->specific_ctx_id_mask; |
19f81df2 RB |
768 | |
769 | /* | |
770 | * Squash whatever is in the CTX_ID field if it's marked as | |
771 | * invalid to be sure we avoid false-positive, single-context | |
772 | * filtering below... | |
773 | * | |
774 | * Note: that we don't clear the valid_ctx_bit so userspace can | |
775 | * understand that the ID has been squashed by the kernel. | |
776 | */ | |
00a7f0d7 LL |
777 | if (!(report32[0] & stream->perf->gen8_valid_ctx_bit) && |
778 | INTEL_GEN(stream->perf->i915) <= 11) | |
19f81df2 RB |
779 | ctx_id = report32[2] = INVALID_CTX_ID; |
780 | ||
781 | /* | |
782 | * NB: For Gen 8 the OA unit no longer supports clock gating | |
783 | * off for a specific context and the kernel can't securely | |
784 | * stop the counters from updating as system-wide / global | |
785 | * values. | |
786 | * | |
787 | * Automatic reports now include a context ID so reports can be | |
788 | * filtered on the cpu but it's not worth trying to | |
789 | * automatically subtract/hide counter progress for other | |
790 | * contexts while filtering since we can't stop userspace | |
791 | * issuing MI_REPORT_PERF_COUNT commands which would still | |
792 | * provide a side-band view of the real values. | |
793 | * | |
794 | * To allow userspace (such as Mesa/GL_INTEL_performance_query) | |
795 | * to normalize counters for a single filtered context then it | |
796 | * needs be forwarded bookend context-switch reports so that it | |
797 | * can track switches in between MI_REPORT_PERF_COUNT commands | |
798 | * and can itself subtract/ignore the progress of counters | |
799 | * associated with other contexts. Note that the hardware | |
800 | * automatically triggers reports when switching to a new | |
801 | * context which are tagged with the ID of the newly active | |
802 | * context. To avoid the complexity (and likely fragility) of | |
803 | * reading ahead while parsing reports to try and minimize | |
804 | * forwarding redundant context switch reports (i.e. between | |
805 | * other, unrelated contexts) we simply elect to forward them | |
806 | * all. | |
807 | * | |
808 | * We don't rely solely on the reason field to identify context | |
809 | * switches since it's not-uncommon for periodic samples to | |
810 | * identify a switch before any 'context switch' report. | |
811 | */ | |
8f8b1171 | 812 | if (!stream->perf->exclusive_stream->ctx || |
a37f08a8 UNR |
813 | stream->specific_ctx_id == ctx_id || |
814 | stream->oa_buffer.last_ctx_id == stream->specific_ctx_id || | |
19f81df2 RB |
815 | reason & OAREPORT_REASON_CTX_SWITCH) { |
816 | ||
817 | /* | |
818 | * While filtering for a single context we avoid | |
819 | * leaking the IDs of other contexts. | |
820 | */ | |
8f8b1171 | 821 | if (stream->perf->exclusive_stream->ctx && |
a37f08a8 | 822 | stream->specific_ctx_id != ctx_id) { |
19f81df2 RB |
823 | report32[2] = INVALID_CTX_ID; |
824 | } | |
825 | ||
826 | ret = append_oa_sample(stream, buf, count, offset, | |
827 | report); | |
828 | if (ret) | |
829 | break; | |
830 | ||
a37f08a8 | 831 | stream->oa_buffer.last_ctx_id = ctx_id; |
19f81df2 RB |
832 | } |
833 | ||
834 | /* | |
835 | * The above reason field sanity check is based on | |
836 | * the assumption that the OA buffer is initially | |
837 | * zeroed and we reset the field after copying so the | |
838 | * check is still meaningful once old reports start | |
839 | * being overwritten. | |
840 | */ | |
841 | report32[0] = 0; | |
842 | } | |
843 | ||
844 | if (start_offset != *offset) { | |
00a7f0d7 LL |
845 | i915_reg_t oaheadptr; |
846 | ||
847 | oaheadptr = IS_GEN(stream->perf->i915, 12) ? | |
848 | GEN12_OAG_OAHEADPTR : GEN8_OAHEADPTR; | |
849 | ||
a37f08a8 | 850 | spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags); |
19f81df2 RB |
851 | |
852 | /* | |
853 | * We removed the gtt_offset for the copy loop above, indexing | |
854 | * relative to oa_buf_base so put back here... | |
855 | */ | |
856 | head += gtt_offset; | |
00a7f0d7 LL |
857 | intel_uncore_write(uncore, oaheadptr, |
858 | head & GEN12_OAG_OAHEADPTR_MASK); | |
a37f08a8 | 859 | stream->oa_buffer.head = head; |
19f81df2 | 860 | |
a37f08a8 | 861 | spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags); |
19f81df2 RB |
862 | } |
863 | ||
864 | return ret; | |
865 | } | |
866 | ||
867 | /** | |
868 | * gen8_oa_read - copy status records then buffered OA reports | |
869 | * @stream: An i915-perf stream opened for OA metrics | |
870 | * @buf: destination buffer given by userspace | |
871 | * @count: the number of bytes userspace wants to read | |
872 | * @offset: (inout): the current position for writing into @buf | |
873 | * | |
874 | * Checks OA unit status registers and if necessary appends corresponding | |
875 | * status records for userspace (such as for a buffer full condition) and then | |
876 | * initiate appending any buffered OA reports. | |
877 | * | |
878 | * Updates @offset according to the number of bytes successfully copied into | |
879 | * the userspace buffer. | |
880 | * | |
881 | * NB: some data may be successfully copied to the userspace buffer | |
882 | * even if an error is returned, and this is reflected in the | |
883 | * updated @offset. | |
884 | * | |
885 | * Returns: zero on success or a negative error code | |
886 | */ | |
887 | static int gen8_oa_read(struct i915_perf_stream *stream, | |
888 | char __user *buf, | |
889 | size_t count, | |
890 | size_t *offset) | |
891 | { | |
52111c46 | 892 | struct intel_uncore *uncore = stream->uncore; |
19f81df2 | 893 | u32 oastatus; |
00a7f0d7 | 894 | i915_reg_t oastatus_reg; |
19f81df2 RB |
895 | int ret; |
896 | ||
a37f08a8 | 897 | if (WARN_ON(!stream->oa_buffer.vaddr)) |
19f81df2 RB |
898 | return -EIO; |
899 | ||
00a7f0d7 LL |
900 | oastatus_reg = IS_GEN(stream->perf->i915, 12) ? |
901 | GEN12_OAG_OASTATUS : GEN8_OASTATUS; | |
902 | ||
903 | oastatus = intel_uncore_read(uncore, oastatus_reg); | |
19f81df2 RB |
904 | |
905 | /* | |
906 | * We treat OABUFFER_OVERFLOW as a significant error: | |
907 | * | |
908 | * Although theoretically we could handle this more gracefully | |
909 | * sometimes, some Gens don't correctly suppress certain | |
910 | * automatically triggered reports in this condition and so we | |
911 | * have to assume that old reports are now being trampled | |
912 | * over. | |
fe841686 JL |
913 | * |
914 | * Considering how we don't currently give userspace control | |
915 | * over the OA buffer size and always configure a large 16MB | |
916 | * buffer, then a buffer overflow does anyway likely indicate | |
917 | * that something has gone quite badly wrong. | |
19f81df2 RB |
918 | */ |
919 | if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) { | |
920 | ret = append_oa_status(stream, buf, count, offset, | |
921 | DRM_I915_PERF_RECORD_OA_BUFFER_LOST); | |
922 | if (ret) | |
923 | return ret; | |
924 | ||
925 | DRM_DEBUG("OA buffer overflow (exponent = %d): force restart\n", | |
a37f08a8 | 926 | stream->period_exponent); |
19f81df2 | 927 | |
8f8b1171 CW |
928 | stream->perf->ops.oa_disable(stream); |
929 | stream->perf->ops.oa_enable(stream); | |
19f81df2 RB |
930 | |
931 | /* | |
932 | * Note: .oa_enable() is expected to re-init the oabuffer and | |
933 | * reset GEN8_OASTATUS for us | |
934 | */ | |
00a7f0d7 | 935 | oastatus = intel_uncore_read(uncore, oastatus_reg); |
19f81df2 RB |
936 | } |
937 | ||
938 | if (oastatus & GEN8_OASTATUS_REPORT_LOST) { | |
939 | ret = append_oa_status(stream, buf, count, offset, | |
940 | DRM_I915_PERF_RECORD_OA_REPORT_LOST); | |
941 | if (ret) | |
942 | return ret; | |
00a7f0d7 | 943 | intel_uncore_write(uncore, oastatus_reg, |
8f8b1171 | 944 | oastatus & ~GEN8_OASTATUS_REPORT_LOST); |
19f81df2 RB |
945 | } |
946 | ||
947 | return gen8_append_oa_reports(stream, buf, count, offset); | |
948 | } | |
949 | ||
d7965152 RB |
950 | /** |
951 | * Copies all buffered OA reports into userspace read() buffer. | |
952 | * @stream: An i915-perf stream opened for OA metrics | |
953 | * @buf: destination buffer given by userspace | |
954 | * @count: the number of bytes userspace wants to read | |
955 | * @offset: (inout): the current position for writing into @buf | |
d7965152 | 956 | * |
16d98b31 RB |
957 | * Notably any error condition resulting in a short read (-%ENOSPC or |
958 | * -%EFAULT) will be returned even though one or more records may | |
d7965152 RB |
959 | * have been successfully copied. In this case it's up to the caller |
960 | * to decide if the error should be squashed before returning to | |
961 | * userspace. | |
962 | * | |
963 | * Note: reports are consumed from the head, and appended to the | |
e81b3a55 | 964 | * tail, so the tail chases the head?... If you think that's mad |
d7965152 RB |
965 | * and back-to-front you're not alone, but this follows the |
966 | * Gen PRM naming convention. | |
16d98b31 RB |
967 | * |
968 | * Returns: 0 on success, negative error code on failure. | |
d7965152 RB |
969 | */ |
970 | static int gen7_append_oa_reports(struct i915_perf_stream *stream, | |
971 | char __user *buf, | |
972 | size_t count, | |
3bb335c1 | 973 | size_t *offset) |
d7965152 | 974 | { |
52111c46 | 975 | struct intel_uncore *uncore = stream->uncore; |
a37f08a8 UNR |
976 | int report_size = stream->oa_buffer.format_size; |
977 | u8 *oa_buf_base = stream->oa_buffer.vaddr; | |
978 | u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); | |
fe841686 | 979 | u32 mask = (OA_BUFFER_SIZE - 1); |
3bb335c1 | 980 | size_t start_offset = *offset; |
0dd860cf RB |
981 | unsigned long flags; |
982 | unsigned int aged_tail_idx; | |
983 | u32 head, tail; | |
d7965152 RB |
984 | u32 taken; |
985 | int ret = 0; | |
986 | ||
987 | if (WARN_ON(!stream->enabled)) | |
988 | return -EIO; | |
989 | ||
a37f08a8 | 990 | spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags); |
f279020a | 991 | |
a37f08a8 UNR |
992 | head = stream->oa_buffer.head; |
993 | aged_tail_idx = stream->oa_buffer.aged_tail_idx; | |
994 | tail = stream->oa_buffer.tails[aged_tail_idx].offset; | |
f279020a | 995 | |
a37f08a8 | 996 | spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags); |
d7965152 | 997 | |
0dd860cf RB |
998 | /* An invalid tail pointer here means we're still waiting for the poll |
999 | * hrtimer callback to give us a pointer | |
d7965152 | 1000 | */ |
0dd860cf RB |
1001 | if (tail == INVALID_TAIL_PTR) |
1002 | return -EAGAIN; | |
d7965152 | 1003 | |
0dd860cf RB |
1004 | /* NB: oa_buffer.head/tail include the gtt_offset which we don't want |
1005 | * while indexing relative to oa_buf_base. | |
d7965152 | 1006 | */ |
0dd860cf RB |
1007 | head -= gtt_offset; |
1008 | tail -= gtt_offset; | |
d7965152 | 1009 | |
0dd860cf RB |
1010 | /* An out of bounds or misaligned head or tail pointer implies a driver |
1011 | * bug since we validate + align the tail pointers we read from the | |
1012 | * hardware and we are in full control of the head pointer which should | |
1013 | * only be incremented by multiples of the report size (notably also | |
1014 | * all a power of two). | |
d7965152 | 1015 | */ |
fe841686 JL |
1016 | if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size || |
1017 | tail > OA_BUFFER_SIZE || tail % report_size, | |
0dd860cf RB |
1018 | "Inconsistent OA buffer pointers: head = %u, tail = %u\n", |
1019 | head, tail)) | |
1020 | return -EIO; | |
d7965152 | 1021 | |
d7965152 RB |
1022 | |
1023 | for (/* none */; | |
1024 | (taken = OA_TAKEN(tail, head)); | |
1025 | head = (head + report_size) & mask) { | |
1026 | u8 *report = oa_buf_base + head; | |
1027 | u32 *report32 = (void *)report; | |
1028 | ||
1029 | /* All the report sizes factor neatly into the buffer | |
1030 | * size so we never expect to see a report split | |
1031 | * between the beginning and end of the buffer. | |
1032 | * | |
1033 | * Given the initial alignment check a misalignment | |
1034 | * here would imply a driver bug that would result | |
1035 | * in an overrun. | |
1036 | */ | |
fe841686 | 1037 | if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) { |
d7965152 RB |
1038 | DRM_ERROR("Spurious OA head ptr: non-integral report offset\n"); |
1039 | break; | |
1040 | } | |
1041 | ||
1042 | /* The report-ID field for periodic samples includes | |
1043 | * some undocumented flags related to what triggered | |
1044 | * the report and is never expected to be zero so we | |
1045 | * can check that the report isn't invalid before | |
1046 | * copying it to userspace... | |
1047 | */ | |
1048 | if (report32[0] == 0) { | |
8f8b1171 | 1049 | if (__ratelimit(&stream->perf->spurious_report_rs)) |
712122ea | 1050 | DRM_NOTE("Skipping spurious, invalid OA report\n"); |
d7965152 RB |
1051 | continue; |
1052 | } | |
1053 | ||
1054 | ret = append_oa_sample(stream, buf, count, offset, report); | |
1055 | if (ret) | |
1056 | break; | |
1057 | ||
1058 | /* The above report-id field sanity check is based on | |
1059 | * the assumption that the OA buffer is initially | |
1060 | * zeroed and we reset the field after copying so the | |
1061 | * check is still meaningful once old reports start | |
1062 | * being overwritten. | |
1063 | */ | |
1064 | report32[0] = 0; | |
1065 | } | |
1066 | ||
3bb335c1 | 1067 | if (start_offset != *offset) { |
a37f08a8 | 1068 | spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags); |
0dd860cf | 1069 | |
3bb335c1 RB |
1070 | /* We removed the gtt_offset for the copy loop above, indexing |
1071 | * relative to oa_buf_base so put back here... | |
1072 | */ | |
1073 | head += gtt_offset; | |
1074 | ||
8f8b1171 CW |
1075 | intel_uncore_write(uncore, GEN7_OASTATUS2, |
1076 | (head & GEN7_OASTATUS2_HEAD_MASK) | | |
1077 | GEN7_OASTATUS2_MEM_SELECT_GGTT); | |
a37f08a8 | 1078 | stream->oa_buffer.head = head; |
0dd860cf | 1079 | |
a37f08a8 | 1080 | spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags); |
3bb335c1 | 1081 | } |
d7965152 RB |
1082 | |
1083 | return ret; | |
1084 | } | |
1085 | ||
16d98b31 RB |
1086 | /** |
1087 | * gen7_oa_read - copy status records then buffered OA reports | |
1088 | * @stream: An i915-perf stream opened for OA metrics | |
1089 | * @buf: destination buffer given by userspace | |
1090 | * @count: the number of bytes userspace wants to read | |
1091 | * @offset: (inout): the current position for writing into @buf | |
1092 | * | |
1093 | * Checks Gen 7 specific OA unit status registers and if necessary appends | |
1094 | * corresponding status records for userspace (such as for a buffer full | |
1095 | * condition) and then initiate appending any buffered OA reports. | |
1096 | * | |
1097 | * Updates @offset according to the number of bytes successfully copied into | |
1098 | * the userspace buffer. | |
1099 | * | |
1100 | * Returns: zero on success or a negative error code | |
1101 | */ | |
d7965152 RB |
1102 | static int gen7_oa_read(struct i915_perf_stream *stream, |
1103 | char __user *buf, | |
1104 | size_t count, | |
1105 | size_t *offset) | |
1106 | { | |
52111c46 | 1107 | struct intel_uncore *uncore = stream->uncore; |
d7965152 | 1108 | u32 oastatus1; |
d7965152 RB |
1109 | int ret; |
1110 | ||
a37f08a8 | 1111 | if (WARN_ON(!stream->oa_buffer.vaddr)) |
d7965152 RB |
1112 | return -EIO; |
1113 | ||
8f8b1171 | 1114 | oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1); |
d7965152 | 1115 | |
d7965152 RB |
1116 | /* XXX: On Haswell we don't have a safe way to clear oastatus1 |
1117 | * bits while the OA unit is enabled (while the tail pointer | |
1118 | * may be updated asynchronously) so we ignore status bits | |
1119 | * that have already been reported to userspace. | |
1120 | */ | |
8f8b1171 | 1121 | oastatus1 &= ~stream->perf->gen7_latched_oastatus1; |
d7965152 RB |
1122 | |
1123 | /* We treat OABUFFER_OVERFLOW as a significant error: | |
1124 | * | |
1125 | * - The status can be interpreted to mean that the buffer is | |
1126 | * currently full (with a higher precedence than OA_TAKEN() | |
1127 | * which will start to report a near-empty buffer after an | |
1128 | * overflow) but it's awkward that we can't clear the status | |
1129 | * on Haswell, so without a reset we won't be able to catch | |
1130 | * the state again. | |
1131 | * | |
1132 | * - Since it also implies the HW has started overwriting old | |
1133 | * reports it may also affect our sanity checks for invalid | |
1134 | * reports when copying to userspace that assume new reports | |
1135 | * are being written to cleared memory. | |
1136 | * | |
1137 | * - In the future we may want to introduce a flight recorder | |
1138 | * mode where the driver will automatically maintain a safe | |
1139 | * guard band between head/tail, avoiding this overflow | |
1140 | * condition, but we avoid the added driver complexity for | |
1141 | * now. | |
1142 | */ | |
1143 | if (unlikely(oastatus1 & GEN7_OASTATUS1_OABUFFER_OVERFLOW)) { | |
1144 | ret = append_oa_status(stream, buf, count, offset, | |
1145 | DRM_I915_PERF_RECORD_OA_BUFFER_LOST); | |
1146 | if (ret) | |
1147 | return ret; | |
1148 | ||
19f81df2 | 1149 | DRM_DEBUG("OA buffer overflow (exponent = %d): force restart\n", |
a37f08a8 | 1150 | stream->period_exponent); |
d7965152 | 1151 | |
8f8b1171 CW |
1152 | stream->perf->ops.oa_disable(stream); |
1153 | stream->perf->ops.oa_enable(stream); | |
d7965152 | 1154 | |
8f8b1171 | 1155 | oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1); |
d7965152 RB |
1156 | } |
1157 | ||
1158 | if (unlikely(oastatus1 & GEN7_OASTATUS1_REPORT_LOST)) { | |
1159 | ret = append_oa_status(stream, buf, count, offset, | |
1160 | DRM_I915_PERF_RECORD_OA_REPORT_LOST); | |
1161 | if (ret) | |
1162 | return ret; | |
8f8b1171 | 1163 | stream->perf->gen7_latched_oastatus1 |= |
d7965152 RB |
1164 | GEN7_OASTATUS1_REPORT_LOST; |
1165 | } | |
1166 | ||
3bb335c1 | 1167 | return gen7_append_oa_reports(stream, buf, count, offset); |
d7965152 RB |
1168 | } |
1169 | ||
16d98b31 RB |
1170 | /** |
1171 | * i915_oa_wait_unlocked - handles blocking IO until OA data available | |
1172 | * @stream: An i915-perf stream opened for OA metrics | |
1173 | * | |
1174 | * Called when userspace tries to read() from a blocking stream FD opened | |
1175 | * for OA metrics. It waits until the hrtimer callback finds a non-empty | |
1176 | * OA buffer and wakes us. | |
1177 | * | |
1178 | * Note: it's acceptable to have this return with some false positives | |
1179 | * since any subsequent read handling will return -EAGAIN if there isn't | |
1180 | * really data ready for userspace yet. | |
1181 | * | |
1182 | * Returns: zero on success or a negative error code | |
1183 | */ | |
d7965152 RB |
1184 | static int i915_oa_wait_unlocked(struct i915_perf_stream *stream) |
1185 | { | |
d7965152 | 1186 | /* We would wait indefinitely if periodic sampling is not enabled */ |
a37f08a8 | 1187 | if (!stream->periodic) |
d7965152 RB |
1188 | return -EIO; |
1189 | ||
a37f08a8 UNR |
1190 | return wait_event_interruptible(stream->poll_wq, |
1191 | oa_buffer_check_unlocked(stream)); | |
d7965152 RB |
1192 | } |
1193 | ||
16d98b31 RB |
1194 | /** |
1195 | * i915_oa_poll_wait - call poll_wait() for an OA stream poll() | |
1196 | * @stream: An i915-perf stream opened for OA metrics | |
1197 | * @file: An i915 perf stream file | |
1198 | * @wait: poll() state table | |
1199 | * | |
1200 | * For handling userspace polling on an i915 perf stream opened for OA metrics, | |
1201 | * this starts a poll_wait with the wait queue that our hrtimer callback wakes | |
1202 | * when it sees data ready to read in the circular OA buffer. | |
1203 | */ | |
d7965152 RB |
1204 | static void i915_oa_poll_wait(struct i915_perf_stream *stream, |
1205 | struct file *file, | |
1206 | poll_table *wait) | |
1207 | { | |
a37f08a8 | 1208 | poll_wait(file, &stream->poll_wq, wait); |
d7965152 RB |
1209 | } |
1210 | ||
16d98b31 RB |
1211 | /** |
1212 | * i915_oa_read - just calls through to &i915_oa_ops->read | |
1213 | * @stream: An i915-perf stream opened for OA metrics | |
1214 | * @buf: destination buffer given by userspace | |
1215 | * @count: the number of bytes userspace wants to read | |
1216 | * @offset: (inout): the current position for writing into @buf | |
1217 | * | |
1218 | * Updates @offset according to the number of bytes successfully copied into | |
1219 | * the userspace buffer. | |
1220 | * | |
1221 | * Returns: zero on success or a negative error code | |
1222 | */ | |
d7965152 RB |
1223 | static int i915_oa_read(struct i915_perf_stream *stream, |
1224 | char __user *buf, | |
1225 | size_t count, | |
1226 | size_t *offset) | |
1227 | { | |
8f8b1171 | 1228 | return stream->perf->ops.read(stream, buf, count, offset); |
d7965152 RB |
1229 | } |
1230 | ||
a37f08a8 | 1231 | static struct intel_context *oa_pin_context(struct i915_perf_stream *stream) |
61d5676b | 1232 | { |
5e2a0419 | 1233 | struct i915_gem_engines_iter it; |
a37f08a8 | 1234 | struct i915_gem_context *ctx = stream->ctx; |
61d5676b | 1235 | struct intel_context *ce; |
fa9f6681 | 1236 | int err; |
61d5676b | 1237 | |
5e2a0419 | 1238 | for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) { |
9a61363a | 1239 | if (ce->engine != stream->engine) /* first match! */ |
5e2a0419 CW |
1240 | continue; |
1241 | ||
1242 | /* | |
1243 | * As the ID is the gtt offset of the context's vma we | |
1244 | * pin the vma to ensure the ID remains fixed. | |
1245 | */ | |
1246 | err = intel_context_pin(ce); | |
1247 | if (err == 0) { | |
a37f08a8 | 1248 | stream->pinned_ctx = ce; |
5e2a0419 CW |
1249 | break; |
1250 | } | |
fa9f6681 | 1251 | } |
5e2a0419 | 1252 | i915_gem_context_unlock_engines(ctx); |
61d5676b | 1253 | |
a37f08a8 | 1254 | return stream->pinned_ctx; |
61d5676b LL |
1255 | } |
1256 | ||
16d98b31 RB |
1257 | /** |
1258 | * oa_get_render_ctx_id - determine and hold ctx hw id | |
1259 | * @stream: An i915-perf stream opened for OA metrics | |
1260 | * | |
1261 | * Determine the render context hw id, and ensure it remains fixed for the | |
d7965152 RB |
1262 | * lifetime of the stream. This ensures that we don't have to worry about |
1263 | * updating the context ID in OACONTROL on the fly. | |
16d98b31 RB |
1264 | * |
1265 | * Returns: zero on success or a negative error code | |
d7965152 RB |
1266 | */ |
1267 | static int oa_get_render_ctx_id(struct i915_perf_stream *stream) | |
1268 | { | |
61d5676b | 1269 | struct intel_context *ce; |
d7965152 | 1270 | |
a37f08a8 | 1271 | ce = oa_pin_context(stream); |
61d5676b LL |
1272 | if (IS_ERR(ce)) |
1273 | return PTR_ERR(ce); | |
19f81df2 | 1274 | |
8f8b1171 | 1275 | switch (INTEL_GEN(ce->engine->i915)) { |
61d5676b | 1276 | case 7: { |
19f81df2 | 1277 | /* |
61d5676b LL |
1278 | * On Haswell we don't do any post processing of the reports |
1279 | * and don't need to use the mask. | |
19f81df2 | 1280 | */ |
a37f08a8 UNR |
1281 | stream->specific_ctx_id = i915_ggtt_offset(ce->state); |
1282 | stream->specific_ctx_id_mask = 0; | |
61d5676b LL |
1283 | break; |
1284 | } | |
d7965152 | 1285 | |
61d5676b LL |
1286 | case 8: |
1287 | case 9: | |
1288 | case 10: | |
19c17b76 MW |
1289 | if (intel_engine_in_execlists_submission_mode(ce->engine)) { |
1290 | stream->specific_ctx_id_mask = | |
1291 | (1U << GEN8_CTX_ID_WIDTH) - 1; | |
1292 | stream->specific_ctx_id = stream->specific_ctx_id_mask; | |
1293 | } else { | |
61d5676b LL |
1294 | /* |
1295 | * When using GuC, the context descriptor we write in | |
1296 | * i915 is read by GuC and rewritten before it's | |
1297 | * actually written into the hardware. The LRCA is | |
1298 | * what is put into the context id field of the | |
1299 | * context descriptor by GuC. Because it's aligned to | |
1300 | * a page, the lower 12bits are always at 0 and | |
1301 | * dropped by GuC. They won't be part of the context | |
1302 | * ID in the OA reports, so squash those lower bits. | |
1303 | */ | |
a37f08a8 | 1304 | stream->specific_ctx_id = |
61d5676b | 1305 | lower_32_bits(ce->lrc_desc) >> 12; |
19f81df2 | 1306 | |
61d5676b LL |
1307 | /* |
1308 | * GuC uses the top bit to signal proxy submission, so | |
1309 | * ignore that bit. | |
1310 | */ | |
a37f08a8 | 1311 | stream->specific_ctx_id_mask = |
61d5676b | 1312 | (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1; |
61d5676b LL |
1313 | } |
1314 | break; | |
1315 | ||
45e9c829 MT |
1316 | case 11: |
1317 | case 12: { | |
a37f08a8 | 1318 | stream->specific_ctx_id_mask = |
2935ed53 CW |
1319 | ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32); |
1320 | stream->specific_ctx_id = stream->specific_ctx_id_mask; | |
61d5676b LL |
1321 | break; |
1322 | } | |
1323 | ||
1324 | default: | |
8f8b1171 | 1325 | MISSING_CASE(INTEL_GEN(ce->engine->i915)); |
19f81df2 | 1326 | } |
d7965152 | 1327 | |
2935ed53 CW |
1328 | ce->tag = stream->specific_ctx_id_mask; |
1329 | ||
61d5676b | 1330 | DRM_DEBUG_DRIVER("filtering on ctx_id=0x%x ctx_id_mask=0x%x\n", |
a37f08a8 UNR |
1331 | stream->specific_ctx_id, |
1332 | stream->specific_ctx_id_mask); | |
61d5676b | 1333 | |
266a240b | 1334 | return 0; |
d7965152 RB |
1335 | } |
1336 | ||
16d98b31 RB |
1337 | /** |
1338 | * oa_put_render_ctx_id - counterpart to oa_get_render_ctx_id releases hold | |
1339 | * @stream: An i915-perf stream opened for OA metrics | |
1340 | * | |
1341 | * In case anything needed doing to ensure the context HW ID would remain valid | |
1342 | * for the lifetime of the stream, then that can be undone here. | |
1343 | */ | |
d7965152 RB |
1344 | static void oa_put_render_ctx_id(struct i915_perf_stream *stream) |
1345 | { | |
1fc44d9b | 1346 | struct intel_context *ce; |
d7965152 | 1347 | |
a37f08a8 | 1348 | ce = fetch_and_zero(&stream->pinned_ctx); |
2935ed53 CW |
1349 | if (ce) { |
1350 | ce->tag = 0; /* recomputed on next submission after parking */ | |
1fc44d9b | 1351 | intel_context_unpin(ce); |
2935ed53 CW |
1352 | } |
1353 | ||
1354 | stream->specific_ctx_id = INVALID_CTX_ID; | |
1355 | stream->specific_ctx_id_mask = 0; | |
d7965152 RB |
1356 | } |
1357 | ||
1358 | static void | |
a37f08a8 | 1359 | free_oa_buffer(struct i915_perf_stream *stream) |
d7965152 | 1360 | { |
a37f08a8 | 1361 | i915_vma_unpin_and_release(&stream->oa_buffer.vma, |
6a2f59e4 | 1362 | I915_VMA_RELEASE_MAP); |
d7965152 | 1363 | |
a37f08a8 | 1364 | stream->oa_buffer.vaddr = NULL; |
d7965152 RB |
1365 | } |
1366 | ||
6a45008a LL |
1367 | static void |
1368 | free_oa_configs(struct i915_perf_stream *stream) | |
1369 | { | |
1370 | struct i915_oa_config_bo *oa_bo, *tmp; | |
1371 | ||
1372 | i915_oa_config_put(stream->oa_config); | |
1373 | llist_for_each_entry_safe(oa_bo, tmp, stream->oa_config_bos.first, node) | |
1374 | free_oa_config_bo(oa_bo); | |
1375 | } | |
1376 | ||
daed3e44 LL |
1377 | static void |
1378 | free_noa_wait(struct i915_perf_stream *stream) | |
1379 | { | |
1380 | i915_vma_unpin_and_release(&stream->noa_wait, 0); | |
1381 | } | |
1382 | ||
d7965152 RB |
1383 | static void i915_oa_stream_destroy(struct i915_perf_stream *stream) |
1384 | { | |
8f8b1171 | 1385 | struct i915_perf *perf = stream->perf; |
d7965152 | 1386 | |
8f8b1171 | 1387 | BUG_ON(stream != perf->exclusive_stream); |
d7965152 | 1388 | |
19f81df2 | 1389 | /* |
f89823c2 LL |
1390 | * Unset exclusive_stream first, it will be checked while disabling |
1391 | * the metric set on gen8+. | |
19f81df2 | 1392 | */ |
8f8b1171 CW |
1393 | perf->exclusive_stream = NULL; |
1394 | perf->ops.disable_metric_set(stream); | |
d7965152 | 1395 | |
a37f08a8 | 1396 | free_oa_buffer(stream); |
d7965152 | 1397 | |
52111c46 | 1398 | intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL); |
a5efcde6 | 1399 | intel_engine_pm_put(stream->engine); |
d7965152 RB |
1400 | |
1401 | if (stream->ctx) | |
1402 | oa_put_render_ctx_id(stream); | |
1403 | ||
6a45008a | 1404 | free_oa_configs(stream); |
daed3e44 | 1405 | free_noa_wait(stream); |
f89823c2 | 1406 | |
8f8b1171 | 1407 | if (perf->spurious_report_rs.missed) { |
712122ea | 1408 | DRM_NOTE("%d spurious OA report notices suppressed due to ratelimiting\n", |
8f8b1171 | 1409 | perf->spurious_report_rs.missed); |
712122ea | 1410 | } |
d7965152 RB |
1411 | } |
1412 | ||
a37f08a8 | 1413 | static void gen7_init_oa_buffer(struct i915_perf_stream *stream) |
d7965152 | 1414 | { |
52111c46 | 1415 | struct intel_uncore *uncore = stream->uncore; |
a37f08a8 | 1416 | u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); |
0dd860cf RB |
1417 | unsigned long flags; |
1418 | ||
a37f08a8 | 1419 | spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags); |
d7965152 RB |
1420 | |
1421 | /* Pre-DevBDW: OABUFFER must be set with counters off, | |
1422 | * before OASTATUS1, but after OASTATUS2 | |
1423 | */ | |
8f8b1171 CW |
1424 | intel_uncore_write(uncore, GEN7_OASTATUS2, /* head */ |
1425 | gtt_offset | GEN7_OASTATUS2_MEM_SELECT_GGTT); | |
a37f08a8 | 1426 | stream->oa_buffer.head = gtt_offset; |
f279020a | 1427 | |
8f8b1171 | 1428 | intel_uncore_write(uncore, GEN7_OABUFFER, gtt_offset); |
f279020a | 1429 | |
8f8b1171 CW |
1430 | intel_uncore_write(uncore, GEN7_OASTATUS1, /* tail */ |
1431 | gtt_offset | OABUFFER_SIZE_16M); | |
d7965152 | 1432 | |
0dd860cf | 1433 | /* Mark that we need updated tail pointers to read from... */ |
a37f08a8 UNR |
1434 | stream->oa_buffer.tails[0].offset = INVALID_TAIL_PTR; |
1435 | stream->oa_buffer.tails[1].offset = INVALID_TAIL_PTR; | |
0dd860cf | 1436 | |
a37f08a8 | 1437 | spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags); |
0dd860cf | 1438 | |
d7965152 RB |
1439 | /* On Haswell we have to track which OASTATUS1 flags we've |
1440 | * already seen since they can't be cleared while periodic | |
1441 | * sampling is enabled. | |
1442 | */ | |
8f8b1171 | 1443 | stream->perf->gen7_latched_oastatus1 = 0; |
d7965152 RB |
1444 | |
1445 | /* NB: although the OA buffer will initially be allocated | |
1446 | * zeroed via shmfs (and so this memset is redundant when | |
1447 | * first allocating), we may re-init the OA buffer, either | |
1448 | * when re-enabling a stream or in error/reset paths. | |
1449 | * | |
1450 | * The reason we clear the buffer for each re-init is for the | |
1451 | * sanity check in gen7_append_oa_reports() that looks at the | |
1452 | * report-id field to make sure it's non-zero which relies on | |
1453 | * the assumption that new reports are being written to zeroed | |
1454 | * memory... | |
1455 | */ | |
a37f08a8 | 1456 | memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE); |
d7965152 | 1457 | |
a37f08a8 | 1458 | stream->pollin = false; |
d7965152 RB |
1459 | } |
1460 | ||
a37f08a8 | 1461 | static void gen8_init_oa_buffer(struct i915_perf_stream *stream) |
19f81df2 | 1462 | { |
52111c46 | 1463 | struct intel_uncore *uncore = stream->uncore; |
a37f08a8 | 1464 | u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); |
19f81df2 RB |
1465 | unsigned long flags; |
1466 | ||
a37f08a8 | 1467 | spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags); |
19f81df2 | 1468 | |
8f8b1171 CW |
1469 | intel_uncore_write(uncore, GEN8_OASTATUS, 0); |
1470 | intel_uncore_write(uncore, GEN8_OAHEADPTR, gtt_offset); | |
a37f08a8 | 1471 | stream->oa_buffer.head = gtt_offset; |
19f81df2 | 1472 | |
8f8b1171 | 1473 | intel_uncore_write(uncore, GEN8_OABUFFER_UDW, 0); |
19f81df2 RB |
1474 | |
1475 | /* | |
1476 | * PRM says: | |
1477 | * | |
1478 | * "This MMIO must be set before the OATAILPTR | |
1479 | * register and after the OAHEADPTR register. This is | |
1480 | * to enable proper functionality of the overflow | |
1481 | * bit." | |
1482 | */ | |
8f8b1171 | 1483 | intel_uncore_write(uncore, GEN8_OABUFFER, gtt_offset | |
fe841686 | 1484 | OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT); |
8f8b1171 | 1485 | intel_uncore_write(uncore, GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK); |
19f81df2 RB |
1486 | |
1487 | /* Mark that we need updated tail pointers to read from... */ | |
a37f08a8 UNR |
1488 | stream->oa_buffer.tails[0].offset = INVALID_TAIL_PTR; |
1489 | stream->oa_buffer.tails[1].offset = INVALID_TAIL_PTR; | |
19f81df2 RB |
1490 | |
1491 | /* | |
1492 | * Reset state used to recognise context switches, affecting which | |
1493 | * reports we will forward to userspace while filtering for a single | |
1494 | * context. | |
1495 | */ | |
a37f08a8 | 1496 | stream->oa_buffer.last_ctx_id = INVALID_CTX_ID; |
19f81df2 | 1497 | |
a37f08a8 | 1498 | spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags); |
19f81df2 RB |
1499 | |
1500 | /* | |
1501 | * NB: although the OA buffer will initially be allocated | |
1502 | * zeroed via shmfs (and so this memset is redundant when | |
1503 | * first allocating), we may re-init the OA buffer, either | |
1504 | * when re-enabling a stream or in error/reset paths. | |
1505 | * | |
1506 | * The reason we clear the buffer for each re-init is for the | |
1507 | * sanity check in gen8_append_oa_reports() that looks at the | |
1508 | * reason field to make sure it's non-zero which relies on | |
1509 | * the assumption that new reports are being written to zeroed | |
1510 | * memory... | |
1511 | */ | |
a37f08a8 | 1512 | memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE); |
19f81df2 | 1513 | |
a37f08a8 | 1514 | stream->pollin = false; |
19f81df2 RB |
1515 | } |
1516 | ||
00a7f0d7 LL |
1517 | static void gen12_init_oa_buffer(struct i915_perf_stream *stream) |
1518 | { | |
1519 | struct intel_uncore *uncore = stream->uncore; | |
1520 | u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); | |
1521 | unsigned long flags; | |
1522 | ||
1523 | spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags); | |
1524 | ||
1525 | intel_uncore_write(uncore, GEN12_OAG_OASTATUS, 0); | |
1526 | intel_uncore_write(uncore, GEN12_OAG_OAHEADPTR, | |
1527 | gtt_offset & GEN12_OAG_OAHEADPTR_MASK); | |
1528 | stream->oa_buffer.head = gtt_offset; | |
1529 | ||
1530 | /* | |
1531 | * PRM says: | |
1532 | * | |
1533 | * "This MMIO must be set before the OATAILPTR | |
1534 | * register and after the OAHEADPTR register. This is | |
1535 | * to enable proper functionality of the overflow | |
1536 | * bit." | |
1537 | */ | |
1538 | intel_uncore_write(uncore, GEN12_OAG_OABUFFER, gtt_offset | | |
1539 | OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT); | |
1540 | intel_uncore_write(uncore, GEN12_OAG_OATAILPTR, | |
1541 | gtt_offset & GEN12_OAG_OATAILPTR_MASK); | |
1542 | ||
1543 | /* Mark that we need updated tail pointers to read from... */ | |
1544 | stream->oa_buffer.tails[0].offset = INVALID_TAIL_PTR; | |
1545 | stream->oa_buffer.tails[1].offset = INVALID_TAIL_PTR; | |
1546 | ||
1547 | /* | |
1548 | * Reset state used to recognise context switches, affecting which | |
1549 | * reports we will forward to userspace while filtering for a single | |
1550 | * context. | |
1551 | */ | |
1552 | stream->oa_buffer.last_ctx_id = INVALID_CTX_ID; | |
1553 | ||
1554 | spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags); | |
1555 | ||
1556 | /* | |
1557 | * NB: although the OA buffer will initially be allocated | |
1558 | * zeroed via shmfs (and so this memset is redundant when | |
1559 | * first allocating), we may re-init the OA buffer, either | |
1560 | * when re-enabling a stream or in error/reset paths. | |
1561 | * | |
1562 | * The reason we clear the buffer for each re-init is for the | |
1563 | * sanity check in gen8_append_oa_reports() that looks at the | |
1564 | * reason field to make sure it's non-zero which relies on | |
1565 | * the assumption that new reports are being written to zeroed | |
1566 | * memory... | |
1567 | */ | |
1568 | memset(stream->oa_buffer.vaddr, 0, | |
1569 | stream->oa_buffer.vma->size); | |
1570 | ||
1571 | stream->pollin = false; | |
1572 | } | |
1573 | ||
a37f08a8 | 1574 | static int alloc_oa_buffer(struct i915_perf_stream *stream) |
d7965152 RB |
1575 | { |
1576 | struct drm_i915_gem_object *bo; | |
1577 | struct i915_vma *vma; | |
1578 | int ret; | |
1579 | ||
a37f08a8 | 1580 | if (WARN_ON(stream->oa_buffer.vma)) |
d7965152 RB |
1581 | return -ENODEV; |
1582 | ||
fe841686 JL |
1583 | BUILD_BUG_ON_NOT_POWER_OF_2(OA_BUFFER_SIZE); |
1584 | BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M); | |
1585 | ||
8f8b1171 | 1586 | bo = i915_gem_object_create_shmem(stream->perf->i915, OA_BUFFER_SIZE); |
d7965152 RB |
1587 | if (IS_ERR(bo)) { |
1588 | DRM_ERROR("Failed to allocate OA buffer\n"); | |
2850748e | 1589 | return PTR_ERR(bo); |
d7965152 RB |
1590 | } |
1591 | ||
a679f58d | 1592 | i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC); |
d7965152 RB |
1593 | |
1594 | /* PreHSW required 512K alignment, HSW requires 16M */ | |
1595 | vma = i915_gem_object_ggtt_pin(bo, NULL, 0, SZ_16M, 0); | |
1596 | if (IS_ERR(vma)) { | |
1597 | ret = PTR_ERR(vma); | |
1598 | goto err_unref; | |
1599 | } | |
a37f08a8 | 1600 | stream->oa_buffer.vma = vma; |
d7965152 | 1601 | |
a37f08a8 | 1602 | stream->oa_buffer.vaddr = |
d7965152 | 1603 | i915_gem_object_pin_map(bo, I915_MAP_WB); |
a37f08a8 UNR |
1604 | if (IS_ERR(stream->oa_buffer.vaddr)) { |
1605 | ret = PTR_ERR(stream->oa_buffer.vaddr); | |
d7965152 RB |
1606 | goto err_unpin; |
1607 | } | |
1608 | ||
2850748e | 1609 | return 0; |
d7965152 RB |
1610 | |
1611 | err_unpin: | |
1612 | __i915_vma_unpin(vma); | |
1613 | ||
1614 | err_unref: | |
1615 | i915_gem_object_put(bo); | |
1616 | ||
a37f08a8 UNR |
1617 | stream->oa_buffer.vaddr = NULL; |
1618 | stream->oa_buffer.vma = NULL; | |
d7965152 | 1619 | |
d7965152 RB |
1620 | return ret; |
1621 | } | |
1622 | ||
daed3e44 LL |
1623 | static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs, |
1624 | bool save, i915_reg_t reg, u32 offset, | |
1625 | u32 dword_count) | |
1626 | { | |
1627 | u32 cmd; | |
1628 | u32 d; | |
1629 | ||
1630 | cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM; | |
1631 | if (INTEL_GEN(stream->perf->i915) >= 8) | |
1632 | cmd++; | |
1633 | ||
1634 | for (d = 0; d < dword_count; d++) { | |
1635 | *cs++ = cmd; | |
1636 | *cs++ = i915_mmio_reg_offset(reg) + 4 * d; | |
1637 | *cs++ = intel_gt_scratch_offset(stream->engine->gt, | |
1638 | offset) + 4 * d; | |
1639 | *cs++ = 0; | |
1640 | } | |
1641 | ||
1642 | return cs; | |
1643 | } | |
1644 | ||
1645 | static int alloc_noa_wait(struct i915_perf_stream *stream) | |
1646 | { | |
1647 | struct drm_i915_private *i915 = stream->perf->i915; | |
1648 | struct drm_i915_gem_object *bo; | |
1649 | struct i915_vma *vma; | |
1650 | const u64 delay_ticks = 0xffffffffffffffff - | |
1651 | DIV64_U64_ROUND_UP( | |
1652 | atomic64_read(&stream->perf->noa_programming_delay) * | |
1653 | RUNTIME_INFO(i915)->cs_timestamp_frequency_khz, | |
1654 | 1000000ull); | |
1655 | const u32 base = stream->engine->mmio_base; | |
1656 | #define CS_GPR(x) GEN8_RING_CS_GPR(base, x) | |
1657 | u32 *batch, *ts0, *cs, *jump; | |
1658 | int ret, i; | |
1659 | enum { | |
1660 | START_TS, | |
1661 | NOW_TS, | |
1662 | DELTA_TS, | |
1663 | JUMP_PREDICATE, | |
1664 | DELTA_TARGET, | |
1665 | N_CS_GPR | |
1666 | }; | |
1667 | ||
1668 | bo = i915_gem_object_create_internal(i915, 4096); | |
1669 | if (IS_ERR(bo)) { | |
1670 | DRM_ERROR("Failed to allocate NOA wait batchbuffer\n"); | |
1671 | return PTR_ERR(bo); | |
1672 | } | |
1673 | ||
1674 | /* | |
1675 | * We pin in GGTT because we jump into this buffer now because | |
1676 | * multiple OA config BOs will have a jump to this address and it | |
1677 | * needs to be fixed during the lifetime of the i915/perf stream. | |
1678 | */ | |
1679 | vma = i915_gem_object_ggtt_pin(bo, NULL, 0, 0, PIN_HIGH); | |
1680 | if (IS_ERR(vma)) { | |
1681 | ret = PTR_ERR(vma); | |
1682 | goto err_unref; | |
1683 | } | |
1684 | ||
1685 | batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB); | |
1686 | if (IS_ERR(batch)) { | |
1687 | ret = PTR_ERR(batch); | |
1688 | goto err_unpin; | |
1689 | } | |
1690 | ||
1691 | /* Save registers. */ | |
1692 | for (i = 0; i < N_CS_GPR; i++) | |
1693 | cs = save_restore_register( | |
1694 | stream, cs, true /* save */, CS_GPR(i), | |
1695 | INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2); | |
1696 | cs = save_restore_register( | |
1697 | stream, cs, true /* save */, MI_PREDICATE_RESULT_1, | |
1698 | INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1); | |
1699 | ||
1700 | /* First timestamp snapshot location. */ | |
1701 | ts0 = cs; | |
1702 | ||
1703 | /* | |
1704 | * Initial snapshot of the timestamp register to implement the wait. | |
1705 | * We work with 32b values, so clear out the top 32b bits of the | |
1706 | * register because the ALU works 64bits. | |
1707 | */ | |
1708 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
1709 | *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4; | |
1710 | *cs++ = 0; | |
1711 | *cs++ = MI_LOAD_REGISTER_REG | (3 - 2); | |
1712 | *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base)); | |
1713 | *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)); | |
1714 | ||
1715 | /* | |
1716 | * This is the location we're going to jump back into until the | |
1717 | * required amount of time has passed. | |
1718 | */ | |
1719 | jump = cs; | |
1720 | ||
1721 | /* | |
1722 | * Take another snapshot of the timestamp register. Take care to clear | |
1723 | * up the top 32bits of CS_GPR(1) as we're using it for other | |
1724 | * operations below. | |
1725 | */ | |
1726 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
1727 | *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4; | |
1728 | *cs++ = 0; | |
1729 | *cs++ = MI_LOAD_REGISTER_REG | (3 - 2); | |
1730 | *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base)); | |
1731 | *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)); | |
1732 | ||
1733 | /* | |
1734 | * Do a diff between the 2 timestamps and store the result back into | |
1735 | * CS_GPR(1). | |
1736 | */ | |
1737 | *cs++ = MI_MATH(5); | |
1738 | *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); | |
1739 | *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); | |
1740 | *cs++ = MI_MATH_SUB; | |
1741 | *cs++ = MI_MATH_STORE(MI_MATH_REG(DELTA_TS), MI_MATH_REG_ACCU); | |
1742 | *cs++ = MI_MATH_STORE(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF); | |
1743 | ||
1744 | /* | |
1745 | * Transfer the carry flag (set to 1 if ts1 < ts0, meaning the | |
1746 | * timestamp have rolled over the 32bits) into the predicate register | |
1747 | * to be used for the predicated jump. | |
1748 | */ | |
1749 | *cs++ = MI_LOAD_REGISTER_REG | (3 - 2); | |
1750 | *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE)); | |
1751 | *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1); | |
1752 | ||
1753 | /* Restart from the beginning if we had timestamps roll over. */ | |
1754 | *cs++ = (INTEL_GEN(i915) < 8 ? | |
1755 | MI_BATCH_BUFFER_START : | |
1756 | MI_BATCH_BUFFER_START_GEN8) | | |
1757 | MI_BATCH_PREDICATE; | |
1758 | *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4; | |
1759 | *cs++ = 0; | |
1760 | ||
1761 | /* | |
1762 | * Now add the diff between to previous timestamps and add it to : | |
1763 | * (((1 * << 64) - 1) - delay_ns) | |
1764 | * | |
1765 | * When the Carry Flag contains 1 this means the elapsed time is | |
1766 | * longer than the expected delay, and we can exit the wait loop. | |
1767 | */ | |
1768 | *cs++ = MI_LOAD_REGISTER_IMM(2); | |
1769 | *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)); | |
1770 | *cs++ = lower_32_bits(delay_ticks); | |
1771 | *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)) + 4; | |
1772 | *cs++ = upper_32_bits(delay_ticks); | |
1773 | ||
1774 | *cs++ = MI_MATH(4); | |
1775 | *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(DELTA_TS)); | |
1776 | *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(DELTA_TARGET)); | |
1777 | *cs++ = MI_MATH_ADD; | |
1778 | *cs++ = MI_MATH_STOREINV(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF); | |
1779 | ||
dd590f68 LL |
1780 | *cs++ = MI_ARB_CHECK; |
1781 | ||
daed3e44 LL |
1782 | /* |
1783 | * Transfer the result into the predicate register to be used for the | |
1784 | * predicated jump. | |
1785 | */ | |
1786 | *cs++ = MI_LOAD_REGISTER_REG | (3 - 2); | |
1787 | *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE)); | |
1788 | *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1); | |
1789 | ||
1790 | /* Predicate the jump. */ | |
1791 | *cs++ = (INTEL_GEN(i915) < 8 ? | |
1792 | MI_BATCH_BUFFER_START : | |
1793 | MI_BATCH_BUFFER_START_GEN8) | | |
1794 | MI_BATCH_PREDICATE; | |
1795 | *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4; | |
1796 | *cs++ = 0; | |
1797 | ||
1798 | /* Restore registers. */ | |
1799 | for (i = 0; i < N_CS_GPR; i++) | |
1800 | cs = save_restore_register( | |
1801 | stream, cs, false /* restore */, CS_GPR(i), | |
1802 | INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2); | |
1803 | cs = save_restore_register( | |
1804 | stream, cs, false /* restore */, MI_PREDICATE_RESULT_1, | |
1805 | INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1); | |
1806 | ||
1807 | /* And return to the ring. */ | |
1808 | *cs++ = MI_BATCH_BUFFER_END; | |
1809 | ||
1810 | GEM_BUG_ON(cs - batch > PAGE_SIZE / sizeof(*batch)); | |
1811 | ||
1812 | i915_gem_object_flush_map(bo); | |
1813 | i915_gem_object_unpin_map(bo); | |
1814 | ||
1815 | stream->noa_wait = vma; | |
1816 | return 0; | |
1817 | ||
1818 | err_unpin: | |
15d0ace1 | 1819 | i915_vma_unpin_and_release(&vma, 0); |
daed3e44 LL |
1820 | err_unref: |
1821 | i915_gem_object_put(bo); | |
1822 | return ret; | |
1823 | } | |
1824 | ||
15d0ace1 LL |
1825 | static u32 *write_cs_mi_lri(u32 *cs, |
1826 | const struct i915_oa_reg *reg_data, | |
1827 | u32 n_regs) | |
d7965152 | 1828 | { |
701f8231 | 1829 | u32 i; |
d7965152 RB |
1830 | |
1831 | for (i = 0; i < n_regs; i++) { | |
15d0ace1 LL |
1832 | if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) { |
1833 | u32 n_lri = min_t(u32, | |
1834 | n_regs - i, | |
1835 | MI_LOAD_REGISTER_IMM_MAX_REGS); | |
d7965152 | 1836 | |
15d0ace1 LL |
1837 | *cs++ = MI_LOAD_REGISTER_IMM(n_lri); |
1838 | } | |
1839 | *cs++ = i915_mmio_reg_offset(reg_data[i].addr); | |
1840 | *cs++ = reg_data[i].value; | |
d7965152 | 1841 | } |
15d0ace1 LL |
1842 | |
1843 | return cs; | |
d7965152 RB |
1844 | } |
1845 | ||
15d0ace1 | 1846 | static int num_lri_dwords(int num_regs) |
d7965152 | 1847 | { |
15d0ace1 LL |
1848 | int count = 0; |
1849 | ||
1850 | if (num_regs > 0) { | |
1851 | count += DIV_ROUND_UP(num_regs, MI_LOAD_REGISTER_IMM_MAX_REGS); | |
1852 | count += num_regs * 2; | |
1853 | } | |
1854 | ||
1855 | return count; | |
1856 | } | |
1857 | ||
1858 | static struct i915_oa_config_bo * | |
1859 | alloc_oa_config_buffer(struct i915_perf_stream *stream, | |
1860 | struct i915_oa_config *oa_config) | |
1861 | { | |
1862 | struct drm_i915_gem_object *obj; | |
1863 | struct i915_oa_config_bo *oa_bo; | |
1864 | size_t config_length = 0; | |
1865 | u32 *cs; | |
1866 | int err; | |
1867 | ||
1868 | oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL); | |
1869 | if (!oa_bo) | |
1870 | return ERR_PTR(-ENOMEM); | |
1871 | ||
1872 | config_length += num_lri_dwords(oa_config->mux_regs_len); | |
1873 | config_length += num_lri_dwords(oa_config->b_counter_regs_len); | |
1874 | config_length += num_lri_dwords(oa_config->flex_regs_len); | |
93937659 | 1875 | config_length += 3; /* MI_BATCH_BUFFER_START */ |
15d0ace1 LL |
1876 | config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE); |
1877 | ||
1878 | obj = i915_gem_object_create_shmem(stream->perf->i915, config_length); | |
1879 | if (IS_ERR(obj)) { | |
1880 | err = PTR_ERR(obj); | |
1881 | goto err_free; | |
1882 | } | |
1883 | ||
1884 | cs = i915_gem_object_pin_map(obj, I915_MAP_WB); | |
1885 | if (IS_ERR(cs)) { | |
1886 | err = PTR_ERR(cs); | |
1887 | goto err_oa_bo; | |
1888 | } | |
1889 | ||
1890 | cs = write_cs_mi_lri(cs, | |
1891 | oa_config->mux_regs, | |
1892 | oa_config->mux_regs_len); | |
1893 | cs = write_cs_mi_lri(cs, | |
1894 | oa_config->b_counter_regs, | |
1895 | oa_config->b_counter_regs_len); | |
1896 | cs = write_cs_mi_lri(cs, | |
1897 | oa_config->flex_regs, | |
1898 | oa_config->flex_regs_len); | |
1899 | ||
93937659 LL |
1900 | /* Jump into the active wait. */ |
1901 | *cs++ = (INTEL_GEN(stream->perf->i915) < 8 ? | |
1902 | MI_BATCH_BUFFER_START : | |
1903 | MI_BATCH_BUFFER_START_GEN8); | |
1904 | *cs++ = i915_ggtt_offset(stream->noa_wait); | |
1905 | *cs++ = 0; | |
15d0ace1 LL |
1906 | |
1907 | i915_gem_object_flush_map(obj); | |
1908 | i915_gem_object_unpin_map(obj); | |
1909 | ||
1910 | oa_bo->vma = i915_vma_instance(obj, | |
1911 | &stream->engine->gt->ggtt->vm, | |
1912 | NULL); | |
1913 | if (IS_ERR(oa_bo->vma)) { | |
1914 | err = PTR_ERR(oa_bo->vma); | |
1915 | goto err_oa_bo; | |
1916 | } | |
1917 | ||
1918 | oa_bo->oa_config = i915_oa_config_get(oa_config); | |
1919 | llist_add(&oa_bo->node, &stream->oa_config_bos); | |
1920 | ||
1921 | return oa_bo; | |
1922 | ||
1923 | err_oa_bo: | |
1924 | i915_gem_object_put(obj); | |
1925 | err_free: | |
1926 | kfree(oa_bo); | |
1927 | return ERR_PTR(err); | |
1928 | } | |
1929 | ||
1930 | static struct i915_vma * | |
1931 | get_oa_vma(struct i915_perf_stream *stream, struct i915_oa_config *oa_config) | |
1932 | { | |
1933 | struct i915_oa_config_bo *oa_bo; | |
1934 | ||
14bfcd3e | 1935 | /* |
15d0ace1 LL |
1936 | * Look for the buffer in the already allocated BOs attached |
1937 | * to the stream. | |
d7965152 | 1938 | */ |
15d0ace1 LL |
1939 | llist_for_each_entry(oa_bo, stream->oa_config_bos.first, node) { |
1940 | if (oa_bo->oa_config == oa_config && | |
1941 | memcmp(oa_bo->oa_config->uuid, | |
1942 | oa_config->uuid, | |
1943 | sizeof(oa_config->uuid)) == 0) | |
1944 | goto out; | |
1945 | } | |
1946 | ||
1947 | oa_bo = alloc_oa_config_buffer(stream, oa_config); | |
1948 | if (IS_ERR(oa_bo)) | |
1949 | return ERR_CAST(oa_bo); | |
1950 | ||
1951 | out: | |
1952 | return i915_vma_get(oa_bo->vma); | |
1953 | } | |
1954 | ||
1955 | static int emit_oa_config(struct i915_perf_stream *stream, | |
8814c6d0 | 1956 | struct i915_oa_config *oa_config, |
15d0ace1 LL |
1957 | struct intel_context *ce) |
1958 | { | |
1959 | struct i915_request *rq; | |
1960 | struct i915_vma *vma; | |
1961 | int err; | |
1962 | ||
8814c6d0 | 1963 | vma = get_oa_vma(stream, oa_config); |
15d0ace1 LL |
1964 | if (IS_ERR(vma)) |
1965 | return PTR_ERR(vma); | |
1966 | ||
1967 | err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); | |
1968 | if (err) | |
1969 | goto err_vma_put; | |
1970 | ||
de5825be | 1971 | intel_engine_pm_get(ce->engine); |
15d0ace1 | 1972 | rq = i915_request_create(ce); |
de5825be | 1973 | intel_engine_pm_put(ce->engine); |
15d0ace1 LL |
1974 | if (IS_ERR(rq)) { |
1975 | err = PTR_ERR(rq); | |
1976 | goto err_vma_unpin; | |
1977 | } | |
1978 | ||
1979 | i915_vma_lock(vma); | |
1980 | err = i915_request_await_object(rq, vma->obj, 0); | |
1981 | if (!err) | |
1982 | err = i915_vma_move_to_active(vma, rq, 0); | |
1983 | i915_vma_unlock(vma); | |
1984 | if (err) | |
1985 | goto err_add_request; | |
1986 | ||
1987 | err = rq->engine->emit_bb_start(rq, | |
1988 | vma->node.start, 0, | |
1989 | I915_DISPATCH_SECURE); | |
1990 | err_add_request: | |
1991 | i915_request_add(rq); | |
1992 | err_vma_unpin: | |
1993 | i915_vma_unpin(vma); | |
1994 | err_vma_put: | |
1995 | i915_vma_put(vma); | |
1996 | return err; | |
14bfcd3e LL |
1997 | } |
1998 | ||
5f5c382e CW |
1999 | static struct intel_context *oa_context(struct i915_perf_stream *stream) |
2000 | { | |
2001 | return stream->pinned_ctx ?: stream->engine->kernel_context; | |
2002 | } | |
2003 | ||
14bfcd3e LL |
2004 | static int hsw_enable_metric_set(struct i915_perf_stream *stream) |
2005 | { | |
52111c46 | 2006 | struct intel_uncore *uncore = stream->uncore; |
14bfcd3e LL |
2007 | |
2008 | /* | |
2009 | * PRM: | |
2010 | * | |
2011 | * OA unit is using “crclk” for its functionality. When trunk | |
2012 | * level clock gating takes place, OA clock would be gated, | |
2013 | * unable to count the events from non-render clock domain. | |
2014 | * Render clock gating must be disabled when OA is enabled to | |
2015 | * count the events from non-render domain. Unit level clock | |
2016 | * gating for RCS should also be disabled. | |
2017 | */ | |
8f8b1171 CW |
2018 | intel_uncore_rmw(uncore, GEN7_MISCCPCTL, |
2019 | GEN7_DOP_CLOCK_GATE_ENABLE, 0); | |
2020 | intel_uncore_rmw(uncore, GEN6_UCGCTL1, | |
2021 | 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
14bfcd3e | 2022 | |
8814c6d0 | 2023 | return emit_oa_config(stream, stream->oa_config, oa_context(stream)); |
d7965152 RB |
2024 | } |
2025 | ||
a37f08a8 | 2026 | static void hsw_disable_metric_set(struct i915_perf_stream *stream) |
d7965152 | 2027 | { |
52111c46 | 2028 | struct intel_uncore *uncore = stream->uncore; |
a37f08a8 | 2029 | |
8f8b1171 CW |
2030 | intel_uncore_rmw(uncore, GEN6_UCGCTL1, |
2031 | GEN6_CSUNIT_CLOCK_GATE_DISABLE, 0); | |
2032 | intel_uncore_rmw(uncore, GEN7_MISCCPCTL, | |
2033 | 0, GEN7_DOP_CLOCK_GATE_ENABLE); | |
d7965152 | 2034 | |
8f8b1171 | 2035 | intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0); |
d7965152 RB |
2036 | } |
2037 | ||
a9877da2 CW |
2038 | static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config, |
2039 | i915_reg_t reg) | |
2040 | { | |
2041 | u32 mmio = i915_mmio_reg_offset(reg); | |
2042 | int i; | |
2043 | ||
2044 | /* | |
2045 | * This arbitrary default will select the 'EU FPU0 Pipeline | |
2046 | * Active' event. In the future it's anticipated that there | |
2047 | * will be an explicit 'No Event' we can select, but not yet... | |
2048 | */ | |
2049 | if (!oa_config) | |
2050 | return 0; | |
2051 | ||
2052 | for (i = 0; i < oa_config->flex_regs_len; i++) { | |
2053 | if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio) | |
2054 | return oa_config->flex_regs[i].value; | |
2055 | } | |
2056 | ||
2057 | return 0; | |
2058 | } | |
19f81df2 RB |
2059 | /* |
2060 | * NB: It must always remain pointer safe to run this even if the OA unit | |
2061 | * has been disabled. | |
2062 | * | |
2063 | * It's fine to put out-of-date values into these per-context registers | |
2064 | * in the case that the OA unit has been disabled. | |
2065 | */ | |
b146e5ef | 2066 | static void |
7dc56af5 CW |
2067 | gen8_update_reg_state_unlocked(const struct intel_context *ce, |
2068 | const struct i915_perf_stream *stream) | |
19f81df2 | 2069 | { |
8f8b1171 CW |
2070 | u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset; |
2071 | u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset; | |
19f81df2 | 2072 | /* The MMIO offsets for Flex EU registers aren't contiguous */ |
35ab4fd2 LL |
2073 | i915_reg_t flex_regs[] = { |
2074 | EU_PERF_CNTL0, | |
2075 | EU_PERF_CNTL1, | |
2076 | EU_PERF_CNTL2, | |
2077 | EU_PERF_CNTL3, | |
2078 | EU_PERF_CNTL4, | |
2079 | EU_PERF_CNTL5, | |
2080 | EU_PERF_CNTL6, | |
19f81df2 | 2081 | }; |
7dc56af5 | 2082 | u32 *reg_state = ce->lrc_reg_state; |
19f81df2 RB |
2083 | int i; |
2084 | ||
00a7f0d7 LL |
2085 | if (IS_GEN(stream->perf->i915, 12)) { |
2086 | u32 format = stream->oa_buffer.format; | |
19f81df2 | 2087 | |
00a7f0d7 LL |
2088 | reg_state[ctx_oactxctrl + 1] = |
2089 | (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) | | |
2090 | (stream->oa_config ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0); | |
2091 | } else { | |
2092 | reg_state[ctx_oactxctrl + 1] = | |
2093 | (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) | | |
2094 | (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) | | |
2095 | GEN8_OA_COUNTER_RESUME; | |
2096 | } | |
2097 | ||
2098 | for (i = 0; !!ctx_flexeu0 && i < ARRAY_SIZE(flex_regs); i++) | |
7dc56af5 CW |
2099 | reg_state[ctx_flexeu0 + i * 2 + 1] = |
2100 | oa_config_flex_reg(stream->oa_config, flex_regs[i]); | |
ec431eae | 2101 | |
8f8b1171 CW |
2102 | reg_state[CTX_R_PWR_CLK_STATE] = |
2103 | intel_sseu_make_rpcs(ce->engine->i915, &ce->sseu); | |
19f81df2 RB |
2104 | } |
2105 | ||
a9877da2 CW |
2106 | struct flex { |
2107 | i915_reg_t reg; | |
2108 | u32 offset; | |
2109 | u32 value; | |
2110 | }; | |
2111 | ||
2112 | static int | |
2113 | gen8_store_flex(struct i915_request *rq, | |
2114 | struct intel_context *ce, | |
2115 | const struct flex *flex, unsigned int count) | |
2116 | { | |
2117 | u32 offset; | |
2118 | u32 *cs; | |
2119 | ||
2120 | cs = intel_ring_begin(rq, 4 * count); | |
2121 | if (IS_ERR(cs)) | |
2122 | return PTR_ERR(cs); | |
2123 | ||
2124 | offset = i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE; | |
2125 | do { | |
2126 | *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; | |
7dc56af5 | 2127 | *cs++ = offset + flex->offset * sizeof(u32); |
a9877da2 CW |
2128 | *cs++ = 0; |
2129 | *cs++ = flex->value; | |
2130 | } while (flex++, --count); | |
2131 | ||
2132 | intel_ring_advance(rq, cs); | |
2133 | ||
2134 | return 0; | |
2135 | } | |
2136 | ||
2137 | static int | |
2138 | gen8_load_flex(struct i915_request *rq, | |
2139 | struct intel_context *ce, | |
2140 | const struct flex *flex, unsigned int count) | |
2141 | { | |
2142 | u32 *cs; | |
2143 | ||
2144 | GEM_BUG_ON(!count || count > 63); | |
2145 | ||
2146 | cs = intel_ring_begin(rq, 2 * count + 2); | |
2147 | if (IS_ERR(cs)) | |
2148 | return PTR_ERR(cs); | |
2149 | ||
2150 | *cs++ = MI_LOAD_REGISTER_IMM(count); | |
2151 | do { | |
2152 | *cs++ = i915_mmio_reg_offset(flex->reg); | |
2153 | *cs++ = flex->value; | |
2154 | } while (flex++, --count); | |
2155 | *cs++ = MI_NOOP; | |
2156 | ||
2157 | intel_ring_advance(rq, cs); | |
2158 | ||
2159 | return 0; | |
2160 | } | |
2161 | ||
2162 | static int gen8_modify_context(struct intel_context *ce, | |
2163 | const struct flex *flex, unsigned int count) | |
2164 | { | |
2165 | struct i915_request *rq; | |
2166 | int err; | |
2167 | ||
2168 | lockdep_assert_held(&ce->pin_mutex); | |
2169 | ||
de5825be | 2170 | rq = intel_engine_create_kernel_request(ce->engine); |
a9877da2 CW |
2171 | if (IS_ERR(rq)) |
2172 | return PTR_ERR(rq); | |
2173 | ||
2174 | /* Serialise with the remote context */ | |
2175 | err = intel_context_prepare_remote_request(ce, rq); | |
2176 | if (err == 0) | |
2177 | err = gen8_store_flex(rq, ce, flex, count); | |
2178 | ||
2179 | i915_request_add(rq); | |
2180 | return err; | |
2181 | } | |
2182 | ||
2183 | static int gen8_modify_self(struct intel_context *ce, | |
2184 | const struct flex *flex, unsigned int count) | |
2185 | { | |
2186 | struct i915_request *rq; | |
2187 | int err; | |
2188 | ||
2189 | rq = i915_request_create(ce); | |
2190 | if (IS_ERR(rq)) | |
2191 | return PTR_ERR(rq); | |
2192 | ||
2193 | err = gen8_load_flex(rq, ce, flex, count); | |
2194 | ||
2195 | i915_request_add(rq); | |
2196 | return err; | |
2197 | } | |
2198 | ||
5cca5038 CW |
2199 | static int gen8_configure_context(struct i915_gem_context *ctx, |
2200 | struct flex *flex, unsigned int count) | |
2201 | { | |
2202 | struct i915_gem_engines_iter it; | |
2203 | struct intel_context *ce; | |
2204 | int err = 0; | |
2205 | ||
2206 | for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) { | |
2207 | GEM_BUG_ON(ce == ce->engine->kernel_context); | |
2208 | ||
2209 | if (ce->engine->class != RENDER_CLASS) | |
2210 | continue; | |
2211 | ||
2212 | err = intel_context_lock_pinned(ce); | |
2213 | if (err) | |
2214 | break; | |
2215 | ||
2216 | flex->value = intel_sseu_make_rpcs(ctx->i915, &ce->sseu); | |
2217 | ||
2218 | /* Otherwise OA settings will be set upon first use */ | |
2219 | if (intel_context_is_pinned(ce)) | |
2220 | err = gen8_modify_context(ce, flex, count); | |
2221 | ||
2222 | intel_context_unlock_pinned(ce); | |
2223 | if (err) | |
2224 | break; | |
2225 | } | |
2226 | i915_gem_context_unlock_engines(ctx); | |
2227 | ||
2228 | return err; | |
2229 | } | |
2230 | ||
00a7f0d7 LL |
2231 | static int gen12_emit_oar_config(struct intel_context *ce, bool enable) |
2232 | { | |
2233 | struct i915_request *rq; | |
2234 | u32 *cs; | |
2235 | int err = 0; | |
2236 | ||
2237 | rq = i915_request_create(ce); | |
2238 | if (IS_ERR(rq)) | |
2239 | return PTR_ERR(rq); | |
2240 | ||
2241 | cs = intel_ring_begin(rq, 4); | |
2242 | if (IS_ERR(cs)) { | |
2243 | err = PTR_ERR(cs); | |
2244 | goto out; | |
2245 | } | |
2246 | ||
2247 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
2248 | *cs++ = i915_mmio_reg_offset(RING_CONTEXT_CONTROL(ce->engine->mmio_base)); | |
2249 | *cs++ = _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE, | |
2250 | enable ? GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE : 0); | |
2251 | *cs++ = MI_NOOP; | |
2252 | ||
2253 | intel_ring_advance(rq, cs); | |
2254 | ||
2255 | out: | |
2256 | i915_request_add(rq); | |
2257 | ||
2258 | return err; | |
2259 | } | |
2260 | ||
19f81df2 RB |
2261 | /* |
2262 | * Manages updating the per-context aspects of the OA stream | |
2263 | * configuration across all contexts. | |
2264 | * | |
2265 | * The awkward consideration here is that OACTXCONTROL controls the | |
2266 | * exponent for periodic sampling which is primarily used for system | |
2267 | * wide profiling where we'd like a consistent sampling period even in | |
2268 | * the face of context switches. | |
2269 | * | |
2270 | * Our approach of updating the register state context (as opposed to | |
2271 | * say using a workaround batch buffer) ensures that the hardware | |
2272 | * won't automatically reload an out-of-date timer exponent even | |
2273 | * transiently before a WA BB could be parsed. | |
2274 | * | |
2275 | * This function needs to: | |
2276 | * - Ensure the currently running context's per-context OA state is | |
2277 | * updated | |
2278 | * - Ensure that all existing contexts will have the correct per-context | |
2279 | * OA state if they are scheduled for use. | |
2280 | * - Ensure any new contexts will be initialized with the correct | |
2281 | * per-context OA state. | |
2282 | * | |
2283 | * Note: it's only the RCS/Render context that has any OA state. | |
2284 | */ | |
00a7f0d7 LL |
2285 | static int lrc_configure_all_contexts(struct i915_perf_stream *stream, |
2286 | const struct i915_oa_config *oa_config) | |
19f81df2 | 2287 | { |
8f8b1171 | 2288 | struct drm_i915_private *i915 = stream->perf->i915; |
a9877da2 | 2289 | /* The MMIO offsets for Flex EU registers aren't contiguous */ |
8f8b1171 | 2290 | const u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset; |
7dc56af5 | 2291 | #define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1) |
a9877da2 CW |
2292 | struct flex regs[] = { |
2293 | { | |
2294 | GEN8_R_PWR_CLK_STATE, | |
2295 | CTX_R_PWR_CLK_STATE, | |
2296 | }, | |
2297 | { | |
00a7f0d7 LL |
2298 | IS_GEN(i915, 12) ? |
2299 | GEN12_OAR_OACONTROL : GEN8_OACTXCONTROL, | |
8f8b1171 | 2300 | stream->perf->ctx_oactxctrl_offset + 1, |
a9877da2 CW |
2301 | }, |
2302 | { EU_PERF_CNTL0, ctx_flexeuN(0) }, | |
2303 | { EU_PERF_CNTL1, ctx_flexeuN(1) }, | |
2304 | { EU_PERF_CNTL2, ctx_flexeuN(2) }, | |
2305 | { EU_PERF_CNTL3, ctx_flexeuN(3) }, | |
2306 | { EU_PERF_CNTL4, ctx_flexeuN(4) }, | |
2307 | { EU_PERF_CNTL5, ctx_flexeuN(5) }, | |
2308 | { EU_PERF_CNTL6, ctx_flexeuN(6) }, | |
2309 | }; | |
2310 | #undef ctx_flexeuN | |
2311 | struct intel_engine_cs *engine; | |
a4e7ccda | 2312 | struct i915_gem_context *ctx, *cn; |
00a7f0d7 | 2313 | size_t array_size = IS_GEN(i915, 12) ? 2 : ARRAY_SIZE(regs); |
a4e7ccda | 2314 | int i, err; |
19f81df2 | 2315 | |
00a7f0d7 LL |
2316 | if (IS_GEN(i915, 12)) { |
2317 | u32 format = stream->oa_buffer.format; | |
2318 | ||
2319 | regs[1].value = | |
2320 | (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) | | |
2321 | (oa_config ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0); | |
2322 | } else { | |
2323 | regs[1].value = | |
2324 | (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) | | |
2325 | (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) | | |
2326 | GEN8_OA_COUNTER_RESUME; | |
2327 | } | |
2328 | ||
2329 | for (i = 2; !!ctx_flexeu0 && i < array_size; i++) | |
a9877da2 CW |
2330 | regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg); |
2331 | ||
a4c969d1 | 2332 | lockdep_assert_held(&stream->perf->lock); |
19f81df2 | 2333 | |
19f81df2 RB |
2334 | /* |
2335 | * The OA register config is setup through the context image. This image | |
2336 | * might be written to by the GPU on context switch (in particular on | |
2337 | * lite-restore). This means we can't safely update a context's image, | |
2338 | * if this context is scheduled/submitted to run on the GPU. | |
2339 | * | |
2340 | * We could emit the OA register config through the batch buffer but | |
2341 | * this might leave small interval of time where the OA unit is | |
2342 | * configured at an invalid sampling period. | |
2343 | * | |
a9877da2 CW |
2344 | * Note that since we emit all requests from a single ring, there |
2345 | * is still an implicit global barrier here that may cause a high | |
2346 | * priority context to wait for an otherwise independent low priority | |
2347 | * context. Contexts idle at the time of reconfiguration are not | |
2348 | * trapped behind the barrier. | |
19f81df2 | 2349 | */ |
a4e7ccda CW |
2350 | spin_lock(&i915->gem.contexts.lock); |
2351 | list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) { | |
a9877da2 CW |
2352 | if (ctx == i915->kernel_context) |
2353 | continue; | |
2354 | ||
a4e7ccda CW |
2355 | if (!kref_get_unless_zero(&ctx->ref)) |
2356 | continue; | |
2357 | ||
2358 | spin_unlock(&i915->gem.contexts.lock); | |
2359 | ||
00a7f0d7 | 2360 | err = gen8_configure_context(ctx, regs, array_size); |
a4e7ccda CW |
2361 | if (err) { |
2362 | i915_gem_context_put(ctx); | |
a9877da2 | 2363 | return err; |
a4e7ccda CW |
2364 | } |
2365 | ||
2366 | spin_lock(&i915->gem.contexts.lock); | |
2367 | list_safe_reset_next(ctx, cn, link); | |
2368 | i915_gem_context_put(ctx); | |
19f81df2 | 2369 | } |
a4e7ccda | 2370 | spin_unlock(&i915->gem.contexts.lock); |
19f81df2 | 2371 | |
722f3de3 | 2372 | /* |
a9877da2 CW |
2373 | * After updating all other contexts, we need to modify ourselves. |
2374 | * If we don't modify the kernel_context, we do not get events while | |
2375 | * idle. | |
722f3de3 | 2376 | */ |
750e76b4 | 2377 | for_each_uabi_engine(engine, i915) { |
a9877da2 | 2378 | struct intel_context *ce = engine->kernel_context; |
722f3de3 | 2379 | |
a9877da2 CW |
2380 | if (engine->class != RENDER_CLASS) |
2381 | continue; | |
2382 | ||
2383 | regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu); | |
2384 | ||
00a7f0d7 | 2385 | err = gen8_modify_self(ce, regs, array_size); |
a9877da2 CW |
2386 | if (err) |
2387 | return err; | |
2388 | } | |
722f3de3 TU |
2389 | |
2390 | return 0; | |
19f81df2 RB |
2391 | } |
2392 | ||
5728de2f | 2393 | static int gen8_enable_metric_set(struct i915_perf_stream *stream) |
19f81df2 | 2394 | { |
52111c46 | 2395 | struct intel_uncore *uncore = stream->uncore; |
8814c6d0 | 2396 | struct i915_oa_config *oa_config = stream->oa_config; |
701f8231 | 2397 | int ret; |
19f81df2 RB |
2398 | |
2399 | /* | |
2400 | * We disable slice/unslice clock ratio change reports on SKL since | |
2401 | * they are too noisy. The HW generates a lot of redundant reports | |
2402 | * where the ratio hasn't really changed causing a lot of redundant | |
2403 | * work to processes and increasing the chances we'll hit buffer | |
2404 | * overruns. | |
2405 | * | |
2406 | * Although we don't currently use the 'disable overrun' OABUFFER | |
2407 | * feature it's worth noting that clock ratio reports have to be | |
2408 | * disabled before considering to use that feature since the HW doesn't | |
2409 | * correctly block these reports. | |
2410 | * | |
2411 | * Currently none of the high-level metrics we have depend on knowing | |
2412 | * this ratio to normalize. | |
2413 | * | |
2414 | * Note: This register is not power context saved and restored, but | |
2415 | * that's OK considering that we disable RC6 while the OA unit is | |
2416 | * enabled. | |
2417 | * | |
2418 | * The _INCLUDE_CLK_RATIO bit allows the slice/unslice frequency to | |
2419 | * be read back from automatically triggered reports, as part of the | |
2420 | * RPT_ID field. | |
2421 | */ | |
8f8b1171 CW |
2422 | if (IS_GEN_RANGE(stream->perf->i915, 9, 11)) { |
2423 | intel_uncore_write(uncore, GEN8_OA_DEBUG, | |
2424 | _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | | |
2425 | GEN9_OA_DEBUG_INCLUDE_CLK_RATIO)); | |
19f81df2 RB |
2426 | } |
2427 | ||
2428 | /* | |
2429 | * Update all contexts prior writing the mux configurations as we need | |
2430 | * to make sure all slices/subslices are ON before writing to NOA | |
2431 | * registers. | |
2432 | */ | |
00a7f0d7 LL |
2433 | ret = lrc_configure_all_contexts(stream, oa_config); |
2434 | if (ret) | |
2435 | return ret; | |
2436 | ||
2437 | return emit_oa_config(stream, oa_config, oa_context(stream)); | |
2438 | } | |
2439 | ||
9278bbb6 CW |
2440 | static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream) |
2441 | { | |
2442 | return _MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS, | |
2443 | (stream->sample_flags & SAMPLE_OA_REPORT) ? | |
2444 | 0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS); | |
2445 | } | |
2446 | ||
00a7f0d7 LL |
2447 | static int gen12_enable_metric_set(struct i915_perf_stream *stream) |
2448 | { | |
2449 | struct intel_uncore *uncore = stream->uncore; | |
2450 | struct i915_oa_config *oa_config = stream->oa_config; | |
2451 | bool periodic = stream->periodic; | |
2452 | u32 period_exponent = stream->period_exponent; | |
2453 | int ret; | |
2454 | ||
2455 | intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG, | |
2456 | /* Disable clk ratio reports, like previous Gens. */ | |
2457 | _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | | |
2458 | GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) | | |
2459 | /* | |
9278bbb6 CW |
2460 | * If the user didn't require OA reports, instruct |
2461 | * the hardware not to emit ctx switch reports. | |
00a7f0d7 | 2462 | */ |
9278bbb6 | 2463 | oag_report_ctx_switches(stream)); |
00a7f0d7 LL |
2464 | |
2465 | intel_uncore_write(uncore, GEN12_OAG_OAGLBCTXCTRL, periodic ? | |
2466 | (GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME | | |
2467 | GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE | | |
2468 | (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT)) | |
2469 | : 0); | |
2470 | ||
2471 | /* | |
2472 | * Update all contexts prior writing the mux configurations as we need | |
2473 | * to make sure all slices/subslices are ON before writing to NOA | |
2474 | * registers. | |
2475 | */ | |
2476 | ret = lrc_configure_all_contexts(stream, oa_config); | |
19f81df2 RB |
2477 | if (ret) |
2478 | return ret; | |
2479 | ||
00a7f0d7 LL |
2480 | /* |
2481 | * For Gen12, performance counters are context | |
2482 | * saved/restored. Only enable it for the context that | |
2483 | * requested this. | |
2484 | */ | |
2485 | if (stream->ctx) { | |
2486 | ret = gen12_emit_oar_config(stream->pinned_ctx, | |
2487 | oa_config != NULL); | |
2488 | if (ret) | |
2489 | return ret; | |
2490 | } | |
2491 | ||
8814c6d0 | 2492 | return emit_oa_config(stream, oa_config, oa_context(stream)); |
19f81df2 RB |
2493 | } |
2494 | ||
a37f08a8 | 2495 | static void gen8_disable_metric_set(struct i915_perf_stream *stream) |
19f81df2 | 2496 | { |
52111c46 | 2497 | struct intel_uncore *uncore = stream->uncore; |
a37f08a8 | 2498 | |
19f81df2 | 2499 | /* Reset all contexts' slices/subslices configurations. */ |
00a7f0d7 | 2500 | lrc_configure_all_contexts(stream, NULL); |
28964cf2 | 2501 | |
8f8b1171 | 2502 | intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0); |
19f81df2 RB |
2503 | } |
2504 | ||
a37f08a8 | 2505 | static void gen10_disable_metric_set(struct i915_perf_stream *stream) |
95690a02 | 2506 | { |
52111c46 | 2507 | struct intel_uncore *uncore = stream->uncore; |
a37f08a8 | 2508 | |
95690a02 | 2509 | /* Reset all contexts' slices/subslices configurations. */ |
00a7f0d7 LL |
2510 | lrc_configure_all_contexts(stream, NULL); |
2511 | ||
2512 | /* Make sure we disable noa to save power. */ | |
2513 | intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0); | |
2514 | } | |
2515 | ||
2516 | static void gen12_disable_metric_set(struct i915_perf_stream *stream) | |
2517 | { | |
2518 | struct intel_uncore *uncore = stream->uncore; | |
2519 | ||
2520 | /* Reset all contexts' slices/subslices configurations. */ | |
2521 | lrc_configure_all_contexts(stream, NULL); | |
2522 | ||
2523 | /* disable the context save/restore or OAR counters */ | |
2524 | if (stream->ctx) | |
2525 | gen12_emit_oar_config(stream->pinned_ctx, false); | |
95690a02 LL |
2526 | |
2527 | /* Make sure we disable noa to save power. */ | |
8f8b1171 | 2528 | intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0); |
95690a02 LL |
2529 | } |
2530 | ||
5728de2f | 2531 | static void gen7_oa_enable(struct i915_perf_stream *stream) |
d7965152 | 2532 | { |
52111c46 | 2533 | struct intel_uncore *uncore = stream->uncore; |
5728de2f | 2534 | struct i915_gem_context *ctx = stream->ctx; |
a37f08a8 UNR |
2535 | u32 ctx_id = stream->specific_ctx_id; |
2536 | bool periodic = stream->periodic; | |
2537 | u32 period_exponent = stream->period_exponent; | |
2538 | u32 report_format = stream->oa_buffer.format; | |
11051303 | 2539 | |
1bef3409 RB |
2540 | /* |
2541 | * Reset buf pointers so we don't forward reports from before now. | |
2542 | * | |
2543 | * Think carefully if considering trying to avoid this, since it | |
2544 | * also ensures status flags and the buffer itself are cleared | |
2545 | * in error paths, and we have checks for invalid reports based | |
2546 | * on the assumption that certain fields are written to zeroed | |
2547 | * memory which this helps maintains. | |
2548 | */ | |
a37f08a8 | 2549 | gen7_init_oa_buffer(stream); |
d7965152 | 2550 | |
8f8b1171 CW |
2551 | intel_uncore_write(uncore, GEN7_OACONTROL, |
2552 | (ctx_id & GEN7_OACONTROL_CTX_MASK) | | |
2553 | (period_exponent << | |
2554 | GEN7_OACONTROL_TIMER_PERIOD_SHIFT) | | |
2555 | (periodic ? GEN7_OACONTROL_TIMER_ENABLE : 0) | | |
2556 | (report_format << GEN7_OACONTROL_FORMAT_SHIFT) | | |
2557 | (ctx ? GEN7_OACONTROL_PER_CTX_ENABLE : 0) | | |
2558 | GEN7_OACONTROL_ENABLE); | |
d7965152 RB |
2559 | } |
2560 | ||
5728de2f | 2561 | static void gen8_oa_enable(struct i915_perf_stream *stream) |
19f81df2 | 2562 | { |
52111c46 | 2563 | struct intel_uncore *uncore = stream->uncore; |
a37f08a8 | 2564 | u32 report_format = stream->oa_buffer.format; |
19f81df2 RB |
2565 | |
2566 | /* | |
2567 | * Reset buf pointers so we don't forward reports from before now. | |
2568 | * | |
2569 | * Think carefully if considering trying to avoid this, since it | |
2570 | * also ensures status flags and the buffer itself are cleared | |
2571 | * in error paths, and we have checks for invalid reports based | |
2572 | * on the assumption that certain fields are written to zeroed | |
2573 | * memory which this helps maintains. | |
2574 | */ | |
a37f08a8 | 2575 | gen8_init_oa_buffer(stream); |
19f81df2 RB |
2576 | |
2577 | /* | |
2578 | * Note: we don't rely on the hardware to perform single context | |
2579 | * filtering and instead filter on the cpu based on the context-id | |
2580 | * field of reports | |
2581 | */ | |
8f8b1171 CW |
2582 | intel_uncore_write(uncore, GEN8_OACONTROL, |
2583 | (report_format << GEN8_OA_REPORT_FORMAT_SHIFT) | | |
2584 | GEN8_OA_COUNTER_ENABLE); | |
19f81df2 RB |
2585 | } |
2586 | ||
00a7f0d7 LL |
2587 | static void gen12_oa_enable(struct i915_perf_stream *stream) |
2588 | { | |
2589 | struct intel_uncore *uncore = stream->uncore; | |
2590 | u32 report_format = stream->oa_buffer.format; | |
2591 | ||
2592 | /* | |
2593 | * If we don't want OA reports from the OA buffer, then we don't even | |
2594 | * need to program the OAG unit. | |
2595 | */ | |
2596 | if (!(stream->sample_flags & SAMPLE_OA_REPORT)) | |
2597 | return; | |
2598 | ||
2599 | gen12_init_oa_buffer(stream); | |
2600 | ||
2601 | intel_uncore_write(uncore, GEN12_OAG_OACONTROL, | |
2602 | (report_format << GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT) | | |
2603 | GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE); | |
2604 | } | |
2605 | ||
16d98b31 RB |
2606 | /** |
2607 | * i915_oa_stream_enable - handle `I915_PERF_IOCTL_ENABLE` for OA stream | |
2608 | * @stream: An i915 perf stream opened for OA metrics | |
2609 | * | |
2610 | * [Re]enables hardware periodic sampling according to the period configured | |
2611 | * when opening the stream. This also starts a hrtimer that will periodically | |
2612 | * check for data in the circular OA buffer for notifying userspace (e.g. | |
2613 | * during a read() or poll()). | |
2614 | */ | |
d7965152 RB |
2615 | static void i915_oa_stream_enable(struct i915_perf_stream *stream) |
2616 | { | |
8f8b1171 | 2617 | stream->perf->ops.oa_enable(stream); |
d7965152 | 2618 | |
a37f08a8 UNR |
2619 | if (stream->periodic) |
2620 | hrtimer_start(&stream->poll_check_timer, | |
d7965152 RB |
2621 | ns_to_ktime(POLL_PERIOD), |
2622 | HRTIMER_MODE_REL_PINNED); | |
2623 | } | |
2624 | ||
5728de2f | 2625 | static void gen7_oa_disable(struct i915_perf_stream *stream) |
d7965152 | 2626 | { |
52111c46 | 2627 | struct intel_uncore *uncore = stream->uncore; |
5728de2f | 2628 | |
97a04e0d DCS |
2629 | intel_uncore_write(uncore, GEN7_OACONTROL, 0); |
2630 | if (intel_wait_for_register(uncore, | |
e896d29a CW |
2631 | GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0, |
2632 | 50)) | |
2633 | DRM_ERROR("wait for OA to be disabled timed out\n"); | |
d7965152 RB |
2634 | } |
2635 | ||
5728de2f | 2636 | static void gen8_oa_disable(struct i915_perf_stream *stream) |
19f81df2 | 2637 | { |
52111c46 | 2638 | struct intel_uncore *uncore = stream->uncore; |
5728de2f | 2639 | |
97a04e0d DCS |
2640 | intel_uncore_write(uncore, GEN8_OACONTROL, 0); |
2641 | if (intel_wait_for_register(uncore, | |
e896d29a CW |
2642 | GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0, |
2643 | 50)) | |
2644 | DRM_ERROR("wait for OA to be disabled timed out\n"); | |
19f81df2 RB |
2645 | } |
2646 | ||
00a7f0d7 LL |
2647 | static void gen12_oa_disable(struct i915_perf_stream *stream) |
2648 | { | |
2649 | struct intel_uncore *uncore = stream->uncore; | |
2650 | ||
2651 | intel_uncore_write(uncore, GEN12_OAG_OACONTROL, 0); | |
2652 | if (intel_wait_for_register(uncore, | |
2653 | GEN12_OAG_OACONTROL, | |
2654 | GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE, 0, | |
2655 | 50)) | |
2656 | DRM_ERROR("wait for OA to be disabled timed out\n"); | |
2657 | } | |
2658 | ||
16d98b31 RB |
2659 | /** |
2660 | * i915_oa_stream_disable - handle `I915_PERF_IOCTL_DISABLE` for OA stream | |
2661 | * @stream: An i915 perf stream opened for OA metrics | |
2662 | * | |
2663 | * Stops the OA unit from periodically writing counter reports into the | |
2664 | * circular OA buffer. This also stops the hrtimer that periodically checks for | |
2665 | * data in the circular OA buffer, for notifying userspace. | |
2666 | */ | |
d7965152 RB |
2667 | static void i915_oa_stream_disable(struct i915_perf_stream *stream) |
2668 | { | |
8f8b1171 | 2669 | stream->perf->ops.oa_disable(stream); |
d7965152 | 2670 | |
a37f08a8 UNR |
2671 | if (stream->periodic) |
2672 | hrtimer_cancel(&stream->poll_check_timer); | |
d7965152 RB |
2673 | } |
2674 | ||
d7965152 RB |
2675 | static const struct i915_perf_stream_ops i915_oa_stream_ops = { |
2676 | .destroy = i915_oa_stream_destroy, | |
2677 | .enable = i915_oa_stream_enable, | |
2678 | .disable = i915_oa_stream_disable, | |
2679 | .wait_unlocked = i915_oa_wait_unlocked, | |
2680 | .poll_wait = i915_oa_poll_wait, | |
2681 | .read = i915_oa_read, | |
eec688e1 RB |
2682 | }; |
2683 | ||
16d98b31 RB |
2684 | /** |
2685 | * i915_oa_stream_init - validate combined props for OA stream and init | |
2686 | * @stream: An i915 perf stream | |
2687 | * @param: The open parameters passed to `DRM_I915_PERF_OPEN` | |
2688 | * @props: The property state that configures stream (individually validated) | |
2689 | * | |
2690 | * While read_properties_unlocked() validates properties in isolation it | |
2691 | * doesn't ensure that the combination necessarily makes sense. | |
2692 | * | |
2693 | * At this point it has been determined that userspace wants a stream of | |
2694 | * OA metrics, but still we need to further validate the combined | |
2695 | * properties are OK. | |
2696 | * | |
2697 | * If the configuration makes sense then we can allocate memory for | |
2698 | * a circular OA buffer and apply the requested metric set configuration. | |
2699 | * | |
2700 | * Returns: zero on success or a negative error code. | |
2701 | */ | |
d7965152 RB |
2702 | static int i915_oa_stream_init(struct i915_perf_stream *stream, |
2703 | struct drm_i915_perf_open_param *param, | |
2704 | struct perf_open_properties *props) | |
2705 | { | |
8f8b1171 | 2706 | struct i915_perf *perf = stream->perf; |
d7965152 RB |
2707 | int format_size; |
2708 | int ret; | |
2709 | ||
9a61363a LL |
2710 | if (!props->engine) { |
2711 | DRM_DEBUG("OA engine not specified\n"); | |
2712 | return -EINVAL; | |
2713 | } | |
2714 | ||
2715 | /* | |
2716 | * If the sysfs metrics/ directory wasn't registered for some | |
442b8c06 RB |
2717 | * reason then don't let userspace try their luck with config |
2718 | * IDs | |
2719 | */ | |
8f8b1171 | 2720 | if (!perf->metrics_kobj) { |
7708550c | 2721 | DRM_DEBUG("OA metrics weren't advertised via sysfs\n"); |
442b8c06 RB |
2722 | return -EINVAL; |
2723 | } | |
2724 | ||
d7965152 | 2725 | if (!(props->sample_flags & SAMPLE_OA_REPORT)) { |
7708550c | 2726 | DRM_DEBUG("Only OA report sampling supported\n"); |
d7965152 RB |
2727 | return -EINVAL; |
2728 | } | |
2729 | ||
8f8b1171 | 2730 | if (!perf->ops.enable_metric_set) { |
7708550c | 2731 | DRM_DEBUG("OA unit not supported\n"); |
d7965152 RB |
2732 | return -ENODEV; |
2733 | } | |
2734 | ||
9a61363a LL |
2735 | /* |
2736 | * To avoid the complexity of having to accurately filter | |
d7965152 RB |
2737 | * counter reports and marshal to the appropriate client |
2738 | * we currently only allow exclusive access | |
2739 | */ | |
8f8b1171 | 2740 | if (perf->exclusive_stream) { |
7708550c | 2741 | DRM_DEBUG("OA unit already in use\n"); |
d7965152 RB |
2742 | return -EBUSY; |
2743 | } | |
2744 | ||
d7965152 | 2745 | if (!props->oa_format) { |
7708550c | 2746 | DRM_DEBUG("OA report format not specified\n"); |
d7965152 RB |
2747 | return -EINVAL; |
2748 | } | |
2749 | ||
9a61363a | 2750 | stream->engine = props->engine; |
52111c46 | 2751 | stream->uncore = stream->engine->gt->uncore; |
9a61363a | 2752 | |
d7965152 RB |
2753 | stream->sample_size = sizeof(struct drm_i915_perf_record_header); |
2754 | ||
8f8b1171 | 2755 | format_size = perf->oa_formats[props->oa_format].size; |
d7965152 RB |
2756 | |
2757 | stream->sample_flags |= SAMPLE_OA_REPORT; | |
2758 | stream->sample_size += format_size; | |
2759 | ||
a37f08a8 UNR |
2760 | stream->oa_buffer.format_size = format_size; |
2761 | if (WARN_ON(stream->oa_buffer.format_size == 0)) | |
d7965152 RB |
2762 | return -EINVAL; |
2763 | ||
9cd20ef7 LL |
2764 | stream->hold_preemption = props->hold_preemption; |
2765 | ||
a37f08a8 | 2766 | stream->oa_buffer.format = |
8f8b1171 | 2767 | perf->oa_formats[props->oa_format].format; |
d7965152 | 2768 | |
a37f08a8 UNR |
2769 | stream->periodic = props->oa_periodic; |
2770 | if (stream->periodic) | |
2771 | stream->period_exponent = props->oa_period_exponent; | |
d7965152 | 2772 | |
d7965152 RB |
2773 | if (stream->ctx) { |
2774 | ret = oa_get_render_ctx_id(stream); | |
9bd9be66 LL |
2775 | if (ret) { |
2776 | DRM_DEBUG("Invalid context id to filter with\n"); | |
d7965152 | 2777 | return ret; |
9bd9be66 | 2778 | } |
d7965152 RB |
2779 | } |
2780 | ||
daed3e44 LL |
2781 | ret = alloc_noa_wait(stream); |
2782 | if (ret) { | |
2783 | DRM_DEBUG("Unable to allocate NOA wait batch buffer\n"); | |
2784 | goto err_noa_wait_alloc; | |
2785 | } | |
2786 | ||
6a45008a LL |
2787 | stream->oa_config = i915_perf_get_oa_config(perf, props->metrics_set); |
2788 | if (!stream->oa_config) { | |
9bd9be66 | 2789 | DRM_DEBUG("Invalid OA config id=%i\n", props->metrics_set); |
6a45008a | 2790 | ret = -EINVAL; |
f89823c2 | 2791 | goto err_config; |
9bd9be66 | 2792 | } |
701f8231 | 2793 | |
d7965152 RB |
2794 | /* PRM - observability performance counters: |
2795 | * | |
2796 | * OACONTROL, performance counter enable, note: | |
2797 | * | |
2798 | * "When this bit is set, in order to have coherent counts, | |
2799 | * RC6 power state and trunk clock gating must be disabled. | |
2800 | * This can be achieved by programming MMIO registers as | |
2801 | * 0xA094=0 and 0xA090[31]=1" | |
2802 | * | |
2803 | * In our case we are expecting that taking pm + FORCEWAKE | |
2804 | * references will effectively disable RC6. | |
2805 | */ | |
a5efcde6 | 2806 | intel_engine_pm_get(stream->engine); |
52111c46 | 2807 | intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL); |
d7965152 | 2808 | |
a37f08a8 | 2809 | ret = alloc_oa_buffer(stream); |
987f8c44 | 2810 | if (ret) |
2811 | goto err_oa_buf_alloc; | |
2812 | ||
ec431eae | 2813 | stream->ops = &i915_oa_stream_ops; |
8f8b1171 | 2814 | perf->exclusive_stream = stream; |
ec431eae | 2815 | |
8f8b1171 | 2816 | ret = perf->ops.enable_metric_set(stream); |
9bd9be66 LL |
2817 | if (ret) { |
2818 | DRM_DEBUG("Unable to enable metric set\n"); | |
d7965152 | 2819 | goto err_enable; |
9bd9be66 | 2820 | } |
d7965152 | 2821 | |
6a45008a LL |
2822 | DRM_DEBUG("opening stream oa config uuid=%s\n", |
2823 | stream->oa_config->uuid); | |
2824 | ||
a37f08a8 UNR |
2825 | hrtimer_init(&stream->poll_check_timer, |
2826 | CLOCK_MONOTONIC, HRTIMER_MODE_REL); | |
2827 | stream->poll_check_timer.function = oa_poll_check_timer_cb; | |
2828 | init_waitqueue_head(&stream->poll_wq); | |
2829 | spin_lock_init(&stream->oa_buffer.ptr_lock); | |
2830 | ||
d7965152 RB |
2831 | return 0; |
2832 | ||
41d3fdcd | 2833 | err_enable: |
8f8b1171 CW |
2834 | perf->exclusive_stream = NULL; |
2835 | perf->ops.disable_metric_set(stream); | |
701f8231 | 2836 | |
a37f08a8 | 2837 | free_oa_buffer(stream); |
d7965152 RB |
2838 | |
2839 | err_oa_buf_alloc: | |
6a45008a | 2840 | free_oa_configs(stream); |
f89823c2 | 2841 | |
52111c46 | 2842 | intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL); |
a5efcde6 | 2843 | intel_engine_pm_put(stream->engine); |
f89823c2 LL |
2844 | |
2845 | err_config: | |
daed3e44 LL |
2846 | free_noa_wait(stream); |
2847 | ||
2848 | err_noa_wait_alloc: | |
d7965152 RB |
2849 | if (stream->ctx) |
2850 | oa_put_render_ctx_id(stream); | |
2851 | ||
2852 | return ret; | |
2853 | } | |
2854 | ||
7dc56af5 CW |
2855 | void i915_oa_init_reg_state(const struct intel_context *ce, |
2856 | const struct intel_engine_cs *engine) | |
19f81df2 | 2857 | { |
28b6cb08 | 2858 | struct i915_perf_stream *stream; |
19f81df2 | 2859 | |
00a7f0d7 | 2860 | /* perf.exclusive_stream serialised by lrc_configure_all_contexts() */ |
dffa8feb | 2861 | |
8a68d464 | 2862 | if (engine->class != RENDER_CLASS) |
19f81df2 RB |
2863 | return; |
2864 | ||
a37f08a8 | 2865 | stream = engine->i915->perf.exclusive_stream; |
701f8231 | 2866 | if (stream) |
7dc56af5 | 2867 | gen8_update_reg_state_unlocked(ce, stream); |
19f81df2 RB |
2868 | } |
2869 | ||
16d98b31 RB |
2870 | /** |
2871 | * i915_perf_read_locked - &i915_perf_stream_ops->read with error normalisation | |
2872 | * @stream: An i915 perf stream | |
2873 | * @file: An i915 perf stream file | |
2874 | * @buf: destination buffer given by userspace | |
2875 | * @count: the number of bytes userspace wants to read | |
2876 | * @ppos: (inout) file seek position (unused) | |
2877 | * | |
2878 | * Besides wrapping &i915_perf_stream_ops->read this provides a common place to | |
2879 | * ensure that if we've successfully copied any data then reporting that takes | |
2880 | * precedence over any internal error status, so the data isn't lost. | |
2881 | * | |
2882 | * For example ret will be -ENOSPC whenever there is more buffered data than | |
2883 | * can be copied to userspace, but that's only interesting if we weren't able | |
2884 | * to copy some data because it implies the userspace buffer is too small to | |
2885 | * receive a single record (and we never split records). | |
2886 | * | |
2887 | * Another case with ret == -EFAULT is more of a grey area since it would seem | |
2888 | * like bad form for userspace to ask us to overrun its buffer, but the user | |
2889 | * knows best: | |
2890 | * | |
2891 | * http://yarchive.net/comp/linux/partial_reads_writes.html | |
2892 | * | |
2893 | * Returns: The number of bytes copied or a negative error code on failure. | |
2894 | */ | |
eec688e1 RB |
2895 | static ssize_t i915_perf_read_locked(struct i915_perf_stream *stream, |
2896 | struct file *file, | |
2897 | char __user *buf, | |
2898 | size_t count, | |
2899 | loff_t *ppos) | |
2900 | { | |
2901 | /* Note we keep the offset (aka bytes read) separate from any | |
2902 | * error status so that the final check for whether we return | |
2903 | * the bytes read with a higher precedence than any error (see | |
2904 | * comment below) doesn't need to be handled/duplicated in | |
2905 | * stream->ops->read() implementations. | |
2906 | */ | |
2907 | size_t offset = 0; | |
2908 | int ret = stream->ops->read(stream, buf, count, &offset); | |
2909 | ||
eec688e1 RB |
2910 | return offset ?: (ret ?: -EAGAIN); |
2911 | } | |
2912 | ||
16d98b31 RB |
2913 | /** |
2914 | * i915_perf_read - handles read() FOP for i915 perf stream FDs | |
2915 | * @file: An i915 perf stream file | |
2916 | * @buf: destination buffer given by userspace | |
2917 | * @count: the number of bytes userspace wants to read | |
2918 | * @ppos: (inout) file seek position (unused) | |
2919 | * | |
2920 | * The entry point for handling a read() on a stream file descriptor from | |
2921 | * userspace. Most of the work is left to the i915_perf_read_locked() and | |
2922 | * &i915_perf_stream_ops->read but to save having stream implementations (of | |
2923 | * which we might have multiple later) we handle blocking read here. | |
2924 | * | |
2925 | * We can also consistently treat trying to read from a disabled stream | |
2926 | * as an IO error so implementations can assume the stream is enabled | |
2927 | * while reading. | |
2928 | * | |
2929 | * Returns: The number of bytes copied or a negative error code on failure. | |
2930 | */ | |
eec688e1 RB |
2931 | static ssize_t i915_perf_read(struct file *file, |
2932 | char __user *buf, | |
2933 | size_t count, | |
2934 | loff_t *ppos) | |
2935 | { | |
2936 | struct i915_perf_stream *stream = file->private_data; | |
8f8b1171 | 2937 | struct i915_perf *perf = stream->perf; |
eec688e1 RB |
2938 | ssize_t ret; |
2939 | ||
d7965152 RB |
2940 | /* To ensure it's handled consistently we simply treat all reads of a |
2941 | * disabled stream as an error. In particular it might otherwise lead | |
2942 | * to a deadlock for blocking file descriptors... | |
2943 | */ | |
2944 | if (!stream->enabled) | |
2945 | return -EIO; | |
2946 | ||
eec688e1 | 2947 | if (!(file->f_flags & O_NONBLOCK)) { |
d7965152 RB |
2948 | /* There's the small chance of false positives from |
2949 | * stream->ops->wait_unlocked. | |
2950 | * | |
2951 | * E.g. with single context filtering since we only wait until | |
2952 | * oabuffer has >= 1 report we don't immediately know whether | |
2953 | * any reports really belong to the current context | |
eec688e1 RB |
2954 | */ |
2955 | do { | |
2956 | ret = stream->ops->wait_unlocked(stream); | |
2957 | if (ret) | |
2958 | return ret; | |
2959 | ||
8f8b1171 | 2960 | mutex_lock(&perf->lock); |
eec688e1 RB |
2961 | ret = i915_perf_read_locked(stream, file, |
2962 | buf, count, ppos); | |
8f8b1171 | 2963 | mutex_unlock(&perf->lock); |
eec688e1 RB |
2964 | } while (ret == -EAGAIN); |
2965 | } else { | |
8f8b1171 | 2966 | mutex_lock(&perf->lock); |
eec688e1 | 2967 | ret = i915_perf_read_locked(stream, file, buf, count, ppos); |
8f8b1171 | 2968 | mutex_unlock(&perf->lock); |
eec688e1 RB |
2969 | } |
2970 | ||
a9a08845 | 2971 | /* We allow the poll checking to sometimes report false positive EPOLLIN |
26ebd9c7 RB |
2972 | * events where we might actually report EAGAIN on read() if there's |
2973 | * not really any data available. In this situation though we don't | |
a9a08845 | 2974 | * want to enter a busy loop between poll() reporting a EPOLLIN event |
26ebd9c7 RB |
2975 | * and read() returning -EAGAIN. Clearing the oa.pollin state here |
2976 | * effectively ensures we back off until the next hrtimer callback | |
a9a08845 | 2977 | * before reporting another EPOLLIN event. |
26ebd9c7 RB |
2978 | */ |
2979 | if (ret >= 0 || ret == -EAGAIN) { | |
d7965152 RB |
2980 | /* Maybe make ->pollin per-stream state if we support multiple |
2981 | * concurrent streams in the future. | |
2982 | */ | |
a37f08a8 | 2983 | stream->pollin = false; |
d7965152 RB |
2984 | } |
2985 | ||
eec688e1 RB |
2986 | return ret; |
2987 | } | |
2988 | ||
d7965152 RB |
2989 | static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer) |
2990 | { | |
a37f08a8 UNR |
2991 | struct i915_perf_stream *stream = |
2992 | container_of(hrtimer, typeof(*stream), poll_check_timer); | |
d7965152 | 2993 | |
a37f08a8 UNR |
2994 | if (oa_buffer_check_unlocked(stream)) { |
2995 | stream->pollin = true; | |
2996 | wake_up(&stream->poll_wq); | |
d7965152 RB |
2997 | } |
2998 | ||
2999 | hrtimer_forward_now(hrtimer, ns_to_ktime(POLL_PERIOD)); | |
3000 | ||
3001 | return HRTIMER_RESTART; | |
3002 | } | |
3003 | ||
16d98b31 RB |
3004 | /** |
3005 | * i915_perf_poll_locked - poll_wait() with a suitable wait queue for stream | |
16d98b31 RB |
3006 | * @stream: An i915 perf stream |
3007 | * @file: An i915 perf stream file | |
3008 | * @wait: poll() state table | |
3009 | * | |
3010 | * For handling userspace polling on an i915 perf stream, this calls through to | |
3011 | * &i915_perf_stream_ops->poll_wait to call poll_wait() with a wait queue that | |
3012 | * will be woken for new stream data. | |
3013 | * | |
8f8b1171 | 3014 | * Note: The &perf->lock mutex has been taken to serialize |
16d98b31 RB |
3015 | * with any non-file-operation driver hooks. |
3016 | * | |
3017 | * Returns: any poll events that are ready without sleeping | |
3018 | */ | |
8f8b1171 CW |
3019 | static __poll_t i915_perf_poll_locked(struct i915_perf_stream *stream, |
3020 | struct file *file, | |
3021 | poll_table *wait) | |
eec688e1 | 3022 | { |
afc9a42b | 3023 | __poll_t events = 0; |
eec688e1 RB |
3024 | |
3025 | stream->ops->poll_wait(stream, file, wait); | |
3026 | ||
d7965152 RB |
3027 | /* Note: we don't explicitly check whether there's something to read |
3028 | * here since this path may be very hot depending on what else | |
3029 | * userspace is polling, or on the timeout in use. We rely solely on | |
3030 | * the hrtimer/oa_poll_check_timer_cb to notify us when there are | |
3031 | * samples to read. | |
3032 | */ | |
a37f08a8 | 3033 | if (stream->pollin) |
a9a08845 | 3034 | events |= EPOLLIN; |
eec688e1 | 3035 | |
d7965152 | 3036 | return events; |
eec688e1 RB |
3037 | } |
3038 | ||
16d98b31 RB |
3039 | /** |
3040 | * i915_perf_poll - call poll_wait() with a suitable wait queue for stream | |
3041 | * @file: An i915 perf stream file | |
3042 | * @wait: poll() state table | |
3043 | * | |
3044 | * For handling userspace polling on an i915 perf stream, this ensures | |
3045 | * poll_wait() gets called with a wait queue that will be woken for new stream | |
3046 | * data. | |
3047 | * | |
3048 | * Note: Implementation deferred to i915_perf_poll_locked() | |
3049 | * | |
3050 | * Returns: any poll events that are ready without sleeping | |
3051 | */ | |
afc9a42b | 3052 | static __poll_t i915_perf_poll(struct file *file, poll_table *wait) |
eec688e1 RB |
3053 | { |
3054 | struct i915_perf_stream *stream = file->private_data; | |
8f8b1171 | 3055 | struct i915_perf *perf = stream->perf; |
afc9a42b | 3056 | __poll_t ret; |
eec688e1 | 3057 | |
8f8b1171 CW |
3058 | mutex_lock(&perf->lock); |
3059 | ret = i915_perf_poll_locked(stream, file, wait); | |
3060 | mutex_unlock(&perf->lock); | |
eec688e1 RB |
3061 | |
3062 | return ret; | |
3063 | } | |
3064 | ||
16d98b31 RB |
3065 | /** |
3066 | * i915_perf_enable_locked - handle `I915_PERF_IOCTL_ENABLE` ioctl | |
3067 | * @stream: A disabled i915 perf stream | |
3068 | * | |
3069 | * [Re]enables the associated capture of data for this stream. | |
3070 | * | |
3071 | * If a stream was previously enabled then there's currently no intention | |
3072 | * to provide userspace any guarantee about the preservation of previously | |
3073 | * buffered data. | |
3074 | */ | |
eec688e1 RB |
3075 | static void i915_perf_enable_locked(struct i915_perf_stream *stream) |
3076 | { | |
3077 | if (stream->enabled) | |
3078 | return; | |
3079 | ||
3080 | /* Allow stream->ops->enable() to refer to this */ | |
3081 | stream->enabled = true; | |
3082 | ||
3083 | if (stream->ops->enable) | |
3084 | stream->ops->enable(stream); | |
9cd20ef7 LL |
3085 | |
3086 | if (stream->hold_preemption) | |
3087 | i915_gem_context_set_nopreempt(stream->ctx); | |
eec688e1 RB |
3088 | } |
3089 | ||
16d98b31 RB |
3090 | /** |
3091 | * i915_perf_disable_locked - handle `I915_PERF_IOCTL_DISABLE` ioctl | |
3092 | * @stream: An enabled i915 perf stream | |
3093 | * | |
3094 | * Disables the associated capture of data for this stream. | |
3095 | * | |
3096 | * The intention is that disabling an re-enabling a stream will ideally be | |
3097 | * cheaper than destroying and re-opening a stream with the same configuration, | |
3098 | * though there are no formal guarantees about what state or buffered data | |
3099 | * must be retained between disabling and re-enabling a stream. | |
3100 | * | |
3101 | * Note: while a stream is disabled it's considered an error for userspace | |
3102 | * to attempt to read from the stream (-EIO). | |
3103 | */ | |
eec688e1 RB |
3104 | static void i915_perf_disable_locked(struct i915_perf_stream *stream) |
3105 | { | |
3106 | if (!stream->enabled) | |
3107 | return; | |
3108 | ||
3109 | /* Allow stream->ops->disable() to refer to this */ | |
3110 | stream->enabled = false; | |
3111 | ||
9cd20ef7 LL |
3112 | if (stream->hold_preemption) |
3113 | i915_gem_context_clear_nopreempt(stream->ctx); | |
3114 | ||
eec688e1 RB |
3115 | if (stream->ops->disable) |
3116 | stream->ops->disable(stream); | |
3117 | } | |
3118 | ||
7831e9a9 CW |
3119 | static long i915_perf_config_locked(struct i915_perf_stream *stream, |
3120 | unsigned long metrics_set) | |
3121 | { | |
3122 | struct i915_oa_config *config; | |
3123 | long ret = stream->oa_config->id; | |
3124 | ||
3125 | config = i915_perf_get_oa_config(stream->perf, metrics_set); | |
3126 | if (!config) | |
3127 | return -EINVAL; | |
3128 | ||
3129 | if (config != stream->oa_config) { | |
3130 | int err; | |
3131 | ||
3132 | /* | |
3133 | * If OA is bound to a specific context, emit the | |
3134 | * reconfiguration inline from that context. The update | |
3135 | * will then be ordered with respect to submission on that | |
3136 | * context. | |
3137 | * | |
3138 | * When set globally, we use a low priority kernel context, | |
3139 | * so it will effectively take effect when idle. | |
3140 | */ | |
8814c6d0 | 3141 | err = emit_oa_config(stream, config, oa_context(stream)); |
7831e9a9 CW |
3142 | if (err == 0) |
3143 | config = xchg(&stream->oa_config, config); | |
3144 | else | |
3145 | ret = err; | |
3146 | } | |
3147 | ||
3148 | i915_oa_config_put(config); | |
3149 | ||
3150 | return ret; | |
3151 | } | |
3152 | ||
16d98b31 RB |
3153 | /** |
3154 | * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs | |
3155 | * @stream: An i915 perf stream | |
3156 | * @cmd: the ioctl request | |
3157 | * @arg: the ioctl data | |
3158 | * | |
8f8b1171 | 3159 | * Note: The &perf->lock mutex has been taken to serialize |
16d98b31 RB |
3160 | * with any non-file-operation driver hooks. |
3161 | * | |
3162 | * Returns: zero on success or a negative error code. Returns -EINVAL for | |
3163 | * an unknown ioctl request. | |
3164 | */ | |
eec688e1 RB |
3165 | static long i915_perf_ioctl_locked(struct i915_perf_stream *stream, |
3166 | unsigned int cmd, | |
3167 | unsigned long arg) | |
3168 | { | |
3169 | switch (cmd) { | |
3170 | case I915_PERF_IOCTL_ENABLE: | |
3171 | i915_perf_enable_locked(stream); | |
3172 | return 0; | |
3173 | case I915_PERF_IOCTL_DISABLE: | |
3174 | i915_perf_disable_locked(stream); | |
3175 | return 0; | |
7831e9a9 CW |
3176 | case I915_PERF_IOCTL_CONFIG: |
3177 | return i915_perf_config_locked(stream, arg); | |
eec688e1 RB |
3178 | } |
3179 | ||
3180 | return -EINVAL; | |
3181 | } | |
3182 | ||
16d98b31 RB |
3183 | /** |
3184 | * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs | |
3185 | * @file: An i915 perf stream file | |
3186 | * @cmd: the ioctl request | |
3187 | * @arg: the ioctl data | |
3188 | * | |
3189 | * Implementation deferred to i915_perf_ioctl_locked(). | |
3190 | * | |
3191 | * Returns: zero on success or a negative error code. Returns -EINVAL for | |
3192 | * an unknown ioctl request. | |
3193 | */ | |
eec688e1 RB |
3194 | static long i915_perf_ioctl(struct file *file, |
3195 | unsigned int cmd, | |
3196 | unsigned long arg) | |
3197 | { | |
3198 | struct i915_perf_stream *stream = file->private_data; | |
8f8b1171 | 3199 | struct i915_perf *perf = stream->perf; |
eec688e1 RB |
3200 | long ret; |
3201 | ||
8f8b1171 | 3202 | mutex_lock(&perf->lock); |
eec688e1 | 3203 | ret = i915_perf_ioctl_locked(stream, cmd, arg); |
8f8b1171 | 3204 | mutex_unlock(&perf->lock); |
eec688e1 RB |
3205 | |
3206 | return ret; | |
3207 | } | |
3208 | ||
16d98b31 RB |
3209 | /** |
3210 | * i915_perf_destroy_locked - destroy an i915 perf stream | |
3211 | * @stream: An i915 perf stream | |
3212 | * | |
3213 | * Frees all resources associated with the given i915 perf @stream, disabling | |
3214 | * any associated data capture in the process. | |
3215 | * | |
8f8b1171 | 3216 | * Note: The &perf->lock mutex has been taken to serialize |
16d98b31 RB |
3217 | * with any non-file-operation driver hooks. |
3218 | */ | |
eec688e1 RB |
3219 | static void i915_perf_destroy_locked(struct i915_perf_stream *stream) |
3220 | { | |
eec688e1 RB |
3221 | if (stream->enabled) |
3222 | i915_perf_disable_locked(stream); | |
3223 | ||
3224 | if (stream->ops->destroy) | |
3225 | stream->ops->destroy(stream); | |
3226 | ||
69df05e1 | 3227 | if (stream->ctx) |
5f09a9c8 | 3228 | i915_gem_context_put(stream->ctx); |
eec688e1 RB |
3229 | |
3230 | kfree(stream); | |
3231 | } | |
3232 | ||
16d98b31 RB |
3233 | /** |
3234 | * i915_perf_release - handles userspace close() of a stream file | |
3235 | * @inode: anonymous inode associated with file | |
3236 | * @file: An i915 perf stream file | |
3237 | * | |
3238 | * Cleans up any resources associated with an open i915 perf stream file. | |
3239 | * | |
3240 | * NB: close() can't really fail from the userspace point of view. | |
3241 | * | |
3242 | * Returns: zero on success or a negative error code. | |
3243 | */ | |
eec688e1 RB |
3244 | static int i915_perf_release(struct inode *inode, struct file *file) |
3245 | { | |
3246 | struct i915_perf_stream *stream = file->private_data; | |
8f8b1171 | 3247 | struct i915_perf *perf = stream->perf; |
eec688e1 | 3248 | |
8f8b1171 | 3249 | mutex_lock(&perf->lock); |
eec688e1 | 3250 | i915_perf_destroy_locked(stream); |
8f8b1171 | 3251 | mutex_unlock(&perf->lock); |
eec688e1 | 3252 | |
a5af1df7 | 3253 | /* Release the reference the perf stream kept on the driver. */ |
8f8b1171 | 3254 | drm_dev_put(&perf->i915->drm); |
a5af1df7 | 3255 | |
eec688e1 RB |
3256 | return 0; |
3257 | } | |
3258 | ||
3259 | ||
3260 | static const struct file_operations fops = { | |
3261 | .owner = THIS_MODULE, | |
3262 | .llseek = no_llseek, | |
3263 | .release = i915_perf_release, | |
3264 | .poll = i915_perf_poll, | |
3265 | .read = i915_perf_read, | |
3266 | .unlocked_ioctl = i915_perf_ioctl, | |
191f8960 LL |
3267 | /* Our ioctl have no arguments, so it's safe to use the same function |
3268 | * to handle 32bits compatibility. | |
3269 | */ | |
3270 | .compat_ioctl = i915_perf_ioctl, | |
eec688e1 RB |
3271 | }; |
3272 | ||
3273 | ||
16d98b31 RB |
3274 | /** |
3275 | * i915_perf_open_ioctl_locked - DRM ioctl() for userspace to open a stream FD | |
8f8b1171 | 3276 | * @perf: i915 perf instance |
16d98b31 RB |
3277 | * @param: The open parameters passed to 'DRM_I915_PERF_OPEN` |
3278 | * @props: individually validated u64 property value pairs | |
3279 | * @file: drm file | |
3280 | * | |
3281 | * See i915_perf_ioctl_open() for interface details. | |
3282 | * | |
3283 | * Implements further stream config validation and stream initialization on | |
8f8b1171 | 3284 | * behalf of i915_perf_open_ioctl() with the &perf->lock mutex |
16d98b31 RB |
3285 | * taken to serialize with any non-file-operation driver hooks. |
3286 | * | |
3287 | * Note: at this point the @props have only been validated in isolation and | |
3288 | * it's still necessary to validate that the combination of properties makes | |
3289 | * sense. | |
3290 | * | |
3291 | * In the case where userspace is interested in OA unit metrics then further | |
3292 | * config validation and stream initialization details will be handled by | |
3293 | * i915_oa_stream_init(). The code here should only validate config state that | |
3294 | * will be relevant to all stream types / backends. | |
3295 | * | |
3296 | * Returns: zero on success or a negative error code. | |
3297 | */ | |
eec688e1 | 3298 | static int |
8f8b1171 | 3299 | i915_perf_open_ioctl_locked(struct i915_perf *perf, |
eec688e1 RB |
3300 | struct drm_i915_perf_open_param *param, |
3301 | struct perf_open_properties *props, | |
3302 | struct drm_file *file) | |
3303 | { | |
3304 | struct i915_gem_context *specific_ctx = NULL; | |
3305 | struct i915_perf_stream *stream = NULL; | |
3306 | unsigned long f_flags = 0; | |
19f81df2 | 3307 | bool privileged_op = true; |
eec688e1 RB |
3308 | int stream_fd; |
3309 | int ret; | |
3310 | ||
3311 | if (props->single_context) { | |
3312 | u32 ctx_handle = props->ctx_handle; | |
3313 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
3314 | ||
635f56c3 ID |
3315 | specific_ctx = i915_gem_context_lookup(file_priv, ctx_handle); |
3316 | if (!specific_ctx) { | |
3317 | DRM_DEBUG("Failed to look up context with ID %u for opening perf stream\n", | |
3318 | ctx_handle); | |
3319 | ret = -ENOENT; | |
eec688e1 RB |
3320 | goto err; |
3321 | } | |
3322 | } | |
3323 | ||
19f81df2 RB |
3324 | /* |
3325 | * On Haswell the OA unit supports clock gating off for a specific | |
3326 | * context and in this mode there's no visibility of metrics for the | |
3327 | * rest of the system, which we consider acceptable for a | |
3328 | * non-privileged client. | |
3329 | * | |
00a7f0d7 | 3330 | * For Gen8->11 the OA unit no longer supports clock gating off for a |
19f81df2 RB |
3331 | * specific context and the kernel can't securely stop the counters |
3332 | * from updating as system-wide / global values. Even though we can | |
3333 | * filter reports based on the included context ID we can't block | |
3334 | * clients from seeing the raw / global counter values via | |
3335 | * MI_REPORT_PERF_COUNT commands and so consider it a privileged op to | |
3336 | * enable the OA unit by default. | |
00a7f0d7 LL |
3337 | * |
3338 | * For Gen12+ we gain a new OAR unit that only monitors the RCS on a | |
3339 | * per context basis. So we can relax requirements there if the user | |
3340 | * doesn't request global stream access (i.e. query based sampling | |
3341 | * using MI_RECORD_PERF_COUNT. | |
19f81df2 | 3342 | */ |
0b0120d4 | 3343 | if (IS_HASWELL(perf->i915) && specific_ctx) |
19f81df2 | 3344 | privileged_op = false; |
00a7f0d7 LL |
3345 | else if (IS_GEN(perf->i915, 12) && specific_ctx && |
3346 | (props->sample_flags & SAMPLE_OA_REPORT) == 0) | |
3347 | privileged_op = false; | |
19f81df2 | 3348 | |
0b0120d4 LL |
3349 | if (props->hold_preemption) { |
3350 | if (!props->single_context) { | |
3351 | DRM_DEBUG("preemption disable with no context\n"); | |
3352 | ret = -EINVAL; | |
3353 | goto err; | |
3354 | } | |
3355 | privileged_op = true; | |
3356 | } | |
3357 | ||
ccdf6341 RB |
3358 | /* Similar to perf's kernel.perf_paranoid_cpu sysctl option |
3359 | * we check a dev.i915.perf_stream_paranoid sysctl option | |
3360 | * to determine if it's ok to access system wide OA counters | |
3361 | * without CAP_SYS_ADMIN privileges. | |
3362 | */ | |
19f81df2 | 3363 | if (privileged_op && |
ccdf6341 | 3364 | i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) { |
9cd20ef7 | 3365 | DRM_DEBUG("Insufficient privileges to open i915 perf stream\n"); |
eec688e1 RB |
3366 | ret = -EACCES; |
3367 | goto err_ctx; | |
3368 | } | |
3369 | ||
3370 | stream = kzalloc(sizeof(*stream), GFP_KERNEL); | |
3371 | if (!stream) { | |
3372 | ret = -ENOMEM; | |
3373 | goto err_ctx; | |
3374 | } | |
3375 | ||
8f8b1171 | 3376 | stream->perf = perf; |
eec688e1 RB |
3377 | stream->ctx = specific_ctx; |
3378 | ||
d7965152 RB |
3379 | ret = i915_oa_stream_init(stream, param, props); |
3380 | if (ret) | |
3381 | goto err_alloc; | |
3382 | ||
3383 | /* we avoid simply assigning stream->sample_flags = props->sample_flags | |
3384 | * to have _stream_init check the combination of sample flags more | |
3385 | * thoroughly, but still this is the expected result at this point. | |
eec688e1 | 3386 | */ |
d7965152 RB |
3387 | if (WARN_ON(stream->sample_flags != props->sample_flags)) { |
3388 | ret = -ENODEV; | |
22f880ca | 3389 | goto err_flags; |
d7965152 | 3390 | } |
eec688e1 | 3391 | |
eec688e1 RB |
3392 | if (param->flags & I915_PERF_FLAG_FD_CLOEXEC) |
3393 | f_flags |= O_CLOEXEC; | |
3394 | if (param->flags & I915_PERF_FLAG_FD_NONBLOCK) | |
3395 | f_flags |= O_NONBLOCK; | |
3396 | ||
3397 | stream_fd = anon_inode_getfd("[i915_perf]", &fops, stream, f_flags); | |
3398 | if (stream_fd < 0) { | |
3399 | ret = stream_fd; | |
23b9e41a | 3400 | goto err_flags; |
eec688e1 RB |
3401 | } |
3402 | ||
3403 | if (!(param->flags & I915_PERF_FLAG_DISABLED)) | |
3404 | i915_perf_enable_locked(stream); | |
3405 | ||
a5af1df7 LL |
3406 | /* Take a reference on the driver that will be kept with stream_fd |
3407 | * until its release. | |
3408 | */ | |
8f8b1171 | 3409 | drm_dev_get(&perf->i915->drm); |
a5af1df7 | 3410 | |
eec688e1 RB |
3411 | return stream_fd; |
3412 | ||
22f880ca | 3413 | err_flags: |
eec688e1 RB |
3414 | if (stream->ops->destroy) |
3415 | stream->ops->destroy(stream); | |
3416 | err_alloc: | |
3417 | kfree(stream); | |
3418 | err_ctx: | |
69df05e1 | 3419 | if (specific_ctx) |
5f09a9c8 | 3420 | i915_gem_context_put(specific_ctx); |
eec688e1 RB |
3421 | err: |
3422 | return ret; | |
3423 | } | |
3424 | ||
8f8b1171 | 3425 | static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent) |
155e941f | 3426 | { |
9f9b2792 | 3427 | return div64_u64(1000000000ULL * (2ULL << exponent), |
8f8b1171 | 3428 | 1000ULL * RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz); |
155e941f RB |
3429 | } |
3430 | ||
16d98b31 RB |
3431 | /** |
3432 | * read_properties_unlocked - validate + copy userspace stream open properties | |
8f8b1171 | 3433 | * @perf: i915 perf instance |
16d98b31 RB |
3434 | * @uprops: The array of u64 key value pairs given by userspace |
3435 | * @n_props: The number of key value pairs expected in @uprops | |
3436 | * @props: The stream configuration built up while validating properties | |
eec688e1 RB |
3437 | * |
3438 | * Note this function only validates properties in isolation it doesn't | |
3439 | * validate that the combination of properties makes sense or that all | |
3440 | * properties necessary for a particular kind of stream have been set. | |
16d98b31 RB |
3441 | * |
3442 | * Note that there currently aren't any ordering requirements for properties so | |
3443 | * we shouldn't validate or assume anything about ordering here. This doesn't | |
3444 | * rule out defining new properties with ordering requirements in the future. | |
eec688e1 | 3445 | */ |
8f8b1171 | 3446 | static int read_properties_unlocked(struct i915_perf *perf, |
eec688e1 RB |
3447 | u64 __user *uprops, |
3448 | u32 n_props, | |
3449 | struct perf_open_properties *props) | |
3450 | { | |
3451 | u64 __user *uprop = uprops; | |
701f8231 | 3452 | u32 i; |
eec688e1 RB |
3453 | |
3454 | memset(props, 0, sizeof(struct perf_open_properties)); | |
3455 | ||
3456 | if (!n_props) { | |
7708550c | 3457 | DRM_DEBUG("No i915 perf properties given\n"); |
eec688e1 RB |
3458 | return -EINVAL; |
3459 | } | |
3460 | ||
9a61363a LL |
3461 | /* At the moment we only support using i915-perf on the RCS. */ |
3462 | props->engine = intel_engine_lookup_user(perf->i915, | |
3463 | I915_ENGINE_CLASS_RENDER, | |
3464 | 0); | |
3465 | if (!props->engine) { | |
3466 | DRM_DEBUG("No RENDER-capable engines\n"); | |
3467 | return -EINVAL; | |
3468 | } | |
3469 | ||
eec688e1 RB |
3470 | /* Considering that ID = 0 is reserved and assuming that we don't |
3471 | * (currently) expect any configurations to ever specify duplicate | |
3472 | * values for a particular property ID then the last _PROP_MAX value is | |
3473 | * one greater than the maximum number of properties we expect to get | |
3474 | * from userspace. | |
3475 | */ | |
3476 | if (n_props >= DRM_I915_PERF_PROP_MAX) { | |
7708550c | 3477 | DRM_DEBUG("More i915 perf properties specified than exist\n"); |
eec688e1 RB |
3478 | return -EINVAL; |
3479 | } | |
3480 | ||
3481 | for (i = 0; i < n_props; i++) { | |
00319ba0 | 3482 | u64 oa_period, oa_freq_hz; |
eec688e1 RB |
3483 | u64 id, value; |
3484 | int ret; | |
3485 | ||
3486 | ret = get_user(id, uprop); | |
3487 | if (ret) | |
3488 | return ret; | |
3489 | ||
3490 | ret = get_user(value, uprop + 1); | |
3491 | if (ret) | |
3492 | return ret; | |
3493 | ||
0a309f9e MA |
3494 | if (id == 0 || id >= DRM_I915_PERF_PROP_MAX) { |
3495 | DRM_DEBUG("Unknown i915 perf property ID\n"); | |
3496 | return -EINVAL; | |
3497 | } | |
3498 | ||
eec688e1 RB |
3499 | switch ((enum drm_i915_perf_property_id)id) { |
3500 | case DRM_I915_PERF_PROP_CTX_HANDLE: | |
3501 | props->single_context = 1; | |
3502 | props->ctx_handle = value; | |
3503 | break; | |
d7965152 | 3504 | case DRM_I915_PERF_PROP_SAMPLE_OA: |
b6dd47b9 LL |
3505 | if (value) |
3506 | props->sample_flags |= SAMPLE_OA_REPORT; | |
d7965152 RB |
3507 | break; |
3508 | case DRM_I915_PERF_PROP_OA_METRICS_SET: | |
701f8231 | 3509 | if (value == 0) { |
7708550c | 3510 | DRM_DEBUG("Unknown OA metric set ID\n"); |
d7965152 RB |
3511 | return -EINVAL; |
3512 | } | |
3513 | props->metrics_set = value; | |
3514 | break; | |
3515 | case DRM_I915_PERF_PROP_OA_FORMAT: | |
3516 | if (value == 0 || value >= I915_OA_FORMAT_MAX) { | |
52c57c26 RB |
3517 | DRM_DEBUG("Out-of-range OA report format %llu\n", |
3518 | value); | |
d7965152 RB |
3519 | return -EINVAL; |
3520 | } | |
8f8b1171 | 3521 | if (!perf->oa_formats[value].size) { |
52c57c26 RB |
3522 | DRM_DEBUG("Unsupported OA report format %llu\n", |
3523 | value); | |
d7965152 RB |
3524 | return -EINVAL; |
3525 | } | |
3526 | props->oa_format = value; | |
3527 | break; | |
3528 | case DRM_I915_PERF_PROP_OA_EXPONENT: | |
3529 | if (value > OA_EXPONENT_MAX) { | |
7708550c RB |
3530 | DRM_DEBUG("OA timer exponent too high (> %u)\n", |
3531 | OA_EXPONENT_MAX); | |
d7965152 RB |
3532 | return -EINVAL; |
3533 | } | |
3534 | ||
00319ba0 | 3535 | /* Theoretically we can program the OA unit to sample |
155e941f RB |
3536 | * e.g. every 160ns for HSW, 167ns for BDW/SKL or 104ns |
3537 | * for BXT. We don't allow such high sampling | |
3538 | * frequencies by default unless root. | |
00319ba0 | 3539 | */ |
155e941f | 3540 | |
00319ba0 | 3541 | BUILD_BUG_ON(sizeof(oa_period) != 8); |
8f8b1171 | 3542 | oa_period = oa_exponent_to_ns(perf, value); |
00319ba0 RB |
3543 | |
3544 | /* This check is primarily to ensure that oa_period <= | |
3545 | * UINT32_MAX (before passing to do_div which only | |
3546 | * accepts a u32 denominator), but we can also skip | |
3547 | * checking anything < 1Hz which implicitly can't be | |
3548 | * limited via an integer oa_max_sample_rate. | |
d7965152 | 3549 | */ |
00319ba0 RB |
3550 | if (oa_period <= NSEC_PER_SEC) { |
3551 | u64 tmp = NSEC_PER_SEC; | |
3552 | do_div(tmp, oa_period); | |
3553 | oa_freq_hz = tmp; | |
3554 | } else | |
3555 | oa_freq_hz = 0; | |
3556 | ||
3557 | if (oa_freq_hz > i915_oa_max_sample_rate && | |
3558 | !capable(CAP_SYS_ADMIN)) { | |
7708550c | 3559 | DRM_DEBUG("OA exponent would exceed the max sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without root privileges\n", |
00319ba0 | 3560 | i915_oa_max_sample_rate); |
d7965152 RB |
3561 | return -EACCES; |
3562 | } | |
3563 | ||
3564 | props->oa_periodic = true; | |
3565 | props->oa_period_exponent = value; | |
3566 | break; | |
9cd20ef7 LL |
3567 | case DRM_I915_PERF_PROP_HOLD_PREEMPTION: |
3568 | props->hold_preemption = !!value; | |
3569 | break; | |
0a309f9e | 3570 | case DRM_I915_PERF_PROP_MAX: |
eec688e1 | 3571 | MISSING_CASE(id); |
eec688e1 RB |
3572 | return -EINVAL; |
3573 | } | |
3574 | ||
3575 | uprop += 2; | |
3576 | } | |
3577 | ||
3578 | return 0; | |
3579 | } | |
3580 | ||
16d98b31 RB |
3581 | /** |
3582 | * i915_perf_open_ioctl - DRM ioctl() for userspace to open a stream FD | |
3583 | * @dev: drm device | |
3584 | * @data: ioctl data copied from userspace (unvalidated) | |
3585 | * @file: drm file | |
3586 | * | |
3587 | * Validates the stream open parameters given by userspace including flags | |
3588 | * and an array of u64 key, value pair properties. | |
3589 | * | |
3590 | * Very little is assumed up front about the nature of the stream being | |
3591 | * opened (for instance we don't assume it's for periodic OA unit metrics). An | |
3592 | * i915-perf stream is expected to be a suitable interface for other forms of | |
3593 | * buffered data written by the GPU besides periodic OA metrics. | |
3594 | * | |
3595 | * Note we copy the properties from userspace outside of the i915 perf | |
3596 | * mutex to avoid an awkward lockdep with mmap_sem. | |
3597 | * | |
3598 | * Most of the implementation details are handled by | |
8f8b1171 | 3599 | * i915_perf_open_ioctl_locked() after taking the &perf->lock |
16d98b31 RB |
3600 | * mutex for serializing with any non-file-operation driver hooks. |
3601 | * | |
3602 | * Return: A newly opened i915 Perf stream file descriptor or negative | |
3603 | * error code on failure. | |
3604 | */ | |
eec688e1 RB |
3605 | int i915_perf_open_ioctl(struct drm_device *dev, void *data, |
3606 | struct drm_file *file) | |
3607 | { | |
8f8b1171 | 3608 | struct i915_perf *perf = &to_i915(dev)->perf; |
eec688e1 RB |
3609 | struct drm_i915_perf_open_param *param = data; |
3610 | struct perf_open_properties props; | |
3611 | u32 known_open_flags; | |
3612 | int ret; | |
3613 | ||
8f8b1171 | 3614 | if (!perf->i915) { |
7708550c | 3615 | DRM_DEBUG("i915 perf interface not available for this system\n"); |
eec688e1 RB |
3616 | return -ENOTSUPP; |
3617 | } | |
3618 | ||
3619 | known_open_flags = I915_PERF_FLAG_FD_CLOEXEC | | |
3620 | I915_PERF_FLAG_FD_NONBLOCK | | |
3621 | I915_PERF_FLAG_DISABLED; | |
3622 | if (param->flags & ~known_open_flags) { | |
7708550c | 3623 | DRM_DEBUG("Unknown drm_i915_perf_open_param flag\n"); |
eec688e1 RB |
3624 | return -EINVAL; |
3625 | } | |
3626 | ||
8f8b1171 | 3627 | ret = read_properties_unlocked(perf, |
eec688e1 RB |
3628 | u64_to_user_ptr(param->properties_ptr), |
3629 | param->num_properties, | |
3630 | &props); | |
3631 | if (ret) | |
3632 | return ret; | |
3633 | ||
8f8b1171 CW |
3634 | mutex_lock(&perf->lock); |
3635 | ret = i915_perf_open_ioctl_locked(perf, param, &props, file); | |
3636 | mutex_unlock(&perf->lock); | |
eec688e1 RB |
3637 | |
3638 | return ret; | |
3639 | } | |
3640 | ||
16d98b31 RB |
3641 | /** |
3642 | * i915_perf_register - exposes i915-perf to userspace | |
8f8b1171 | 3643 | * @i915: i915 device instance |
16d98b31 RB |
3644 | * |
3645 | * In particular OA metric sets are advertised under a sysfs metrics/ | |
3646 | * directory allowing userspace to enumerate valid IDs that can be | |
3647 | * used to open an i915-perf stream. | |
3648 | */ | |
8f8b1171 | 3649 | void i915_perf_register(struct drm_i915_private *i915) |
442b8c06 | 3650 | { |
8f8b1171 | 3651 | struct i915_perf *perf = &i915->perf; |
701f8231 LL |
3652 | int ret; |
3653 | ||
8f8b1171 | 3654 | if (!perf->i915) |
442b8c06 RB |
3655 | return; |
3656 | ||
3657 | /* To be sure we're synchronized with an attempted | |
3658 | * i915_perf_open_ioctl(); considering that we register after | |
3659 | * being exposed to userspace. | |
3660 | */ | |
8f8b1171 | 3661 | mutex_lock(&perf->lock); |
442b8c06 | 3662 | |
8f8b1171 | 3663 | perf->metrics_kobj = |
442b8c06 | 3664 | kobject_create_and_add("metrics", |
8f8b1171 CW |
3665 | &i915->drm.primary->kdev->kobj); |
3666 | if (!perf->metrics_kobj) | |
442b8c06 RB |
3667 | goto exit; |
3668 | ||
8f8b1171 CW |
3669 | sysfs_attr_init(&perf->test_config.sysfs_metric_id.attr); |
3670 | ||
00a7f0d7 LL |
3671 | if (IS_TIGERLAKE(i915)) { |
3672 | i915_perf_load_test_config_tgl(i915); | |
3673 | } else if (INTEL_GEN(i915) >= 11) { | |
8f8b1171 CW |
3674 | i915_perf_load_test_config_icl(i915); |
3675 | } else if (IS_CANNONLAKE(i915)) { | |
3676 | i915_perf_load_test_config_cnl(i915); | |
3677 | } else if (IS_COFFEELAKE(i915)) { | |
3678 | if (IS_CFL_GT2(i915)) | |
3679 | i915_perf_load_test_config_cflgt2(i915); | |
3680 | if (IS_CFL_GT3(i915)) | |
3681 | i915_perf_load_test_config_cflgt3(i915); | |
3682 | } else if (IS_GEMINILAKE(i915)) { | |
3683 | i915_perf_load_test_config_glk(i915); | |
3684 | } else if (IS_KABYLAKE(i915)) { | |
3685 | if (IS_KBL_GT2(i915)) | |
3686 | i915_perf_load_test_config_kblgt2(i915); | |
3687 | else if (IS_KBL_GT3(i915)) | |
3688 | i915_perf_load_test_config_kblgt3(i915); | |
3689 | } else if (IS_BROXTON(i915)) { | |
3690 | i915_perf_load_test_config_bxt(i915); | |
3691 | } else if (IS_SKYLAKE(i915)) { | |
3692 | if (IS_SKL_GT2(i915)) | |
3693 | i915_perf_load_test_config_sklgt2(i915); | |
3694 | else if (IS_SKL_GT3(i915)) | |
3695 | i915_perf_load_test_config_sklgt3(i915); | |
3696 | else if (IS_SKL_GT4(i915)) | |
3697 | i915_perf_load_test_config_sklgt4(i915); | |
3698 | } else if (IS_CHERRYVIEW(i915)) { | |
3699 | i915_perf_load_test_config_chv(i915); | |
3700 | } else if (IS_BROADWELL(i915)) { | |
3701 | i915_perf_load_test_config_bdw(i915); | |
3702 | } else if (IS_HASWELL(i915)) { | |
3703 | i915_perf_load_test_config_hsw(i915); | |
3704 | } | |
3705 | ||
3706 | if (perf->test_config.id == 0) | |
701f8231 LL |
3707 | goto sysfs_error; |
3708 | ||
8f8b1171 CW |
3709 | ret = sysfs_create_group(perf->metrics_kobj, |
3710 | &perf->test_config.sysfs_metric); | |
701f8231 LL |
3711 | if (ret) |
3712 | goto sysfs_error; | |
f89823c2 | 3713 | |
6a45008a LL |
3714 | perf->test_config.perf = perf; |
3715 | kref_init(&perf->test_config.ref); | |
f89823c2 | 3716 | |
19f81df2 RB |
3717 | goto exit; |
3718 | ||
3719 | sysfs_error: | |
8f8b1171 CW |
3720 | kobject_put(perf->metrics_kobj); |
3721 | perf->metrics_kobj = NULL; | |
19f81df2 | 3722 | |
442b8c06 | 3723 | exit: |
8f8b1171 | 3724 | mutex_unlock(&perf->lock); |
442b8c06 RB |
3725 | } |
3726 | ||
16d98b31 RB |
3727 | /** |
3728 | * i915_perf_unregister - hide i915-perf from userspace | |
8f8b1171 | 3729 | * @i915: i915 device instance |
16d98b31 RB |
3730 | * |
3731 | * i915-perf state cleanup is split up into an 'unregister' and | |
3732 | * 'deinit' phase where the interface is first hidden from | |
3733 | * userspace by i915_perf_unregister() before cleaning up | |
3734 | * remaining state in i915_perf_fini(). | |
3735 | */ | |
8f8b1171 | 3736 | void i915_perf_unregister(struct drm_i915_private *i915) |
442b8c06 | 3737 | { |
8f8b1171 CW |
3738 | struct i915_perf *perf = &i915->perf; |
3739 | ||
3740 | if (!perf->metrics_kobj) | |
442b8c06 RB |
3741 | return; |
3742 | ||
8f8b1171 CW |
3743 | sysfs_remove_group(perf->metrics_kobj, |
3744 | &perf->test_config.sysfs_metric); | |
442b8c06 | 3745 | |
8f8b1171 CW |
3746 | kobject_put(perf->metrics_kobj); |
3747 | perf->metrics_kobj = NULL; | |
442b8c06 RB |
3748 | } |
3749 | ||
8f8b1171 | 3750 | static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr) |
f89823c2 LL |
3751 | { |
3752 | static const i915_reg_t flex_eu_regs[] = { | |
3753 | EU_PERF_CNTL0, | |
3754 | EU_PERF_CNTL1, | |
3755 | EU_PERF_CNTL2, | |
3756 | EU_PERF_CNTL3, | |
3757 | EU_PERF_CNTL4, | |
3758 | EU_PERF_CNTL5, | |
3759 | EU_PERF_CNTL6, | |
3760 | }; | |
3761 | int i; | |
3762 | ||
3763 | for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) { | |
7c52a221 | 3764 | if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr) |
f89823c2 LL |
3765 | return true; |
3766 | } | |
3767 | return false; | |
3768 | } | |
3769 | ||
fc215230 UNR |
3770 | #define ADDR_IN_RANGE(addr, start, end) \ |
3771 | ((addr) >= (start) && \ | |
3772 | (addr) <= (end)) | |
3773 | ||
3774 | #define REG_IN_RANGE(addr, start, end) \ | |
3775 | ((addr) >= i915_mmio_reg_offset(start) && \ | |
3776 | (addr) <= i915_mmio_reg_offset(end)) | |
3777 | ||
3778 | #define REG_EQUAL(addr, mmio) \ | |
3779 | ((addr) == i915_mmio_reg_offset(mmio)) | |
3780 | ||
8f8b1171 | 3781 | static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr) |
f89823c2 | 3782 | { |
fc215230 UNR |
3783 | return REG_IN_RANGE(addr, OASTARTTRIG1, OASTARTTRIG8) || |
3784 | REG_IN_RANGE(addr, OAREPORTTRIG1, OAREPORTTRIG8) || | |
3785 | REG_IN_RANGE(addr, OACEC0_0, OACEC7_1); | |
f89823c2 LL |
3786 | } |
3787 | ||
8f8b1171 | 3788 | static bool gen7_is_valid_mux_addr(struct i915_perf *perf, u32 addr) |
f89823c2 | 3789 | { |
fc215230 UNR |
3790 | return REG_EQUAL(addr, HALF_SLICE_CHICKEN2) || |
3791 | REG_IN_RANGE(addr, MICRO_BP0_0, NOA_WRITE) || | |
3792 | REG_IN_RANGE(addr, OA_PERFCNT1_LO, OA_PERFCNT2_HI) || | |
3793 | REG_IN_RANGE(addr, OA_PERFMATRIX_LO, OA_PERFMATRIX_HI); | |
f89823c2 LL |
3794 | } |
3795 | ||
8f8b1171 | 3796 | static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr) |
f89823c2 | 3797 | { |
8f8b1171 | 3798 | return gen7_is_valid_mux_addr(perf, addr) || |
fc215230 UNR |
3799 | REG_EQUAL(addr, WAIT_FOR_RC6_EXIT) || |
3800 | REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8)); | |
f89823c2 LL |
3801 | } |
3802 | ||
8f8b1171 | 3803 | static bool gen10_is_valid_mux_addr(struct i915_perf *perf, u32 addr) |
95690a02 | 3804 | { |
8f8b1171 | 3805 | return gen8_is_valid_mux_addr(perf, addr) || |
fc215230 UNR |
3806 | REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) || |
3807 | REG_IN_RANGE(addr, OA_PERFCNT3_LO, OA_PERFCNT4_HI); | |
95690a02 LL |
3808 | } |
3809 | ||
8f8b1171 | 3810 | static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr) |
f89823c2 | 3811 | { |
8f8b1171 | 3812 | return gen7_is_valid_mux_addr(perf, addr) || |
fc215230 UNR |
3813 | ADDR_IN_RANGE(addr, 0x25100, 0x2FF90) || |
3814 | REG_IN_RANGE(addr, HSW_MBVID2_NOA0, HSW_MBVID2_NOA9) || | |
3815 | REG_EQUAL(addr, HSW_MBVID2_MISR0); | |
f89823c2 LL |
3816 | } |
3817 | ||
8f8b1171 | 3818 | static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr) |
f89823c2 | 3819 | { |
8f8b1171 | 3820 | return gen7_is_valid_mux_addr(perf, addr) || |
fc215230 | 3821 | ADDR_IN_RANGE(addr, 0x182300, 0x1823A4); |
f89823c2 LL |
3822 | } |
3823 | ||
00a7f0d7 LL |
3824 | static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr) |
3825 | { | |
3826 | return REG_IN_RANGE(addr, GEN12_OAG_OASTARTTRIG1, GEN12_OAG_OASTARTTRIG8) || | |
3827 | REG_IN_RANGE(addr, GEN12_OAG_OAREPORTTRIG1, GEN12_OAG_OAREPORTTRIG8) || | |
3828 | REG_IN_RANGE(addr, GEN12_OAG_CEC0_0, GEN12_OAG_CEC7_1) || | |
3829 | REG_IN_RANGE(addr, GEN12_OAG_SCEC0_0, GEN12_OAG_SCEC7_1) || | |
3830 | REG_EQUAL(addr, GEN12_OAA_DBG_REG) || | |
3831 | REG_EQUAL(addr, GEN12_OAG_OA_PESS) || | |
3832 | REG_EQUAL(addr, GEN12_OAG_SPCTR_CNF); | |
3833 | } | |
3834 | ||
3835 | static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr) | |
3836 | { | |
3837 | return REG_EQUAL(addr, NOA_WRITE) || | |
3838 | REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) || | |
3839 | REG_EQUAL(addr, GDT_CHICKEN_BITS) || | |
3840 | REG_EQUAL(addr, WAIT_FOR_RC6_EXIT) || | |
3841 | REG_EQUAL(addr, RPM_CONFIG0) || | |
3842 | REG_EQUAL(addr, RPM_CONFIG1) || | |
3843 | REG_IN_RANGE(addr, NOA_CONFIG(0), NOA_CONFIG(8)); | |
3844 | } | |
3845 | ||
739f3abd | 3846 | static u32 mask_reg_value(u32 reg, u32 val) |
f89823c2 LL |
3847 | { |
3848 | /* HALF_SLICE_CHICKEN2 is programmed with a the | |
3849 | * WaDisableSTUnitPowerOptimization workaround. Make sure the value | |
3850 | * programmed by userspace doesn't change this. | |
3851 | */ | |
fc215230 | 3852 | if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2)) |
f89823c2 LL |
3853 | val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); |
3854 | ||
3855 | /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function | |
3856 | * indicated by its name and a bunch of selection fields used by OA | |
3857 | * configs. | |
3858 | */ | |
fc215230 | 3859 | if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT)) |
f89823c2 LL |
3860 | val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); |
3861 | ||
3862 | return val; | |
3863 | } | |
3864 | ||
8f8b1171 CW |
3865 | static struct i915_oa_reg *alloc_oa_regs(struct i915_perf *perf, |
3866 | bool (*is_valid)(struct i915_perf *perf, u32 addr), | |
f89823c2 LL |
3867 | u32 __user *regs, |
3868 | u32 n_regs) | |
3869 | { | |
3870 | struct i915_oa_reg *oa_regs; | |
3871 | int err; | |
3872 | u32 i; | |
3873 | ||
3874 | if (!n_regs) | |
3875 | return NULL; | |
3876 | ||
96d4f267 | 3877 | if (!access_ok(regs, n_regs * sizeof(u32) * 2)) |
f89823c2 LL |
3878 | return ERR_PTR(-EFAULT); |
3879 | ||
3880 | /* No is_valid function means we're not allowing any register to be programmed. */ | |
3881 | GEM_BUG_ON(!is_valid); | |
3882 | if (!is_valid) | |
3883 | return ERR_PTR(-EINVAL); | |
3884 | ||
3885 | oa_regs = kmalloc_array(n_regs, sizeof(*oa_regs), GFP_KERNEL); | |
3886 | if (!oa_regs) | |
3887 | return ERR_PTR(-ENOMEM); | |
3888 | ||
3889 | for (i = 0; i < n_regs; i++) { | |
3890 | u32 addr, value; | |
3891 | ||
3892 | err = get_user(addr, regs); | |
3893 | if (err) | |
3894 | goto addr_err; | |
3895 | ||
8f8b1171 | 3896 | if (!is_valid(perf, addr)) { |
f89823c2 LL |
3897 | DRM_DEBUG("Invalid oa_reg address: %X\n", addr); |
3898 | err = -EINVAL; | |
3899 | goto addr_err; | |
3900 | } | |
3901 | ||
3902 | err = get_user(value, regs + 1); | |
3903 | if (err) | |
3904 | goto addr_err; | |
3905 | ||
3906 | oa_regs[i].addr = _MMIO(addr); | |
3907 | oa_regs[i].value = mask_reg_value(addr, value); | |
3908 | ||
3909 | regs += 2; | |
3910 | } | |
3911 | ||
3912 | return oa_regs; | |
3913 | ||
3914 | addr_err: | |
3915 | kfree(oa_regs); | |
3916 | return ERR_PTR(err); | |
3917 | } | |
3918 | ||
3919 | static ssize_t show_dynamic_id(struct device *dev, | |
3920 | struct device_attribute *attr, | |
3921 | char *buf) | |
3922 | { | |
3923 | struct i915_oa_config *oa_config = | |
3924 | container_of(attr, typeof(*oa_config), sysfs_metric_id); | |
3925 | ||
3926 | return sprintf(buf, "%d\n", oa_config->id); | |
3927 | } | |
3928 | ||
8f8b1171 | 3929 | static int create_dynamic_oa_sysfs_entry(struct i915_perf *perf, |
f89823c2 LL |
3930 | struct i915_oa_config *oa_config) |
3931 | { | |
28152a23 | 3932 | sysfs_attr_init(&oa_config->sysfs_metric_id.attr); |
f89823c2 LL |
3933 | oa_config->sysfs_metric_id.attr.name = "id"; |
3934 | oa_config->sysfs_metric_id.attr.mode = S_IRUGO; | |
3935 | oa_config->sysfs_metric_id.show = show_dynamic_id; | |
3936 | oa_config->sysfs_metric_id.store = NULL; | |
3937 | ||
3938 | oa_config->attrs[0] = &oa_config->sysfs_metric_id.attr; | |
3939 | oa_config->attrs[1] = NULL; | |
3940 | ||
3941 | oa_config->sysfs_metric.name = oa_config->uuid; | |
3942 | oa_config->sysfs_metric.attrs = oa_config->attrs; | |
3943 | ||
8f8b1171 | 3944 | return sysfs_create_group(perf->metrics_kobj, |
f89823c2 LL |
3945 | &oa_config->sysfs_metric); |
3946 | } | |
3947 | ||
3948 | /** | |
3949 | * i915_perf_add_config_ioctl - DRM ioctl() for userspace to add a new OA config | |
3950 | * @dev: drm device | |
3951 | * @data: ioctl data (pointer to struct drm_i915_perf_oa_config) copied from | |
3952 | * userspace (unvalidated) | |
3953 | * @file: drm file | |
3954 | * | |
3955 | * Validates the submitted OA register to be saved into a new OA config that | |
3956 | * can then be used for programming the OA unit and its NOA network. | |
3957 | * | |
3958 | * Returns: A new allocated config number to be used with the perf open ioctl | |
3959 | * or a negative error code on failure. | |
3960 | */ | |
3961 | int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, | |
3962 | struct drm_file *file) | |
3963 | { | |
8f8b1171 | 3964 | struct i915_perf *perf = &to_i915(dev)->perf; |
f89823c2 LL |
3965 | struct drm_i915_perf_oa_config *args = data; |
3966 | struct i915_oa_config *oa_config, *tmp; | |
c2fba936 | 3967 | static struct i915_oa_reg *regs; |
f89823c2 LL |
3968 | int err, id; |
3969 | ||
8f8b1171 | 3970 | if (!perf->i915) { |
f89823c2 LL |
3971 | DRM_DEBUG("i915 perf interface not available for this system\n"); |
3972 | return -ENOTSUPP; | |
3973 | } | |
3974 | ||
8f8b1171 | 3975 | if (!perf->metrics_kobj) { |
f89823c2 LL |
3976 | DRM_DEBUG("OA metrics weren't advertised via sysfs\n"); |
3977 | return -EINVAL; | |
3978 | } | |
3979 | ||
3980 | if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) { | |
3981 | DRM_DEBUG("Insufficient privileges to add i915 OA config\n"); | |
3982 | return -EACCES; | |
3983 | } | |
3984 | ||
3985 | if ((!args->mux_regs_ptr || !args->n_mux_regs) && | |
3986 | (!args->boolean_regs_ptr || !args->n_boolean_regs) && | |
3987 | (!args->flex_regs_ptr || !args->n_flex_regs)) { | |
3988 | DRM_DEBUG("No OA registers given\n"); | |
3989 | return -EINVAL; | |
3990 | } | |
3991 | ||
3992 | oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL); | |
3993 | if (!oa_config) { | |
3994 | DRM_DEBUG("Failed to allocate memory for the OA config\n"); | |
3995 | return -ENOMEM; | |
3996 | } | |
3997 | ||
6a45008a LL |
3998 | oa_config->perf = perf; |
3999 | kref_init(&oa_config->ref); | |
f89823c2 LL |
4000 | |
4001 | if (!uuid_is_valid(args->uuid)) { | |
4002 | DRM_DEBUG("Invalid uuid format for OA config\n"); | |
4003 | err = -EINVAL; | |
4004 | goto reg_err; | |
4005 | } | |
4006 | ||
4007 | /* Last character in oa_config->uuid will be 0 because oa_config is | |
4008 | * kzalloc. | |
4009 | */ | |
4010 | memcpy(oa_config->uuid, args->uuid, sizeof(args->uuid)); | |
4011 | ||
4012 | oa_config->mux_regs_len = args->n_mux_regs; | |
c2fba936 CW |
4013 | regs = alloc_oa_regs(perf, |
4014 | perf->ops.is_valid_mux_reg, | |
4015 | u64_to_user_ptr(args->mux_regs_ptr), | |
4016 | args->n_mux_regs); | |
f89823c2 | 4017 | |
c2fba936 | 4018 | if (IS_ERR(regs)) { |
f89823c2 | 4019 | DRM_DEBUG("Failed to create OA config for mux_regs\n"); |
c2fba936 | 4020 | err = PTR_ERR(regs); |
f89823c2 LL |
4021 | goto reg_err; |
4022 | } | |
c2fba936 | 4023 | oa_config->mux_regs = regs; |
f89823c2 LL |
4024 | |
4025 | oa_config->b_counter_regs_len = args->n_boolean_regs; | |
c2fba936 CW |
4026 | regs = alloc_oa_regs(perf, |
4027 | perf->ops.is_valid_b_counter_reg, | |
4028 | u64_to_user_ptr(args->boolean_regs_ptr), | |
4029 | args->n_boolean_regs); | |
f89823c2 | 4030 | |
c2fba936 | 4031 | if (IS_ERR(regs)) { |
f89823c2 | 4032 | DRM_DEBUG("Failed to create OA config for b_counter_regs\n"); |
c2fba936 | 4033 | err = PTR_ERR(regs); |
f89823c2 LL |
4034 | goto reg_err; |
4035 | } | |
c2fba936 | 4036 | oa_config->b_counter_regs = regs; |
f89823c2 | 4037 | |
8f8b1171 | 4038 | if (INTEL_GEN(perf->i915) < 8) { |
f89823c2 LL |
4039 | if (args->n_flex_regs != 0) { |
4040 | err = -EINVAL; | |
4041 | goto reg_err; | |
4042 | } | |
4043 | } else { | |
4044 | oa_config->flex_regs_len = args->n_flex_regs; | |
c2fba936 CW |
4045 | regs = alloc_oa_regs(perf, |
4046 | perf->ops.is_valid_flex_reg, | |
4047 | u64_to_user_ptr(args->flex_regs_ptr), | |
4048 | args->n_flex_regs); | |
f89823c2 | 4049 | |
c2fba936 | 4050 | if (IS_ERR(regs)) { |
f89823c2 | 4051 | DRM_DEBUG("Failed to create OA config for flex_regs\n"); |
c2fba936 | 4052 | err = PTR_ERR(regs); |
f89823c2 LL |
4053 | goto reg_err; |
4054 | } | |
c2fba936 | 4055 | oa_config->flex_regs = regs; |
f89823c2 LL |
4056 | } |
4057 | ||
8f8b1171 | 4058 | err = mutex_lock_interruptible(&perf->metrics_lock); |
f89823c2 LL |
4059 | if (err) |
4060 | goto reg_err; | |
4061 | ||
4062 | /* We shouldn't have too many configs, so this iteration shouldn't be | |
4063 | * too costly. | |
4064 | */ | |
8f8b1171 | 4065 | idr_for_each_entry(&perf->metrics_idr, tmp, id) { |
f89823c2 LL |
4066 | if (!strcmp(tmp->uuid, oa_config->uuid)) { |
4067 | DRM_DEBUG("OA config already exists with this uuid\n"); | |
4068 | err = -EADDRINUSE; | |
4069 | goto sysfs_err; | |
4070 | } | |
4071 | } | |
4072 | ||
8f8b1171 | 4073 | err = create_dynamic_oa_sysfs_entry(perf, oa_config); |
f89823c2 LL |
4074 | if (err) { |
4075 | DRM_DEBUG("Failed to create sysfs entry for OA config\n"); | |
4076 | goto sysfs_err; | |
4077 | } | |
4078 | ||
4079 | /* Config id 0 is invalid, id 1 for kernel stored test config. */ | |
8f8b1171 | 4080 | oa_config->id = idr_alloc(&perf->metrics_idr, |
f89823c2 LL |
4081 | oa_config, 2, |
4082 | 0, GFP_KERNEL); | |
4083 | if (oa_config->id < 0) { | |
4084 | DRM_DEBUG("Failed to create sysfs entry for OA config\n"); | |
4085 | err = oa_config->id; | |
4086 | goto sysfs_err; | |
4087 | } | |
4088 | ||
8f8b1171 | 4089 | mutex_unlock(&perf->metrics_lock); |
f89823c2 | 4090 | |
9bd9be66 LL |
4091 | DRM_DEBUG("Added config %s id=%i\n", oa_config->uuid, oa_config->id); |
4092 | ||
f89823c2 LL |
4093 | return oa_config->id; |
4094 | ||
4095 | sysfs_err: | |
8f8b1171 | 4096 | mutex_unlock(&perf->metrics_lock); |
f89823c2 | 4097 | reg_err: |
6a45008a | 4098 | i915_oa_config_put(oa_config); |
f89823c2 LL |
4099 | DRM_DEBUG("Failed to add new OA config\n"); |
4100 | return err; | |
4101 | } | |
4102 | ||
4103 | /** | |
4104 | * i915_perf_remove_config_ioctl - DRM ioctl() for userspace to remove an OA config | |
4105 | * @dev: drm device | |
4106 | * @data: ioctl data (pointer to u64 integer) copied from userspace | |
4107 | * @file: drm file | |
4108 | * | |
4109 | * Configs can be removed while being used, the will stop appearing in sysfs | |
4110 | * and their content will be freed when the stream using the config is closed. | |
4111 | * | |
4112 | * Returns: 0 on success or a negative error code on failure. | |
4113 | */ | |
4114 | int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, | |
4115 | struct drm_file *file) | |
4116 | { | |
8f8b1171 | 4117 | struct i915_perf *perf = &to_i915(dev)->perf; |
f89823c2 LL |
4118 | u64 *arg = data; |
4119 | struct i915_oa_config *oa_config; | |
4120 | int ret; | |
4121 | ||
8f8b1171 | 4122 | if (!perf->i915) { |
f89823c2 LL |
4123 | DRM_DEBUG("i915 perf interface not available for this system\n"); |
4124 | return -ENOTSUPP; | |
4125 | } | |
4126 | ||
4127 | if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) { | |
4128 | DRM_DEBUG("Insufficient privileges to remove i915 OA config\n"); | |
4129 | return -EACCES; | |
4130 | } | |
4131 | ||
8f8b1171 | 4132 | ret = mutex_lock_interruptible(&perf->metrics_lock); |
f89823c2 | 4133 | if (ret) |
6a45008a | 4134 | return ret; |
f89823c2 | 4135 | |
8f8b1171 | 4136 | oa_config = idr_find(&perf->metrics_idr, *arg); |
f89823c2 LL |
4137 | if (!oa_config) { |
4138 | DRM_DEBUG("Failed to remove unknown OA config\n"); | |
4139 | ret = -ENOENT; | |
6a45008a | 4140 | goto err_unlock; |
f89823c2 LL |
4141 | } |
4142 | ||
4143 | GEM_BUG_ON(*arg != oa_config->id); | |
4144 | ||
4f6ccc74 | 4145 | sysfs_remove_group(perf->metrics_kobj, &oa_config->sysfs_metric); |
f89823c2 | 4146 | |
8f8b1171 | 4147 | idr_remove(&perf->metrics_idr, *arg); |
9bd9be66 | 4148 | |
6a45008a LL |
4149 | mutex_unlock(&perf->metrics_lock); |
4150 | ||
9bd9be66 LL |
4151 | DRM_DEBUG("Removed config %s id=%i\n", oa_config->uuid, oa_config->id); |
4152 | ||
6a45008a LL |
4153 | i915_oa_config_put(oa_config); |
4154 | ||
4155 | return 0; | |
f89823c2 | 4156 | |
6a45008a | 4157 | err_unlock: |
8f8b1171 | 4158 | mutex_unlock(&perf->metrics_lock); |
f89823c2 LL |
4159 | return ret; |
4160 | } | |
4161 | ||
ccdf6341 RB |
4162 | static struct ctl_table oa_table[] = { |
4163 | { | |
4164 | .procname = "perf_stream_paranoid", | |
4165 | .data = &i915_perf_stream_paranoid, | |
4166 | .maxlen = sizeof(i915_perf_stream_paranoid), | |
4167 | .mode = 0644, | |
4168 | .proc_handler = proc_dointvec_minmax, | |
eec4844f MC |
4169 | .extra1 = SYSCTL_ZERO, |
4170 | .extra2 = SYSCTL_ONE, | |
ccdf6341 | 4171 | }, |
00319ba0 RB |
4172 | { |
4173 | .procname = "oa_max_sample_rate", | |
4174 | .data = &i915_oa_max_sample_rate, | |
4175 | .maxlen = sizeof(i915_oa_max_sample_rate), | |
4176 | .mode = 0644, | |
4177 | .proc_handler = proc_dointvec_minmax, | |
eec4844f | 4178 | .extra1 = SYSCTL_ZERO, |
00319ba0 RB |
4179 | .extra2 = &oa_sample_rate_hard_limit, |
4180 | }, | |
ccdf6341 RB |
4181 | {} |
4182 | }; | |
4183 | ||
4184 | static struct ctl_table i915_root[] = { | |
4185 | { | |
4186 | .procname = "i915", | |
4187 | .maxlen = 0, | |
4188 | .mode = 0555, | |
4189 | .child = oa_table, | |
4190 | }, | |
4191 | {} | |
4192 | }; | |
4193 | ||
4194 | static struct ctl_table dev_root[] = { | |
4195 | { | |
4196 | .procname = "dev", | |
4197 | .maxlen = 0, | |
4198 | .mode = 0555, | |
4199 | .child = i915_root, | |
4200 | }, | |
4201 | {} | |
4202 | }; | |
4203 | ||
16d98b31 RB |
4204 | /** |
4205 | * i915_perf_init - initialize i915-perf state on module load | |
8f8b1171 | 4206 | * @i915: i915 device instance |
16d98b31 RB |
4207 | * |
4208 | * Initializes i915-perf state without exposing anything to userspace. | |
4209 | * | |
4210 | * Note: i915-perf initialization is split into an 'init' and 'register' | |
4211 | * phase with the i915_perf_register() exposing state to userspace. | |
4212 | */ | |
8f8b1171 CW |
4213 | void i915_perf_init(struct drm_i915_private *i915) |
4214 | { | |
4215 | struct i915_perf *perf = &i915->perf; | |
4216 | ||
4217 | /* XXX const struct i915_perf_ops! */ | |
4218 | ||
4219 | if (IS_HASWELL(i915)) { | |
4220 | perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr; | |
4221 | perf->ops.is_valid_mux_reg = hsw_is_valid_mux_addr; | |
4222 | perf->ops.is_valid_flex_reg = NULL; | |
4223 | perf->ops.enable_metric_set = hsw_enable_metric_set; | |
4224 | perf->ops.disable_metric_set = hsw_disable_metric_set; | |
4225 | perf->ops.oa_enable = gen7_oa_enable; | |
4226 | perf->ops.oa_disable = gen7_oa_disable; | |
4227 | perf->ops.read = gen7_oa_read; | |
4228 | perf->ops.oa_hw_tail_read = gen7_oa_hw_tail_read; | |
4229 | ||
4230 | perf->oa_formats = hsw_oa_formats; | |
4231 | } else if (HAS_LOGICAL_RING_CONTEXTS(i915)) { | |
19f81df2 RB |
4232 | /* Note: that although we could theoretically also support the |
4233 | * legacy ringbuffer mode on BDW (and earlier iterations of | |
4234 | * this driver, before upstreaming did this) it didn't seem | |
4235 | * worth the complexity to maintain now that BDW+ enable | |
4236 | * execlist mode by default. | |
4237 | */ | |
8f8b1171 | 4238 | perf->ops.read = gen8_oa_read; |
701f8231 | 4239 | |
8f8b1171 | 4240 | if (IS_GEN_RANGE(i915, 8, 9)) { |
00a7f0d7 LL |
4241 | perf->oa_formats = gen8_plus_oa_formats; |
4242 | ||
8f8b1171 | 4243 | perf->ops.is_valid_b_counter_reg = |
ba6b7c1a | 4244 | gen7_is_valid_b_counter_addr; |
8f8b1171 | 4245 | perf->ops.is_valid_mux_reg = |
ba6b7c1a | 4246 | gen8_is_valid_mux_addr; |
8f8b1171 | 4247 | perf->ops.is_valid_flex_reg = |
ba6b7c1a | 4248 | gen8_is_valid_flex_addr; |
155e941f | 4249 | |
8f8b1171 CW |
4250 | if (IS_CHERRYVIEW(i915)) { |
4251 | perf->ops.is_valid_mux_reg = | |
f89823c2 LL |
4252 | chv_is_valid_mux_addr; |
4253 | } | |
155e941f | 4254 | |
00a7f0d7 LL |
4255 | perf->ops.oa_enable = gen8_oa_enable; |
4256 | perf->ops.oa_disable = gen8_oa_disable; | |
8f8b1171 CW |
4257 | perf->ops.enable_metric_set = gen8_enable_metric_set; |
4258 | perf->ops.disable_metric_set = gen8_disable_metric_set; | |
00a7f0d7 | 4259 | perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read; |
ba6b7c1a | 4260 | |
8f8b1171 CW |
4261 | if (IS_GEN(i915, 8)) { |
4262 | perf->ctx_oactxctrl_offset = 0x120; | |
4263 | perf->ctx_flexeu0_offset = 0x2ce; | |
ba6b7c1a | 4264 | |
8f8b1171 | 4265 | perf->gen8_valid_ctx_bit = BIT(25); |
ba6b7c1a | 4266 | } else { |
8f8b1171 CW |
4267 | perf->ctx_oactxctrl_offset = 0x128; |
4268 | perf->ctx_flexeu0_offset = 0x3de; | |
ba6b7c1a | 4269 | |
8f8b1171 | 4270 | perf->gen8_valid_ctx_bit = BIT(16); |
ba6b7c1a | 4271 | } |
8f8b1171 | 4272 | } else if (IS_GEN_RANGE(i915, 10, 11)) { |
00a7f0d7 LL |
4273 | perf->oa_formats = gen8_plus_oa_formats; |
4274 | ||
8f8b1171 | 4275 | perf->ops.is_valid_b_counter_reg = |
95690a02 | 4276 | gen7_is_valid_b_counter_addr; |
8f8b1171 | 4277 | perf->ops.is_valid_mux_reg = |
95690a02 | 4278 | gen10_is_valid_mux_addr; |
8f8b1171 | 4279 | perf->ops.is_valid_flex_reg = |
95690a02 LL |
4280 | gen8_is_valid_flex_addr; |
4281 | ||
00a7f0d7 LL |
4282 | perf->ops.oa_enable = gen8_oa_enable; |
4283 | perf->ops.oa_disable = gen8_oa_disable; | |
8f8b1171 CW |
4284 | perf->ops.enable_metric_set = gen8_enable_metric_set; |
4285 | perf->ops.disable_metric_set = gen10_disable_metric_set; | |
00a7f0d7 | 4286 | perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read; |
95690a02 | 4287 | |
8f8b1171 CW |
4288 | if (IS_GEN(i915, 10)) { |
4289 | perf->ctx_oactxctrl_offset = 0x128; | |
4290 | perf->ctx_flexeu0_offset = 0x3de; | |
8dcfdfb4 | 4291 | } else { |
8f8b1171 CW |
4292 | perf->ctx_oactxctrl_offset = 0x124; |
4293 | perf->ctx_flexeu0_offset = 0x78e; | |
8dcfdfb4 | 4294 | } |
8f8b1171 | 4295 | perf->gen8_valid_ctx_bit = BIT(16); |
00a7f0d7 LL |
4296 | } else if (IS_GEN(i915, 12)) { |
4297 | perf->oa_formats = gen12_oa_formats; | |
4298 | ||
4299 | perf->ops.is_valid_b_counter_reg = | |
4300 | gen12_is_valid_b_counter_addr; | |
4301 | perf->ops.is_valid_mux_reg = | |
4302 | gen12_is_valid_mux_addr; | |
4303 | perf->ops.is_valid_flex_reg = | |
4304 | gen8_is_valid_flex_addr; | |
4305 | ||
4306 | perf->ops.oa_enable = gen12_oa_enable; | |
4307 | perf->ops.oa_disable = gen12_oa_disable; | |
4308 | perf->ops.enable_metric_set = gen12_enable_metric_set; | |
4309 | perf->ops.disable_metric_set = gen12_disable_metric_set; | |
4310 | perf->ops.oa_hw_tail_read = gen12_oa_hw_tail_read; | |
4311 | ||
4312 | perf->ctx_flexeu0_offset = 0; | |
4313 | perf->ctx_oactxctrl_offset = 0x144; | |
19f81df2 | 4314 | } |
19f81df2 | 4315 | } |
d7965152 | 4316 | |
8f8b1171 | 4317 | if (perf->ops.enable_metric_set) { |
8f8b1171 | 4318 | mutex_init(&perf->lock); |
eec688e1 | 4319 | |
9f9b2792 | 4320 | oa_sample_rate_hard_limit = 1000 * |
8f8b1171 CW |
4321 | (RUNTIME_INFO(i915)->cs_timestamp_frequency_khz / 2); |
4322 | perf->sysctl_header = register_sysctl_table(dev_root); | |
ccdf6341 | 4323 | |
8f8b1171 CW |
4324 | mutex_init(&perf->metrics_lock); |
4325 | idr_init(&perf->metrics_idr); | |
f89823c2 | 4326 | |
a37f08a8 UNR |
4327 | /* We set up some ratelimit state to potentially throttle any |
4328 | * _NOTES about spurious, invalid OA reports which we don't | |
4329 | * forward to userspace. | |
4330 | * | |
4331 | * We print a _NOTE about any throttling when closing the | |
4332 | * stream instead of waiting until driver _fini which no one | |
4333 | * would ever see. | |
4334 | * | |
4335 | * Using the same limiting factors as printk_ratelimit() | |
4336 | */ | |
8f8b1171 | 4337 | ratelimit_state_init(&perf->spurious_report_rs, 5 * HZ, 10); |
a37f08a8 UNR |
4338 | /* Since we use a DRM_NOTE for spurious reports it would be |
4339 | * inconsistent to let __ratelimit() automatically print a | |
4340 | * warning for throttling. | |
4341 | */ | |
8f8b1171 | 4342 | ratelimit_set_flags(&perf->spurious_report_rs, |
a37f08a8 UNR |
4343 | RATELIMIT_MSG_ON_RELEASE); |
4344 | ||
daed3e44 LL |
4345 | atomic64_set(&perf->noa_programming_delay, |
4346 | 500 * 1000 /* 500us */); | |
4347 | ||
8f8b1171 | 4348 | perf->i915 = i915; |
19f81df2 | 4349 | } |
eec688e1 RB |
4350 | } |
4351 | ||
f89823c2 LL |
4352 | static int destroy_config(int id, void *p, void *data) |
4353 | { | |
6a45008a | 4354 | i915_oa_config_put(p); |
f89823c2 LL |
4355 | return 0; |
4356 | } | |
4357 | ||
16d98b31 RB |
4358 | /** |
4359 | * i915_perf_fini - Counter part to i915_perf_init() | |
8f8b1171 | 4360 | * @i915: i915 device instance |
16d98b31 | 4361 | */ |
8f8b1171 | 4362 | void i915_perf_fini(struct drm_i915_private *i915) |
eec688e1 | 4363 | { |
8f8b1171 | 4364 | struct i915_perf *perf = &i915->perf; |
eec688e1 | 4365 | |
8f8b1171 CW |
4366 | if (!perf->i915) |
4367 | return; | |
f89823c2 | 4368 | |
8f8b1171 CW |
4369 | idr_for_each(&perf->metrics_idr, destroy_config, perf); |
4370 | idr_destroy(&perf->metrics_idr); | |
ccdf6341 | 4371 | |
8f8b1171 | 4372 | unregister_sysctl_table(perf->sysctl_header); |
19f81df2 | 4373 | |
8f8b1171 CW |
4374 | memset(&perf->ops, 0, sizeof(perf->ops)); |
4375 | perf->i915 = NULL; | |
eec688e1 | 4376 | } |
daed3e44 | 4377 | |
b8d49f28 LL |
4378 | /** |
4379 | * i915_perf_ioctl_version - Version of the i915-perf subsystem | |
4380 | * | |
4381 | * This version number is used by userspace to detect available features. | |
4382 | */ | |
4383 | int i915_perf_ioctl_version(void) | |
4384 | { | |
7831e9a9 CW |
4385 | /* |
4386 | * 1: Initial version | |
4387 | * I915_PERF_IOCTL_ENABLE | |
4388 | * I915_PERF_IOCTL_DISABLE | |
4389 | * | |
4390 | * 2: Added runtime modification of OA config. | |
4391 | * I915_PERF_IOCTL_CONFIG | |
9cd20ef7 LL |
4392 | * |
4393 | * 3: Add DRM_I915_PERF_PROP_HOLD_PREEMPTION parameter to hold | |
4394 | * preemption on a particular context so that performance data is | |
4395 | * accessible from a delta of MI_RPC reports without looking at the | |
4396 | * OA buffer. | |
7831e9a9 | 4397 | */ |
9cd20ef7 | 4398 | return 3; |
b8d49f28 LL |
4399 | } |
4400 | ||
daed3e44 LL |
4401 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
4402 | #include "selftests/i915_perf.c" | |
4403 | #endif |