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42f5551d CW |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
01b94a93 | 25 | #include <drm/drm_color_mgmt.h> |
fcd70cd3 | 26 | #include <drm/drm_drv.h> |
83d2bdb6 | 27 | #include <drm/i915_pciids.h> |
fcd70cd3 | 28 | |
f0e2f00c MR |
29 | #include "gt/intel_gt_regs.h" |
30 | #include "gt/intel_sa_media.h" | |
31 | ||
58471f63 | 32 | #include "i915_driver.h" |
42f5551d | 33 | #include "i915_drv.h" |
708b7df3 | 34 | #include "i915_pci.h" |
ce2fce25 | 35 | #include "i915_reg.h" |
1bba7323 | 36 | #include "intel_pci_config.h" |
42f5551d | 37 | |
805446c8 | 38 | #define PLATFORM(x) .platform = (x) |
93babb06 | 39 | #define GEN(x) \ |
f9e932a8 RS |
40 | .__runtime.graphics.ip.ver = (x), \ |
41 | .__runtime.media.ip.ver = (x), \ | |
42 | .__runtime.display.ip.ver = (x) | |
bc76298e | 43 | |
47c3d075 JN |
44 | #define NO_DISPLAY .__runtime.pipe_mask = 0 |
45 | ||
37fbbd49 | 46 | #define I845_PIPE_OFFSETS \ |
12d74553 | 47 | .display.pipe_offsets = { \ |
37fbbd49 VS |
48 | [TRANSCODER_A] = PIPE_A_OFFSET, \ |
49 | }, \ | |
12d74553 | 50 | .display.trans_offsets = { \ |
37fbbd49 VS |
51 | [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ |
52 | } | |
53 | ||
54 | #define I9XX_PIPE_OFFSETS \ | |
12d74553 | 55 | .display.pipe_offsets = { \ |
37fbbd49 VS |
56 | [TRANSCODER_A] = PIPE_A_OFFSET, \ |
57 | [TRANSCODER_B] = PIPE_B_OFFSET, \ | |
58 | }, \ | |
12d74553 | 59 | .display.trans_offsets = { \ |
37fbbd49 VS |
60 | [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ |
61 | [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ | |
62 | } | |
63 | ||
64 | #define IVB_PIPE_OFFSETS \ | |
12d74553 | 65 | .display.pipe_offsets = { \ |
37fbbd49 VS |
66 | [TRANSCODER_A] = PIPE_A_OFFSET, \ |
67 | [TRANSCODER_B] = PIPE_B_OFFSET, \ | |
68 | [TRANSCODER_C] = PIPE_C_OFFSET, \ | |
69 | }, \ | |
12d74553 | 70 | .display.trans_offsets = { \ |
37fbbd49 VS |
71 | [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ |
72 | [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ | |
73 | [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ | |
74 | } | |
75 | ||
76 | #define HSW_PIPE_OFFSETS \ | |
12d74553 | 77 | .display.pipe_offsets = { \ |
931f5492 ID |
78 | [TRANSCODER_A] = PIPE_A_OFFSET, \ |
79 | [TRANSCODER_B] = PIPE_B_OFFSET, \ | |
80 | [TRANSCODER_C] = PIPE_C_OFFSET, \ | |
81 | [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ | |
82 | }, \ | |
12d74553 | 83 | .display.trans_offsets = { \ |
931f5492 ID |
84 | [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ |
85 | [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ | |
86 | [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ | |
87 | [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ | |
88 | } | |
42f5551d | 89 | |
37fbbd49 | 90 | #define CHV_PIPE_OFFSETS \ |
12d74553 | 91 | .display.pipe_offsets = { \ |
931f5492 ID |
92 | [TRANSCODER_A] = PIPE_A_OFFSET, \ |
93 | [TRANSCODER_B] = PIPE_B_OFFSET, \ | |
94 | [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ | |
95 | }, \ | |
12d74553 | 96 | .display.trans_offsets = { \ |
931f5492 ID |
97 | [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ |
98 | [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ | |
99 | [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ | |
100 | } | |
42f5551d | 101 | |
37fbbd49 | 102 | #define I845_CURSOR_OFFSETS \ |
12d74553 | 103 | .display.cursor_offsets = { \ |
37fbbd49 VS |
104 | [PIPE_A] = CURSOR_A_OFFSET, \ |
105 | } | |
106 | ||
107 | #define I9XX_CURSOR_OFFSETS \ | |
12d74553 | 108 | .display.cursor_offsets = { \ |
37fbbd49 VS |
109 | [PIPE_A] = CURSOR_A_OFFSET, \ |
110 | [PIPE_B] = CURSOR_B_OFFSET, \ | |
111 | } | |
112 | ||
113 | #define CHV_CURSOR_OFFSETS \ | |
12d74553 | 114 | .display.cursor_offsets = { \ |
37fbbd49 VS |
115 | [PIPE_A] = CURSOR_A_OFFSET, \ |
116 | [PIPE_B] = CURSOR_B_OFFSET, \ | |
117 | [PIPE_C] = CHV_CURSOR_C_OFFSET, \ | |
118 | } | |
42f5551d CW |
119 | |
120 | #define IVB_CURSOR_OFFSETS \ | |
12d74553 | 121 | .display.cursor_offsets = { \ |
37fbbd49 VS |
122 | [PIPE_A] = CURSOR_A_OFFSET, \ |
123 | [PIPE_B] = IVB_CURSOR_B_OFFSET, \ | |
124 | [PIPE_C] = IVB_CURSOR_C_OFFSET, \ | |
125 | } | |
42f5551d | 126 | |
6ea3cee6 | 127 | #define TGL_CURSOR_OFFSETS \ |
12d74553 | 128 | .display.cursor_offsets = { \ |
6ea3cee6 AN |
129 | [PIPE_A] = CURSOR_A_OFFSET, \ |
130 | [PIPE_B] = IVB_CURSOR_B_OFFSET, \ | |
131 | [PIPE_C] = IVB_CURSOR_C_OFFSET, \ | |
132 | [PIPE_D] = TGL_CURSOR_D_OFFSET, \ | |
133 | } | |
134 | ||
82106247 | 135 | #define I9XX_COLORS \ |
f7fb92cd | 136 | .display.color = { .gamma_lut_size = 256 } |
e262568e | 137 | #define I965_COLORS \ |
f7fb92cd | 138 | .display.color = { .gamma_lut_size = 129, \ |
e262568e VS |
139 | .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ |
140 | } | |
514462ca | 141 | #define ILK_COLORS \ |
f7fb92cd | 142 | .display.color = { .gamma_lut_size = 1024 } |
c21ce2ef | 143 | #define IVB_COLORS \ |
f7fb92cd | 144 | .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } |
42f5551d | 145 | #define CHV_COLORS \ |
f7fb92cd VS |
146 | .display.color = { \ |
147 | .degamma_lut_size = 65, .gamma_lut_size = 257, \ | |
148 | .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ | |
149 | .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ | |
e4c0d531 | 150 | } |
4672770d | 151 | #define GLK_COLORS \ |
f7fb92cd VS |
152 | .display.color = { \ |
153 | .degamma_lut_size = 33, .gamma_lut_size = 1024, \ | |
154 | .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ | |
155 | DRM_COLOR_LUT_EQUAL_CHANNELS, \ | |
e4c0d531 | 156 | } |
a37795cb | 157 | #define ICL_COLORS \ |
f7fb92cd VS |
158 | .display.color = { \ |
159 | .degamma_lut_size = 33, .gamma_lut_size = 262145, \ | |
160 | .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ | |
161 | DRM_COLOR_LUT_EQUAL_CHANNELS, \ | |
162 | .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ | |
a37795cb | 163 | } |
42f5551d | 164 | |
a5ce929b | 165 | /* Keep in gen based order, and chronological order within a gen */ |
2a9654b2 MA |
166 | |
167 | #define GEN_DEFAULT_PAGE_SIZES \ | |
9d0bad17 | 168 | .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K |
2a9654b2 | 169 | |
da1184cd | 170 | #define GEN_DEFAULT_REGIONS \ |
f81f30b3 | 171 | .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM |
da1184cd | 172 | |
37fbbd49 VS |
173 | #define I830_FEATURES \ |
174 | GEN(2), \ | |
175 | .is_mobile = 1, \ | |
00c6cbfd JN |
176 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ |
177 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ | |
37fbbd49 VS |
178 | .display.has_overlay = 1, \ |
179 | .display.cursor_needs_physical = 1, \ | |
180 | .display.overlay_needs_physical = 1, \ | |
181 | .display.has_gmch = 1, \ | |
182 | .gpu_reset_clobbers_display = true, \ | |
1eb31338 | 183 | .has_3d_pipeline = 1, \ |
37fbbd49 VS |
184 | .hws_needs_physical = 1, \ |
185 | .unfenced_needs_alignment = 1, \ | |
488e29fe | 186 | .__runtime.platform_engine_mask = BIT(RCS0), \ |
37fbbd49 VS |
187 | .has_snoop = true, \ |
188 | .has_coherent_ggtt = false, \ | |
31a02eb7 | 189 | .dma_mask_size = 32, \ |
37fbbd49 VS |
190 | I9XX_PIPE_OFFSETS, \ |
191 | I9XX_CURSOR_OFFSETS, \ | |
82106247 | 192 | I9XX_COLORS, \ |
da1184cd MA |
193 | GEN_DEFAULT_PAGE_SIZES, \ |
194 | GEN_DEFAULT_REGIONS | |
37fbbd49 VS |
195 | |
196 | #define I845_FEATURES \ | |
bc76298e | 197 | GEN(2), \ |
00c6cbfd JN |
198 | .__runtime.pipe_mask = BIT(PIPE_A), \ |
199 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \ | |
d53db442 JRS |
200 | .display.has_overlay = 1, \ |
201 | .display.overlay_needs_physical = 1, \ | |
b2ae318a | 202 | .display.has_gmch = 1, \ |
1eb31338 | 203 | .has_3d_pipeline = 1, \ |
55277e1f | 204 | .gpu_reset_clobbers_display = true, \ |
3177659a | 205 | .hws_needs_physical = 1, \ |
f4ce766f | 206 | .unfenced_needs_alignment = 1, \ |
488e29fe | 207 | .__runtime.platform_engine_mask = BIT(RCS0), \ |
5d95c248 | 208 | .has_snoop = true, \ |
900ccf30 | 209 | .has_coherent_ggtt = false, \ |
31a02eb7 | 210 | .dma_mask_size = 32, \ |
37fbbd49 VS |
211 | I845_PIPE_OFFSETS, \ |
212 | I845_CURSOR_OFFSETS, \ | |
82106247 | 213 | I9XX_COLORS, \ |
da1184cd MA |
214 | GEN_DEFAULT_PAGE_SIZES, \ |
215 | GEN_DEFAULT_REGIONS | |
0eec8dc7 | 216 | |
31409fff | 217 | static const struct intel_device_info i830_info = { |
37fbbd49 | 218 | I830_FEATURES, |
c5cb21c1 | 219 | PLATFORM(INTEL_I830), |
42f5551d CW |
220 | }; |
221 | ||
31409fff | 222 | static const struct intel_device_info i845g_info = { |
37fbbd49 | 223 | I845_FEATURES, |
c5cb21c1 | 224 | PLATFORM(INTEL_I845G), |
42f5551d CW |
225 | }; |
226 | ||
31409fff | 227 | static const struct intel_device_info i85x_info = { |
37fbbd49 | 228 | I830_FEATURES, |
c5cb21c1 | 229 | PLATFORM(INTEL_I85X), |
e6f19648 | 230 | .__runtime.fbc_mask = BIT(INTEL_FBC_A), |
42f5551d CW |
231 | }; |
232 | ||
31409fff | 233 | static const struct intel_device_info i865g_info = { |
37fbbd49 | 234 | I845_FEATURES, |
c5cb21c1 | 235 | PLATFORM(INTEL_I865G), |
e6f19648 | 236 | .__runtime.fbc_mask = BIT(INTEL_FBC_A), |
42f5551d CW |
237 | }; |
238 | ||
54d2a6a1 | 239 | #define GEN3_FEATURES \ |
bc76298e | 240 | GEN(3), \ |
00c6cbfd JN |
241 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ |
242 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ | |
b2ae318a | 243 | .display.has_gmch = 1, \ |
55277e1f | 244 | .gpu_reset_clobbers_display = true, \ |
488e29fe | 245 | .__runtime.platform_engine_mask = BIT(RCS0), \ |
1eb31338 | 246 | .has_3d_pipeline = 1, \ |
5d95c248 | 247 | .has_snoop = true, \ |
900ccf30 | 248 | .has_coherent_ggtt = true, \ |
31a02eb7 | 249 | .dma_mask_size = 32, \ |
37fbbd49 VS |
250 | I9XX_PIPE_OFFSETS, \ |
251 | I9XX_CURSOR_OFFSETS, \ | |
82106247 | 252 | I9XX_COLORS, \ |
da1184cd MA |
253 | GEN_DEFAULT_PAGE_SIZES, \ |
254 | GEN_DEFAULT_REGIONS | |
54d2a6a1 | 255 | |
31409fff | 256 | static const struct intel_device_info i915g_info = { |
54d2a6a1 | 257 | GEN3_FEATURES, |
c5cb21c1 | 258 | PLATFORM(INTEL_I915G), |
900ccf30 | 259 | .has_coherent_ggtt = false, |
d53db442 JRS |
260 | .display.cursor_needs_physical = 1, |
261 | .display.has_overlay = 1, | |
262 | .display.overlay_needs_physical = 1, | |
3177659a | 263 | .hws_needs_physical = 1, |
f4ce766f | 264 | .unfenced_needs_alignment = 1, |
42f5551d | 265 | }; |
a5ce929b | 266 | |
31409fff | 267 | static const struct intel_device_info i915gm_info = { |
54d2a6a1 | 268 | GEN3_FEATURES, |
c5cb21c1 | 269 | PLATFORM(INTEL_I915GM), |
54d2a6a1 | 270 | .is_mobile = 1, |
d53db442 JRS |
271 | .display.cursor_needs_physical = 1, |
272 | .display.has_overlay = 1, | |
273 | .display.overlay_needs_physical = 1, | |
274 | .display.supports_tv = 1, | |
e6f19648 | 275 | .__runtime.fbc_mask = BIT(INTEL_FBC_A), |
3177659a | 276 | .hws_needs_physical = 1, |
f4ce766f | 277 | .unfenced_needs_alignment = 1, |
42f5551d | 278 | }; |
a5ce929b | 279 | |
31409fff | 280 | static const struct intel_device_info i945g_info = { |
54d2a6a1 | 281 | GEN3_FEATURES, |
c5cb21c1 | 282 | PLATFORM(INTEL_I945G), |
d53db442 JRS |
283 | .display.has_hotplug = 1, |
284 | .display.cursor_needs_physical = 1, | |
285 | .display.has_overlay = 1, | |
286 | .display.overlay_needs_physical = 1, | |
3177659a | 287 | .hws_needs_physical = 1, |
f4ce766f | 288 | .unfenced_needs_alignment = 1, |
42f5551d | 289 | }; |
a5ce929b | 290 | |
31409fff | 291 | static const struct intel_device_info i945gm_info = { |
54d2a6a1 | 292 | GEN3_FEATURES, |
c5cb21c1 CW |
293 | PLATFORM(INTEL_I945GM), |
294 | .is_mobile = 1, | |
d53db442 JRS |
295 | .display.has_hotplug = 1, |
296 | .display.cursor_needs_physical = 1, | |
297 | .display.has_overlay = 1, | |
298 | .display.overlay_needs_physical = 1, | |
299 | .display.supports_tv = 1, | |
e6f19648 | 300 | .__runtime.fbc_mask = BIT(INTEL_FBC_A), |
3177659a | 301 | .hws_needs_physical = 1, |
f4ce766f | 302 | .unfenced_needs_alignment = 1, |
42f5551d CW |
303 | }; |
304 | ||
31409fff | 305 | static const struct intel_device_info g33_info = { |
a5ce929b | 306 | GEN3_FEATURES, |
c5cb21c1 | 307 | PLATFORM(INTEL_G33), |
d53db442 JRS |
308 | .display.has_hotplug = 1, |
309 | .display.has_overlay = 1, | |
31a02eb7 | 310 | .dma_mask_size = 36, |
a5ce929b JN |
311 | }; |
312 | ||
31409fff | 313 | static const struct intel_device_info pnv_g_info = { |
86d35d4e TU |
314 | GEN3_FEATURES, |
315 | PLATFORM(INTEL_PINEVIEW), | |
316 | .display.has_hotplug = 1, | |
317 | .display.has_overlay = 1, | |
31a02eb7 | 318 | .dma_mask_size = 36, |
86d35d4e TU |
319 | }; |
320 | ||
31409fff | 321 | static const struct intel_device_info pnv_m_info = { |
a5ce929b | 322 | GEN3_FEATURES, |
c5cb21c1 CW |
323 | PLATFORM(INTEL_PINEVIEW), |
324 | .is_mobile = 1, | |
d53db442 JRS |
325 | .display.has_hotplug = 1, |
326 | .display.has_overlay = 1, | |
31a02eb7 | 327 | .dma_mask_size = 36, |
a5ce929b JN |
328 | }; |
329 | ||
4d495bea | 330 | #define GEN4_FEATURES \ |
bc76298e | 331 | GEN(4), \ |
00c6cbfd JN |
332 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ |
333 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ | |
d53db442 | 334 | .display.has_hotplug = 1, \ |
b2ae318a | 335 | .display.has_gmch = 1, \ |
55277e1f | 336 | .gpu_reset_clobbers_display = true, \ |
488e29fe | 337 | .__runtime.platform_engine_mask = BIT(RCS0), \ |
1eb31338 | 338 | .has_3d_pipeline = 1, \ |
5d95c248 | 339 | .has_snoop = true, \ |
900ccf30 | 340 | .has_coherent_ggtt = true, \ |
31a02eb7 | 341 | .dma_mask_size = 36, \ |
37fbbd49 VS |
342 | I9XX_PIPE_OFFSETS, \ |
343 | I9XX_CURSOR_OFFSETS, \ | |
e262568e | 344 | I965_COLORS, \ |
da1184cd MA |
345 | GEN_DEFAULT_PAGE_SIZES, \ |
346 | GEN_DEFAULT_REGIONS | |
4d495bea | 347 | |
31409fff | 348 | static const struct intel_device_info i965g_info = { |
4d495bea | 349 | GEN4_FEATURES, |
c5cb21c1 | 350 | PLATFORM(INTEL_I965G), |
d53db442 | 351 | .display.has_overlay = 1, |
3177659a | 352 | .hws_needs_physical = 1, |
df0700e5 | 353 | .has_snoop = false, |
42f5551d CW |
354 | }; |
355 | ||
31409fff | 356 | static const struct intel_device_info i965gm_info = { |
4d495bea | 357 | GEN4_FEATURES, |
c5cb21c1 | 358 | PLATFORM(INTEL_I965GM), |
d53db442 | 359 | .is_mobile = 1, |
e6f19648 | 360 | .__runtime.fbc_mask = BIT(INTEL_FBC_A), |
d53db442 JRS |
361 | .display.has_overlay = 1, |
362 | .display.supports_tv = 1, | |
3177659a | 363 | .hws_needs_physical = 1, |
df0700e5 | 364 | .has_snoop = false, |
42f5551d CW |
365 | }; |
366 | ||
31409fff | 367 | static const struct intel_device_info g45_info = { |
4d495bea | 368 | GEN4_FEATURES, |
c5cb21c1 | 369 | PLATFORM(INTEL_G45), |
488e29fe | 370 | .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), |
55277e1f | 371 | .gpu_reset_clobbers_display = false, |
42f5551d CW |
372 | }; |
373 | ||
31409fff | 374 | static const struct intel_device_info gm45_info = { |
4d495bea | 375 | GEN4_FEATURES, |
c5cb21c1 | 376 | PLATFORM(INTEL_GM45), |
d53db442 | 377 | .is_mobile = 1, |
e6f19648 | 378 | .__runtime.fbc_mask = BIT(INTEL_FBC_A), |
d53db442 | 379 | .display.supports_tv = 1, |
488e29fe | 380 | .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), |
55277e1f | 381 | .gpu_reset_clobbers_display = false, |
42f5551d CW |
382 | }; |
383 | ||
a1323380 | 384 | #define GEN5_FEATURES \ |
bc76298e | 385 | GEN(5), \ |
00c6cbfd JN |
386 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ |
387 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ | |
d53db442 | 388 | .display.has_hotplug = 1, \ |
488e29fe | 389 | .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ |
1eb31338 | 390 | .has_3d_pipeline = 1, \ |
5d95c248 | 391 | .has_snoop = true, \ |
900ccf30 | 392 | .has_coherent_ggtt = true, \ |
fdbec9ff TU |
393 | /* ilk does support rc6, but we do not implement [power] contexts */ \ |
394 | .has_rc6 = 0, \ | |
31a02eb7 | 395 | .dma_mask_size = 36, \ |
37fbbd49 VS |
396 | I9XX_PIPE_OFFSETS, \ |
397 | I9XX_CURSOR_OFFSETS, \ | |
514462ca | 398 | ILK_COLORS, \ |
da1184cd MA |
399 | GEN_DEFAULT_PAGE_SIZES, \ |
400 | GEN_DEFAULT_REGIONS | |
a1323380 | 401 | |
31409fff | 402 | static const struct intel_device_info ilk_d_info = { |
a1323380 | 403 | GEN5_FEATURES, |
c5cb21c1 | 404 | PLATFORM(INTEL_IRONLAKE), |
42f5551d CW |
405 | }; |
406 | ||
31409fff | 407 | static const struct intel_device_info ilk_m_info = { |
a1323380 | 408 | GEN5_FEATURES, |
c5cb21c1 | 409 | PLATFORM(INTEL_IRONLAKE), |
d53db442 | 410 | .is_mobile = 1, |
2bf06370 | 411 | .has_rps = true, |
e6f19648 | 412 | .__runtime.fbc_mask = BIT(INTEL_FBC_A), |
42f5551d CW |
413 | }; |
414 | ||
07db6be7 | 415 | #define GEN6_FEATURES \ |
bc76298e | 416 | GEN(6), \ |
00c6cbfd JN |
417 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ |
418 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ | |
d53db442 | 419 | .display.has_hotplug = 1, \ |
e6f19648 | 420 | .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ |
488e29fe | 421 | .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ |
1eb31338 | 422 | .has_3d_pipeline = 1, \ |
900ccf30 | 423 | .has_coherent_ggtt = true, \ |
07db6be7 | 424 | .has_llc = 1, \ |
fdbec9ff | 425 | .has_rc6 = 1, \ |
67b0b4ed SD |
426 | /* snb does support rc6p, but enabling it causes various issues */ \ |
427 | .has_rc6p = 0, \ | |
91cbdb83 | 428 | .has_rps = true, \ |
31a02eb7 | 429 | .dma_mask_size = 40, \ |
268c67e5 JN |
430 | .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ |
431 | .__runtime.ppgtt_size = 31, \ | |
37fbbd49 VS |
432 | I9XX_PIPE_OFFSETS, \ |
433 | I9XX_CURSOR_OFFSETS, \ | |
514462ca | 434 | ILK_COLORS, \ |
da1184cd MA |
435 | GEN_DEFAULT_PAGE_SIZES, \ |
436 | GEN_DEFAULT_REGIONS | |
07db6be7 | 437 | |
0890540e LL |
438 | #define SNB_D_PLATFORM \ |
439 | GEN6_FEATURES, \ | |
c5cb21c1 | 440 | PLATFORM(INTEL_SANDYBRIDGE) |
0890540e | 441 | |
31409fff | 442 | static const struct intel_device_info snb_d_gt1_info = { |
0890540e LL |
443 | SNB_D_PLATFORM, |
444 | .gt = 1, | |
42f5551d CW |
445 | }; |
446 | ||
31409fff | 447 | static const struct intel_device_info snb_d_gt2_info = { |
0890540e LL |
448 | SNB_D_PLATFORM, |
449 | .gt = 2, | |
450 | }; | |
451 | ||
452 | #define SNB_M_PLATFORM \ | |
453 | GEN6_FEATURES, \ | |
c5cb21c1 | 454 | PLATFORM(INTEL_SANDYBRIDGE), \ |
0890540e LL |
455 | .is_mobile = 1 |
456 | ||
457 | ||
31409fff | 458 | static const struct intel_device_info snb_m_gt1_info = { |
0890540e LL |
459 | SNB_M_PLATFORM, |
460 | .gt = 1, | |
461 | }; | |
462 | ||
31409fff | 463 | static const struct intel_device_info snb_m_gt2_info = { |
0890540e LL |
464 | SNB_M_PLATFORM, |
465 | .gt = 2, | |
42f5551d CW |
466 | }; |
467 | ||
468 | #define GEN7_FEATURES \ | |
bc76298e | 469 | GEN(7), \ |
00c6cbfd JN |
470 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ |
471 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ | |
d53db442 | 472 | .display.has_hotplug = 1, \ |
e6f19648 | 473 | .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ |
488e29fe | 474 | .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ |
1eb31338 | 475 | .has_3d_pipeline = 1, \ |
900ccf30 | 476 | .has_coherent_ggtt = true, \ |
42f5551d | 477 | .has_llc = 1, \ |
fdbec9ff | 478 | .has_rc6 = 1, \ |
33b5bf82 | 479 | .has_rc6p = 1, \ |
b409db08 | 480 | .has_reset_engine = true, \ |
91cbdb83 | 481 | .has_rps = true, \ |
31a02eb7 | 482 | .dma_mask_size = 40, \ |
268c67e5 JN |
483 | .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ |
484 | .__runtime.ppgtt_size = 31, \ | |
37fbbd49 VS |
485 | IVB_PIPE_OFFSETS, \ |
486 | IVB_CURSOR_OFFSETS, \ | |
c21ce2ef | 487 | IVB_COLORS, \ |
da1184cd MA |
488 | GEN_DEFAULT_PAGE_SIZES, \ |
489 | GEN_DEFAULT_REGIONS | |
42f5551d | 490 | |
0890540e LL |
491 | #define IVB_D_PLATFORM \ |
492 | GEN7_FEATURES, \ | |
c5cb21c1 | 493 | PLATFORM(INTEL_IVYBRIDGE), \ |
0890540e LL |
494 | .has_l3_dpf = 1 |
495 | ||
31409fff | 496 | static const struct intel_device_info ivb_d_gt1_info = { |
0890540e LL |
497 | IVB_D_PLATFORM, |
498 | .gt = 1, | |
42f5551d CW |
499 | }; |
500 | ||
31409fff | 501 | static const struct intel_device_info ivb_d_gt2_info = { |
0890540e LL |
502 | IVB_D_PLATFORM, |
503 | .gt = 2, | |
504 | }; | |
505 | ||
506 | #define IVB_M_PLATFORM \ | |
507 | GEN7_FEATURES, \ | |
c5cb21c1 | 508 | PLATFORM(INTEL_IVYBRIDGE), \ |
0890540e LL |
509 | .is_mobile = 1, \ |
510 | .has_l3_dpf = 1 | |
511 | ||
31409fff | 512 | static const struct intel_device_info ivb_m_gt1_info = { |
0890540e LL |
513 | IVB_M_PLATFORM, |
514 | .gt = 1, | |
515 | }; | |
516 | ||
31409fff | 517 | static const struct intel_device_info ivb_m_gt2_info = { |
0890540e LL |
518 | IVB_M_PLATFORM, |
519 | .gt = 2, | |
42f5551d CW |
520 | }; |
521 | ||
31409fff | 522 | static const struct intel_device_info ivb_q_info = { |
42f5551d | 523 | GEN7_FEATURES, |
c5cb21c1 | 524 | PLATFORM(INTEL_IVYBRIDGE), |
47c3d075 | 525 | NO_DISPLAY, |
0890540e | 526 | .gt = 2, |
ca9c4523 | 527 | .has_l3_dpf = 1, |
42f5551d CW |
528 | }; |
529 | ||
31409fff | 530 | static const struct intel_device_info vlv_info = { |
c5cb21c1 | 531 | PLATFORM(INTEL_VALLEYVIEW), |
bc76298e | 532 | GEN(7), |
eb6f771b | 533 | .is_lp = 1, |
00c6cbfd JN |
534 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), |
535 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), | |
eb6f771b | 536 | .has_runtime_pm = 1, |
fdbec9ff | 537 | .has_rc6 = 1, |
b409db08 | 538 | .has_reset_engine = true, |
91cbdb83 | 539 | .has_rps = true, |
b2ae318a | 540 | .display.has_gmch = 1, |
d53db442 | 541 | .display.has_hotplug = 1, |
31a02eb7 | 542 | .dma_mask_size = 40, |
268c67e5 JN |
543 | .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, |
544 | .__runtime.ppgtt_size = 31, | |
5d95c248 | 545 | .has_snoop = true, |
900ccf30 | 546 | .has_coherent_ggtt = false, |
488e29fe | 547 | .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), |
c92df6aa | 548 | .display.mmio_offset = VLV_DISPLAY_BASE, |
37fbbd49 VS |
549 | I9XX_PIPE_OFFSETS, |
550 | I9XX_CURSOR_OFFSETS, | |
e262568e | 551 | I965_COLORS, |
2a9654b2 | 552 | GEN_DEFAULT_PAGE_SIZES, |
da1184cd | 553 | GEN_DEFAULT_REGIONS, |
42f5551d CW |
554 | }; |
555 | ||
42a3ae88 | 556 | #define G75_FEATURES \ |
42f5551d | 557 | GEN7_FEATURES, \ |
488e29fe | 558 | .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ |
00c6cbfd | 559 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ |
10cf8e75 | 560 | BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ |
9d8d5a39 | 561 | .display.has_ddi = 1, \ |
a321c3c6 | 562 | .display.has_fpga_dbg = 1, \ |
e91eec91 | 563 | .display.has_dp_mst = 1, \ |
33b5bf82 | 564 | .has_rc6p = 0 /* RC6p removed-by HSW */, \ |
37fbbd49 | 565 | HSW_PIPE_OFFSETS, \ |
4aa4c23f | 566 | .has_runtime_pm = 1 |
42f5551d | 567 | |
0890540e | 568 | #define HSW_PLATFORM \ |
42a3ae88 | 569 | G75_FEATURES, \ |
c5cb21c1 | 570 | PLATFORM(INTEL_HASWELL), \ |
0890540e LL |
571 | .has_l3_dpf = 1 |
572 | ||
31409fff | 573 | static const struct intel_device_info hsw_gt1_info = { |
0890540e LL |
574 | HSW_PLATFORM, |
575 | .gt = 1, | |
576 | }; | |
577 | ||
31409fff | 578 | static const struct intel_device_info hsw_gt2_info = { |
0890540e LL |
579 | HSW_PLATFORM, |
580 | .gt = 2, | |
581 | }; | |
582 | ||
31409fff | 583 | static const struct intel_device_info hsw_gt3_info = { |
0890540e LL |
584 | HSW_PLATFORM, |
585 | .gt = 3, | |
42f5551d CW |
586 | }; |
587 | ||
42a3ae88 RV |
588 | #define GEN8_FEATURES \ |
589 | G75_FEATURES, \ | |
a6e1c5ac | 590 | GEN(8), \ |
dfc5148f | 591 | .has_logical_ring_contexts = 1, \ |
31a02eb7 | 592 | .dma_mask_size = 39, \ |
268c67e5 JN |
593 | .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ |
594 | .__runtime.ppgtt_size = 48, \ | |
6f0f70cd | 595 | .has_64bit_reloc = 1 |
42f5551d | 596 | |
94829de4 | 597 | #define BDW_PLATFORM \ |
42a3ae88 | 598 | GEN8_FEATURES, \ |
c5cb21c1 | 599 | PLATFORM(INTEL_BROADWELL) |
94829de4 | 600 | |
31409fff | 601 | static const struct intel_device_info bdw_gt1_info = { |
0890540e LL |
602 | BDW_PLATFORM, |
603 | .gt = 1, | |
604 | }; | |
605 | ||
31409fff | 606 | static const struct intel_device_info bdw_gt2_info = { |
94829de4 | 607 | BDW_PLATFORM, |
0890540e LL |
608 | .gt = 2, |
609 | }; | |
610 | ||
31409fff | 611 | static const struct intel_device_info bdw_rsvd_info = { |
0890540e LL |
612 | BDW_PLATFORM, |
613 | .gt = 3, | |
614 | /* According to the device ID those devices are GT3, they were | |
615 | * previously treated as not GT3, keep it like that. | |
616 | */ | |
42f5551d CW |
617 | }; |
618 | ||
31409fff | 619 | static const struct intel_device_info bdw_gt3_info = { |
94829de4 | 620 | BDW_PLATFORM, |
0890540e | 621 | .gt = 3, |
488e29fe | 622 | .__runtime.platform_engine_mask = |
8a68d464 | 623 | BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), |
42f5551d CW |
624 | }; |
625 | ||
31409fff | 626 | static const struct intel_device_info chv_info = { |
c5cb21c1 | 627 | PLATFORM(INTEL_CHERRYVIEW), |
bc76298e | 628 | GEN(8), |
00c6cbfd JN |
629 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), |
630 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), | |
d53db442 | 631 | .display.has_hotplug = 1, |
8727dc09 | 632 | .is_lp = 1, |
488e29fe | 633 | .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), |
dfc5148f | 634 | .has_64bit_reloc = 1, |
4aa4c23f | 635 | .has_runtime_pm = 1, |
fdbec9ff | 636 | .has_rc6 = 1, |
91cbdb83 | 637 | .has_rps = true, |
4586f1d0 | 638 | .has_logical_ring_contexts = 1, |
b2ae318a | 639 | .display.has_gmch = 1, |
31a02eb7 | 640 | .dma_mask_size = 39, |
268c67e5 JN |
641 | .__runtime.ppgtt_type = INTEL_PPGTT_FULL, |
642 | .__runtime.ppgtt_size = 32, | |
b409db08 | 643 | .has_reset_engine = 1, |
5d95c248 | 644 | .has_snoop = true, |
900ccf30 | 645 | .has_coherent_ggtt = false, |
c92df6aa | 646 | .display.mmio_offset = VLV_DISPLAY_BASE, |
37fbbd49 VS |
647 | CHV_PIPE_OFFSETS, |
648 | CHV_CURSOR_OFFSETS, | |
42f5551d | 649 | CHV_COLORS, |
37fbbd49 | 650 | GEN_DEFAULT_PAGE_SIZES, |
da1184cd | 651 | GEN_DEFAULT_REGIONS, |
42f5551d CW |
652 | }; |
653 | ||
2a9654b2 | 654 | #define GEN9_DEFAULT_PAGE_SIZES \ |
9d0bad17 JN |
655 | .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ |
656 | I915_GTT_PAGE_SIZE_64K | |
2a9654b2 | 657 | |
42a3ae88 RV |
658 | #define GEN9_FEATURES \ |
659 | GEN8_FEATURES, \ | |
a6e1c5ac | 660 | GEN(9), \ |
2a9654b2 | 661 | GEN9_DEFAULT_PAGE_SIZES, \ |
e26700fc | 662 | .__runtime.has_dmc = 1, \ |
39921e5f | 663 | .has_gt_uc = 1, \ |
7578fc4d | 664 | .__runtime.has_hdcp = 1, \ |
d53db442 | 665 | .display.has_ipc = 1, \ |
9602efab | 666 | .display.has_psr = 1, \ |
ad26451a | 667 | .display.has_psr_hw_tracking = 1, \ |
04155815 VS |
668 | .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ |
669 | .display.dbuf.slice_mask = BIT(DBUF_S1) | |
94829de4 | 670 | |
42a3ae88 RV |
671 | #define SKL_PLATFORM \ |
672 | GEN9_FEATURES, \ | |
c5cb21c1 | 673 | PLATFORM(INTEL_SKYLAKE) |
42a3ae88 | 674 | |
31409fff | 675 | static const struct intel_device_info skl_gt1_info = { |
94829de4 | 676 | SKL_PLATFORM, |
0890540e | 677 | .gt = 1, |
42f5551d CW |
678 | }; |
679 | ||
31409fff | 680 | static const struct intel_device_info skl_gt2_info = { |
94829de4 | 681 | SKL_PLATFORM, |
0890540e LL |
682 | .gt = 2, |
683 | }; | |
684 | ||
685 | #define SKL_GT3_PLUS_PLATFORM \ | |
686 | SKL_PLATFORM, \ | |
488e29fe | 687 | .__runtime.platform_engine_mask = \ |
8a68d464 | 688 | BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) |
0890540e LL |
689 | |
690 | ||
31409fff | 691 | static const struct intel_device_info skl_gt3_info = { |
0890540e LL |
692 | SKL_GT3_PLUS_PLATFORM, |
693 | .gt = 3, | |
694 | }; | |
695 | ||
31409fff | 696 | static const struct intel_device_info skl_gt4_info = { |
0890540e LL |
697 | SKL_GT3_PLUS_PLATFORM, |
698 | .gt = 4, | |
42f5551d CW |
699 | }; |
700 | ||
80fa66b6 | 701 | #define GEN9_LP_FEATURES \ |
bc76298e | 702 | GEN(9), \ |
3e4274f8 | 703 | .is_lp = 1, \ |
04155815 | 704 | .display.dbuf.slice_mask = BIT(DBUF_S1), \ |
d53db442 | 705 | .display.has_hotplug = 1, \ |
488e29fe | 706 | .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ |
00c6cbfd JN |
707 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ |
708 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ | |
10cf8e75 VS |
709 | BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ |
710 | BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ | |
1eb31338 | 711 | .has_3d_pipeline = 1, \ |
80fa66b6 | 712 | .has_64bit_reloc = 1, \ |
9d8d5a39 | 713 | .display.has_ddi = 1, \ |
a321c3c6 | 714 | .display.has_fpga_dbg = 1, \ |
e6f19648 | 715 | .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ |
7578fc4d | 716 | .__runtime.has_hdcp = 1, \ |
9602efab | 717 | .display.has_psr = 1, \ |
24d2fc3d | 718 | .display.has_psr_hw_tracking = 1, \ |
80fa66b6 | 719 | .has_runtime_pm = 1, \ |
e26700fc | 720 | .__runtime.has_dmc = 1, \ |
fdbec9ff | 721 | .has_rc6 = 1, \ |
91cbdb83 | 722 | .has_rps = true, \ |
e91eec91 | 723 | .display.has_dp_mst = 1, \ |
80fa66b6 | 724 | .has_logical_ring_contexts = 1, \ |
39921e5f | 725 | .has_gt_uc = 1, \ |
31a02eb7 | 726 | .dma_mask_size = 39, \ |
268c67e5 JN |
727 | .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ |
728 | .__runtime.ppgtt_size = 48, \ | |
b409db08 | 729 | .has_reset_engine = 1, \ |
5d95c248 | 730 | .has_snoop = true, \ |
900ccf30 | 731 | .has_coherent_ggtt = false, \ |
d53db442 | 732 | .display.has_ipc = 1, \ |
37fbbd49 | 733 | HSW_PIPE_OFFSETS, \ |
80fa66b6 | 734 | IVB_CURSOR_OFFSETS, \ |
c21ce2ef | 735 | IVB_COLORS, \ |
da1184cd MA |
736 | GEN9_DEFAULT_PAGE_SIZES, \ |
737 | GEN_DEFAULT_REGIONS | |
80fa66b6 | 738 | |
31409fff | 739 | static const struct intel_device_info bxt_info = { |
80fa66b6 | 740 | GEN9_LP_FEATURES, |
c5cb21c1 | 741 | PLATFORM(INTEL_BROXTON), |
04155815 | 742 | .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ |
42f5551d CW |
743 | }; |
744 | ||
31409fff | 745 | static const struct intel_device_info glk_info = { |
c22097fa | 746 | GEN9_LP_FEATURES, |
c5cb21c1 | 747 | PLATFORM(INTEL_GEMINILAKE), |
f9e932a8 | 748 | .__runtime.display.ip.ver = 10, |
04155815 | 749 | .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ |
4672770d | 750 | GLK_COLORS, |
c22097fa ACO |
751 | }; |
752 | ||
94829de4 | 753 | #define KBL_PLATFORM \ |
42a3ae88 | 754 | GEN9_FEATURES, \ |
c5cb21c1 | 755 | PLATFORM(INTEL_KABYLAKE) |
94829de4 | 756 | |
31409fff | 757 | static const struct intel_device_info kbl_gt1_info = { |
94829de4 | 758 | KBL_PLATFORM, |
0890540e LL |
759 | .gt = 1, |
760 | }; | |
761 | ||
31409fff | 762 | static const struct intel_device_info kbl_gt2_info = { |
0890540e LL |
763 | KBL_PLATFORM, |
764 | .gt = 2, | |
42f5551d CW |
765 | }; |
766 | ||
31409fff | 767 | static const struct intel_device_info kbl_gt3_info = { |
94829de4 | 768 | KBL_PLATFORM, |
0890540e | 769 | .gt = 3, |
488e29fe | 770 | .__runtime.platform_engine_mask = |
8a68d464 | 771 | BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), |
42f5551d CW |
772 | }; |
773 | ||
71851fa8 | 774 | #define CFL_PLATFORM \ |
42a3ae88 | 775 | GEN9_FEATURES, \ |
c5cb21c1 | 776 | PLATFORM(INTEL_COFFEELAKE) |
71851fa8 | 777 | |
31409fff | 778 | static const struct intel_device_info cfl_gt1_info = { |
0890540e LL |
779 | CFL_PLATFORM, |
780 | .gt = 1, | |
781 | }; | |
782 | ||
31409fff | 783 | static const struct intel_device_info cfl_gt2_info = { |
71851fa8 | 784 | CFL_PLATFORM, |
0890540e | 785 | .gt = 2, |
71851fa8 RV |
786 | }; |
787 | ||
31409fff | 788 | static const struct intel_device_info cfl_gt3_info = { |
71851fa8 | 789 | CFL_PLATFORM, |
0890540e | 790 | .gt = 3, |
488e29fe | 791 | .__runtime.platform_engine_mask = |
8a68d464 | 792 | BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), |
71851fa8 RV |
793 | }; |
794 | ||
5f4ae270 CW |
795 | #define CML_PLATFORM \ |
796 | GEN9_FEATURES, \ | |
797 | PLATFORM(INTEL_COMETLAKE) | |
798 | ||
799 | static const struct intel_device_info cml_gt1_info = { | |
800 | CML_PLATFORM, | |
801 | .gt = 1, | |
802 | }; | |
803 | ||
804 | static const struct intel_device_info cml_gt2_info = { | |
805 | CML_PLATFORM, | |
806 | .gt = 2, | |
807 | }; | |
808 | ||
aaa914cd | 809 | #define GEN11_DEFAULT_PAGE_SIZES \ |
9d0bad17 JN |
810 | .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ |
811 | I915_GTT_PAGE_SIZE_64K | \ | |
812 | I915_GTT_PAGE_SIZE_2M | |
aaa914cd | 813 | |
41231001 | 814 | #define GEN11_FEATURES \ |
78f613ba | 815 | GEN9_FEATURES, \ |
aaa914cd | 816 | GEN11_DEFAULT_PAGE_SIZES, \ |
6678916d | 817 | .display.abox_mask = BIT(0), \ |
00c6cbfd | 818 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ |
10cf8e75 VS |
819 | BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ |
820 | BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ | |
12d74553 | 821 | .display.pipe_offsets = { \ |
931f5492 ID |
822 | [TRANSCODER_A] = PIPE_A_OFFSET, \ |
823 | [TRANSCODER_B] = PIPE_B_OFFSET, \ | |
824 | [TRANSCODER_C] = PIPE_C_OFFSET, \ | |
825 | [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ | |
826 | [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ | |
827 | [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ | |
828 | }, \ | |
12d74553 | 829 | .display.trans_offsets = { \ |
931f5492 ID |
830 | [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ |
831 | [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ | |
832 | [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ | |
833 | [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ | |
834 | [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ | |
835 | [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ | |
836 | }, \ | |
bc76298e | 837 | GEN(11), \ |
a37795cb | 838 | ICL_COLORS, \ |
04155815 VS |
839 | .display.dbuf.size = 2048, \ |
840 | .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ | |
3a9313d8 | 841 | .__runtime.has_dsc = 1, \ |
3d6c72b7 TU |
842 | .has_coherent_ggtt = false, \ |
843 | .has_logical_ring_elsq = 1 | |
41231001 | 844 | |
31409fff | 845 | static const struct intel_device_info icl_info = { |
41231001 | 846 | GEN11_FEATURES, |
c5cb21c1 | 847 | PLATFORM(INTEL_ICELAKE), |
488e29fe | 848 | .__runtime.platform_engine_mask = |
8a68d464 | 849 | BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), |
41231001 RV |
850 | }; |
851 | ||
31409fff | 852 | static const struct intel_device_info ehl_info = { |
29f3863d | 853 | GEN11_FEATURES, |
897f2961 | 854 | PLATFORM(INTEL_ELKHARTLAKE), |
488e29fe | 855 | .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), |
268c67e5 | 856 | .__runtime.ppgtt_size = 36, |
29f3863d JA |
857 | }; |
858 | ||
24ea098b TU |
859 | static const struct intel_device_info jsl_info = { |
860 | GEN11_FEATURES, | |
861 | PLATFORM(INTEL_JASPERLAKE), | |
488e29fe | 862 | .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), |
268c67e5 | 863 | .__runtime.ppgtt_size = 36, |
24ea098b TU |
864 | }; |
865 | ||
abd3a0fe DCS |
866 | #define GEN12_FEATURES \ |
867 | GEN11_FEATURES, \ | |
868 | GEN(12), \ | |
6678916d | 869 | .display.abox_mask = GENMASK(2, 1), \ |
00c6cbfd JN |
870 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ |
871 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ | |
10cf8e75 VS |
872 | BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ |
873 | BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ | |
12d74553 | 874 | .display.pipe_offsets = { \ |
abd3a0fe DCS |
875 | [TRANSCODER_A] = PIPE_A_OFFSET, \ |
876 | [TRANSCODER_B] = PIPE_B_OFFSET, \ | |
877 | [TRANSCODER_C] = PIPE_C_OFFSET, \ | |
878 | [TRANSCODER_D] = PIPE_D_OFFSET, \ | |
879 | [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ | |
880 | [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ | |
881 | }, \ | |
12d74553 | 882 | .display.trans_offsets = { \ |
abd3a0fe DCS |
883 | [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ |
884 | [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ | |
885 | [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ | |
886 | [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ | |
887 | [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ | |
888 | [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ | |
a7a7a0e6 | 889 | }, \ |
6ea3cee6 | 890 | TGL_CURSOR_OFFSETS, \ |
dfaa6f28 | 891 | .has_global_mocs = 1, \ |
6f8e2038 | 892 | .has_pxp = 1, \ |
99510e1a | 893 | .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */ |
abd3a0fe | 894 | |
31409fff | 895 | static const struct intel_device_info tgl_info = { |
abd3a0fe DCS |
896 | GEN12_FEATURES, |
897 | PLATFORM(INTEL_TIGERLAKE), | |
139ab811 | 898 | .display.has_modular_fia = 1, |
488e29fe | 899 | .__runtime.platform_engine_mask = |
abd3a0fe DCS |
900 | BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), |
901 | }; | |
902 | ||
123f62de MR |
903 | static const struct intel_device_info rkl_info = { |
904 | GEN12_FEATURES, | |
905 | PLATFORM(INTEL_ROCKETLAKE), | |
6678916d | 906 | .display.abox_mask = BIT(0), |
00c6cbfd JN |
907 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), |
908 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | | |
e95e7974 | 909 | BIT(TRANSCODER_C), |
ddff9a60 | 910 | .display.has_hti = 1, |
24d2fc3d | 911 | .display.has_psr_hw_tracking = 0, |
488e29fe | 912 | .__runtime.platform_engine_mask = |
123f62de MR |
913 | BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), |
914 | }; | |
915 | ||
425390c5 | 916 | #define DGFX_FEATURES \ |
f81f30b3 | 917 | .__runtime.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \ |
a4dbcf41 | 918 | .has_llc = 0, \ |
6f8e2038 | 919 | .has_pxp = 0, \ |
a4dbcf41 | 920 | .has_snoop = 1, \ |
1e3dc1d8 TW |
921 | .is_dgfx = 1, \ |
922 | .has_heci_gscfi = 1 | |
d8203d39 | 923 | |
81a14bed | 924 | static const struct intel_device_info dg1_info = { |
425390c5 LDM |
925 | GEN12_FEATURES, |
926 | DGFX_FEATURES, | |
f9e932a8 | 927 | .__runtime.graphics.ip.rel = 10, |
05e26584 | 928 | PLATFORM(INTEL_DG1), |
00c6cbfd | 929 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), |
05e26584 | 930 | .require_force_probe = 1, |
488e29fe | 931 | .__runtime.platform_engine_mask = |
05e26584 AJ |
932 | BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | |
933 | BIT(VCS0) | BIT(VCS2), | |
da942750 | 934 | /* Wa_16011227922 */ |
268c67e5 | 935 | .__runtime.ppgtt_size = 47, |
05e26584 AJ |
936 | }; |
937 | ||
0883d63b CY |
938 | static const struct intel_device_info adl_s_info = { |
939 | GEN12_FEATURES, | |
940 | PLATFORM(INTEL_ALDERLAKE_S), | |
00c6cbfd | 941 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), |
0883d63b CY |
942 | .display.has_hti = 1, |
943 | .display.has_psr_hw_tracking = 0, | |
488e29fe | 944 | .__runtime.platform_engine_mask = |
0883d63b | 945 | BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), |
88c6317b | 946 | .dma_mask_size = 39, |
0883d63b CY |
947 | }; |
948 | ||
8398024b | 949 | #define XE_LPD_FEATURES \ |
6678916d | 950 | .display.abox_mask = GENMASK(1, 0), \ |
f7fb92cd VS |
951 | .display.color = { \ |
952 | .degamma_lut_size = 128, .gamma_lut_size = 1024, \ | |
953 | .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ | |
954 | DRM_COLOR_LUT_EQUAL_CHANNELS, \ | |
1c7ab5af | 955 | }, \ |
04155815 VS |
956 | .display.dbuf.size = 4096, \ |
957 | .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ | |
b91e3c83 | 958 | BIT(DBUF_S4), \ |
9d8d5a39 | 959 | .display.has_ddi = 1, \ |
e26700fc | 960 | .__runtime.has_dmc = 1, \ |
e91eec91 | 961 | .display.has_dp_mst = 1, \ |
b91e3c83 | 962 | .display.has_dsb = 1, \ |
3a9313d8 | 963 | .__runtime.has_dsc = 1, \ |
e6f19648 | 964 | .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ |
b91e3c83 | 965 | .display.has_fpga_dbg = 1, \ |
7578fc4d | 966 | .__runtime.has_hdcp = 1, \ |
b91e3c83 LDM |
967 | .display.has_hotplug = 1, \ |
968 | .display.has_ipc = 1, \ | |
9602efab | 969 | .display.has_psr = 1, \ |
f9e932a8 | 970 | .__runtime.display.ip.ver = 13, \ |
00c6cbfd | 971 | .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ |
12d74553 | 972 | .display.pipe_offsets = { \ |
b91e3c83 LDM |
973 | [TRANSCODER_A] = PIPE_A_OFFSET, \ |
974 | [TRANSCODER_B] = PIPE_B_OFFSET, \ | |
975 | [TRANSCODER_C] = PIPE_C_OFFSET, \ | |
976 | [TRANSCODER_D] = PIPE_D_OFFSET, \ | |
09eea212 VK |
977 | [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ |
978 | [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ | |
b91e3c83 | 979 | }, \ |
12d74553 | 980 | .display.trans_offsets = { \ |
b91e3c83 LDM |
981 | [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ |
982 | [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ | |
983 | [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ | |
984 | [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ | |
09eea212 VK |
985 | [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ |
986 | [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ | |
b91e3c83 | 987 | }, \ |
95be40c8 | 988 | TGL_CURSOR_OFFSETS |
8398024b | 989 | |
bdd27cad CT |
990 | static const struct intel_device_info adl_p_info = { |
991 | GEN12_FEATURES, | |
992 | XE_LPD_FEATURES, | |
993 | PLATFORM(INTEL_ALDERLAKE_P), | |
00c6cbfd | 994 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | |
09eea212 VK |
995 | BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | |
996 | BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), | |
eafaa3e9 | 997 | .display.has_cdclk_crawl = 1, |
57ed0dfb | 998 | .display.has_modular_fia = 1, |
b91e3c83 | 999 | .display.has_psr_hw_tracking = 0, |
488e29fe | 1000 | .__runtime.platform_engine_mask = |
bdd27cad | 1001 | BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), |
268c67e5 | 1002 | .__runtime.ppgtt_size = 48, |
bdd27cad CT |
1003 | .dma_mask_size = 39, |
1004 | }; | |
1005 | ||
bc76298e | 1006 | #undef GEN |
05eb4638 LDM |
1007 | |
1008 | #define XE_HP_PAGE_SIZES \ | |
9d0bad17 JN |
1009 | .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ |
1010 | I915_GTT_PAGE_SIZE_64K | \ | |
1011 | I915_GTT_PAGE_SIZE_2M | |
05eb4638 LDM |
1012 | |
1013 | #define XE_HP_FEATURES \ | |
f9e932a8 RS |
1014 | .__runtime.graphics.ip.ver = 12, \ |
1015 | .__runtime.graphics.ip.rel = 50, \ | |
05eb4638 LDM |
1016 | XE_HP_PAGE_SIZES, \ |
1017 | .dma_mask_size = 46, \ | |
1eb31338 | 1018 | .has_3d_pipeline = 1, \ |
05eb4638 | 1019 | .has_64bit_reloc = 1, \ |
5e3094cf | 1020 | .has_flat_ccs = 1, \ |
05eb4638 | 1021 | .has_global_mocs = 1, \ |
39921e5f | 1022 | .has_gt_uc = 1, \ |
05eb4638 LDM |
1023 | .has_llc = 1, \ |
1024 | .has_logical_ring_contexts = 1, \ | |
3d6c72b7 | 1025 | .has_logical_ring_elsq = 1, \ |
e0d7371b | 1026 | .has_mslice_steering = 1, \ |
cceb0849 | 1027 | .has_oa_bpc_reporting = 1, \ |
0fa9349d | 1028 | .has_oa_slice_contrib_limits = 1, \ |
fdbec9ff | 1029 | .has_rc6 = 1, \ |
b409db08 | 1030 | .has_reset_engine = 1, \ |
05eb4638 LDM |
1031 | .has_rps = 1, \ |
1032 | .has_runtime_pm = 1, \ | |
268c67e5 JN |
1033 | .__runtime.ppgtt_size = 48, \ |
1034 | .__runtime.ppgtt_type = INTEL_PPGTT_FULL | |
05eb4638 | 1035 | |
086df54e | 1036 | #define XE_HPM_FEATURES \ |
f9e932a8 RS |
1037 | .__runtime.media.ip.ver = 12, \ |
1038 | .__runtime.media.ip.rel = 50 | |
086df54e LDM |
1039 | |
1040 | __maybe_unused | |
1041 | static const struct intel_device_info xehpsdv_info = { | |
1042 | XE_HP_FEATURES, | |
1043 | XE_HPM_FEATURES, | |
1044 | DGFX_FEATURES, | |
1045 | PLATFORM(INTEL_XEHPSDV), | |
47c3d075 | 1046 | NO_DISPLAY, |
c83125bb | 1047 | .has_64k_pages = 1, |
85a040bc | 1048 | .has_media_ratio_mode = 1, |
488e29fe | 1049 | .__runtime.platform_engine_mask = |
086df54e | 1050 | BIT(RCS0) | BIT(BCS0) | |
938c778f JH |
1051 | BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | |
1052 | BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | | |
59a47528 DCS |
1053 | BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) | |
1054 | BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), | |
086df54e LDM |
1055 | .require_force_probe = 1, |
1056 | }; | |
1057 | ||
412c942b MR |
1058 | #define DG2_FEATURES \ |
1059 | XE_HP_FEATURES, \ | |
1060 | XE_HPM_FEATURES, \ | |
1061 | DGFX_FEATURES, \ | |
f9e932a8 RS |
1062 | .__runtime.graphics.ip.rel = 55, \ |
1063 | .__runtime.media.ip.rel = 55, \ | |
412c942b MR |
1064 | PLATFORM(INTEL_DG2), \ |
1065 | .has_4tile = 1, \ | |
1066 | .has_64k_pages = 1, \ | |
1067 | .has_guc_deprivilege = 1, \ | |
f15856d7 | 1068 | .has_heci_pxp = 1, \ |
85a040bc | 1069 | .has_media_ratio_mode = 1, \ |
1d32f5d6 | 1070 | .display.has_cdclk_squash = 1, \ |
488e29fe | 1071 | .__runtime.platform_engine_mask = \ |
412c942b MR |
1072 | BIT(RCS0) | BIT(BCS0) | \ |
1073 | BIT(VECS0) | BIT(VECS1) | \ | |
59a47528 DCS |
1074 | BIT(VCS0) | BIT(VCS2) | \ |
1075 | BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3) | |
412c942b | 1076 | |
9e22cfc5 | 1077 | static const struct intel_device_info dg2_info = { |
412c942b | 1078 | DG2_FEATURES, |
9e22cfc5 | 1079 | XE_LPD_FEATURES, |
00c6cbfd | 1080 | .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | |
09eea212 | 1081 | BIT(TRANSCODER_C) | BIT(TRANSCODER_D), |
412c942b MR |
1082 | }; |
1083 | ||
412c942b MR |
1084 | static const struct intel_device_info ats_m_info = { |
1085 | DG2_FEATURES, | |
47c3d075 | 1086 | NO_DISPLAY, |
412c942b | 1087 | .require_force_probe = 1, |
73c7a8a8 | 1088 | .tuning_thread_rr_after_dep = 1, |
9e22cfc5 MR |
1089 | }; |
1090 | ||
448a54ac SS |
1091 | #define XE_HPC_FEATURES \ |
1092 | XE_HP_FEATURES, \ | |
9d67edba | 1093 | .dma_mask_size = 52, \ |
1eb31338 | 1094 | .has_3d_pipeline = 0, \ |
f7dad0da | 1095 | .has_guc_deprivilege = 1, \ |
5ac342ef | 1096 | .has_l3_ccs_read = 1, \ |
e0d7371b | 1097 | .has_mslice_steering = 0, \ |
5ac342ef | 1098 | .has_one_eu_per_fuse_bit = 1 |
448a54ac SS |
1099 | |
1100 | __maybe_unused | |
1101 | static const struct intel_device_info pvc_info = { | |
1102 | XE_HPC_FEATURES, | |
1103 | XE_HPM_FEATURES, | |
1104 | DGFX_FEATURES, | |
f9e932a8 RS |
1105 | .__runtime.graphics.ip.rel = 60, |
1106 | .__runtime.media.ip.rel = 60, | |
448a54ac | 1107 | PLATFORM(INTEL_PONTEVECCHIO), |
47c3d075 | 1108 | NO_DISPLAY, |
448a54ac | 1109 | .has_flat_ccs = 0, |
488e29fe | 1110 | .__runtime.platform_engine_mask = |
448a54ac SS |
1111 | BIT(BCS0) | |
1112 | BIT(VCS0) | | |
1113 | BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), | |
1114 | .require_force_probe = 1, | |
1115 | }; | |
1116 | ||
bcf9b296 RS |
1117 | #define XE_LPDP_FEATURES \ |
1118 | XE_LPD_FEATURES, \ | |
f9e932a8 | 1119 | .__runtime.display.ip.ver = 14, \ |
4cf05a4d | 1120 | .display.has_cdclk_crawl = 1, \ |
e6f19648 | 1121 | .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
bcf9b296 | 1122 | |
f0e2f00c MR |
1123 | static const struct intel_gt_definition xelpmp_extra_gt[] = { |
1124 | { | |
1125 | .type = GT_MEDIA, | |
1126 | .name = "Standalone Media GT", | |
1127 | .gsi_offset = MTL_MEDIA_GSI_BASE, | |
1128 | .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2), | |
1129 | }, | |
1130 | {} | |
1131 | }; | |
1132 | ||
bcf9b296 RS |
1133 | static const struct intel_device_info mtl_info = { |
1134 | XE_HP_FEATURES, | |
1135 | XE_LPDP_FEATURES, | |
1136 | /* | |
1137 | * Real graphics IP version will be obtained from hardware GMD_ID | |
1138 | * register. Value provided here is just for sanity checking. | |
1139 | */ | |
f9e932a8 RS |
1140 | .__runtime.graphics.ip.ver = 12, |
1141 | .__runtime.graphics.ip.rel = 70, | |
1142 | .__runtime.media.ip.ver = 13, | |
bcf9b296 RS |
1143 | PLATFORM(INTEL_METEORLAKE), |
1144 | .display.has_modular_fia = 1, | |
f0e2f00c | 1145 | .extra_gt_list = xelpmp_extra_gt, |
bcf9b296 | 1146 | .has_flat_ccs = 0, |
c2c70752 | 1147 | .has_gmd_id = 1, |
00b4c0ef | 1148 | .has_guc_deprivilege = 1, |
f32898c9 | 1149 | .has_mslice_steering = 0, |
bcf9b296 | 1150 | .has_snoop = 1, |
f81f30b3 | 1151 | .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, |
488e29fe | 1152 | .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), |
bcf9b296 RS |
1153 | .require_force_probe = 1, |
1154 | }; | |
1155 | ||
c5cb21c1 | 1156 | #undef PLATFORM |
bc76298e | 1157 | |
42f5551d CW |
1158 | /* |
1159 | * Make sure any device matches here are from most specific to most | |
1160 | * general. For example, since the Quanta match is based on the subsystem | |
1161 | * and subvendor IDs, we need it to come before the more general IVB | |
1162 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
1163 | */ | |
1164 | static const struct pci_device_id pciidlist[] = { | |
31409fff LDM |
1165 | INTEL_I830_IDS(&i830_info), |
1166 | INTEL_I845G_IDS(&i845g_info), | |
1167 | INTEL_I85X_IDS(&i85x_info), | |
1168 | INTEL_I865G_IDS(&i865g_info), | |
1169 | INTEL_I915G_IDS(&i915g_info), | |
1170 | INTEL_I915GM_IDS(&i915gm_info), | |
1171 | INTEL_I945G_IDS(&i945g_info), | |
1172 | INTEL_I945GM_IDS(&i945gm_info), | |
1173 | INTEL_I965G_IDS(&i965g_info), | |
1174 | INTEL_G33_IDS(&g33_info), | |
1175 | INTEL_I965GM_IDS(&i965gm_info), | |
1176 | INTEL_GM45_IDS(&gm45_info), | |
1177 | INTEL_G45_IDS(&g45_info), | |
1178 | INTEL_PINEVIEW_G_IDS(&pnv_g_info), | |
1179 | INTEL_PINEVIEW_M_IDS(&pnv_m_info), | |
1180 | INTEL_IRONLAKE_D_IDS(&ilk_d_info), | |
1181 | INTEL_IRONLAKE_M_IDS(&ilk_m_info), | |
1182 | INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), | |
1183 | INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), | |
1184 | INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), | |
1185 | INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), | |
1186 | INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ | |
1187 | INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), | |
1188 | INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), | |
1189 | INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), | |
1190 | INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), | |
1191 | INTEL_HSW_GT1_IDS(&hsw_gt1_info), | |
1192 | INTEL_HSW_GT2_IDS(&hsw_gt2_info), | |
1193 | INTEL_HSW_GT3_IDS(&hsw_gt3_info), | |
1194 | INTEL_VLV_IDS(&vlv_info), | |
1195 | INTEL_BDW_GT1_IDS(&bdw_gt1_info), | |
1196 | INTEL_BDW_GT2_IDS(&bdw_gt2_info), | |
1197 | INTEL_BDW_GT3_IDS(&bdw_gt3_info), | |
1198 | INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), | |
1199 | INTEL_CHV_IDS(&chv_info), | |
1200 | INTEL_SKL_GT1_IDS(&skl_gt1_info), | |
1201 | INTEL_SKL_GT2_IDS(&skl_gt2_info), | |
1202 | INTEL_SKL_GT3_IDS(&skl_gt3_info), | |
1203 | INTEL_SKL_GT4_IDS(&skl_gt4_info), | |
1204 | INTEL_BXT_IDS(&bxt_info), | |
1205 | INTEL_GLK_IDS(&glk_info), | |
1206 | INTEL_KBL_GT1_IDS(&kbl_gt1_info), | |
1207 | INTEL_KBL_GT2_IDS(&kbl_gt2_info), | |
1208 | INTEL_KBL_GT3_IDS(&kbl_gt3_info), | |
1209 | INTEL_KBL_GT4_IDS(&kbl_gt3_info), | |
1210 | INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), | |
1211 | INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), | |
1212 | INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), | |
1213 | INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), | |
1214 | INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), | |
1215 | INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), | |
1216 | INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), | |
1217 | INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), | |
1218 | INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), | |
1219 | INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), | |
1220 | INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), | |
5f4ae270 CW |
1221 | INTEL_CML_GT1_IDS(&cml_gt1_info), |
1222 | INTEL_CML_GT2_IDS(&cml_gt2_info), | |
1223 | INTEL_CML_U_GT1_IDS(&cml_gt1_info), | |
1224 | INTEL_CML_U_GT2_IDS(&cml_gt2_info), | |
31409fff LDM |
1225 | INTEL_ICL_11_IDS(&icl_info), |
1226 | INTEL_EHL_IDS(&ehl_info), | |
24ea098b | 1227 | INTEL_JSL_IDS(&jsl_info), |
31409fff | 1228 | INTEL_TGL_12_IDS(&tgl_info), |
123f62de | 1229 | INTEL_RKL_IDS(&rkl_info), |
0883d63b | 1230 | INTEL_ADLS_IDS(&adl_s_info), |
bdd27cad | 1231 | INTEL_ADLP_IDS(&adl_p_info), |
7e28d0b2 | 1232 | INTEL_ADLN_IDS(&adl_p_info), |
d5ef86b3 | 1233 | INTEL_DG1_IDS(&dg1_info), |
52407c22 | 1234 | INTEL_RPLS_IDS(&adl_s_info), |
72c3c8d6 | 1235 | INTEL_RPLP_IDS(&adl_p_info), |
1bc4ae0c | 1236 | INTEL_DG2_IDS(&dg2_info), |
8618b848 | 1237 | INTEL_ATS_M_IDS(&ats_m_info), |
78353039 | 1238 | INTEL_MTL_IDS(&mtl_info), |
42f5551d CW |
1239 | {0, 0, 0} |
1240 | }; | |
1241 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
1242 | ||
953c7f82 CW |
1243 | static void i915_pci_remove(struct pci_dev *pdev) |
1244 | { | |
361f9dc2 | 1245 | struct drm_i915_private *i915; |
159b69bc | 1246 | |
361f9dc2 CW |
1247 | i915 = pci_get_drvdata(pdev); |
1248 | if (!i915) /* driver load aborted, nothing to cleanup */ | |
159b69bc | 1249 | return; |
953c7f82 | 1250 | |
361f9dc2 | 1251 | i915_driver_remove(i915); |
159b69bc | 1252 | pci_set_drvdata(pdev, NULL); |
953c7f82 CW |
1253 | } |
1254 | ||
7ef5ef5c JN |
1255 | /* is device_id present in comma separated list of ids */ |
1256 | static bool force_probe(u16 device_id, const char *devices) | |
1257 | { | |
1258 | char *s, *p, *tok; | |
1259 | bool ret; | |
1260 | ||
7ef5ef5c JN |
1261 | if (!devices || !*devices) |
1262 | return false; | |
1263 | ||
1264 | /* match everything */ | |
1265 | if (strcmp(devices, "*") == 0) | |
1266 | return true; | |
1267 | ||
1268 | s = kstrdup(devices, GFP_KERNEL); | |
1269 | if (!s) | |
1270 | return false; | |
1271 | ||
1272 | for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { | |
1273 | u16 val; | |
1274 | ||
1275 | if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { | |
1276 | ret = true; | |
1277 | break; | |
1278 | } | |
1279 | } | |
1280 | ||
1281 | kfree(s); | |
1282 | ||
1283 | return ret; | |
1284 | } | |
1285 | ||
1bba7323 PP |
1286 | bool i915_pci_resource_valid(struct pci_dev *pdev, int bar) |
1287 | { | |
1288 | if (!pci_resource_flags(pdev, bar)) | |
1289 | return false; | |
1290 | ||
1291 | if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) | |
1292 | return false; | |
1293 | ||
1294 | if (!pci_resource_len(pdev, bar)) | |
1295 | return false; | |
1296 | ||
1297 | return true; | |
1298 | } | |
1299 | ||
1300 | static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info) | |
1301 | { | |
5bfcff51 | 1302 | return i915_pci_resource_valid(pdev, intel_mmio_bar(intel_info->__runtime.graphics.ip.ver)); |
1bba7323 PP |
1303 | } |
1304 | ||
42f5551d CW |
1305 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1306 | { | |
1307 | struct intel_device_info *intel_info = | |
1308 | (struct intel_device_info *) ent->driver_data; | |
953c7f82 | 1309 | int err; |
42f5551d | 1310 | |
7ef5ef5c JN |
1311 | if (intel_info->require_force_probe && |
1312 | !force_probe(pdev->device, i915_modparams.force_probe)) { | |
71b7cc60 | 1313 | dev_info(&pdev->dev, |
7daac72e | 1314 | "Your graphics device %04x is not properly supported by the driver in this\n" |
7ef5ef5c JN |
1315 | "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" |
1316 | "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" | |
1317 | "or (recommended) check for kernel updates.\n", | |
1318 | pdev->device, pdev->device, pdev->device); | |
42f5551d CW |
1319 | return -ENODEV; |
1320 | } | |
1321 | ||
1322 | /* Only bind to function 0 of the device. Early generations | |
1323 | * used function 1 as a placeholder for multi-head. This causes | |
1324 | * us confusion instead, especially on the systems where both | |
1325 | * functions have the same PCI-ID! | |
1326 | */ | |
1327 | if (PCI_FUNC(pdev->devfn)) | |
1328 | return -ENODEV; | |
1329 | ||
1bba7323 PP |
1330 | if (!intel_mmio_bar_valid(pdev, intel_info)) |
1331 | return -ENXIO; | |
1332 | ||
94b541f5 HG |
1333 | /* Detect if we need to wait for other drivers early on */ |
1334 | if (intel_modeset_probe_defer(pdev)) | |
42f5551d CW |
1335 | return -EPROBE_DEFER; |
1336 | ||
b01558e5 | 1337 | err = i915_driver_probe(pdev, ent); |
953c7f82 CW |
1338 | if (err) |
1339 | return err; | |
42f5551d | 1340 | |
361f9dc2 | 1341 | if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { |
159b69bc CW |
1342 | i915_pci_remove(pdev); |
1343 | return -ENODEV; | |
1344 | } | |
1345 | ||
953c7f82 CW |
1346 | err = i915_live_selftests(pdev); |
1347 | if (err) { | |
1348 | i915_pci_remove(pdev); | |
1349 | return err > 0 ? -ENOTTY : err; | |
1350 | } | |
42f5551d | 1351 | |
3c7a44bb CW |
1352 | err = i915_perf_selftests(pdev); |
1353 | if (err) { | |
1354 | i915_pci_remove(pdev); | |
1355 | return err > 0 ? -ENOTTY : err; | |
1356 | } | |
1357 | ||
953c7f82 | 1358 | return 0; |
42f5551d CW |
1359 | } |
1360 | ||
fe0f1e3b VS |
1361 | static void i915_pci_shutdown(struct pci_dev *pdev) |
1362 | { | |
1363 | struct drm_i915_private *i915 = pci_get_drvdata(pdev); | |
1364 | ||
1365 | i915_driver_shutdown(i915); | |
1366 | } | |
1367 | ||
a09d0ba1 | 1368 | static struct pci_driver i915_pci_driver = { |
42f5551d CW |
1369 | .name = DRIVER_NAME, |
1370 | .id_table = pciidlist, | |
1371 | .probe = i915_pci_probe, | |
1372 | .remove = i915_pci_remove, | |
fe0f1e3b | 1373 | .shutdown = i915_pci_shutdown, |
42f5551d CW |
1374 | .driver.pm = &i915_pm_ops, |
1375 | }; | |
a09d0ba1 | 1376 | |
f3ede209 | 1377 | int i915_pci_register_driver(void) |
a09d0ba1 | 1378 | { |
a04ea6ae | 1379 | return pci_register_driver(&i915_pci_driver); |
a09d0ba1 CW |
1380 | } |
1381 | ||
f3ede209 | 1382 | void i915_pci_unregister_driver(void) |
a09d0ba1 | 1383 | { |
a09d0ba1 CW |
1384 | pci_unregister_driver(&i915_pci_driver); |
1385 | } |