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drm/i915: manage PCH PLLs separately from pipes
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
1da177e4 40#define MAX_NOPID ((u32)~0)
1da177e4 41
7c463586
KP		 42/**
43 * Interrupts that are always left unmasked.
44 *
45 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
46 * we leave them always unmasked in IMR and then control enabling them through
47 * PIPESTAT alone.
48 */
6b95a207
KH		 49#define I915_INTERRUPT_ENABLE_FIX \
50 (I915_ASLE_INTERRUPT | \
51 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
52 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
53 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
54 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
55 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
7c463586
KP		 56
57/** Interrupts that we mask and unmask at runtime. */
d1b851fc 58#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
7c463586 59
79e53945
JB		 60#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
61 PIPE_VBLANK_INTERRUPT_STATUS)
62
63#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
64 PIPE_VBLANK_INTERRUPT_ENABLE)
65
66#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
67 DRM_I915_VBLANK_PIPE_B)
68
036a4a7d 69/* For display hotplug interrupt */
995b6762 70static void
f2b115e6 71ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 72{
1ec14ad3
CW		 73 if ((dev_priv->irq_mask & mask) != 0) {
74 dev_priv->irq_mask &= ~mask;
75 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 76 POSTING_READ(DEIMR);
036a4a7d
ZW		 77 }
78}
79
80static inline void
f2b115e6 81ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 82{
1ec14ad3
CW		 83 if ((dev_priv->irq_mask & mask) != mask) {
84 dev_priv->irq_mask |= mask;
85 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 86 POSTING_READ(DEIMR);
036a4a7d
ZW		 87 }
88}
89
7c463586
KP		 90void
91i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
92{
93 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 94 u32 reg = PIPESTAT(pipe);
7c463586
KP		 95
96 dev_priv->pipestat[pipe] |= mask;
97 /* Enable the interrupt, clear any pending status */
98 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 99 POSTING_READ(reg);
7c463586
KP		 100 }
101}
102
103void
104i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
105{
106 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 107 u32 reg = PIPESTAT(pipe);
7c463586
KP		 108
109 dev_priv->pipestat[pipe] &= ~mask;
110 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 111 POSTING_READ(reg);
7c463586
KP		 112 }
113}
114
01c66889
ZY		 115/**
116 * intel_enable_asle - enable ASLE interrupt for OpRegion
117 */
1ec14ad3 118void intel_enable_asle(struct drm_device *dev)
01c66889 119{
1ec14ad3
CW		 120 drm_i915_private_t *dev_priv = dev->dev_private;
121 unsigned long irqflags;
122
7e231dbe
JB		 123 /* FIXME: opregion/asle for VLV */
124 if (IS_VALLEYVIEW(dev))
125 return;
126
1ec14ad3 127 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 128
c619eed4 129 if (HAS_PCH_SPLIT(dev))
f2b115e6 130 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 131 else {
01c66889 132 i915_enable_pipestat(dev_priv, 1,
d874bcff 133 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 134 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 135 i915_enable_pipestat(dev_priv, 0,
d874bcff 136 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 137 }
1ec14ad3
CW		 138
139 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 140}
141
0a3e67a4
JB		 142/**
143 * i915_pipe_enabled - check if a pipe is enabled
144 * @dev: DRM device
145 * @pipe: pipe to check
146 *
147 * Reading certain registers when the pipe is disabled can hang the chip.
148 * Use this routine to make sure the PLL is running and the pipe is active
149 * before reading such registers if unsure.
150 */
151static int
152i915_pipe_enabled(struct drm_device *dev, int pipe)
153{
154 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 155 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 156}
157
42f52ef8
KP		 158/* Called from drm generic code, passed a 'crtc', which
159 * we use as a pipe index
160 */
f71d4af4 161static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 162{
163 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
164 unsigned long high_frame;
165 unsigned long low_frame;
5eddb70b 166 u32 high1, high2, low;
0a3e67a4
JB		 167
168 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 169 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 170 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 171 return 0;
172 }
173
9db4a9c7
JB		 174 high_frame = PIPEFRAME(pipe);
175 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 176
0a3e67a4
JB		 177 /*
178 * High & low register fields aren't synchronized, so make sure
179 * we get a low value that's stable across two reads of the high
180 * register.
181 */
182 do {
5eddb70b
CW		 183 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
184 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
185 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 186 } while (high1 != high2);
187
5eddb70b
CW		 188 high1 >>= PIPE_FRAME_HIGH_SHIFT;
189 low >>= PIPE_FRAME_LOW_SHIFT;
190 return (high1 << 8) | low;
0a3e67a4
JB		 191}
192
f71d4af4 193static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 194{
195 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 196 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 197
198 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 199 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 200 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 201 return 0;
202 }
203
204 return I915_READ(reg);
205}
206
f71d4af4 207static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 208 int *vpos, int *hpos)
209{
210 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
211 u32 vbl = 0, position = 0;
212 int vbl_start, vbl_end, htotal, vtotal;
213 bool in_vbl = true;
214 int ret = 0;
215
216 if (!i915_pipe_enabled(dev, pipe)) {
217 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 218 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 219 return 0;
220 }
221
222 /* Get vtotal. */
223 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
224
225 if (INTEL_INFO(dev)->gen >= 4) {
226 /* No obvious pixelcount register. Only query vertical
227 * scanout position from Display scan line register.
228 */
229 position = I915_READ(PIPEDSL(pipe));
230
231 /* Decode into vertical scanout position. Don't have
232 * horizontal scanout position.
233 */
234 *vpos = position & 0x1fff;
235 *hpos = 0;
236 } else {
237 /* Have access to pixelcount since start of frame.
238 * We can split this into vertical and horizontal
239 * scanout position.
240 */
241 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
242
243 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
244 *vpos = position / htotal;
245 *hpos = position - (*vpos * htotal);
246 }
247
248 /* Query vblank area. */
249 vbl = I915_READ(VBLANK(pipe));
250
251 /* Test position against vblank region. */
252 vbl_start = vbl & 0x1fff;
253 vbl_end = (vbl >> 16) & 0x1fff;
254
255 if ((*vpos < vbl_start) || (*vpos > vbl_end))
256 in_vbl = false;
257
258 /* Inside "upper part" of vblank area? Apply corrective offset: */
259 if (in_vbl && (*vpos >= vbl_start))
260 *vpos = *vpos - vtotal;
261
262 /* Readouts valid? */
263 if (vbl > 0)
264 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
265
266 /* In vblank? */
267 if (in_vbl)
268 ret |= DRM_SCANOUTPOS_INVBL;
269
270 return ret;
271}
272
f71d4af4 273static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 274 int *max_error,
275 struct timeval *vblank_time,
276 unsigned flags)
277{
4041b853
CW		 278 struct drm_i915_private *dev_priv = dev->dev_private;
279 struct drm_crtc *crtc;
0af7e4df 280
4041b853
CW		 281 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
282 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 283 return -EINVAL;
284 }
285
286 /* Get drm_crtc to timestamp: */
4041b853
CW		 287 crtc = intel_get_crtc_for_pipe(dev, pipe);
288 if (crtc == NULL) {
289 DRM_ERROR("Invalid crtc %d\n", pipe);
290 return -EINVAL;
291 }
292
293 if (!crtc->enabled) {
294 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
295 return -EBUSY;
296 }
0af7e4df
MK		 297
298 /* Helper routine in DRM core does all the work: */
4041b853
CW		 299 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
300 vblank_time, flags,
301 crtc);
0af7e4df
MK		 302}
303
5ca58282
JB		 304/*
305 * Handle hotplug events outside the interrupt handler proper.
306 */
307static void i915_hotplug_work_func(struct work_struct *work)
308{
309 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
310 hotplug_work);
311 struct drm_device *dev = dev_priv->dev;
c31c4ba3 312 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 313 struct intel_encoder *encoder;
314
a65e34c7 315 mutex_lock(&mode_config->mutex);
e67189ab
JB		 316 DRM_DEBUG_KMS("running encoder hotplug functions\n");
317
4ef69c7a
CW		 318 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
319 if (encoder->hot_plug)
320 encoder->hot_plug(encoder);
321
40ee3381
KP		 322 mutex_unlock(&mode_config->mutex);
323
5ca58282 324 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 325 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 326}
327
f97108d1
JB		 328static void i915_handle_rps_change(struct drm_device *dev)
329{
330 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 331 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 332 u8 new_delay = dev_priv->cur_delay;
333
7648fa99 334 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 335 busy_up = I915_READ(RCPREVBSYTUPAVG);
336 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 337 max_avg = I915_READ(RCBMAXAVG);
338 min_avg = I915_READ(RCBMINAVG);
339
340 /* Handle RCS change request from hw */
b5b72e89 341 if (busy_up > max_avg) {
f97108d1
JB		 342 if (dev_priv->cur_delay != dev_priv->max_delay)
343 new_delay = dev_priv->cur_delay - 1;
344 if (new_delay < dev_priv->max_delay)
345 new_delay = dev_priv->max_delay;
b5b72e89 346 } else if (busy_down < min_avg) {
f97108d1
JB		 347 if (dev_priv->cur_delay != dev_priv->min_delay)
348 new_delay = dev_priv->cur_delay + 1;
349 if (new_delay > dev_priv->min_delay)
350 new_delay = dev_priv->min_delay;
351 }
352
7648fa99
JB		 353 if (ironlake_set_drps(dev, new_delay))
354 dev_priv->cur_delay = new_delay;
f97108d1
JB		 355
356 return;
357}
358
549f7365
CW		 359static void notify_ring(struct drm_device *dev,
360 struct intel_ring_buffer *ring)
361{
362 struct drm_i915_private *dev_priv = dev->dev_private;
475553de 363 u32 seqno;
9862e600 364
475553de
CW		 365 if (ring->obj == NULL)
366 return;
367
368 seqno = ring->get_seqno(ring);
db53a302 369 trace_i915_gem_request_complete(ring, seqno);
9862e600
CW		 370
371 ring->irq_seqno = seqno;
549f7365 372 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 373 if (i915_enable_hangcheck) {
374 dev_priv->hangcheck_count = 0;
375 mod_timer(&dev_priv->hangcheck_timer,
376 jiffies +
377 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
378 }
549f7365
CW		 379}
380
4912d041 381static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 382{
4912d041
BW		 383 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
384 rps_work);
3b8d8d91 385 u8 new_delay = dev_priv->cur_delay;
4912d041
BW		 386 u32 pm_iir, pm_imr;
387
388 spin_lock_irq(&dev_priv->rps_lock);
389 pm_iir = dev_priv->pm_iir;
390 dev_priv->pm_iir = 0;
391 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 392 I915_WRITE(GEN6_PMIMR, 0);
4912d041 393 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 394
3b8d8d91
JB		 395 if (!pm_iir)
396 return;
397
4912d041 398 mutex_lock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 399 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
400 if (dev_priv->cur_delay != dev_priv->max_delay)
401 new_delay = dev_priv->cur_delay + 1;
402 if (new_delay > dev_priv->max_delay)
403 new_delay = dev_priv->max_delay;
404 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
4912d041 405 gen6_gt_force_wake_get(dev_priv);
3b8d8d91
JB		 406 if (dev_priv->cur_delay != dev_priv->min_delay)
407 new_delay = dev_priv->cur_delay - 1;
408 if (new_delay < dev_priv->min_delay) {
409 new_delay = dev_priv->min_delay;
410 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
411 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
412 ((new_delay << 16) & 0x3f0000));
413 } else {
414 /* Make sure we continue to get down interrupts
415 * until we hit the minimum frequency */
416 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
417 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
418 }
4912d041 419 gen6_gt_force_wake_put(dev_priv);
3b8d8d91
JB		 420 }
421
4912d041 422 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91
JB		 423 dev_priv->cur_delay = new_delay;
424
4912d041
BW		 425 /*
426 * rps_lock not held here because clearing is non-destructive. There is
427 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
428 * by holding struct_mutex for the duration of the write.
429 */
4912d041 430 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 431}
432
e7b4c6b1
DV		 433static void snb_gt_irq_handler(struct drm_device *dev,
434 struct drm_i915_private *dev_priv,
435 u32 gt_iir)
436{
437
438 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
439 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
440 notify_ring(dev, &dev_priv->ring[RCS]);
441 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
442 notify_ring(dev, &dev_priv->ring[VCS]);
443 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
444 notify_ring(dev, &dev_priv->ring[BCS]);
445
446 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
447 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
448 GT_RENDER_CS_ERROR_INTERRUPT)) {
449 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
450 i915_handle_error(dev, false);
451 }
452}
453
fc6826d1
CW		 454static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
455 u32 pm_iir)
456{
457 unsigned long flags;
458
459 /*
460 * IIR bits should never already be set because IMR should
461 * prevent an interrupt from being shown in IIR. The warning
462 * displays a case where we've unsafely cleared
463 * dev_priv->pm_iir. Although missing an interrupt of the same
464 * type is not a problem, it displays a problem in the logic.
465 *
466 * The mask bit in IMR is cleared by rps_work.
467 */
468
469 spin_lock_irqsave(&dev_priv->rps_lock, flags);
470 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
471 dev_priv->pm_iir |= pm_iir;
472 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
473 POSTING_READ(GEN6_PMIMR);
474 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
475
476 queue_work(dev_priv->wq, &dev_priv->rps_work);
477}
478
7e231dbe
JB		 479static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
480{
481 struct drm_device *dev = (struct drm_device *) arg;
482 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
483 u32 iir, gt_iir, pm_iir;
484 irqreturn_t ret = IRQ_NONE;
485 unsigned long irqflags;
486 int pipe;
487 u32 pipe_stats[I915_MAX_PIPES];
488 u32 vblank_status;
489 int vblank = 0;
490 bool blc_event;
491
492 atomic_inc(&dev_priv->irq_received);
493
494 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
495 PIPE_VBLANK_INTERRUPT_STATUS;
496
497 while (true) {
498 iir = I915_READ(VLV_IIR);
499 gt_iir = I915_READ(GTIIR);
500 pm_iir = I915_READ(GEN6_PMIIR);
501
502 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
503 goto out;
504
505 ret = IRQ_HANDLED;
506
e7b4c6b1 507 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 508
509 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
510 for_each_pipe(pipe) {
511 int reg = PIPESTAT(pipe);
512 pipe_stats[pipe] = I915_READ(reg);
513
514 /*
515 * Clear the PIPE*STAT regs before the IIR
516 */
517 if (pipe_stats[pipe] & 0x8000ffff) {
518 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
519 DRM_DEBUG_DRIVER("pipe %c underrun\n",
520 pipe_name(pipe));
521 I915_WRITE(reg, pipe_stats[pipe]);
522 }
523 }
524 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
525
526 /* Consume port. Then clear IIR or we'll miss events */
527 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
528 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
529
530 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
531 hotplug_status);
532 if (hotplug_status & dev_priv->hotplug_supported_mask)
533 queue_work(dev_priv->wq,
534 &dev_priv->hotplug_work);
535
536 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
537 I915_READ(PORT_HOTPLUG_STAT);
538 }
539
540
541 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
542 drm_handle_vblank(dev, 0);
543 vblank++;
544 if (!dev_priv->flip_pending_is_done) {
545 intel_finish_page_flip(dev, 0);
546 }
547 }
548
549 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
550 drm_handle_vblank(dev, 1);
551 vblank++;
552 if (!dev_priv->flip_pending_is_done) {
553 intel_finish_page_flip(dev, 0);
554 }
555 }
556
557 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
558 blc_event = true;
559
fc6826d1
CW		 560 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
561 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 562
563 I915_WRITE(GTIIR, gt_iir);
564 I915_WRITE(GEN6_PMIIR, pm_iir);
565 I915_WRITE(VLV_IIR, iir);
566 }
567
568out:
569 return ret;
570}
571
776ad806
JB		 572static void pch_irq_handler(struct drm_device *dev)
573{
574 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
575 u32 pch_iir;
9db4a9c7 576 int pipe;
776ad806
JB		 577
578 pch_iir = I915_READ(SDEIIR);
579
580 if (pch_iir & SDE_AUDIO_POWER_MASK)
581 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
582 (pch_iir & SDE_AUDIO_POWER_MASK) >>
583 SDE_AUDIO_POWER_SHIFT);
584
585 if (pch_iir & SDE_GMBUS)
586 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
587
588 if (pch_iir & SDE_AUDIO_HDCP_MASK)
589 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
590
591 if (pch_iir & SDE_AUDIO_TRANS_MASK)
592 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
593
594 if (pch_iir & SDE_POISON)
595 DRM_ERROR("PCH poison interrupt\n");
596
9db4a9c7
JB		 597 if (pch_iir & SDE_FDI_MASK)
598 for_each_pipe(pipe)
599 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
600 pipe_name(pipe),
601 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 602
603 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
604 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
605
606 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
607 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
608
609 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
610 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
611 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
612 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
613}
614
f71d4af4 615static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 616{
617 struct drm_device *dev = (struct drm_device *) arg;
618 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
619 int ret = IRQ_NONE;
620 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
621 struct drm_i915_master_private *master_priv;
622
623 atomic_inc(&dev_priv->irq_received);
624
625 /* disable master interrupt before clearing iir */
626 de_ier = I915_READ(DEIER);
627 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
628 POSTING_READ(DEIER);
629
630 de_iir = I915_READ(DEIIR);
631 gt_iir = I915_READ(GTIIR);
632 pch_iir = I915_READ(SDEIIR);
633 pm_iir = I915_READ(GEN6_PMIIR);
634
635 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
636 goto done;
637
638 ret = IRQ_HANDLED;
639
640 if (dev->primary->master) {
641 master_priv = dev->primary->master->driver_priv;
642 if (master_priv->sarea_priv)
643 master_priv->sarea_priv->last_dispatch =
644 READ_BREADCRUMB(dev_priv);
645 }
646
e7b4c6b1 647 snb_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 648
649 if (de_iir & DE_GSE_IVB)
650 intel_opregion_gse_intr(dev);
651
652 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
653 intel_prepare_page_flip(dev, 0);
654 intel_finish_page_flip_plane(dev, 0);
655 }
656
657 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
658 intel_prepare_page_flip(dev, 1);
659 intel_finish_page_flip_plane(dev, 1);
660 }
661
662 if (de_iir & DE_PIPEA_VBLANK_IVB)
663 drm_handle_vblank(dev, 0);
664
f6b07f45 665 if (de_iir & DE_PIPEB_VBLANK_IVB)
b1f14ad0
JB		 666 drm_handle_vblank(dev, 1);
667
668 /* check event from PCH */
669 if (de_iir & DE_PCH_EVENT_IVB) {
670 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
671 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
672 pch_irq_handler(dev);
673 }
674
fc6826d1
CW		 675 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
676 gen6_queue_rps_work(dev_priv, pm_iir);
b1f14ad0
JB		 677
678 /* should clear PCH hotplug event before clear CPU irq */
679 I915_WRITE(SDEIIR, pch_iir);
680 I915_WRITE(GTIIR, gt_iir);
681 I915_WRITE(DEIIR, de_iir);
682 I915_WRITE(GEN6_PMIIR, pm_iir);
683
684done:
685 I915_WRITE(DEIER, de_ier);
686 POSTING_READ(DEIER);
687
688 return ret;
689}
690
e7b4c6b1
DV		 691static void ilk_gt_irq_handler(struct drm_device *dev,
692 struct drm_i915_private *dev_priv,
693 u32 gt_iir)
694{
695 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
696 notify_ring(dev, &dev_priv->ring[RCS]);
697 if (gt_iir & GT_BSD_USER_INTERRUPT)
698 notify_ring(dev, &dev_priv->ring[VCS]);
699}
700
f71d4af4 701static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 702{
4697995b 703 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 704 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
705 int ret = IRQ_NONE;
3b8d8d91 706 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 707 u32 hotplug_mask;
036a4a7d 708 struct drm_i915_master_private *master_priv;
881f47b6 709
4697995b
JB		 710 atomic_inc(&dev_priv->irq_received);
711
2d109a84
ZN		 712 /* disable master interrupt before clearing iir */
713 de_ier = I915_READ(DEIER);
714 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 715 POSTING_READ(DEIER);
2d109a84 716
036a4a7d
ZW		 717 de_iir = I915_READ(DEIIR);
718 gt_iir = I915_READ(GTIIR);
c650156a 719 pch_iir = I915_READ(SDEIIR);
3b8d8d91 720 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 721
3b8d8d91
JB		 722 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
723 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 724 goto done;
036a4a7d 725
2d7b8366
YL		 726 if (HAS_PCH_CPT(dev))
727 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
728 else
729 hotplug_mask = SDE_HOTPLUG_MASK;
730
c7c85101 731 ret = IRQ_HANDLED;
036a4a7d 732
c7c85101
ZN		 733 if (dev->primary->master) {
734 master_priv = dev->primary->master->driver_priv;
735 if (master_priv->sarea_priv)
736 master_priv->sarea_priv->last_dispatch =
737 READ_BREADCRUMB(dev_priv);
738 }
036a4a7d 739
e7b4c6b1
DV		 740 if (IS_GEN5(dev))
741 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
742 else
743 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 744
c7c85101 745 if (de_iir & DE_GSE)
3b617967 746 intel_opregion_gse_intr(dev);
c650156a 747
f072d2e7 748 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 749 intel_prepare_page_flip(dev, 0);
2bbda389 750 intel_finish_page_flip_plane(dev, 0);
f072d2e7 751 }
013d5aa2 752
f072d2e7 753 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 754 intel_prepare_page_flip(dev, 1);
2bbda389 755 intel_finish_page_flip_plane(dev, 1);
f072d2e7 756 }
013d5aa2 757
f072d2e7 758 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 759 drm_handle_vblank(dev, 0);
760
f072d2e7 761 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 762 drm_handle_vblank(dev, 1);
763
c7c85101 764 /* check event from PCH */
776ad806
JB		 765 if (de_iir & DE_PCH_EVENT) {
766 if (pch_iir & hotplug_mask)
767 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
768 pch_irq_handler(dev);
769 }
036a4a7d 770
f97108d1 771 if (de_iir & DE_PCU_EVENT) {
7648fa99 772 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 773 i915_handle_rps_change(dev);
774 }
775
fc6826d1
CW		 776 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
777 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 778
c7c85101
ZN		 779 /* should clear PCH hotplug event before clear CPU irq */
780 I915_WRITE(SDEIIR, pch_iir);
781 I915_WRITE(GTIIR, gt_iir);
782 I915_WRITE(DEIIR, de_iir);
4912d041 783 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 784
785done:
2d109a84 786 I915_WRITE(DEIER, de_ier);
3143a2bf 787 POSTING_READ(DEIER);
2d109a84 788
036a4a7d
ZW		 789 return ret;
790}
791
8a905236
JB		 792/**
793 * i915_error_work_func - do process context error handling work
794 * @work: work struct
795 *
796 * Fire an error uevent so userspace can see that a hang or error
797 * was detected.
798 */
799static void i915_error_work_func(struct work_struct *work)
800{
801 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
802 error_work);
803 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 804 char *error_event[] = { "ERROR=1", NULL };
805 char *reset_event[] = { "RESET=1", NULL };
806 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 807
f316a42c
BG		 808 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
809
ba1234d1 810 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 811 DRM_DEBUG_DRIVER("resetting chip\n");
812 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
813 if (!i915_reset(dev, GRDOM_RENDER)) {
814 atomic_set(&dev_priv->mm.wedged, 0);
815 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 816 }
30dbf0c0 817 complete_all(&dev_priv->error_completion);
f316a42c 818 }
8a905236
JB		 819}
820
3bd3c932 821#ifdef CONFIG_DEBUG_FS
9df30794 822static struct drm_i915_error_object *
bcfb2e28 823i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 824 struct drm_i915_gem_object *src)
9df30794
CW		 825{
826 struct drm_i915_error_object *dst;
9df30794 827 int page, page_count;
e56660dd 828 u32 reloc_offset;
9df30794 829
05394f39 830 if (src == NULL || src->pages == NULL)
9df30794
CW		 831 return NULL;
832
05394f39 833 page_count = src->base.size / PAGE_SIZE;
9df30794 834
0206e353 835 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 836 if (dst == NULL)
837 return NULL;
838
05394f39 839 reloc_offset = src->gtt_offset;
9df30794 840 for (page = 0; page < page_count; page++) {
788885ae 841 unsigned long flags;
e56660dd 842 void *d;
788885ae 843
e56660dd 844 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 845 if (d == NULL)
846 goto unwind;
e56660dd 847
788885ae 848 local_irq_save(flags);
74898d7e
DV		 849 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
850 src->has_global_gtt_mapping) {
172975aa
CW		 851 void __iomem *s;
852
853 /* Simply ignore tiling or any overlapping fence.
854 * It's part of the error state, and this hopefully
855 * captures what the GPU read.
856 */
857
858 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
859 reloc_offset);
860 memcpy_fromio(d, s, PAGE_SIZE);
861 io_mapping_unmap_atomic(s);
862 } else {
863 void *s;
864
865 drm_clflush_pages(&src->pages[page], 1);
866
867 s = kmap_atomic(src->pages[page]);
868 memcpy(d, s, PAGE_SIZE);
869 kunmap_atomic(s);
870
871 drm_clflush_pages(&src->pages[page], 1);
872 }
788885ae 873 local_irq_restore(flags);
e56660dd 874
9df30794 875 dst->pages[page] = d;
e56660dd
CW		 876
877 reloc_offset += PAGE_SIZE;
9df30794
CW		 878 }
879 dst->page_count = page_count;
05394f39 880 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 881
882 return dst;
883
884unwind:
885 while (page--)
886 kfree(dst->pages[page]);
887 kfree(dst);
888 return NULL;
889}
890
891static void
892i915_error_object_free(struct drm_i915_error_object *obj)
893{
894 int page;
895
896 if (obj == NULL)
897 return;
898
899 for (page = 0; page < obj->page_count; page++)
900 kfree(obj->pages[page]);
901
902 kfree(obj);
903}
904
905static void
906i915_error_state_free(struct drm_device *dev,
907 struct drm_i915_error_state *error)
908{
e2f973d5
CW		 909 int i;
910
52d39a21
CW		 911 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
912 i915_error_object_free(error->ring[i].batchbuffer);
913 i915_error_object_free(error->ring[i].ringbuffer);
914 kfree(error->ring[i].requests);
915 }
e2f973d5 916
9df30794 917 kfree(error->active_bo);
6ef3d427 918 kfree(error->overlay);
9df30794
CW		 919 kfree(error);
920}
921
c724e8a9
CW		 922static u32 capture_bo_list(struct drm_i915_error_buffer *err,
923 int count,
924 struct list_head *head)
925{
926 struct drm_i915_gem_object *obj;
927 int i = 0;
928
929 list_for_each_entry(obj, head, mm_list) {
930 err->size = obj->base.size;
931 err->name = obj->base.name;
932 err->seqno = obj->last_rendering_seqno;
933 err->gtt_offset = obj->gtt_offset;
934 err->read_domains = obj->base.read_domains;
935 err->write_domain = obj->base.write_domain;
936 err->fence_reg = obj->fence_reg;
937 err->pinned = 0;
938 if (obj->pin_count > 0)
939 err->pinned = 1;
940 if (obj->user_pin_count > 0)
941 err->pinned = -1;
942 err->tiling = obj->tiling_mode;
943 err->dirty = obj->dirty;
944 err->purgeable = obj->madv != I915_MADV_WILLNEED;
96154f2f 945 err->ring = obj->ring ? obj->ring->id : -1;
93dfb40c 946 err->cache_level = obj->cache_level;
c724e8a9
CW		 947
948 if (++i == count)
949 break;
950
951 err++;
952 }
953
954 return i;
955}
956
748ebc60
CW		 957static void i915_gem_record_fences(struct drm_device *dev,
958 struct drm_i915_error_state *error)
959{
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 int i;
962
963 /* Fences */
964 switch (INTEL_INFO(dev)->gen) {
775d17b6 965 case 7:
748ebc60
CW		 966 case 6:
967 for (i = 0; i < 16; i++)
968 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
969 break;
970 case 5:
971 case 4:
972 for (i = 0; i < 16; i++)
973 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
974 break;
975 case 3:
976 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
977 for (i = 0; i < 8; i++)
978 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
979 case 2:
980 for (i = 0; i < 8; i++)
981 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
982 break;
983
984 }
985}
986
bcfb2e28
CW		 987static struct drm_i915_error_object *
988i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
989 struct intel_ring_buffer *ring)
990{
991 struct drm_i915_gem_object *obj;
992 u32 seqno;
993
994 if (!ring->get_seqno)
995 return NULL;
996
997 seqno = ring->get_seqno(ring);
998 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
999 if (obj->ring != ring)
1000 continue;
1001
c37d9a5d 1002 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 1003 continue;
1004
1005 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1006 continue;
1007
1008 /* We need to copy these to an anonymous buffer as the simplest
1009 * method to avoid being overwritten by userspace.
1010 */
1011 return i915_error_object_create(dev_priv, obj);
1012 }
1013
1014 return NULL;
1015}
1016
d27b1e0e
DV		 1017static void i915_record_ring_state(struct drm_device *dev,
1018 struct drm_i915_error_state *error,
1019 struct intel_ring_buffer *ring)
1020{
1021 struct drm_i915_private *dev_priv = dev->dev_private;
1022
33f3f518 1023 if (INTEL_INFO(dev)->gen >= 6) {
33f3f518 1024 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1025 error->semaphore_mboxes[ring->id][0]
1026 = I915_READ(RING_SYNC_0(ring->mmio_base));
1027 error->semaphore_mboxes[ring->id][1]
1028 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1029 }
c1cd90ed 1030
d27b1e0e 1031 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1032 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1033 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1034 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1035 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1036 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 1037 if (ring->id == RCS) {
d27b1e0e
DV		 1038 error->instdone1 = I915_READ(INSTDONE1);
1039 error->bbaddr = I915_READ64(BB_ADDR);
1040 }
1041 } else {
9d2f41fa 1042 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1043 error->ipeir[ring->id] = I915_READ(IPEIR);
1044 error->ipehr[ring->id] = I915_READ(IPEHR);
1045 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1046 }
1047
c1cd90ed 1048 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 1049 error->seqno[ring->id] = ring->get_seqno(ring);
1050 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1051 error->head[ring->id] = I915_READ_HEAD(ring);
1052 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1053
1054 error->cpu_ring_head[ring->id] = ring->head;
1055 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1056}
1057
52d39a21
CW		 1058static void i915_gem_record_rings(struct drm_device *dev,
1059 struct drm_i915_error_state *error)
1060{
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1062 struct drm_i915_gem_request *request;
1063 int i, count;
1064
1065 for (i = 0; i < I915_NUM_RINGS; i++) {
1066 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1067
1068 if (ring->obj == NULL)
1069 continue;
1070
1071 i915_record_ring_state(dev, error, ring);
1072
1073 error->ring[i].batchbuffer =
1074 i915_error_first_batchbuffer(dev_priv, ring);
1075
1076 error->ring[i].ringbuffer =
1077 i915_error_object_create(dev_priv, ring->obj);
1078
1079 count = 0;
1080 list_for_each_entry(request, &ring->request_list, list)
1081 count++;
1082
1083 error->ring[i].num_requests = count;
1084 error->ring[i].requests =
1085 kmalloc(count*sizeof(struct drm_i915_error_request),
1086 GFP_ATOMIC);
1087 if (error->ring[i].requests == NULL) {
1088 error->ring[i].num_requests = 0;
1089 continue;
1090 }
1091
1092 count = 0;
1093 list_for_each_entry(request, &ring->request_list, list) {
1094 struct drm_i915_error_request *erq;
1095
1096 erq = &error->ring[i].requests[count++];
1097 erq->seqno = request->seqno;
1098 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1099 erq->tail = request->tail;
52d39a21
CW		 1100 }
1101 }
1102}
1103
8a905236
JB		 1104/**
1105 * i915_capture_error_state - capture an error record for later analysis
1106 * @dev: drm device
1107 *
1108 * Should be called when an error is detected (either a hang or an error
1109 * interrupt) to capture error state from the time of the error. Fills
1110 * out a structure which becomes available in debugfs for user level tools
1111 * to pick up.
1112 */
63eeaf38
JB		 1113static void i915_capture_error_state(struct drm_device *dev)
1114{
1115 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1116 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1117 struct drm_i915_error_state *error;
1118 unsigned long flags;
9db4a9c7 1119 int i, pipe;
63eeaf38
JB		 1120
1121 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1122 error = dev_priv->first_error;
1123 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1124 if (error)
1125 return;
63eeaf38 1126
9db4a9c7 1127 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1128 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1129 if (!error) {
9df30794
CW		 1130 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1131 return;
63eeaf38
JB		 1132 }
1133
b6f7833b
CW		 1134 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1135 dev->primary->index);
2fa772f3 1136
63eeaf38
JB		 1137 error->eir = I915_READ(EIR);
1138 error->pgtbl_er = I915_READ(PGTBL_ER);
9db4a9c7
JB		 1139 for_each_pipe(pipe)
1140 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1141
33f3f518 1142 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1143 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1144 error->done_reg = I915_READ(DONE_REG);
1145 }
d27b1e0e 1146
748ebc60 1147 i915_gem_record_fences(dev, error);
52d39a21 1148 i915_gem_record_rings(dev, error);
9df30794 1149
c724e8a9 1150 /* Record buffers on the active and pinned lists. */
9df30794 1151 error->active_bo = NULL;
c724e8a9 1152 error->pinned_bo = NULL;
9df30794 1153
bcfb2e28
CW		 1154 i = 0;
1155 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1156 i++;
1157 error->active_bo_count = i;
05394f39 1158 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
bcfb2e28
CW		 1159 i++;
1160 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1161
8e934dbf
CW		 1162 error->active_bo = NULL;
1163 error->pinned_bo = NULL;
bcfb2e28
CW		 1164 if (i) {
1165 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1166 GFP_ATOMIC);
c724e8a9
CW		 1167 if (error->active_bo)
1168 error->pinned_bo =
1169 error->active_bo + error->active_bo_count;
9df30794
CW		 1170 }
1171
c724e8a9
CW		 1172 if (error->active_bo)
1173 error->active_bo_count =
1174 capture_bo_list(error->active_bo,
1175 error->active_bo_count,
1176 &dev_priv->mm.active_list);
1177
1178 if (error->pinned_bo)
1179 error->pinned_bo_count =
1180 capture_bo_list(error->pinned_bo,
1181 error->pinned_bo_count,
1182 &dev_priv->mm.pinned_list);
1183
9df30794
CW		 1184 do_gettimeofday(&error->time);
1185
6ef3d427 1186 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1187 error->display = intel_display_capture_error_state(dev);
6ef3d427 1188
9df30794
CW		 1189 spin_lock_irqsave(&dev_priv->error_lock, flags);
1190 if (dev_priv->first_error == NULL) {
1191 dev_priv->first_error = error;
1192 error = NULL;
1193 }
63eeaf38 1194 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1195
1196 if (error)
1197 i915_error_state_free(dev, error);
1198}
1199
1200void i915_destroy_error_state(struct drm_device *dev)
1201{
1202 struct drm_i915_private *dev_priv = dev->dev_private;
1203 struct drm_i915_error_state *error;
6dc0e816 1204 unsigned long flags;
9df30794 1205
6dc0e816 1206 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1207 error = dev_priv->first_error;
1208 dev_priv->first_error = NULL;
6dc0e816 1209 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1210
1211 if (error)
1212 i915_error_state_free(dev, error);
63eeaf38 1213}
3bd3c932
CW		 1214#else
1215#define i915_capture_error_state(x)
1216#endif
63eeaf38 1217
35aed2e6 1218static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1219{
1220 struct drm_i915_private *dev_priv = dev->dev_private;
1221 u32 eir = I915_READ(EIR);
9db4a9c7 1222 int pipe;
8a905236 1223
35aed2e6
CW		 1224 if (!eir)
1225 return;
8a905236 1226
a70491cc 1227 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1228
1229 if (IS_G4X(dev)) {
1230 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1231 u32 ipeir = I915_READ(IPEIR_I965);
1232
a70491cc
JP		 1233 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1234 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1235 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1236 I915_READ(INSTDONE_I965));
a70491cc
JP		 1237 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1238 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1239 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1240 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1241 POSTING_READ(IPEIR_I965);
8a905236
JB		 1242 }
1243 if (eir & GM45_ERROR_PAGE_TABLE) {
1244 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1245 pr_err("page table error\n");
1246 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1247 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1248 POSTING_READ(PGTBL_ER);
8a905236
JB		 1249 }
1250 }
1251
a6c45cf0 1252 if (!IS_GEN2(dev)) {
8a905236
JB		 1253 if (eir & I915_ERROR_PAGE_TABLE) {
1254 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1255 pr_err("page table error\n");
1256 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1257 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1258 POSTING_READ(PGTBL_ER);
8a905236
JB		 1259 }
1260 }
1261
1262 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1263 pr_err("memory refresh error:\n");
9db4a9c7 1264 for_each_pipe(pipe)
a70491cc 1265 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1266 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1267 /* pipestat has already been acked */
1268 }
1269 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1270 pr_err("instruction error\n");
1271 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1272 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1273 u32 ipeir = I915_READ(IPEIR);
1274
a70491cc
JP		 1275 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1276 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1277 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1278 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1279 I915_WRITE(IPEIR, ipeir);
3143a2bf 1280 POSTING_READ(IPEIR);
8a905236
JB		 1281 } else {
1282 u32 ipeir = I915_READ(IPEIR_I965);
1283
a70491cc
JP		 1284 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1285 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1286 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1287 I915_READ(INSTDONE_I965));
a70491cc
JP		 1288 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1289 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1290 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1291 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1292 POSTING_READ(IPEIR_I965);
8a905236
JB		 1293 }
1294 }
1295
1296 I915_WRITE(EIR, eir);
3143a2bf 1297 POSTING_READ(EIR);
8a905236
JB		 1298 eir = I915_READ(EIR);
1299 if (eir) {
1300 /*
1301 * some errors might have become stuck,
1302 * mask them.
1303 */
1304 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1305 I915_WRITE(EMR, I915_READ(EMR) | eir);
1306 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1307 }
35aed2e6
CW		 1308}
1309
1310/**
1311 * i915_handle_error - handle an error interrupt
1312 * @dev: drm device
1313 *
1314 * Do some basic checking of regsiter state at error interrupt time and
1315 * dump it to the syslog. Also call i915_capture_error_state() to make
1316 * sure we get a record and make it available in debugfs. Fire a uevent
1317 * so userspace knows something bad happened (should trigger collection
1318 * of a ring dump etc.).
1319 */
527f9e90 1320void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1321{
1322 struct drm_i915_private *dev_priv = dev->dev_private;
1323
1324 i915_capture_error_state(dev);
1325 i915_report_and_clear_eir(dev);
8a905236 1326
ba1234d1 1327 if (wedged) {
30dbf0c0 1328 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1329 atomic_set(&dev_priv->mm.wedged, 1);
1330
11ed50ec
BG		 1331 /*
1332 * Wakeup waiting processes so they don't hang
1333 */
1ec14ad3 1334 wake_up_all(&dev_priv->ring[RCS].irq_queue);
f787a5f5 1335 if (HAS_BSD(dev))
1ec14ad3 1336 wake_up_all(&dev_priv->ring[VCS].irq_queue);
549f7365 1337 if (HAS_BLT(dev))
1ec14ad3 1338 wake_up_all(&dev_priv->ring[BCS].irq_queue);
11ed50ec
BG		 1339 }
1340
9c9fe1f8 1341 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1342}
1343
4e5359cd
SF		 1344static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1345{
1346 drm_i915_private_t *dev_priv = dev->dev_private;
1347 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1349 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1350 struct intel_unpin_work *work;
1351 unsigned long flags;
1352 bool stall_detected;
1353
1354 /* Ignore early vblank irqs */
1355 if (intel_crtc == NULL)
1356 return;
1357
1358 spin_lock_irqsave(&dev->event_lock, flags);
1359 work = intel_crtc->unpin_work;
1360
1361 if (work == NULL || work->pending || !work->enable_stall_check) {
1362 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1363 spin_unlock_irqrestore(&dev->event_lock, flags);
1364 return;
1365 }
1366
1367 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1368 obj = work->pending_flip_obj;
a6c45cf0 1369 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1370 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1371 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1372 obj->gtt_offset;
4e5359cd 1373 } else {
9db4a9c7 1374 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1375 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1376 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1377 crtc->x * crtc->fb->bits_per_pixel/8);
1378 }
1379
1380 spin_unlock_irqrestore(&dev->event_lock, flags);
1381
1382 if (stall_detected) {
1383 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1384 intel_prepare_page_flip(dev, intel_crtc->plane);
1385 }
1386}
1387
f71d4af4 1388static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1da177e4 1389{
84b1fd10 1390 struct drm_device *dev = (struct drm_device *) arg;
1da177e4 1391 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 1392 struct drm_i915_master_private *master_priv;
cdfbc41f 1393 u32 iir, new_iir;
9db4a9c7 1394 u32 pipe_stats[I915_MAX_PIPES];
05eff845 1395 u32 vblank_status;
0a3e67a4 1396 int vblank = 0;
7c463586 1397 unsigned long irqflags;
05eff845 1398 int irq_received;
9db4a9c7
JB		 1399 int ret = IRQ_NONE, pipe;
1400 bool blc_event = false;
6e5fca53 1401
630681d9
EA		 1402 atomic_inc(&dev_priv->irq_received);
1403
ed4cb414 1404 iir = I915_READ(IIR);
a6b54f3f 1405
a6c45cf0 1406 if (INTEL_INFO(dev)->gen >= 4)
d874bcff 1407 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
e25e6601 1408 else
d874bcff 1409 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
af6061af 1410
05eff845
KP		 1411 for (;;) {
1412 irq_received = iir != 0;
1413
1414 /* Can't rely on pipestat interrupt bit in iir as it might
1415 * have been cleared after the pipestat interrupt was received.
1416 * It doesn't set the bit in iir again, but it still produces
1417 * interrupts (for non-MSI).
1418 */
1ec14ad3 1419 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8a905236 1420 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
ba1234d1 1421 i915_handle_error(dev, false);
8a905236 1422
9db4a9c7
JB		 1423 for_each_pipe(pipe) {
1424 int reg = PIPESTAT(pipe);
1425 pipe_stats[pipe] = I915_READ(reg);
1426
1427 /*
1428 * Clear the PIPE*STAT regs before the IIR
1429 */
1430 if (pipe_stats[pipe] & 0x8000ffff) {
1431 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1432 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1433 pipe_name(pipe));
1434 I915_WRITE(reg, pipe_stats[pipe]);
1435 irq_received = 1;
1436 }
cdfbc41f 1437 }
1ec14ad3 1438 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
05eff845
KP		 1439
1440 if (!irq_received)
1441 break;
1442
1443 ret = IRQ_HANDLED;
8ee1c3db 1444
5ca58282
JB		 1445 /* Consume port. Then clear IIR or we'll miss events */
1446 if ((I915_HAS_HOTPLUG(dev)) &&
1447 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1448 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1449
44d98a61 1450 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
5ca58282
JB		 1451 hotplug_status);
1452 if (hotplug_status & dev_priv->hotplug_supported_mask)
9c9fe1f8
EA		 1453 queue_work(dev_priv->wq,
1454 &dev_priv->hotplug_work);
5ca58282
JB		 1455
1456 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1457 I915_READ(PORT_HOTPLUG_STAT);
1458 }
1459
cdfbc41f
EA		 1460 I915_WRITE(IIR, iir);
1461 new_iir = I915_READ(IIR); /* Flush posted writes */
7c463586 1462
7c1c2871
DA		 1463 if (dev->primary->master) {
1464 master_priv = dev->primary->master->driver_priv;
1465 if (master_priv->sarea_priv)
1466 master_priv->sarea_priv->last_dispatch =
1467 READ_BREADCRUMB(dev_priv);
1468 }
0a3e67a4 1469
549f7365 1470 if (iir & I915_USER_INTERRUPT)
1ec14ad3
CW		 1471 notify_ring(dev, &dev_priv->ring[RCS]);
1472 if (iir & I915_BSD_USER_INTERRUPT)
1473 notify_ring(dev, &dev_priv->ring[VCS]);
d1b851fc 1474
1afe3e9d 1475 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
6b95a207 1476 intel_prepare_page_flip(dev, 0);
1afe3e9d
JB		 1477 if (dev_priv->flip_pending_is_done)
1478 intel_finish_page_flip_plane(dev, 0);
1479 }
6b95a207 1480
1afe3e9d 1481 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
70565d00 1482 intel_prepare_page_flip(dev, 1);
1afe3e9d
JB		 1483 if (dev_priv->flip_pending_is_done)
1484 intel_finish_page_flip_plane(dev, 1);
1afe3e9d 1485 }
6b95a207 1486
9db4a9c7
JB		 1487 for_each_pipe(pipe) {
1488 if (pipe_stats[pipe] & vblank_status &&
1489 drm_handle_vblank(dev, pipe)) {
1490 vblank++;
1491 if (!dev_priv->flip_pending_is_done) {
1492 i915_pageflip_stall_check(dev, pipe);
1493 intel_finish_page_flip(dev, pipe);
1494 }
4e5359cd 1495 }
7c463586 1496
9db4a9c7
JB		 1497 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1498 blc_event = true;
cdfbc41f 1499 }
7c463586 1500
9db4a9c7
JB		 1501
1502 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3b617967 1503 intel_opregion_asle_intr(dev);
cdfbc41f
EA		 1504
1505 /* With MSI, interrupts are only generated when iir
1506 * transitions from zero to nonzero. If another bit got
1507 * set while we were handling the existing iir bits, then
1508 * we would never get another interrupt.
1509 *
1510 * This is fine on non-MSI as well, as if we hit this path
1511 * we avoid exiting the interrupt handler only to generate
1512 * another one.
1513 *
1514 * Note that for MSI this could cause a stray interrupt report
1515 * if an interrupt landed in the time between writing IIR and
1516 * the posting read. This should be rare enough to never
1517 * trigger the 99% of 100,000 interrupts test for disabling
1518 * stray interrupts.
1519 */
1520 iir = new_iir;
05eff845 1521 }
0a3e67a4 1522
05eff845 1523 return ret;
1da177e4
LT		 1524}
1525
af6061af 1526static int i915_emit_irq(struct drm_device * dev)
1da177e4
LT		 1527{
1528 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 1529 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4
LT		 1530
1531 i915_kernel_lost_context(dev);
1532
44d98a61 1533 DRM_DEBUG_DRIVER("\n");
1da177e4 1534
c99b058f 1535 dev_priv->counter++;
c29b669c 1536 if (dev_priv->counter > 0x7FFFFFFFUL)
c99b058f 1537 dev_priv->counter = 1;
7c1c2871
DA		 1538 if (master_priv->sarea_priv)
1539 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
c29b669c 1540
e1f99ce6
CW		 1541 if (BEGIN_LP_RING(4) == 0) {
1542 OUT_RING(MI_STORE_DWORD_INDEX);
1543 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1544 OUT_RING(dev_priv->counter);
1545 OUT_RING(MI_USER_INTERRUPT);
1546 ADVANCE_LP_RING();
1547 }
bc5f4523 1548
c29b669c 1549 return dev_priv->counter;
1da177e4
LT		 1550}
1551
84b1fd10 1552static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1da177e4
LT		 1553{
1554 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 1555 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 1556 int ret = 0;
1ec14ad3 1557 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1da177e4 1558
44d98a61 1559 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1da177e4
LT		 1560 READ_BREADCRUMB(dev_priv));
1561
ed4cb414 1562 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
7c1c2871
DA		 1563 if (master_priv->sarea_priv)
1564 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1da177e4 1565 return 0;
ed4cb414 1566 }
1da177e4 1567
7c1c2871
DA		 1568 if (master_priv->sarea_priv)
1569 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1da177e4 1570
b13c2b96
CW		 1571 if (ring->irq_get(ring)) {
1572 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1573 READ_BREADCRUMB(dev_priv) >= irq_nr);
1574 ring->irq_put(ring);
5a9a8d1a
CW		 1575 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1576 ret = -EBUSY;
1da177e4 1577
20caafa6 1578 if (ret == -EBUSY) {
3e684eae 1579 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1da177e4
LT		 1580 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1581 }
1582
af6061af
DA		 1583 return ret;
1584}
1585
1da177e4
LT		 1586/* Needs the lock as it touches the ring.
1587 */
c153f45f
EA		 1588int i915_irq_emit(struct drm_device *dev, void *data,
1589 struct drm_file *file_priv)
1da177e4 1590{
1da177e4 1591 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1592 drm_i915_irq_emit_t *emit = data;
1da177e4
LT		 1593 int result;
1594
1ec14ad3 1595 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
3e684eae 1596 DRM_ERROR("called with no initialization\n");
20caafa6 1597 return -EINVAL;
1da177e4 1598 }
299eb93c
EA		 1599
1600 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1601
546b0974 1602 mutex_lock(&dev->struct_mutex);
1da177e4 1603 result = i915_emit_irq(dev);
546b0974 1604 mutex_unlock(&dev->struct_mutex);
1da177e4 1605
c153f45f 1606 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1da177e4 1607 DRM_ERROR("copy_to_user\n");
20caafa6 1608 return -EFAULT;
1da177e4
LT		 1609 }
1610
1611 return 0;
1612}
1613
1614/* Doesn't need the hardware lock.
1615 */
c153f45f
EA		 1616int i915_irq_wait(struct drm_device *dev, void *data,
1617 struct drm_file *file_priv)
1da177e4 1618{
1da177e4 1619 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1620 drm_i915_irq_wait_t *irqwait = data;
1da177e4
LT		 1621
1622 if (!dev_priv) {
3e684eae 1623 DRM_ERROR("called with no initialization\n");
20caafa6 1624 return -EINVAL;
1da177e4
LT		 1625 }
1626
c153f45f 1627 return i915_wait_irq(dev, irqwait->irq_seq);
1da177e4
LT		 1628}
1629
42f52ef8
KP		 1630/* Called from drm generic code, passed 'crtc' which
1631 * we use as a pipe index
1632 */
f71d4af4 1633static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1634{
1635 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1636 unsigned long irqflags;
71e0ffa5 1637
5eddb70b 1638 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1639 return -EINVAL;
0a3e67a4 1640
1ec14ad3 1641 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1642 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1643 i915_enable_pipestat(dev_priv, pipe,
1644 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1645 else
7c463586
KP		 1646 i915_enable_pipestat(dev_priv, pipe,
1647 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1648
1649 /* maintain vblank delivery even in deep C-states */
1650 if (dev_priv->info->gen == 3)
1651 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1ec14ad3 1652 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1653
0a3e67a4
JB		 1654 return 0;
1655}
1656
f71d4af4 1657static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1658{
1659 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1660 unsigned long irqflags;
1661
1662 if (!i915_pipe_enabled(dev, pipe))
1663 return -EINVAL;
1664
1665 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1666 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1667 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1668 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1669
1670 return 0;
1671}
1672
f71d4af4 1673static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1674{
1675 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1676 unsigned long irqflags;
1677
1678 if (!i915_pipe_enabled(dev, pipe))
1679 return -EINVAL;
1680
1681 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1682 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1683 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1684 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1685
1686 return 0;
1687}
1688
7e231dbe
JB		 1689static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1690{
1691 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1692 unsigned long irqflags;
1693 u32 dpfl, imr;
1694
1695 if (!i915_pipe_enabled(dev, pipe))
1696 return -EINVAL;
1697
1698 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1699 dpfl = I915_READ(VLV_DPFLIPSTAT);
1700 imr = I915_READ(VLV_IMR);
1701 if (pipe == 0) {
1702 dpfl |= PIPEA_VBLANK_INT_EN;
1703 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1704 } else {
1705 dpfl |= PIPEA_VBLANK_INT_EN;
1706 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1707 }
1708 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1709 I915_WRITE(VLV_IMR, imr);
1710 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1711
1712 return 0;
1713}
1714
42f52ef8
KP		 1715/* Called from drm generic code, passed 'crtc' which
1716 * we use as a pipe index
1717 */
f71d4af4 1718static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1719{
1720 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1721 unsigned long irqflags;
0a3e67a4 1722
1ec14ad3 1723 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e
CW		 1724 if (dev_priv->info->gen == 3)
1725 I915_WRITE(INSTPM,
1726 INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1727
f796cf8f
JB		 1728 i915_disable_pipestat(dev_priv, pipe,
1729 PIPE_VBLANK_INTERRUPT_ENABLE |
1730 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1731 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1732}
1733
f71d4af4 1734static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1735{
1736 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1737 unsigned long irqflags;
1738
1739 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1740 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1741 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1742 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1743}
1744
f71d4af4 1745static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1746{
1747 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1748 unsigned long irqflags;
1749
1750 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1751 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1752 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1753 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1754}
1755
7e231dbe
JB		 1756static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1757{
1758 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1759 unsigned long irqflags;
1760 u32 dpfl, imr;
1761
1762 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1763 dpfl = I915_READ(VLV_DPFLIPSTAT);
1764 imr = I915_READ(VLV_IMR);
1765 if (pipe == 0) {
1766 dpfl &= ~PIPEA_VBLANK_INT_EN;
1767 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1768 } else {
1769 dpfl &= ~PIPEB_VBLANK_INT_EN;
1770 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1771 }
1772 I915_WRITE(VLV_IMR, imr);
1773 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1774 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1775}
1776
1777
702880f2
DA		 1778/* Set the vblank monitor pipe
1779 */
c153f45f
EA		 1780int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1781 struct drm_file *file_priv)
702880f2 1782{
702880f2 1783 drm_i915_private_t *dev_priv = dev->dev_private;
702880f2
DA		 1784
1785 if (!dev_priv) {
3e684eae 1786 DRM_ERROR("called with no initialization\n");
20caafa6 1787 return -EINVAL;
702880f2
DA		 1788 }
1789
5b51694a 1790 return 0;
702880f2
DA		 1791}
1792
c153f45f
EA		 1793int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1794 struct drm_file *file_priv)
702880f2 1795{
702880f2 1796 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1797 drm_i915_vblank_pipe_t *pipe = data;
702880f2
DA		 1798
1799 if (!dev_priv) {
3e684eae 1800 DRM_ERROR("called with no initialization\n");
20caafa6 1801 return -EINVAL;
702880f2
DA		 1802 }
1803
0a3e67a4 1804 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
c153f45f 1805
702880f2
DA		 1806 return 0;
1807}
1808
a6b54f3f
MCA		 1809/**
1810 * Schedule buffer swap at given vertical blank.
1811 */
c153f45f
EA		 1812int i915_vblank_swap(struct drm_device *dev, void *data,
1813 struct drm_file *file_priv)
a6b54f3f 1814{
bd95e0a4
EA		 1815 /* The delayed swap mechanism was fundamentally racy, and has been
1816 * removed. The model was that the client requested a delayed flip/swap
1817 * from the kernel, then waited for vblank before continuing to perform
1818 * rendering. The problem was that the kernel might wake the client
1819 * up before it dispatched the vblank swap (since the lock has to be
1820 * held while touching the ringbuffer), in which case the client would
1821 * clear and start the next frame before the swap occurred, and
1822 * flicker would occur in addition to likely missing the vblank.
1823 *
1824 * In the absence of this ioctl, userland falls back to a correct path
1825 * of waiting for a vblank, then dispatching the swap on its own.
1826 * Context switching to userland and back is plenty fast enough for
1827 * meeting the requirements of vblank swapping.
0a3e67a4 1828 */
bd95e0a4 1829 return -EINVAL;
a6b54f3f
MCA		 1830}
1831
893eead0
CW		 1832static u32
1833ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1834{
893eead0
CW		 1835 return list_entry(ring->request_list.prev,
1836 struct drm_i915_gem_request, list)->seqno;
1837}
1838
1839static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1840{
1841 if (list_empty(&ring->request_list) ||
1842 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1843 /* Issue a wake-up to catch stuck h/w. */
b2223497 1844 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
893eead0
CW		 1845 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1846 ring->name,
b2223497 1847 ring->waiting_seqno,
893eead0
CW		 1848 ring->get_seqno(ring));
1849 wake_up_all(&ring->irq_queue);
1850 *err = true;
1851 }
1852 return true;
1853 }
1854 return false;
f65d9421
BG		 1855}
1856
1ec14ad3
CW		 1857static bool kick_ring(struct intel_ring_buffer *ring)
1858{
1859 struct drm_device *dev = ring->dev;
1860 struct drm_i915_private *dev_priv = dev->dev_private;
1861 u32 tmp = I915_READ_CTL(ring);
1862 if (tmp & RING_WAIT) {
1863 DRM_ERROR("Kicking stuck wait on %s\n",
1864 ring->name);
1865 I915_WRITE_CTL(ring, tmp);
1866 return true;
1867 }
1ec14ad3
CW		 1868 return false;
1869}
1870
d1e61e7f
CW		 1871static bool i915_hangcheck_hung(struct drm_device *dev)
1872{
1873 drm_i915_private_t *dev_priv = dev->dev_private;
1874
1875 if (dev_priv->hangcheck_count++ > 1) {
1876 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1877 i915_handle_error(dev, true);
1878
1879 if (!IS_GEN2(dev)) {
1880 /* Is the chip hanging on a WAIT_FOR_EVENT?
1881 * If so we can simply poke the RB_WAIT bit
1882 * and break the hang. This should work on
1883 * all but the second generation chipsets.
1884 */
1885 if (kick_ring(&dev_priv->ring[RCS]))
1886 return false;
1887
1888 if (HAS_BSD(dev) && kick_ring(&dev_priv->ring[VCS]))
1889 return false;
1890
1891 if (HAS_BLT(dev) && kick_ring(&dev_priv->ring[BCS]))
1892 return false;
1893 }
1894
1895 return true;
1896 }
1897
1898 return false;
1899}
1900
f65d9421
BG		 1901/**
1902 * This is called when the chip hasn't reported back with completed
1903 * batchbuffers in a long time. The first time this is called we simply record
1904 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1905 * again, we assume the chip is wedged and try to fix it.
1906 */
1907void i915_hangcheck_elapsed(unsigned long data)
1908{
1909 struct drm_device *dev = (struct drm_device *)data;
1910 drm_i915_private_t *dev_priv = dev->dev_private;
097354eb 1911 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
893eead0
CW		 1912 bool err = false;
1913
3e0dc6b0
BW		 1914 if (!i915_enable_hangcheck)
1915 return;
1916
893eead0 1917 /* If all work is done then ACTHD clearly hasn't advanced. */
1ec14ad3
CW		 1918 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1919 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1920 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
d1e61e7f
CW		 1921 if (err) {
1922 if (i915_hangcheck_hung(dev))
1923 return;
1924
893eead0 1925 goto repeat;
d1e61e7f
CW		 1926 }
1927
1928 dev_priv->hangcheck_count = 0;
893eead0
CW		 1929 return;
1930 }
b9201c14 1931
a6c45cf0 1932 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1933 instdone = I915_READ(INSTDONE);
1934 instdone1 = 0;
1935 } else {
cbb465e7
CW		 1936 instdone = I915_READ(INSTDONE_I965);
1937 instdone1 = I915_READ(INSTDONE1);
1938 }
097354eb
DV		 1939 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1940 acthd_bsd = HAS_BSD(dev) ?
1941 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1942 acthd_blt = HAS_BLT(dev) ?
1943 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
f65d9421 1944
cbb465e7 1945 if (dev_priv->last_acthd == acthd &&
097354eb
DV		 1946 dev_priv->last_acthd_bsd == acthd_bsd &&
1947 dev_priv->last_acthd_blt == acthd_blt &&
cbb465e7
CW		 1948 dev_priv->last_instdone == instdone &&
1949 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1950 if (i915_hangcheck_hung(dev))
cbb465e7 1951 return;
cbb465e7
CW		 1952 } else {
1953 dev_priv->hangcheck_count = 0;
1954
1955 dev_priv->last_acthd = acthd;
097354eb
DV		 1956 dev_priv->last_acthd_bsd = acthd_bsd;
1957 dev_priv->last_acthd_blt = acthd_blt;
cbb465e7
CW		 1958 dev_priv->last_instdone = instdone;
1959 dev_priv->last_instdone1 = instdone1;
1960 }
f65d9421 1961
893eead0 1962repeat:
f65d9421 1963 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1964 mod_timer(&dev_priv->hangcheck_timer,
1965 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1966}
1967
1da177e4
LT		 1968/* drm_dma.h hooks
1969*/
f71d4af4 1970static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1971{
1972 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1973
4697995b
JB		 1974 atomic_set(&dev_priv->irq_received, 0);
1975
1976 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1977 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
9e3c256d
JB		 1978 if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1979 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
4697995b 1980
036a4a7d 1981 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1982
036a4a7d
ZW		 1983 /* XXX hotplug from PCH */
1984
1985 I915_WRITE(DEIMR, 0xffffffff);
1986 I915_WRITE(DEIER, 0x0);
3143a2bf 1987 POSTING_READ(DEIER);
036a4a7d
ZW		 1988
1989 /* and GT */
1990 I915_WRITE(GTIMR, 0xffffffff);
1991 I915_WRITE(GTIER, 0x0);
3143a2bf 1992 POSTING_READ(GTIER);
c650156a
ZW		 1993
1994 /* south display irq */
1995 I915_WRITE(SDEIMR, 0xffffffff);
1996 I915_WRITE(SDEIER, 0x0);
3143a2bf 1997 POSTING_READ(SDEIER);
036a4a7d
ZW		 1998}
1999
7e231dbe
JB		 2000static void valleyview_irq_preinstall(struct drm_device *dev)
2001{
2002 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2003 int pipe;
2004
2005 atomic_set(&dev_priv->irq_received, 0);
2006
2007 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2008 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2009
2010 /* VLV magic */
2011 I915_WRITE(VLV_IMR, 0);
2012 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2013 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2014 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2015
7e231dbe
JB		 2016 /* and GT */
2017 I915_WRITE(GTIIR, I915_READ(GTIIR));
2018 I915_WRITE(GTIIR, I915_READ(GTIIR));
2019 I915_WRITE(GTIMR, 0xffffffff);
2020 I915_WRITE(GTIER, 0x0);
2021 POSTING_READ(GTIER);
2022
2023 I915_WRITE(DPINVGTT, 0xff);
2024
2025 I915_WRITE(PORT_HOTPLUG_EN, 0);
2026 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2027 for_each_pipe(pipe)
2028 I915_WRITE(PIPESTAT(pipe), 0xffff);
2029 I915_WRITE(VLV_IIR, 0xffffffff);
2030 I915_WRITE(VLV_IMR, 0xffffffff);
2031 I915_WRITE(VLV_IER, 0x0);
2032 POSTING_READ(VLV_IER);
2033}
2034
7fe0b973
KP		 2035/*
2036 * Enable digital hotplug on the PCH, and configure the DP short pulse
2037 * duration to 2ms (which is the minimum in the Display Port spec)
2038 *
2039 * This register is the same on all known PCH chips.
2040 */
2041
2042static void ironlake_enable_pch_hotplug(struct drm_device *dev)
2043{
2044 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2045 u32 hotplug;
2046
2047 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2048 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2049 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2050 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2051 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2052 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2053}
2054
f71d4af4 2055static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 2056{
2057 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2058 /* enable kind of interrupts always enabled */
013d5aa2
JB		 2059 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2060 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 2061 u32 render_irqs;
2d7b8366 2062 u32 hotplug_mask;
036a4a7d 2063
4697995b
JB		 2064 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
2065 if (HAS_BSD(dev))
2066 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
2067 if (HAS_BLT(dev))
2068 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
2069
2070 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1ec14ad3 2071 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2072
2073 /* should always can generate irq */
2074 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 2075 I915_WRITE(DEIMR, dev_priv->irq_mask);
2076 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 2077 POSTING_READ(DEIER);
036a4a7d 2078
1ec14ad3 2079 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 2080
2081 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 2082 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 2083
1ec14ad3
CW		 2084 if (IS_GEN6(dev))
2085 render_irqs =
2086 GT_USER_INTERRUPT |
e2a1e2f0
BW		 2087 GEN6_BSD_USER_INTERRUPT |
2088 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 2089 else
2090 render_irqs =
88f23b8f 2091 GT_USER_INTERRUPT |
c6df541c 2092 GT_PIPE_NOTIFY |
1ec14ad3
CW		 2093 GT_BSD_USER_INTERRUPT;
2094 I915_WRITE(GTIER, render_irqs);
3143a2bf 2095 POSTING_READ(GTIER);
036a4a7d 2096
2d7b8366 2097 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 2098 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
2099 SDE_PORTB_HOTPLUG_CPT |
2100 SDE_PORTC_HOTPLUG_CPT |
2101 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 2102 } else {
9035a97a
CW		 2103 hotplug_mask = (SDE_CRT_HOTPLUG |
2104 SDE_PORTB_HOTPLUG |
2105 SDE_PORTC_HOTPLUG |
2106 SDE_PORTD_HOTPLUG |
2107 SDE_AUX_MASK);
2d7b8366
YL		 2108 }
2109
1ec14ad3 2110 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 2111
2112 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 2113 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
2114 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 2115 POSTING_READ(SDEIER);
c650156a 2116
7fe0b973
KP		 2117 ironlake_enable_pch_hotplug(dev);
2118
f97108d1
JB		 2119 if (IS_IRONLAKE_M(dev)) {
2120 /* Clear & enable PCU event interrupts */
2121 I915_WRITE(DEIIR, DE_PCU_EVENT);
2122 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2123 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2124 }
2125
036a4a7d
ZW		 2126 return 0;
2127}
2128
f71d4af4 2129static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2130{
2131 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2132 /* enable kind of interrupts always enabled */
2133 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2134 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
2135 DE_PLANEB_FLIP_DONE_IVB;
2136 u32 render_irqs;
2137 u32 hotplug_mask;
2138
2139 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
2140 if (HAS_BSD(dev))
2141 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
2142 if (HAS_BLT(dev))
2143 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
2144
2145 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2146 dev_priv->irq_mask = ~display_mask;
2147
2148 /* should always can generate irq */
2149 I915_WRITE(DEIIR, I915_READ(DEIIR));
2150 I915_WRITE(DEIMR, dev_priv->irq_mask);
2151 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
2152 DE_PIPEB_VBLANK_IVB);
2153 POSTING_READ(DEIER);
2154
2155 dev_priv->gt_irq_mask = ~0;
2156
2157 I915_WRITE(GTIIR, I915_READ(GTIIR));
2158 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2159
e2a1e2f0
BW		 2160 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2161 GEN6_BLITTER_USER_INTERRUPT;
b1f14ad0
JB		 2162 I915_WRITE(GTIER, render_irqs);
2163 POSTING_READ(GTIER);
2164
2165 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
2166 SDE_PORTB_HOTPLUG_CPT |
2167 SDE_PORTC_HOTPLUG_CPT |
2168 SDE_PORTD_HOTPLUG_CPT);
2169 dev_priv->pch_irq_mask = ~hotplug_mask;
2170
2171 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2172 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
2173 I915_WRITE(SDEIER, hotplug_mask);
2174 POSTING_READ(SDEIER);
2175
7fe0b973
KP		 2176 ironlake_enable_pch_hotplug(dev);
2177
b1f14ad0
JB		 2178 return 0;
2179}
2180
7e231dbe
JB		 2181static int valleyview_irq_postinstall(struct drm_device *dev)
2182{
2183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2184 u32 render_irqs;
2185 u32 enable_mask;
2186 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2187 u16 msid;
2188
2189 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2190 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2191 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2192
2193 dev_priv->irq_mask = ~enable_mask;
2194
2195
2196 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
2197 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
2198 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
2199
2200 dev_priv->pipestat[0] = 0;
2201 dev_priv->pipestat[1] = 0;
2202
2203 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2204
2205 /* Hack for broken MSIs on VLV */
2206 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2207 pci_read_config_word(dev->pdev, 0x98, &msid);
2208 msid &= 0xff; /* mask out delivery bits */
2209 msid |= (1<<14);
2210 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2211
2212 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2213 I915_WRITE(VLV_IER, enable_mask);
2214 I915_WRITE(VLV_IIR, 0xffffffff);
2215 I915_WRITE(PIPESTAT(0), 0xffff);
2216 I915_WRITE(PIPESTAT(1), 0xffff);
2217 POSTING_READ(VLV_IER);
2218
2219 I915_WRITE(VLV_IIR, 0xffffffff);
2220 I915_WRITE(VLV_IIR, 0xffffffff);
2221
2222 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
2223 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
e2a1e2f0 2224 GT_GEN6_BLT_USER_INTERRUPT |
7e231dbe
JB		 2225 GT_GEN6_BSD_USER_INTERRUPT |
2226 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
2227 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
2228 GT_PIPE_NOTIFY |
2229 GT_RENDER_CS_ERROR_INTERRUPT |
2230 GT_SYNC_STATUS |
2231 GT_USER_INTERRUPT;
2232
2233 dev_priv->gt_irq_mask = ~render_irqs;
2234
2235 I915_WRITE(GTIIR, I915_READ(GTIIR));
2236 I915_WRITE(GTIIR, I915_READ(GTIIR));
2237 I915_WRITE(GTIMR, 0);
2238 I915_WRITE(GTIER, render_irqs);
2239 POSTING_READ(GTIER);
2240
2241 /* ack & enable invalid PTE error interrupts */
2242#if 0 /* FIXME: add support to irq handler for checking these bits */
2243 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2244 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2245#endif
2246
2247 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2248#if 0 /* FIXME: check register definitions; some have moved */
2249 /* Note HDMI and DP share bits */
2250 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2251 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2252 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2253 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2254 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2255 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2256 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2257 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2258 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2259 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2260 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2261 hotplug_en |= CRT_HOTPLUG_INT_EN;
2262 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2263 }
2264#endif
2265
2266 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2267
2268 return 0;
2269}
2270
f71d4af4 2271static void i915_driver_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2272{
2273 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2274 int pipe;
1da177e4 2275
79e53945
JB		 2276 atomic_set(&dev_priv->irq_received, 0);
2277
036a4a7d 2278 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
8a905236 2279 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
036a4a7d 2280
5ca58282
JB		 2281 if (I915_HAS_HOTPLUG(dev)) {
2282 I915_WRITE(PORT_HOTPLUG_EN, 0);
2283 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2284 }
2285
0a3e67a4 2286 I915_WRITE(HWSTAM, 0xeffe);
9db4a9c7
JB		 2287 for_each_pipe(pipe)
2288 I915_WRITE(PIPESTAT(pipe), 0);
0a3e67a4 2289 I915_WRITE(IMR, 0xffffffff);
ed4cb414 2290 I915_WRITE(IER, 0x0);
3143a2bf 2291 POSTING_READ(IER);
1da177e4
LT		 2292}
2293
b01f2c3a
JB		 2294/*
2295 * Must be called after intel_modeset_init or hotplug interrupts won't be
2296 * enabled correctly.
2297 */
f71d4af4 2298static int i915_driver_irq_postinstall(struct drm_device *dev)
1da177e4
LT		 2299{
2300 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5ca58282 2301 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
63eeaf38 2302 u32 error_mask;
0a3e67a4
JB		 2303
2304 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
0a3e67a4 2305
7c463586 2306 /* Unmask the interrupts that we always want on. */
1ec14ad3 2307 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
7c463586
KP		 2308
2309 dev_priv->pipestat[0] = 0;
2310 dev_priv->pipestat[1] = 0;
2311
5ca58282 2312 if (I915_HAS_HOTPLUG(dev)) {
5ca58282
JB		 2313 /* Enable in IER... */
2314 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2315 /* and unmask in IMR */
1ec14ad3 2316 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
5ca58282
JB		 2317 }
2318
63eeaf38
JB		 2319 /*
2320 * Enable some error detection, note the instruction error mask
2321 * bit is reserved, so we leave it masked.
2322 */
2323 if (IS_G4X(dev)) {
2324 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2325 GM45_ERROR_MEM_PRIV |
2326 GM45_ERROR_CP_PRIV |
2327 I915_ERROR_MEMORY_REFRESH);
2328 } else {
2329 error_mask = ~(I915_ERROR_PAGE_TABLE |
2330 I915_ERROR_MEMORY_REFRESH);
2331 }
2332 I915_WRITE(EMR, error_mask);
2333
1ec14ad3 2334 I915_WRITE(IMR, dev_priv->irq_mask);
c496fa1f 2335 I915_WRITE(IER, enable_mask);
3143a2bf 2336 POSTING_READ(IER);
ed4cb414 2337
c496fa1f
AJ		 2338 if (I915_HAS_HOTPLUG(dev)) {
2339 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2340
2341 /* Note HDMI and DP share bits */
2342 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2343 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2344 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2345 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2346 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2347 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2348 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2349 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2350 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2351 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2d1c9752 2352 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
c496fa1f 2353 hotplug_en |= CRT_HOTPLUG_INT_EN;
2d1c9752
AL		 2354
2355 /* Programming the CRT detection parameters tends
2356 to generate a spurious hotplug event about three
2357 seconds later. So just do it once.
2358 */
2359 if (IS_G4X(dev))
2360 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2361 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2362 }
2363
c496fa1f
AJ		 2364 /* Ignore TV since it's buggy */
2365
2366 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2367 }
2368
3b617967 2369 intel_opregion_enable_asle(dev);
0a3e67a4
JB		 2370
2371 return 0;
1da177e4
LT		 2372}
2373
7e231dbe
JB		 2374static void valleyview_irq_uninstall(struct drm_device *dev)
2375{
2376 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2377 int pipe;
2378
2379 if (!dev_priv)
2380 return;
2381
2382 dev_priv->vblank_pipe = 0;
2383
2384 for_each_pipe(pipe)
2385 I915_WRITE(PIPESTAT(pipe), 0xffff);
2386
2387 I915_WRITE(HWSTAM, 0xffffffff);
2388 I915_WRITE(PORT_HOTPLUG_EN, 0);
2389 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2390 for_each_pipe(pipe)
2391 I915_WRITE(PIPESTAT(pipe), 0xffff);
2392 I915_WRITE(VLV_IIR, 0xffffffff);
2393 I915_WRITE(VLV_IMR, 0xffffffff);
2394 I915_WRITE(VLV_IER, 0x0);
2395 POSTING_READ(VLV_IER);
2396}
2397
f71d4af4 2398static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2399{
2400 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2401
2402 if (!dev_priv)
2403 return;
2404
2405 dev_priv->vblank_pipe = 0;
2406
036a4a7d
ZW		 2407 I915_WRITE(HWSTAM, 0xffffffff);
2408
2409 I915_WRITE(DEIMR, 0xffffffff);
2410 I915_WRITE(DEIER, 0x0);
2411 I915_WRITE(DEIIR, I915_READ(DEIIR));
2412
2413 I915_WRITE(GTIMR, 0xffffffff);
2414 I915_WRITE(GTIER, 0x0);
2415 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2416
2417 I915_WRITE(SDEIMR, 0xffffffff);
2418 I915_WRITE(SDEIER, 0x0);
2419 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2420}
2421
f71d4af4 2422static void i915_driver_irq_uninstall(struct drm_device * dev)
1da177e4
LT		 2423{
2424 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2425 int pipe;
91e3738e 2426
1da177e4
LT		 2427 if (!dev_priv)
2428 return;
2429
0a3e67a4
JB		 2430 dev_priv->vblank_pipe = 0;
2431
5ca58282
JB		 2432 if (I915_HAS_HOTPLUG(dev)) {
2433 I915_WRITE(PORT_HOTPLUG_EN, 0);
2434 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2435 }
2436
0a3e67a4 2437 I915_WRITE(HWSTAM, 0xffffffff);
9db4a9c7
JB		 2438 for_each_pipe(pipe)
2439 I915_WRITE(PIPESTAT(pipe), 0);
0a3e67a4 2440 I915_WRITE(IMR, 0xffffffff);
ed4cb414 2441 I915_WRITE(IER, 0x0);
af6061af 2442
9db4a9c7
JB		 2443 for_each_pipe(pipe)
2444 I915_WRITE(PIPESTAT(pipe),
2445 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
7c463586 2446 I915_WRITE(IIR, I915_READ(IIR));
1da177e4 2447}
f71d4af4 2448
c2798b19
CW		 2449static void i8xx_irq_preinstall(struct drm_device * dev)
2450{
2451 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2452 int pipe;
2453
2454 atomic_set(&dev_priv->irq_received, 0);
2455
2456 for_each_pipe(pipe)
2457 I915_WRITE(PIPESTAT(pipe), 0);
2458 I915_WRITE16(IMR, 0xffff);
2459 I915_WRITE16(IER, 0x0);
2460 POSTING_READ16(IER);
2461}
2462
2463static int i8xx_irq_postinstall(struct drm_device *dev)
2464{
2465 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2466
2467 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2468
2469 dev_priv->pipestat[0] = 0;
2470 dev_priv->pipestat[1] = 0;
2471
2472 I915_WRITE16(EMR,
2473 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2474
2475 /* Unmask the interrupts that we always want on. */
2476 dev_priv->irq_mask =
2477 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2478 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2479 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2480 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2481 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2482 I915_WRITE16(IMR, dev_priv->irq_mask);
2483
2484 I915_WRITE16(IER,
2485 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2486 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2487 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2488 I915_USER_INTERRUPT);
2489 POSTING_READ16(IER);
2490
2491 return 0;
2492}
2493
2494static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2495{
2496 struct drm_device *dev = (struct drm_device *) arg;
2497 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2498 struct drm_i915_master_private *master_priv;
2499 u16 iir, new_iir;
2500 u32 pipe_stats[2];
2501 unsigned long irqflags;
2502 int irq_received;
2503 int pipe;
2504 u16 flip_mask =
2505 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2506 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2507
2508 atomic_inc(&dev_priv->irq_received);
2509
2510 iir = I915_READ16(IIR);
2511 if (iir == 0)
2512 return IRQ_NONE;
2513
2514 while (iir & ~flip_mask) {
2515 /* Can't rely on pipestat interrupt bit in iir as it might
2516 * have been cleared after the pipestat interrupt was received.
2517 * It doesn't set the bit in iir again, but it still produces
2518 * interrupts (for non-MSI).
2519 */
2520 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2521 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2522 i915_handle_error(dev, false);
2523
2524 for_each_pipe(pipe) {
2525 int reg = PIPESTAT(pipe);
2526 pipe_stats[pipe] = I915_READ(reg);
2527
2528 /*
2529 * Clear the PIPE*STAT regs before the IIR
2530 */
2531 if (pipe_stats[pipe] & 0x8000ffff) {
2532 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2533 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2534 pipe_name(pipe));
2535 I915_WRITE(reg, pipe_stats[pipe]);
2536 irq_received = 1;
2537 }
2538 }
2539 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2540
2541 I915_WRITE16(IIR, iir & ~flip_mask);
2542 new_iir = I915_READ16(IIR); /* Flush posted writes */
2543
2544 if (dev->primary->master) {
2545 master_priv = dev->primary->master->driver_priv;
2546 if (master_priv->sarea_priv)
2547 master_priv->sarea_priv->last_dispatch =
2548 READ_BREADCRUMB(dev_priv);
2549 }
2550
2551 if (iir & I915_USER_INTERRUPT)
2552 notify_ring(dev, &dev_priv->ring[RCS]);
2553
2554 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2555 drm_handle_vblank(dev, 0)) {
2556 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2557 intel_prepare_page_flip(dev, 0);
2558 intel_finish_page_flip(dev, 0);
2559 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2560 }
2561 }
2562
2563 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2564 drm_handle_vblank(dev, 1)) {
2565 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2566 intel_prepare_page_flip(dev, 1);
2567 intel_finish_page_flip(dev, 1);
2568 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2569 }
2570 }
2571
2572 iir = new_iir;
2573 }
2574
2575 return IRQ_HANDLED;
2576}
2577
2578static void i8xx_irq_uninstall(struct drm_device * dev)
2579{
2580 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2581 int pipe;
2582
2583 dev_priv->vblank_pipe = 0;
2584
2585 for_each_pipe(pipe) {
2586 /* Clear enable bits; then clear status bits */
2587 I915_WRITE(PIPESTAT(pipe), 0);
2588 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2589 }
2590 I915_WRITE16(IMR, 0xffff);
2591 I915_WRITE16(IER, 0x0);
2592 I915_WRITE16(IIR, I915_READ16(IIR));
2593}
2594
f71d4af4
JB		 2595void intel_irq_init(struct drm_device *dev)
2596{
2597 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2598 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7e231dbe
JB		 2599 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
2600 IS_VALLEYVIEW(dev)) {
f71d4af4
JB		 2601 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2602 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2603 }
2604
c3613de9
KP		 2605 if (drm_core_check_feature(dev, DRIVER_MODESET))
2606 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2607 else
2608 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2609 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2610
7e231dbe
JB		 2611 if (IS_VALLEYVIEW(dev)) {
2612 dev->driver->irq_handler = valleyview_irq_handler;
2613 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2614 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2615 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2616 dev->driver->enable_vblank = valleyview_enable_vblank;
2617 dev->driver->disable_vblank = valleyview_disable_vblank;
2618 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2619 /* Share pre & uninstall handlers with ILK/SNB */
2620 dev->driver->irq_handler = ivybridge_irq_handler;
2621 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2622 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2623 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2624 dev->driver->enable_vblank = ivybridge_enable_vblank;
2625 dev->driver->disable_vblank = ivybridge_disable_vblank;
2626 } else if (HAS_PCH_SPLIT(dev)) {
2627 dev->driver->irq_handler = ironlake_irq_handler;
2628 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2629 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2630 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2631 dev->driver->enable_vblank = ironlake_enable_vblank;
2632 dev->driver->disable_vblank = ironlake_disable_vblank;
2633 } else {
c2798b19
CW		 2634 if (INTEL_INFO(dev)->gen == 2) {
2635 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2636 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2637 dev->driver->irq_handler = i8xx_irq_handler;
2638 dev->driver->irq_uninstall = i8xx_irq_uninstall;
2639 } else {
2640 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2641 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2642 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2643 dev->driver->irq_handler = i915_driver_irq_handler;
2644 }
f71d4af4
JB		 2645 dev->driver->enable_vblank = i915_enable_vblank;
2646 dev->driver->disable_vblank = i915_disable_vblank;
2647 }
2648}
Linux 6.x block layer and io_uring tree(s)