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drm/i915: Skip register reads in i915_get_crtc_scanoutpos()
[linux-block.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
e5868a31
EE		 73static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
036a4a7d 82/* For display hotplug interrupt */
995b6762 83static void
f2b115e6 84ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 85{
4bc9d430
DV		 86 assert_spin_locked(&dev_priv->irq_lock);
87
c67a470b
PZ		 88 if (dev_priv->pc8.irqs_disabled) {
89 WARN(1, "IRQs disabled\n");
90 dev_priv->pc8.regsave.deimr &= ~mask;
91 return;
92 }
93
1ec14ad3
CW		 94 if ((dev_priv->irq_mask & mask) != 0) {
95 dev_priv->irq_mask &= ~mask;
96 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 97 POSTING_READ(DEIMR);
036a4a7d
ZW		 98 }
99}
100
0ff9800a 101static void
f2b115e6 102ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 103{
4bc9d430
DV		 104 assert_spin_locked(&dev_priv->irq_lock);
105
c67a470b
PZ		 106 if (dev_priv->pc8.irqs_disabled) {
107 WARN(1, "IRQs disabled\n");
108 dev_priv->pc8.regsave.deimr |= mask;
109 return;
110 }
111
1ec14ad3
CW		 112 if ((dev_priv->irq_mask & mask) != mask) {
113 dev_priv->irq_mask |= mask;
114 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 115 POSTING_READ(DEIMR);
036a4a7d
ZW		 116 }
117}
118
43eaea13
PZ		 119/**
120 * ilk_update_gt_irq - update GTIMR
121 * @dev_priv: driver private
122 * @interrupt_mask: mask of interrupt bits to update
123 * @enabled_irq_mask: mask of interrupt bits to enable
124 */
125static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
126 uint32_t interrupt_mask,
127 uint32_t enabled_irq_mask)
128{
129 assert_spin_locked(&dev_priv->irq_lock);
130
c67a470b
PZ		 131 if (dev_priv->pc8.irqs_disabled) {
132 WARN(1, "IRQs disabled\n");
133 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
134 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
135 interrupt_mask);
136 return;
137 }
138
43eaea13
PZ		 139 dev_priv->gt_irq_mask &= ~interrupt_mask;
140 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
141 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
142 POSTING_READ(GTIMR);
143}
144
145void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
146{
147 ilk_update_gt_irq(dev_priv, mask, mask);
148}
149
150void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
151{
152 ilk_update_gt_irq(dev_priv, mask, 0);
153}
154
edbfdb45
PZ		 155/**
156 * snb_update_pm_irq - update GEN6_PMIMR
157 * @dev_priv: driver private
158 * @interrupt_mask: mask of interrupt bits to update
159 * @enabled_irq_mask: mask of interrupt bits to enable
160 */
161static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
162 uint32_t interrupt_mask,
163 uint32_t enabled_irq_mask)
164{
605cd25b 165 uint32_t new_val;
edbfdb45
PZ		 166
167 assert_spin_locked(&dev_priv->irq_lock);
168
c67a470b
PZ		 169 if (dev_priv->pc8.irqs_disabled) {
170 WARN(1, "IRQs disabled\n");
171 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
172 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
173 interrupt_mask);
174 return;
175 }
176
605cd25b 177 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 178 new_val &= ~interrupt_mask;
179 new_val |= (~enabled_irq_mask & interrupt_mask);
180
605cd25b
PZ		 181 if (new_val != dev_priv->pm_irq_mask) {
182 dev_priv->pm_irq_mask = new_val;
183 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
f52ecbcf
PZ		 184 POSTING_READ(GEN6_PMIMR);
185 }
edbfdb45
PZ		 186}
187
188void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
189{
190 snb_update_pm_irq(dev_priv, mask, mask);
191}
192
193void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
194{
195 snb_update_pm_irq(dev_priv, mask, 0);
196}
197
8664281b
PZ		 198static bool ivb_can_enable_err_int(struct drm_device *dev)
199{
200 struct drm_i915_private *dev_priv = dev->dev_private;
201 struct intel_crtc *crtc;
202 enum pipe pipe;
203
4bc9d430
DV		 204 assert_spin_locked(&dev_priv->irq_lock);
205
8664281b
PZ		 206 for_each_pipe(pipe) {
207 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
208
209 if (crtc->cpu_fifo_underrun_disabled)
210 return false;
211 }
212
213 return true;
214}
215
216static bool cpt_can_enable_serr_int(struct drm_device *dev)
217{
218 struct drm_i915_private *dev_priv = dev->dev_private;
219 enum pipe pipe;
220 struct intel_crtc *crtc;
221
fee884ed
DV		 222 assert_spin_locked(&dev_priv->irq_lock);
223
8664281b
PZ		 224 for_each_pipe(pipe) {
225 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
226
227 if (crtc->pch_fifo_underrun_disabled)
228 return false;
229 }
230
231 return true;
232}
233
234static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
235 enum pipe pipe, bool enable)
236{
237 struct drm_i915_private *dev_priv = dev->dev_private;
238 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
239 DE_PIPEB_FIFO_UNDERRUN;
240
241 if (enable)
242 ironlake_enable_display_irq(dev_priv, bit);
243 else
244 ironlake_disable_display_irq(dev_priv, bit);
245}
246
247static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
7336df65 248 enum pipe pipe, bool enable)
8664281b
PZ		 249{
250 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 251 if (enable) {
7336df65
DV		 252 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
253
8664281b
PZ		 254 if (!ivb_can_enable_err_int(dev))
255 return;
256
8664281b
PZ		 257 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
258 } else {
7336df65
DV		 259 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
260
261 /* Change the state _after_ we've read out the current one. */
8664281b 262 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65
DV		 263
264 if (!was_enabled &&
265 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
266 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
267 pipe_name(pipe));
268 }
8664281b
PZ		 269 }
270}
271
fee884ed
DV		 272/**
273 * ibx_display_interrupt_update - update SDEIMR
274 * @dev_priv: driver private
275 * @interrupt_mask: mask of interrupt bits to update
276 * @enabled_irq_mask: mask of interrupt bits to enable
277 */
278static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
279 uint32_t interrupt_mask,
280 uint32_t enabled_irq_mask)
281{
282 uint32_t sdeimr = I915_READ(SDEIMR);
283 sdeimr &= ~interrupt_mask;
284 sdeimr |= (~enabled_irq_mask & interrupt_mask);
285
286 assert_spin_locked(&dev_priv->irq_lock);
287
c67a470b
PZ		 288 if (dev_priv->pc8.irqs_disabled &&
289 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
290 WARN(1, "IRQs disabled\n");
291 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
292 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
293 interrupt_mask);
294 return;
295 }
296
fee884ed
DV		 297 I915_WRITE(SDEIMR, sdeimr);
298 POSTING_READ(SDEIMR);
299}
300#define ibx_enable_display_interrupt(dev_priv, bits) \
301 ibx_display_interrupt_update((dev_priv), (bits), (bits))
302#define ibx_disable_display_interrupt(dev_priv, bits) \
303 ibx_display_interrupt_update((dev_priv), (bits), 0)
304
de28075d
DV		 305static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
306 enum transcoder pch_transcoder,
8664281b
PZ		 307 bool enable)
308{
8664281b 309 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 310 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
311 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 312
313 if (enable)
fee884ed 314 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 315 else
fee884ed 316 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 317}
318
319static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
320 enum transcoder pch_transcoder,
321 bool enable)
322{
323 struct drm_i915_private *dev_priv = dev->dev_private;
324
325 if (enable) {
1dd246fb
DV		 326 I915_WRITE(SERR_INT,
327 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
328
8664281b
PZ		 329 if (!cpt_can_enable_serr_int(dev))
330 return;
331
fee884ed 332 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 333 } else {
1dd246fb
DV		 334 uint32_t tmp = I915_READ(SERR_INT);
335 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
336
337 /* Change the state _after_ we've read out the current one. */
fee884ed 338 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb
DV		 339
340 if (!was_enabled &&
341 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
342 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
343 transcoder_name(pch_transcoder));
344 }
8664281b 345 }
8664281b
PZ		 346}
347
348/**
349 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
350 * @dev: drm device
351 * @pipe: pipe
352 * @enable: true if we want to report FIFO underrun errors, false otherwise
353 *
354 * This function makes us disable or enable CPU fifo underruns for a specific
355 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
356 * reporting for one pipe may also disable all the other CPU error interruts for
357 * the other pipes, due to the fact that there's just one interrupt mask/enable
358 * bit for all the pipes.
359 *
360 * Returns the previous state of underrun reporting.
361 */
362bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
363 enum pipe pipe, bool enable)
364{
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
368 unsigned long flags;
369 bool ret;
370
371 spin_lock_irqsave(&dev_priv->irq_lock, flags);
372
373 ret = !intel_crtc->cpu_fifo_underrun_disabled;
374
375 if (enable == ret)
376 goto done;
377
378 intel_crtc->cpu_fifo_underrun_disabled = !enable;
379
380 if (IS_GEN5(dev) || IS_GEN6(dev))
381 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
382 else if (IS_GEN7(dev))
7336df65 383 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b
PZ		 384
385done:
386 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
387 return ret;
388}
389
390/**
391 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
392 * @dev: drm device
393 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
394 * @enable: true if we want to report FIFO underrun errors, false otherwise
395 *
396 * This function makes us disable or enable PCH fifo underruns for a specific
397 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
398 * underrun reporting for one transcoder may also disable all the other PCH
399 * error interruts for the other transcoders, due to the fact that there's just
400 * one interrupt mask/enable bit for all the transcoders.
401 *
402 * Returns the previous state of underrun reporting.
403 */
404bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
405 enum transcoder pch_transcoder,
406 bool enable)
407{
408 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 409 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 411 unsigned long flags;
412 bool ret;
413
de28075d
DV		 414 /*
415 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
416 * has only one pch transcoder A that all pipes can use. To avoid racy
417 * pch transcoder -> pipe lookups from interrupt code simply store the
418 * underrun statistics in crtc A. Since we never expose this anywhere
419 * nor use it outside of the fifo underrun code here using the "wrong"
420 * crtc on LPT won't cause issues.
421 */
8664281b
PZ		 422
423 spin_lock_irqsave(&dev_priv->irq_lock, flags);
424
425 ret = !intel_crtc->pch_fifo_underrun_disabled;
426
427 if (enable == ret)
428 goto done;
429
430 intel_crtc->pch_fifo_underrun_disabled = !enable;
431
432 if (HAS_PCH_IBX(dev))
de28075d 433 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b
PZ		 434 else
435 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
436
437done:
438 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
439 return ret;
440}
441
442
7c463586
KP		 443void
444i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
445{
46c06a30
VS		 446 u32 reg = PIPESTAT(pipe);
447 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 448
b79480ba
DV		 449 assert_spin_locked(&dev_priv->irq_lock);
450
46c06a30
VS		 451 if ((pipestat & mask) == mask)
452 return;
453
454 /* Enable the interrupt, clear any pending status */
455 pipestat |= mask | (mask >> 16);
456 I915_WRITE(reg, pipestat);
457 POSTING_READ(reg);
7c463586
KP		 458}
459
460void
461i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
462{
46c06a30
VS		 463 u32 reg = PIPESTAT(pipe);
464 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 465
b79480ba
DV		 466 assert_spin_locked(&dev_priv->irq_lock);
467
46c06a30
VS		 468 if ((pipestat & mask) == 0)
469 return;
470
471 pipestat &= ~mask;
472 I915_WRITE(reg, pipestat);
473 POSTING_READ(reg);
7c463586
KP		 474}
475
01c66889 476/**
f49e38dd 477 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 478 */
f49e38dd 479static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 480{
1ec14ad3
CW		 481 drm_i915_private_t *dev_priv = dev->dev_private;
482 unsigned long irqflags;
483
f49e38dd
JN		 484 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
485 return;
486
1ec14ad3 487 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 488
f898780b
JN		 489 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
490 if (INTEL_INFO(dev)->gen >= 4)
491 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 492
493 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 494}
495
0a3e67a4
JB		 496/**
497 * i915_pipe_enabled - check if a pipe is enabled
498 * @dev: DRM device
499 * @pipe: pipe to check
500 *
501 * Reading certain registers when the pipe is disabled can hang the chip.
502 * Use this routine to make sure the PLL is running and the pipe is active
503 * before reading such registers if unsure.
504 */
505static int
506i915_pipe_enabled(struct drm_device *dev, int pipe)
507{
508 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 509
a01025af
DV		 510 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
511 /* Locking is horribly broken here, but whatever. */
512 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 514
a01025af
DV		 515 return intel_crtc->active;
516 } else {
517 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
518 }
0a3e67a4
JB		 519}
520
42f52ef8
KP		 521/* Called from drm generic code, passed a 'crtc', which
522 * we use as a pipe index
523 */
f71d4af4 524static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 525{
526 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
527 unsigned long high_frame;
528 unsigned long low_frame;
391f75e2 529 u32 high1, high2, low, pixel, vbl_start;
0a3e67a4
JB		 530
531 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 532 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 533 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 534 return 0;
535 }
536
391f75e2
VS		 537 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
538 struct intel_crtc *intel_crtc =
539 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
540 const struct drm_display_mode *mode =
541 &intel_crtc->config.adjusted_mode;
542
543 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
544 } else {
545 enum transcoder cpu_transcoder =
546 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
547 u32 htotal;
548
549 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
550 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
551
552 vbl_start *= htotal;
553 }
554
9db4a9c7
JB		 555 high_frame = PIPEFRAME(pipe);
556 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 557
0a3e67a4
JB		 558 /*
559 * High & low register fields aren't synchronized, so make sure
560 * we get a low value that's stable across two reads of the high
561 * register.
562 */
563 do {
5eddb70b 564 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 565 low = I915_READ(low_frame);
5eddb70b 566 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 567 } while (high1 != high2);
568
5eddb70b 569 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 570 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 571 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 572
573 /*
574 * The frame counter increments at beginning of active.
575 * Cook up a vblank counter by also checking the pixel
576 * counter against vblank start.
577 */
578 return ((high1 << 8) | low) + (pixel >= vbl_start);
0a3e67a4
JB		 579}
580
f71d4af4 581static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 582{
583 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 584 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 585
586 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 587 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 588 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 589 return 0;
590 }
591
592 return I915_READ(reg);
593}
594
f71d4af4 595static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 596 int *vpos, int *hpos)
597{
c2baf4b7
VS		 598 struct drm_i915_private *dev_priv = dev->dev_private;
599 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
601 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
602 u32 position;
0af7e4df
MK		 603 int vbl_start, vbl_end, htotal, vtotal;
604 bool in_vbl = true;
605 int ret = 0;
606
c2baf4b7 607 if (!intel_crtc->active) {
0af7e4df 608 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 609 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 610 return 0;
611 }
612
c2baf4b7
VS		 613 htotal = mode->crtc_htotal;
614 vtotal = mode->crtc_vtotal;
615 vbl_start = mode->crtc_vblank_start;
616 vbl_end = mode->crtc_vblank_end;
0af7e4df 617
c2baf4b7
VS		 618 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
619
620 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 621 /* No obvious pixelcount register. Only query vertical
622 * scanout position from Display scan line register.
623 */
624 position = I915_READ(PIPEDSL(pipe));
625
626 /* Decode into vertical scanout position. Don't have
627 * horizontal scanout position.
628 */
629 *vpos = position & 0x1fff;
630 *hpos = 0;
631 } else {
632 /* Have access to pixelcount since start of frame.
633 * We can split this into vertical and horizontal
634 * scanout position.
635 */
636 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
637
0af7e4df
MK		 638 *vpos = position / htotal;
639 *hpos = position - (*vpos * htotal);
640 }
641
c2baf4b7 642 in_vbl = *vpos >= vbl_start && *vpos < vbl_end;
0af7e4df
MK		 643
644 /* Inside "upper part" of vblank area? Apply corrective offset: */
645 if (in_vbl && (*vpos >= vbl_start))
646 *vpos = *vpos - vtotal;
647
0af7e4df
MK		 648 /* In vblank? */
649 if (in_vbl)
650 ret |= DRM_SCANOUTPOS_INVBL;
651
652 return ret;
653}
654
f71d4af4 655static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 656 int *max_error,
657 struct timeval *vblank_time,
658 unsigned flags)
659{
4041b853 660 struct drm_crtc *crtc;
0af7e4df 661
7eb552ae 662 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 663 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 664 return -EINVAL;
665 }
666
667 /* Get drm_crtc to timestamp: */
4041b853
CW		 668 crtc = intel_get_crtc_for_pipe(dev, pipe);
669 if (crtc == NULL) {
670 DRM_ERROR("Invalid crtc %d\n", pipe);
671 return -EINVAL;
672 }
673
674 if (!crtc->enabled) {
675 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
676 return -EBUSY;
677 }
0af7e4df
MK		 678
679 /* Helper routine in DRM core does all the work: */
4041b853
CW		 680 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
681 vblank_time, flags,
682 crtc);
0af7e4df
MK		 683}
684
67c347ff
JN		 685static bool intel_hpd_irq_event(struct drm_device *dev,
686 struct drm_connector *connector)
321a1b30
EE		 687{
688 enum drm_connector_status old_status;
689
690 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
691 old_status = connector->status;
692
693 connector->status = connector->funcs->detect(connector, false);
67c347ff
JN		 694 if (old_status == connector->status)
695 return false;
696
697 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
321a1b30
EE		 698 connector->base.id,
699 drm_get_connector_name(connector),
67c347ff
JN		 700 drm_get_connector_status_name(old_status),
701 drm_get_connector_status_name(connector->status));
702
703 return true;
321a1b30
EE		 704}
705
5ca58282
JB		 706/*
707 * Handle hotplug events outside the interrupt handler proper.
708 */
ac4c16c5
EE		 709#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
710
5ca58282
JB		 711static void i915_hotplug_work_func(struct work_struct *work)
712{
713 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
714 hotplug_work);
715 struct drm_device *dev = dev_priv->dev;
c31c4ba3 716 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 717 struct intel_connector *intel_connector;
718 struct intel_encoder *intel_encoder;
719 struct drm_connector *connector;
720 unsigned long irqflags;
721 bool hpd_disabled = false;
321a1b30 722 bool changed = false;
142e2398 723 u32 hpd_event_bits;
4ef69c7a 724
52d7eced
DV		 725 /* HPD irq before everything is fully set up. */
726 if (!dev_priv->enable_hotplug_processing)
727 return;
728
a65e34c7 729 mutex_lock(&mode_config->mutex);
e67189ab
JB		 730 DRM_DEBUG_KMS("running encoder hotplug functions\n");
731
cd569aed 732 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 733
734 hpd_event_bits = dev_priv->hpd_event_bits;
735 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 736 list_for_each_entry(connector, &mode_config->connector_list, head) {
737 intel_connector = to_intel_connector(connector);
738 intel_encoder = intel_connector->encoder;
739 if (intel_encoder->hpd_pin > HPD_NONE &&
740 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
741 connector->polled == DRM_CONNECTOR_POLL_HPD) {
742 DRM_INFO("HPD interrupt storm detected on connector %s: "
743 "switching from hotplug detection to polling\n",
744 drm_get_connector_name(connector));
745 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
746 connector->polled = DRM_CONNECTOR_POLL_CONNECT
747 | DRM_CONNECTOR_POLL_DISCONNECT;
748 hpd_disabled = true;
749 }
142e2398
EE		 750 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
751 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
752 drm_get_connector_name(connector), intel_encoder->hpd_pin);
753 }
cd569aed
EE		 754 }
755 /* if there were no outputs to poll, poll was disabled,
756 * therefore make sure it's enabled when disabling HPD on
757 * some connectors */
ac4c16c5 758 if (hpd_disabled) {
cd569aed 759 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 760 mod_timer(&dev_priv->hotplug_reenable_timer,
761 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
762 }
cd569aed
EE		 763
764 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
765
321a1b30
EE		 766 list_for_each_entry(connector, &mode_config->connector_list, head) {
767 intel_connector = to_intel_connector(connector);
768 intel_encoder = intel_connector->encoder;
769 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
770 if (intel_encoder->hot_plug)
771 intel_encoder->hot_plug(intel_encoder);
772 if (intel_hpd_irq_event(dev, connector))
773 changed = true;
774 }
775 }
40ee3381
KP		 776 mutex_unlock(&mode_config->mutex);
777
321a1b30
EE		 778 if (changed)
779 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 780}
781
d0ecd7e2 782static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1
JB		 783{
784 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 785 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 786 u8 new_delay;
9270388e 787
d0ecd7e2 788 spin_lock(&mchdev_lock);
f97108d1 789
73edd18f
DV		 790 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
791
20e4d407 792 new_delay = dev_priv->ips.cur_delay;
9270388e 793
7648fa99 794 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 795 busy_up = I915_READ(RCPREVBSYTUPAVG);
796 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 797 max_avg = I915_READ(RCBMAXAVG);
798 min_avg = I915_READ(RCBMINAVG);
799
800 /* Handle RCS change request from hw */
b5b72e89 801 if (busy_up > max_avg) {
20e4d407
DV		 802 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
803 new_delay = dev_priv->ips.cur_delay - 1;
804 if (new_delay < dev_priv->ips.max_delay)
805 new_delay = dev_priv->ips.max_delay;
b5b72e89 806 } else if (busy_down < min_avg) {
20e4d407
DV		 807 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
808 new_delay = dev_priv->ips.cur_delay + 1;
809 if (new_delay > dev_priv->ips.min_delay)
810 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 811 }
812
7648fa99 813 if (ironlake_set_drps(dev, new_delay))
20e4d407 814 dev_priv->ips.cur_delay = new_delay;
f97108d1 815
d0ecd7e2 816 spin_unlock(&mchdev_lock);
9270388e 817
f97108d1
JB		 818 return;
819}
820
549f7365
CW		 821static void notify_ring(struct drm_device *dev,
822 struct intel_ring_buffer *ring)
823{
475553de
CW		 824 if (ring->obj == NULL)
825 return;
826
814e9b57 827 trace_i915_gem_request_complete(ring);
9862e600 828
549f7365 829 wake_up_all(&ring->irq_queue);
10cd45b6 830 i915_queue_hangcheck(dev);
549f7365
CW		 831}
832
4912d041 833static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 834{
4912d041 835 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 836 rps.work);
edbfdb45 837 u32 pm_iir;
dd75fdc8 838 int new_delay, adj;
4912d041 839
59cdb63d 840 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3
DV		 841 pm_iir = dev_priv->rps.pm_iir;
842 dev_priv->rps.pm_iir = 0;
4848405c 843 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
edbfdb45 844 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
59cdb63d 845 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 846
60611c13
PZ		 847 /* Make sure we didn't queue anything we're not going to process. */
848 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
849
4848405c 850 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 851 return;
852
4fc688ce 853 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 854
dd75fdc8 855 adj = dev_priv->rps.last_adj;
7425034a 856 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 857 if (adj > 0)
858 adj *= 2;
859 else
860 adj = 1;
861 new_delay = dev_priv->rps.cur_delay + adj;
7425034a
VS		 862
863 /*
864 * For better performance, jump directly
865 * to RPe if we're below it.
866 */
dd75fdc8
CW		 867 if (new_delay < dev_priv->rps.rpe_delay)
868 new_delay = dev_priv->rps.rpe_delay;
869 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
870 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
7425034a 871 new_delay = dev_priv->rps.rpe_delay;
dd75fdc8
CW		 872 else
873 new_delay = dev_priv->rps.min_delay;
874 adj = 0;
875 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
876 if (adj < 0)
877 adj *= 2;
878 else
879 adj = -1;
880 new_delay = dev_priv->rps.cur_delay + adj;
881 } else { /* unknown event */
882 new_delay = dev_priv->rps.cur_delay;
883 }
3b8d8d91 884
79249636
BW		 885 /* sysfs frequency interfaces may have snuck in while servicing the
886 * interrupt
887 */
dd75fdc8
CW		 888 if (new_delay < (int)dev_priv->rps.min_delay)
889 new_delay = dev_priv->rps.min_delay;
890 if (new_delay > (int)dev_priv->rps.max_delay)
891 new_delay = dev_priv->rps.max_delay;
892 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
893
894 if (IS_VALLEYVIEW(dev_priv->dev))
895 valleyview_set_rps(dev_priv->dev, new_delay);
896 else
897 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 898
4fc688ce 899 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 900}
901
e3689190
BW		 902
903/**
904 * ivybridge_parity_work - Workqueue called when a parity error interrupt
905 * occurred.
906 * @work: workqueue struct
907 *
908 * Doesn't actually do anything except notify userspace. As a consequence of
909 * this event, userspace should try to remap the bad rows since statistically
910 * it is likely the same row is more likely to go bad again.
911 */
912static void ivybridge_parity_work(struct work_struct *work)
913{
914 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 915 l3_parity.error_work);
e3689190 916 u32 error_status, row, bank, subbank;
35a85ac6 917 char *parity_event[6];
e3689190
BW		 918 uint32_t misccpctl;
919 unsigned long flags;
35a85ac6 920 uint8_t slice = 0;
e3689190
BW		 921
922 /* We must turn off DOP level clock gating to access the L3 registers.
923 * In order to prevent a get/put style interface, acquire struct mutex
924 * any time we access those registers.
925 */
926 mutex_lock(&dev_priv->dev->struct_mutex);
927
35a85ac6
BW		 928 /* If we've screwed up tracking, just let the interrupt fire again */
929 if (WARN_ON(!dev_priv->l3_parity.which_slice))
930 goto out;
931
e3689190
BW		 932 misccpctl = I915_READ(GEN7_MISCCPCTL);
933 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
934 POSTING_READ(GEN7_MISCCPCTL);
935
35a85ac6
BW		 936 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
937 u32 reg;
e3689190 938
35a85ac6
BW		 939 slice--;
940 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
941 break;
e3689190 942
35a85ac6 943 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 944
35a85ac6 945 reg = GEN7_L3CDERRST1 + (slice * 0x200);
e3689190 946
35a85ac6
BW		 947 error_status = I915_READ(reg);
948 row = GEN7_PARITY_ERROR_ROW(error_status);
949 bank = GEN7_PARITY_ERROR_BANK(error_status);
950 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
951
952 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
953 POSTING_READ(reg);
954
955 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
956 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
957 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
958 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
959 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
960 parity_event[5] = NULL;
961
962 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
963 KOBJ_CHANGE, parity_event);
e3689190 964
35a85ac6
BW		 965 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
966 slice, row, bank, subbank);
e3689190 967
35a85ac6
BW		 968 kfree(parity_event[4]);
969 kfree(parity_event[3]);
970 kfree(parity_event[2]);
971 kfree(parity_event[1]);
972 }
e3689190 973
35a85ac6 974 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 975
35a85ac6
BW		 976out:
977 WARN_ON(dev_priv->l3_parity.which_slice);
978 spin_lock_irqsave(&dev_priv->irq_lock, flags);
979 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
980 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
981
982 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 983}
984
35a85ac6 985static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190
BW		 986{
987 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e3689190 988
040d2baa 989 if (!HAS_L3_DPF(dev))
e3689190
BW		 990 return;
991
d0ecd7e2 992 spin_lock(&dev_priv->irq_lock);
35a85ac6 993 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 994 spin_unlock(&dev_priv->irq_lock);
e3689190 995
35a85ac6
BW		 996 iir &= GT_PARITY_ERROR(dev);
997 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
998 dev_priv->l3_parity.which_slice |= 1 << 1;
999
1000 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1001 dev_priv->l3_parity.which_slice |= 1 << 0;
1002
a4da4fa4 1003 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1004}
1005
f1af8fc1
PZ		 1006static void ilk_gt_irq_handler(struct drm_device *dev,
1007 struct drm_i915_private *dev_priv,
1008 u32 gt_iir)
1009{
1010 if (gt_iir &
1011 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1012 notify_ring(dev, &dev_priv->ring[RCS]);
1013 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1014 notify_ring(dev, &dev_priv->ring[VCS]);
1015}
1016
e7b4c6b1
DV		 1017static void snb_gt_irq_handler(struct drm_device *dev,
1018 struct drm_i915_private *dev_priv,
1019 u32 gt_iir)
1020{
1021
cc609d5d
BW		 1022 if (gt_iir &
1023 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1024 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1025 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 1026 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 1027 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 1028 notify_ring(dev, &dev_priv->ring[BCS]);
1029
cc609d5d
BW		 1030 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1031 GT_BSD_CS_ERROR_INTERRUPT |
1032 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 1033 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1034 i915_handle_error(dev, false);
1035 }
e3689190 1036
35a85ac6
BW		 1037 if (gt_iir & GT_PARITY_ERROR(dev))
1038 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1039}
1040
b543fb04
EE		 1041#define HPD_STORM_DETECT_PERIOD 1000
1042#define HPD_STORM_THRESHOLD 5
1043
10a504de 1044static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 1045 u32 hotplug_trigger,
1046 const u32 *hpd)
b543fb04
EE		 1047{
1048 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 1049 int i;
10a504de 1050 bool storm_detected = false;
b543fb04 1051
91d131d2
DV		 1052 if (!hotplug_trigger)
1053 return;
1054
b5ea2d56 1055 spin_lock(&dev_priv->irq_lock);
b543fb04 1056 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 1057
b8f102e8
EE		 1058 WARN(((hpd[i] & hotplug_trigger) &&
1059 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
1060 "Received HPD interrupt although disabled\n");
1061
b543fb04
EE		 1062 if (!(hpd[i] & hotplug_trigger) ||
1063 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1064 continue;
1065
bc5ead8c 1066 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 1067 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1068 dev_priv->hpd_stats[i].hpd_last_jiffies
1069 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1070 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1071 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1072 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1073 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1074 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1075 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1076 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1077 storm_detected = true;
b543fb04
EE		 1078 } else {
1079 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1080 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1081 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1082 }
1083 }
1084
10a504de
DV		 1085 if (storm_detected)
1086 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1087 spin_unlock(&dev_priv->irq_lock);
5876fa0d 1088
645416f5
DV		 1089 /*
1090 * Our hotplug handler can grab modeset locks (by calling down into the
1091 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1092 * queue for otherwise the flush_work in the pageflip code will
1093 * deadlock.
1094 */
1095 schedule_work(&dev_priv->hotplug_work);
b543fb04
EE		 1096}
1097
515ac2bb
DV		 1098static void gmbus_irq_handler(struct drm_device *dev)
1099{
28c70f16
DV		 1100 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1101
28c70f16 1102 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1103}
1104
ce99c256
DV		 1105static void dp_aux_irq_handler(struct drm_device *dev)
1106{
9ee32fea
DV		 1107 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1108
9ee32fea 1109 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1110}
1111
1403c0d4
PZ		 1112/* The RPS events need forcewake, so we add them to a work queue and mask their
1113 * IMR bits until the work is done. Other interrupts can be processed without
1114 * the work queue. */
1115static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1116{
41a05a3a 1117 if (pm_iir & GEN6_PM_RPS_EVENTS) {
59cdb63d 1118 spin_lock(&dev_priv->irq_lock);
41a05a3a 1119 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
4d3b3d5f 1120 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
59cdb63d 1121 spin_unlock(&dev_priv->irq_lock);
2adbee62
DV		 1122
1123 queue_work(dev_priv->wq, &dev_priv->rps.work);
baf02a1f 1124 }
baf02a1f 1125
1403c0d4
PZ		 1126 if (HAS_VEBOX(dev_priv->dev)) {
1127 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1128 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 1129
1403c0d4
PZ		 1130 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1131 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1132 i915_handle_error(dev_priv->dev, false);
1133 }
12638c57 1134 }
baf02a1f
BW		 1135}
1136
ff1f525e 1137static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 1138{
1139 struct drm_device *dev = (struct drm_device *) arg;
1140 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1141 u32 iir, gt_iir, pm_iir;
1142 irqreturn_t ret = IRQ_NONE;
1143 unsigned long irqflags;
1144 int pipe;
1145 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 1146
1147 atomic_inc(&dev_priv->irq_received);
1148
7e231dbe
JB		 1149 while (true) {
1150 iir = I915_READ(VLV_IIR);
1151 gt_iir = I915_READ(GTIIR);
1152 pm_iir = I915_READ(GEN6_PMIIR);
1153
1154 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1155 goto out;
1156
1157 ret = IRQ_HANDLED;
1158
e7b4c6b1 1159 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 1160
1161 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1162 for_each_pipe(pipe) {
1163 int reg = PIPESTAT(pipe);
1164 pipe_stats[pipe] = I915_READ(reg);
1165
1166 /*
1167 * Clear the PIPE*STAT regs before the IIR
1168 */
1169 if (pipe_stats[pipe] & 0x8000ffff) {
1170 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1171 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1172 pipe_name(pipe));
1173 I915_WRITE(reg, pipe_stats[pipe]);
1174 }
1175 }
1176 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1177
31acc7f5
JB		 1178 for_each_pipe(pipe) {
1179 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1180 drm_handle_vblank(dev, pipe);
1181
1182 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1183 intel_prepare_page_flip(dev, pipe);
1184 intel_finish_page_flip(dev, pipe);
1185 }
1186 }
1187
7e231dbe
JB		 1188 /* Consume port. Then clear IIR or we'll miss events */
1189 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1190 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1191 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 1192
1193 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1194 hotplug_status);
91d131d2
DV		 1195
1196 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1197
7e231dbe
JB		 1198 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1199 I915_READ(PORT_HOTPLUG_STAT);
1200 }
1201
515ac2bb
DV		 1202 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1203 gmbus_irq_handler(dev);
7e231dbe 1204
60611c13 1205 if (pm_iir)
d0ecd7e2 1206 gen6_rps_irq_handler(dev_priv, pm_iir);
7e231dbe
JB		 1207
1208 I915_WRITE(GTIIR, gt_iir);
1209 I915_WRITE(GEN6_PMIIR, pm_iir);
1210 I915_WRITE(VLV_IIR, iir);
1211 }
1212
1213out:
1214 return ret;
1215}
1216
23e81d69 1217static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1218{
1219 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1220 int pipe;
b543fb04 1221 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1222
91d131d2
DV		 1223 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1224
cfc33bf7
VS		 1225 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1226 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1227 SDE_AUDIO_POWER_SHIFT);
776ad806 1228 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1229 port_name(port));
1230 }
776ad806 1231
ce99c256
DV		 1232 if (pch_iir & SDE_AUX_MASK)
1233 dp_aux_irq_handler(dev);
1234
776ad806 1235 if (pch_iir & SDE_GMBUS)
515ac2bb 1236 gmbus_irq_handler(dev);
776ad806
JB		 1237
1238 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1239 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1240
1241 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1242 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1243
1244 if (pch_iir & SDE_POISON)
1245 DRM_ERROR("PCH poison interrupt\n");
1246
9db4a9c7
JB		 1247 if (pch_iir & SDE_FDI_MASK)
1248 for_each_pipe(pipe)
1249 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1250 pipe_name(pipe),
1251 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1252
1253 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1254 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1255
1256 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1257 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1258
776ad806 1259 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1260 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1261 false))
1262 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1263
1264 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1265 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1266 false))
1267 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1268}
1269
1270static void ivb_err_int_handler(struct drm_device *dev)
1271{
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273 u32 err_int = I915_READ(GEN7_ERR_INT);
1274
de032bf4
PZ		 1275 if (err_int & ERR_INT_POISON)
1276 DRM_ERROR("Poison interrupt\n");
1277
8664281b
PZ		 1278 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1279 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1280 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1281
1282 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1283 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1284 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1285
1286 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1287 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1288 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1289
1290 I915_WRITE(GEN7_ERR_INT, err_int);
1291}
1292
1293static void cpt_serr_int_handler(struct drm_device *dev)
1294{
1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 u32 serr_int = I915_READ(SERR_INT);
1297
de032bf4
PZ		 1298 if (serr_int & SERR_INT_POISON)
1299 DRM_ERROR("PCH poison interrupt\n");
1300
8664281b
PZ		 1301 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1302 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1303 false))
1304 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1305
1306 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1307 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1308 false))
1309 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1310
1311 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1312 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1313 false))
1314 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1315
1316 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1317}
1318
23e81d69
AJ		 1319static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1320{
1321 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1322 int pipe;
b543fb04 1323 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1324
91d131d2
DV		 1325 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1326
cfc33bf7
VS		 1327 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1328 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1329 SDE_AUDIO_POWER_SHIFT_CPT);
1330 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1331 port_name(port));
1332 }
23e81d69
AJ		 1333
1334 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1335 dp_aux_irq_handler(dev);
23e81d69
AJ		 1336
1337 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1338 gmbus_irq_handler(dev);
23e81d69
AJ		 1339
1340 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1341 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1342
1343 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1344 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1345
1346 if (pch_iir & SDE_FDI_MASK_CPT)
1347 for_each_pipe(pipe)
1348 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1349 pipe_name(pipe),
1350 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1351
1352 if (pch_iir & SDE_ERROR_CPT)
1353 cpt_serr_int_handler(dev);
23e81d69
AJ		 1354}
1355
c008bc6e
PZ		 1356static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1357{
1358 struct drm_i915_private *dev_priv = dev->dev_private;
1359
1360 if (de_iir & DE_AUX_CHANNEL_A)
1361 dp_aux_irq_handler(dev);
1362
1363 if (de_iir & DE_GSE)
1364 intel_opregion_asle_intr(dev);
1365
1366 if (de_iir & DE_PIPEA_VBLANK)
1367 drm_handle_vblank(dev, 0);
1368
1369 if (de_iir & DE_PIPEB_VBLANK)
1370 drm_handle_vblank(dev, 1);
1371
1372 if (de_iir & DE_POISON)
1373 DRM_ERROR("Poison interrupt\n");
1374
1375 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1376 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1377 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1378
1379 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1380 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1381 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1382
1383 if (de_iir & DE_PLANEA_FLIP_DONE) {
1384 intel_prepare_page_flip(dev, 0);
1385 intel_finish_page_flip_plane(dev, 0);
1386 }
1387
1388 if (de_iir & DE_PLANEB_FLIP_DONE) {
1389 intel_prepare_page_flip(dev, 1);
1390 intel_finish_page_flip_plane(dev, 1);
1391 }
1392
1393 /* check event from PCH */
1394 if (de_iir & DE_PCH_EVENT) {
1395 u32 pch_iir = I915_READ(SDEIIR);
1396
1397 if (HAS_PCH_CPT(dev))
1398 cpt_irq_handler(dev, pch_iir);
1399 else
1400 ibx_irq_handler(dev, pch_iir);
1401
1402 /* should clear PCH hotplug event before clear CPU irq */
1403 I915_WRITE(SDEIIR, pch_iir);
1404 }
1405
1406 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1407 ironlake_rps_change_irq_handler(dev);
1408}
1409
9719fb98
PZ		 1410static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1411{
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 int i;
1414
1415 if (de_iir & DE_ERR_INT_IVB)
1416 ivb_err_int_handler(dev);
1417
1418 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1419 dp_aux_irq_handler(dev);
1420
1421 if (de_iir & DE_GSE_IVB)
1422 intel_opregion_asle_intr(dev);
1423
1424 for (i = 0; i < 3; i++) {
1425 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1426 drm_handle_vblank(dev, i);
1427 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1428 intel_prepare_page_flip(dev, i);
1429 intel_finish_page_flip_plane(dev, i);
1430 }
1431 }
1432
1433 /* check event from PCH */
1434 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1435 u32 pch_iir = I915_READ(SDEIIR);
1436
1437 cpt_irq_handler(dev, pch_iir);
1438
1439 /* clear PCH hotplug event before clear CPU irq */
1440 I915_WRITE(SDEIIR, pch_iir);
1441 }
1442}
1443
f1af8fc1 1444static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1445{
1446 struct drm_device *dev = (struct drm_device *) arg;
1447 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
f1af8fc1 1448 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 1449 irqreturn_t ret = IRQ_NONE;
b1f14ad0
JB		 1450
1451 atomic_inc(&dev_priv->irq_received);
1452
8664281b
PZ		 1453 /* We get interrupts on unclaimed registers, so check for this before we
1454 * do any I915_{READ,WRITE}. */
907b28c5 1455 intel_uncore_check_errors(dev);
8664281b 1456
b1f14ad0
JB		 1457 /* disable master interrupt before clearing iir */
1458 de_ier = I915_READ(DEIER);
1459 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 1460 POSTING_READ(DEIER);
b1f14ad0 1461
44498aea
PZ		 1462 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1463 * interrupts will will be stored on its back queue, and then we'll be
1464 * able to process them after we restore SDEIER (as soon as we restore
1465 * it, we'll get an interrupt if SDEIIR still has something to process
1466 * due to its back queue). */
ab5c608b
BW		 1467 if (!HAS_PCH_NOP(dev)) {
1468 sde_ier = I915_READ(SDEIER);
1469 I915_WRITE(SDEIER, 0);
1470 POSTING_READ(SDEIER);
1471 }
44498aea 1472
b1f14ad0 1473 gt_iir = I915_READ(GTIIR);
0e43406b 1474 if (gt_iir) {
d8fc8a47 1475 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 1476 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 1477 else
1478 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
0e43406b
CW		 1479 I915_WRITE(GTIIR, gt_iir);
1480 ret = IRQ_HANDLED;
b1f14ad0
JB		 1481 }
1482
0e43406b
CW		 1483 de_iir = I915_READ(DEIIR);
1484 if (de_iir) {
f1af8fc1
PZ		 1485 if (INTEL_INFO(dev)->gen >= 7)
1486 ivb_display_irq_handler(dev, de_iir);
1487 else
1488 ilk_display_irq_handler(dev, de_iir);
0e43406b
CW		 1489 I915_WRITE(DEIIR, de_iir);
1490 ret = IRQ_HANDLED;
b1f14ad0
JB		 1491 }
1492
f1af8fc1
PZ		 1493 if (INTEL_INFO(dev)->gen >= 6) {
1494 u32 pm_iir = I915_READ(GEN6_PMIIR);
1495 if (pm_iir) {
1403c0d4 1496 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1
PZ		 1497 I915_WRITE(GEN6_PMIIR, pm_iir);
1498 ret = IRQ_HANDLED;
1499 }
0e43406b 1500 }
b1f14ad0 1501
b1f14ad0
JB		 1502 I915_WRITE(DEIER, de_ier);
1503 POSTING_READ(DEIER);
ab5c608b
BW		 1504 if (!HAS_PCH_NOP(dev)) {
1505 I915_WRITE(SDEIER, sde_ier);
1506 POSTING_READ(SDEIER);
1507 }
b1f14ad0
JB		 1508
1509 return ret;
1510}
1511
17e1df07
DV		 1512static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1513 bool reset_completed)
1514{
1515 struct intel_ring_buffer *ring;
1516 int i;
1517
1518 /*
1519 * Notify all waiters for GPU completion events that reset state has
1520 * been changed, and that they need to restart their wait after
1521 * checking for potential errors (and bail out to drop locks if there is
1522 * a gpu reset pending so that i915_error_work_func can acquire them).
1523 */
1524
1525 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1526 for_each_ring(ring, dev_priv, i)
1527 wake_up_all(&ring->irq_queue);
1528
1529 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1530 wake_up_all(&dev_priv->pending_flip_queue);
1531
1532 /*
1533 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1534 * reset state is cleared.
1535 */
1536 if (reset_completed)
1537 wake_up_all(&dev_priv->gpu_error.reset_queue);
1538}
1539
8a905236
JB		 1540/**
1541 * i915_error_work_func - do process context error handling work
1542 * @work: work struct
1543 *
1544 * Fire an error uevent so userspace can see that a hang or error
1545 * was detected.
1546 */
1547static void i915_error_work_func(struct work_struct *work)
1548{
1f83fee0
DV		 1549 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1550 work);
1551 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1552 gpu_error);
8a905236 1553 struct drm_device *dev = dev_priv->dev;
cce723ed
BW		 1554 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1555 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1556 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 1557 int ret;
8a905236 1558
f316a42c
BG		 1559 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1560
7db0ba24
DV		 1561 /*
1562 * Note that there's only one work item which does gpu resets, so we
1563 * need not worry about concurrent gpu resets potentially incrementing
1564 * error->reset_counter twice. We only need to take care of another
1565 * racing irq/hangcheck declaring the gpu dead for a second time. A
1566 * quick check for that is good enough: schedule_work ensures the
1567 * correct ordering between hang detection and this work item, and since
1568 * the reset in-progress bit is only ever set by code outside of this
1569 * work we don't need to worry about any other races.
1570 */
1571 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1572 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1573 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1574 reset_event);
1f83fee0 1575
17e1df07
DV		 1576 /*
1577 * All state reset _must_ be completed before we update the
1578 * reset counter, for otherwise waiters might miss the reset
1579 * pending state and not properly drop locks, resulting in
1580 * deadlocks with the reset work.
1581 */
f69061be
DV		 1582 ret = i915_reset(dev);
1583
17e1df07
DV		 1584 intel_display_handle_reset(dev);
1585
f69061be
DV		 1586 if (ret == 0) {
1587 /*
1588 * After all the gem state is reset, increment the reset
1589 * counter and wake up everyone waiting for the reset to
1590 * complete.
1591 *
1592 * Since unlock operations are a one-sided barrier only,
1593 * we need to insert a barrier here to order any seqno
1594 * updates before
1595 * the counter increment.
1596 */
1597 smp_mb__before_atomic_inc();
1598 atomic_inc(&dev_priv->gpu_error.reset_counter);
1599
1600 kobject_uevent_env(&dev->primary->kdev.kobj,
1601 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1602 } else {
1603 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1604 }
1f83fee0 1605
17e1df07
DV		 1606 /*
1607 * Note: The wake_up also serves as a memory barrier so that
1608 * waiters see the update value of the reset counter atomic_t.
1609 */
1610 i915_error_wake_up(dev_priv, true);
f316a42c 1611 }
8a905236
JB		 1612}
1613
35aed2e6 1614static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1615{
1616 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1617 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1618 u32 eir = I915_READ(EIR);
050ee91f 1619 int pipe, i;
8a905236 1620
35aed2e6
CW		 1621 if (!eir)
1622 return;
8a905236 1623
a70491cc 1624 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1625
bd9854f9
BW		 1626 i915_get_extra_instdone(dev, instdone);
1627
8a905236
JB		 1628 if (IS_G4X(dev)) {
1629 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1630 u32 ipeir = I915_READ(IPEIR_I965);
1631
a70491cc
JP		 1632 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1633 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1634 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1635 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1636 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1637 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1638 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1639 POSTING_READ(IPEIR_I965);
8a905236
JB		 1640 }
1641 if (eir & GM45_ERROR_PAGE_TABLE) {
1642 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1643 pr_err("page table error\n");
1644 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1645 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1646 POSTING_READ(PGTBL_ER);
8a905236
JB		 1647 }
1648 }
1649
a6c45cf0 1650 if (!IS_GEN2(dev)) {
8a905236
JB		 1651 if (eir & I915_ERROR_PAGE_TABLE) {
1652 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1653 pr_err("page table error\n");
1654 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1655 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1656 POSTING_READ(PGTBL_ER);
8a905236
JB		 1657 }
1658 }
1659
1660 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1661 pr_err("memory refresh error:\n");
9db4a9c7 1662 for_each_pipe(pipe)
a70491cc 1663 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1664 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1665 /* pipestat has already been acked */
1666 }
1667 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1668 pr_err("instruction error\n");
1669 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1670 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1671 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1672 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1673 u32 ipeir = I915_READ(IPEIR);
1674
a70491cc
JP		 1675 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1676 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1677 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1678 I915_WRITE(IPEIR, ipeir);
3143a2bf 1679 POSTING_READ(IPEIR);
8a905236
JB		 1680 } else {
1681 u32 ipeir = I915_READ(IPEIR_I965);
1682
a70491cc
JP		 1683 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1684 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1685 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1686 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1687 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1688 POSTING_READ(IPEIR_I965);
8a905236
JB		 1689 }
1690 }
1691
1692 I915_WRITE(EIR, eir);
3143a2bf 1693 POSTING_READ(EIR);
8a905236
JB		 1694 eir = I915_READ(EIR);
1695 if (eir) {
1696 /*
1697 * some errors might have become stuck,
1698 * mask them.
1699 */
1700 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1701 I915_WRITE(EMR, I915_READ(EMR) | eir);
1702 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1703 }
35aed2e6
CW		 1704}
1705
1706/**
1707 * i915_handle_error - handle an error interrupt
1708 * @dev: drm device
1709 *
1710 * Do some basic checking of regsiter state at error interrupt time and
1711 * dump it to the syslog. Also call i915_capture_error_state() to make
1712 * sure we get a record and make it available in debugfs. Fire a uevent
1713 * so userspace knows something bad happened (should trigger collection
1714 * of a ring dump etc.).
1715 */
527f9e90 1716void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1717{
1718 struct drm_i915_private *dev_priv = dev->dev_private;
1719
1720 i915_capture_error_state(dev);
1721 i915_report_and_clear_eir(dev);
8a905236 1722
ba1234d1 1723 if (wedged) {
f69061be
DV		 1724 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1725 &dev_priv->gpu_error.reset_counter);
ba1234d1 1726
11ed50ec 1727 /*
17e1df07
DV		 1728 * Wakeup waiting processes so that the reset work function
1729 * i915_error_work_func doesn't deadlock trying to grab various
1730 * locks. By bumping the reset counter first, the woken
1731 * processes will see a reset in progress and back off,
1732 * releasing their locks and then wait for the reset completion.
1733 * We must do this for _all_ gpu waiters that might hold locks
1734 * that the reset work needs to acquire.
1735 *
1736 * Note: The wake_up serves as the required memory barrier to
1737 * ensure that the waiters see the updated value of the reset
1738 * counter atomic_t.
11ed50ec 1739 */
17e1df07 1740 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 1741 }
1742
122f46ba
DV		 1743 /*
1744 * Our reset work can grab modeset locks (since it needs to reset the
1745 * state of outstanding pagelips). Hence it must not be run on our own
1746 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1747 * code will deadlock.
1748 */
1749 schedule_work(&dev_priv->gpu_error.work);
8a905236
JB		 1750}
1751
21ad8330 1752static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 1753{
1754 drm_i915_private_t *dev_priv = dev->dev_private;
1755 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1757 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1758 struct intel_unpin_work *work;
1759 unsigned long flags;
1760 bool stall_detected;
1761
1762 /* Ignore early vblank irqs */
1763 if (intel_crtc == NULL)
1764 return;
1765
1766 spin_lock_irqsave(&dev->event_lock, flags);
1767 work = intel_crtc->unpin_work;
1768
e7d841ca
CW		 1769 if (work == NULL ||
1770 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1771 !work->enable_stall_check) {
4e5359cd
SF		 1772 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1773 spin_unlock_irqrestore(&dev->event_lock, flags);
1774 return;
1775 }
1776
1777 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1778 obj = work->pending_flip_obj;
a6c45cf0 1779 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1780 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 1781 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 1782 i915_gem_obj_ggtt_offset(obj);
4e5359cd 1783 } else {
9db4a9c7 1784 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 1785 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
01f2c773 1786 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1787 crtc->x * crtc->fb->bits_per_pixel/8);
1788 }
1789
1790 spin_unlock_irqrestore(&dev->event_lock, flags);
1791
1792 if (stall_detected) {
1793 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1794 intel_prepare_page_flip(dev, intel_crtc->plane);
1795 }
1796}
1797
42f52ef8
KP		 1798/* Called from drm generic code, passed 'crtc' which
1799 * we use as a pipe index
1800 */
f71d4af4 1801static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1802{
1803 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1804 unsigned long irqflags;
71e0ffa5 1805
5eddb70b 1806 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1807 return -EINVAL;
0a3e67a4 1808
1ec14ad3 1809 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1810 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1811 i915_enable_pipestat(dev_priv, pipe,
1812 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1813 else
7c463586
KP		 1814 i915_enable_pipestat(dev_priv, pipe,
1815 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1816
1817 /* maintain vblank delivery even in deep C-states */
1818 if (dev_priv->info->gen == 3)
6b26c86d 1819 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1820 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1821
0a3e67a4
JB		 1822 return 0;
1823}
1824
f71d4af4 1825static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1826{
1827 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1828 unsigned long irqflags;
b518421f
PZ		 1829 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1830 DE_PIPE_VBLANK_ILK(pipe);
f796cf8f
JB		 1831
1832 if (!i915_pipe_enabled(dev, pipe))
1833 return -EINVAL;
1834
1835 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 1836 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 1837 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1838
1839 return 0;
1840}
1841
7e231dbe
JB		 1842static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1843{
1844 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1845 unsigned long irqflags;
31acc7f5 1846 u32 imr;
7e231dbe
JB		 1847
1848 if (!i915_pipe_enabled(dev, pipe))
1849 return -EINVAL;
1850
1851 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1852 imr = I915_READ(VLV_IMR);
31acc7f5 1853 if (pipe == 0)
7e231dbe 1854 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1855 else
7e231dbe 1856 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1857 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1858 i915_enable_pipestat(dev_priv, pipe,
1859 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1860 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1861
1862 return 0;
1863}
1864
42f52ef8
KP		 1865/* Called from drm generic code, passed 'crtc' which
1866 * we use as a pipe index
1867 */
f71d4af4 1868static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1869{
1870 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1871 unsigned long irqflags;
0a3e67a4 1872
1ec14ad3 1873 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1874 if (dev_priv->info->gen == 3)
6b26c86d 1875 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1876
f796cf8f
JB		 1877 i915_disable_pipestat(dev_priv, pipe,
1878 PIPE_VBLANK_INTERRUPT_ENABLE |
1879 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1880 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1881}
1882
f71d4af4 1883static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1884{
1885 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1886 unsigned long irqflags;
b518421f
PZ		 1887 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1888 DE_PIPE_VBLANK_ILK(pipe);
f796cf8f
JB		 1889
1890 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 1891 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 1892 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1893}
1894
7e231dbe
JB		 1895static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1896{
1897 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1898 unsigned long irqflags;
31acc7f5 1899 u32 imr;
7e231dbe
JB		 1900
1901 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1902 i915_disable_pipestat(dev_priv, pipe,
1903 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1904 imr = I915_READ(VLV_IMR);
31acc7f5 1905 if (pipe == 0)
7e231dbe 1906 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1907 else
7e231dbe 1908 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1909 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1910 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1911}
1912
893eead0
CW		 1913static u32
1914ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1915{
893eead0
CW		 1916 return list_entry(ring->request_list.prev,
1917 struct drm_i915_gem_request, list)->seqno;
1918}
1919
9107e9d2
CW		 1920static bool
1921ring_idle(struct intel_ring_buffer *ring, u32 seqno)
1922{
1923 return (list_empty(&ring->request_list) ||
1924 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 1925}
1926
6274f212
CW		 1927static struct intel_ring_buffer *
1928semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 1929{
1930 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 1931 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 1932
1933 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1934 if ((ipehr & ~(0x3 << 16)) !=
1935 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 1936 return NULL;
a24a11e6
CW		 1937
1938 /* ACTHD is likely pointing to the dword after the actual command,
1939 * so scan backwards until we find the MBOX.
1940 */
6274f212 1941 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 1942 acthd_min = max((int)acthd - 3 * 4, 0);
1943 do {
1944 cmd = ioread32(ring->virtual_start + acthd);
1945 if (cmd == ipehr)
1946 break;
1947
1948 acthd -= 4;
1949 if (acthd < acthd_min)
6274f212 1950 return NULL;
a24a11e6
CW		 1951 } while (1);
1952
6274f212
CW		 1953 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
1954 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 1955}
1956
6274f212
CW		 1957static int semaphore_passed(struct intel_ring_buffer *ring)
1958{
1959 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1960 struct intel_ring_buffer *signaller;
1961 u32 seqno, ctl;
1962
1963 ring->hangcheck.deadlock = true;
1964
1965 signaller = semaphore_waits_for(ring, &seqno);
1966 if (signaller == NULL || signaller->hangcheck.deadlock)
1967 return -1;
1968
1969 /* cursory check for an unkickable deadlock */
1970 ctl = I915_READ_CTL(signaller);
1971 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
1972 return -1;
1973
1974 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
1975}
1976
1977static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
1978{
1979 struct intel_ring_buffer *ring;
1980 int i;
1981
1982 for_each_ring(ring, dev_priv, i)
1983 ring->hangcheck.deadlock = false;
1984}
1985
ad8beaea
MK		 1986static enum intel_ring_hangcheck_action
1987ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 1988{
1989 struct drm_device *dev = ring->dev;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 1991 u32 tmp;
1992
6274f212 1993 if (ring->hangcheck.acthd != acthd)
f2f4d82f 1994 return HANGCHECK_ACTIVE;
6274f212 1995
9107e9d2 1996 if (IS_GEN2(dev))
f2f4d82f 1997 return HANGCHECK_HUNG;
9107e9d2
CW		 1998
1999 /* Is the chip hanging on a WAIT_FOR_EVENT?
2000 * If so we can simply poke the RB_WAIT bit
2001 * and break the hang. This should work on
2002 * all but the second generation chipsets.
2003 */
2004 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 2005 if (tmp & RING_WAIT) {
2006 DRM_ERROR("Kicking stuck wait on %s\n",
2007 ring->name);
09e14bf3 2008 i915_handle_error(dev, false);
1ec14ad3 2009 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2010 return HANGCHECK_KICK;
6274f212
CW		 2011 }
2012
2013 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2014 switch (semaphore_passed(ring)) {
2015 default:
f2f4d82f 2016 return HANGCHECK_HUNG;
6274f212
CW		 2017 case 1:
2018 DRM_ERROR("Kicking stuck semaphore on %s\n",
2019 ring->name);
09e14bf3 2020 i915_handle_error(dev, false);
6274f212 2021 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2022 return HANGCHECK_KICK;
6274f212 2023 case 0:
f2f4d82f 2024 return HANGCHECK_WAIT;
6274f212 2025 }
9107e9d2 2026 }
ed5cbb03 2027
f2f4d82f 2028 return HANGCHECK_HUNG;
ed5cbb03
MK		 2029}
2030
f65d9421
BG		 2031/**
2032 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2033 * batchbuffers in a long time. We keep track per ring seqno progress and
2034 * if there are no progress, hangcheck score for that ring is increased.
2035 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2036 * we kick the ring. If we see no progress on three subsequent calls
2037 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 2038 */
a658b5d2 2039static void i915_hangcheck_elapsed(unsigned long data)
f65d9421
BG		 2040{
2041 struct drm_device *dev = (struct drm_device *)data;
2042 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 2043 struct intel_ring_buffer *ring;
b4519513 2044 int i;
05407ff8 2045 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2046 bool stuck[I915_NUM_RINGS] = { 0 };
2047#define BUSY 1
2048#define KICK 5
2049#define HUNG 20
2050#define FIRE 30
893eead0 2051
3e0dc6b0
BW		 2052 if (!i915_enable_hangcheck)
2053 return;
2054
b4519513 2055 for_each_ring(ring, dev_priv, i) {
05407ff8 2056 u32 seqno, acthd;
9107e9d2 2057 bool busy = true;
05407ff8 2058
6274f212
CW		 2059 semaphore_clear_deadlocks(dev_priv);
2060
05407ff8
MK		 2061 seqno = ring->get_seqno(ring, false);
2062 acthd = intel_ring_get_active_head(ring);
b4519513 2063
9107e9d2
CW		 2064 if (ring->hangcheck.seqno == seqno) {
2065 if (ring_idle(ring, seqno)) {
da661464
MK		 2066 ring->hangcheck.action = HANGCHECK_IDLE;
2067
9107e9d2
CW		 2068 if (waitqueue_active(&ring->irq_queue)) {
2069 /* Issue a wake-up to catch stuck h/w. */
094f9a54
CW		 2070 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2071 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2072 ring->name);
2073 wake_up_all(&ring->irq_queue);
2074 }
2075 /* Safeguard against driver failure */
2076 ring->hangcheck.score += BUSY;
9107e9d2
CW		 2077 } else
2078 busy = false;
05407ff8 2079 } else {
6274f212
CW		 2080 /* We always increment the hangcheck score
2081 * if the ring is busy and still processing
2082 * the same request, so that no single request
2083 * can run indefinitely (such as a chain of
2084 * batches). The only time we do not increment
2085 * the hangcheck score on this ring, if this
2086 * ring is in a legitimate wait for another
2087 * ring. In that case the waiting ring is a
2088 * victim and we want to be sure we catch the
2089 * right culprit. Then every time we do kick
2090 * the ring, add a small increment to the
2091 * score so that we can catch a batch that is
2092 * being repeatedly kicked and so responsible
2093 * for stalling the machine.
2094 */
ad8beaea
MK		 2095 ring->hangcheck.action = ring_stuck(ring,
2096 acthd);
2097
2098 switch (ring->hangcheck.action) {
da661464 2099 case HANGCHECK_IDLE:
f2f4d82f 2100 case HANGCHECK_WAIT:
6274f212 2101 break;
f2f4d82f 2102 case HANGCHECK_ACTIVE:
ea04cb31 2103 ring->hangcheck.score += BUSY;
6274f212 2104 break;
f2f4d82f 2105 case HANGCHECK_KICK:
ea04cb31 2106 ring->hangcheck.score += KICK;
6274f212 2107 break;
f2f4d82f 2108 case HANGCHECK_HUNG:
ea04cb31 2109 ring->hangcheck.score += HUNG;
6274f212
CW		 2110 stuck[i] = true;
2111 break;
2112 }
05407ff8 2113 }
9107e9d2 2114 } else {
da661464
MK		 2115 ring->hangcheck.action = HANGCHECK_ACTIVE;
2116
9107e9d2
CW		 2117 /* Gradually reduce the count so that we catch DoS
2118 * attempts across multiple batches.
2119 */
2120 if (ring->hangcheck.score > 0)
2121 ring->hangcheck.score--;
d1e61e7f
CW		 2122 }
2123
05407ff8
MK		 2124 ring->hangcheck.seqno = seqno;
2125 ring->hangcheck.acthd = acthd;
9107e9d2 2126 busy_count += busy;
893eead0 2127 }
b9201c14 2128
92cab734 2129 for_each_ring(ring, dev_priv, i) {
9107e9d2 2130 if (ring->hangcheck.score > FIRE) {
b8d88d1d
DV		 2131 DRM_INFO("%s on %s\n",
2132 stuck[i] ? "stuck" : "no progress",
2133 ring->name);
a43adf07 2134 rings_hung++;
92cab734
MK		 2135 }
2136 }
2137
05407ff8
MK		 2138 if (rings_hung)
2139 return i915_handle_error(dev, true);
f65d9421 2140
05407ff8
MK		 2141 if (busy_count)
2142 /* Reset timer case chip hangs without another request
2143 * being added */
10cd45b6
MK		 2144 i915_queue_hangcheck(dev);
2145}
2146
2147void i915_queue_hangcheck(struct drm_device *dev)
2148{
2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150 if (!i915_enable_hangcheck)
2151 return;
2152
2153 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2154 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2155}
2156
91738a95
PZ		 2157static void ibx_irq_preinstall(struct drm_device *dev)
2158{
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2160
2161 if (HAS_PCH_NOP(dev))
2162 return;
2163
2164 /* south display irq */
2165 I915_WRITE(SDEIMR, 0xffffffff);
2166 /*
2167 * SDEIER is also touched by the interrupt handler to work around missed
2168 * PCH interrupts. Hence we can't update it after the interrupt handler
2169 * is enabled - instead we unconditionally enable all PCH interrupt
2170 * sources here, but then only unmask them as needed with SDEIMR.
2171 */
2172 I915_WRITE(SDEIER, 0xffffffff);
2173 POSTING_READ(SDEIER);
2174}
2175
d18ea1b5
DV		 2176static void gen5_gt_irq_preinstall(struct drm_device *dev)
2177{
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179
2180 /* and GT */
2181 I915_WRITE(GTIMR, 0xffffffff);
2182 I915_WRITE(GTIER, 0x0);
2183 POSTING_READ(GTIER);
2184
2185 if (INTEL_INFO(dev)->gen >= 6) {
2186 /* and PM */
2187 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2188 I915_WRITE(GEN6_PMIER, 0x0);
2189 POSTING_READ(GEN6_PMIER);
2190 }
2191}
2192
1da177e4
LT		 2193/* drm_dma.h hooks
2194*/
f71d4af4 2195static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2196{
2197 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2198
4697995b
JB		 2199 atomic_set(&dev_priv->irq_received, 0);
2200
036a4a7d 2201 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2202
036a4a7d
ZW		 2203 I915_WRITE(DEIMR, 0xffffffff);
2204 I915_WRITE(DEIER, 0x0);
3143a2bf 2205 POSTING_READ(DEIER);
036a4a7d 2206
d18ea1b5 2207 gen5_gt_irq_preinstall(dev);
c650156a 2208
91738a95 2209 ibx_irq_preinstall(dev);
7d99163d
BW		 2210}
2211
7e231dbe
JB		 2212static void valleyview_irq_preinstall(struct drm_device *dev)
2213{
2214 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2215 int pipe;
2216
2217 atomic_set(&dev_priv->irq_received, 0);
2218
7e231dbe
JB		 2219 /* VLV magic */
2220 I915_WRITE(VLV_IMR, 0);
2221 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2222 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2223 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2224
7e231dbe
JB		 2225 /* and GT */
2226 I915_WRITE(GTIIR, I915_READ(GTIIR));
2227 I915_WRITE(GTIIR, I915_READ(GTIIR));
d18ea1b5
DV		 2228
2229 gen5_gt_irq_preinstall(dev);
7e231dbe
JB		 2230
2231 I915_WRITE(DPINVGTT, 0xff);
2232
2233 I915_WRITE(PORT_HOTPLUG_EN, 0);
2234 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2235 for_each_pipe(pipe)
2236 I915_WRITE(PIPESTAT(pipe), 0xffff);
2237 I915_WRITE(VLV_IIR, 0xffffffff);
2238 I915_WRITE(VLV_IMR, 0xffffffff);
2239 I915_WRITE(VLV_IER, 0x0);
2240 POSTING_READ(VLV_IER);
2241}
2242
82a28bcf 2243static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2244{
2245 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2246 struct drm_mode_config *mode_config = &dev->mode_config;
2247 struct intel_encoder *intel_encoder;
fee884ed 2248 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2249
2250 if (HAS_PCH_IBX(dev)) {
fee884ed 2251 hotplug_irqs = SDE_HOTPLUG_MASK;
82a28bcf 2252 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2253 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2254 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2255 } else {
fee884ed 2256 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
82a28bcf 2257 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2258 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2259 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2260 }
7fe0b973 2261
fee884ed 2262 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 2263
2264 /*
2265 * Enable digital hotplug on the PCH, and configure the DP short pulse
2266 * duration to 2ms (which is the minimum in the Display Port spec)
2267 *
2268 * This register is the same on all known PCH chips.
2269 */
7fe0b973
KP		 2270 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2271 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2272 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2273 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2274 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2275 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2276}
2277
d46da437
PZ		 2278static void ibx_irq_postinstall(struct drm_device *dev)
2279{
2280 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2281 u32 mask;
e5868a31 2282
692a04cf
DV		 2283 if (HAS_PCH_NOP(dev))
2284 return;
2285
8664281b
PZ		 2286 if (HAS_PCH_IBX(dev)) {
2287 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2288 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2289 } else {
2290 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2291
2292 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2293 }
ab5c608b 2294
d46da437
PZ		 2295 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2296 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2297}
2298
0a9a8c91
DV		 2299static void gen5_gt_irq_postinstall(struct drm_device *dev)
2300{
2301 struct drm_i915_private *dev_priv = dev->dev_private;
2302 u32 pm_irqs, gt_irqs;
2303
2304 pm_irqs = gt_irqs = 0;
2305
2306 dev_priv->gt_irq_mask = ~0;
040d2baa 2307 if (HAS_L3_DPF(dev)) {
0a9a8c91 2308 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 2309 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2310 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 2311 }
2312
2313 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2314 if (IS_GEN5(dev)) {
2315 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2316 ILK_BSD_USER_INTERRUPT;
2317 } else {
2318 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2319 }
2320
2321 I915_WRITE(GTIIR, I915_READ(GTIIR));
2322 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2323 I915_WRITE(GTIER, gt_irqs);
2324 POSTING_READ(GTIER);
2325
2326 if (INTEL_INFO(dev)->gen >= 6) {
2327 pm_irqs |= GEN6_PM_RPS_EVENTS;
2328
2329 if (HAS_VEBOX(dev))
2330 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2331
605cd25b 2332 dev_priv->pm_irq_mask = 0xffffffff;
0a9a8c91 2333 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
605cd25b 2334 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
0a9a8c91
DV		 2335 I915_WRITE(GEN6_PMIER, pm_irqs);
2336 POSTING_READ(GEN6_PMIER);
2337 }
2338}
2339
f71d4af4 2340static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2341{
4bc9d430 2342 unsigned long irqflags;
036a4a7d 2343 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8e76f8dc
PZ		 2344 u32 display_mask, extra_mask;
2345
2346 if (INTEL_INFO(dev)->gen >= 7) {
2347 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2348 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2349 DE_PLANEB_FLIP_DONE_IVB |
2350 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2351 DE_ERR_INT_IVB);
2352 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2353 DE_PIPEA_VBLANK_IVB);
2354
2355 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2356 } else {
2357 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2358 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2359 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2360 DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
2361 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2362 }
036a4a7d 2363
1ec14ad3 2364 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2365
2366 /* should always can generate irq */
2367 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2368 I915_WRITE(DEIMR, dev_priv->irq_mask);
8e76f8dc 2369 I915_WRITE(DEIER, display_mask | extra_mask);
3143a2bf 2370 POSTING_READ(DEIER);
036a4a7d 2371
0a9a8c91 2372 gen5_gt_irq_postinstall(dev);
036a4a7d 2373
d46da437 2374 ibx_irq_postinstall(dev);
7fe0b973 2375
f97108d1 2376 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2377 /* Enable PCU event interrupts
2378 *
2379 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2380 * setup is guaranteed to run in single-threaded context. But we
2381 * need it to make the assert_spin_locked happy. */
2382 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2383 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2384 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2385 }
2386
036a4a7d
ZW		 2387 return 0;
2388}
2389
7e231dbe
JB		 2390static int valleyview_irq_postinstall(struct drm_device *dev)
2391{
2392 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2393 u32 enable_mask;
31acc7f5 2394 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
b79480ba 2395 unsigned long irqflags;
7e231dbe
JB		 2396
2397 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2398 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2399 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2400 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2401 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2402
31acc7f5
JB		 2403 /*
2404 *Leave vblank interrupts masked initially. enable/disable will
2405 * toggle them based on usage.
2406 */
2407 dev_priv->irq_mask = (~enable_mask) |
2408 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2409 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2410
20afbda2
DV		 2411 I915_WRITE(PORT_HOTPLUG_EN, 0);
2412 POSTING_READ(PORT_HOTPLUG_EN);
2413
7e231dbe
JB		 2414 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2415 I915_WRITE(VLV_IER, enable_mask);
2416 I915_WRITE(VLV_IIR, 0xffffffff);
2417 I915_WRITE(PIPESTAT(0), 0xffff);
2418 I915_WRITE(PIPESTAT(1), 0xffff);
2419 POSTING_READ(VLV_IER);
2420
b79480ba
DV		 2421 /* Interrupt setup is already guaranteed to be single-threaded, this is
2422 * just to make the assert_spin_locked check happy. */
2423 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2424 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2425 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5 2426 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
b79480ba 2427 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 2428
7e231dbe
JB		 2429 I915_WRITE(VLV_IIR, 0xffffffff);
2430 I915_WRITE(VLV_IIR, 0xffffffff);
2431
0a9a8c91 2432 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 2433
2434 /* ack & enable invalid PTE error interrupts */
2435#if 0 /* FIXME: add support to irq handler for checking these bits */
2436 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2437 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2438#endif
2439
2440 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2441
2442 return 0;
2443}
2444
7e231dbe
JB		 2445static void valleyview_irq_uninstall(struct drm_device *dev)
2446{
2447 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2448 int pipe;
2449
2450 if (!dev_priv)
2451 return;
2452
ac4c16c5
EE		 2453 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2454
7e231dbe
JB		 2455 for_each_pipe(pipe)
2456 I915_WRITE(PIPESTAT(pipe), 0xffff);
2457
2458 I915_WRITE(HWSTAM, 0xffffffff);
2459 I915_WRITE(PORT_HOTPLUG_EN, 0);
2460 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2461 for_each_pipe(pipe)
2462 I915_WRITE(PIPESTAT(pipe), 0xffff);
2463 I915_WRITE(VLV_IIR, 0xffffffff);
2464 I915_WRITE(VLV_IMR, 0xffffffff);
2465 I915_WRITE(VLV_IER, 0x0);
2466 POSTING_READ(VLV_IER);
2467}
2468
f71d4af4 2469static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2470{
2471 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2472
2473 if (!dev_priv)
2474 return;
2475
ac4c16c5
EE		 2476 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2477
036a4a7d
ZW		 2478 I915_WRITE(HWSTAM, 0xffffffff);
2479
2480 I915_WRITE(DEIMR, 0xffffffff);
2481 I915_WRITE(DEIER, 0x0);
2482 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2483 if (IS_GEN7(dev))
2484 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2485
2486 I915_WRITE(GTIMR, 0xffffffff);
2487 I915_WRITE(GTIER, 0x0);
2488 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2489
ab5c608b
BW		 2490 if (HAS_PCH_NOP(dev))
2491 return;
2492
192aac1f
KP		 2493 I915_WRITE(SDEIMR, 0xffffffff);
2494 I915_WRITE(SDEIER, 0x0);
2495 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2496 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2497 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2498}
2499
a266c7d5 2500static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2501{
2502 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2503 int pipe;
91e3738e 2504
a266c7d5 2505 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2506
9db4a9c7
JB		 2507 for_each_pipe(pipe)
2508 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2509 I915_WRITE16(IMR, 0xffff);
2510 I915_WRITE16(IER, 0x0);
2511 POSTING_READ16(IER);
c2798b19
CW		 2512}
2513
2514static int i8xx_irq_postinstall(struct drm_device *dev)
2515{
2516 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2517
c2798b19
CW		 2518 I915_WRITE16(EMR,
2519 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2520
2521 /* Unmask the interrupts that we always want on. */
2522 dev_priv->irq_mask =
2523 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2524 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2525 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2526 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2527 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2528 I915_WRITE16(IMR, dev_priv->irq_mask);
2529
2530 I915_WRITE16(IER,
2531 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2532 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2533 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2534 I915_USER_INTERRUPT);
2535 POSTING_READ16(IER);
2536
2537 return 0;
2538}
2539
90a72f87
VS		 2540/*
2541 * Returns true when a page flip has completed.
2542 */
2543static bool i8xx_handle_vblank(struct drm_device *dev,
2544 int pipe, u16 iir)
2545{
2546 drm_i915_private_t *dev_priv = dev->dev_private;
2547 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2548
2549 if (!drm_handle_vblank(dev, pipe))
2550 return false;
2551
2552 if ((iir & flip_pending) == 0)
2553 return false;
2554
2555 intel_prepare_page_flip(dev, pipe);
2556
2557 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2558 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2559 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2560 * the flip is completed (no longer pending). Since this doesn't raise
2561 * an interrupt per se, we watch for the change at vblank.
2562 */
2563 if (I915_READ16(ISR) & flip_pending)
2564 return false;
2565
2566 intel_finish_page_flip(dev, pipe);
2567
2568 return true;
2569}
2570
ff1f525e 2571static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2572{
2573 struct drm_device *dev = (struct drm_device *) arg;
2574 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2575 u16 iir, new_iir;
2576 u32 pipe_stats[2];
2577 unsigned long irqflags;
c2798b19
CW		 2578 int pipe;
2579 u16 flip_mask =
2580 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2581 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2582
2583 atomic_inc(&dev_priv->irq_received);
2584
2585 iir = I915_READ16(IIR);
2586 if (iir == 0)
2587 return IRQ_NONE;
2588
2589 while (iir & ~flip_mask) {
2590 /* Can't rely on pipestat interrupt bit in iir as it might
2591 * have been cleared after the pipestat interrupt was received.
2592 * It doesn't set the bit in iir again, but it still produces
2593 * interrupts (for non-MSI).
2594 */
2595 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2596 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2597 i915_handle_error(dev, false);
2598
2599 for_each_pipe(pipe) {
2600 int reg = PIPESTAT(pipe);
2601 pipe_stats[pipe] = I915_READ(reg);
2602
2603 /*
2604 * Clear the PIPE*STAT regs before the IIR
2605 */
2606 if (pipe_stats[pipe] & 0x8000ffff) {
2607 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2608 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2609 pipe_name(pipe));
2610 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19
CW		 2611 }
2612 }
2613 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2614
2615 I915_WRITE16(IIR, iir & ~flip_mask);
2616 new_iir = I915_READ16(IIR); /* Flush posted writes */
2617
d05c617e 2618 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2619
2620 if (iir & I915_USER_INTERRUPT)
2621 notify_ring(dev, &dev_priv->ring[RCS]);
2622
2623 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2624 i8xx_handle_vblank(dev, 0, iir))
2625 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 2626
2627 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2628 i8xx_handle_vblank(dev, 1, iir))
2629 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 2630
2631 iir = new_iir;
2632 }
2633
2634 return IRQ_HANDLED;
2635}
2636
2637static void i8xx_irq_uninstall(struct drm_device * dev)
2638{
2639 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2640 int pipe;
2641
c2798b19
CW		 2642 for_each_pipe(pipe) {
2643 /* Clear enable bits; then clear status bits */
2644 I915_WRITE(PIPESTAT(pipe), 0);
2645 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2646 }
2647 I915_WRITE16(IMR, 0xffff);
2648 I915_WRITE16(IER, 0x0);
2649 I915_WRITE16(IIR, I915_READ16(IIR));
2650}
2651
a266c7d5
CW		 2652static void i915_irq_preinstall(struct drm_device * dev)
2653{
2654 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2655 int pipe;
2656
2657 atomic_set(&dev_priv->irq_received, 0);
2658
2659 if (I915_HAS_HOTPLUG(dev)) {
2660 I915_WRITE(PORT_HOTPLUG_EN, 0);
2661 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2662 }
2663
00d98ebd 2664 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2665 for_each_pipe(pipe)
2666 I915_WRITE(PIPESTAT(pipe), 0);
2667 I915_WRITE(IMR, 0xffffffff);
2668 I915_WRITE(IER, 0x0);
2669 POSTING_READ(IER);
2670}
2671
2672static int i915_irq_postinstall(struct drm_device *dev)
2673{
2674 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2675 u32 enable_mask;
a266c7d5 2676
38bde180
CW		 2677 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2678
2679 /* Unmask the interrupts that we always want on. */
2680 dev_priv->irq_mask =
2681 ~(I915_ASLE_INTERRUPT |
2682 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2683 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2684 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2685 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2686 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2687
2688 enable_mask =
2689 I915_ASLE_INTERRUPT |
2690 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2691 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2692 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2693 I915_USER_INTERRUPT;
2694
a266c7d5 2695 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 2696 I915_WRITE(PORT_HOTPLUG_EN, 0);
2697 POSTING_READ(PORT_HOTPLUG_EN);
2698
a266c7d5
CW		 2699 /* Enable in IER... */
2700 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2701 /* and unmask in IMR */
2702 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2703 }
2704
a266c7d5
CW		 2705 I915_WRITE(IMR, dev_priv->irq_mask);
2706 I915_WRITE(IER, enable_mask);
2707 POSTING_READ(IER);
2708
f49e38dd 2709 i915_enable_asle_pipestat(dev);
20afbda2
DV		 2710
2711 return 0;
2712}
2713
90a72f87
VS		 2714/*
2715 * Returns true when a page flip has completed.
2716 */
2717static bool i915_handle_vblank(struct drm_device *dev,
2718 int plane, int pipe, u32 iir)
2719{
2720 drm_i915_private_t *dev_priv = dev->dev_private;
2721 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2722
2723 if (!drm_handle_vblank(dev, pipe))
2724 return false;
2725
2726 if ((iir & flip_pending) == 0)
2727 return false;
2728
2729 intel_prepare_page_flip(dev, plane);
2730
2731 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2732 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2733 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2734 * the flip is completed (no longer pending). Since this doesn't raise
2735 * an interrupt per se, we watch for the change at vblank.
2736 */
2737 if (I915_READ(ISR) & flip_pending)
2738 return false;
2739
2740 intel_finish_page_flip(dev, pipe);
2741
2742 return true;
2743}
2744
ff1f525e 2745static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2746{
2747 struct drm_device *dev = (struct drm_device *) arg;
2748 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2749 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2750 unsigned long irqflags;
38bde180
CW		 2751 u32 flip_mask =
2752 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2753 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 2754 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2755
2756 atomic_inc(&dev_priv->irq_received);
2757
2758 iir = I915_READ(IIR);
38bde180
CW		 2759 do {
2760 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2761 bool blc_event = false;
a266c7d5
CW		 2762
2763 /* Can't rely on pipestat interrupt bit in iir as it might
2764 * have been cleared after the pipestat interrupt was received.
2765 * It doesn't set the bit in iir again, but it still produces
2766 * interrupts (for non-MSI).
2767 */
2768 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2769 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2770 i915_handle_error(dev, false);
2771
2772 for_each_pipe(pipe) {
2773 int reg = PIPESTAT(pipe);
2774 pipe_stats[pipe] = I915_READ(reg);
2775
38bde180 2776 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2777 if (pipe_stats[pipe] & 0x8000ffff) {
2778 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2779 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2780 pipe_name(pipe));
2781 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2782 irq_received = true;
a266c7d5
CW		 2783 }
2784 }
2785 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2786
2787 if (!irq_received)
2788 break;
2789
a266c7d5
CW		 2790 /* Consume port. Then clear IIR or we'll miss events */
2791 if ((I915_HAS_HOTPLUG(dev)) &&
2792 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2793 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 2794 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 2795
2796 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2797 hotplug_status);
91d131d2
DV		 2798
2799 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
2800
a266c7d5 2801 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2802 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2803 }
2804
38bde180 2805 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2806 new_iir = I915_READ(IIR); /* Flush posted writes */
2807
a266c7d5
CW		 2808 if (iir & I915_USER_INTERRUPT)
2809 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2810
a266c7d5 2811 for_each_pipe(pipe) {
38bde180
CW		 2812 int plane = pipe;
2813 if (IS_MOBILE(dev))
2814 plane = !plane;
90a72f87 2815
8291ee90 2816 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2817 i915_handle_vblank(dev, plane, pipe, iir))
2818 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 2819
2820 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2821 blc_event = true;
2822 }
2823
a266c7d5
CW		 2824 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2825 intel_opregion_asle_intr(dev);
2826
2827 /* With MSI, interrupts are only generated when iir
2828 * transitions from zero to nonzero. If another bit got
2829 * set while we were handling the existing iir bits, then
2830 * we would never get another interrupt.
2831 *
2832 * This is fine on non-MSI as well, as if we hit this path
2833 * we avoid exiting the interrupt handler only to generate
2834 * another one.
2835 *
2836 * Note that for MSI this could cause a stray interrupt report
2837 * if an interrupt landed in the time between writing IIR and
2838 * the posting read. This should be rare enough to never
2839 * trigger the 99% of 100,000 interrupts test for disabling
2840 * stray interrupts.
2841 */
38bde180 2842 ret = IRQ_HANDLED;
a266c7d5 2843 iir = new_iir;
38bde180 2844 } while (iir & ~flip_mask);
a266c7d5 2845
d05c617e 2846 i915_update_dri1_breadcrumb(dev);
8291ee90 2847
a266c7d5
CW		 2848 return ret;
2849}
2850
2851static void i915_irq_uninstall(struct drm_device * dev)
2852{
2853 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2854 int pipe;
2855
ac4c16c5
EE		 2856 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2857
a266c7d5
CW		 2858 if (I915_HAS_HOTPLUG(dev)) {
2859 I915_WRITE(PORT_HOTPLUG_EN, 0);
2860 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2861 }
2862
00d98ebd 2863 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2864 for_each_pipe(pipe) {
2865 /* Clear enable bits; then clear status bits */
a266c7d5 2866 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2867 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2868 }
a266c7d5
CW		 2869 I915_WRITE(IMR, 0xffffffff);
2870 I915_WRITE(IER, 0x0);
2871
a266c7d5
CW		 2872 I915_WRITE(IIR, I915_READ(IIR));
2873}
2874
2875static void i965_irq_preinstall(struct drm_device * dev)
2876{
2877 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2878 int pipe;
2879
2880 atomic_set(&dev_priv->irq_received, 0);
2881
adca4730
CW		 2882 I915_WRITE(PORT_HOTPLUG_EN, 0);
2883 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2884
2885 I915_WRITE(HWSTAM, 0xeffe);
2886 for_each_pipe(pipe)
2887 I915_WRITE(PIPESTAT(pipe), 0);
2888 I915_WRITE(IMR, 0xffffffff);
2889 I915_WRITE(IER, 0x0);
2890 POSTING_READ(IER);
2891}
2892
2893static int i965_irq_postinstall(struct drm_device *dev)
2894{
2895 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2896 u32 enable_mask;
a266c7d5 2897 u32 error_mask;
b79480ba 2898 unsigned long irqflags;
a266c7d5 2899
a266c7d5 2900 /* Unmask the interrupts that we always want on. */
bbba0a97 2901 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2902 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2903 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2904 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2905 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2906 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2907 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2908
2909 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 2910 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2911 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 2912 enable_mask |= I915_USER_INTERRUPT;
2913
2914 if (IS_G4X(dev))
2915 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 2916
b79480ba
DV		 2917 /* Interrupt setup is already guaranteed to be single-threaded, this is
2918 * just to make the assert_spin_locked check happy. */
2919 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
515ac2bb 2920 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
b79480ba 2921 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 2922
a266c7d5
CW		 2923 /*
2924 * Enable some error detection, note the instruction error mask
2925 * bit is reserved, so we leave it masked.
2926 */
2927 if (IS_G4X(dev)) {
2928 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2929 GM45_ERROR_MEM_PRIV |
2930 GM45_ERROR_CP_PRIV |
2931 I915_ERROR_MEMORY_REFRESH);
2932 } else {
2933 error_mask = ~(I915_ERROR_PAGE_TABLE |
2934 I915_ERROR_MEMORY_REFRESH);
2935 }
2936 I915_WRITE(EMR, error_mask);
2937
2938 I915_WRITE(IMR, dev_priv->irq_mask);
2939 I915_WRITE(IER, enable_mask);
2940 POSTING_READ(IER);
2941
20afbda2
DV		 2942 I915_WRITE(PORT_HOTPLUG_EN, 0);
2943 POSTING_READ(PORT_HOTPLUG_EN);
2944
f49e38dd 2945 i915_enable_asle_pipestat(dev);
20afbda2
DV		 2946
2947 return 0;
2948}
2949
bac56d5b 2950static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 2951{
2952 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 2953 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 2954 struct intel_encoder *intel_encoder;
20afbda2
DV		 2955 u32 hotplug_en;
2956
b5ea2d56
DV		 2957 assert_spin_locked(&dev_priv->irq_lock);
2958
bac56d5b
EE		 2959 if (I915_HAS_HOTPLUG(dev)) {
2960 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2961 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2962 /* Note HDMI and DP share hotplug bits */
e5868a31 2963 /* enable bits are the same for all generations */
cd569aed
EE		 2964 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2965 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2966 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 2967 /* Programming the CRT detection parameters tends
2968 to generate a spurious hotplug event about three
2969 seconds later. So just do it once.
2970 */
2971 if (IS_G4X(dev))
2972 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 2973 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 2974 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 2975
bac56d5b
EE		 2976 /* Ignore TV since it's buggy */
2977 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2978 }
a266c7d5
CW		 2979}
2980
ff1f525e 2981static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2982{
2983 struct drm_device *dev = (struct drm_device *) arg;
2984 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2985 u32 iir, new_iir;
2986 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2987 unsigned long irqflags;
2988 int irq_received;
2989 int ret = IRQ_NONE, pipe;
21ad8330
VS		 2990 u32 flip_mask =
2991 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2992 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 2993
2994 atomic_inc(&dev_priv->irq_received);
2995
2996 iir = I915_READ(IIR);
2997
a266c7d5 2998 for (;;) {
2c8ba29f
CW		 2999 bool blc_event = false;
3000
21ad8330 3001 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 3002
3003 /* Can't rely on pipestat interrupt bit in iir as it might
3004 * have been cleared after the pipestat interrupt was received.
3005 * It doesn't set the bit in iir again, but it still produces
3006 * interrupts (for non-MSI).
3007 */
3008 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3009 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3010 i915_handle_error(dev, false);
3011
3012 for_each_pipe(pipe) {
3013 int reg = PIPESTAT(pipe);
3014 pipe_stats[pipe] = I915_READ(reg);
3015
3016 /*
3017 * Clear the PIPE*STAT regs before the IIR
3018 */
3019 if (pipe_stats[pipe] & 0x8000ffff) {
3020 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3021 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3022 pipe_name(pipe));
3023 I915_WRITE(reg, pipe_stats[pipe]);
3024 irq_received = 1;
3025 }
3026 }
3027 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3028
3029 if (!irq_received)
3030 break;
3031
3032 ret = IRQ_HANDLED;
3033
3034 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3035 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3036 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3037 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3038 HOTPLUG_INT_STATUS_G4X :
4f7fd709 3039 HOTPLUG_INT_STATUS_I915);
a266c7d5
CW		 3040
3041 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3042 hotplug_status);
91d131d2
DV		 3043
3044 intel_hpd_irq_handler(dev, hotplug_trigger,
3045 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3046
a266c7d5
CW		 3047 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3048 I915_READ(PORT_HOTPLUG_STAT);
3049 }
3050
21ad8330 3051 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3052 new_iir = I915_READ(IIR); /* Flush posted writes */
3053
a266c7d5
CW		 3054 if (iir & I915_USER_INTERRUPT)
3055 notify_ring(dev, &dev_priv->ring[RCS]);
3056 if (iir & I915_BSD_USER_INTERRUPT)
3057 notify_ring(dev, &dev_priv->ring[VCS]);
3058
a266c7d5 3059 for_each_pipe(pipe) {
2c8ba29f 3060 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3061 i915_handle_vblank(dev, pipe, pipe, iir))
3062 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3063
3064 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3065 blc_event = true;
3066 }
3067
3068
3069 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3070 intel_opregion_asle_intr(dev);
3071
515ac2bb
DV		 3072 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3073 gmbus_irq_handler(dev);
3074
a266c7d5
CW		 3075 /* With MSI, interrupts are only generated when iir
3076 * transitions from zero to nonzero. If another bit got
3077 * set while we were handling the existing iir bits, then
3078 * we would never get another interrupt.
3079 *
3080 * This is fine on non-MSI as well, as if we hit this path
3081 * we avoid exiting the interrupt handler only to generate
3082 * another one.
3083 *
3084 * Note that for MSI this could cause a stray interrupt report
3085 * if an interrupt landed in the time between writing IIR and
3086 * the posting read. This should be rare enough to never
3087 * trigger the 99% of 100,000 interrupts test for disabling
3088 * stray interrupts.
3089 */
3090 iir = new_iir;
3091 }
3092
d05c617e 3093 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3094
a266c7d5
CW		 3095 return ret;
3096}
3097
3098static void i965_irq_uninstall(struct drm_device * dev)
3099{
3100 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3101 int pipe;
3102
3103 if (!dev_priv)
3104 return;
3105
ac4c16c5
EE		 3106 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3107
adca4730
CW		 3108 I915_WRITE(PORT_HOTPLUG_EN, 0);
3109 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3110
3111 I915_WRITE(HWSTAM, 0xffffffff);
3112 for_each_pipe(pipe)
3113 I915_WRITE(PIPESTAT(pipe), 0);
3114 I915_WRITE(IMR, 0xffffffff);
3115 I915_WRITE(IER, 0x0);
3116
3117 for_each_pipe(pipe)
3118 I915_WRITE(PIPESTAT(pipe),
3119 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3120 I915_WRITE(IIR, I915_READ(IIR));
3121}
3122
ac4c16c5
EE		 3123static void i915_reenable_hotplug_timer_func(unsigned long data)
3124{
3125 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3126 struct drm_device *dev = dev_priv->dev;
3127 struct drm_mode_config *mode_config = &dev->mode_config;
3128 unsigned long irqflags;
3129 int i;
3130
3131 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3132 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3133 struct drm_connector *connector;
3134
3135 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3136 continue;
3137
3138 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3139
3140 list_for_each_entry(connector, &mode_config->connector_list, head) {
3141 struct intel_connector *intel_connector = to_intel_connector(connector);
3142
3143 if (intel_connector->encoder->hpd_pin == i) {
3144 if (connector->polled != intel_connector->polled)
3145 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3146 drm_get_connector_name(connector));
3147 connector->polled = intel_connector->polled;
3148 if (!connector->polled)
3149 connector->polled = DRM_CONNECTOR_POLL_HPD;
3150 }
3151 }
3152 }
3153 if (dev_priv->display.hpd_irq_setup)
3154 dev_priv->display.hpd_irq_setup(dev);
3155 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3156}
3157
f71d4af4
JB		 3158void intel_irq_init(struct drm_device *dev)
3159{
8b2e326d
CW		 3160 struct drm_i915_private *dev_priv = dev->dev_private;
3161
3162 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3163 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3164 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3165 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3166
99584db3
DV		 3167 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3168 i915_hangcheck_elapsed,
61bac78e 3169 (unsigned long) dev);
ac4c16c5
EE		 3170 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3171 (unsigned long) dev_priv);
61bac78e 3172
97a19a24 3173 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3174
7d4e146f 3175 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3176 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3177 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
391f75e2
VS		 3178 } else {
3179 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3180 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 3181 }
3182
c2baf4b7 3183 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
c3613de9 3184 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
c2baf4b7
VS		 3185 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3186 }
f71d4af4 3187
7e231dbe
JB		 3188 if (IS_VALLEYVIEW(dev)) {
3189 dev->driver->irq_handler = valleyview_irq_handler;
3190 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3191 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3192 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3193 dev->driver->enable_vblank = valleyview_enable_vblank;
3194 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3195 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
f71d4af4
JB		 3196 } else if (HAS_PCH_SPLIT(dev)) {
3197 dev->driver->irq_handler = ironlake_irq_handler;
3198 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3199 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3200 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3201 dev->driver->enable_vblank = ironlake_enable_vblank;
3202 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3203 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3204 } else {
c2798b19
CW		 3205 if (INTEL_INFO(dev)->gen == 2) {
3206 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3207 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3208 dev->driver->irq_handler = i8xx_irq_handler;
3209 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3210 } else if (INTEL_INFO(dev)->gen == 3) {
3211 dev->driver->irq_preinstall = i915_irq_preinstall;
3212 dev->driver->irq_postinstall = i915_irq_postinstall;
3213 dev->driver->irq_uninstall = i915_irq_uninstall;
3214 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3215 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3216 } else {
a266c7d5
CW		 3217 dev->driver->irq_preinstall = i965_irq_preinstall;
3218 dev->driver->irq_postinstall = i965_irq_postinstall;
3219 dev->driver->irq_uninstall = i965_irq_uninstall;
3220 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3221 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3222 }
f71d4af4
JB		 3223 dev->driver->enable_vblank = i915_enable_vblank;
3224 dev->driver->disable_vblank = i915_disable_vblank;
3225 }
3226}
20afbda2
DV		 3227
3228void intel_hpd_init(struct drm_device *dev)
3229{
3230 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3231 struct drm_mode_config *mode_config = &dev->mode_config;
3232 struct drm_connector *connector;
b5ea2d56 3233 unsigned long irqflags;
821450c6 3234 int i;
20afbda2 3235
821450c6
EE		 3236 for (i = 1; i < HPD_NUM_PINS; i++) {
3237 dev_priv->hpd_stats[i].hpd_cnt = 0;
3238 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3239 }
3240 list_for_each_entry(connector, &mode_config->connector_list, head) {
3241 struct intel_connector *intel_connector = to_intel_connector(connector);
3242 connector->polled = intel_connector->polled;
3243 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3244 connector->polled = DRM_CONNECTOR_POLL_HPD;
3245 }
b5ea2d56
DV		 3246
3247 /* Interrupt setup is already guaranteed to be single-threaded, this is
3248 * just to make the assert_spin_locked checks happy. */
3249 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3250 if (dev_priv->display.hpd_irq_setup)
3251 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3252 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3253}
c67a470b
PZ		 3254
3255/* Disable interrupts so we can allow Package C8+. */
3256void hsw_pc8_disable_interrupts(struct drm_device *dev)
3257{
3258 struct drm_i915_private *dev_priv = dev->dev_private;
3259 unsigned long irqflags;
3260
3261 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3262
3263 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3264 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3265 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3266 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3267 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3268
3269 ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB);
3270 ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT);
3271 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3272 snb_disable_pm_irq(dev_priv, 0xffffffff);
3273
3274 dev_priv->pc8.irqs_disabled = true;
3275
3276 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3277}
3278
3279/* Restore interrupts so we can recover from Package C8+. */
3280void hsw_pc8_restore_interrupts(struct drm_device *dev)
3281{
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 unsigned long irqflags;
3284 uint32_t val, expected;
3285
3286 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3287
3288 val = I915_READ(DEIMR);
3289 expected = ~DE_PCH_EVENT_IVB;
3290 WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);
3291
3292 val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT;
3293 expected = ~SDE_HOTPLUG_MASK_CPT;
3294 WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3295 val, expected);
3296
3297 val = I915_READ(GTIMR);
3298 expected = 0xffffffff;
3299 WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);
3300
3301 val = I915_READ(GEN6_PMIMR);
3302 expected = 0xffffffff;
3303 WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
3304 expected);
3305
3306 dev_priv->pc8.irqs_disabled = false;
3307
3308 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3309 ibx_enable_display_interrupt(dev_priv,
3310 ~dev_priv->pc8.regsave.sdeimr &
3311 ~SDE_HOTPLUG_MASK_CPT);
3312 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3313 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3314 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3315
3316 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3317}
Linux 6.x block layer and io_uring tree(s)