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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e4ce95aa VS |
48 | static const u32 hpd_ilk[HPD_NUM_PINS] = { |
49 | [HPD_PORT_A] = DE_DP_A_HOTPLUG, | |
50 | }; | |
51 | ||
23bb4cb5 VS |
52 | static const u32 hpd_ivb[HPD_NUM_PINS] = { |
53 | [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, | |
54 | }; | |
55 | ||
3a3b3c7d VS |
56 | static const u32 hpd_bdw[HPD_NUM_PINS] = { |
57 | [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG, | |
58 | }; | |
59 | ||
7c7e10db | 60 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
e5868a31 EE |
61 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
62 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
63 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
64 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
65 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
66 | }; | |
67 | ||
7c7e10db | 68 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
e5868a31 | 69 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
73c352a2 | 70 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
71 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
72 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
73 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
74 | }; | |
75 | ||
26951caf | 76 | static const u32 hpd_spt[HPD_NUM_PINS] = { |
74c0b395 | 77 | [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, |
26951caf XZ |
78 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
79 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
80 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, | |
81 | [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT | |
82 | }; | |
83 | ||
7c7e10db | 84 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
85 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
86 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
87 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
88 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
89 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
90 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
91 | }; | |
92 | ||
7c7e10db | 93 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
e5868a31 EE |
94 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
95 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
96 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
97 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
98 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
99 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
100 | }; | |
101 | ||
4bca26d0 | 102 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
103 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
104 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
105 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
106 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
107 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
108 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
109 | }; | |
110 | ||
e0a20ad7 SS |
111 | /* BXT hpd list */ |
112 | static const u32 hpd_bxt[HPD_NUM_PINS] = { | |
7f3561be | 113 | [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, |
e0a20ad7 SS |
114 | [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, |
115 | [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC | |
116 | }; | |
117 | ||
5c502442 | 118 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 119 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
120 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
121 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
122 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
123 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
124 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
125 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
126 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
127 | } while (0) | |
128 | ||
f86f3fb0 | 129 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 130 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 131 | POSTING_READ(type##IMR); \ |
a9d356a6 | 132 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
133 | I915_WRITE(type##IIR, 0xffffffff); \ |
134 | POSTING_READ(type##IIR); \ | |
135 | I915_WRITE(type##IIR, 0xffffffff); \ | |
136 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
137 | } while (0) |
138 | ||
337ba017 PZ |
139 | /* |
140 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
141 | */ | |
f0f59a00 VS |
142 | static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, |
143 | i915_reg_t reg) | |
b51a2842 VS |
144 | { |
145 | u32 val = I915_READ(reg); | |
146 | ||
147 | if (val == 0) | |
148 | return; | |
149 | ||
150 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", | |
f0f59a00 | 151 | i915_mmio_reg_offset(reg), val); |
b51a2842 VS |
152 | I915_WRITE(reg, 0xffffffff); |
153 | POSTING_READ(reg); | |
154 | I915_WRITE(reg, 0xffffffff); | |
155 | POSTING_READ(reg); | |
156 | } | |
337ba017 | 157 | |
35079899 | 158 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
b51a2842 | 159 | gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \ |
35079899 | 160 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
161 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
162 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
163 | } while (0) |
164 | ||
165 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
b51a2842 | 166 | gen5_assert_iir_is_zero(dev_priv, type##IIR); \ |
35079899 | 167 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
168 | I915_WRITE(type##IMR, (imr_val)); \ |
169 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
170 | } while (0) |
171 | ||
c9a9a268 ID |
172 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
173 | ||
0706f17c EE |
174 | /* For display hotplug interrupt */ |
175 | static inline void | |
176 | i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, | |
177 | uint32_t mask, | |
178 | uint32_t bits) | |
179 | { | |
180 | uint32_t val; | |
181 | ||
182 | assert_spin_locked(&dev_priv->irq_lock); | |
183 | WARN_ON(bits & ~mask); | |
184 | ||
185 | val = I915_READ(PORT_HOTPLUG_EN); | |
186 | val &= ~mask; | |
187 | val |= bits; | |
188 | I915_WRITE(PORT_HOTPLUG_EN, val); | |
189 | } | |
190 | ||
191 | /** | |
192 | * i915_hotplug_interrupt_update - update hotplug interrupt enable | |
193 | * @dev_priv: driver private | |
194 | * @mask: bits to update | |
195 | * @bits: bits to enable | |
196 | * NOTE: the HPD enable bits are modified both inside and outside | |
197 | * of an interrupt context. To avoid that read-modify-write cycles | |
198 | * interfer, these bits are protected by a spinlock. Since this | |
199 | * function is usually not called from a context where the lock is | |
200 | * held already, this function acquires the lock itself. A non-locking | |
201 | * version is also available. | |
202 | */ | |
203 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, | |
204 | uint32_t mask, | |
205 | uint32_t bits) | |
206 | { | |
207 | spin_lock_irq(&dev_priv->irq_lock); | |
208 | i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); | |
209 | spin_unlock_irq(&dev_priv->irq_lock); | |
210 | } | |
211 | ||
d9dc34f1 VS |
212 | /** |
213 | * ilk_update_display_irq - update DEIMR | |
214 | * @dev_priv: driver private | |
215 | * @interrupt_mask: mask of interrupt bits to update | |
216 | * @enabled_irq_mask: mask of interrupt bits to enable | |
217 | */ | |
fbdedaea VS |
218 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
219 | uint32_t interrupt_mask, | |
220 | uint32_t enabled_irq_mask) | |
036a4a7d | 221 | { |
d9dc34f1 VS |
222 | uint32_t new_val; |
223 | ||
4bc9d430 DV |
224 | assert_spin_locked(&dev_priv->irq_lock); |
225 | ||
d9dc34f1 VS |
226 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
227 | ||
9df7575f | 228 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 229 | return; |
c67a470b | 230 | |
d9dc34f1 VS |
231 | new_val = dev_priv->irq_mask; |
232 | new_val &= ~interrupt_mask; | |
233 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
234 | ||
235 | if (new_val != dev_priv->irq_mask) { | |
236 | dev_priv->irq_mask = new_val; | |
1ec14ad3 | 237 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
3143a2bf | 238 | POSTING_READ(DEIMR); |
036a4a7d ZW |
239 | } |
240 | } | |
241 | ||
43eaea13 PZ |
242 | /** |
243 | * ilk_update_gt_irq - update GTIMR | |
244 | * @dev_priv: driver private | |
245 | * @interrupt_mask: mask of interrupt bits to update | |
246 | * @enabled_irq_mask: mask of interrupt bits to enable | |
247 | */ | |
248 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
249 | uint32_t interrupt_mask, | |
250 | uint32_t enabled_irq_mask) | |
251 | { | |
252 | assert_spin_locked(&dev_priv->irq_lock); | |
253 | ||
15a17aae DV |
254 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
255 | ||
9df7575f | 256 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 257 | return; |
c67a470b | 258 | |
43eaea13 PZ |
259 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
260 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
261 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
262 | POSTING_READ(GTIMR); | |
263 | } | |
264 | ||
480c8033 | 265 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
266 | { |
267 | ilk_update_gt_irq(dev_priv, mask, mask); | |
268 | } | |
269 | ||
480c8033 | 270 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
271 | { |
272 | ilk_update_gt_irq(dev_priv, mask, 0); | |
273 | } | |
274 | ||
f0f59a00 | 275 | static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) |
b900b949 ID |
276 | { |
277 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
278 | } | |
279 | ||
f0f59a00 | 280 | static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) |
a72fbc3a ID |
281 | { |
282 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
283 | } | |
284 | ||
f0f59a00 | 285 | static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) |
b900b949 ID |
286 | { |
287 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
288 | } | |
289 | ||
edbfdb45 | 290 | /** |
81fd874e VS |
291 | * snb_update_pm_irq - update GEN6_PMIMR |
292 | * @dev_priv: driver private | |
293 | * @interrupt_mask: mask of interrupt bits to update | |
294 | * @enabled_irq_mask: mask of interrupt bits to enable | |
295 | */ | |
edbfdb45 PZ |
296 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, |
297 | uint32_t interrupt_mask, | |
298 | uint32_t enabled_irq_mask) | |
299 | { | |
605cd25b | 300 | uint32_t new_val; |
edbfdb45 | 301 | |
15a17aae DV |
302 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
303 | ||
edbfdb45 PZ |
304 | assert_spin_locked(&dev_priv->irq_lock); |
305 | ||
605cd25b | 306 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
307 | new_val &= ~interrupt_mask; |
308 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
309 | ||
605cd25b PZ |
310 | if (new_val != dev_priv->pm_irq_mask) { |
311 | dev_priv->pm_irq_mask = new_val; | |
a72fbc3a ID |
312 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
313 | POSTING_READ(gen6_pm_imr(dev_priv)); | |
f52ecbcf | 314 | } |
edbfdb45 PZ |
315 | } |
316 | ||
480c8033 | 317 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 | 318 | { |
9939fba2 ID |
319 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
320 | return; | |
321 | ||
edbfdb45 PZ |
322 | snb_update_pm_irq(dev_priv, mask, mask); |
323 | } | |
324 | ||
9939fba2 ID |
325 | static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, |
326 | uint32_t mask) | |
edbfdb45 PZ |
327 | { |
328 | snb_update_pm_irq(dev_priv, mask, 0); | |
329 | } | |
330 | ||
9939fba2 ID |
331 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
332 | { | |
333 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
334 | return; | |
335 | ||
336 | __gen6_disable_pm_irq(dev_priv, mask); | |
337 | } | |
338 | ||
3cc134e3 ID |
339 | void gen6_reset_rps_interrupts(struct drm_device *dev) |
340 | { | |
341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 342 | i915_reg_t reg = gen6_pm_iir(dev_priv); |
3cc134e3 ID |
343 | |
344 | spin_lock_irq(&dev_priv->irq_lock); | |
345 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
346 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
347 | POSTING_READ(reg); | |
096fad9e | 348 | dev_priv->rps.pm_iir = 0; |
3cc134e3 ID |
349 | spin_unlock_irq(&dev_priv->irq_lock); |
350 | } | |
351 | ||
91d14251 | 352 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) |
b900b949 | 353 | { |
b900b949 | 354 | spin_lock_irq(&dev_priv->irq_lock); |
78e68d36 | 355 | |
b900b949 | 356 | WARN_ON(dev_priv->rps.pm_iir); |
3cc134e3 | 357 | WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
d4d70aa5 | 358 | dev_priv->rps.interrupts_enabled = true; |
78e68d36 ID |
359 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | |
360 | dev_priv->pm_rps_events); | |
b900b949 | 361 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 362 | |
b900b949 ID |
363 | spin_unlock_irq(&dev_priv->irq_lock); |
364 | } | |
365 | ||
59d02a1f ID |
366 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) |
367 | { | |
368 | /* | |
f24eeb19 | 369 | * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer |
59d02a1f | 370 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
f24eeb19 ID |
371 | * |
372 | * TODO: verify if this can be reproduced on VLV,CHV. | |
59d02a1f ID |
373 | */ |
374 | if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) | |
375 | mask &= ~GEN6_PM_RP_UP_EI_EXPIRED; | |
376 | ||
377 | if (INTEL_INFO(dev_priv)->gen >= 8) | |
378 | mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
379 | ||
380 | return mask; | |
381 | } | |
382 | ||
91d14251 | 383 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) |
b900b949 | 384 | { |
d4d70aa5 ID |
385 | spin_lock_irq(&dev_priv->irq_lock); |
386 | dev_priv->rps.interrupts_enabled = false; | |
387 | spin_unlock_irq(&dev_priv->irq_lock); | |
388 | ||
389 | cancel_work_sync(&dev_priv->rps.work); | |
390 | ||
9939fba2 ID |
391 | spin_lock_irq(&dev_priv->irq_lock); |
392 | ||
59d02a1f | 393 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); |
9939fba2 ID |
394 | |
395 | __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
b900b949 ID |
396 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & |
397 | ~dev_priv->pm_rps_events); | |
58072ccb ID |
398 | |
399 | spin_unlock_irq(&dev_priv->irq_lock); | |
400 | ||
91d14251 | 401 | synchronize_irq(dev_priv->dev->irq); |
b900b949 ID |
402 | } |
403 | ||
3a3b3c7d | 404 | /** |
81fd874e VS |
405 | * bdw_update_port_irq - update DE port interrupt |
406 | * @dev_priv: driver private | |
407 | * @interrupt_mask: mask of interrupt bits to update | |
408 | * @enabled_irq_mask: mask of interrupt bits to enable | |
409 | */ | |
3a3b3c7d VS |
410 | static void bdw_update_port_irq(struct drm_i915_private *dev_priv, |
411 | uint32_t interrupt_mask, | |
412 | uint32_t enabled_irq_mask) | |
413 | { | |
414 | uint32_t new_val; | |
415 | uint32_t old_val; | |
416 | ||
417 | assert_spin_locked(&dev_priv->irq_lock); | |
418 | ||
419 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
420 | ||
421 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
422 | return; | |
423 | ||
424 | old_val = I915_READ(GEN8_DE_PORT_IMR); | |
425 | ||
426 | new_val = old_val; | |
427 | new_val &= ~interrupt_mask; | |
428 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
429 | ||
430 | if (new_val != old_val) { | |
431 | I915_WRITE(GEN8_DE_PORT_IMR, new_val); | |
432 | POSTING_READ(GEN8_DE_PORT_IMR); | |
433 | } | |
434 | } | |
435 | ||
013d3752 VS |
436 | /** |
437 | * bdw_update_pipe_irq - update DE pipe interrupt | |
438 | * @dev_priv: driver private | |
439 | * @pipe: pipe whose interrupt to update | |
440 | * @interrupt_mask: mask of interrupt bits to update | |
441 | * @enabled_irq_mask: mask of interrupt bits to enable | |
442 | */ | |
443 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, | |
444 | enum pipe pipe, | |
445 | uint32_t interrupt_mask, | |
446 | uint32_t enabled_irq_mask) | |
447 | { | |
448 | uint32_t new_val; | |
449 | ||
450 | assert_spin_locked(&dev_priv->irq_lock); | |
451 | ||
452 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
453 | ||
454 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
455 | return; | |
456 | ||
457 | new_val = dev_priv->de_irq_mask[pipe]; | |
458 | new_val &= ~interrupt_mask; | |
459 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
460 | ||
461 | if (new_val != dev_priv->de_irq_mask[pipe]) { | |
462 | dev_priv->de_irq_mask[pipe] = new_val; | |
463 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
464 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
465 | } | |
466 | } | |
467 | ||
fee884ed DV |
468 | /** |
469 | * ibx_display_interrupt_update - update SDEIMR | |
470 | * @dev_priv: driver private | |
471 | * @interrupt_mask: mask of interrupt bits to update | |
472 | * @enabled_irq_mask: mask of interrupt bits to enable | |
473 | */ | |
47339cd9 DV |
474 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
475 | uint32_t interrupt_mask, | |
476 | uint32_t enabled_irq_mask) | |
fee884ed DV |
477 | { |
478 | uint32_t sdeimr = I915_READ(SDEIMR); | |
479 | sdeimr &= ~interrupt_mask; | |
480 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
481 | ||
15a17aae DV |
482 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
483 | ||
fee884ed DV |
484 | assert_spin_locked(&dev_priv->irq_lock); |
485 | ||
9df7575f | 486 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 487 | return; |
c67a470b | 488 | |
fee884ed DV |
489 | I915_WRITE(SDEIMR, sdeimr); |
490 | POSTING_READ(SDEIMR); | |
491 | } | |
8664281b | 492 | |
b5ea642a | 493 | static void |
755e9019 ID |
494 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
495 | u32 enable_mask, u32 status_mask) | |
7c463586 | 496 | { |
f0f59a00 | 497 | i915_reg_t reg = PIPESTAT(pipe); |
755e9019 | 498 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 499 | |
b79480ba | 500 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 501 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 502 | |
04feced9 VS |
503 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
504 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
505 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
506 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
507 | return; |
508 | ||
509 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
510 | return; |
511 | ||
91d181dd ID |
512 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
513 | ||
46c06a30 | 514 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 515 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
516 | I915_WRITE(reg, pipestat); |
517 | POSTING_READ(reg); | |
7c463586 KP |
518 | } |
519 | ||
b5ea642a | 520 | static void |
755e9019 ID |
521 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
522 | u32 enable_mask, u32 status_mask) | |
7c463586 | 523 | { |
f0f59a00 | 524 | i915_reg_t reg = PIPESTAT(pipe); |
755e9019 | 525 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 526 | |
b79480ba | 527 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 528 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 529 | |
04feced9 VS |
530 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
531 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
532 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
533 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
534 | return; |
535 | ||
755e9019 ID |
536 | if ((pipestat & enable_mask) == 0) |
537 | return; | |
538 | ||
91d181dd ID |
539 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
540 | ||
755e9019 | 541 | pipestat &= ~enable_mask; |
46c06a30 VS |
542 | I915_WRITE(reg, pipestat); |
543 | POSTING_READ(reg); | |
7c463586 KP |
544 | } |
545 | ||
10c59c51 ID |
546 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
547 | { | |
548 | u32 enable_mask = status_mask << 16; | |
549 | ||
550 | /* | |
724a6905 VS |
551 | * On pipe A we don't support the PSR interrupt yet, |
552 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
553 | */ |
554 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
555 | return 0; | |
724a6905 VS |
556 | /* |
557 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
558 | * A the same bit is for perf counters which we don't use either. | |
559 | */ | |
560 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
561 | return 0; | |
10c59c51 ID |
562 | |
563 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
564 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
565 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
566 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
567 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
568 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
569 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
570 | ||
571 | return enable_mask; | |
572 | } | |
573 | ||
755e9019 ID |
574 | void |
575 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
576 | u32 status_mask) | |
577 | { | |
578 | u32 enable_mask; | |
579 | ||
666a4537 | 580 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
10c59c51 ID |
581 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, |
582 | status_mask); | |
583 | else | |
584 | enable_mask = status_mask << 16; | |
755e9019 ID |
585 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
586 | } | |
587 | ||
588 | void | |
589 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
590 | u32 status_mask) | |
591 | { | |
592 | u32 enable_mask; | |
593 | ||
666a4537 | 594 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
10c59c51 ID |
595 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, |
596 | status_mask); | |
597 | else | |
598 | enable_mask = status_mask << 16; | |
755e9019 ID |
599 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
600 | } | |
601 | ||
01c66889 | 602 | /** |
f49e38dd | 603 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
468f9d29 | 604 | * @dev: drm device |
01c66889 | 605 | */ |
91d14251 | 606 | static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) |
01c66889 | 607 | { |
91d14251 | 608 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv)) |
f49e38dd JN |
609 | return; |
610 | ||
13321786 | 611 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 612 | |
755e9019 | 613 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
91d14251 | 614 | if (INTEL_GEN(dev_priv) >= 4) |
3b6c42e8 | 615 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 616 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 617 | |
13321786 | 618 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
619 | } |
620 | ||
f75f3746 VS |
621 | /* |
622 | * This timing diagram depicts the video signal in and | |
623 | * around the vertical blanking period. | |
624 | * | |
625 | * Assumptions about the fictitious mode used in this example: | |
626 | * vblank_start >= 3 | |
627 | * vsync_start = vblank_start + 1 | |
628 | * vsync_end = vblank_start + 2 | |
629 | * vtotal = vblank_start + 3 | |
630 | * | |
631 | * start of vblank: | |
632 | * latch double buffered registers | |
633 | * increment frame counter (ctg+) | |
634 | * generate start of vblank interrupt (gen4+) | |
635 | * | | |
636 | * | frame start: | |
637 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
638 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
639 | * | | | |
640 | * | | start of vsync: | |
641 | * | | generate vsync interrupt | |
642 | * | | | | |
643 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
644 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
645 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
646 | * | | <----vs-----> | | |
647 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
648 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
649 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
650 | * | | | | |
651 | * last visible pixel first visible pixel | |
652 | * | increment frame counter (gen3/4) | |
653 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
654 | * | |
655 | * x = horizontal active | |
656 | * _ = horizontal blanking | |
657 | * hs = horizontal sync | |
658 | * va = vertical active | |
659 | * vb = vertical blanking | |
660 | * vs = vertical sync | |
661 | * vbs = vblank_start (number) | |
662 | * | |
663 | * Summary: | |
664 | * - most events happen at the start of horizontal sync | |
665 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
666 | * (depending on PIPECONF settings) after the start of vblank | |
667 | * - gen3/4 pixel and frame counter are synchronized with the start | |
668 | * of horizontal active on the first line of vertical active | |
669 | */ | |
670 | ||
88e72717 | 671 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
4cdb83ec VS |
672 | { |
673 | /* Gen2 doesn't have a hardware frame counter */ | |
674 | return 0; | |
675 | } | |
676 | ||
42f52ef8 KP |
677 | /* Called from drm generic code, passed a 'crtc', which |
678 | * we use as a pipe index | |
679 | */ | |
88e72717 | 680 | static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 681 | { |
2d1013dd | 682 | struct drm_i915_private *dev_priv = dev->dev_private; |
f0f59a00 | 683 | i915_reg_t high_frame, low_frame; |
0b2a8e09 | 684 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
f3a5c3f6 DV |
685 | struct intel_crtc *intel_crtc = |
686 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
fc467a22 | 687 | const struct drm_display_mode *mode = &intel_crtc->base.hwmode; |
0a3e67a4 | 688 | |
f3a5c3f6 DV |
689 | htotal = mode->crtc_htotal; |
690 | hsync_start = mode->crtc_hsync_start; | |
691 | vbl_start = mode->crtc_vblank_start; | |
692 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
693 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 694 | |
0b2a8e09 VS |
695 | /* Convert to pixel count */ |
696 | vbl_start *= htotal; | |
697 | ||
698 | /* Start of vblank event occurs at start of hsync */ | |
699 | vbl_start -= htotal - hsync_start; | |
700 | ||
9db4a9c7 JB |
701 | high_frame = PIPEFRAME(pipe); |
702 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 703 | |
0a3e67a4 JB |
704 | /* |
705 | * High & low register fields aren't synchronized, so make sure | |
706 | * we get a low value that's stable across two reads of the high | |
707 | * register. | |
708 | */ | |
709 | do { | |
5eddb70b | 710 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 711 | low = I915_READ(low_frame); |
5eddb70b | 712 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
713 | } while (high1 != high2); |
714 | ||
5eddb70b | 715 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 716 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 717 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
718 | |
719 | /* | |
720 | * The frame counter increments at beginning of active. | |
721 | * Cook up a vblank counter by also checking the pixel | |
722 | * counter against vblank start. | |
723 | */ | |
edc08d0a | 724 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
725 | } |
726 | ||
974e59ba | 727 | static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
9880b7a5 | 728 | { |
2d1013dd | 729 | struct drm_i915_private *dev_priv = dev->dev_private; |
9880b7a5 | 730 | |
649636ef | 731 | return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); |
9880b7a5 JB |
732 | } |
733 | ||
75aa3f63 | 734 | /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */ |
a225f079 VS |
735 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
736 | { | |
737 | struct drm_device *dev = crtc->base.dev; | |
738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fc467a22 | 739 | const struct drm_display_mode *mode = &crtc->base.hwmode; |
a225f079 | 740 | enum pipe pipe = crtc->pipe; |
80715b2f | 741 | int position, vtotal; |
a225f079 | 742 | |
80715b2f | 743 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
744 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
745 | vtotal /= 2; | |
746 | ||
91d14251 | 747 | if (IS_GEN2(dev_priv)) |
75aa3f63 | 748 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
a225f079 | 749 | else |
75aa3f63 | 750 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
a225f079 | 751 | |
41b578fb JB |
752 | /* |
753 | * On HSW, the DSL reg (0x70000) appears to return 0 if we | |
754 | * read it just before the start of vblank. So try it again | |
755 | * so we don't accidentally end up spanning a vblank frame | |
756 | * increment, causing the pipe_update_end() code to squak at us. | |
757 | * | |
758 | * The nature of this problem means we can't simply check the ISR | |
759 | * bit and return the vblank start value; nor can we use the scanline | |
760 | * debug register in the transcoder as it appears to have the same | |
761 | * problem. We may need to extend this to include other platforms, | |
762 | * but so far testing only shows the problem on HSW. | |
763 | */ | |
91d14251 | 764 | if (HAS_DDI(dev_priv) && !position) { |
41b578fb JB |
765 | int i, temp; |
766 | ||
767 | for (i = 0; i < 100; i++) { | |
768 | udelay(1); | |
769 | temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & | |
770 | DSL_LINEMASK_GEN3; | |
771 | if (temp != position) { | |
772 | position = temp; | |
773 | break; | |
774 | } | |
775 | } | |
776 | } | |
777 | ||
a225f079 | 778 | /* |
80715b2f VS |
779 | * See update_scanline_offset() for the details on the |
780 | * scanline_offset adjustment. | |
a225f079 | 781 | */ |
80715b2f | 782 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
783 | } |
784 | ||
88e72717 | 785 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
abca9e45 | 786 | unsigned int flags, int *vpos, int *hpos, |
3bb403bf VS |
787 | ktime_t *stime, ktime_t *etime, |
788 | const struct drm_display_mode *mode) | |
0af7e4df | 789 | { |
c2baf4b7 VS |
790 | struct drm_i915_private *dev_priv = dev->dev_private; |
791 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
792 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3aa18df8 | 793 | int position; |
78e8fc6b | 794 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
795 | bool in_vbl = true; |
796 | int ret = 0; | |
ad3543ed | 797 | unsigned long irqflags; |
0af7e4df | 798 | |
fc467a22 | 799 | if (WARN_ON(!mode->crtc_clock)) { |
0af7e4df | 800 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 801 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
802 | return 0; |
803 | } | |
804 | ||
c2baf4b7 | 805 | htotal = mode->crtc_htotal; |
78e8fc6b | 806 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
807 | vtotal = mode->crtc_vtotal; |
808 | vbl_start = mode->crtc_vblank_start; | |
809 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 810 | |
d31faf65 VS |
811 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
812 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
813 | vbl_end /= 2; | |
814 | vtotal /= 2; | |
815 | } | |
816 | ||
c2baf4b7 VS |
817 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
818 | ||
ad3543ed MK |
819 | /* |
820 | * Lock uncore.lock, as we will do multiple timing critical raw | |
821 | * register reads, potentially with preemption disabled, so the | |
822 | * following code must not block on uncore.lock. | |
823 | */ | |
824 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 825 | |
ad3543ed MK |
826 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
827 | ||
828 | /* Get optional system timestamp before query. */ | |
829 | if (stime) | |
830 | *stime = ktime_get(); | |
831 | ||
91d14251 | 832 | if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
0af7e4df MK |
833 | /* No obvious pixelcount register. Only query vertical |
834 | * scanout position from Display scan line register. | |
835 | */ | |
a225f079 | 836 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
837 | } else { |
838 | /* Have access to pixelcount since start of frame. | |
839 | * We can split this into vertical and horizontal | |
840 | * scanout position. | |
841 | */ | |
75aa3f63 | 842 | position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 843 | |
3aa18df8 VS |
844 | /* convert to pixel counts */ |
845 | vbl_start *= htotal; | |
846 | vbl_end *= htotal; | |
847 | vtotal *= htotal; | |
78e8fc6b | 848 | |
7e78f1cb VS |
849 | /* |
850 | * In interlaced modes, the pixel counter counts all pixels, | |
851 | * so one field will have htotal more pixels. In order to avoid | |
852 | * the reported position from jumping backwards when the pixel | |
853 | * counter is beyond the length of the shorter field, just | |
854 | * clamp the position the length of the shorter field. This | |
855 | * matches how the scanline counter based position works since | |
856 | * the scanline counter doesn't count the two half lines. | |
857 | */ | |
858 | if (position >= vtotal) | |
859 | position = vtotal - 1; | |
860 | ||
78e8fc6b VS |
861 | /* |
862 | * Start of vblank interrupt is triggered at start of hsync, | |
863 | * just prior to the first active line of vblank. However we | |
864 | * consider lines to start at the leading edge of horizontal | |
865 | * active. So, should we get here before we've crossed into | |
866 | * the horizontal active of the first line in vblank, we would | |
867 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
868 | * always add htotal-hsync_start to the current pixel position. | |
869 | */ | |
870 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
871 | } |
872 | ||
ad3543ed MK |
873 | /* Get optional system timestamp after query. */ |
874 | if (etime) | |
875 | *etime = ktime_get(); | |
876 | ||
877 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
878 | ||
879 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
880 | ||
3aa18df8 VS |
881 | in_vbl = position >= vbl_start && position < vbl_end; |
882 | ||
883 | /* | |
884 | * While in vblank, position will be negative | |
885 | * counting up towards 0 at vbl_end. And outside | |
886 | * vblank, position will be positive counting | |
887 | * up since vbl_end. | |
888 | */ | |
889 | if (position >= vbl_start) | |
890 | position -= vbl_end; | |
891 | else | |
892 | position += vtotal - vbl_end; | |
0af7e4df | 893 | |
91d14251 | 894 | if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
3aa18df8 VS |
895 | *vpos = position; |
896 | *hpos = 0; | |
897 | } else { | |
898 | *vpos = position / htotal; | |
899 | *hpos = position - (*vpos * htotal); | |
900 | } | |
0af7e4df | 901 | |
0af7e4df MK |
902 | /* In vblank? */ |
903 | if (in_vbl) | |
3d3cbd84 | 904 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
905 | |
906 | return ret; | |
907 | } | |
908 | ||
a225f079 VS |
909 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
910 | { | |
911 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
912 | unsigned long irqflags; | |
913 | int position; | |
914 | ||
915 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
916 | position = __intel_get_crtc_scanline(crtc); | |
917 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
918 | ||
919 | return position; | |
920 | } | |
921 | ||
88e72717 | 922 | static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe, |
0af7e4df MK |
923 | int *max_error, |
924 | struct timeval *vblank_time, | |
925 | unsigned flags) | |
926 | { | |
4041b853 | 927 | struct drm_crtc *crtc; |
0af7e4df | 928 | |
88e72717 TR |
929 | if (pipe >= INTEL_INFO(dev)->num_pipes) { |
930 | DRM_ERROR("Invalid crtc %u\n", pipe); | |
0af7e4df MK |
931 | return -EINVAL; |
932 | } | |
933 | ||
934 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
935 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
936 | if (crtc == NULL) { | |
88e72717 | 937 | DRM_ERROR("Invalid crtc %u\n", pipe); |
4041b853 CW |
938 | return -EINVAL; |
939 | } | |
940 | ||
fc467a22 | 941 | if (!crtc->hwmode.crtc_clock) { |
88e72717 | 942 | DRM_DEBUG_KMS("crtc %u is disabled\n", pipe); |
4041b853 CW |
943 | return -EBUSY; |
944 | } | |
0af7e4df MK |
945 | |
946 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
947 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
948 | vblank_time, flags, | |
fc467a22 | 949 | &crtc->hwmode); |
0af7e4df MK |
950 | } |
951 | ||
91d14251 | 952 | static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv) |
f97108d1 | 953 | { |
b5b72e89 | 954 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 955 | u8 new_delay; |
9270388e | 956 | |
d0ecd7e2 | 957 | spin_lock(&mchdev_lock); |
f97108d1 | 958 | |
73edd18f DV |
959 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
960 | ||
20e4d407 | 961 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 962 | |
7648fa99 | 963 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
964 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
965 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
966 | max_avg = I915_READ(RCBMAXAVG); |
967 | min_avg = I915_READ(RCBMINAVG); | |
968 | ||
969 | /* Handle RCS change request from hw */ | |
b5b72e89 | 970 | if (busy_up > max_avg) { |
20e4d407 DV |
971 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
972 | new_delay = dev_priv->ips.cur_delay - 1; | |
973 | if (new_delay < dev_priv->ips.max_delay) | |
974 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 975 | } else if (busy_down < min_avg) { |
20e4d407 DV |
976 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
977 | new_delay = dev_priv->ips.cur_delay + 1; | |
978 | if (new_delay > dev_priv->ips.min_delay) | |
979 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
980 | } |
981 | ||
91d14251 | 982 | if (ironlake_set_drps(dev_priv, new_delay)) |
20e4d407 | 983 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 984 | |
d0ecd7e2 | 985 | spin_unlock(&mchdev_lock); |
9270388e | 986 | |
f97108d1 JB |
987 | return; |
988 | } | |
989 | ||
0bc40be8 | 990 | static void notify_ring(struct intel_engine_cs *engine) |
549f7365 | 991 | { |
117897f4 | 992 | if (!intel_engine_initialized(engine)) |
475553de CW |
993 | return; |
994 | ||
0bc40be8 | 995 | trace_i915_gem_request_notify(engine); |
12471ba8 | 996 | engine->user_interrupts++; |
9862e600 | 997 | |
0bc40be8 | 998 | wake_up_all(&engine->irq_queue); |
549f7365 CW |
999 | } |
1000 | ||
43cf3bf0 CW |
1001 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
1002 | struct intel_rps_ei *ei) | |
31685c25 | 1003 | { |
43cf3bf0 CW |
1004 | ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); |
1005 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); | |
1006 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); | |
1007 | } | |
31685c25 | 1008 | |
43cf3bf0 CW |
1009 | static bool vlv_c0_above(struct drm_i915_private *dev_priv, |
1010 | const struct intel_rps_ei *old, | |
1011 | const struct intel_rps_ei *now, | |
1012 | int threshold) | |
1013 | { | |
1014 | u64 time, c0; | |
7bad74d5 | 1015 | unsigned int mul = 100; |
31685c25 | 1016 | |
43cf3bf0 CW |
1017 | if (old->cz_clock == 0) |
1018 | return false; | |
31685c25 | 1019 | |
7bad74d5 VS |
1020 | if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) |
1021 | mul <<= 8; | |
1022 | ||
43cf3bf0 | 1023 | time = now->cz_clock - old->cz_clock; |
7bad74d5 | 1024 | time *= threshold * dev_priv->czclk_freq; |
31685c25 | 1025 | |
43cf3bf0 CW |
1026 | /* Workload can be split between render + media, e.g. SwapBuffers |
1027 | * being blitted in X after being rendered in mesa. To account for | |
1028 | * this we need to combine both engines into our activity counter. | |
31685c25 | 1029 | */ |
43cf3bf0 CW |
1030 | c0 = now->render_c0 - old->render_c0; |
1031 | c0 += now->media_c0 - old->media_c0; | |
7bad74d5 | 1032 | c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC; |
31685c25 | 1033 | |
43cf3bf0 | 1034 | return c0 >= time; |
31685c25 D |
1035 | } |
1036 | ||
43cf3bf0 | 1037 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
31685c25 | 1038 | { |
43cf3bf0 CW |
1039 | vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); |
1040 | dev_priv->rps.up_ei = dev_priv->rps.down_ei; | |
43cf3bf0 | 1041 | } |
31685c25 | 1042 | |
43cf3bf0 CW |
1043 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
1044 | { | |
1045 | struct intel_rps_ei now; | |
1046 | u32 events = 0; | |
31685c25 | 1047 | |
6f4b12f8 | 1048 | if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0) |
43cf3bf0 | 1049 | return 0; |
31685c25 | 1050 | |
43cf3bf0 CW |
1051 | vlv_c0_read(dev_priv, &now); |
1052 | if (now.cz_clock == 0) | |
1053 | return 0; | |
31685c25 | 1054 | |
43cf3bf0 CW |
1055 | if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { |
1056 | if (!vlv_c0_above(dev_priv, | |
1057 | &dev_priv->rps.down_ei, &now, | |
8fb55197 | 1058 | dev_priv->rps.down_threshold)) |
43cf3bf0 CW |
1059 | events |= GEN6_PM_RP_DOWN_THRESHOLD; |
1060 | dev_priv->rps.down_ei = now; | |
1061 | } | |
31685c25 | 1062 | |
43cf3bf0 CW |
1063 | if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1064 | if (vlv_c0_above(dev_priv, | |
1065 | &dev_priv->rps.up_ei, &now, | |
8fb55197 | 1066 | dev_priv->rps.up_threshold)) |
43cf3bf0 CW |
1067 | events |= GEN6_PM_RP_UP_THRESHOLD; |
1068 | dev_priv->rps.up_ei = now; | |
31685c25 D |
1069 | } |
1070 | ||
43cf3bf0 | 1071 | return events; |
31685c25 D |
1072 | } |
1073 | ||
f5a4c67d CW |
1074 | static bool any_waiters(struct drm_i915_private *dev_priv) |
1075 | { | |
e2f80391 | 1076 | struct intel_engine_cs *engine; |
f5a4c67d | 1077 | |
b4ac5afc | 1078 | for_each_engine(engine, dev_priv) |
e2f80391 | 1079 | if (engine->irq_refcount) |
f5a4c67d CW |
1080 | return true; |
1081 | ||
1082 | return false; | |
1083 | } | |
1084 | ||
4912d041 | 1085 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1086 | { |
2d1013dd JN |
1087 | struct drm_i915_private *dev_priv = |
1088 | container_of(work, struct drm_i915_private, rps.work); | |
8d3afd7d CW |
1089 | bool client_boost; |
1090 | int new_delay, adj, min, max; | |
edbfdb45 | 1091 | u32 pm_iir; |
4912d041 | 1092 | |
59cdb63d | 1093 | spin_lock_irq(&dev_priv->irq_lock); |
d4d70aa5 ID |
1094 | /* Speed up work cancelation during disabling rps interrupts. */ |
1095 | if (!dev_priv->rps.interrupts_enabled) { | |
1096 | spin_unlock_irq(&dev_priv->irq_lock); | |
1097 | return; | |
1098 | } | |
1f814dac ID |
1099 | |
1100 | /* | |
1101 | * The RPS work is synced during runtime suspend, we don't require a | |
1102 | * wakeref. TODO: instead of disabling the asserts make sure that we | |
1103 | * always hold an RPM reference while the work is running. | |
1104 | */ | |
1105 | DISABLE_RPM_WAKEREF_ASSERTS(dev_priv); | |
1106 | ||
c6a828d3 DV |
1107 | pm_iir = dev_priv->rps.pm_iir; |
1108 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a ID |
1109 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
1110 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
8d3afd7d CW |
1111 | client_boost = dev_priv->rps.client_boost; |
1112 | dev_priv->rps.client_boost = false; | |
59cdb63d | 1113 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1114 | |
60611c13 | 1115 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1116 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1117 | |
8d3afd7d | 1118 | if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) |
1f814dac | 1119 | goto out; |
3b8d8d91 | 1120 | |
4fc688ce | 1121 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1122 | |
43cf3bf0 CW |
1123 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
1124 | ||
dd75fdc8 | 1125 | adj = dev_priv->rps.last_adj; |
edcf284b | 1126 | new_delay = dev_priv->rps.cur_freq; |
8d3afd7d CW |
1127 | min = dev_priv->rps.min_freq_softlimit; |
1128 | max = dev_priv->rps.max_freq_softlimit; | |
1129 | ||
1130 | if (client_boost) { | |
1131 | new_delay = dev_priv->rps.max_freq_softlimit; | |
1132 | adj = 0; | |
1133 | } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
dd75fdc8 CW |
1134 | if (adj > 0) |
1135 | adj *= 2; | |
edcf284b CW |
1136 | else /* CHV needs even encode values */ |
1137 | adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; | |
7425034a VS |
1138 | /* |
1139 | * For better performance, jump directly | |
1140 | * to RPe if we're below it. | |
1141 | */ | |
edcf284b | 1142 | if (new_delay < dev_priv->rps.efficient_freq - adj) { |
b39fb297 | 1143 | new_delay = dev_priv->rps.efficient_freq; |
edcf284b CW |
1144 | adj = 0; |
1145 | } | |
f5a4c67d CW |
1146 | } else if (any_waiters(dev_priv)) { |
1147 | adj = 0; | |
dd75fdc8 | 1148 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1149 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1150 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1151 | else |
b39fb297 | 1152 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1153 | adj = 0; |
1154 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1155 | if (adj < 0) | |
1156 | adj *= 2; | |
edcf284b CW |
1157 | else /* CHV needs even encode values */ |
1158 | adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; | |
dd75fdc8 | 1159 | } else { /* unknown event */ |
edcf284b | 1160 | adj = 0; |
dd75fdc8 | 1161 | } |
3b8d8d91 | 1162 | |
edcf284b CW |
1163 | dev_priv->rps.last_adj = adj; |
1164 | ||
79249636 BW |
1165 | /* sysfs frequency interfaces may have snuck in while servicing the |
1166 | * interrupt | |
1167 | */ | |
edcf284b | 1168 | new_delay += adj; |
8d3afd7d | 1169 | new_delay = clamp_t(int, new_delay, min, max); |
27544369 | 1170 | |
ffe02b40 | 1171 | intel_set_rps(dev_priv->dev, new_delay); |
3b8d8d91 | 1172 | |
4fc688ce | 1173 | mutex_unlock(&dev_priv->rps.hw_lock); |
1f814dac ID |
1174 | out: |
1175 | ENABLE_RPM_WAKEREF_ASSERTS(dev_priv); | |
3b8d8d91 JB |
1176 | } |
1177 | ||
e3689190 BW |
1178 | |
1179 | /** | |
1180 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1181 | * occurred. | |
1182 | * @work: workqueue struct | |
1183 | * | |
1184 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1185 | * this event, userspace should try to remap the bad rows since statistically | |
1186 | * it is likely the same row is more likely to go bad again. | |
1187 | */ | |
1188 | static void ivybridge_parity_work(struct work_struct *work) | |
1189 | { | |
2d1013dd JN |
1190 | struct drm_i915_private *dev_priv = |
1191 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1192 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1193 | char *parity_event[6]; |
e3689190 | 1194 | uint32_t misccpctl; |
35a85ac6 | 1195 | uint8_t slice = 0; |
e3689190 BW |
1196 | |
1197 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1198 | * In order to prevent a get/put style interface, acquire struct mutex | |
1199 | * any time we access those registers. | |
1200 | */ | |
1201 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1202 | ||
35a85ac6 BW |
1203 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1204 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1205 | goto out; | |
1206 | ||
e3689190 BW |
1207 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1208 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1209 | POSTING_READ(GEN7_MISCCPCTL); | |
1210 | ||
35a85ac6 | 1211 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
f0f59a00 | 1212 | i915_reg_t reg; |
e3689190 | 1213 | |
35a85ac6 | 1214 | slice--; |
2d1fe073 | 1215 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv))) |
35a85ac6 | 1216 | break; |
e3689190 | 1217 | |
35a85ac6 | 1218 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1219 | |
6fa1c5f1 | 1220 | reg = GEN7_L3CDERRST1(slice); |
e3689190 | 1221 | |
35a85ac6 BW |
1222 | error_status = I915_READ(reg); |
1223 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1224 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1225 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1226 | ||
1227 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1228 | POSTING_READ(reg); | |
1229 | ||
1230 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1231 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1232 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1233 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1234 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1235 | parity_event[5] = NULL; | |
1236 | ||
5bdebb18 | 1237 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1238 | KOBJ_CHANGE, parity_event); |
e3689190 | 1239 | |
35a85ac6 BW |
1240 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1241 | slice, row, bank, subbank); | |
e3689190 | 1242 | |
35a85ac6 BW |
1243 | kfree(parity_event[4]); |
1244 | kfree(parity_event[3]); | |
1245 | kfree(parity_event[2]); | |
1246 | kfree(parity_event[1]); | |
1247 | } | |
e3689190 | 1248 | |
35a85ac6 | 1249 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1250 | |
35a85ac6 BW |
1251 | out: |
1252 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1253 | spin_lock_irq(&dev_priv->irq_lock); |
2d1fe073 | 1254 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
4cb21832 | 1255 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1256 | |
1257 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1258 | } |
1259 | ||
261e40b8 VS |
1260 | static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv, |
1261 | u32 iir) | |
e3689190 | 1262 | { |
261e40b8 | 1263 | if (!HAS_L3_DPF(dev_priv)) |
e3689190 BW |
1264 | return; |
1265 | ||
d0ecd7e2 | 1266 | spin_lock(&dev_priv->irq_lock); |
261e40b8 | 1267 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
d0ecd7e2 | 1268 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1269 | |
261e40b8 | 1270 | iir &= GT_PARITY_ERROR(dev_priv); |
35a85ac6 BW |
1271 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) |
1272 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1273 | ||
1274 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1275 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1276 | ||
a4da4fa4 | 1277 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1278 | } |
1279 | ||
261e40b8 | 1280 | static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv, |
f1af8fc1 PZ |
1281 | u32 gt_iir) |
1282 | { | |
1283 | if (gt_iir & | |
1284 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
4a570db5 | 1285 | notify_ring(&dev_priv->engine[RCS]); |
f1af8fc1 | 1286 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
4a570db5 | 1287 | notify_ring(&dev_priv->engine[VCS]); |
f1af8fc1 PZ |
1288 | } |
1289 | ||
261e40b8 | 1290 | static void snb_gt_irq_handler(struct drm_i915_private *dev_priv, |
e7b4c6b1 DV |
1291 | u32 gt_iir) |
1292 | { | |
1293 | ||
cc609d5d BW |
1294 | if (gt_iir & |
1295 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
4a570db5 | 1296 | notify_ring(&dev_priv->engine[RCS]); |
cc609d5d | 1297 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
4a570db5 | 1298 | notify_ring(&dev_priv->engine[VCS]); |
cc609d5d | 1299 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
4a570db5 | 1300 | notify_ring(&dev_priv->engine[BCS]); |
e7b4c6b1 | 1301 | |
cc609d5d BW |
1302 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1303 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1304 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1305 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1306 | |
261e40b8 VS |
1307 | if (gt_iir & GT_PARITY_ERROR(dev_priv)) |
1308 | ivybridge_parity_error_irq_handler(dev_priv, gt_iir); | |
e7b4c6b1 DV |
1309 | } |
1310 | ||
fbcc1a0c | 1311 | static __always_inline void |
0bc40be8 | 1312 | gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift) |
fbcc1a0c NH |
1313 | { |
1314 | if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) | |
0bc40be8 | 1315 | notify_ring(engine); |
fbcc1a0c | 1316 | if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) |
27af5eea | 1317 | tasklet_schedule(&engine->irq_tasklet); |
fbcc1a0c NH |
1318 | } |
1319 | ||
e30e251a VS |
1320 | static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv, |
1321 | u32 master_ctl, | |
1322 | u32 gt_iir[4]) | |
abd58f01 | 1323 | { |
abd58f01 BW |
1324 | irqreturn_t ret = IRQ_NONE; |
1325 | ||
1326 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
e30e251a VS |
1327 | gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0)); |
1328 | if (gt_iir[0]) { | |
1329 | I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]); | |
abd58f01 | 1330 | ret = IRQ_HANDLED; |
abd58f01 BW |
1331 | } else |
1332 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1333 | } | |
1334 | ||
85f9b5f9 | 1335 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
e30e251a VS |
1336 | gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1)); |
1337 | if (gt_iir[1]) { | |
1338 | I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]); | |
abd58f01 | 1339 | ret = IRQ_HANDLED; |
0961021a | 1340 | } else |
abd58f01 | 1341 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
0961021a BW |
1342 | } |
1343 | ||
abd58f01 | 1344 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
e30e251a VS |
1345 | gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3)); |
1346 | if (gt_iir[3]) { | |
1347 | I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]); | |
abd58f01 | 1348 | ret = IRQ_HANDLED; |
abd58f01 BW |
1349 | } else |
1350 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1351 | } | |
1352 | ||
0961021a | 1353 | if (master_ctl & GEN8_GT_PM_IRQ) { |
e30e251a VS |
1354 | gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2)); |
1355 | if (gt_iir[2] & dev_priv->pm_rps_events) { | |
cb0d205e | 1356 | I915_WRITE_FW(GEN8_GT_IIR(2), |
e30e251a | 1357 | gt_iir[2] & dev_priv->pm_rps_events); |
38cc46d7 | 1358 | ret = IRQ_HANDLED; |
0961021a BW |
1359 | } else |
1360 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1361 | } | |
1362 | ||
abd58f01 BW |
1363 | return ret; |
1364 | } | |
1365 | ||
e30e251a VS |
1366 | static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv, |
1367 | u32 gt_iir[4]) | |
1368 | { | |
1369 | if (gt_iir[0]) { | |
1370 | gen8_cs_irq_handler(&dev_priv->engine[RCS], | |
1371 | gt_iir[0], GEN8_RCS_IRQ_SHIFT); | |
1372 | gen8_cs_irq_handler(&dev_priv->engine[BCS], | |
1373 | gt_iir[0], GEN8_BCS_IRQ_SHIFT); | |
1374 | } | |
1375 | ||
1376 | if (gt_iir[1]) { | |
1377 | gen8_cs_irq_handler(&dev_priv->engine[VCS], | |
1378 | gt_iir[1], GEN8_VCS1_IRQ_SHIFT); | |
1379 | gen8_cs_irq_handler(&dev_priv->engine[VCS2], | |
1380 | gt_iir[1], GEN8_VCS2_IRQ_SHIFT); | |
1381 | } | |
1382 | ||
1383 | if (gt_iir[3]) | |
1384 | gen8_cs_irq_handler(&dev_priv->engine[VECS], | |
1385 | gt_iir[3], GEN8_VECS_IRQ_SHIFT); | |
1386 | ||
1387 | if (gt_iir[2] & dev_priv->pm_rps_events) | |
1388 | gen6_rps_irq_handler(dev_priv, gt_iir[2]); | |
1389 | } | |
1390 | ||
63c88d22 ID |
1391 | static bool bxt_port_hotplug_long_detect(enum port port, u32 val) |
1392 | { | |
1393 | switch (port) { | |
1394 | case PORT_A: | |
195baa06 | 1395 | return val & PORTA_HOTPLUG_LONG_DETECT; |
63c88d22 ID |
1396 | case PORT_B: |
1397 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1398 | case PORT_C: | |
1399 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
63c88d22 ID |
1400 | default: |
1401 | return false; | |
1402 | } | |
1403 | } | |
1404 | ||
6dbf30ce VS |
1405 | static bool spt_port_hotplug2_long_detect(enum port port, u32 val) |
1406 | { | |
1407 | switch (port) { | |
1408 | case PORT_E: | |
1409 | return val & PORTE_HOTPLUG_LONG_DETECT; | |
1410 | default: | |
1411 | return false; | |
1412 | } | |
1413 | } | |
1414 | ||
74c0b395 VS |
1415 | static bool spt_port_hotplug_long_detect(enum port port, u32 val) |
1416 | { | |
1417 | switch (port) { | |
1418 | case PORT_A: | |
1419 | return val & PORTA_HOTPLUG_LONG_DETECT; | |
1420 | case PORT_B: | |
1421 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1422 | case PORT_C: | |
1423 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
1424 | case PORT_D: | |
1425 | return val & PORTD_HOTPLUG_LONG_DETECT; | |
1426 | default: | |
1427 | return false; | |
1428 | } | |
1429 | } | |
1430 | ||
e4ce95aa VS |
1431 | static bool ilk_port_hotplug_long_detect(enum port port, u32 val) |
1432 | { | |
1433 | switch (port) { | |
1434 | case PORT_A: | |
1435 | return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; | |
1436 | default: | |
1437 | return false; | |
1438 | } | |
1439 | } | |
1440 | ||
676574df | 1441 | static bool pch_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1442 | { |
1443 | switch (port) { | |
13cf5504 | 1444 | case PORT_B: |
676574df | 1445 | return val & PORTB_HOTPLUG_LONG_DETECT; |
13cf5504 | 1446 | case PORT_C: |
676574df | 1447 | return val & PORTC_HOTPLUG_LONG_DETECT; |
13cf5504 | 1448 | case PORT_D: |
676574df JN |
1449 | return val & PORTD_HOTPLUG_LONG_DETECT; |
1450 | default: | |
1451 | return false; | |
13cf5504 DA |
1452 | } |
1453 | } | |
1454 | ||
676574df | 1455 | static bool i9xx_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1456 | { |
1457 | switch (port) { | |
13cf5504 | 1458 | case PORT_B: |
676574df | 1459 | return val & PORTB_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1460 | case PORT_C: |
676574df | 1461 | return val & PORTC_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1462 | case PORT_D: |
676574df JN |
1463 | return val & PORTD_HOTPLUG_INT_LONG_PULSE; |
1464 | default: | |
1465 | return false; | |
13cf5504 DA |
1466 | } |
1467 | } | |
1468 | ||
42db67d6 VS |
1469 | /* |
1470 | * Get a bit mask of pins that have triggered, and which ones may be long. | |
1471 | * This can be called multiple times with the same masks to accumulate | |
1472 | * hotplug detection results from several registers. | |
1473 | * | |
1474 | * Note that the caller is expected to zero out the masks initially. | |
1475 | */ | |
fd63e2a9 | 1476 | static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, |
8c841e57 | 1477 | u32 hotplug_trigger, u32 dig_hotplug_reg, |
fd63e2a9 ID |
1478 | const u32 hpd[HPD_NUM_PINS], |
1479 | bool long_pulse_detect(enum port port, u32 val)) | |
676574df | 1480 | { |
8c841e57 | 1481 | enum port port; |
676574df JN |
1482 | int i; |
1483 | ||
676574df | 1484 | for_each_hpd_pin(i) { |
8c841e57 JN |
1485 | if ((hpd[i] & hotplug_trigger) == 0) |
1486 | continue; | |
676574df | 1487 | |
8c841e57 JN |
1488 | *pin_mask |= BIT(i); |
1489 | ||
cc24fcdc ID |
1490 | if (!intel_hpd_pin_to_port(i, &port)) |
1491 | continue; | |
1492 | ||
fd63e2a9 | 1493 | if (long_pulse_detect(port, dig_hotplug_reg)) |
8c841e57 | 1494 | *long_mask |= BIT(i); |
676574df JN |
1495 | } |
1496 | ||
1497 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n", | |
1498 | hotplug_trigger, dig_hotplug_reg, *pin_mask); | |
1499 | ||
1500 | } | |
1501 | ||
91d14251 | 1502 | static void gmbus_irq_handler(struct drm_i915_private *dev_priv) |
515ac2bb | 1503 | { |
28c70f16 | 1504 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1505 | } |
1506 | ||
91d14251 | 1507 | static void dp_aux_irq_handler(struct drm_i915_private *dev_priv) |
ce99c256 | 1508 | { |
9ee32fea | 1509 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1510 | } |
1511 | ||
8bf1e9f1 | 1512 | #if defined(CONFIG_DEBUG_FS) |
91d14251 TU |
1513 | static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1514 | enum pipe pipe, | |
277de95e DV |
1515 | uint32_t crc0, uint32_t crc1, |
1516 | uint32_t crc2, uint32_t crc3, | |
1517 | uint32_t crc4) | |
8bf1e9f1 | 1518 | { |
8bf1e9f1 SH |
1519 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
1520 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1521 | int head, tail; |
b2c88f5b | 1522 | |
d538bbdf DL |
1523 | spin_lock(&pipe_crc->lock); |
1524 | ||
0c912c79 | 1525 | if (!pipe_crc->entries) { |
d538bbdf | 1526 | spin_unlock(&pipe_crc->lock); |
34273620 | 1527 | DRM_DEBUG_KMS("spurious interrupt\n"); |
0c912c79 DL |
1528 | return; |
1529 | } | |
1530 | ||
d538bbdf DL |
1531 | head = pipe_crc->head; |
1532 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1533 | |
1534 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1535 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1536 | DRM_ERROR("CRC buffer overflowing\n"); |
1537 | return; | |
1538 | } | |
1539 | ||
1540 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1541 | |
91d14251 TU |
1542 | entry->frame = dev_priv->dev->driver->get_vblank_counter(dev_priv->dev, |
1543 | pipe); | |
eba94eb9 DV |
1544 | entry->crc[0] = crc0; |
1545 | entry->crc[1] = crc1; | |
1546 | entry->crc[2] = crc2; | |
1547 | entry->crc[3] = crc3; | |
1548 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1549 | |
1550 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1551 | pipe_crc->head = head; |
1552 | ||
1553 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1554 | |
1555 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1556 | } |
277de95e DV |
1557 | #else |
1558 | static inline void | |
91d14251 TU |
1559 | display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1560 | enum pipe pipe, | |
277de95e DV |
1561 | uint32_t crc0, uint32_t crc1, |
1562 | uint32_t crc2, uint32_t crc3, | |
1563 | uint32_t crc4) {} | |
1564 | #endif | |
1565 | ||
eba94eb9 | 1566 | |
91d14251 TU |
1567 | static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1568 | enum pipe pipe) | |
5a69b89f | 1569 | { |
91d14251 | 1570 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1571 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
1572 | 0, 0, 0, 0); | |
5a69b89f DV |
1573 | } |
1574 | ||
91d14251 TU |
1575 | static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1576 | enum pipe pipe) | |
eba94eb9 | 1577 | { |
91d14251 | 1578 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1579 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
1580 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1581 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1582 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1583 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1584 | } |
5b3a856b | 1585 | |
91d14251 TU |
1586 | static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1587 | enum pipe pipe) | |
5b3a856b | 1588 | { |
0b5c5ed0 DV |
1589 | uint32_t res1, res2; |
1590 | ||
91d14251 | 1591 | if (INTEL_GEN(dev_priv) >= 3) |
0b5c5ed0 DV |
1592 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); |
1593 | else | |
1594 | res1 = 0; | |
1595 | ||
91d14251 | 1596 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
0b5c5ed0 DV |
1597 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); |
1598 | else | |
1599 | res2 = 0; | |
5b3a856b | 1600 | |
91d14251 | 1601 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1602 | I915_READ(PIPE_CRC_RES_RED(pipe)), |
1603 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1604 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1605 | res1, res2); | |
5b3a856b | 1606 | } |
8bf1e9f1 | 1607 | |
1403c0d4 PZ |
1608 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1609 | * IMR bits until the work is done. Other interrupts can be processed without | |
1610 | * the work queue. */ | |
1611 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1612 | { |
a6706b45 | 1613 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1614 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1615 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1616 | if (dev_priv->rps.interrupts_enabled) { |
1617 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1618 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1619 | } | |
59cdb63d | 1620 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1621 | } |
baf02a1f | 1622 | |
c9a9a268 ID |
1623 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1624 | return; | |
1625 | ||
2d1fe073 | 1626 | if (HAS_VEBOX(dev_priv)) { |
1403c0d4 | 1627 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) |
4a570db5 | 1628 | notify_ring(&dev_priv->engine[VECS]); |
12638c57 | 1629 | |
aaecdf61 DV |
1630 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1631 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1632 | } |
baf02a1f BW |
1633 | } |
1634 | ||
91d14251 TU |
1635 | static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv, |
1636 | enum pipe pipe) | |
8d7849db | 1637 | { |
91d14251 | 1638 | return drm_handle_vblank(dev_priv->dev, pipe); |
8d7849db VS |
1639 | } |
1640 | ||
91d14251 TU |
1641 | static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv, |
1642 | u32 iir, u32 pipe_stats[I915_MAX_PIPES]) | |
c1874ed7 | 1643 | { |
c1874ed7 ID |
1644 | int pipe; |
1645 | ||
58ead0d7 | 1646 | spin_lock(&dev_priv->irq_lock); |
1ca993d2 VS |
1647 | |
1648 | if (!dev_priv->display_irqs_enabled) { | |
1649 | spin_unlock(&dev_priv->irq_lock); | |
1650 | return; | |
1651 | } | |
1652 | ||
055e393f | 1653 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 1654 | i915_reg_t reg; |
bbb5eebf | 1655 | u32 mask, iir_bit = 0; |
91d181dd | 1656 | |
bbb5eebf DV |
1657 | /* |
1658 | * PIPESTAT bits get signalled even when the interrupt is | |
1659 | * disabled with the mask bits, and some of the status bits do | |
1660 | * not generate interrupts at all (like the underrun bit). Hence | |
1661 | * we need to be careful that we only handle what we want to | |
1662 | * handle. | |
1663 | */ | |
0f239f4c DV |
1664 | |
1665 | /* fifo underruns are filterered in the underrun handler. */ | |
1666 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1667 | |
1668 | switch (pipe) { | |
1669 | case PIPE_A: | |
1670 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1671 | break; | |
1672 | case PIPE_B: | |
1673 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1674 | break; | |
3278f67f VS |
1675 | case PIPE_C: |
1676 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1677 | break; | |
bbb5eebf DV |
1678 | } |
1679 | if (iir & iir_bit) | |
1680 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1681 | ||
1682 | if (!mask) | |
91d181dd ID |
1683 | continue; |
1684 | ||
1685 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1686 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1687 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1688 | |
1689 | /* | |
1690 | * Clear the PIPE*STAT regs before the IIR | |
1691 | */ | |
91d181dd ID |
1692 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1693 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1694 | I915_WRITE(reg, pipe_stats[pipe]); |
1695 | } | |
58ead0d7 | 1696 | spin_unlock(&dev_priv->irq_lock); |
2ecb8ca4 VS |
1697 | } |
1698 | ||
91d14251 | 1699 | static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, |
2ecb8ca4 VS |
1700 | u32 pipe_stats[I915_MAX_PIPES]) |
1701 | { | |
2ecb8ca4 | 1702 | enum pipe pipe; |
c1874ed7 | 1703 | |
055e393f | 1704 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 | 1705 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
91d14251 TU |
1706 | intel_pipe_handle_vblank(dev_priv, pipe)) |
1707 | intel_check_page_flip(dev_priv, pipe); | |
c1874ed7 | 1708 | |
579a9b0e | 1709 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
91d14251 TU |
1710 | intel_prepare_page_flip(dev_priv, pipe); |
1711 | intel_finish_page_flip(dev_priv, pipe); | |
c1874ed7 ID |
1712 | } |
1713 | ||
1714 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 1715 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
c1874ed7 | 1716 | |
1f7247c0 DV |
1717 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1718 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1719 | } |
1720 | ||
1721 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
91d14251 | 1722 | gmbus_irq_handler(dev_priv); |
c1874ed7 ID |
1723 | } |
1724 | ||
1ae3c34c | 1725 | static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) |
16c6c56b | 1726 | { |
16c6c56b VS |
1727 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
1728 | ||
1ae3c34c VS |
1729 | if (hotplug_status) |
1730 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
16c6c56b | 1731 | |
1ae3c34c VS |
1732 | return hotplug_status; |
1733 | } | |
1734 | ||
91d14251 | 1735 | static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, |
1ae3c34c VS |
1736 | u32 hotplug_status) |
1737 | { | |
1738 | u32 pin_mask = 0, long_mask = 0; | |
16c6c56b | 1739 | |
91d14251 TU |
1740 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
1741 | IS_CHERRYVIEW(dev_priv)) { | |
0d2e4297 | 1742 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; |
16c6c56b | 1743 | |
58f2cf24 VS |
1744 | if (hotplug_trigger) { |
1745 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1746 | hotplug_trigger, hpd_status_g4x, | |
1747 | i9xx_port_hotplug_long_detect); | |
1748 | ||
91d14251 | 1749 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
58f2cf24 | 1750 | } |
369712e8 JN |
1751 | |
1752 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
91d14251 | 1753 | dp_aux_irq_handler(dev_priv); |
0d2e4297 JN |
1754 | } else { |
1755 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1756 | |
58f2cf24 VS |
1757 | if (hotplug_trigger) { |
1758 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
44cc6c08 | 1759 | hotplug_trigger, hpd_status_i915, |
58f2cf24 | 1760 | i9xx_port_hotplug_long_detect); |
91d14251 | 1761 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
58f2cf24 | 1762 | } |
3ff60f89 | 1763 | } |
16c6c56b VS |
1764 | } |
1765 | ||
ff1f525e | 1766 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1767 | { |
45a83f84 | 1768 | struct drm_device *dev = arg; |
2d1013dd | 1769 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 1770 | irqreturn_t ret = IRQ_NONE; |
7e231dbe | 1771 | |
2dd2a883 ID |
1772 | if (!intel_irqs_enabled(dev_priv)) |
1773 | return IRQ_NONE; | |
1774 | ||
1f814dac ID |
1775 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
1776 | disable_rpm_wakeref_asserts(dev_priv); | |
1777 | ||
1e1cace9 | 1778 | do { |
6e814800 | 1779 | u32 iir, gt_iir, pm_iir; |
2ecb8ca4 | 1780 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
1ae3c34c | 1781 | u32 hotplug_status = 0; |
a5e485a9 | 1782 | u32 ier = 0; |
3ff60f89 | 1783 | |
7e231dbe JB |
1784 | gt_iir = I915_READ(GTIIR); |
1785 | pm_iir = I915_READ(GEN6_PMIIR); | |
3ff60f89 | 1786 | iir = I915_READ(VLV_IIR); |
7e231dbe JB |
1787 | |
1788 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1e1cace9 | 1789 | break; |
7e231dbe JB |
1790 | |
1791 | ret = IRQ_HANDLED; | |
1792 | ||
a5e485a9 VS |
1793 | /* |
1794 | * Theory on interrupt generation, based on empirical evidence: | |
1795 | * | |
1796 | * x = ((VLV_IIR & VLV_IER) || | |
1797 | * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && | |
1798 | * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); | |
1799 | * | |
1800 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. | |
1801 | * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to | |
1802 | * guarantee the CPU interrupt will be raised again even if we | |
1803 | * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR | |
1804 | * bits this time around. | |
1805 | */ | |
4a0a0202 | 1806 | I915_WRITE(VLV_MASTER_IER, 0); |
a5e485a9 VS |
1807 | ier = I915_READ(VLV_IER); |
1808 | I915_WRITE(VLV_IER, 0); | |
4a0a0202 VS |
1809 | |
1810 | if (gt_iir) | |
1811 | I915_WRITE(GTIIR, gt_iir); | |
1812 | if (pm_iir) | |
1813 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1814 | ||
7ce4d1f2 | 1815 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1ae3c34c | 1816 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
7ce4d1f2 | 1817 | |
3ff60f89 OM |
1818 | /* Call regardless, as some status bits might not be |
1819 | * signalled in iir */ | |
91d14251 | 1820 | valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
7ce4d1f2 VS |
1821 | |
1822 | /* | |
1823 | * VLV_IIR is single buffered, and reflects the level | |
1824 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. | |
1825 | */ | |
1826 | if (iir) | |
1827 | I915_WRITE(VLV_IIR, iir); | |
4a0a0202 | 1828 | |
a5e485a9 | 1829 | I915_WRITE(VLV_IER, ier); |
4a0a0202 VS |
1830 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
1831 | POSTING_READ(VLV_MASTER_IER); | |
1ae3c34c | 1832 | |
52894874 | 1833 | if (gt_iir) |
261e40b8 | 1834 | snb_gt_irq_handler(dev_priv, gt_iir); |
52894874 VS |
1835 | if (pm_iir) |
1836 | gen6_rps_irq_handler(dev_priv, pm_iir); | |
1837 | ||
1ae3c34c | 1838 | if (hotplug_status) |
91d14251 | 1839 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
2ecb8ca4 | 1840 | |
91d14251 | 1841 | valleyview_pipestat_irq_handler(dev_priv, pipe_stats); |
1e1cace9 | 1842 | } while (0); |
7e231dbe | 1843 | |
1f814dac ID |
1844 | enable_rpm_wakeref_asserts(dev_priv); |
1845 | ||
7e231dbe JB |
1846 | return ret; |
1847 | } | |
1848 | ||
43f328d7 VS |
1849 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1850 | { | |
45a83f84 | 1851 | struct drm_device *dev = arg; |
43f328d7 | 1852 | struct drm_i915_private *dev_priv = dev->dev_private; |
43f328d7 | 1853 | irqreturn_t ret = IRQ_NONE; |
43f328d7 | 1854 | |
2dd2a883 ID |
1855 | if (!intel_irqs_enabled(dev_priv)) |
1856 | return IRQ_NONE; | |
1857 | ||
1f814dac ID |
1858 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
1859 | disable_rpm_wakeref_asserts(dev_priv); | |
1860 | ||
579de73b | 1861 | do { |
6e814800 | 1862 | u32 master_ctl, iir; |
e30e251a | 1863 | u32 gt_iir[4] = {}; |
2ecb8ca4 | 1864 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
1ae3c34c | 1865 | u32 hotplug_status = 0; |
a5e485a9 VS |
1866 | u32 ier = 0; |
1867 | ||
8e5fd599 VS |
1868 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; |
1869 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1870 | |
8e5fd599 VS |
1871 | if (master_ctl == 0 && iir == 0) |
1872 | break; | |
43f328d7 | 1873 | |
27b6c122 OM |
1874 | ret = IRQ_HANDLED; |
1875 | ||
a5e485a9 VS |
1876 | /* |
1877 | * Theory on interrupt generation, based on empirical evidence: | |
1878 | * | |
1879 | * x = ((VLV_IIR & VLV_IER) || | |
1880 | * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && | |
1881 | * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); | |
1882 | * | |
1883 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. | |
1884 | * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to | |
1885 | * guarantee the CPU interrupt will be raised again even if we | |
1886 | * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL | |
1887 | * bits this time around. | |
1888 | */ | |
8e5fd599 | 1889 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
a5e485a9 VS |
1890 | ier = I915_READ(VLV_IER); |
1891 | I915_WRITE(VLV_IER, 0); | |
43f328d7 | 1892 | |
e30e251a | 1893 | gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
43f328d7 | 1894 | |
7ce4d1f2 | 1895 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1ae3c34c | 1896 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
7ce4d1f2 | 1897 | |
27b6c122 OM |
1898 | /* Call regardless, as some status bits might not be |
1899 | * signalled in iir */ | |
91d14251 | 1900 | valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
43f328d7 | 1901 | |
7ce4d1f2 VS |
1902 | /* |
1903 | * VLV_IIR is single buffered, and reflects the level | |
1904 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. | |
1905 | */ | |
1906 | if (iir) | |
1907 | I915_WRITE(VLV_IIR, iir); | |
1908 | ||
a5e485a9 | 1909 | I915_WRITE(VLV_IER, ier); |
e5328c43 | 1910 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
8e5fd599 | 1911 | POSTING_READ(GEN8_MASTER_IRQ); |
1ae3c34c | 1912 | |
e30e251a VS |
1913 | gen8_gt_irq_handler(dev_priv, gt_iir); |
1914 | ||
1ae3c34c | 1915 | if (hotplug_status) |
91d14251 | 1916 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
2ecb8ca4 | 1917 | |
91d14251 | 1918 | valleyview_pipestat_irq_handler(dev_priv, pipe_stats); |
579de73b | 1919 | } while (0); |
3278f67f | 1920 | |
1f814dac ID |
1921 | enable_rpm_wakeref_asserts(dev_priv); |
1922 | ||
43f328d7 VS |
1923 | return ret; |
1924 | } | |
1925 | ||
91d14251 TU |
1926 | static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, |
1927 | u32 hotplug_trigger, | |
40e56410 VS |
1928 | const u32 hpd[HPD_NUM_PINS]) |
1929 | { | |
40e56410 VS |
1930 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
1931 | ||
6a39d7c9 JN |
1932 | /* |
1933 | * Somehow the PCH doesn't seem to really ack the interrupt to the CPU | |
1934 | * unless we touch the hotplug register, even if hotplug_trigger is | |
1935 | * zero. Not acking leads to "The master control interrupt lied (SDE)!" | |
1936 | * errors. | |
1937 | */ | |
40e56410 | 1938 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
6a39d7c9 JN |
1939 | if (!hotplug_trigger) { |
1940 | u32 mask = PORTA_HOTPLUG_STATUS_MASK | | |
1941 | PORTD_HOTPLUG_STATUS_MASK | | |
1942 | PORTC_HOTPLUG_STATUS_MASK | | |
1943 | PORTB_HOTPLUG_STATUS_MASK; | |
1944 | dig_hotplug_reg &= ~mask; | |
1945 | } | |
1946 | ||
40e56410 | 1947 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
6a39d7c9 JN |
1948 | if (!hotplug_trigger) |
1949 | return; | |
40e56410 VS |
1950 | |
1951 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1952 | dig_hotplug_reg, hpd, | |
1953 | pch_port_hotplug_long_detect); | |
1954 | ||
91d14251 | 1955 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
40e56410 VS |
1956 | } |
1957 | ||
91d14251 | 1958 | static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
776ad806 | 1959 | { |
9db4a9c7 | 1960 | int pipe; |
b543fb04 | 1961 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 | 1962 | |
91d14251 | 1963 | ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx); |
91d131d2 | 1964 | |
cfc33bf7 VS |
1965 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1966 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1967 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1968 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1969 | port_name(port)); |
1970 | } | |
776ad806 | 1971 | |
ce99c256 | 1972 | if (pch_iir & SDE_AUX_MASK) |
91d14251 | 1973 | dp_aux_irq_handler(dev_priv); |
ce99c256 | 1974 | |
776ad806 | 1975 | if (pch_iir & SDE_GMBUS) |
91d14251 | 1976 | gmbus_irq_handler(dev_priv); |
776ad806 JB |
1977 | |
1978 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1979 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1980 | ||
1981 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1982 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1983 | ||
1984 | if (pch_iir & SDE_POISON) | |
1985 | DRM_ERROR("PCH poison interrupt\n"); | |
1986 | ||
9db4a9c7 | 1987 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 1988 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
1989 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1990 | pipe_name(pipe), | |
1991 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1992 | |
1993 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1994 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1995 | ||
1996 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1997 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1998 | ||
776ad806 | 1999 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 2000 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2001 | |
2002 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 2003 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2004 | } |
2005 | ||
91d14251 | 2006 | static void ivb_err_int_handler(struct drm_i915_private *dev_priv) |
8664281b | 2007 | { |
8664281b | 2008 | u32 err_int = I915_READ(GEN7_ERR_INT); |
5a69b89f | 2009 | enum pipe pipe; |
8664281b | 2010 | |
de032bf4 PZ |
2011 | if (err_int & ERR_INT_POISON) |
2012 | DRM_ERROR("Poison interrupt\n"); | |
2013 | ||
055e393f | 2014 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
2015 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
2016 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 2017 | |
5a69b89f | 2018 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
91d14251 TU |
2019 | if (IS_IVYBRIDGE(dev_priv)) |
2020 | ivb_pipe_crc_irq_handler(dev_priv, pipe); | |
5a69b89f | 2021 | else |
91d14251 | 2022 | hsw_pipe_crc_irq_handler(dev_priv, pipe); |
5a69b89f DV |
2023 | } |
2024 | } | |
8bf1e9f1 | 2025 | |
8664281b PZ |
2026 | I915_WRITE(GEN7_ERR_INT, err_int); |
2027 | } | |
2028 | ||
91d14251 | 2029 | static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) |
8664281b | 2030 | { |
8664281b PZ |
2031 | u32 serr_int = I915_READ(SERR_INT); |
2032 | ||
de032bf4 PZ |
2033 | if (serr_int & SERR_INT_POISON) |
2034 | DRM_ERROR("PCH poison interrupt\n"); | |
2035 | ||
8664281b | 2036 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 2037 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2038 | |
2039 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 2040 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2041 | |
2042 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 2043 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
2044 | |
2045 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
2046 | } |
2047 | ||
91d14251 | 2048 | static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
23e81d69 | 2049 | { |
23e81d69 | 2050 | int pipe; |
6dbf30ce | 2051 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 | 2052 | |
91d14251 | 2053 | ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt); |
91d131d2 | 2054 | |
cfc33bf7 VS |
2055 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
2056 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
2057 | SDE_AUDIO_POWER_SHIFT_CPT); | |
2058 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
2059 | port_name(port)); | |
2060 | } | |
23e81d69 AJ |
2061 | |
2062 | if (pch_iir & SDE_AUX_MASK_CPT) | |
91d14251 | 2063 | dp_aux_irq_handler(dev_priv); |
23e81d69 AJ |
2064 | |
2065 | if (pch_iir & SDE_GMBUS_CPT) | |
91d14251 | 2066 | gmbus_irq_handler(dev_priv); |
23e81d69 AJ |
2067 | |
2068 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
2069 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
2070 | ||
2071 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
2072 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
2073 | ||
2074 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 2075 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
2076 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2077 | pipe_name(pipe), | |
2078 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
2079 | |
2080 | if (pch_iir & SDE_ERROR_CPT) | |
91d14251 | 2081 | cpt_serr_int_handler(dev_priv); |
23e81d69 AJ |
2082 | } |
2083 | ||
91d14251 | 2084 | static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
6dbf30ce | 2085 | { |
6dbf30ce VS |
2086 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & |
2087 | ~SDE_PORTE_HOTPLUG_SPT; | |
2088 | u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; | |
2089 | u32 pin_mask = 0, long_mask = 0; | |
2090 | ||
2091 | if (hotplug_trigger) { | |
2092 | u32 dig_hotplug_reg; | |
2093 | ||
2094 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
2095 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
2096 | ||
2097 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2098 | dig_hotplug_reg, hpd_spt, | |
74c0b395 | 2099 | spt_port_hotplug_long_detect); |
6dbf30ce VS |
2100 | } |
2101 | ||
2102 | if (hotplug2_trigger) { | |
2103 | u32 dig_hotplug_reg; | |
2104 | ||
2105 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2); | |
2106 | I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg); | |
2107 | ||
2108 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger, | |
2109 | dig_hotplug_reg, hpd_spt, | |
2110 | spt_port_hotplug2_long_detect); | |
2111 | } | |
2112 | ||
2113 | if (pin_mask) | |
91d14251 | 2114 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
6dbf30ce VS |
2115 | |
2116 | if (pch_iir & SDE_GMBUS_CPT) | |
91d14251 | 2117 | gmbus_irq_handler(dev_priv); |
6dbf30ce VS |
2118 | } |
2119 | ||
91d14251 TU |
2120 | static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2121 | u32 hotplug_trigger, | |
40e56410 VS |
2122 | const u32 hpd[HPD_NUM_PINS]) |
2123 | { | |
40e56410 VS |
2124 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
2125 | ||
2126 | dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
2127 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); | |
2128 | ||
2129 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2130 | dig_hotplug_reg, hpd, | |
2131 | ilk_port_hotplug_long_detect); | |
2132 | ||
91d14251 | 2133 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
40e56410 VS |
2134 | } |
2135 | ||
91d14251 TU |
2136 | static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, |
2137 | u32 de_iir) | |
c008bc6e | 2138 | { |
40da17c2 | 2139 | enum pipe pipe; |
e4ce95aa VS |
2140 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; |
2141 | ||
40e56410 | 2142 | if (hotplug_trigger) |
91d14251 | 2143 | ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk); |
c008bc6e PZ |
2144 | |
2145 | if (de_iir & DE_AUX_CHANNEL_A) | |
91d14251 | 2146 | dp_aux_irq_handler(dev_priv); |
c008bc6e PZ |
2147 | |
2148 | if (de_iir & DE_GSE) | |
91d14251 | 2149 | intel_opregion_asle_intr(dev_priv); |
c008bc6e | 2150 | |
c008bc6e PZ |
2151 | if (de_iir & DE_POISON) |
2152 | DRM_ERROR("Poison interrupt\n"); | |
2153 | ||
055e393f | 2154 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 | 2155 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
91d14251 TU |
2156 | intel_pipe_handle_vblank(dev_priv, pipe)) |
2157 | intel_check_page_flip(dev_priv, pipe); | |
5b3a856b | 2158 | |
40da17c2 | 2159 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2160 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2161 | |
40da17c2 | 2162 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
91d14251 | 2163 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
c008bc6e | 2164 | |
40da17c2 DV |
2165 | /* plane/pipes map 1:1 on ilk+ */ |
2166 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
91d14251 TU |
2167 | intel_prepare_page_flip(dev_priv, pipe); |
2168 | intel_finish_page_flip_plane(dev_priv, pipe); | |
40da17c2 | 2169 | } |
c008bc6e PZ |
2170 | } |
2171 | ||
2172 | /* check event from PCH */ | |
2173 | if (de_iir & DE_PCH_EVENT) { | |
2174 | u32 pch_iir = I915_READ(SDEIIR); | |
2175 | ||
91d14251 TU |
2176 | if (HAS_PCH_CPT(dev_priv)) |
2177 | cpt_irq_handler(dev_priv, pch_iir); | |
c008bc6e | 2178 | else |
91d14251 | 2179 | ibx_irq_handler(dev_priv, pch_iir); |
c008bc6e PZ |
2180 | |
2181 | /* should clear PCH hotplug event before clear CPU irq */ | |
2182 | I915_WRITE(SDEIIR, pch_iir); | |
2183 | } | |
2184 | ||
91d14251 TU |
2185 | if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT) |
2186 | ironlake_rps_change_irq_handler(dev_priv); | |
c008bc6e PZ |
2187 | } |
2188 | ||
91d14251 TU |
2189 | static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, |
2190 | u32 de_iir) | |
9719fb98 | 2191 | { |
07d27e20 | 2192 | enum pipe pipe; |
23bb4cb5 VS |
2193 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; |
2194 | ||
40e56410 | 2195 | if (hotplug_trigger) |
91d14251 | 2196 | ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb); |
9719fb98 PZ |
2197 | |
2198 | if (de_iir & DE_ERR_INT_IVB) | |
91d14251 | 2199 | ivb_err_int_handler(dev_priv); |
9719fb98 PZ |
2200 | |
2201 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
91d14251 | 2202 | dp_aux_irq_handler(dev_priv); |
9719fb98 PZ |
2203 | |
2204 | if (de_iir & DE_GSE_IVB) | |
91d14251 | 2205 | intel_opregion_asle_intr(dev_priv); |
9719fb98 | 2206 | |
055e393f | 2207 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 | 2208 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
91d14251 TU |
2209 | intel_pipe_handle_vblank(dev_priv, pipe)) |
2210 | intel_check_page_flip(dev_priv, pipe); | |
40da17c2 DV |
2211 | |
2212 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 | 2213 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
91d14251 TU |
2214 | intel_prepare_page_flip(dev_priv, pipe); |
2215 | intel_finish_page_flip_plane(dev_priv, pipe); | |
9719fb98 PZ |
2216 | } |
2217 | } | |
2218 | ||
2219 | /* check event from PCH */ | |
91d14251 | 2220 | if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { |
9719fb98 PZ |
2221 | u32 pch_iir = I915_READ(SDEIIR); |
2222 | ||
91d14251 | 2223 | cpt_irq_handler(dev_priv, pch_iir); |
9719fb98 PZ |
2224 | |
2225 | /* clear PCH hotplug event before clear CPU irq */ | |
2226 | I915_WRITE(SDEIIR, pch_iir); | |
2227 | } | |
2228 | } | |
2229 | ||
72c90f62 OM |
2230 | /* |
2231 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2232 | * 1 - Disable Master Interrupt Control. | |
2233 | * 2 - Find the source(s) of the interrupt. | |
2234 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2235 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2236 | * 5 - Re-enable Master Interrupt Control. | |
2237 | */ | |
f1af8fc1 | 2238 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2239 | { |
45a83f84 | 2240 | struct drm_device *dev = arg; |
2d1013dd | 2241 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2242 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2243 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2244 | |
2dd2a883 ID |
2245 | if (!intel_irqs_enabled(dev_priv)) |
2246 | return IRQ_NONE; | |
2247 | ||
1f814dac ID |
2248 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
2249 | disable_rpm_wakeref_asserts(dev_priv); | |
2250 | ||
b1f14ad0 JB |
2251 | /* disable master interrupt before clearing iir */ |
2252 | de_ier = I915_READ(DEIER); | |
2253 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2254 | POSTING_READ(DEIER); |
b1f14ad0 | 2255 | |
44498aea PZ |
2256 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2257 | * interrupts will will be stored on its back queue, and then we'll be | |
2258 | * able to process them after we restore SDEIER (as soon as we restore | |
2259 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2260 | * due to its back queue). */ | |
91d14251 | 2261 | if (!HAS_PCH_NOP(dev_priv)) { |
ab5c608b BW |
2262 | sde_ier = I915_READ(SDEIER); |
2263 | I915_WRITE(SDEIER, 0); | |
2264 | POSTING_READ(SDEIER); | |
2265 | } | |
44498aea | 2266 | |
72c90f62 OM |
2267 | /* Find, clear, then process each source of interrupt */ |
2268 | ||
b1f14ad0 | 2269 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2270 | if (gt_iir) { |
72c90f62 OM |
2271 | I915_WRITE(GTIIR, gt_iir); |
2272 | ret = IRQ_HANDLED; | |
91d14251 | 2273 | if (INTEL_GEN(dev_priv) >= 6) |
261e40b8 | 2274 | snb_gt_irq_handler(dev_priv, gt_iir); |
d8fc8a47 | 2275 | else |
261e40b8 | 2276 | ilk_gt_irq_handler(dev_priv, gt_iir); |
b1f14ad0 JB |
2277 | } |
2278 | ||
0e43406b CW |
2279 | de_iir = I915_READ(DEIIR); |
2280 | if (de_iir) { | |
72c90f62 OM |
2281 | I915_WRITE(DEIIR, de_iir); |
2282 | ret = IRQ_HANDLED; | |
91d14251 TU |
2283 | if (INTEL_GEN(dev_priv) >= 7) |
2284 | ivb_display_irq_handler(dev_priv, de_iir); | |
f1af8fc1 | 2285 | else |
91d14251 | 2286 | ilk_display_irq_handler(dev_priv, de_iir); |
b1f14ad0 JB |
2287 | } |
2288 | ||
91d14251 | 2289 | if (INTEL_GEN(dev_priv) >= 6) { |
f1af8fc1 PZ |
2290 | u32 pm_iir = I915_READ(GEN6_PMIIR); |
2291 | if (pm_iir) { | |
f1af8fc1 PZ |
2292 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2293 | ret = IRQ_HANDLED; | |
72c90f62 | 2294 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2295 | } |
0e43406b | 2296 | } |
b1f14ad0 | 2297 | |
b1f14ad0 JB |
2298 | I915_WRITE(DEIER, de_ier); |
2299 | POSTING_READ(DEIER); | |
91d14251 | 2300 | if (!HAS_PCH_NOP(dev_priv)) { |
ab5c608b BW |
2301 | I915_WRITE(SDEIER, sde_ier); |
2302 | POSTING_READ(SDEIER); | |
2303 | } | |
b1f14ad0 | 2304 | |
1f814dac ID |
2305 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
2306 | enable_rpm_wakeref_asserts(dev_priv); | |
2307 | ||
b1f14ad0 JB |
2308 | return ret; |
2309 | } | |
2310 | ||
91d14251 TU |
2311 | static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2312 | u32 hotplug_trigger, | |
40e56410 | 2313 | const u32 hpd[HPD_NUM_PINS]) |
d04a492d | 2314 | { |
cebd87a0 | 2315 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
d04a492d | 2316 | |
a52bb15b VS |
2317 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
2318 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
d04a492d | 2319 | |
cebd87a0 | 2320 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, |
40e56410 | 2321 | dig_hotplug_reg, hpd, |
cebd87a0 | 2322 | bxt_port_hotplug_long_detect); |
40e56410 | 2323 | |
91d14251 | 2324 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
d04a492d SS |
2325 | } |
2326 | ||
f11a0f46 TU |
2327 | static irqreturn_t |
2328 | gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) | |
abd58f01 | 2329 | { |
abd58f01 | 2330 | irqreturn_t ret = IRQ_NONE; |
f11a0f46 | 2331 | u32 iir; |
c42664cc | 2332 | enum pipe pipe; |
88e04703 | 2333 | |
abd58f01 | 2334 | if (master_ctl & GEN8_DE_MISC_IRQ) { |
e32192e1 TU |
2335 | iir = I915_READ(GEN8_DE_MISC_IIR); |
2336 | if (iir) { | |
2337 | I915_WRITE(GEN8_DE_MISC_IIR, iir); | |
abd58f01 | 2338 | ret = IRQ_HANDLED; |
e32192e1 | 2339 | if (iir & GEN8_DE_MISC_GSE) |
91d14251 | 2340 | intel_opregion_asle_intr(dev_priv); |
38cc46d7 OM |
2341 | else |
2342 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2343 | } |
38cc46d7 OM |
2344 | else |
2345 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2346 | } |
2347 | ||
6d766f02 | 2348 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
e32192e1 TU |
2349 | iir = I915_READ(GEN8_DE_PORT_IIR); |
2350 | if (iir) { | |
2351 | u32 tmp_mask; | |
d04a492d | 2352 | bool found = false; |
cebd87a0 | 2353 | |
e32192e1 | 2354 | I915_WRITE(GEN8_DE_PORT_IIR, iir); |
6d766f02 | 2355 | ret = IRQ_HANDLED; |
88e04703 | 2356 | |
e32192e1 TU |
2357 | tmp_mask = GEN8_AUX_CHANNEL_A; |
2358 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2359 | tmp_mask |= GEN9_AUX_CHANNEL_B | | |
2360 | GEN9_AUX_CHANNEL_C | | |
2361 | GEN9_AUX_CHANNEL_D; | |
2362 | ||
2363 | if (iir & tmp_mask) { | |
91d14251 | 2364 | dp_aux_irq_handler(dev_priv); |
d04a492d SS |
2365 | found = true; |
2366 | } | |
2367 | ||
e32192e1 TU |
2368 | if (IS_BROXTON(dev_priv)) { |
2369 | tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK; | |
2370 | if (tmp_mask) { | |
91d14251 TU |
2371 | bxt_hpd_irq_handler(dev_priv, tmp_mask, |
2372 | hpd_bxt); | |
e32192e1 TU |
2373 | found = true; |
2374 | } | |
2375 | } else if (IS_BROADWELL(dev_priv)) { | |
2376 | tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG; | |
2377 | if (tmp_mask) { | |
91d14251 TU |
2378 | ilk_hpd_irq_handler(dev_priv, |
2379 | tmp_mask, hpd_bdw); | |
e32192e1 TU |
2380 | found = true; |
2381 | } | |
d04a492d SS |
2382 | } |
2383 | ||
91d14251 TU |
2384 | if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { |
2385 | gmbus_irq_handler(dev_priv); | |
9e63743e SS |
2386 | found = true; |
2387 | } | |
2388 | ||
d04a492d | 2389 | if (!found) |
38cc46d7 | 2390 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
6d766f02 | 2391 | } |
38cc46d7 OM |
2392 | else |
2393 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2394 | } |
2395 | ||
055e393f | 2396 | for_each_pipe(dev_priv, pipe) { |
e32192e1 | 2397 | u32 flip_done, fault_errors; |
abd58f01 | 2398 | |
c42664cc DV |
2399 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2400 | continue; | |
abd58f01 | 2401 | |
e32192e1 TU |
2402 | iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
2403 | if (!iir) { | |
2404 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); | |
2405 | continue; | |
2406 | } | |
770de83d | 2407 | |
e32192e1 TU |
2408 | ret = IRQ_HANDLED; |
2409 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); | |
38cc46d7 | 2410 | |
e32192e1 | 2411 | if (iir & GEN8_PIPE_VBLANK && |
91d14251 TU |
2412 | intel_pipe_handle_vblank(dev_priv, pipe)) |
2413 | intel_check_page_flip(dev_priv, pipe); | |
770de83d | 2414 | |
e32192e1 TU |
2415 | flip_done = iir; |
2416 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2417 | flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE; | |
2418 | else | |
2419 | flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE; | |
38cc46d7 | 2420 | |
e32192e1 | 2421 | if (flip_done) { |
91d14251 TU |
2422 | intel_prepare_page_flip(dev_priv, pipe); |
2423 | intel_finish_page_flip_plane(dev_priv, pipe); | |
e32192e1 | 2424 | } |
38cc46d7 | 2425 | |
e32192e1 | 2426 | if (iir & GEN8_PIPE_CDCLK_CRC_DONE) |
91d14251 | 2427 | hsw_pipe_crc_irq_handler(dev_priv, pipe); |
38cc46d7 | 2428 | |
e32192e1 TU |
2429 | if (iir & GEN8_PIPE_FIFO_UNDERRUN) |
2430 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
770de83d | 2431 | |
e32192e1 TU |
2432 | fault_errors = iir; |
2433 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2434 | fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2435 | else | |
2436 | fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
770de83d | 2437 | |
e32192e1 TU |
2438 | if (fault_errors) |
2439 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", | |
2440 | pipe_name(pipe), | |
2441 | fault_errors); | |
abd58f01 BW |
2442 | } |
2443 | ||
91d14251 | 2444 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && |
266ea3d9 | 2445 | master_ctl & GEN8_DE_PCH_IRQ) { |
92d03a80 DV |
2446 | /* |
2447 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2448 | * scheme also closed the SDE interrupt handling race we've seen | |
2449 | * on older pch-split platforms. But this needs testing. | |
2450 | */ | |
e32192e1 TU |
2451 | iir = I915_READ(SDEIIR); |
2452 | if (iir) { | |
2453 | I915_WRITE(SDEIIR, iir); | |
92d03a80 | 2454 | ret = IRQ_HANDLED; |
6dbf30ce VS |
2455 | |
2456 | if (HAS_PCH_SPT(dev_priv)) | |
91d14251 | 2457 | spt_irq_handler(dev_priv, iir); |
6dbf30ce | 2458 | else |
91d14251 | 2459 | cpt_irq_handler(dev_priv, iir); |
2dfb0b81 JN |
2460 | } else { |
2461 | /* | |
2462 | * Like on previous PCH there seems to be something | |
2463 | * fishy going on with forwarding PCH interrupts. | |
2464 | */ | |
2465 | DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n"); | |
2466 | } | |
92d03a80 DV |
2467 | } |
2468 | ||
f11a0f46 TU |
2469 | return ret; |
2470 | } | |
2471 | ||
2472 | static irqreturn_t gen8_irq_handler(int irq, void *arg) | |
2473 | { | |
2474 | struct drm_device *dev = arg; | |
2475 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2476 | u32 master_ctl; | |
e30e251a | 2477 | u32 gt_iir[4] = {}; |
f11a0f46 TU |
2478 | irqreturn_t ret; |
2479 | ||
2480 | if (!intel_irqs_enabled(dev_priv)) | |
2481 | return IRQ_NONE; | |
2482 | ||
2483 | master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); | |
2484 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2485 | if (!master_ctl) | |
2486 | return IRQ_NONE; | |
2487 | ||
2488 | I915_WRITE_FW(GEN8_MASTER_IRQ, 0); | |
2489 | ||
2490 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ | |
2491 | disable_rpm_wakeref_asserts(dev_priv); | |
2492 | ||
2493 | /* Find, clear, then process each source of interrupt */ | |
e30e251a VS |
2494 | ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
2495 | gen8_gt_irq_handler(dev_priv, gt_iir); | |
f11a0f46 TU |
2496 | ret |= gen8_de_irq_handler(dev_priv, master_ctl); |
2497 | ||
cb0d205e CW |
2498 | I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2499 | POSTING_READ_FW(GEN8_MASTER_IRQ); | |
abd58f01 | 2500 | |
1f814dac ID |
2501 | enable_rpm_wakeref_asserts(dev_priv); |
2502 | ||
abd58f01 BW |
2503 | return ret; |
2504 | } | |
2505 | ||
17e1df07 DV |
2506 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2507 | bool reset_completed) | |
2508 | { | |
e2f80391 | 2509 | struct intel_engine_cs *engine; |
17e1df07 DV |
2510 | |
2511 | /* | |
2512 | * Notify all waiters for GPU completion events that reset state has | |
2513 | * been changed, and that they need to restart their wait after | |
2514 | * checking for potential errors (and bail out to drop locks if there is | |
2515 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2516 | */ | |
2517 | ||
2518 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
b4ac5afc | 2519 | for_each_engine(engine, dev_priv) |
e2f80391 | 2520 | wake_up_all(&engine->irq_queue); |
17e1df07 DV |
2521 | |
2522 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2523 | wake_up_all(&dev_priv->pending_flip_queue); | |
2524 | ||
2525 | /* | |
2526 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2527 | * reset state is cleared. | |
2528 | */ | |
2529 | if (reset_completed) | |
2530 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2531 | } | |
2532 | ||
8a905236 | 2533 | /** |
b8d24a06 | 2534 | * i915_reset_and_wakeup - do process context error handling work |
468f9d29 | 2535 | * @dev: drm device |
8a905236 JB |
2536 | * |
2537 | * Fire an error uevent so userspace can see that a hang or error | |
2538 | * was detected. | |
2539 | */ | |
c033666a | 2540 | static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv) |
8a905236 | 2541 | { |
c033666a | 2542 | struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj; |
cce723ed BW |
2543 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2544 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2545 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2546 | int ret; |
8a905236 | 2547 | |
c033666a | 2548 | kobject_uevent_env(kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2549 | |
7db0ba24 DV |
2550 | /* |
2551 | * Note that there's only one work item which does gpu resets, so we | |
2552 | * need not worry about concurrent gpu resets potentially incrementing | |
2553 | * error->reset_counter twice. We only need to take care of another | |
2554 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2555 | * quick check for that is good enough: schedule_work ensures the | |
2556 | * correct ordering between hang detection and this work item, and since | |
2557 | * the reset in-progress bit is only ever set by code outside of this | |
2558 | * work we don't need to worry about any other races. | |
2559 | */ | |
d98c52cf | 2560 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
f803aa55 | 2561 | DRM_DEBUG_DRIVER("resetting chip\n"); |
c033666a | 2562 | kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event); |
1f83fee0 | 2563 | |
f454c694 ID |
2564 | /* |
2565 | * In most cases it's guaranteed that we get here with an RPM | |
2566 | * reference held, for example because there is a pending GPU | |
2567 | * request that won't finish until the reset is done. This | |
2568 | * isn't the case at least when we get here by doing a | |
2569 | * simulated reset via debugs, so get an RPM reference. | |
2570 | */ | |
2571 | intel_runtime_pm_get(dev_priv); | |
7514747d | 2572 | |
c033666a | 2573 | intel_prepare_reset(dev_priv); |
7514747d | 2574 | |
17e1df07 DV |
2575 | /* |
2576 | * All state reset _must_ be completed before we update the | |
2577 | * reset counter, for otherwise waiters might miss the reset | |
2578 | * pending state and not properly drop locks, resulting in | |
2579 | * deadlocks with the reset work. | |
2580 | */ | |
c033666a | 2581 | ret = i915_reset(dev_priv); |
f69061be | 2582 | |
c033666a | 2583 | intel_finish_reset(dev_priv); |
17e1df07 | 2584 | |
f454c694 ID |
2585 | intel_runtime_pm_put(dev_priv); |
2586 | ||
d98c52cf | 2587 | if (ret == 0) |
c033666a | 2588 | kobject_uevent_env(kobj, |
f69061be | 2589 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2590 | |
17e1df07 DV |
2591 | /* |
2592 | * Note: The wake_up also serves as a memory barrier so that | |
2593 | * waiters see the update value of the reset counter atomic_t. | |
2594 | */ | |
2595 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2596 | } |
8a905236 JB |
2597 | } |
2598 | ||
c033666a | 2599 | static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv) |
8a905236 | 2600 | { |
bd9854f9 | 2601 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2602 | u32 eir = I915_READ(EIR); |
050ee91f | 2603 | int pipe, i; |
8a905236 | 2604 | |
35aed2e6 CW |
2605 | if (!eir) |
2606 | return; | |
8a905236 | 2607 | |
a70491cc | 2608 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2609 | |
c033666a | 2610 | i915_get_extra_instdone(dev_priv, instdone); |
bd9854f9 | 2611 | |
c033666a | 2612 | if (IS_G4X(dev_priv)) { |
8a905236 JB |
2613 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
2614 | u32 ipeir = I915_READ(IPEIR_I965); | |
2615 | ||
a70491cc JP |
2616 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2617 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2618 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2619 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2620 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2621 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2622 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2623 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2624 | } |
2625 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2626 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2627 | pr_err("page table error\n"); |
2628 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2629 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2630 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2631 | } |
2632 | } | |
2633 | ||
c033666a | 2634 | if (!IS_GEN2(dev_priv)) { |
8a905236 JB |
2635 | if (eir & I915_ERROR_PAGE_TABLE) { |
2636 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2637 | pr_err("page table error\n"); |
2638 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2639 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2640 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2641 | } |
2642 | } | |
2643 | ||
2644 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2645 | pr_err("memory refresh error:\n"); |
055e393f | 2646 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2647 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2648 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2649 | /* pipestat has already been acked */ |
2650 | } | |
2651 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2652 | pr_err("instruction error\n"); |
2653 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2654 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2655 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
c033666a | 2656 | if (INTEL_GEN(dev_priv) < 4) { |
8a905236 JB |
2657 | u32 ipeir = I915_READ(IPEIR); |
2658 | ||
a70491cc JP |
2659 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2660 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2661 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2662 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2663 | POSTING_READ(IPEIR); |
8a905236 JB |
2664 | } else { |
2665 | u32 ipeir = I915_READ(IPEIR_I965); | |
2666 | ||
a70491cc JP |
2667 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2668 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2669 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2670 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2671 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2672 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2673 | } |
2674 | } | |
2675 | ||
2676 | I915_WRITE(EIR, eir); | |
3143a2bf | 2677 | POSTING_READ(EIR); |
8a905236 JB |
2678 | eir = I915_READ(EIR); |
2679 | if (eir) { | |
2680 | /* | |
2681 | * some errors might have become stuck, | |
2682 | * mask them. | |
2683 | */ | |
2684 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2685 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2686 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2687 | } | |
35aed2e6 CW |
2688 | } |
2689 | ||
2690 | /** | |
b8d24a06 | 2691 | * i915_handle_error - handle a gpu error |
35aed2e6 | 2692 | * @dev: drm device |
14b730fc | 2693 | * @engine_mask: mask representing engines that are hung |
aafd8581 | 2694 | * Do some basic checking of register state at error time and |
35aed2e6 CW |
2695 | * dump it to the syslog. Also call i915_capture_error_state() to make |
2696 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2697 | * so userspace knows something bad happened (should trigger collection | |
2698 | * of a ring dump etc.). | |
2699 | */ | |
c033666a CW |
2700 | void i915_handle_error(struct drm_i915_private *dev_priv, |
2701 | u32 engine_mask, | |
58174462 | 2702 | const char *fmt, ...) |
35aed2e6 | 2703 | { |
58174462 MK |
2704 | va_list args; |
2705 | char error_msg[80]; | |
35aed2e6 | 2706 | |
58174462 MK |
2707 | va_start(args, fmt); |
2708 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2709 | va_end(args); | |
2710 | ||
c033666a CW |
2711 | i915_capture_error_state(dev_priv, engine_mask, error_msg); |
2712 | i915_report_and_clear_eir(dev_priv); | |
8a905236 | 2713 | |
14b730fc | 2714 | if (engine_mask) { |
805de8f4 | 2715 | atomic_or(I915_RESET_IN_PROGRESS_FLAG, |
f69061be | 2716 | &dev_priv->gpu_error.reset_counter); |
ba1234d1 | 2717 | |
11ed50ec | 2718 | /* |
b8d24a06 MK |
2719 | * Wakeup waiting processes so that the reset function |
2720 | * i915_reset_and_wakeup doesn't deadlock trying to grab | |
2721 | * various locks. By bumping the reset counter first, the woken | |
17e1df07 DV |
2722 | * processes will see a reset in progress and back off, |
2723 | * releasing their locks and then wait for the reset completion. | |
2724 | * We must do this for _all_ gpu waiters that might hold locks | |
2725 | * that the reset work needs to acquire. | |
2726 | * | |
2727 | * Note: The wake_up serves as the required memory barrier to | |
2728 | * ensure that the waiters see the updated value of the reset | |
2729 | * counter atomic_t. | |
11ed50ec | 2730 | */ |
17e1df07 | 2731 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2732 | } |
2733 | ||
c033666a | 2734 | i915_reset_and_wakeup(dev_priv); |
8a905236 JB |
2735 | } |
2736 | ||
42f52ef8 KP |
2737 | /* Called from drm generic code, passed 'crtc' which |
2738 | * we use as a pipe index | |
2739 | */ | |
88e72717 | 2740 | static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 2741 | { |
2d1013dd | 2742 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2743 | unsigned long irqflags; |
71e0ffa5 | 2744 | |
1ec14ad3 | 2745 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2746 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2747 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2748 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2749 | else |
7c463586 | 2750 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2751 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2752 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2753 | |
0a3e67a4 JB |
2754 | return 0; |
2755 | } | |
2756 | ||
88e72717 | 2757 | static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) |
f796cf8f | 2758 | { |
2d1013dd | 2759 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2760 | unsigned long irqflags; |
b518421f | 2761 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2762 | DE_PIPE_VBLANK(pipe); |
f796cf8f | 2763 | |
f796cf8f | 2764 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
fbdedaea | 2765 | ilk_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2766 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2767 | ||
2768 | return 0; | |
2769 | } | |
2770 | ||
88e72717 | 2771 | static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe) |
7e231dbe | 2772 | { |
2d1013dd | 2773 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2774 | unsigned long irqflags; |
7e231dbe | 2775 | |
7e231dbe | 2776 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2777 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2778 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2779 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2780 | ||
2781 | return 0; | |
2782 | } | |
2783 | ||
88e72717 | 2784 | static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) |
abd58f01 BW |
2785 | { |
2786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2787 | unsigned long irqflags; | |
abd58f01 | 2788 | |
abd58f01 | 2789 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
013d3752 | 2790 | bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
abd58f01 | 2791 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
013d3752 | 2792 | |
abd58f01 BW |
2793 | return 0; |
2794 | } | |
2795 | ||
42f52ef8 KP |
2796 | /* Called from drm generic code, passed 'crtc' which |
2797 | * we use as a pipe index | |
2798 | */ | |
88e72717 | 2799 | static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 2800 | { |
2d1013dd | 2801 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2802 | unsigned long irqflags; |
0a3e67a4 | 2803 | |
1ec14ad3 | 2804 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2805 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2806 | PIPE_VBLANK_INTERRUPT_STATUS | |
2807 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2808 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2809 | } | |
2810 | ||
88e72717 | 2811 | static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) |
f796cf8f | 2812 | { |
2d1013dd | 2813 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2814 | unsigned long irqflags; |
b518421f | 2815 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2816 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2817 | |
2818 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
fbdedaea | 2819 | ilk_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2820 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2821 | } | |
2822 | ||
88e72717 | 2823 | static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe) |
7e231dbe | 2824 | { |
2d1013dd | 2825 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2826 | unsigned long irqflags; |
7e231dbe JB |
2827 | |
2828 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2829 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2830 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2831 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2832 | } | |
2833 | ||
88e72717 | 2834 | static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) |
abd58f01 BW |
2835 | { |
2836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2837 | unsigned long irqflags; | |
abd58f01 | 2838 | |
abd58f01 | 2839 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
013d3752 | 2840 | bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
abd58f01 BW |
2841 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2842 | } | |
2843 | ||
9107e9d2 | 2844 | static bool |
0bc40be8 | 2845 | ring_idle(struct intel_engine_cs *engine, u32 seqno) |
9107e9d2 | 2846 | { |
cffa781e CW |
2847 | return i915_seqno_passed(seqno, |
2848 | READ_ONCE(engine->last_submitted_seqno)); | |
f65d9421 BG |
2849 | } |
2850 | ||
a028c4b0 | 2851 | static bool |
c033666a | 2852 | ipehr_is_semaphore_wait(struct drm_i915_private *dev_priv, u32 ipehr) |
a028c4b0 | 2853 | { |
c033666a | 2854 | if (INTEL_GEN(dev_priv) >= 8) { |
a6cdb93a | 2855 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2856 | } else { |
2857 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2858 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2859 | MI_SEMAPHORE_REGISTER); | |
2860 | } | |
2861 | } | |
2862 | ||
a4872ba6 | 2863 | static struct intel_engine_cs * |
0bc40be8 TU |
2864 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr, |
2865 | u64 offset) | |
921d42ea | 2866 | { |
c033666a | 2867 | struct drm_i915_private *dev_priv = engine->i915; |
a4872ba6 | 2868 | struct intel_engine_cs *signaller; |
921d42ea | 2869 | |
c033666a | 2870 | if (INTEL_GEN(dev_priv) >= 8) { |
b4ac5afc | 2871 | for_each_engine(signaller, dev_priv) { |
0bc40be8 | 2872 | if (engine == signaller) |
a6cdb93a RV |
2873 | continue; |
2874 | ||
0bc40be8 | 2875 | if (offset == signaller->semaphore.signal_ggtt[engine->id]) |
a6cdb93a RV |
2876 | return signaller; |
2877 | } | |
921d42ea DV |
2878 | } else { |
2879 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2880 | ||
b4ac5afc | 2881 | for_each_engine(signaller, dev_priv) { |
0bc40be8 | 2882 | if(engine == signaller) |
921d42ea DV |
2883 | continue; |
2884 | ||
0bc40be8 | 2885 | if (sync_bits == signaller->semaphore.mbox.wait[engine->id]) |
921d42ea DV |
2886 | return signaller; |
2887 | } | |
2888 | } | |
2889 | ||
a6cdb93a | 2890 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
0bc40be8 | 2891 | engine->id, ipehr, offset); |
921d42ea DV |
2892 | |
2893 | return NULL; | |
2894 | } | |
2895 | ||
a4872ba6 | 2896 | static struct intel_engine_cs * |
0bc40be8 | 2897 | semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno) |
a24a11e6 | 2898 | { |
c033666a | 2899 | struct drm_i915_private *dev_priv = engine->i915; |
88fe429d | 2900 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2901 | u64 offset = 0; |
2902 | int i, backwards; | |
a24a11e6 | 2903 | |
381e8ae3 TE |
2904 | /* |
2905 | * This function does not support execlist mode - any attempt to | |
2906 | * proceed further into this function will result in a kernel panic | |
2907 | * when dereferencing ring->buffer, which is not set up in execlist | |
2908 | * mode. | |
2909 | * | |
2910 | * The correct way of doing it would be to derive the currently | |
2911 | * executing ring buffer from the current context, which is derived | |
2912 | * from the currently running request. Unfortunately, to get the | |
2913 | * current request we would have to grab the struct_mutex before doing | |
2914 | * anything else, which would be ill-advised since some other thread | |
2915 | * might have grabbed it already and managed to hang itself, causing | |
2916 | * the hang checker to deadlock. | |
2917 | * | |
2918 | * Therefore, this function does not support execlist mode in its | |
2919 | * current form. Just return NULL and move on. | |
2920 | */ | |
0bc40be8 | 2921 | if (engine->buffer == NULL) |
381e8ae3 TE |
2922 | return NULL; |
2923 | ||
0bc40be8 | 2924 | ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); |
c033666a | 2925 | if (!ipehr_is_semaphore_wait(engine->i915, ipehr)) |
6274f212 | 2926 | return NULL; |
a24a11e6 | 2927 | |
88fe429d DV |
2928 | /* |
2929 | * HEAD is likely pointing to the dword after the actual command, | |
2930 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2931 | * or 4 dwords depending on the semaphore wait command size. |
2932 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2933 | * point at at batch, and semaphores are always emitted into the |
2934 | * ringbuffer itself. | |
a24a11e6 | 2935 | */ |
0bc40be8 | 2936 | head = I915_READ_HEAD(engine) & HEAD_ADDR; |
c033666a | 2937 | backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4; |
88fe429d | 2938 | |
a6cdb93a | 2939 | for (i = backwards; i; --i) { |
88fe429d DV |
2940 | /* |
2941 | * Be paranoid and presume the hw has gone off into the wild - | |
2942 | * our ring is smaller than what the hardware (and hence | |
2943 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2944 | */ | |
0bc40be8 | 2945 | head &= engine->buffer->size - 1; |
88fe429d DV |
2946 | |
2947 | /* This here seems to blow up */ | |
0bc40be8 | 2948 | cmd = ioread32(engine->buffer->virtual_start + head); |
a24a11e6 CW |
2949 | if (cmd == ipehr) |
2950 | break; | |
2951 | ||
88fe429d DV |
2952 | head -= 4; |
2953 | } | |
a24a11e6 | 2954 | |
88fe429d DV |
2955 | if (!i) |
2956 | return NULL; | |
a24a11e6 | 2957 | |
0bc40be8 | 2958 | *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1; |
c033666a | 2959 | if (INTEL_GEN(dev_priv) >= 8) { |
0bc40be8 | 2960 | offset = ioread32(engine->buffer->virtual_start + head + 12); |
a6cdb93a | 2961 | offset <<= 32; |
0bc40be8 | 2962 | offset = ioread32(engine->buffer->virtual_start + head + 8); |
a6cdb93a | 2963 | } |
0bc40be8 | 2964 | return semaphore_wait_to_signaller_ring(engine, ipehr, offset); |
a24a11e6 CW |
2965 | } |
2966 | ||
0bc40be8 | 2967 | static int semaphore_passed(struct intel_engine_cs *engine) |
6274f212 | 2968 | { |
c033666a | 2969 | struct drm_i915_private *dev_priv = engine->i915; |
a4872ba6 | 2970 | struct intel_engine_cs *signaller; |
a0d036b0 | 2971 | u32 seqno; |
6274f212 | 2972 | |
0bc40be8 | 2973 | engine->hangcheck.deadlock++; |
6274f212 | 2974 | |
0bc40be8 | 2975 | signaller = semaphore_waits_for(engine, &seqno); |
4be17381 CW |
2976 | if (signaller == NULL) |
2977 | return -1; | |
2978 | ||
2979 | /* Prevent pathological recursion due to driver bugs */ | |
666796da | 2980 | if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES) |
6274f212 CW |
2981 | return -1; |
2982 | ||
c04e0f3b | 2983 | if (i915_seqno_passed(signaller->get_seqno(signaller), seqno)) |
4be17381 CW |
2984 | return 1; |
2985 | ||
a0d036b0 CW |
2986 | /* cursory check for an unkickable deadlock */ |
2987 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
2988 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
2989 | return -1; |
2990 | ||
2991 | return 0; | |
6274f212 CW |
2992 | } |
2993 | ||
2994 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2995 | { | |
e2f80391 | 2996 | struct intel_engine_cs *engine; |
6274f212 | 2997 | |
b4ac5afc | 2998 | for_each_engine(engine, dev_priv) |
e2f80391 | 2999 | engine->hangcheck.deadlock = 0; |
6274f212 CW |
3000 | } |
3001 | ||
0bc40be8 | 3002 | static bool subunits_stuck(struct intel_engine_cs *engine) |
1ec14ad3 | 3003 | { |
61642ff0 MK |
3004 | u32 instdone[I915_NUM_INSTDONE_REG]; |
3005 | bool stuck; | |
3006 | int i; | |
3007 | ||
0bc40be8 | 3008 | if (engine->id != RCS) |
61642ff0 MK |
3009 | return true; |
3010 | ||
c033666a | 3011 | i915_get_extra_instdone(engine->i915, instdone); |
9107e9d2 | 3012 | |
61642ff0 MK |
3013 | /* There might be unstable subunit states even when |
3014 | * actual head is not moving. Filter out the unstable ones by | |
3015 | * accumulating the undone -> done transitions and only | |
3016 | * consider those as progress. | |
3017 | */ | |
3018 | stuck = true; | |
3019 | for (i = 0; i < I915_NUM_INSTDONE_REG; i++) { | |
0bc40be8 | 3020 | const u32 tmp = instdone[i] | engine->hangcheck.instdone[i]; |
61642ff0 | 3021 | |
0bc40be8 | 3022 | if (tmp != engine->hangcheck.instdone[i]) |
61642ff0 MK |
3023 | stuck = false; |
3024 | ||
0bc40be8 | 3025 | engine->hangcheck.instdone[i] |= tmp; |
61642ff0 MK |
3026 | } |
3027 | ||
3028 | return stuck; | |
3029 | } | |
3030 | ||
3031 | static enum intel_ring_hangcheck_action | |
0bc40be8 | 3032 | head_stuck(struct intel_engine_cs *engine, u64 acthd) |
61642ff0 | 3033 | { |
0bc40be8 | 3034 | if (acthd != engine->hangcheck.acthd) { |
61642ff0 MK |
3035 | |
3036 | /* Clear subunit states on head movement */ | |
0bc40be8 TU |
3037 | memset(engine->hangcheck.instdone, 0, |
3038 | sizeof(engine->hangcheck.instdone)); | |
61642ff0 | 3039 | |
24a65e62 | 3040 | return HANGCHECK_ACTIVE; |
f260fe7b | 3041 | } |
6274f212 | 3042 | |
0bc40be8 | 3043 | if (!subunits_stuck(engine)) |
61642ff0 MK |
3044 | return HANGCHECK_ACTIVE; |
3045 | ||
3046 | return HANGCHECK_HUNG; | |
3047 | } | |
3048 | ||
3049 | static enum intel_ring_hangcheck_action | |
0bc40be8 | 3050 | ring_stuck(struct intel_engine_cs *engine, u64 acthd) |
61642ff0 | 3051 | { |
c033666a | 3052 | struct drm_i915_private *dev_priv = engine->i915; |
61642ff0 MK |
3053 | enum intel_ring_hangcheck_action ha; |
3054 | u32 tmp; | |
3055 | ||
0bc40be8 | 3056 | ha = head_stuck(engine, acthd); |
61642ff0 MK |
3057 | if (ha != HANGCHECK_HUNG) |
3058 | return ha; | |
3059 | ||
c033666a | 3060 | if (IS_GEN2(dev_priv)) |
f2f4d82f | 3061 | return HANGCHECK_HUNG; |
9107e9d2 CW |
3062 | |
3063 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
3064 | * If so we can simply poke the RB_WAIT bit | |
3065 | * and break the hang. This should work on | |
3066 | * all but the second generation chipsets. | |
3067 | */ | |
0bc40be8 | 3068 | tmp = I915_READ_CTL(engine); |
1ec14ad3 | 3069 | if (tmp & RING_WAIT) { |
c033666a | 3070 | i915_handle_error(dev_priv, 0, |
58174462 | 3071 | "Kicking stuck wait on %s", |
0bc40be8 TU |
3072 | engine->name); |
3073 | I915_WRITE_CTL(engine, tmp); | |
f2f4d82f | 3074 | return HANGCHECK_KICK; |
6274f212 CW |
3075 | } |
3076 | ||
c033666a | 3077 | if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) { |
0bc40be8 | 3078 | switch (semaphore_passed(engine)) { |
6274f212 | 3079 | default: |
f2f4d82f | 3080 | return HANGCHECK_HUNG; |
6274f212 | 3081 | case 1: |
c033666a | 3082 | i915_handle_error(dev_priv, 0, |
58174462 | 3083 | "Kicking stuck semaphore on %s", |
0bc40be8 TU |
3084 | engine->name); |
3085 | I915_WRITE_CTL(engine, tmp); | |
f2f4d82f | 3086 | return HANGCHECK_KICK; |
6274f212 | 3087 | case 0: |
f2f4d82f | 3088 | return HANGCHECK_WAIT; |
6274f212 | 3089 | } |
9107e9d2 | 3090 | } |
ed5cbb03 | 3091 | |
f2f4d82f | 3092 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
3093 | } |
3094 | ||
12471ba8 CW |
3095 | static unsigned kick_waiters(struct intel_engine_cs *engine) |
3096 | { | |
c033666a | 3097 | struct drm_i915_private *i915 = engine->i915; |
12471ba8 CW |
3098 | unsigned user_interrupts = READ_ONCE(engine->user_interrupts); |
3099 | ||
3100 | if (engine->hangcheck.user_interrupts == user_interrupts && | |
3101 | !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) { | |
3102 | if (!(i915->gpu_error.test_irq_rings & intel_engine_flag(engine))) | |
3103 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
3104 | engine->name); | |
3105 | else | |
3106 | DRM_INFO("Fake missed irq on %s\n", | |
3107 | engine->name); | |
3108 | wake_up_all(&engine->irq_queue); | |
3109 | } | |
3110 | ||
3111 | return user_interrupts; | |
3112 | } | |
737b1506 | 3113 | /* |
f65d9421 | 3114 | * This is called when the chip hasn't reported back with completed |
05407ff8 MK |
3115 | * batchbuffers in a long time. We keep track per ring seqno progress and |
3116 | * if there are no progress, hangcheck score for that ring is increased. | |
3117 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
3118 | * we kick the ring. If we see no progress on three subsequent calls | |
3119 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 3120 | */ |
737b1506 | 3121 | static void i915_hangcheck_elapsed(struct work_struct *work) |
f65d9421 | 3122 | { |
737b1506 CW |
3123 | struct drm_i915_private *dev_priv = |
3124 | container_of(work, typeof(*dev_priv), | |
3125 | gpu_error.hangcheck_work.work); | |
e2f80391 | 3126 | struct intel_engine_cs *engine; |
c3232b18 | 3127 | enum intel_engine_id id; |
05407ff8 | 3128 | int busy_count = 0, rings_hung = 0; |
666796da | 3129 | bool stuck[I915_NUM_ENGINES] = { 0 }; |
9107e9d2 CW |
3130 | #define BUSY 1 |
3131 | #define KICK 5 | |
3132 | #define HUNG 20 | |
24a65e62 | 3133 | #define ACTIVE_DECAY 15 |
893eead0 | 3134 | |
d330a953 | 3135 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
3136 | return; |
3137 | ||
1f814dac ID |
3138 | /* |
3139 | * The hangcheck work is synced during runtime suspend, we don't | |
3140 | * require a wakeref. TODO: instead of disabling the asserts make | |
3141 | * sure that we hold a reference when this work is running. | |
3142 | */ | |
3143 | DISABLE_RPM_WAKEREF_ASSERTS(dev_priv); | |
3144 | ||
75714940 MK |
3145 | /* As enabling the GPU requires fairly extensive mmio access, |
3146 | * periodically arm the mmio checker to see if we are triggering | |
3147 | * any invalid access. | |
3148 | */ | |
3149 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
3150 | ||
c3232b18 | 3151 | for_each_engine_id(engine, dev_priv, id) { |
50877445 CW |
3152 | u64 acthd; |
3153 | u32 seqno; | |
12471ba8 | 3154 | unsigned user_interrupts; |
9107e9d2 | 3155 | bool busy = true; |
05407ff8 | 3156 | |
6274f212 CW |
3157 | semaphore_clear_deadlocks(dev_priv); |
3158 | ||
c04e0f3b CW |
3159 | /* We don't strictly need an irq-barrier here, as we are not |
3160 | * serving an interrupt request, be paranoid in case the | |
3161 | * barrier has side-effects (such as preventing a broken | |
3162 | * cacheline snoop) and so be sure that we can see the seqno | |
3163 | * advance. If the seqno should stick, due to a stale | |
3164 | * cacheline, we would erroneously declare the GPU hung. | |
3165 | */ | |
3166 | if (engine->irq_seqno_barrier) | |
3167 | engine->irq_seqno_barrier(engine); | |
3168 | ||
e2f80391 | 3169 | acthd = intel_ring_get_active_head(engine); |
c04e0f3b | 3170 | seqno = engine->get_seqno(engine); |
b4519513 | 3171 | |
12471ba8 CW |
3172 | /* Reset stuck interrupts between batch advances */ |
3173 | user_interrupts = 0; | |
3174 | ||
e2f80391 TU |
3175 | if (engine->hangcheck.seqno == seqno) { |
3176 | if (ring_idle(engine, seqno)) { | |
3177 | engine->hangcheck.action = HANGCHECK_IDLE; | |
e2f80391 | 3178 | if (waitqueue_active(&engine->irq_queue)) { |
094f9a54 | 3179 | /* Safeguard against driver failure */ |
12471ba8 | 3180 | user_interrupts = kick_waiters(engine); |
e2f80391 | 3181 | engine->hangcheck.score += BUSY; |
9107e9d2 CW |
3182 | } else |
3183 | busy = false; | |
05407ff8 | 3184 | } else { |
6274f212 CW |
3185 | /* We always increment the hangcheck score |
3186 | * if the ring is busy and still processing | |
3187 | * the same request, so that no single request | |
3188 | * can run indefinitely (such as a chain of | |
3189 | * batches). The only time we do not increment | |
3190 | * the hangcheck score on this ring, if this | |
3191 | * ring is in a legitimate wait for another | |
3192 | * ring. In that case the waiting ring is a | |
3193 | * victim and we want to be sure we catch the | |
3194 | * right culprit. Then every time we do kick | |
3195 | * the ring, add a small increment to the | |
3196 | * score so that we can catch a batch that is | |
3197 | * being repeatedly kicked and so responsible | |
3198 | * for stalling the machine. | |
3199 | */ | |
e2f80391 TU |
3200 | engine->hangcheck.action = ring_stuck(engine, |
3201 | acthd); | |
ad8beaea | 3202 | |
e2f80391 | 3203 | switch (engine->hangcheck.action) { |
da661464 | 3204 | case HANGCHECK_IDLE: |
f2f4d82f | 3205 | case HANGCHECK_WAIT: |
f260fe7b | 3206 | break; |
24a65e62 | 3207 | case HANGCHECK_ACTIVE: |
e2f80391 | 3208 | engine->hangcheck.score += BUSY; |
6274f212 | 3209 | break; |
f2f4d82f | 3210 | case HANGCHECK_KICK: |
e2f80391 | 3211 | engine->hangcheck.score += KICK; |
6274f212 | 3212 | break; |
f2f4d82f | 3213 | case HANGCHECK_HUNG: |
e2f80391 | 3214 | engine->hangcheck.score += HUNG; |
c3232b18 | 3215 | stuck[id] = true; |
6274f212 CW |
3216 | break; |
3217 | } | |
05407ff8 | 3218 | } |
9107e9d2 | 3219 | } else { |
e2f80391 | 3220 | engine->hangcheck.action = HANGCHECK_ACTIVE; |
da661464 | 3221 | |
9107e9d2 CW |
3222 | /* Gradually reduce the count so that we catch DoS |
3223 | * attempts across multiple batches. | |
3224 | */ | |
e2f80391 TU |
3225 | if (engine->hangcheck.score > 0) |
3226 | engine->hangcheck.score -= ACTIVE_DECAY; | |
3227 | if (engine->hangcheck.score < 0) | |
3228 | engine->hangcheck.score = 0; | |
f260fe7b | 3229 | |
61642ff0 | 3230 | /* Clear head and subunit states on seqno movement */ |
12471ba8 | 3231 | acthd = 0; |
61642ff0 | 3232 | |
e2f80391 TU |
3233 | memset(engine->hangcheck.instdone, 0, |
3234 | sizeof(engine->hangcheck.instdone)); | |
d1e61e7f CW |
3235 | } |
3236 | ||
e2f80391 TU |
3237 | engine->hangcheck.seqno = seqno; |
3238 | engine->hangcheck.acthd = acthd; | |
12471ba8 | 3239 | engine->hangcheck.user_interrupts = user_interrupts; |
9107e9d2 | 3240 | busy_count += busy; |
893eead0 | 3241 | } |
b9201c14 | 3242 | |
c3232b18 | 3243 | for_each_engine_id(engine, dev_priv, id) { |
e2f80391 | 3244 | if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d | 3245 | DRM_INFO("%s on %s\n", |
c3232b18 | 3246 | stuck[id] ? "stuck" : "no progress", |
e2f80391 | 3247 | engine->name); |
14b730fc | 3248 | rings_hung |= intel_engine_flag(engine); |
92cab734 MK |
3249 | } |
3250 | } | |
3251 | ||
1f814dac | 3252 | if (rings_hung) { |
c033666a | 3253 | i915_handle_error(dev_priv, rings_hung, "Engine(s) hung"); |
1f814dac ID |
3254 | goto out; |
3255 | } | |
f65d9421 | 3256 | |
05407ff8 MK |
3257 | if (busy_count) |
3258 | /* Reset timer case chip hangs without another request | |
3259 | * being added */ | |
c033666a | 3260 | i915_queue_hangcheck(dev_priv); |
1f814dac ID |
3261 | |
3262 | out: | |
3263 | ENABLE_RPM_WAKEREF_ASSERTS(dev_priv); | |
10cd45b6 MK |
3264 | } |
3265 | ||
c033666a | 3266 | void i915_queue_hangcheck(struct drm_i915_private *dev_priv) |
10cd45b6 | 3267 | { |
c033666a | 3268 | struct i915_gpu_error *e = &dev_priv->gpu_error; |
672e7b7c | 3269 | |
d330a953 | 3270 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
3271 | return; |
3272 | ||
737b1506 CW |
3273 | /* Don't continually defer the hangcheck so that it is always run at |
3274 | * least once after work has been scheduled on any ring. Otherwise, | |
3275 | * we will ignore a hung ring if a second ring is kept busy. | |
3276 | */ | |
3277 | ||
3278 | queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work, | |
3279 | round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
3280 | } |
3281 | ||
1c69eb42 | 3282 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
3283 | { |
3284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3285 | ||
3286 | if (HAS_PCH_NOP(dev)) | |
3287 | return; | |
3288 | ||
f86f3fb0 | 3289 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3290 | |
3291 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3292 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3293 | } |
105b122e | 3294 | |
622364b6 PZ |
3295 | /* |
3296 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3297 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3298 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3299 | * only unmask them as needed with SDEIMR. | |
3300 | * | |
3301 | * This function needs to be called before interrupts are enabled. | |
3302 | */ | |
3303 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3304 | { | |
3305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3306 | ||
3307 | if (HAS_PCH_NOP(dev)) | |
3308 | return; | |
3309 | ||
3310 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3311 | I915_WRITE(SDEIER, 0xffffffff); |
3312 | POSTING_READ(SDEIER); | |
3313 | } | |
3314 | ||
7c4d664e | 3315 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3316 | { |
3317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3318 | ||
f86f3fb0 | 3319 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3320 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3321 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3322 | } |
3323 | ||
70591a41 VS |
3324 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
3325 | { | |
3326 | enum pipe pipe; | |
3327 | ||
71b8b41d VS |
3328 | if (IS_CHERRYVIEW(dev_priv)) |
3329 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); | |
3330 | else | |
3331 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3332 | ||
ad22d106 | 3333 | i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); |
70591a41 VS |
3334 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
3335 | ||
ad22d106 VS |
3336 | for_each_pipe(dev_priv, pipe) { |
3337 | I915_WRITE(PIPESTAT(pipe), | |
3338 | PIPE_FIFO_UNDERRUN_STATUS | | |
3339 | PIPESTAT_INT_STATUS_MASK); | |
3340 | dev_priv->pipestat_irq_mask[pipe] = 0; | |
3341 | } | |
70591a41 VS |
3342 | |
3343 | GEN5_IRQ_RESET(VLV_); | |
ad22d106 | 3344 | dev_priv->irq_mask = ~0; |
70591a41 VS |
3345 | } |
3346 | ||
8bb61306 VS |
3347 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
3348 | { | |
3349 | u32 pipestat_mask; | |
9ab981f2 | 3350 | u32 enable_mask; |
8bb61306 VS |
3351 | enum pipe pipe; |
3352 | ||
8bb61306 VS |
3353 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | |
3354 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3355 | ||
3356 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); | |
3357 | for_each_pipe(dev_priv, pipe) | |
3358 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
3359 | ||
9ab981f2 VS |
3360 | enable_mask = I915_DISPLAY_PORT_INTERRUPT | |
3361 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3362 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
8bb61306 | 3363 | if (IS_CHERRYVIEW(dev_priv)) |
9ab981f2 | 3364 | enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
6b7eafc1 VS |
3365 | |
3366 | WARN_ON(dev_priv->irq_mask != ~0); | |
3367 | ||
9ab981f2 VS |
3368 | dev_priv->irq_mask = ~enable_mask; |
3369 | ||
3370 | GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask); | |
8bb61306 VS |
3371 | } |
3372 | ||
3373 | /* drm_dma.h hooks | |
3374 | */ | |
3375 | static void ironlake_irq_reset(struct drm_device *dev) | |
3376 | { | |
3377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3378 | ||
3379 | I915_WRITE(HWSTAM, 0xffffffff); | |
3380 | ||
3381 | GEN5_IRQ_RESET(DE); | |
3382 | if (IS_GEN7(dev)) | |
3383 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
3384 | ||
3385 | gen5_gt_irq_reset(dev); | |
3386 | ||
3387 | ibx_irq_reset(dev); | |
3388 | } | |
3389 | ||
7e231dbe JB |
3390 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3391 | { | |
2d1013dd | 3392 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3393 | |
34c7b8a7 VS |
3394 | I915_WRITE(VLV_MASTER_IER, 0); |
3395 | POSTING_READ(VLV_MASTER_IER); | |
3396 | ||
7c4d664e | 3397 | gen5_gt_irq_reset(dev); |
7e231dbe | 3398 | |
ad22d106 | 3399 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3400 | if (dev_priv->display_irqs_enabled) |
3401 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3402 | spin_unlock_irq(&dev_priv->irq_lock); |
7e231dbe JB |
3403 | } |
3404 | ||
d6e3cca3 DV |
3405 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3406 | { | |
3407 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3408 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3409 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3410 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3411 | } | |
3412 | ||
823f6b38 | 3413 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3414 | { |
3415 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3416 | int pipe; | |
3417 | ||
abd58f01 BW |
3418 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3419 | POSTING_READ(GEN8_MASTER_IRQ); | |
3420 | ||
d6e3cca3 | 3421 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3422 | |
055e393f | 3423 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3424 | if (intel_display_power_is_enabled(dev_priv, |
3425 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3426 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3427 | |
f86f3fb0 PZ |
3428 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3429 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3430 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3431 | |
266ea3d9 SS |
3432 | if (HAS_PCH_SPLIT(dev)) |
3433 | ibx_irq_reset(dev); | |
abd58f01 | 3434 | } |
09f2344d | 3435 | |
4c6c03be DL |
3436 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
3437 | unsigned int pipe_mask) | |
d49bdb0e | 3438 | { |
1180e206 | 3439 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
6831f3e3 | 3440 | enum pipe pipe; |
d49bdb0e | 3441 | |
13321786 | 3442 | spin_lock_irq(&dev_priv->irq_lock); |
6831f3e3 VS |
3443 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
3444 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3445 | dev_priv->de_irq_mask[pipe], | |
3446 | ~dev_priv->de_irq_mask[pipe] | extra_ier); | |
13321786 | 3447 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3448 | } |
3449 | ||
aae8ba84 VS |
3450 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
3451 | unsigned int pipe_mask) | |
3452 | { | |
6831f3e3 VS |
3453 | enum pipe pipe; |
3454 | ||
aae8ba84 | 3455 | spin_lock_irq(&dev_priv->irq_lock); |
6831f3e3 VS |
3456 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
3457 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); | |
aae8ba84 VS |
3458 | spin_unlock_irq(&dev_priv->irq_lock); |
3459 | ||
3460 | /* make sure we're done processing display irqs */ | |
3461 | synchronize_irq(dev_priv->dev->irq); | |
3462 | } | |
3463 | ||
43f328d7 VS |
3464 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3465 | { | |
3466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3467 | |
3468 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3469 | POSTING_READ(GEN8_MASTER_IRQ); | |
3470 | ||
d6e3cca3 | 3471 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3472 | |
3473 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3474 | ||
ad22d106 | 3475 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3476 | if (dev_priv->display_irqs_enabled) |
3477 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3478 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3479 | } |
3480 | ||
91d14251 | 3481 | static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, |
87a02106 VS |
3482 | const u32 hpd[HPD_NUM_PINS]) |
3483 | { | |
87a02106 VS |
3484 | struct intel_encoder *encoder; |
3485 | u32 enabled_irqs = 0; | |
3486 | ||
91d14251 | 3487 | for_each_intel_encoder(dev_priv->dev, encoder) |
87a02106 VS |
3488 | if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) |
3489 | enabled_irqs |= hpd[encoder->hpd_pin]; | |
3490 | ||
3491 | return enabled_irqs; | |
3492 | } | |
3493 | ||
91d14251 | 3494 | static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) |
7fe0b973 | 3495 | { |
87a02106 | 3496 | u32 hotplug_irqs, hotplug, enabled_irqs; |
82a28bcf | 3497 | |
91d14251 | 3498 | if (HAS_PCH_IBX(dev_priv)) { |
fee884ed | 3499 | hotplug_irqs = SDE_HOTPLUG_MASK; |
91d14251 | 3500 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx); |
82a28bcf | 3501 | } else { |
fee884ed | 3502 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
91d14251 | 3503 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt); |
82a28bcf | 3504 | } |
7fe0b973 | 3505 | |
fee884ed | 3506 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3507 | |
3508 | /* | |
3509 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
6dbf30ce VS |
3510 | * duration to 2ms (which is the minimum in the Display Port spec). |
3511 | * The pulse duration bits are reserved on LPT+. | |
82a28bcf | 3512 | */ |
7fe0b973 KP |
3513 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3514 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3515 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3516 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3517 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
0b2eb33e VS |
3518 | /* |
3519 | * When CPU and PCH are on the same package, port A | |
3520 | * HPD must be enabled in both north and south. | |
3521 | */ | |
91d14251 | 3522 | if (HAS_PCH_LPT_LP(dev_priv)) |
0b2eb33e | 3523 | hotplug |= PORTA_HOTPLUG_ENABLE; |
7fe0b973 | 3524 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
6dbf30ce | 3525 | } |
26951caf | 3526 | |
91d14251 | 3527 | static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) |
6dbf30ce | 3528 | { |
6dbf30ce VS |
3529 | u32 hotplug_irqs, hotplug, enabled_irqs; |
3530 | ||
3531 | hotplug_irqs = SDE_HOTPLUG_MASK_SPT; | |
91d14251 | 3532 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt); |
6dbf30ce VS |
3533 | |
3534 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); | |
3535 | ||
3536 | /* Enable digital hotplug on the PCH */ | |
3537 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
3538 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE | | |
74c0b395 | 3539 | PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE; |
6dbf30ce VS |
3540 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
3541 | ||
3542 | hotplug = I915_READ(PCH_PORT_HOTPLUG2); | |
3543 | hotplug |= PORTE_HOTPLUG_ENABLE; | |
3544 | I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); | |
7fe0b973 KP |
3545 | } |
3546 | ||
91d14251 | 3547 | static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) |
e4ce95aa | 3548 | { |
e4ce95aa VS |
3549 | u32 hotplug_irqs, hotplug, enabled_irqs; |
3550 | ||
91d14251 | 3551 | if (INTEL_GEN(dev_priv) >= 8) { |
3a3b3c7d | 3552 | hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; |
91d14251 | 3553 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw); |
3a3b3c7d VS |
3554 | |
3555 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
91d14251 | 3556 | } else if (INTEL_GEN(dev_priv) >= 7) { |
23bb4cb5 | 3557 | hotplug_irqs = DE_DP_A_HOTPLUG_IVB; |
91d14251 | 3558 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb); |
3a3b3c7d VS |
3559 | |
3560 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
23bb4cb5 VS |
3561 | } else { |
3562 | hotplug_irqs = DE_DP_A_HOTPLUG; | |
91d14251 | 3563 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk); |
e4ce95aa | 3564 | |
3a3b3c7d VS |
3565 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); |
3566 | } | |
e4ce95aa VS |
3567 | |
3568 | /* | |
3569 | * Enable digital hotplug on the CPU, and configure the DP short pulse | |
3570 | * duration to 2ms (which is the minimum in the Display Port spec) | |
23bb4cb5 | 3571 | * The pulse duration bits are reserved on HSW+. |
e4ce95aa VS |
3572 | */ |
3573 | hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
3574 | hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK; | |
3575 | hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms; | |
3576 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); | |
3577 | ||
91d14251 | 3578 | ibx_hpd_irq_setup(dev_priv); |
e4ce95aa VS |
3579 | } |
3580 | ||
91d14251 | 3581 | static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) |
e0a20ad7 | 3582 | { |
a52bb15b | 3583 | u32 hotplug_irqs, hotplug, enabled_irqs; |
e0a20ad7 | 3584 | |
91d14251 | 3585 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt); |
a52bb15b | 3586 | hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; |
e0a20ad7 | 3587 | |
a52bb15b | 3588 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); |
e0a20ad7 | 3589 | |
a52bb15b VS |
3590 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3591 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE | | |
3592 | PORTA_HOTPLUG_ENABLE; | |
d252bf68 SS |
3593 | |
3594 | DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n", | |
3595 | hotplug, enabled_irqs); | |
3596 | hotplug &= ~BXT_DDI_HPD_INVERT_MASK; | |
3597 | ||
3598 | /* | |
3599 | * For BXT invert bit has to be set based on AOB design | |
3600 | * for HPD detection logic, update it based on VBT fields. | |
3601 | */ | |
3602 | ||
3603 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) && | |
3604 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) | |
3605 | hotplug |= BXT_DDIA_HPD_INVERT; | |
3606 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) && | |
3607 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) | |
3608 | hotplug |= BXT_DDIB_HPD_INVERT; | |
3609 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) && | |
3610 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) | |
3611 | hotplug |= BXT_DDIC_HPD_INVERT; | |
3612 | ||
a52bb15b | 3613 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
e0a20ad7 SS |
3614 | } |
3615 | ||
d46da437 PZ |
3616 | static void ibx_irq_postinstall(struct drm_device *dev) |
3617 | { | |
2d1013dd | 3618 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3619 | u32 mask; |
e5868a31 | 3620 | |
692a04cf DV |
3621 | if (HAS_PCH_NOP(dev)) |
3622 | return; | |
3623 | ||
105b122e | 3624 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3625 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3626 | else |
5c673b60 | 3627 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3628 | |
b51a2842 | 3629 | gen5_assert_iir_is_zero(dev_priv, SDEIIR); |
d46da437 | 3630 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3631 | } |
3632 | ||
0a9a8c91 DV |
3633 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3634 | { | |
3635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3636 | u32 pm_irqs, gt_irqs; | |
3637 | ||
3638 | pm_irqs = gt_irqs = 0; | |
3639 | ||
3640 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3641 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3642 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3643 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3644 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3645 | } |
3646 | ||
3647 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3648 | if (IS_GEN5(dev)) { | |
3649 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3650 | ILK_BSD_USER_INTERRUPT; | |
3651 | } else { | |
3652 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3653 | } | |
3654 | ||
35079899 | 3655 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3656 | |
3657 | if (INTEL_INFO(dev)->gen >= 6) { | |
78e68d36 ID |
3658 | /* |
3659 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3660 | * itself is enabled/disabled. | |
3661 | */ | |
0a9a8c91 DV |
3662 | if (HAS_VEBOX(dev)) |
3663 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3664 | ||
605cd25b | 3665 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3666 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3667 | } |
3668 | } | |
3669 | ||
f71d4af4 | 3670 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3671 | { |
2d1013dd | 3672 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3673 | u32 display_mask, extra_mask; |
3674 | ||
3675 | if (INTEL_INFO(dev)->gen >= 7) { | |
3676 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3677 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3678 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3679 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3680 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
23bb4cb5 VS |
3681 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | |
3682 | DE_DP_A_HOTPLUG_IVB); | |
8e76f8dc PZ |
3683 | } else { |
3684 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3685 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3686 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3687 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3688 | DE_POISON); | |
e4ce95aa VS |
3689 | extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3690 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | | |
3691 | DE_DP_A_HOTPLUG); | |
8e76f8dc | 3692 | } |
036a4a7d | 3693 | |
1ec14ad3 | 3694 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3695 | |
0c841212 PZ |
3696 | I915_WRITE(HWSTAM, 0xeffe); |
3697 | ||
622364b6 PZ |
3698 | ibx_irq_pre_postinstall(dev); |
3699 | ||
35079899 | 3700 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3701 | |
0a9a8c91 | 3702 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3703 | |
d46da437 | 3704 | ibx_irq_postinstall(dev); |
7fe0b973 | 3705 | |
f97108d1 | 3706 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3707 | /* Enable PCU event interrupts |
3708 | * | |
3709 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3710 | * setup is guaranteed to run in single-threaded context. But we |
3711 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3712 | spin_lock_irq(&dev_priv->irq_lock); |
fbdedaea | 3713 | ilk_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3714 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3715 | } |
3716 | ||
036a4a7d ZW |
3717 | return 0; |
3718 | } | |
3719 | ||
f8b79e58 ID |
3720 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) |
3721 | { | |
3722 | assert_spin_locked(&dev_priv->irq_lock); | |
3723 | ||
3724 | if (dev_priv->display_irqs_enabled) | |
3725 | return; | |
3726 | ||
3727 | dev_priv->display_irqs_enabled = true; | |
3728 | ||
d6c69803 VS |
3729 | if (intel_irqs_enabled(dev_priv)) { |
3730 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3731 | vlv_display_irq_postinstall(dev_priv); |
d6c69803 | 3732 | } |
f8b79e58 ID |
3733 | } |
3734 | ||
3735 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3736 | { | |
3737 | assert_spin_locked(&dev_priv->irq_lock); | |
3738 | ||
3739 | if (!dev_priv->display_irqs_enabled) | |
3740 | return; | |
3741 | ||
3742 | dev_priv->display_irqs_enabled = false; | |
3743 | ||
950eabaf | 3744 | if (intel_irqs_enabled(dev_priv)) |
ad22d106 | 3745 | vlv_display_irq_reset(dev_priv); |
f8b79e58 ID |
3746 | } |
3747 | ||
0e6c9a9e VS |
3748 | |
3749 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3750 | { | |
3751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3752 | ||
0a9a8c91 | 3753 | gen5_gt_irq_postinstall(dev); |
7e231dbe | 3754 | |
ad22d106 | 3755 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3756 | if (dev_priv->display_irqs_enabled) |
3757 | vlv_display_irq_postinstall(dev_priv); | |
ad22d106 VS |
3758 | spin_unlock_irq(&dev_priv->irq_lock); |
3759 | ||
7e231dbe | 3760 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
34c7b8a7 | 3761 | POSTING_READ(VLV_MASTER_IER); |
20afbda2 DV |
3762 | |
3763 | return 0; | |
3764 | } | |
3765 | ||
abd58f01 BW |
3766 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3767 | { | |
abd58f01 BW |
3768 | /* These are interrupts we'll toggle with the ring mask register */ |
3769 | uint32_t gt_interrupts[] = { | |
3770 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3771 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
73d477f6 OM |
3772 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3773 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3774 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3775 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3776 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3777 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3778 | 0, |
73d477f6 OM |
3779 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3780 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3781 | }; |
3782 | ||
98735739 TU |
3783 | if (HAS_L3_DPF(dev_priv)) |
3784 | gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
3785 | ||
0961021a | 3786 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3787 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3788 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3789 | /* |
3790 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
3791 | * is enabled/disabled. | |
3792 | */ | |
3793 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0); | |
9a2d2d87 | 3794 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3795 | } |
3796 | ||
3797 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3798 | { | |
770de83d DL |
3799 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3800 | uint32_t de_pipe_enables; | |
3a3b3c7d VS |
3801 | u32 de_port_masked = GEN8_AUX_CHANNEL_A; |
3802 | u32 de_port_enables; | |
3803 | enum pipe pipe; | |
770de83d | 3804 | |
b4834a50 | 3805 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
770de83d DL |
3806 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3807 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d VS |
3808 | de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3809 | GEN9_AUX_CHANNEL_D; | |
9e63743e | 3810 | if (IS_BROXTON(dev_priv)) |
3a3b3c7d VS |
3811 | de_port_masked |= BXT_DE_PORT_GMBUS; |
3812 | } else { | |
770de83d DL |
3813 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3814 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d | 3815 | } |
770de83d DL |
3816 | |
3817 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3818 | GEN8_PIPE_FIFO_UNDERRUN; | |
3819 | ||
3a3b3c7d | 3820 | de_port_enables = de_port_masked; |
a52bb15b VS |
3821 | if (IS_BROXTON(dev_priv)) |
3822 | de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; | |
3823 | else if (IS_BROADWELL(dev_priv)) | |
3a3b3c7d VS |
3824 | de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; |
3825 | ||
13b3a0a7 DV |
3826 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3827 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3828 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3829 | |
055e393f | 3830 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3831 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3832 | POWER_DOMAIN_PIPE(pipe))) |
3833 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3834 | dev_priv->de_irq_mask[pipe], | |
3835 | de_pipe_enables); | |
abd58f01 | 3836 | |
3a3b3c7d | 3837 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); |
abd58f01 BW |
3838 | } |
3839 | ||
3840 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3841 | { | |
3842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3843 | ||
266ea3d9 SS |
3844 | if (HAS_PCH_SPLIT(dev)) |
3845 | ibx_irq_pre_postinstall(dev); | |
622364b6 | 3846 | |
abd58f01 BW |
3847 | gen8_gt_irq_postinstall(dev_priv); |
3848 | gen8_de_irq_postinstall(dev_priv); | |
3849 | ||
266ea3d9 SS |
3850 | if (HAS_PCH_SPLIT(dev)) |
3851 | ibx_irq_postinstall(dev); | |
abd58f01 | 3852 | |
e5328c43 | 3853 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
abd58f01 BW |
3854 | POSTING_READ(GEN8_MASTER_IRQ); |
3855 | ||
3856 | return 0; | |
3857 | } | |
3858 | ||
43f328d7 VS |
3859 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3860 | { | |
3861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 | 3862 | |
43f328d7 VS |
3863 | gen8_gt_irq_postinstall(dev_priv); |
3864 | ||
ad22d106 | 3865 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3866 | if (dev_priv->display_irqs_enabled) |
3867 | vlv_display_irq_postinstall(dev_priv); | |
ad22d106 VS |
3868 | spin_unlock_irq(&dev_priv->irq_lock); |
3869 | ||
e5328c43 | 3870 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
43f328d7 VS |
3871 | POSTING_READ(GEN8_MASTER_IRQ); |
3872 | ||
3873 | return 0; | |
3874 | } | |
3875 | ||
abd58f01 BW |
3876 | static void gen8_irq_uninstall(struct drm_device *dev) |
3877 | { | |
3878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3879 | |
3880 | if (!dev_priv) | |
3881 | return; | |
3882 | ||
823f6b38 | 3883 | gen8_irq_reset(dev); |
abd58f01 BW |
3884 | } |
3885 | ||
7e231dbe JB |
3886 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3887 | { | |
2d1013dd | 3888 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3889 | |
3890 | if (!dev_priv) | |
3891 | return; | |
3892 | ||
843d0e7d | 3893 | I915_WRITE(VLV_MASTER_IER, 0); |
34c7b8a7 | 3894 | POSTING_READ(VLV_MASTER_IER); |
843d0e7d | 3895 | |
893fce8e VS |
3896 | gen5_gt_irq_reset(dev); |
3897 | ||
7e231dbe | 3898 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3899 | |
ad22d106 | 3900 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3901 | if (dev_priv->display_irqs_enabled) |
3902 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3903 | spin_unlock_irq(&dev_priv->irq_lock); |
7e231dbe JB |
3904 | } |
3905 | ||
43f328d7 VS |
3906 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3907 | { | |
3908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3909 | |
3910 | if (!dev_priv) | |
3911 | return; | |
3912 | ||
3913 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3914 | POSTING_READ(GEN8_MASTER_IRQ); | |
3915 | ||
a2c30fba | 3916 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3917 | |
a2c30fba | 3918 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3919 | |
ad22d106 | 3920 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3921 | if (dev_priv->display_irqs_enabled) |
3922 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3923 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3924 | } |
3925 | ||
f71d4af4 | 3926 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3927 | { |
2d1013dd | 3928 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3929 | |
3930 | if (!dev_priv) | |
3931 | return; | |
3932 | ||
be30b29f | 3933 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3934 | } |
3935 | ||
a266c7d5 | 3936 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3937 | { |
2d1013dd | 3938 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3939 | int pipe; |
91e3738e | 3940 | |
055e393f | 3941 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3942 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3943 | I915_WRITE16(IMR, 0xffff); |
3944 | I915_WRITE16(IER, 0x0); | |
3945 | POSTING_READ16(IER); | |
c2798b19 CW |
3946 | } |
3947 | ||
3948 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3949 | { | |
2d1013dd | 3950 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3951 | |
c2798b19 CW |
3952 | I915_WRITE16(EMR, |
3953 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3954 | ||
3955 | /* Unmask the interrupts that we always want on. */ | |
3956 | dev_priv->irq_mask = | |
3957 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3958 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3959 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3960 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
c2798b19 CW |
3961 | I915_WRITE16(IMR, dev_priv->irq_mask); |
3962 | ||
3963 | I915_WRITE16(IER, | |
3964 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3965 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
c2798b19 CW |
3966 | I915_USER_INTERRUPT); |
3967 | POSTING_READ16(IER); | |
3968 | ||
379ef82d DV |
3969 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3970 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3971 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3972 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3973 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3974 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3975 | |
c2798b19 CW |
3976 | return 0; |
3977 | } | |
3978 | ||
90a72f87 VS |
3979 | /* |
3980 | * Returns true when a page flip has completed. | |
3981 | */ | |
91d14251 | 3982 | static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv, |
1f1c2e24 | 3983 | int plane, int pipe, u32 iir) |
90a72f87 | 3984 | { |
1f1c2e24 | 3985 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3986 | |
91d14251 | 3987 | if (!intel_pipe_handle_vblank(dev_priv, pipe)) |
90a72f87 VS |
3988 | return false; |
3989 | ||
3990 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3991 | goto check_page_flip; |
90a72f87 | 3992 | |
90a72f87 VS |
3993 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3994 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3995 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3996 | * the flip is completed (no longer pending). Since this doesn't raise | |
3997 | * an interrupt per se, we watch for the change at vblank. | |
3998 | */ | |
3999 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 4000 | goto check_page_flip; |
90a72f87 | 4001 | |
91d14251 TU |
4002 | intel_prepare_page_flip(dev_priv, plane); |
4003 | intel_finish_page_flip(dev_priv, pipe); | |
90a72f87 | 4004 | return true; |
d6bbafa1 CW |
4005 | |
4006 | check_page_flip: | |
91d14251 | 4007 | intel_check_page_flip(dev_priv, pipe); |
d6bbafa1 | 4008 | return false; |
90a72f87 VS |
4009 | } |
4010 | ||
ff1f525e | 4011 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 4012 | { |
45a83f84 | 4013 | struct drm_device *dev = arg; |
2d1013dd | 4014 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
4015 | u16 iir, new_iir; |
4016 | u32 pipe_stats[2]; | |
c2798b19 CW |
4017 | int pipe; |
4018 | u16 flip_mask = | |
4019 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4020 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
1f814dac | 4021 | irqreturn_t ret; |
c2798b19 | 4022 | |
2dd2a883 ID |
4023 | if (!intel_irqs_enabled(dev_priv)) |
4024 | return IRQ_NONE; | |
4025 | ||
1f814dac ID |
4026 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
4027 | disable_rpm_wakeref_asserts(dev_priv); | |
4028 | ||
4029 | ret = IRQ_NONE; | |
c2798b19 CW |
4030 | iir = I915_READ16(IIR); |
4031 | if (iir == 0) | |
1f814dac | 4032 | goto out; |
c2798b19 CW |
4033 | |
4034 | while (iir & ~flip_mask) { | |
4035 | /* Can't rely on pipestat interrupt bit in iir as it might | |
4036 | * have been cleared after the pipestat interrupt was received. | |
4037 | * It doesn't set the bit in iir again, but it still produces | |
4038 | * interrupts (for non-MSI). | |
4039 | */ | |
222c7f51 | 4040 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 4041 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4042 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 4043 | |
055e393f | 4044 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 4045 | i915_reg_t reg = PIPESTAT(pipe); |
c2798b19 CW |
4046 | pipe_stats[pipe] = I915_READ(reg); |
4047 | ||
4048 | /* | |
4049 | * Clear the PIPE*STAT regs before the IIR | |
4050 | */ | |
2d9d2b0b | 4051 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 4052 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 4053 | } |
222c7f51 | 4054 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
4055 | |
4056 | I915_WRITE16(IIR, iir & ~flip_mask); | |
4057 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
4058 | ||
c2798b19 | 4059 | if (iir & I915_USER_INTERRUPT) |
4a570db5 | 4060 | notify_ring(&dev_priv->engine[RCS]); |
c2798b19 | 4061 | |
055e393f | 4062 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 4063 | int plane = pipe; |
91d14251 | 4064 | if (HAS_FBC(dev_priv)) |
1f1c2e24 VS |
4065 | plane = !plane; |
4066 | ||
4356d586 | 4067 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
91d14251 | 4068 | i8xx_handle_vblank(dev_priv, plane, pipe, iir)) |
1f1c2e24 | 4069 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); |
c2798b19 | 4070 | |
4356d586 | 4071 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
91d14251 | 4072 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
2d9d2b0b | 4073 | |
1f7247c0 DV |
4074 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4075 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
4076 | pipe); | |
4356d586 | 4077 | } |
c2798b19 CW |
4078 | |
4079 | iir = new_iir; | |
4080 | } | |
1f814dac ID |
4081 | ret = IRQ_HANDLED; |
4082 | ||
4083 | out: | |
4084 | enable_rpm_wakeref_asserts(dev_priv); | |
c2798b19 | 4085 | |
1f814dac | 4086 | return ret; |
c2798b19 CW |
4087 | } |
4088 | ||
4089 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
4090 | { | |
2d1013dd | 4091 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
4092 | int pipe; |
4093 | ||
055e393f | 4094 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
4095 | /* Clear enable bits; then clear status bits */ |
4096 | I915_WRITE(PIPESTAT(pipe), 0); | |
4097 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
4098 | } | |
4099 | I915_WRITE16(IMR, 0xffff); | |
4100 | I915_WRITE16(IER, 0x0); | |
4101 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
4102 | } | |
4103 | ||
a266c7d5 CW |
4104 | static void i915_irq_preinstall(struct drm_device * dev) |
4105 | { | |
2d1013dd | 4106 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4107 | int pipe; |
4108 | ||
a266c7d5 | 4109 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 4110 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
4111 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
4112 | } | |
4113 | ||
00d98ebd | 4114 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 4115 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4116 | I915_WRITE(PIPESTAT(pipe), 0); |
4117 | I915_WRITE(IMR, 0xffffffff); | |
4118 | I915_WRITE(IER, 0x0); | |
4119 | POSTING_READ(IER); | |
4120 | } | |
4121 | ||
4122 | static int i915_irq_postinstall(struct drm_device *dev) | |
4123 | { | |
2d1013dd | 4124 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 4125 | u32 enable_mask; |
a266c7d5 | 4126 | |
38bde180 CW |
4127 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
4128 | ||
4129 | /* Unmask the interrupts that we always want on. */ | |
4130 | dev_priv->irq_mask = | |
4131 | ~(I915_ASLE_INTERRUPT | | |
4132 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
4133 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4134 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 4135 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
38bde180 CW |
4136 | |
4137 | enable_mask = | |
4138 | I915_ASLE_INTERRUPT | | |
4139 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
4140 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
38bde180 CW |
4141 | I915_USER_INTERRUPT; |
4142 | ||
a266c7d5 | 4143 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 4144 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
4145 | POSTING_READ(PORT_HOTPLUG_EN); |
4146 | ||
a266c7d5 CW |
4147 | /* Enable in IER... */ |
4148 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
4149 | /* and unmask in IMR */ | |
4150 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
4151 | } | |
4152 | ||
a266c7d5 CW |
4153 | I915_WRITE(IMR, dev_priv->irq_mask); |
4154 | I915_WRITE(IER, enable_mask); | |
4155 | POSTING_READ(IER); | |
4156 | ||
91d14251 | 4157 | i915_enable_asle_pipestat(dev_priv); |
20afbda2 | 4158 | |
379ef82d DV |
4159 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4160 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4161 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4162 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
4163 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4164 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 4165 | |
20afbda2 DV |
4166 | return 0; |
4167 | } | |
4168 | ||
90a72f87 VS |
4169 | /* |
4170 | * Returns true when a page flip has completed. | |
4171 | */ | |
91d14251 | 4172 | static bool i915_handle_vblank(struct drm_i915_private *dev_priv, |
90a72f87 VS |
4173 | int plane, int pipe, u32 iir) |
4174 | { | |
90a72f87 VS |
4175 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
4176 | ||
91d14251 | 4177 | if (!intel_pipe_handle_vblank(dev_priv, pipe)) |
90a72f87 VS |
4178 | return false; |
4179 | ||
4180 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 4181 | goto check_page_flip; |
90a72f87 | 4182 | |
90a72f87 VS |
4183 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
4184 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
4185 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
4186 | * the flip is completed (no longer pending). Since this doesn't raise | |
4187 | * an interrupt per se, we watch for the change at vblank. | |
4188 | */ | |
4189 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 4190 | goto check_page_flip; |
90a72f87 | 4191 | |
91d14251 TU |
4192 | intel_prepare_page_flip(dev_priv, plane); |
4193 | intel_finish_page_flip(dev_priv, pipe); | |
90a72f87 | 4194 | return true; |
d6bbafa1 CW |
4195 | |
4196 | check_page_flip: | |
91d14251 | 4197 | intel_check_page_flip(dev_priv, pipe); |
d6bbafa1 | 4198 | return false; |
90a72f87 VS |
4199 | } |
4200 | ||
ff1f525e | 4201 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 4202 | { |
45a83f84 | 4203 | struct drm_device *dev = arg; |
2d1013dd | 4204 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 4205 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
4206 | u32 flip_mask = |
4207 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4208 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 4209 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 4210 | |
2dd2a883 ID |
4211 | if (!intel_irqs_enabled(dev_priv)) |
4212 | return IRQ_NONE; | |
4213 | ||
1f814dac ID |
4214 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
4215 | disable_rpm_wakeref_asserts(dev_priv); | |
4216 | ||
a266c7d5 | 4217 | iir = I915_READ(IIR); |
38bde180 CW |
4218 | do { |
4219 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 4220 | bool blc_event = false; |
a266c7d5 CW |
4221 | |
4222 | /* Can't rely on pipestat interrupt bit in iir as it might | |
4223 | * have been cleared after the pipestat interrupt was received. | |
4224 | * It doesn't set the bit in iir again, but it still produces | |
4225 | * interrupts (for non-MSI). | |
4226 | */ | |
222c7f51 | 4227 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4228 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4229 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4230 | |
055e393f | 4231 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 4232 | i915_reg_t reg = PIPESTAT(pipe); |
a266c7d5 CW |
4233 | pipe_stats[pipe] = I915_READ(reg); |
4234 | ||
38bde180 | 4235 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 4236 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 4237 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 4238 | irq_received = true; |
a266c7d5 CW |
4239 | } |
4240 | } | |
222c7f51 | 4241 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4242 | |
4243 | if (!irq_received) | |
4244 | break; | |
4245 | ||
a266c7d5 | 4246 | /* Consume port. Then clear IIR or we'll miss events */ |
91d14251 | 4247 | if (I915_HAS_HOTPLUG(dev_priv) && |
1ae3c34c VS |
4248 | iir & I915_DISPLAY_PORT_INTERRUPT) { |
4249 | u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); | |
4250 | if (hotplug_status) | |
91d14251 | 4251 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
1ae3c34c | 4252 | } |
a266c7d5 | 4253 | |
38bde180 | 4254 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4255 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4256 | ||
a266c7d5 | 4257 | if (iir & I915_USER_INTERRUPT) |
4a570db5 | 4258 | notify_ring(&dev_priv->engine[RCS]); |
a266c7d5 | 4259 | |
055e393f | 4260 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 4261 | int plane = pipe; |
91d14251 | 4262 | if (HAS_FBC(dev_priv)) |
38bde180 | 4263 | plane = !plane; |
90a72f87 | 4264 | |
8291ee90 | 4265 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
91d14251 | 4266 | i915_handle_vblank(dev_priv, plane, pipe, iir)) |
90a72f87 | 4267 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); |
a266c7d5 CW |
4268 | |
4269 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4270 | blc_event = true; | |
4356d586 DV |
4271 | |
4272 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 4273 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
2d9d2b0b | 4274 | |
1f7247c0 DV |
4275 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4276 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
4277 | pipe); | |
a266c7d5 CW |
4278 | } |
4279 | ||
a266c7d5 | 4280 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
91d14251 | 4281 | intel_opregion_asle_intr(dev_priv); |
a266c7d5 CW |
4282 | |
4283 | /* With MSI, interrupts are only generated when iir | |
4284 | * transitions from zero to nonzero. If another bit got | |
4285 | * set while we were handling the existing iir bits, then | |
4286 | * we would never get another interrupt. | |
4287 | * | |
4288 | * This is fine on non-MSI as well, as if we hit this path | |
4289 | * we avoid exiting the interrupt handler only to generate | |
4290 | * another one. | |
4291 | * | |
4292 | * Note that for MSI this could cause a stray interrupt report | |
4293 | * if an interrupt landed in the time between writing IIR and | |
4294 | * the posting read. This should be rare enough to never | |
4295 | * trigger the 99% of 100,000 interrupts test for disabling | |
4296 | * stray interrupts. | |
4297 | */ | |
38bde180 | 4298 | ret = IRQ_HANDLED; |
a266c7d5 | 4299 | iir = new_iir; |
38bde180 | 4300 | } while (iir & ~flip_mask); |
a266c7d5 | 4301 | |
1f814dac ID |
4302 | enable_rpm_wakeref_asserts(dev_priv); |
4303 | ||
a266c7d5 CW |
4304 | return ret; |
4305 | } | |
4306 | ||
4307 | static void i915_irq_uninstall(struct drm_device * dev) | |
4308 | { | |
2d1013dd | 4309 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4310 | int pipe; |
4311 | ||
a266c7d5 | 4312 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 4313 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
4314 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
4315 | } | |
4316 | ||
00d98ebd | 4317 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 4318 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 4319 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 4320 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4321 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4322 | } | |
a266c7d5 CW |
4323 | I915_WRITE(IMR, 0xffffffff); |
4324 | I915_WRITE(IER, 0x0); | |
4325 | ||
a266c7d5 CW |
4326 | I915_WRITE(IIR, I915_READ(IIR)); |
4327 | } | |
4328 | ||
4329 | static void i965_irq_preinstall(struct drm_device * dev) | |
4330 | { | |
2d1013dd | 4331 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4332 | int pipe; |
4333 | ||
0706f17c | 4334 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4335 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4336 | |
4337 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4338 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4339 | I915_WRITE(PIPESTAT(pipe), 0); |
4340 | I915_WRITE(IMR, 0xffffffff); | |
4341 | I915_WRITE(IER, 0x0); | |
4342 | POSTING_READ(IER); | |
4343 | } | |
4344 | ||
4345 | static int i965_irq_postinstall(struct drm_device *dev) | |
4346 | { | |
2d1013dd | 4347 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4348 | u32 enable_mask; |
a266c7d5 CW |
4349 | u32 error_mask; |
4350 | ||
a266c7d5 | 4351 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4352 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4353 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4354 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4355 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4356 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4357 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4358 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4359 | ||
4360 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4361 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4362 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4363 | enable_mask |= I915_USER_INTERRUPT; |
4364 | ||
91d14251 | 4365 | if (IS_G4X(dev_priv)) |
bbba0a97 | 4366 | enable_mask |= I915_BSD_USER_INTERRUPT; |
a266c7d5 | 4367 | |
b79480ba DV |
4368 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4369 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4370 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4371 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4372 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4373 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4374 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4375 | |
a266c7d5 CW |
4376 | /* |
4377 | * Enable some error detection, note the instruction error mask | |
4378 | * bit is reserved, so we leave it masked. | |
4379 | */ | |
91d14251 | 4380 | if (IS_G4X(dev_priv)) { |
a266c7d5 CW |
4381 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
4382 | GM45_ERROR_MEM_PRIV | | |
4383 | GM45_ERROR_CP_PRIV | | |
4384 | I915_ERROR_MEMORY_REFRESH); | |
4385 | } else { | |
4386 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4387 | I915_ERROR_MEMORY_REFRESH); | |
4388 | } | |
4389 | I915_WRITE(EMR, error_mask); | |
4390 | ||
4391 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4392 | I915_WRITE(IER, enable_mask); | |
4393 | POSTING_READ(IER); | |
4394 | ||
0706f17c | 4395 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
4396 | POSTING_READ(PORT_HOTPLUG_EN); |
4397 | ||
91d14251 | 4398 | i915_enable_asle_pipestat(dev_priv); |
20afbda2 DV |
4399 | |
4400 | return 0; | |
4401 | } | |
4402 | ||
91d14251 | 4403 | static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) |
20afbda2 | 4404 | { |
20afbda2 DV |
4405 | u32 hotplug_en; |
4406 | ||
b5ea2d56 DV |
4407 | assert_spin_locked(&dev_priv->irq_lock); |
4408 | ||
778eb334 VS |
4409 | /* Note HDMI and DP share hotplug bits */ |
4410 | /* enable bits are the same for all generations */ | |
91d14251 | 4411 | hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); |
778eb334 VS |
4412 | /* Programming the CRT detection parameters tends |
4413 | to generate a spurious hotplug event about three | |
4414 | seconds later. So just do it once. | |
4415 | */ | |
91d14251 | 4416 | if (IS_G4X(dev_priv)) |
778eb334 | 4417 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
778eb334 VS |
4418 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
4419 | ||
4420 | /* Ignore TV since it's buggy */ | |
0706f17c | 4421 | i915_hotplug_interrupt_update_locked(dev_priv, |
f9e3dc78 JN |
4422 | HOTPLUG_INT_EN_MASK | |
4423 | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | | |
4424 | CRT_HOTPLUG_ACTIVATION_PERIOD_64, | |
4425 | hotplug_en); | |
a266c7d5 CW |
4426 | } |
4427 | ||
ff1f525e | 4428 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4429 | { |
45a83f84 | 4430 | struct drm_device *dev = arg; |
2d1013dd | 4431 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4432 | u32 iir, new_iir; |
4433 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4434 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4435 | u32 flip_mask = |
4436 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4437 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4438 | |
2dd2a883 ID |
4439 | if (!intel_irqs_enabled(dev_priv)) |
4440 | return IRQ_NONE; | |
4441 | ||
1f814dac ID |
4442 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
4443 | disable_rpm_wakeref_asserts(dev_priv); | |
4444 | ||
a266c7d5 CW |
4445 | iir = I915_READ(IIR); |
4446 | ||
a266c7d5 | 4447 | for (;;) { |
501e01d7 | 4448 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4449 | bool blc_event = false; |
4450 | ||
a266c7d5 CW |
4451 | /* Can't rely on pipestat interrupt bit in iir as it might |
4452 | * have been cleared after the pipestat interrupt was received. | |
4453 | * It doesn't set the bit in iir again, but it still produces | |
4454 | * interrupts (for non-MSI). | |
4455 | */ | |
222c7f51 | 4456 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4457 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4458 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4459 | |
055e393f | 4460 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 4461 | i915_reg_t reg = PIPESTAT(pipe); |
a266c7d5 CW |
4462 | pipe_stats[pipe] = I915_READ(reg); |
4463 | ||
4464 | /* | |
4465 | * Clear the PIPE*STAT regs before the IIR | |
4466 | */ | |
4467 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4468 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4469 | irq_received = true; |
a266c7d5 CW |
4470 | } |
4471 | } | |
222c7f51 | 4472 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4473 | |
4474 | if (!irq_received) | |
4475 | break; | |
4476 | ||
4477 | ret = IRQ_HANDLED; | |
4478 | ||
4479 | /* Consume port. Then clear IIR or we'll miss events */ | |
1ae3c34c VS |
4480 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
4481 | u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); | |
4482 | if (hotplug_status) | |
91d14251 | 4483 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
1ae3c34c | 4484 | } |
a266c7d5 | 4485 | |
21ad8330 | 4486 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4487 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4488 | ||
a266c7d5 | 4489 | if (iir & I915_USER_INTERRUPT) |
4a570db5 | 4490 | notify_ring(&dev_priv->engine[RCS]); |
a266c7d5 | 4491 | if (iir & I915_BSD_USER_INTERRUPT) |
4a570db5 | 4492 | notify_ring(&dev_priv->engine[VCS]); |
a266c7d5 | 4493 | |
055e393f | 4494 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 4495 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
91d14251 | 4496 | i915_handle_vblank(dev_priv, pipe, pipe, iir)) |
90a72f87 | 4497 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); |
a266c7d5 CW |
4498 | |
4499 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4500 | blc_event = true; | |
4356d586 DV |
4501 | |
4502 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 4503 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
a266c7d5 | 4504 | |
1f7247c0 DV |
4505 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4506 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4507 | } |
a266c7d5 CW |
4508 | |
4509 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
91d14251 | 4510 | intel_opregion_asle_intr(dev_priv); |
a266c7d5 | 4511 | |
515ac2bb | 4512 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
91d14251 | 4513 | gmbus_irq_handler(dev_priv); |
515ac2bb | 4514 | |
a266c7d5 CW |
4515 | /* With MSI, interrupts are only generated when iir |
4516 | * transitions from zero to nonzero. If another bit got | |
4517 | * set while we were handling the existing iir bits, then | |
4518 | * we would never get another interrupt. | |
4519 | * | |
4520 | * This is fine on non-MSI as well, as if we hit this path | |
4521 | * we avoid exiting the interrupt handler only to generate | |
4522 | * another one. | |
4523 | * | |
4524 | * Note that for MSI this could cause a stray interrupt report | |
4525 | * if an interrupt landed in the time between writing IIR and | |
4526 | * the posting read. This should be rare enough to never | |
4527 | * trigger the 99% of 100,000 interrupts test for disabling | |
4528 | * stray interrupts. | |
4529 | */ | |
4530 | iir = new_iir; | |
4531 | } | |
4532 | ||
1f814dac ID |
4533 | enable_rpm_wakeref_asserts(dev_priv); |
4534 | ||
a266c7d5 CW |
4535 | return ret; |
4536 | } | |
4537 | ||
4538 | static void i965_irq_uninstall(struct drm_device * dev) | |
4539 | { | |
2d1013dd | 4540 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4541 | int pipe; |
4542 | ||
4543 | if (!dev_priv) | |
4544 | return; | |
4545 | ||
0706f17c | 4546 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4547 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4548 | |
4549 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4550 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4551 | I915_WRITE(PIPESTAT(pipe), 0); |
4552 | I915_WRITE(IMR, 0xffffffff); | |
4553 | I915_WRITE(IER, 0x0); | |
4554 | ||
055e393f | 4555 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4556 | I915_WRITE(PIPESTAT(pipe), |
4557 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4558 | I915_WRITE(IIR, I915_READ(IIR)); | |
4559 | } | |
4560 | ||
fca52a55 DV |
4561 | /** |
4562 | * intel_irq_init - initializes irq support | |
4563 | * @dev_priv: i915 device instance | |
4564 | * | |
4565 | * This function initializes all the irq support including work items, timers | |
4566 | * and all the vtables. It does not setup the interrupt itself though. | |
4567 | */ | |
b963291c | 4568 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4569 | { |
b963291c | 4570 | struct drm_device *dev = dev_priv->dev; |
8b2e326d | 4571 | |
77913b39 JN |
4572 | intel_hpd_init_work(dev_priv); |
4573 | ||
c6a828d3 | 4574 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4575 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4576 | |
a6706b45 | 4577 | /* Let's track the enabled rps events */ |
666a4537 | 4578 | if (IS_VALLEYVIEW(dev_priv)) |
6c65a587 | 4579 | /* WaGsvRC0ResidencyMethod:vlv */ |
6f4b12f8 | 4580 | dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; |
31685c25 D |
4581 | else |
4582 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4583 | |
737b1506 CW |
4584 | INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work, |
4585 | i915_hangcheck_elapsed); | |
61bac78e | 4586 | |
b963291c | 4587 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4588 | dev->max_vblank_count = 0; |
4589 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4590 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 | 4591 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
fd8f507c | 4592 | dev->driver->get_vblank_counter = g4x_get_vblank_counter; |
391f75e2 VS |
4593 | } else { |
4594 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4595 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4596 | } |
4597 | ||
21da2700 VS |
4598 | /* |
4599 | * Opt out of the vblank disable timer on everything except gen2. | |
4600 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4601 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4602 | */ | |
b963291c | 4603 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4604 | dev->vblank_disable_immediate = true; |
4605 | ||
f3a5c3f6 DV |
4606 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
4607 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; | |
f71d4af4 | 4608 | |
b963291c | 4609 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4610 | dev->driver->irq_handler = cherryview_irq_handler; |
4611 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4612 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4613 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4614 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4615 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4616 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4617 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4618 | dev->driver->irq_handler = valleyview_irq_handler; |
4619 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4620 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4621 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4622 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4623 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4624 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4625 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4626 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4627 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4628 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4629 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4630 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4631 | dev->driver->disable_vblank = gen8_disable_vblank; | |
6dbf30ce | 4632 | if (IS_BROXTON(dev)) |
e0a20ad7 | 4633 | dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; |
6dbf30ce VS |
4634 | else if (HAS_PCH_SPT(dev)) |
4635 | dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; | |
4636 | else | |
3a3b3c7d | 4637 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 JB |
4638 | } else if (HAS_PCH_SPLIT(dev)) { |
4639 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4640 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4641 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4642 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4643 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4644 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
23bb4cb5 | 4645 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 | 4646 | } else { |
b963291c | 4647 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4648 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4649 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4650 | dev->driver->irq_handler = i8xx_irq_handler; | |
4651 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4652 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4653 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4654 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4655 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4656 | dev->driver->irq_handler = i915_irq_handler; | |
c2798b19 | 4657 | } else { |
a266c7d5 CW |
4658 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4659 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4660 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4661 | dev->driver->irq_handler = i965_irq_handler; | |
c2798b19 | 4662 | } |
778eb334 VS |
4663 | if (I915_HAS_HOTPLUG(dev_priv)) |
4664 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
f71d4af4 JB |
4665 | dev->driver->enable_vblank = i915_enable_vblank; |
4666 | dev->driver->disable_vblank = i915_disable_vblank; | |
4667 | } | |
4668 | } | |
20afbda2 | 4669 | |
fca52a55 DV |
4670 | /** |
4671 | * intel_irq_install - enables the hardware interrupt | |
4672 | * @dev_priv: i915 device instance | |
4673 | * | |
4674 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4675 | * handling still disabled. It is called after intel_irq_init(). | |
4676 | * | |
4677 | * In the driver load and resume code we need working interrupts in a few places | |
4678 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4679 | * workers. Hence the split into this two-stage approach. | |
4680 | */ | |
2aeb7d3a DV |
4681 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4682 | { | |
4683 | /* | |
4684 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4685 | * interrupts as enabled _before_ actually enabling them to avoid | |
4686 | * special cases in our ordering checks. | |
4687 | */ | |
4688 | dev_priv->pm.irqs_enabled = true; | |
4689 | ||
4690 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4691 | } | |
4692 | ||
fca52a55 DV |
4693 | /** |
4694 | * intel_irq_uninstall - finilizes all irq handling | |
4695 | * @dev_priv: i915 device instance | |
4696 | * | |
4697 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4698 | * resources acquired in the init functions. | |
4699 | */ | |
2aeb7d3a DV |
4700 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4701 | { | |
4702 | drm_irq_uninstall(dev_priv->dev); | |
4703 | intel_hpd_cancel_work(dev_priv); | |
4704 | dev_priv->pm.irqs_enabled = false; | |
4705 | } | |
4706 | ||
fca52a55 DV |
4707 | /** |
4708 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4709 | * @dev_priv: i915 device instance | |
4710 | * | |
4711 | * This function is used to disable interrupts at runtime, both in the runtime | |
4712 | * pm and the system suspend/resume code. | |
4713 | */ | |
b963291c | 4714 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4715 | { |
b963291c | 4716 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4717 | dev_priv->pm.irqs_enabled = false; |
2dd2a883 | 4718 | synchronize_irq(dev_priv->dev->irq); |
c67a470b PZ |
4719 | } |
4720 | ||
fca52a55 DV |
4721 | /** |
4722 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4723 | * @dev_priv: i915 device instance | |
4724 | * | |
4725 | * This function is used to enable interrupts at runtime, both in the runtime | |
4726 | * pm and the system suspend/resume code. | |
4727 | */ | |
b963291c | 4728 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4729 | { |
2aeb7d3a | 4730 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4731 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4732 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4733 | } |