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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e5868a31 EE |
48 | static const u32 hpd_ibx[] = { |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
54 | }; | |
55 | ||
56 | static const u32 hpd_cpt[] = { | |
57 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 58 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
59 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
60 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
61 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
62 | }; | |
63 | ||
64 | static const u32 hpd_mask_i915[] = { | |
65 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
71 | }; | |
72 | ||
704cfb87 | 73 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
80 | }; | |
81 | ||
e5868a31 EE |
82 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
83 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
84 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
85 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
86 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
87 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
88 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
89 | }; | |
90 | ||
5c502442 | 91 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 92 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
93 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
94 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
95 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
96 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
97 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
98 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
99 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
100 | } while (0) | |
101 | ||
f86f3fb0 | 102 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 103 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 104 | POSTING_READ(type##IMR); \ |
a9d356a6 | 105 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
106 | I915_WRITE(type##IIR, 0xffffffff); \ |
107 | POSTING_READ(type##IIR); \ | |
108 | I915_WRITE(type##IIR, 0xffffffff); \ | |
109 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
110 | } while (0) |
111 | ||
337ba017 PZ |
112 | /* |
113 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
114 | */ | |
115 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
116 | u32 val = I915_READ(reg); \ | |
117 | if (val) { \ | |
118 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
119 | (reg), val); \ | |
120 | I915_WRITE((reg), 0xffffffff); \ | |
121 | POSTING_READ(reg); \ | |
122 | I915_WRITE((reg), 0xffffffff); \ | |
123 | POSTING_READ(reg); \ | |
124 | } \ | |
125 | } while (0) | |
126 | ||
35079899 | 127 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 128 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 | 129 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
130 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
131 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
132 | } while (0) |
133 | ||
134 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 135 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 | 136 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
137 | I915_WRITE(type##IMR, (imr_val)); \ |
138 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
139 | } while (0) |
140 | ||
c9a9a268 ID |
141 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
142 | ||
036a4a7d | 143 | /* For display hotplug interrupt */ |
47339cd9 | 144 | void |
2d1013dd | 145 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 146 | { |
4bc9d430 DV |
147 | assert_spin_locked(&dev_priv->irq_lock); |
148 | ||
9df7575f | 149 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 150 | return; |
c67a470b | 151 | |
1ec14ad3 CW |
152 | if ((dev_priv->irq_mask & mask) != 0) { |
153 | dev_priv->irq_mask &= ~mask; | |
154 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 155 | POSTING_READ(DEIMR); |
036a4a7d ZW |
156 | } |
157 | } | |
158 | ||
47339cd9 | 159 | void |
2d1013dd | 160 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 161 | { |
4bc9d430 DV |
162 | assert_spin_locked(&dev_priv->irq_lock); |
163 | ||
06ffc778 | 164 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 165 | return; |
c67a470b | 166 | |
1ec14ad3 CW |
167 | if ((dev_priv->irq_mask & mask) != mask) { |
168 | dev_priv->irq_mask |= mask; | |
169 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 170 | POSTING_READ(DEIMR); |
036a4a7d ZW |
171 | } |
172 | } | |
173 | ||
43eaea13 PZ |
174 | /** |
175 | * ilk_update_gt_irq - update GTIMR | |
176 | * @dev_priv: driver private | |
177 | * @interrupt_mask: mask of interrupt bits to update | |
178 | * @enabled_irq_mask: mask of interrupt bits to enable | |
179 | */ | |
180 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
181 | uint32_t interrupt_mask, | |
182 | uint32_t enabled_irq_mask) | |
183 | { | |
184 | assert_spin_locked(&dev_priv->irq_lock); | |
185 | ||
9df7575f | 186 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 187 | return; |
c67a470b | 188 | |
43eaea13 PZ |
189 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
190 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
191 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
192 | POSTING_READ(GTIMR); | |
193 | } | |
194 | ||
480c8033 | 195 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
196 | { |
197 | ilk_update_gt_irq(dev_priv, mask, mask); | |
198 | } | |
199 | ||
480c8033 | 200 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
201 | { |
202 | ilk_update_gt_irq(dev_priv, mask, 0); | |
203 | } | |
204 | ||
b900b949 ID |
205 | static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) |
206 | { | |
207 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
208 | } | |
209 | ||
a72fbc3a ID |
210 | static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) |
211 | { | |
212 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
213 | } | |
214 | ||
b900b949 ID |
215 | static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) |
216 | { | |
217 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
218 | } | |
219 | ||
edbfdb45 PZ |
220 | /** |
221 | * snb_update_pm_irq - update GEN6_PMIMR | |
222 | * @dev_priv: driver private | |
223 | * @interrupt_mask: mask of interrupt bits to update | |
224 | * @enabled_irq_mask: mask of interrupt bits to enable | |
225 | */ | |
226 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
227 | uint32_t interrupt_mask, | |
228 | uint32_t enabled_irq_mask) | |
229 | { | |
605cd25b | 230 | uint32_t new_val; |
edbfdb45 PZ |
231 | |
232 | assert_spin_locked(&dev_priv->irq_lock); | |
233 | ||
9df7575f | 234 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 235 | return; |
c67a470b | 236 | |
605cd25b | 237 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
238 | new_val &= ~interrupt_mask; |
239 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
240 | ||
605cd25b PZ |
241 | if (new_val != dev_priv->pm_irq_mask) { |
242 | dev_priv->pm_irq_mask = new_val; | |
a72fbc3a ID |
243 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
244 | POSTING_READ(gen6_pm_imr(dev_priv)); | |
f52ecbcf | 245 | } |
edbfdb45 PZ |
246 | } |
247 | ||
480c8033 | 248 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 PZ |
249 | { |
250 | snb_update_pm_irq(dev_priv, mask, mask); | |
251 | } | |
252 | ||
480c8033 | 253 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 PZ |
254 | { |
255 | snb_update_pm_irq(dev_priv, mask, 0); | |
256 | } | |
257 | ||
b900b949 ID |
258 | void gen6_enable_rps_interrupts(struct drm_device *dev) |
259 | { | |
260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
261 | ||
262 | spin_lock_irq(&dev_priv->irq_lock); | |
263 | WARN_ON(dev_priv->rps.pm_iir); | |
264 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
265 | I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); | |
266 | spin_unlock_irq(&dev_priv->irq_lock); | |
267 | } | |
268 | ||
269 | void gen6_disable_rps_interrupts(struct drm_device *dev) | |
270 | { | |
271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
272 | ||
273 | I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ? | |
274 | ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0); | |
275 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & | |
276 | ~dev_priv->pm_rps_events); | |
277 | /* Complete PM interrupt masking here doesn't race with the rps work | |
278 | * item again unmasking PM interrupts because that is using a different | |
279 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving | |
280 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ | |
281 | ||
282 | spin_lock_irq(&dev_priv->irq_lock); | |
283 | dev_priv->rps.pm_iir = 0; | |
284 | spin_unlock_irq(&dev_priv->irq_lock); | |
285 | ||
286 | I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); | |
287 | } | |
288 | ||
fee884ed DV |
289 | /** |
290 | * ibx_display_interrupt_update - update SDEIMR | |
291 | * @dev_priv: driver private | |
292 | * @interrupt_mask: mask of interrupt bits to update | |
293 | * @enabled_irq_mask: mask of interrupt bits to enable | |
294 | */ | |
47339cd9 DV |
295 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
296 | uint32_t interrupt_mask, | |
297 | uint32_t enabled_irq_mask) | |
fee884ed DV |
298 | { |
299 | uint32_t sdeimr = I915_READ(SDEIMR); | |
300 | sdeimr &= ~interrupt_mask; | |
301 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
302 | ||
303 | assert_spin_locked(&dev_priv->irq_lock); | |
304 | ||
9df7575f | 305 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 306 | return; |
c67a470b | 307 | |
fee884ed DV |
308 | I915_WRITE(SDEIMR, sdeimr); |
309 | POSTING_READ(SDEIMR); | |
310 | } | |
8664281b | 311 | |
b5ea642a | 312 | static void |
755e9019 ID |
313 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
314 | u32 enable_mask, u32 status_mask) | |
7c463586 | 315 | { |
46c06a30 | 316 | u32 reg = PIPESTAT(pipe); |
755e9019 | 317 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 318 | |
b79480ba | 319 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 320 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 321 | |
04feced9 VS |
322 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
323 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
324 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
325 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
326 | return; |
327 | ||
328 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
329 | return; |
330 | ||
91d181dd ID |
331 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
332 | ||
46c06a30 | 333 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 334 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
335 | I915_WRITE(reg, pipestat); |
336 | POSTING_READ(reg); | |
7c463586 KP |
337 | } |
338 | ||
b5ea642a | 339 | static void |
755e9019 ID |
340 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
341 | u32 enable_mask, u32 status_mask) | |
7c463586 | 342 | { |
46c06a30 | 343 | u32 reg = PIPESTAT(pipe); |
755e9019 | 344 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 345 | |
b79480ba | 346 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 347 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 348 | |
04feced9 VS |
349 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
350 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
351 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
352 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
353 | return; |
354 | ||
755e9019 ID |
355 | if ((pipestat & enable_mask) == 0) |
356 | return; | |
357 | ||
91d181dd ID |
358 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
359 | ||
755e9019 | 360 | pipestat &= ~enable_mask; |
46c06a30 VS |
361 | I915_WRITE(reg, pipestat); |
362 | POSTING_READ(reg); | |
7c463586 KP |
363 | } |
364 | ||
10c59c51 ID |
365 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
366 | { | |
367 | u32 enable_mask = status_mask << 16; | |
368 | ||
369 | /* | |
724a6905 VS |
370 | * On pipe A we don't support the PSR interrupt yet, |
371 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
372 | */ |
373 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
374 | return 0; | |
724a6905 VS |
375 | /* |
376 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
377 | * A the same bit is for perf counters which we don't use either. | |
378 | */ | |
379 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
380 | return 0; | |
10c59c51 ID |
381 | |
382 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
383 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
384 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
385 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
386 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
387 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
388 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
389 | ||
390 | return enable_mask; | |
391 | } | |
392 | ||
755e9019 ID |
393 | void |
394 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
395 | u32 status_mask) | |
396 | { | |
397 | u32 enable_mask; | |
398 | ||
10c59c51 ID |
399 | if (IS_VALLEYVIEW(dev_priv->dev)) |
400 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
401 | status_mask); | |
402 | else | |
403 | enable_mask = status_mask << 16; | |
755e9019 ID |
404 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
405 | } | |
406 | ||
407 | void | |
408 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
409 | u32 status_mask) | |
410 | { | |
411 | u32 enable_mask; | |
412 | ||
10c59c51 ID |
413 | if (IS_VALLEYVIEW(dev_priv->dev)) |
414 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
415 | status_mask); | |
416 | else | |
417 | enable_mask = status_mask << 16; | |
755e9019 ID |
418 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
419 | } | |
420 | ||
01c66889 | 421 | /** |
f49e38dd | 422 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 423 | */ |
f49e38dd | 424 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 425 | { |
2d1013dd | 426 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 427 | |
f49e38dd JN |
428 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
429 | return; | |
430 | ||
13321786 | 431 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 432 | |
755e9019 | 433 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 434 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 435 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 436 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 437 | |
13321786 | 438 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
439 | } |
440 | ||
0a3e67a4 JB |
441 | /** |
442 | * i915_pipe_enabled - check if a pipe is enabled | |
443 | * @dev: DRM device | |
444 | * @pipe: pipe to check | |
445 | * | |
446 | * Reading certain registers when the pipe is disabled can hang the chip. | |
447 | * Use this routine to make sure the PLL is running and the pipe is active | |
448 | * before reading such registers if unsure. | |
449 | */ | |
450 | static int | |
451 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
452 | { | |
2d1013dd | 453 | struct drm_i915_private *dev_priv = dev->dev_private; |
702e7a56 | 454 | |
a01025af DV |
455 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
456 | /* Locking is horribly broken here, but whatever. */ | |
457 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
458 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 459 | |
a01025af DV |
460 | return intel_crtc->active; |
461 | } else { | |
462 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
463 | } | |
0a3e67a4 JB |
464 | } |
465 | ||
f75f3746 VS |
466 | /* |
467 | * This timing diagram depicts the video signal in and | |
468 | * around the vertical blanking period. | |
469 | * | |
470 | * Assumptions about the fictitious mode used in this example: | |
471 | * vblank_start >= 3 | |
472 | * vsync_start = vblank_start + 1 | |
473 | * vsync_end = vblank_start + 2 | |
474 | * vtotal = vblank_start + 3 | |
475 | * | |
476 | * start of vblank: | |
477 | * latch double buffered registers | |
478 | * increment frame counter (ctg+) | |
479 | * generate start of vblank interrupt (gen4+) | |
480 | * | | |
481 | * | frame start: | |
482 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
483 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
484 | * | | | |
485 | * | | start of vsync: | |
486 | * | | generate vsync interrupt | |
487 | * | | | | |
488 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
489 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
490 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
491 | * | | <----vs-----> | | |
492 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
493 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
494 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
495 | * | | | | |
496 | * last visible pixel first visible pixel | |
497 | * | increment frame counter (gen3/4) | |
498 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
499 | * | |
500 | * x = horizontal active | |
501 | * _ = horizontal blanking | |
502 | * hs = horizontal sync | |
503 | * va = vertical active | |
504 | * vb = vertical blanking | |
505 | * vs = vertical sync | |
506 | * vbs = vblank_start (number) | |
507 | * | |
508 | * Summary: | |
509 | * - most events happen at the start of horizontal sync | |
510 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
511 | * (depending on PIPECONF settings) after the start of vblank | |
512 | * - gen3/4 pixel and frame counter are synchronized with the start | |
513 | * of horizontal active on the first line of vertical active | |
514 | */ | |
515 | ||
4cdb83ec VS |
516 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
517 | { | |
518 | /* Gen2 doesn't have a hardware frame counter */ | |
519 | return 0; | |
520 | } | |
521 | ||
42f52ef8 KP |
522 | /* Called from drm generic code, passed a 'crtc', which |
523 | * we use as a pipe index | |
524 | */ | |
f71d4af4 | 525 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 526 | { |
2d1013dd | 527 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
528 | unsigned long high_frame; |
529 | unsigned long low_frame; | |
0b2a8e09 | 530 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
0a3e67a4 JB |
531 | |
532 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 533 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 534 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
535 | return 0; |
536 | } | |
537 | ||
391f75e2 VS |
538 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
539 | struct intel_crtc *intel_crtc = | |
540 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
541 | const struct drm_display_mode *mode = | |
542 | &intel_crtc->config.adjusted_mode; | |
543 | ||
0b2a8e09 VS |
544 | htotal = mode->crtc_htotal; |
545 | hsync_start = mode->crtc_hsync_start; | |
546 | vbl_start = mode->crtc_vblank_start; | |
547 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
548 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 549 | } else { |
a2d213dd | 550 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
391f75e2 VS |
551 | |
552 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
0b2a8e09 | 553 | hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1; |
391f75e2 | 554 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; |
0b2a8e09 VS |
555 | if ((I915_READ(PIPECONF(cpu_transcoder)) & |
556 | PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE) | |
557 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 VS |
558 | } |
559 | ||
0b2a8e09 VS |
560 | /* Convert to pixel count */ |
561 | vbl_start *= htotal; | |
562 | ||
563 | /* Start of vblank event occurs at start of hsync */ | |
564 | vbl_start -= htotal - hsync_start; | |
565 | ||
9db4a9c7 JB |
566 | high_frame = PIPEFRAME(pipe); |
567 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 568 | |
0a3e67a4 JB |
569 | /* |
570 | * High & low register fields aren't synchronized, so make sure | |
571 | * we get a low value that's stable across two reads of the high | |
572 | * register. | |
573 | */ | |
574 | do { | |
5eddb70b | 575 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 576 | low = I915_READ(low_frame); |
5eddb70b | 577 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
578 | } while (high1 != high2); |
579 | ||
5eddb70b | 580 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 581 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 582 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
583 | |
584 | /* | |
585 | * The frame counter increments at beginning of active. | |
586 | * Cook up a vblank counter by also checking the pixel | |
587 | * counter against vblank start. | |
588 | */ | |
edc08d0a | 589 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
590 | } |
591 | ||
f71d4af4 | 592 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 593 | { |
2d1013dd | 594 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 595 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
596 | |
597 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 598 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 599 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
600 | return 0; |
601 | } | |
602 | ||
603 | return I915_READ(reg); | |
604 | } | |
605 | ||
ad3543ed MK |
606 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
607 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 608 | |
a225f079 VS |
609 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
610 | { | |
611 | struct drm_device *dev = crtc->base.dev; | |
612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
613 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
614 | enum pipe pipe = crtc->pipe; | |
80715b2f | 615 | int position, vtotal; |
a225f079 | 616 | |
80715b2f | 617 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
618 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
619 | vtotal /= 2; | |
620 | ||
621 | if (IS_GEN2(dev)) | |
622 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
623 | else | |
624 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
625 | ||
626 | /* | |
80715b2f VS |
627 | * See update_scanline_offset() for the details on the |
628 | * scanline_offset adjustment. | |
a225f079 | 629 | */ |
80715b2f | 630 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
631 | } |
632 | ||
f71d4af4 | 633 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
634 | unsigned int flags, int *vpos, int *hpos, |
635 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 636 | { |
c2baf4b7 VS |
637 | struct drm_i915_private *dev_priv = dev->dev_private; |
638 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
639 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
640 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 641 | int position; |
78e8fc6b | 642 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
643 | bool in_vbl = true; |
644 | int ret = 0; | |
ad3543ed | 645 | unsigned long irqflags; |
0af7e4df | 646 | |
c2baf4b7 | 647 | if (!intel_crtc->active) { |
0af7e4df | 648 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 649 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
650 | return 0; |
651 | } | |
652 | ||
c2baf4b7 | 653 | htotal = mode->crtc_htotal; |
78e8fc6b | 654 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
655 | vtotal = mode->crtc_vtotal; |
656 | vbl_start = mode->crtc_vblank_start; | |
657 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 658 | |
d31faf65 VS |
659 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
660 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
661 | vbl_end /= 2; | |
662 | vtotal /= 2; | |
663 | } | |
664 | ||
c2baf4b7 VS |
665 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
666 | ||
ad3543ed MK |
667 | /* |
668 | * Lock uncore.lock, as we will do multiple timing critical raw | |
669 | * register reads, potentially with preemption disabled, so the | |
670 | * following code must not block on uncore.lock. | |
671 | */ | |
672 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 673 | |
ad3543ed MK |
674 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
675 | ||
676 | /* Get optional system timestamp before query. */ | |
677 | if (stime) | |
678 | *stime = ktime_get(); | |
679 | ||
7c06b08a | 680 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
681 | /* No obvious pixelcount register. Only query vertical |
682 | * scanout position from Display scan line register. | |
683 | */ | |
a225f079 | 684 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
685 | } else { |
686 | /* Have access to pixelcount since start of frame. | |
687 | * We can split this into vertical and horizontal | |
688 | * scanout position. | |
689 | */ | |
ad3543ed | 690 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 691 | |
3aa18df8 VS |
692 | /* convert to pixel counts */ |
693 | vbl_start *= htotal; | |
694 | vbl_end *= htotal; | |
695 | vtotal *= htotal; | |
78e8fc6b | 696 | |
7e78f1cb VS |
697 | /* |
698 | * In interlaced modes, the pixel counter counts all pixels, | |
699 | * so one field will have htotal more pixels. In order to avoid | |
700 | * the reported position from jumping backwards when the pixel | |
701 | * counter is beyond the length of the shorter field, just | |
702 | * clamp the position the length of the shorter field. This | |
703 | * matches how the scanline counter based position works since | |
704 | * the scanline counter doesn't count the two half lines. | |
705 | */ | |
706 | if (position >= vtotal) | |
707 | position = vtotal - 1; | |
708 | ||
78e8fc6b VS |
709 | /* |
710 | * Start of vblank interrupt is triggered at start of hsync, | |
711 | * just prior to the first active line of vblank. However we | |
712 | * consider lines to start at the leading edge of horizontal | |
713 | * active. So, should we get here before we've crossed into | |
714 | * the horizontal active of the first line in vblank, we would | |
715 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
716 | * always add htotal-hsync_start to the current pixel position. | |
717 | */ | |
718 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
719 | } |
720 | ||
ad3543ed MK |
721 | /* Get optional system timestamp after query. */ |
722 | if (etime) | |
723 | *etime = ktime_get(); | |
724 | ||
725 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
726 | ||
727 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
728 | ||
3aa18df8 VS |
729 | in_vbl = position >= vbl_start && position < vbl_end; |
730 | ||
731 | /* | |
732 | * While in vblank, position will be negative | |
733 | * counting up towards 0 at vbl_end. And outside | |
734 | * vblank, position will be positive counting | |
735 | * up since vbl_end. | |
736 | */ | |
737 | if (position >= vbl_start) | |
738 | position -= vbl_end; | |
739 | else | |
740 | position += vtotal - vbl_end; | |
0af7e4df | 741 | |
7c06b08a | 742 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
743 | *vpos = position; |
744 | *hpos = 0; | |
745 | } else { | |
746 | *vpos = position / htotal; | |
747 | *hpos = position - (*vpos * htotal); | |
748 | } | |
0af7e4df | 749 | |
0af7e4df MK |
750 | /* In vblank? */ |
751 | if (in_vbl) | |
3d3cbd84 | 752 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
753 | |
754 | return ret; | |
755 | } | |
756 | ||
a225f079 VS |
757 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
758 | { | |
759 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
760 | unsigned long irqflags; | |
761 | int position; | |
762 | ||
763 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
764 | position = __intel_get_crtc_scanline(crtc); | |
765 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
766 | ||
767 | return position; | |
768 | } | |
769 | ||
f71d4af4 | 770 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
771 | int *max_error, |
772 | struct timeval *vblank_time, | |
773 | unsigned flags) | |
774 | { | |
4041b853 | 775 | struct drm_crtc *crtc; |
0af7e4df | 776 | |
7eb552ae | 777 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 778 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
779 | return -EINVAL; |
780 | } | |
781 | ||
782 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
783 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
784 | if (crtc == NULL) { | |
785 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
786 | return -EINVAL; | |
787 | } | |
788 | ||
789 | if (!crtc->enabled) { | |
790 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
791 | return -EBUSY; | |
792 | } | |
0af7e4df MK |
793 | |
794 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
795 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
796 | vblank_time, flags, | |
7da903ef VS |
797 | crtc, |
798 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
799 | } |
800 | ||
67c347ff JN |
801 | static bool intel_hpd_irq_event(struct drm_device *dev, |
802 | struct drm_connector *connector) | |
321a1b30 EE |
803 | { |
804 | enum drm_connector_status old_status; | |
805 | ||
806 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
807 | old_status = connector->status; | |
808 | ||
809 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
810 | if (old_status == connector->status) |
811 | return false; | |
812 | ||
813 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 | 814 | connector->base.id, |
c23cc417 | 815 | connector->name, |
67c347ff JN |
816 | drm_get_connector_status_name(old_status), |
817 | drm_get_connector_status_name(connector->status)); | |
818 | ||
819 | return true; | |
321a1b30 EE |
820 | } |
821 | ||
13cf5504 DA |
822 | static void i915_digport_work_func(struct work_struct *work) |
823 | { | |
824 | struct drm_i915_private *dev_priv = | |
825 | container_of(work, struct drm_i915_private, dig_port_work); | |
13cf5504 DA |
826 | u32 long_port_mask, short_port_mask; |
827 | struct intel_digital_port *intel_dig_port; | |
828 | int i, ret; | |
829 | u32 old_bits = 0; | |
830 | ||
4cb21832 | 831 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
832 | long_port_mask = dev_priv->long_hpd_port_mask; |
833 | dev_priv->long_hpd_port_mask = 0; | |
834 | short_port_mask = dev_priv->short_hpd_port_mask; | |
835 | dev_priv->short_hpd_port_mask = 0; | |
4cb21832 | 836 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
837 | |
838 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
839 | bool valid = false; | |
840 | bool long_hpd = false; | |
841 | intel_dig_port = dev_priv->hpd_irq_port[i]; | |
842 | if (!intel_dig_port || !intel_dig_port->hpd_pulse) | |
843 | continue; | |
844 | ||
845 | if (long_port_mask & (1 << i)) { | |
846 | valid = true; | |
847 | long_hpd = true; | |
848 | } else if (short_port_mask & (1 << i)) | |
849 | valid = true; | |
850 | ||
851 | if (valid) { | |
852 | ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd); | |
853 | if (ret == true) { | |
854 | /* if we get true fallback to old school hpd */ | |
855 | old_bits |= (1 << intel_dig_port->base.hpd_pin); | |
856 | } | |
857 | } | |
858 | } | |
859 | ||
860 | if (old_bits) { | |
4cb21832 | 861 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 | 862 | dev_priv->hpd_event_bits |= old_bits; |
4cb21832 | 863 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
864 | schedule_work(&dev_priv->hotplug_work); |
865 | } | |
866 | } | |
867 | ||
5ca58282 JB |
868 | /* |
869 | * Handle hotplug events outside the interrupt handler proper. | |
870 | */ | |
ac4c16c5 EE |
871 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
872 | ||
5ca58282 JB |
873 | static void i915_hotplug_work_func(struct work_struct *work) |
874 | { | |
2d1013dd JN |
875 | struct drm_i915_private *dev_priv = |
876 | container_of(work, struct drm_i915_private, hotplug_work); | |
5ca58282 | 877 | struct drm_device *dev = dev_priv->dev; |
c31c4ba3 | 878 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
879 | struct intel_connector *intel_connector; |
880 | struct intel_encoder *intel_encoder; | |
881 | struct drm_connector *connector; | |
cd569aed | 882 | bool hpd_disabled = false; |
321a1b30 | 883 | bool changed = false; |
142e2398 | 884 | u32 hpd_event_bits; |
4ef69c7a | 885 | |
a65e34c7 | 886 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
887 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
888 | ||
4cb21832 | 889 | spin_lock_irq(&dev_priv->irq_lock); |
142e2398 EE |
890 | |
891 | hpd_event_bits = dev_priv->hpd_event_bits; | |
892 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
893 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
894 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
895 | if (!intel_connector->encoder) |
896 | continue; | |
cd569aed EE |
897 | intel_encoder = intel_connector->encoder; |
898 | if (intel_encoder->hpd_pin > HPD_NONE && | |
899 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
900 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
901 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
902 | "switching from hotplug detection to polling\n", | |
c23cc417 | 903 | connector->name); |
cd569aed EE |
904 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; |
905 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
906 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
907 | hpd_disabled = true; | |
908 | } | |
142e2398 EE |
909 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
910 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
c23cc417 | 911 | connector->name, intel_encoder->hpd_pin); |
142e2398 | 912 | } |
cd569aed EE |
913 | } |
914 | /* if there were no outputs to poll, poll was disabled, | |
915 | * therefore make sure it's enabled when disabling HPD on | |
916 | * some connectors */ | |
ac4c16c5 | 917 | if (hpd_disabled) { |
cd569aed | 918 | drm_kms_helper_poll_enable(dev); |
6323751d ID |
919 | mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work, |
920 | msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
ac4c16c5 | 921 | } |
cd569aed | 922 | |
4cb21832 | 923 | spin_unlock_irq(&dev_priv->irq_lock); |
cd569aed | 924 | |
321a1b30 EE |
925 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
926 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
927 | if (!intel_connector->encoder) |
928 | continue; | |
321a1b30 EE |
929 | intel_encoder = intel_connector->encoder; |
930 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
931 | if (intel_encoder->hot_plug) | |
932 | intel_encoder->hot_plug(intel_encoder); | |
933 | if (intel_hpd_irq_event(dev, connector)) | |
934 | changed = true; | |
935 | } | |
936 | } | |
40ee3381 KP |
937 | mutex_unlock(&mode_config->mutex); |
938 | ||
321a1b30 EE |
939 | if (changed) |
940 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
941 | } |
942 | ||
d0ecd7e2 | 943 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 944 | { |
2d1013dd | 945 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 946 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 947 | u8 new_delay; |
9270388e | 948 | |
d0ecd7e2 | 949 | spin_lock(&mchdev_lock); |
f97108d1 | 950 | |
73edd18f DV |
951 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
952 | ||
20e4d407 | 953 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 954 | |
7648fa99 | 955 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
956 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
957 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
958 | max_avg = I915_READ(RCBMAXAVG); |
959 | min_avg = I915_READ(RCBMINAVG); | |
960 | ||
961 | /* Handle RCS change request from hw */ | |
b5b72e89 | 962 | if (busy_up > max_avg) { |
20e4d407 DV |
963 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
964 | new_delay = dev_priv->ips.cur_delay - 1; | |
965 | if (new_delay < dev_priv->ips.max_delay) | |
966 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 967 | } else if (busy_down < min_avg) { |
20e4d407 DV |
968 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
969 | new_delay = dev_priv->ips.cur_delay + 1; | |
970 | if (new_delay > dev_priv->ips.min_delay) | |
971 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
972 | } |
973 | ||
7648fa99 | 974 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 975 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 976 | |
d0ecd7e2 | 977 | spin_unlock(&mchdev_lock); |
9270388e | 978 | |
f97108d1 JB |
979 | return; |
980 | } | |
981 | ||
549f7365 | 982 | static void notify_ring(struct drm_device *dev, |
a4872ba6 | 983 | struct intel_engine_cs *ring) |
549f7365 | 984 | { |
93b0a4e0 | 985 | if (!intel_ring_initialized(ring)) |
475553de CW |
986 | return; |
987 | ||
814e9b57 | 988 | trace_i915_gem_request_complete(ring); |
9862e600 | 989 | |
549f7365 | 990 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 991 | i915_queue_hangcheck(dev); |
549f7365 CW |
992 | } |
993 | ||
31685c25 | 994 | static u32 vlv_c0_residency(struct drm_i915_private *dev_priv, |
bf225f20 | 995 | struct intel_rps_ei *rps_ei) |
31685c25 D |
996 | { |
997 | u32 cz_ts, cz_freq_khz; | |
998 | u32 render_count, media_count; | |
999 | u32 elapsed_render, elapsed_media, elapsed_time; | |
1000 | u32 residency = 0; | |
1001 | ||
1002 | cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); | |
1003 | cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4); | |
1004 | ||
1005 | render_count = I915_READ(VLV_RENDER_C0_COUNT_REG); | |
1006 | media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG); | |
1007 | ||
bf225f20 CW |
1008 | if (rps_ei->cz_clock == 0) { |
1009 | rps_ei->cz_clock = cz_ts; | |
1010 | rps_ei->render_c0 = render_count; | |
1011 | rps_ei->media_c0 = media_count; | |
31685c25 D |
1012 | |
1013 | return dev_priv->rps.cur_freq; | |
1014 | } | |
1015 | ||
bf225f20 CW |
1016 | elapsed_time = cz_ts - rps_ei->cz_clock; |
1017 | rps_ei->cz_clock = cz_ts; | |
31685c25 | 1018 | |
bf225f20 CW |
1019 | elapsed_render = render_count - rps_ei->render_c0; |
1020 | rps_ei->render_c0 = render_count; | |
31685c25 | 1021 | |
bf225f20 CW |
1022 | elapsed_media = media_count - rps_ei->media_c0; |
1023 | rps_ei->media_c0 = media_count; | |
31685c25 D |
1024 | |
1025 | /* Convert all the counters into common unit of milli sec */ | |
1026 | elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC; | |
1027 | elapsed_render /= cz_freq_khz; | |
1028 | elapsed_media /= cz_freq_khz; | |
1029 | ||
1030 | /* | |
1031 | * Calculate overall C0 residency percentage | |
1032 | * only if elapsed time is non zero | |
1033 | */ | |
1034 | if (elapsed_time) { | |
1035 | residency = | |
1036 | ((max(elapsed_render, elapsed_media) * 100) | |
1037 | / elapsed_time); | |
1038 | } | |
1039 | ||
1040 | return residency; | |
1041 | } | |
1042 | ||
1043 | /** | |
1044 | * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU | |
1045 | * busy-ness calculated from C0 counters of render & media power wells | |
1046 | * @dev_priv: DRM device private | |
1047 | * | |
1048 | */ | |
4fa79042 | 1049 | static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv) |
31685c25 D |
1050 | { |
1051 | u32 residency_C0_up = 0, residency_C0_down = 0; | |
4fa79042 | 1052 | int new_delay, adj; |
31685c25 D |
1053 | |
1054 | dev_priv->rps.ei_interrupt_count++; | |
1055 | ||
1056 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
1057 | ||
1058 | ||
bf225f20 CW |
1059 | if (dev_priv->rps.up_ei.cz_clock == 0) { |
1060 | vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei); | |
1061 | vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei); | |
31685c25 D |
1062 | return dev_priv->rps.cur_freq; |
1063 | } | |
1064 | ||
1065 | ||
1066 | /* | |
1067 | * To down throttle, C0 residency should be less than down threshold | |
1068 | * for continous EI intervals. So calculate down EI counters | |
1069 | * once in VLV_INT_COUNT_FOR_DOWN_EI | |
1070 | */ | |
1071 | if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) { | |
1072 | ||
1073 | dev_priv->rps.ei_interrupt_count = 0; | |
1074 | ||
1075 | residency_C0_down = vlv_c0_residency(dev_priv, | |
bf225f20 | 1076 | &dev_priv->rps.down_ei); |
31685c25 D |
1077 | } else { |
1078 | residency_C0_up = vlv_c0_residency(dev_priv, | |
bf225f20 | 1079 | &dev_priv->rps.up_ei); |
31685c25 D |
1080 | } |
1081 | ||
1082 | new_delay = dev_priv->rps.cur_freq; | |
1083 | ||
1084 | adj = dev_priv->rps.last_adj; | |
1085 | /* C0 residency is greater than UP threshold. Increase Frequency */ | |
1086 | if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) { | |
1087 | if (adj > 0) | |
1088 | adj *= 2; | |
1089 | else | |
1090 | adj = 1; | |
1091 | ||
1092 | if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit) | |
1093 | new_delay = dev_priv->rps.cur_freq + adj; | |
1094 | ||
1095 | /* | |
1096 | * For better performance, jump directly | |
1097 | * to RPe if we're below it. | |
1098 | */ | |
1099 | if (new_delay < dev_priv->rps.efficient_freq) | |
1100 | new_delay = dev_priv->rps.efficient_freq; | |
1101 | ||
1102 | } else if (!dev_priv->rps.ei_interrupt_count && | |
1103 | (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) { | |
1104 | if (adj < 0) | |
1105 | adj *= 2; | |
1106 | else | |
1107 | adj = -1; | |
1108 | /* | |
1109 | * This means, C0 residency is less than down threshold over | |
1110 | * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq | |
1111 | */ | |
1112 | if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit) | |
1113 | new_delay = dev_priv->rps.cur_freq + adj; | |
1114 | } | |
1115 | ||
1116 | return new_delay; | |
1117 | } | |
1118 | ||
4912d041 | 1119 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1120 | { |
2d1013dd JN |
1121 | struct drm_i915_private *dev_priv = |
1122 | container_of(work, struct drm_i915_private, rps.work); | |
edbfdb45 | 1123 | u32 pm_iir; |
dd75fdc8 | 1124 | int new_delay, adj; |
4912d041 | 1125 | |
59cdb63d | 1126 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
1127 | pm_iir = dev_priv->rps.pm_iir; |
1128 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a ID |
1129 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
1130 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
59cdb63d | 1131 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1132 | |
60611c13 | 1133 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1134 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1135 | |
a6706b45 | 1136 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
3b8d8d91 JB |
1137 | return; |
1138 | ||
4fc688ce | 1139 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1140 | |
dd75fdc8 | 1141 | adj = dev_priv->rps.last_adj; |
7425034a | 1142 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1143 | if (adj > 0) |
1144 | adj *= 2; | |
13a5660c D |
1145 | else { |
1146 | /* CHV needs even encode values */ | |
1147 | adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1; | |
1148 | } | |
b39fb297 | 1149 | new_delay = dev_priv->rps.cur_freq + adj; |
7425034a VS |
1150 | |
1151 | /* | |
1152 | * For better performance, jump directly | |
1153 | * to RPe if we're below it. | |
1154 | */ | |
b39fb297 BW |
1155 | if (new_delay < dev_priv->rps.efficient_freq) |
1156 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1157 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1158 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1159 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1160 | else |
b39fb297 | 1161 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 | 1162 | adj = 0; |
31685c25 D |
1163 | } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1164 | new_delay = vlv_calc_delay_from_C0_counters(dev_priv); | |
dd75fdc8 CW |
1165 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { |
1166 | if (adj < 0) | |
1167 | adj *= 2; | |
13a5660c D |
1168 | else { |
1169 | /* CHV needs even encode values */ | |
1170 | adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1; | |
1171 | } | |
b39fb297 | 1172 | new_delay = dev_priv->rps.cur_freq + adj; |
dd75fdc8 | 1173 | } else { /* unknown event */ |
b39fb297 | 1174 | new_delay = dev_priv->rps.cur_freq; |
dd75fdc8 | 1175 | } |
3b8d8d91 | 1176 | |
79249636 BW |
1177 | /* sysfs frequency interfaces may have snuck in while servicing the |
1178 | * interrupt | |
1179 | */ | |
1272e7b8 | 1180 | new_delay = clamp_t(int, new_delay, |
b39fb297 BW |
1181 | dev_priv->rps.min_freq_softlimit, |
1182 | dev_priv->rps.max_freq_softlimit); | |
27544369 | 1183 | |
b39fb297 | 1184 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
dd75fdc8 CW |
1185 | |
1186 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1187 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1188 | else | |
1189 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1190 | |
4fc688ce | 1191 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1192 | } |
1193 | ||
e3689190 BW |
1194 | |
1195 | /** | |
1196 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1197 | * occurred. | |
1198 | * @work: workqueue struct | |
1199 | * | |
1200 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1201 | * this event, userspace should try to remap the bad rows since statistically | |
1202 | * it is likely the same row is more likely to go bad again. | |
1203 | */ | |
1204 | static void ivybridge_parity_work(struct work_struct *work) | |
1205 | { | |
2d1013dd JN |
1206 | struct drm_i915_private *dev_priv = |
1207 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1208 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1209 | char *parity_event[6]; |
e3689190 | 1210 | uint32_t misccpctl; |
35a85ac6 | 1211 | uint8_t slice = 0; |
e3689190 BW |
1212 | |
1213 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1214 | * In order to prevent a get/put style interface, acquire struct mutex | |
1215 | * any time we access those registers. | |
1216 | */ | |
1217 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1218 | ||
35a85ac6 BW |
1219 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1220 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1221 | goto out; | |
1222 | ||
e3689190 BW |
1223 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1224 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1225 | POSTING_READ(GEN7_MISCCPCTL); | |
1226 | ||
35a85ac6 BW |
1227 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1228 | u32 reg; | |
e3689190 | 1229 | |
35a85ac6 BW |
1230 | slice--; |
1231 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1232 | break; | |
e3689190 | 1233 | |
35a85ac6 | 1234 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1235 | |
35a85ac6 | 1236 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1237 | |
35a85ac6 BW |
1238 | error_status = I915_READ(reg); |
1239 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1240 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1241 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1242 | ||
1243 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1244 | POSTING_READ(reg); | |
1245 | ||
1246 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1247 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1248 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1249 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1250 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1251 | parity_event[5] = NULL; | |
1252 | ||
5bdebb18 | 1253 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1254 | KOBJ_CHANGE, parity_event); |
e3689190 | 1255 | |
35a85ac6 BW |
1256 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1257 | slice, row, bank, subbank); | |
e3689190 | 1258 | |
35a85ac6 BW |
1259 | kfree(parity_event[4]); |
1260 | kfree(parity_event[3]); | |
1261 | kfree(parity_event[2]); | |
1262 | kfree(parity_event[1]); | |
1263 | } | |
e3689190 | 1264 | |
35a85ac6 | 1265 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1266 | |
35a85ac6 BW |
1267 | out: |
1268 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1269 | spin_lock_irq(&dev_priv->irq_lock); |
480c8033 | 1270 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
4cb21832 | 1271 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1272 | |
1273 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1274 | } |
1275 | ||
35a85ac6 | 1276 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1277 | { |
2d1013dd | 1278 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1279 | |
040d2baa | 1280 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1281 | return; |
1282 | ||
d0ecd7e2 | 1283 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1284 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1285 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1286 | |
35a85ac6 BW |
1287 | iir &= GT_PARITY_ERROR(dev); |
1288 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1289 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1290 | ||
1291 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1292 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1293 | ||
a4da4fa4 | 1294 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1295 | } |
1296 | ||
f1af8fc1 PZ |
1297 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1298 | struct drm_i915_private *dev_priv, | |
1299 | u32 gt_iir) | |
1300 | { | |
1301 | if (gt_iir & | |
1302 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1303 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1304 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1305 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1306 | } | |
1307 | ||
e7b4c6b1 DV |
1308 | static void snb_gt_irq_handler(struct drm_device *dev, |
1309 | struct drm_i915_private *dev_priv, | |
1310 | u32 gt_iir) | |
1311 | { | |
1312 | ||
cc609d5d BW |
1313 | if (gt_iir & |
1314 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1315 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1316 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1317 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1318 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1319 | notify_ring(dev, &dev_priv->ring[BCS]); |
1320 | ||
cc609d5d BW |
1321 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1322 | GT_BSD_CS_ERROR_INTERRUPT | | |
1323 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
58174462 MK |
1324 | i915_handle_error(dev, false, "GT error interrupt 0x%08x", |
1325 | gt_iir); | |
e7b4c6b1 | 1326 | } |
e3689190 | 1327 | |
35a85ac6 BW |
1328 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1329 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1330 | } |
1331 | ||
abd58f01 BW |
1332 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1333 | struct drm_i915_private *dev_priv, | |
1334 | u32 master_ctl) | |
1335 | { | |
e981e7b1 | 1336 | struct intel_engine_cs *ring; |
abd58f01 BW |
1337 | u32 rcs, bcs, vcs; |
1338 | uint32_t tmp = 0; | |
1339 | irqreturn_t ret = IRQ_NONE; | |
1340 | ||
1341 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1342 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1343 | if (tmp) { | |
38cc46d7 | 1344 | I915_WRITE(GEN8_GT_IIR(0), tmp); |
abd58f01 | 1345 | ret = IRQ_HANDLED; |
e981e7b1 | 1346 | |
abd58f01 | 1347 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; |
e981e7b1 | 1348 | ring = &dev_priv->ring[RCS]; |
abd58f01 | 1349 | if (rcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 TD |
1350 | notify_ring(dev, ring); |
1351 | if (rcs & GT_CONTEXT_SWITCH_INTERRUPT) | |
1352 | intel_execlists_handle_ctx_events(ring); | |
1353 | ||
1354 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1355 | ring = &dev_priv->ring[BCS]; | |
abd58f01 | 1356 | if (bcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 TD |
1357 | notify_ring(dev, ring); |
1358 | if (bcs & GT_CONTEXT_SWITCH_INTERRUPT) | |
1359 | intel_execlists_handle_ctx_events(ring); | |
abd58f01 BW |
1360 | } else |
1361 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1362 | } | |
1363 | ||
85f9b5f9 | 1364 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
abd58f01 BW |
1365 | tmp = I915_READ(GEN8_GT_IIR(1)); |
1366 | if (tmp) { | |
38cc46d7 | 1367 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
abd58f01 | 1368 | ret = IRQ_HANDLED; |
e981e7b1 | 1369 | |
abd58f01 | 1370 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; |
e981e7b1 | 1371 | ring = &dev_priv->ring[VCS]; |
abd58f01 | 1372 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1373 | notify_ring(dev, ring); |
73d477f6 | 1374 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 TD |
1375 | intel_execlists_handle_ctx_events(ring); |
1376 | ||
85f9b5f9 | 1377 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
e981e7b1 | 1378 | ring = &dev_priv->ring[VCS2]; |
85f9b5f9 | 1379 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1380 | notify_ring(dev, ring); |
73d477f6 | 1381 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 | 1382 | intel_execlists_handle_ctx_events(ring); |
abd58f01 BW |
1383 | } else |
1384 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1385 | } | |
1386 | ||
0961021a BW |
1387 | if (master_ctl & GEN8_GT_PM_IRQ) { |
1388 | tmp = I915_READ(GEN8_GT_IIR(2)); | |
1389 | if (tmp & dev_priv->pm_rps_events) { | |
0961021a BW |
1390 | I915_WRITE(GEN8_GT_IIR(2), |
1391 | tmp & dev_priv->pm_rps_events); | |
38cc46d7 | 1392 | ret = IRQ_HANDLED; |
c9a9a268 | 1393 | gen6_rps_irq_handler(dev_priv, tmp); |
0961021a BW |
1394 | } else |
1395 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1396 | } | |
1397 | ||
abd58f01 BW |
1398 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
1399 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1400 | if (tmp) { | |
38cc46d7 | 1401 | I915_WRITE(GEN8_GT_IIR(3), tmp); |
abd58f01 | 1402 | ret = IRQ_HANDLED; |
e981e7b1 | 1403 | |
abd58f01 | 1404 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; |
e981e7b1 | 1405 | ring = &dev_priv->ring[VECS]; |
abd58f01 | 1406 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1407 | notify_ring(dev, ring); |
73d477f6 | 1408 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 | 1409 | intel_execlists_handle_ctx_events(ring); |
abd58f01 BW |
1410 | } else |
1411 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1412 | } | |
1413 | ||
1414 | return ret; | |
1415 | } | |
1416 | ||
b543fb04 EE |
1417 | #define HPD_STORM_DETECT_PERIOD 1000 |
1418 | #define HPD_STORM_THRESHOLD 5 | |
1419 | ||
07c338ce | 1420 | static int pch_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1421 | { |
1422 | switch (port) { | |
1423 | case PORT_A: | |
1424 | case PORT_E: | |
1425 | default: | |
1426 | return -1; | |
1427 | case PORT_B: | |
1428 | return 0; | |
1429 | case PORT_C: | |
1430 | return 8; | |
1431 | case PORT_D: | |
1432 | return 16; | |
1433 | } | |
1434 | } | |
1435 | ||
07c338ce | 1436 | static int i915_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1437 | { |
1438 | switch (port) { | |
1439 | case PORT_A: | |
1440 | case PORT_E: | |
1441 | default: | |
1442 | return -1; | |
1443 | case PORT_B: | |
1444 | return 17; | |
1445 | case PORT_C: | |
1446 | return 19; | |
1447 | case PORT_D: | |
1448 | return 21; | |
1449 | } | |
1450 | } | |
1451 | ||
1452 | static inline enum port get_port_from_pin(enum hpd_pin pin) | |
1453 | { | |
1454 | switch (pin) { | |
1455 | case HPD_PORT_B: | |
1456 | return PORT_B; | |
1457 | case HPD_PORT_C: | |
1458 | return PORT_C; | |
1459 | case HPD_PORT_D: | |
1460 | return PORT_D; | |
1461 | default: | |
1462 | return PORT_A; /* no hpd */ | |
1463 | } | |
1464 | } | |
1465 | ||
10a504de | 1466 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba | 1467 | u32 hotplug_trigger, |
13cf5504 | 1468 | u32 dig_hotplug_reg, |
22062dba | 1469 | const u32 *hpd) |
b543fb04 | 1470 | { |
2d1013dd | 1471 | struct drm_i915_private *dev_priv = dev->dev_private; |
b543fb04 | 1472 | int i; |
13cf5504 | 1473 | enum port port; |
10a504de | 1474 | bool storm_detected = false; |
13cf5504 DA |
1475 | bool queue_dig = false, queue_hp = false; |
1476 | u32 dig_shift; | |
1477 | u32 dig_port_mask = 0; | |
b543fb04 | 1478 | |
91d131d2 DV |
1479 | if (!hotplug_trigger) |
1480 | return; | |
1481 | ||
13cf5504 DA |
1482 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n", |
1483 | hotplug_trigger, dig_hotplug_reg); | |
cc9bd499 | 1484 | |
b5ea2d56 | 1485 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1486 | for (i = 1; i < HPD_NUM_PINS; i++) { |
13cf5504 DA |
1487 | if (!(hpd[i] & hotplug_trigger)) |
1488 | continue; | |
1489 | ||
1490 | port = get_port_from_pin(i); | |
1491 | if (port && dev_priv->hpd_irq_port[port]) { | |
1492 | bool long_hpd; | |
1493 | ||
07c338ce JN |
1494 | if (HAS_PCH_SPLIT(dev)) { |
1495 | dig_shift = pch_port_to_hotplug_shift(port); | |
13cf5504 | 1496 | long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; |
07c338ce JN |
1497 | } else { |
1498 | dig_shift = i915_port_to_hotplug_shift(port); | |
1499 | long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; | |
13cf5504 DA |
1500 | } |
1501 | ||
26fbb774 VS |
1502 | DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", |
1503 | port_name(port), | |
1504 | long_hpd ? "long" : "short"); | |
13cf5504 DA |
1505 | /* for long HPD pulses we want to have the digital queue happen, |
1506 | but we still want HPD storm detection to function. */ | |
1507 | if (long_hpd) { | |
1508 | dev_priv->long_hpd_port_mask |= (1 << port); | |
1509 | dig_port_mask |= hpd[i]; | |
1510 | } else { | |
1511 | /* for short HPD just trigger the digital queue */ | |
1512 | dev_priv->short_hpd_port_mask |= (1 << port); | |
1513 | hotplug_trigger &= ~hpd[i]; | |
1514 | } | |
1515 | queue_dig = true; | |
1516 | } | |
1517 | } | |
821450c6 | 1518 | |
13cf5504 | 1519 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3ff04a16 DV |
1520 | if (hpd[i] & hotplug_trigger && |
1521 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { | |
1522 | /* | |
1523 | * On GMCH platforms the interrupt mask bits only | |
1524 | * prevent irq generation, not the setting of the | |
1525 | * hotplug bits itself. So only WARN about unexpected | |
1526 | * interrupts on saner platforms. | |
1527 | */ | |
1528 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), | |
1529 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | |
1530 | hotplug_trigger, i, hpd[i]); | |
1531 | ||
1532 | continue; | |
1533 | } | |
b8f102e8 | 1534 | |
b543fb04 EE |
1535 | if (!(hpd[i] & hotplug_trigger) || |
1536 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1537 | continue; | |
1538 | ||
13cf5504 DA |
1539 | if (!(dig_port_mask & hpd[i])) { |
1540 | dev_priv->hpd_event_bits |= (1 << i); | |
1541 | queue_hp = true; | |
1542 | } | |
1543 | ||
b543fb04 EE |
1544 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1545 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1546 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1547 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1548 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1549 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1550 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1551 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1552 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1553 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1554 | storm_detected = true; |
b543fb04 EE |
1555 | } else { |
1556 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1557 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1558 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1559 | } |
1560 | } | |
1561 | ||
10a504de DV |
1562 | if (storm_detected) |
1563 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1564 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1565 | |
645416f5 DV |
1566 | /* |
1567 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1568 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1569 | * queue for otherwise the flush_work in the pageflip code will | |
1570 | * deadlock. | |
1571 | */ | |
13cf5504 | 1572 | if (queue_dig) |
0e32b39c | 1573 | queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work); |
13cf5504 DA |
1574 | if (queue_hp) |
1575 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1576 | } |
1577 | ||
515ac2bb DV |
1578 | static void gmbus_irq_handler(struct drm_device *dev) |
1579 | { | |
2d1013dd | 1580 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1581 | |
28c70f16 | 1582 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1583 | } |
1584 | ||
ce99c256 DV |
1585 | static void dp_aux_irq_handler(struct drm_device *dev) |
1586 | { | |
2d1013dd | 1587 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1588 | |
9ee32fea | 1589 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1590 | } |
1591 | ||
8bf1e9f1 | 1592 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1593 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1594 | uint32_t crc0, uint32_t crc1, | |
1595 | uint32_t crc2, uint32_t crc3, | |
1596 | uint32_t crc4) | |
8bf1e9f1 SH |
1597 | { |
1598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1599 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1600 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1601 | int head, tail; |
b2c88f5b | 1602 | |
d538bbdf DL |
1603 | spin_lock(&pipe_crc->lock); |
1604 | ||
0c912c79 | 1605 | if (!pipe_crc->entries) { |
d538bbdf | 1606 | spin_unlock(&pipe_crc->lock); |
0c912c79 DL |
1607 | DRM_ERROR("spurious interrupt\n"); |
1608 | return; | |
1609 | } | |
1610 | ||
d538bbdf DL |
1611 | head = pipe_crc->head; |
1612 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1613 | |
1614 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1615 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1616 | DRM_ERROR("CRC buffer overflowing\n"); |
1617 | return; | |
1618 | } | |
1619 | ||
1620 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1621 | |
8bc5e955 | 1622 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1623 | entry->crc[0] = crc0; |
1624 | entry->crc[1] = crc1; | |
1625 | entry->crc[2] = crc2; | |
1626 | entry->crc[3] = crc3; | |
1627 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1628 | |
1629 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1630 | pipe_crc->head = head; |
1631 | ||
1632 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1633 | |
1634 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1635 | } |
277de95e DV |
1636 | #else |
1637 | static inline void | |
1638 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1639 | uint32_t crc0, uint32_t crc1, | |
1640 | uint32_t crc2, uint32_t crc3, | |
1641 | uint32_t crc4) {} | |
1642 | #endif | |
1643 | ||
eba94eb9 | 1644 | |
277de95e | 1645 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1646 | { |
1647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1648 | ||
277de95e DV |
1649 | display_pipe_crc_irq_handler(dev, pipe, |
1650 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1651 | 0, 0, 0, 0); | |
5a69b89f DV |
1652 | } |
1653 | ||
277de95e | 1654 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1655 | { |
1656 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1657 | ||
277de95e DV |
1658 | display_pipe_crc_irq_handler(dev, pipe, |
1659 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1660 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1661 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1662 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1663 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1664 | } |
5b3a856b | 1665 | |
277de95e | 1666 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1667 | { |
1668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1669 | uint32_t res1, res2; |
1670 | ||
1671 | if (INTEL_INFO(dev)->gen >= 3) | |
1672 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1673 | else | |
1674 | res1 = 0; | |
1675 | ||
1676 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1677 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1678 | else | |
1679 | res2 = 0; | |
5b3a856b | 1680 | |
277de95e DV |
1681 | display_pipe_crc_irq_handler(dev, pipe, |
1682 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1683 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1684 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1685 | res1, res2); | |
5b3a856b | 1686 | } |
8bf1e9f1 | 1687 | |
1403c0d4 PZ |
1688 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1689 | * IMR bits until the work is done. Other interrupts can be processed without | |
1690 | * the work queue. */ | |
1691 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1692 | { |
132f3f17 ID |
1693 | /* TODO: RPS on GEN9 is not supported yet. */ |
1694 | if (WARN_ONCE(INTEL_INFO(dev_priv)->gen == 9, | |
1695 | "GEN9: unexpected RPS IRQ\n")) | |
1696 | return; | |
1697 | ||
a6706b45 | 1698 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1699 | spin_lock(&dev_priv->irq_lock); |
a6706b45 | 1700 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; |
480c8033 | 1701 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
59cdb63d | 1702 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1703 | |
1704 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1705 | } |
baf02a1f | 1706 | |
c9a9a268 ID |
1707 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1708 | return; | |
1709 | ||
1403c0d4 PZ |
1710 | if (HAS_VEBOX(dev_priv->dev)) { |
1711 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1712 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1713 | |
1403c0d4 | 1714 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
58174462 MK |
1715 | i915_handle_error(dev_priv->dev, false, |
1716 | "VEBOX CS error interrupt 0x%08x", | |
1717 | pm_iir); | |
1403c0d4 | 1718 | } |
12638c57 | 1719 | } |
baf02a1f BW |
1720 | } |
1721 | ||
8d7849db VS |
1722 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1723 | { | |
8d7849db VS |
1724 | if (!drm_handle_vblank(dev, pipe)) |
1725 | return false; | |
1726 | ||
8d7849db VS |
1727 | return true; |
1728 | } | |
1729 | ||
c1874ed7 ID |
1730 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1731 | { | |
1732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1733 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1734 | int pipe; |
1735 | ||
58ead0d7 | 1736 | spin_lock(&dev_priv->irq_lock); |
055e393f | 1737 | for_each_pipe(dev_priv, pipe) { |
91d181dd | 1738 | int reg; |
bbb5eebf | 1739 | u32 mask, iir_bit = 0; |
91d181dd | 1740 | |
bbb5eebf DV |
1741 | /* |
1742 | * PIPESTAT bits get signalled even when the interrupt is | |
1743 | * disabled with the mask bits, and some of the status bits do | |
1744 | * not generate interrupts at all (like the underrun bit). Hence | |
1745 | * we need to be careful that we only handle what we want to | |
1746 | * handle. | |
1747 | */ | |
0f239f4c DV |
1748 | |
1749 | /* fifo underruns are filterered in the underrun handler. */ | |
1750 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1751 | |
1752 | switch (pipe) { | |
1753 | case PIPE_A: | |
1754 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1755 | break; | |
1756 | case PIPE_B: | |
1757 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1758 | break; | |
3278f67f VS |
1759 | case PIPE_C: |
1760 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1761 | break; | |
bbb5eebf DV |
1762 | } |
1763 | if (iir & iir_bit) | |
1764 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1765 | ||
1766 | if (!mask) | |
91d181dd ID |
1767 | continue; |
1768 | ||
1769 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1770 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1771 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1772 | |
1773 | /* | |
1774 | * Clear the PIPE*STAT regs before the IIR | |
1775 | */ | |
91d181dd ID |
1776 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1777 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1778 | I915_WRITE(reg, pipe_stats[pipe]); |
1779 | } | |
58ead0d7 | 1780 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 | 1781 | |
055e393f | 1782 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1783 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1784 | intel_pipe_handle_vblank(dev, pipe)) | |
1785 | intel_check_page_flip(dev, pipe); | |
c1874ed7 | 1786 | |
579a9b0e | 1787 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1788 | intel_prepare_page_flip(dev, pipe); |
1789 | intel_finish_page_flip(dev, pipe); | |
1790 | } | |
1791 | ||
1792 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1793 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1794 | ||
1f7247c0 DV |
1795 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1796 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1797 | } |
1798 | ||
1799 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1800 | gmbus_irq_handler(dev); | |
1801 | } | |
1802 | ||
16c6c56b VS |
1803 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1804 | { | |
1805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1806 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1807 | ||
3ff60f89 OM |
1808 | if (hotplug_status) { |
1809 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1810 | /* | |
1811 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1812 | * may miss hotplug events. | |
1813 | */ | |
1814 | POSTING_READ(PORT_HOTPLUG_STAT); | |
16c6c56b | 1815 | |
3ff60f89 OM |
1816 | if (IS_G4X(dev)) { |
1817 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
16c6c56b | 1818 | |
13cf5504 | 1819 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x); |
3ff60f89 OM |
1820 | } else { |
1821 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1822 | |
13cf5504 | 1823 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915); |
3ff60f89 | 1824 | } |
16c6c56b | 1825 | |
3ff60f89 OM |
1826 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && |
1827 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1828 | dp_aux_irq_handler(dev); | |
1829 | } | |
16c6c56b VS |
1830 | } |
1831 | ||
ff1f525e | 1832 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1833 | { |
45a83f84 | 1834 | struct drm_device *dev = arg; |
2d1013dd | 1835 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1836 | u32 iir, gt_iir, pm_iir; |
1837 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1838 | |
7e231dbe | 1839 | while (true) { |
3ff60f89 OM |
1840 | /* Find, clear, then process each source of interrupt */ |
1841 | ||
7e231dbe | 1842 | gt_iir = I915_READ(GTIIR); |
3ff60f89 OM |
1843 | if (gt_iir) |
1844 | I915_WRITE(GTIIR, gt_iir); | |
1845 | ||
7e231dbe | 1846 | pm_iir = I915_READ(GEN6_PMIIR); |
3ff60f89 OM |
1847 | if (pm_iir) |
1848 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1849 | ||
1850 | iir = I915_READ(VLV_IIR); | |
1851 | if (iir) { | |
1852 | /* Consume port before clearing IIR or we'll miss events */ | |
1853 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1854 | i9xx_hpd_irq_handler(dev); | |
1855 | I915_WRITE(VLV_IIR, iir); | |
1856 | } | |
7e231dbe JB |
1857 | |
1858 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1859 | goto out; | |
1860 | ||
1861 | ret = IRQ_HANDLED; | |
1862 | ||
3ff60f89 OM |
1863 | if (gt_iir) |
1864 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
60611c13 | 1865 | if (pm_iir) |
d0ecd7e2 | 1866 | gen6_rps_irq_handler(dev_priv, pm_iir); |
3ff60f89 OM |
1867 | /* Call regardless, as some status bits might not be |
1868 | * signalled in iir */ | |
1869 | valleyview_pipestat_irq_handler(dev, iir); | |
7e231dbe JB |
1870 | } |
1871 | ||
1872 | out: | |
1873 | return ret; | |
1874 | } | |
1875 | ||
43f328d7 VS |
1876 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1877 | { | |
45a83f84 | 1878 | struct drm_device *dev = arg; |
43f328d7 VS |
1879 | struct drm_i915_private *dev_priv = dev->dev_private; |
1880 | u32 master_ctl, iir; | |
1881 | irqreturn_t ret = IRQ_NONE; | |
43f328d7 | 1882 | |
8e5fd599 VS |
1883 | for (;;) { |
1884 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; | |
1885 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1886 | |
8e5fd599 VS |
1887 | if (master_ctl == 0 && iir == 0) |
1888 | break; | |
43f328d7 | 1889 | |
27b6c122 OM |
1890 | ret = IRQ_HANDLED; |
1891 | ||
8e5fd599 | 1892 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
43f328d7 | 1893 | |
27b6c122 | 1894 | /* Find, clear, then process each source of interrupt */ |
43f328d7 | 1895 | |
27b6c122 OM |
1896 | if (iir) { |
1897 | /* Consume port before clearing IIR or we'll miss events */ | |
1898 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1899 | i9xx_hpd_irq_handler(dev); | |
1900 | I915_WRITE(VLV_IIR, iir); | |
1901 | } | |
43f328d7 | 1902 | |
27b6c122 | 1903 | gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
43f328d7 | 1904 | |
27b6c122 OM |
1905 | /* Call regardless, as some status bits might not be |
1906 | * signalled in iir */ | |
1907 | valleyview_pipestat_irq_handler(dev, iir); | |
43f328d7 | 1908 | |
8e5fd599 VS |
1909 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
1910 | POSTING_READ(GEN8_MASTER_IRQ); | |
8e5fd599 | 1911 | } |
3278f67f | 1912 | |
43f328d7 VS |
1913 | return ret; |
1914 | } | |
1915 | ||
23e81d69 | 1916 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1917 | { |
2d1013dd | 1918 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1919 | int pipe; |
b543fb04 | 1920 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 DA |
1921 | u32 dig_hotplug_reg; |
1922 | ||
1923 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1924 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
776ad806 | 1925 | |
13cf5504 | 1926 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx); |
91d131d2 | 1927 | |
cfc33bf7 VS |
1928 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1929 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1930 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1931 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1932 | port_name(port)); |
1933 | } | |
776ad806 | 1934 | |
ce99c256 DV |
1935 | if (pch_iir & SDE_AUX_MASK) |
1936 | dp_aux_irq_handler(dev); | |
1937 | ||
776ad806 | 1938 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1939 | gmbus_irq_handler(dev); |
776ad806 JB |
1940 | |
1941 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1942 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1943 | ||
1944 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1945 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1946 | ||
1947 | if (pch_iir & SDE_POISON) | |
1948 | DRM_ERROR("PCH poison interrupt\n"); | |
1949 | ||
9db4a9c7 | 1950 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 1951 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
1952 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1953 | pipe_name(pipe), | |
1954 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1955 | |
1956 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1957 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1958 | ||
1959 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1960 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1961 | ||
776ad806 | 1962 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 1963 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1964 | |
1965 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 1966 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1967 | } |
1968 | ||
1969 | static void ivb_err_int_handler(struct drm_device *dev) | |
1970 | { | |
1971 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1972 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1973 | enum pipe pipe; |
8664281b | 1974 | |
de032bf4 PZ |
1975 | if (err_int & ERR_INT_POISON) |
1976 | DRM_ERROR("Poison interrupt\n"); | |
1977 | ||
055e393f | 1978 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
1979 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
1980 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 1981 | |
5a69b89f DV |
1982 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1983 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1984 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1985 | else |
277de95e | 1986 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1987 | } |
1988 | } | |
8bf1e9f1 | 1989 | |
8664281b PZ |
1990 | I915_WRITE(GEN7_ERR_INT, err_int); |
1991 | } | |
1992 | ||
1993 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1994 | { | |
1995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1996 | u32 serr_int = I915_READ(SERR_INT); | |
1997 | ||
de032bf4 PZ |
1998 | if (serr_int & SERR_INT_POISON) |
1999 | DRM_ERROR("PCH poison interrupt\n"); | |
2000 | ||
8664281b | 2001 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 2002 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2003 | |
2004 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 2005 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2006 | |
2007 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 2008 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
2009 | |
2010 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
2011 | } |
2012 | ||
23e81d69 AJ |
2013 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
2014 | { | |
2d1013dd | 2015 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 2016 | int pipe; |
b543fb04 | 2017 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 DA |
2018 | u32 dig_hotplug_reg; |
2019 | ||
2020 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
2021 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
23e81d69 | 2022 | |
13cf5504 | 2023 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt); |
91d131d2 | 2024 | |
cfc33bf7 VS |
2025 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
2026 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
2027 | SDE_AUDIO_POWER_SHIFT_CPT); | |
2028 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
2029 | port_name(port)); | |
2030 | } | |
23e81d69 AJ |
2031 | |
2032 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 2033 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
2034 | |
2035 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 2036 | gmbus_irq_handler(dev); |
23e81d69 AJ |
2037 | |
2038 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
2039 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
2040 | ||
2041 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
2042 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
2043 | ||
2044 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 2045 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
2046 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2047 | pipe_name(pipe), | |
2048 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
2049 | |
2050 | if (pch_iir & SDE_ERROR_CPT) | |
2051 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
2052 | } |
2053 | ||
c008bc6e PZ |
2054 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2055 | { | |
2056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 2057 | enum pipe pipe; |
c008bc6e PZ |
2058 | |
2059 | if (de_iir & DE_AUX_CHANNEL_A) | |
2060 | dp_aux_irq_handler(dev); | |
2061 | ||
2062 | if (de_iir & DE_GSE) | |
2063 | intel_opregion_asle_intr(dev); | |
2064 | ||
c008bc6e PZ |
2065 | if (de_iir & DE_POISON) |
2066 | DRM_ERROR("Poison interrupt\n"); | |
2067 | ||
055e393f | 2068 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2069 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2070 | intel_pipe_handle_vblank(dev, pipe)) | |
2071 | intel_check_page_flip(dev, pipe); | |
5b3a856b | 2072 | |
40da17c2 | 2073 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2074 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2075 | |
40da17c2 DV |
2076 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
2077 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 2078 | |
40da17c2 DV |
2079 | /* plane/pipes map 1:1 on ilk+ */ |
2080 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
2081 | intel_prepare_page_flip(dev, pipe); | |
2082 | intel_finish_page_flip_plane(dev, pipe); | |
2083 | } | |
c008bc6e PZ |
2084 | } |
2085 | ||
2086 | /* check event from PCH */ | |
2087 | if (de_iir & DE_PCH_EVENT) { | |
2088 | u32 pch_iir = I915_READ(SDEIIR); | |
2089 | ||
2090 | if (HAS_PCH_CPT(dev)) | |
2091 | cpt_irq_handler(dev, pch_iir); | |
2092 | else | |
2093 | ibx_irq_handler(dev, pch_iir); | |
2094 | ||
2095 | /* should clear PCH hotplug event before clear CPU irq */ | |
2096 | I915_WRITE(SDEIIR, pch_iir); | |
2097 | } | |
2098 | ||
2099 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
2100 | ironlake_rps_change_irq_handler(dev); | |
2101 | } | |
2102 | ||
9719fb98 PZ |
2103 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2104 | { | |
2105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 2106 | enum pipe pipe; |
9719fb98 PZ |
2107 | |
2108 | if (de_iir & DE_ERR_INT_IVB) | |
2109 | ivb_err_int_handler(dev); | |
2110 | ||
2111 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2112 | dp_aux_irq_handler(dev); | |
2113 | ||
2114 | if (de_iir & DE_GSE_IVB) | |
2115 | intel_opregion_asle_intr(dev); | |
2116 | ||
055e393f | 2117 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2118 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2119 | intel_pipe_handle_vblank(dev, pipe)) | |
2120 | intel_check_page_flip(dev, pipe); | |
40da17c2 DV |
2121 | |
2122 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2123 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2124 | intel_prepare_page_flip(dev, pipe); | |
2125 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2126 | } |
2127 | } | |
2128 | ||
2129 | /* check event from PCH */ | |
2130 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2131 | u32 pch_iir = I915_READ(SDEIIR); | |
2132 | ||
2133 | cpt_irq_handler(dev, pch_iir); | |
2134 | ||
2135 | /* clear PCH hotplug event before clear CPU irq */ | |
2136 | I915_WRITE(SDEIIR, pch_iir); | |
2137 | } | |
2138 | } | |
2139 | ||
72c90f62 OM |
2140 | /* |
2141 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2142 | * 1 - Disable Master Interrupt Control. | |
2143 | * 2 - Find the source(s) of the interrupt. | |
2144 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2145 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2146 | * 5 - Re-enable Master Interrupt Control. | |
2147 | */ | |
f1af8fc1 | 2148 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2149 | { |
45a83f84 | 2150 | struct drm_device *dev = arg; |
2d1013dd | 2151 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2152 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2153 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2154 | |
8664281b PZ |
2155 | /* We get interrupts on unclaimed registers, so check for this before we |
2156 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 2157 | intel_uncore_check_errors(dev); |
8664281b | 2158 | |
b1f14ad0 JB |
2159 | /* disable master interrupt before clearing iir */ |
2160 | de_ier = I915_READ(DEIER); | |
2161 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2162 | POSTING_READ(DEIER); |
b1f14ad0 | 2163 | |
44498aea PZ |
2164 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2165 | * interrupts will will be stored on its back queue, and then we'll be | |
2166 | * able to process them after we restore SDEIER (as soon as we restore | |
2167 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2168 | * due to its back queue). */ | |
ab5c608b BW |
2169 | if (!HAS_PCH_NOP(dev)) { |
2170 | sde_ier = I915_READ(SDEIER); | |
2171 | I915_WRITE(SDEIER, 0); | |
2172 | POSTING_READ(SDEIER); | |
2173 | } | |
44498aea | 2174 | |
72c90f62 OM |
2175 | /* Find, clear, then process each source of interrupt */ |
2176 | ||
b1f14ad0 | 2177 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2178 | if (gt_iir) { |
72c90f62 OM |
2179 | I915_WRITE(GTIIR, gt_iir); |
2180 | ret = IRQ_HANDLED; | |
d8fc8a47 | 2181 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 2182 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
2183 | else |
2184 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
b1f14ad0 JB |
2185 | } |
2186 | ||
0e43406b CW |
2187 | de_iir = I915_READ(DEIIR); |
2188 | if (de_iir) { | |
72c90f62 OM |
2189 | I915_WRITE(DEIIR, de_iir); |
2190 | ret = IRQ_HANDLED; | |
f1af8fc1 PZ |
2191 | if (INTEL_INFO(dev)->gen >= 7) |
2192 | ivb_display_irq_handler(dev, de_iir); | |
2193 | else | |
2194 | ilk_display_irq_handler(dev, de_iir); | |
b1f14ad0 JB |
2195 | } |
2196 | ||
f1af8fc1 PZ |
2197 | if (INTEL_INFO(dev)->gen >= 6) { |
2198 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2199 | if (pm_iir) { | |
f1af8fc1 PZ |
2200 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2201 | ret = IRQ_HANDLED; | |
72c90f62 | 2202 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2203 | } |
0e43406b | 2204 | } |
b1f14ad0 | 2205 | |
b1f14ad0 JB |
2206 | I915_WRITE(DEIER, de_ier); |
2207 | POSTING_READ(DEIER); | |
ab5c608b BW |
2208 | if (!HAS_PCH_NOP(dev)) { |
2209 | I915_WRITE(SDEIER, sde_ier); | |
2210 | POSTING_READ(SDEIER); | |
2211 | } | |
b1f14ad0 JB |
2212 | |
2213 | return ret; | |
2214 | } | |
2215 | ||
abd58f01 BW |
2216 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2217 | { | |
2218 | struct drm_device *dev = arg; | |
2219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2220 | u32 master_ctl; | |
2221 | irqreturn_t ret = IRQ_NONE; | |
2222 | uint32_t tmp = 0; | |
c42664cc | 2223 | enum pipe pipe; |
88e04703 JB |
2224 | u32 aux_mask = GEN8_AUX_CHANNEL_A; |
2225 | ||
2226 | if (IS_GEN9(dev)) | |
2227 | aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | | |
2228 | GEN9_AUX_CHANNEL_D; | |
abd58f01 | 2229 | |
abd58f01 BW |
2230 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
2231 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2232 | if (!master_ctl) | |
2233 | return IRQ_NONE; | |
2234 | ||
2235 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
2236 | POSTING_READ(GEN8_MASTER_IRQ); | |
2237 | ||
38cc46d7 OM |
2238 | /* Find, clear, then process each source of interrupt */ |
2239 | ||
abd58f01 BW |
2240 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
2241 | ||
2242 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2243 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
abd58f01 BW |
2244 | if (tmp) { |
2245 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2246 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2247 | if (tmp & GEN8_DE_MISC_GSE) |
2248 | intel_opregion_asle_intr(dev); | |
2249 | else | |
2250 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2251 | } |
38cc46d7 OM |
2252 | else |
2253 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2254 | } |
2255 | ||
6d766f02 DV |
2256 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2257 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
6d766f02 DV |
2258 | if (tmp) { |
2259 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
2260 | ret = IRQ_HANDLED; | |
88e04703 JB |
2261 | |
2262 | if (tmp & aux_mask) | |
38cc46d7 OM |
2263 | dp_aux_irq_handler(dev); |
2264 | else | |
2265 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
6d766f02 | 2266 | } |
38cc46d7 OM |
2267 | else |
2268 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2269 | } |
2270 | ||
055e393f | 2271 | for_each_pipe(dev_priv, pipe) { |
770de83d | 2272 | uint32_t pipe_iir, flip_done = 0, fault_errors = 0; |
abd58f01 | 2273 | |
c42664cc DV |
2274 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2275 | continue; | |
abd58f01 | 2276 | |
c42664cc | 2277 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
c42664cc DV |
2278 | if (pipe_iir) { |
2279 | ret = IRQ_HANDLED; | |
2280 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
770de83d | 2281 | |
d6bbafa1 CW |
2282 | if (pipe_iir & GEN8_PIPE_VBLANK && |
2283 | intel_pipe_handle_vblank(dev, pipe)) | |
2284 | intel_check_page_flip(dev, pipe); | |
38cc46d7 | 2285 | |
770de83d DL |
2286 | if (IS_GEN9(dev)) |
2287 | flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; | |
2288 | else | |
2289 | flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; | |
2290 | ||
2291 | if (flip_done) { | |
38cc46d7 OM |
2292 | intel_prepare_page_flip(dev, pipe); |
2293 | intel_finish_page_flip_plane(dev, pipe); | |
2294 | } | |
2295 | ||
2296 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) | |
2297 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2298 | ||
1f7247c0 DV |
2299 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) |
2300 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
2301 | pipe); | |
38cc46d7 | 2302 | |
770de83d DL |
2303 | |
2304 | if (IS_GEN9(dev)) | |
2305 | fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2306 | else | |
2307 | fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2308 | ||
2309 | if (fault_errors) | |
38cc46d7 OM |
2310 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
2311 | pipe_name(pipe), | |
2312 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
c42664cc | 2313 | } else |
abd58f01 BW |
2314 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2315 | } | |
2316 | ||
92d03a80 DV |
2317 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2318 | /* | |
2319 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2320 | * scheme also closed the SDE interrupt handling race we've seen | |
2321 | * on older pch-split platforms. But this needs testing. | |
2322 | */ | |
2323 | u32 pch_iir = I915_READ(SDEIIR); | |
92d03a80 DV |
2324 | if (pch_iir) { |
2325 | I915_WRITE(SDEIIR, pch_iir); | |
2326 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2327 | cpt_irq_handler(dev, pch_iir); |
2328 | } else | |
2329 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); | |
2330 | ||
92d03a80 DV |
2331 | } |
2332 | ||
abd58f01 BW |
2333 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2334 | POSTING_READ(GEN8_MASTER_IRQ); | |
2335 | ||
2336 | return ret; | |
2337 | } | |
2338 | ||
17e1df07 DV |
2339 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2340 | bool reset_completed) | |
2341 | { | |
a4872ba6 | 2342 | struct intel_engine_cs *ring; |
17e1df07 DV |
2343 | int i; |
2344 | ||
2345 | /* | |
2346 | * Notify all waiters for GPU completion events that reset state has | |
2347 | * been changed, and that they need to restart their wait after | |
2348 | * checking for potential errors (and bail out to drop locks if there is | |
2349 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2350 | */ | |
2351 | ||
2352 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2353 | for_each_ring(ring, dev_priv, i) | |
2354 | wake_up_all(&ring->irq_queue); | |
2355 | ||
2356 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2357 | wake_up_all(&dev_priv->pending_flip_queue); | |
2358 | ||
2359 | /* | |
2360 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2361 | * reset state is cleared. | |
2362 | */ | |
2363 | if (reset_completed) | |
2364 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2365 | } | |
2366 | ||
8a905236 JB |
2367 | /** |
2368 | * i915_error_work_func - do process context error handling work | |
2369 | * @work: work struct | |
2370 | * | |
2371 | * Fire an error uevent so userspace can see that a hang or error | |
2372 | * was detected. | |
2373 | */ | |
2374 | static void i915_error_work_func(struct work_struct *work) | |
2375 | { | |
1f83fee0 DV |
2376 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
2377 | work); | |
2d1013dd JN |
2378 | struct drm_i915_private *dev_priv = |
2379 | container_of(error, struct drm_i915_private, gpu_error); | |
8a905236 | 2380 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
2381 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2382 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2383 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2384 | int ret; |
8a905236 | 2385 | |
5bdebb18 | 2386 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2387 | |
7db0ba24 DV |
2388 | /* |
2389 | * Note that there's only one work item which does gpu resets, so we | |
2390 | * need not worry about concurrent gpu resets potentially incrementing | |
2391 | * error->reset_counter twice. We only need to take care of another | |
2392 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2393 | * quick check for that is good enough: schedule_work ensures the | |
2394 | * correct ordering between hang detection and this work item, and since | |
2395 | * the reset in-progress bit is only ever set by code outside of this | |
2396 | * work we don't need to worry about any other races. | |
2397 | */ | |
2398 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2399 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2400 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2401 | reset_event); |
1f83fee0 | 2402 | |
f454c694 ID |
2403 | /* |
2404 | * In most cases it's guaranteed that we get here with an RPM | |
2405 | * reference held, for example because there is a pending GPU | |
2406 | * request that won't finish until the reset is done. This | |
2407 | * isn't the case at least when we get here by doing a | |
2408 | * simulated reset via debugs, so get an RPM reference. | |
2409 | */ | |
2410 | intel_runtime_pm_get(dev_priv); | |
17e1df07 DV |
2411 | /* |
2412 | * All state reset _must_ be completed before we update the | |
2413 | * reset counter, for otherwise waiters might miss the reset | |
2414 | * pending state and not properly drop locks, resulting in | |
2415 | * deadlocks with the reset work. | |
2416 | */ | |
f69061be DV |
2417 | ret = i915_reset(dev); |
2418 | ||
17e1df07 DV |
2419 | intel_display_handle_reset(dev); |
2420 | ||
f454c694 ID |
2421 | intel_runtime_pm_put(dev_priv); |
2422 | ||
f69061be DV |
2423 | if (ret == 0) { |
2424 | /* | |
2425 | * After all the gem state is reset, increment the reset | |
2426 | * counter and wake up everyone waiting for the reset to | |
2427 | * complete. | |
2428 | * | |
2429 | * Since unlock operations are a one-sided barrier only, | |
2430 | * we need to insert a barrier here to order any seqno | |
2431 | * updates before | |
2432 | * the counter increment. | |
2433 | */ | |
4e857c58 | 2434 | smp_mb__before_atomic(); |
f69061be DV |
2435 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
2436 | ||
5bdebb18 | 2437 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2438 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2439 | } else { |
2ac0f450 | 2440 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2441 | } |
1f83fee0 | 2442 | |
17e1df07 DV |
2443 | /* |
2444 | * Note: The wake_up also serves as a memory barrier so that | |
2445 | * waiters see the update value of the reset counter atomic_t. | |
2446 | */ | |
2447 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2448 | } |
8a905236 JB |
2449 | } |
2450 | ||
35aed2e6 | 2451 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2452 | { |
2453 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2454 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2455 | u32 eir = I915_READ(EIR); |
050ee91f | 2456 | int pipe, i; |
8a905236 | 2457 | |
35aed2e6 CW |
2458 | if (!eir) |
2459 | return; | |
8a905236 | 2460 | |
a70491cc | 2461 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2462 | |
bd9854f9 BW |
2463 | i915_get_extra_instdone(dev, instdone); |
2464 | ||
8a905236 JB |
2465 | if (IS_G4X(dev)) { |
2466 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2467 | u32 ipeir = I915_READ(IPEIR_I965); | |
2468 | ||
a70491cc JP |
2469 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2470 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2471 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2472 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2473 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2474 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2475 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2476 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2477 | } |
2478 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2479 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2480 | pr_err("page table error\n"); |
2481 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2482 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2483 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2484 | } |
2485 | } | |
2486 | ||
a6c45cf0 | 2487 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2488 | if (eir & I915_ERROR_PAGE_TABLE) { |
2489 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2490 | pr_err("page table error\n"); |
2491 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2492 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2493 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2494 | } |
2495 | } | |
2496 | ||
2497 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2498 | pr_err("memory refresh error:\n"); |
055e393f | 2499 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2500 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2501 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2502 | /* pipestat has already been acked */ |
2503 | } | |
2504 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2505 | pr_err("instruction error\n"); |
2506 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2507 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2508 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2509 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2510 | u32 ipeir = I915_READ(IPEIR); |
2511 | ||
a70491cc JP |
2512 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2513 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2514 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2515 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2516 | POSTING_READ(IPEIR); |
8a905236 JB |
2517 | } else { |
2518 | u32 ipeir = I915_READ(IPEIR_I965); | |
2519 | ||
a70491cc JP |
2520 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2521 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2522 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2523 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2524 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2525 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2526 | } |
2527 | } | |
2528 | ||
2529 | I915_WRITE(EIR, eir); | |
3143a2bf | 2530 | POSTING_READ(EIR); |
8a905236 JB |
2531 | eir = I915_READ(EIR); |
2532 | if (eir) { | |
2533 | /* | |
2534 | * some errors might have become stuck, | |
2535 | * mask them. | |
2536 | */ | |
2537 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2538 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2539 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2540 | } | |
35aed2e6 CW |
2541 | } |
2542 | ||
2543 | /** | |
2544 | * i915_handle_error - handle an error interrupt | |
2545 | * @dev: drm device | |
2546 | * | |
2547 | * Do some basic checking of regsiter state at error interrupt time and | |
2548 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2549 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2550 | * so userspace knows something bad happened (should trigger collection | |
2551 | * of a ring dump etc.). | |
2552 | */ | |
58174462 MK |
2553 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2554 | const char *fmt, ...) | |
35aed2e6 CW |
2555 | { |
2556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2557 | va_list args; |
2558 | char error_msg[80]; | |
35aed2e6 | 2559 | |
58174462 MK |
2560 | va_start(args, fmt); |
2561 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2562 | va_end(args); | |
2563 | ||
2564 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2565 | i915_report_and_clear_eir(dev); |
8a905236 | 2566 | |
ba1234d1 | 2567 | if (wedged) { |
f69061be DV |
2568 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2569 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2570 | |
11ed50ec | 2571 | /* |
17e1df07 DV |
2572 | * Wakeup waiting processes so that the reset work function |
2573 | * i915_error_work_func doesn't deadlock trying to grab various | |
2574 | * locks. By bumping the reset counter first, the woken | |
2575 | * processes will see a reset in progress and back off, | |
2576 | * releasing their locks and then wait for the reset completion. | |
2577 | * We must do this for _all_ gpu waiters that might hold locks | |
2578 | * that the reset work needs to acquire. | |
2579 | * | |
2580 | * Note: The wake_up serves as the required memory barrier to | |
2581 | * ensure that the waiters see the updated value of the reset | |
2582 | * counter atomic_t. | |
11ed50ec | 2583 | */ |
17e1df07 | 2584 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2585 | } |
2586 | ||
122f46ba DV |
2587 | /* |
2588 | * Our reset work can grab modeset locks (since it needs to reset the | |
2589 | * state of outstanding pagelips). Hence it must not be run on our own | |
2590 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2591 | * code will deadlock. | |
2592 | */ | |
2593 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2594 | } |
2595 | ||
42f52ef8 KP |
2596 | /* Called from drm generic code, passed 'crtc' which |
2597 | * we use as a pipe index | |
2598 | */ | |
f71d4af4 | 2599 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2600 | { |
2d1013dd | 2601 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2602 | unsigned long irqflags; |
71e0ffa5 | 2603 | |
5eddb70b | 2604 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2605 | return -EINVAL; |
0a3e67a4 | 2606 | |
1ec14ad3 | 2607 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2608 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2609 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2610 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2611 | else |
7c463586 | 2612 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2613 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2614 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2615 | |
0a3e67a4 JB |
2616 | return 0; |
2617 | } | |
2618 | ||
f71d4af4 | 2619 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2620 | { |
2d1013dd | 2621 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2622 | unsigned long irqflags; |
b518421f | 2623 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2624 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2625 | |
2626 | if (!i915_pipe_enabled(dev, pipe)) | |
2627 | return -EINVAL; | |
2628 | ||
2629 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2630 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2631 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2632 | ||
2633 | return 0; | |
2634 | } | |
2635 | ||
7e231dbe JB |
2636 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2637 | { | |
2d1013dd | 2638 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2639 | unsigned long irqflags; |
7e231dbe JB |
2640 | |
2641 | if (!i915_pipe_enabled(dev, pipe)) | |
2642 | return -EINVAL; | |
2643 | ||
2644 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2645 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2646 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2647 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2648 | ||
2649 | return 0; | |
2650 | } | |
2651 | ||
abd58f01 BW |
2652 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2653 | { | |
2654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2655 | unsigned long irqflags; | |
abd58f01 BW |
2656 | |
2657 | if (!i915_pipe_enabled(dev, pipe)) | |
2658 | return -EINVAL; | |
2659 | ||
2660 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2661 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2662 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2663 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2664 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2665 | return 0; | |
2666 | } | |
2667 | ||
42f52ef8 KP |
2668 | /* Called from drm generic code, passed 'crtc' which |
2669 | * we use as a pipe index | |
2670 | */ | |
f71d4af4 | 2671 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2672 | { |
2d1013dd | 2673 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2674 | unsigned long irqflags; |
0a3e67a4 | 2675 | |
1ec14ad3 | 2676 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2677 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2678 | PIPE_VBLANK_INTERRUPT_STATUS | |
2679 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2680 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2681 | } | |
2682 | ||
f71d4af4 | 2683 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2684 | { |
2d1013dd | 2685 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2686 | unsigned long irqflags; |
b518421f | 2687 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2688 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2689 | |
2690 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2691 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2692 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2693 | } | |
2694 | ||
7e231dbe JB |
2695 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2696 | { | |
2d1013dd | 2697 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2698 | unsigned long irqflags; |
7e231dbe JB |
2699 | |
2700 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2701 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2702 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2703 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2704 | } | |
2705 | ||
abd58f01 BW |
2706 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2707 | { | |
2708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2709 | unsigned long irqflags; | |
abd58f01 BW |
2710 | |
2711 | if (!i915_pipe_enabled(dev, pipe)) | |
2712 | return; | |
2713 | ||
2714 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2715 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2716 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2717 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2718 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2719 | } | |
2720 | ||
893eead0 | 2721 | static u32 |
a4872ba6 | 2722 | ring_last_seqno(struct intel_engine_cs *ring) |
852835f3 | 2723 | { |
893eead0 CW |
2724 | return list_entry(ring->request_list.prev, |
2725 | struct drm_i915_gem_request, list)->seqno; | |
2726 | } | |
2727 | ||
9107e9d2 | 2728 | static bool |
a4872ba6 | 2729 | ring_idle(struct intel_engine_cs *ring, u32 seqno) |
9107e9d2 CW |
2730 | { |
2731 | return (list_empty(&ring->request_list) || | |
2732 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2733 | } |
2734 | ||
a028c4b0 DV |
2735 | static bool |
2736 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2737 | { | |
2738 | if (INTEL_INFO(dev)->gen >= 8) { | |
a6cdb93a | 2739 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2740 | } else { |
2741 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2742 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2743 | MI_SEMAPHORE_REGISTER); | |
2744 | } | |
2745 | } | |
2746 | ||
a4872ba6 | 2747 | static struct intel_engine_cs * |
a6cdb93a | 2748 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
921d42ea DV |
2749 | { |
2750 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2751 | struct intel_engine_cs *signaller; |
921d42ea DV |
2752 | int i; |
2753 | ||
2754 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
a6cdb93a RV |
2755 | for_each_ring(signaller, dev_priv, i) { |
2756 | if (ring == signaller) | |
2757 | continue; | |
2758 | ||
2759 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) | |
2760 | return signaller; | |
2761 | } | |
921d42ea DV |
2762 | } else { |
2763 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2764 | ||
2765 | for_each_ring(signaller, dev_priv, i) { | |
2766 | if(ring == signaller) | |
2767 | continue; | |
2768 | ||
ebc348b2 | 2769 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2770 | return signaller; |
2771 | } | |
2772 | } | |
2773 | ||
a6cdb93a RV |
2774 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
2775 | ring->id, ipehr, offset); | |
921d42ea DV |
2776 | |
2777 | return NULL; | |
2778 | } | |
2779 | ||
a4872ba6 OM |
2780 | static struct intel_engine_cs * |
2781 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) | |
a24a11e6 CW |
2782 | { |
2783 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d | 2784 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2785 | u64 offset = 0; |
2786 | int i, backwards; | |
a24a11e6 CW |
2787 | |
2788 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2789 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2790 | return NULL; |
a24a11e6 | 2791 | |
88fe429d DV |
2792 | /* |
2793 | * HEAD is likely pointing to the dword after the actual command, | |
2794 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2795 | * or 4 dwords depending on the semaphore wait command size. |
2796 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2797 | * point at at batch, and semaphores are always emitted into the |
2798 | * ringbuffer itself. | |
a24a11e6 | 2799 | */ |
88fe429d | 2800 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
a6cdb93a | 2801 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
88fe429d | 2802 | |
a6cdb93a | 2803 | for (i = backwards; i; --i) { |
88fe429d DV |
2804 | /* |
2805 | * Be paranoid and presume the hw has gone off into the wild - | |
2806 | * our ring is smaller than what the hardware (and hence | |
2807 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2808 | */ | |
ee1b1e5e | 2809 | head &= ring->buffer->size - 1; |
88fe429d DV |
2810 | |
2811 | /* This here seems to blow up */ | |
ee1b1e5e | 2812 | cmd = ioread32(ring->buffer->virtual_start + head); |
a24a11e6 CW |
2813 | if (cmd == ipehr) |
2814 | break; | |
2815 | ||
88fe429d DV |
2816 | head -= 4; |
2817 | } | |
a24a11e6 | 2818 | |
88fe429d DV |
2819 | if (!i) |
2820 | return NULL; | |
a24a11e6 | 2821 | |
ee1b1e5e | 2822 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
a6cdb93a RV |
2823 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2824 | offset = ioread32(ring->buffer->virtual_start + head + 12); | |
2825 | offset <<= 32; | |
2826 | offset = ioread32(ring->buffer->virtual_start + head + 8); | |
2827 | } | |
2828 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); | |
a24a11e6 CW |
2829 | } |
2830 | ||
a4872ba6 | 2831 | static int semaphore_passed(struct intel_engine_cs *ring) |
6274f212 CW |
2832 | { |
2833 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2834 | struct intel_engine_cs *signaller; |
a0d036b0 | 2835 | u32 seqno; |
6274f212 | 2836 | |
4be17381 | 2837 | ring->hangcheck.deadlock++; |
6274f212 CW |
2838 | |
2839 | signaller = semaphore_waits_for(ring, &seqno); | |
4be17381 CW |
2840 | if (signaller == NULL) |
2841 | return -1; | |
2842 | ||
2843 | /* Prevent pathological recursion due to driver bugs */ | |
2844 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) | |
6274f212 CW |
2845 | return -1; |
2846 | ||
4be17381 CW |
2847 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
2848 | return 1; | |
2849 | ||
a0d036b0 CW |
2850 | /* cursory check for an unkickable deadlock */ |
2851 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
2852 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
2853 | return -1; |
2854 | ||
2855 | return 0; | |
6274f212 CW |
2856 | } |
2857 | ||
2858 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2859 | { | |
a4872ba6 | 2860 | struct intel_engine_cs *ring; |
6274f212 CW |
2861 | int i; |
2862 | ||
2863 | for_each_ring(ring, dev_priv, i) | |
4be17381 | 2864 | ring->hangcheck.deadlock = 0; |
6274f212 CW |
2865 | } |
2866 | ||
ad8beaea | 2867 | static enum intel_ring_hangcheck_action |
a4872ba6 | 2868 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
1ec14ad3 CW |
2869 | { |
2870 | struct drm_device *dev = ring->dev; | |
2871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2872 | u32 tmp; |
2873 | ||
f260fe7b MK |
2874 | if (acthd != ring->hangcheck.acthd) { |
2875 | if (acthd > ring->hangcheck.max_acthd) { | |
2876 | ring->hangcheck.max_acthd = acthd; | |
2877 | return HANGCHECK_ACTIVE; | |
2878 | } | |
2879 | ||
2880 | return HANGCHECK_ACTIVE_LOOP; | |
2881 | } | |
6274f212 | 2882 | |
9107e9d2 | 2883 | if (IS_GEN2(dev)) |
f2f4d82f | 2884 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2885 | |
2886 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2887 | * If so we can simply poke the RB_WAIT bit | |
2888 | * and break the hang. This should work on | |
2889 | * all but the second generation chipsets. | |
2890 | */ | |
2891 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2892 | if (tmp & RING_WAIT) { |
58174462 MK |
2893 | i915_handle_error(dev, false, |
2894 | "Kicking stuck wait on %s", | |
2895 | ring->name); | |
1ec14ad3 | 2896 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2897 | return HANGCHECK_KICK; |
6274f212 CW |
2898 | } |
2899 | ||
2900 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2901 | switch (semaphore_passed(ring)) { | |
2902 | default: | |
f2f4d82f | 2903 | return HANGCHECK_HUNG; |
6274f212 | 2904 | case 1: |
58174462 MK |
2905 | i915_handle_error(dev, false, |
2906 | "Kicking stuck semaphore on %s", | |
2907 | ring->name); | |
6274f212 | 2908 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2909 | return HANGCHECK_KICK; |
6274f212 | 2910 | case 0: |
f2f4d82f | 2911 | return HANGCHECK_WAIT; |
6274f212 | 2912 | } |
9107e9d2 | 2913 | } |
ed5cbb03 | 2914 | |
f2f4d82f | 2915 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2916 | } |
2917 | ||
f65d9421 BG |
2918 | /** |
2919 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2920 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2921 | * if there are no progress, hangcheck score for that ring is increased. | |
2922 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2923 | * we kick the ring. If we see no progress on three subsequent calls | |
2924 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2925 | */ |
a658b5d2 | 2926 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2927 | { |
2928 | struct drm_device *dev = (struct drm_device *)data; | |
2d1013dd | 2929 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2930 | struct intel_engine_cs *ring; |
b4519513 | 2931 | int i; |
05407ff8 | 2932 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2933 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2934 | #define BUSY 1 | |
2935 | #define KICK 5 | |
2936 | #define HUNG 20 | |
893eead0 | 2937 | |
d330a953 | 2938 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2939 | return; |
2940 | ||
b4519513 | 2941 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2942 | u64 acthd; |
2943 | u32 seqno; | |
9107e9d2 | 2944 | bool busy = true; |
05407ff8 | 2945 | |
6274f212 CW |
2946 | semaphore_clear_deadlocks(dev_priv); |
2947 | ||
05407ff8 MK |
2948 | seqno = ring->get_seqno(ring, false); |
2949 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2950 | |
9107e9d2 CW |
2951 | if (ring->hangcheck.seqno == seqno) { |
2952 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2953 | ring->hangcheck.action = HANGCHECK_IDLE; |
2954 | ||
9107e9d2 CW |
2955 | if (waitqueue_active(&ring->irq_queue)) { |
2956 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2957 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2958 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2959 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2960 | ring->name); | |
2961 | else | |
2962 | DRM_INFO("Fake missed irq on %s\n", | |
2963 | ring->name); | |
094f9a54 CW |
2964 | wake_up_all(&ring->irq_queue); |
2965 | } | |
2966 | /* Safeguard against driver failure */ | |
2967 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2968 | } else |
2969 | busy = false; | |
05407ff8 | 2970 | } else { |
6274f212 CW |
2971 | /* We always increment the hangcheck score |
2972 | * if the ring is busy and still processing | |
2973 | * the same request, so that no single request | |
2974 | * can run indefinitely (such as a chain of | |
2975 | * batches). The only time we do not increment | |
2976 | * the hangcheck score on this ring, if this | |
2977 | * ring is in a legitimate wait for another | |
2978 | * ring. In that case the waiting ring is a | |
2979 | * victim and we want to be sure we catch the | |
2980 | * right culprit. Then every time we do kick | |
2981 | * the ring, add a small increment to the | |
2982 | * score so that we can catch a batch that is | |
2983 | * being repeatedly kicked and so responsible | |
2984 | * for stalling the machine. | |
2985 | */ | |
ad8beaea MK |
2986 | ring->hangcheck.action = ring_stuck(ring, |
2987 | acthd); | |
2988 | ||
2989 | switch (ring->hangcheck.action) { | |
da661464 | 2990 | case HANGCHECK_IDLE: |
f2f4d82f | 2991 | case HANGCHECK_WAIT: |
f2f4d82f | 2992 | case HANGCHECK_ACTIVE: |
f260fe7b MK |
2993 | break; |
2994 | case HANGCHECK_ACTIVE_LOOP: | |
ea04cb31 | 2995 | ring->hangcheck.score += BUSY; |
6274f212 | 2996 | break; |
f2f4d82f | 2997 | case HANGCHECK_KICK: |
ea04cb31 | 2998 | ring->hangcheck.score += KICK; |
6274f212 | 2999 | break; |
f2f4d82f | 3000 | case HANGCHECK_HUNG: |
ea04cb31 | 3001 | ring->hangcheck.score += HUNG; |
6274f212 CW |
3002 | stuck[i] = true; |
3003 | break; | |
3004 | } | |
05407ff8 | 3005 | } |
9107e9d2 | 3006 | } else { |
da661464 MK |
3007 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
3008 | ||
9107e9d2 CW |
3009 | /* Gradually reduce the count so that we catch DoS |
3010 | * attempts across multiple batches. | |
3011 | */ | |
3012 | if (ring->hangcheck.score > 0) | |
3013 | ring->hangcheck.score--; | |
f260fe7b MK |
3014 | |
3015 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; | |
d1e61e7f CW |
3016 | } |
3017 | ||
05407ff8 MK |
3018 | ring->hangcheck.seqno = seqno; |
3019 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 3020 | busy_count += busy; |
893eead0 | 3021 | } |
b9201c14 | 3022 | |
92cab734 | 3023 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 3024 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
3025 | DRM_INFO("%s on %s\n", |
3026 | stuck[i] ? "stuck" : "no progress", | |
3027 | ring->name); | |
a43adf07 | 3028 | rings_hung++; |
92cab734 MK |
3029 | } |
3030 | } | |
3031 | ||
05407ff8 | 3032 | if (rings_hung) |
58174462 | 3033 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 3034 | |
05407ff8 MK |
3035 | if (busy_count) |
3036 | /* Reset timer case chip hangs without another request | |
3037 | * being added */ | |
10cd45b6 MK |
3038 | i915_queue_hangcheck(dev); |
3039 | } | |
3040 | ||
3041 | void i915_queue_hangcheck(struct drm_device *dev) | |
3042 | { | |
3043 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d330a953 | 3044 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
3045 | return; |
3046 | ||
3047 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
3048 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
3049 | } |
3050 | ||
1c69eb42 | 3051 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
3052 | { |
3053 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3054 | ||
3055 | if (HAS_PCH_NOP(dev)) | |
3056 | return; | |
3057 | ||
f86f3fb0 | 3058 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3059 | |
3060 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3061 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3062 | } |
105b122e | 3063 | |
622364b6 PZ |
3064 | /* |
3065 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3066 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3067 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3068 | * only unmask them as needed with SDEIMR. | |
3069 | * | |
3070 | * This function needs to be called before interrupts are enabled. | |
3071 | */ | |
3072 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3073 | { | |
3074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3075 | ||
3076 | if (HAS_PCH_NOP(dev)) | |
3077 | return; | |
3078 | ||
3079 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3080 | I915_WRITE(SDEIER, 0xffffffff); |
3081 | POSTING_READ(SDEIER); | |
3082 | } | |
3083 | ||
7c4d664e | 3084 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3085 | { |
3086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3087 | ||
f86f3fb0 | 3088 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3089 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3090 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3091 | } |
3092 | ||
1da177e4 LT |
3093 | /* drm_dma.h hooks |
3094 | */ | |
be30b29f | 3095 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 3096 | { |
2d1013dd | 3097 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 3098 | |
0c841212 | 3099 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 3100 | |
f86f3fb0 | 3101 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
3102 | if (IS_GEN7(dev)) |
3103 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 3104 | |
7c4d664e | 3105 | gen5_gt_irq_reset(dev); |
c650156a | 3106 | |
1c69eb42 | 3107 | ibx_irq_reset(dev); |
7d99163d | 3108 | } |
c650156a | 3109 | |
70591a41 VS |
3110 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
3111 | { | |
3112 | enum pipe pipe; | |
3113 | ||
3114 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3115 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3116 | ||
3117 | for_each_pipe(dev_priv, pipe) | |
3118 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3119 | ||
3120 | GEN5_IRQ_RESET(VLV_); | |
3121 | } | |
3122 | ||
7e231dbe JB |
3123 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3124 | { | |
2d1013dd | 3125 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3126 | |
7e231dbe JB |
3127 | /* VLV magic */ |
3128 | I915_WRITE(VLV_IMR, 0); | |
3129 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
3130 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
3131 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
3132 | ||
7c4d664e | 3133 | gen5_gt_irq_reset(dev); |
7e231dbe | 3134 | |
7c4cde39 | 3135 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
7e231dbe | 3136 | |
70591a41 | 3137 | vlv_display_irq_reset(dev_priv); |
7e231dbe JB |
3138 | } |
3139 | ||
d6e3cca3 DV |
3140 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3141 | { | |
3142 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3143 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3144 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3145 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3146 | } | |
3147 | ||
823f6b38 | 3148 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3149 | { |
3150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3151 | int pipe; | |
3152 | ||
abd58f01 BW |
3153 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3154 | POSTING_READ(GEN8_MASTER_IRQ); | |
3155 | ||
d6e3cca3 | 3156 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3157 | |
055e393f | 3158 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3159 | if (intel_display_power_is_enabled(dev_priv, |
3160 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3161 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3162 | |
f86f3fb0 PZ |
3163 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3164 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3165 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3166 | |
1c69eb42 | 3167 | ibx_irq_reset(dev); |
abd58f01 | 3168 | } |
09f2344d | 3169 | |
d49bdb0e PZ |
3170 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) |
3171 | { | |
1180e206 | 3172 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
d49bdb0e | 3173 | |
13321786 | 3174 | spin_lock_irq(&dev_priv->irq_lock); |
d49bdb0e | 3175 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], |
1180e206 | 3176 | ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); |
d49bdb0e | 3177 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], |
1180e206 | 3178 | ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); |
13321786 | 3179 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3180 | } |
3181 | ||
43f328d7 VS |
3182 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3183 | { | |
3184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3185 | |
3186 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3187 | POSTING_READ(GEN8_MASTER_IRQ); | |
3188 | ||
d6e3cca3 | 3189 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3190 | |
3191 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3192 | ||
43f328d7 VS |
3193 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
3194 | ||
70591a41 | 3195 | vlv_display_irq_reset(dev_priv); |
43f328d7 VS |
3196 | } |
3197 | ||
82a28bcf | 3198 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3199 | { |
2d1013dd | 3200 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3201 | struct intel_encoder *intel_encoder; |
fee884ed | 3202 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
3203 | |
3204 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3205 | hotplug_irqs = SDE_HOTPLUG_MASK; |
b2784e15 | 3206 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3207 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3208 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 3209 | } else { |
fee884ed | 3210 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
b2784e15 | 3211 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3212 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3213 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 3214 | } |
7fe0b973 | 3215 | |
fee884ed | 3216 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3217 | |
3218 | /* | |
3219 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
3220 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3221 | * | |
3222 | * This register is the same on all known PCH chips. | |
3223 | */ | |
7fe0b973 KP |
3224 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3225 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3226 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3227 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3228 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
3229 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
3230 | } | |
3231 | ||
d46da437 PZ |
3232 | static void ibx_irq_postinstall(struct drm_device *dev) |
3233 | { | |
2d1013dd | 3234 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3235 | u32 mask; |
e5868a31 | 3236 | |
692a04cf DV |
3237 | if (HAS_PCH_NOP(dev)) |
3238 | return; | |
3239 | ||
105b122e | 3240 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3241 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3242 | else |
5c673b60 | 3243 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3244 | |
337ba017 | 3245 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3246 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3247 | } |
3248 | ||
0a9a8c91 DV |
3249 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3250 | { | |
3251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3252 | u32 pm_irqs, gt_irqs; | |
3253 | ||
3254 | pm_irqs = gt_irqs = 0; | |
3255 | ||
3256 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3257 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3258 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3259 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3260 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3261 | } |
3262 | ||
3263 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3264 | if (IS_GEN5(dev)) { | |
3265 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3266 | ILK_BSD_USER_INTERRUPT; | |
3267 | } else { | |
3268 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3269 | } | |
3270 | ||
35079899 | 3271 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3272 | |
3273 | if (INTEL_INFO(dev)->gen >= 6) { | |
a6706b45 | 3274 | pm_irqs |= dev_priv->pm_rps_events; |
0a9a8c91 DV |
3275 | |
3276 | if (HAS_VEBOX(dev)) | |
3277 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3278 | ||
605cd25b | 3279 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3280 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3281 | } |
3282 | } | |
3283 | ||
f71d4af4 | 3284 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3285 | { |
2d1013dd | 3286 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3287 | u32 display_mask, extra_mask; |
3288 | ||
3289 | if (INTEL_INFO(dev)->gen >= 7) { | |
3290 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3291 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3292 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3293 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3294 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 3295 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
3296 | } else { |
3297 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3298 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3299 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3300 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3301 | DE_POISON); | |
5c673b60 DV |
3302 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3303 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3304 | } |
036a4a7d | 3305 | |
1ec14ad3 | 3306 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3307 | |
0c841212 PZ |
3308 | I915_WRITE(HWSTAM, 0xeffe); |
3309 | ||
622364b6 PZ |
3310 | ibx_irq_pre_postinstall(dev); |
3311 | ||
35079899 | 3312 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3313 | |
0a9a8c91 | 3314 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3315 | |
d46da437 | 3316 | ibx_irq_postinstall(dev); |
7fe0b973 | 3317 | |
f97108d1 | 3318 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3319 | /* Enable PCU event interrupts |
3320 | * | |
3321 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3322 | * setup is guaranteed to run in single-threaded context. But we |
3323 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3324 | spin_lock_irq(&dev_priv->irq_lock); |
f97108d1 | 3325 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3326 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3327 | } |
3328 | ||
036a4a7d ZW |
3329 | return 0; |
3330 | } | |
3331 | ||
f8b79e58 ID |
3332 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3333 | { | |
3334 | u32 pipestat_mask; | |
3335 | u32 iir_mask; | |
120dda4f | 3336 | enum pipe pipe; |
f8b79e58 ID |
3337 | |
3338 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3339 | PIPE_FIFO_UNDERRUN_STATUS; | |
3340 | ||
120dda4f VS |
3341 | for_each_pipe(dev_priv, pipe) |
3342 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3343 | POSTING_READ(PIPESTAT(PIPE_A)); |
3344 | ||
3345 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3346 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3347 | ||
120dda4f VS |
3348 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3349 | for_each_pipe(dev_priv, pipe) | |
3350 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3351 | |
3352 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3353 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3354 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
120dda4f VS |
3355 | if (IS_CHERRYVIEW(dev_priv)) |
3356 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3357 | dev_priv->irq_mask &= ~iir_mask; |
3358 | ||
3359 | I915_WRITE(VLV_IIR, iir_mask); | |
3360 | I915_WRITE(VLV_IIR, iir_mask); | |
f8b79e58 | 3361 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
76e41860 VS |
3362 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3363 | POSTING_READ(VLV_IMR); | |
f8b79e58 ID |
3364 | } |
3365 | ||
3366 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3367 | { | |
3368 | u32 pipestat_mask; | |
3369 | u32 iir_mask; | |
120dda4f | 3370 | enum pipe pipe; |
f8b79e58 ID |
3371 | |
3372 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3373 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3374 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
120dda4f VS |
3375 | if (IS_CHERRYVIEW(dev_priv)) |
3376 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3377 | |
3378 | dev_priv->irq_mask |= iir_mask; | |
f8b79e58 | 3379 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
76e41860 | 3380 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
f8b79e58 ID |
3381 | I915_WRITE(VLV_IIR, iir_mask); |
3382 | I915_WRITE(VLV_IIR, iir_mask); | |
3383 | POSTING_READ(VLV_IIR); | |
3384 | ||
3385 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3386 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3387 | ||
120dda4f VS |
3388 | i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3389 | for_each_pipe(dev_priv, pipe) | |
3390 | i915_disable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3391 | |
3392 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3393 | PIPE_FIFO_UNDERRUN_STATUS; | |
120dda4f VS |
3394 | |
3395 | for_each_pipe(dev_priv, pipe) | |
3396 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3397 | POSTING_READ(PIPESTAT(PIPE_A)); |
3398 | } | |
3399 | ||
3400 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3401 | { | |
3402 | assert_spin_locked(&dev_priv->irq_lock); | |
3403 | ||
3404 | if (dev_priv->display_irqs_enabled) | |
3405 | return; | |
3406 | ||
3407 | dev_priv->display_irqs_enabled = true; | |
3408 | ||
950eabaf | 3409 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3410 | valleyview_display_irqs_install(dev_priv); |
3411 | } | |
3412 | ||
3413 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3414 | { | |
3415 | assert_spin_locked(&dev_priv->irq_lock); | |
3416 | ||
3417 | if (!dev_priv->display_irqs_enabled) | |
3418 | return; | |
3419 | ||
3420 | dev_priv->display_irqs_enabled = false; | |
3421 | ||
950eabaf | 3422 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3423 | valleyview_display_irqs_uninstall(dev_priv); |
3424 | } | |
3425 | ||
0e6c9a9e | 3426 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
7e231dbe | 3427 | { |
f8b79e58 | 3428 | dev_priv->irq_mask = ~0; |
7e231dbe | 3429 | |
20afbda2 DV |
3430 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3431 | POSTING_READ(PORT_HOTPLUG_EN); | |
3432 | ||
7e231dbe | 3433 | I915_WRITE(VLV_IIR, 0xffffffff); |
76e41860 VS |
3434 | I915_WRITE(VLV_IIR, 0xffffffff); |
3435 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3436 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3437 | POSTING_READ(VLV_IMR); | |
7e231dbe | 3438 | |
b79480ba DV |
3439 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3440 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3441 | spin_lock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3442 | if (dev_priv->display_irqs_enabled) |
3443 | valleyview_display_irqs_install(dev_priv); | |
d6207435 | 3444 | spin_unlock_irq(&dev_priv->irq_lock); |
0e6c9a9e VS |
3445 | } |
3446 | ||
3447 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3448 | { | |
3449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3450 | ||
3451 | vlv_display_irq_postinstall(dev_priv); | |
7e231dbe | 3452 | |
0a9a8c91 | 3453 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3454 | |
3455 | /* ack & enable invalid PTE error interrupts */ | |
3456 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3457 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3458 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3459 | #endif | |
3460 | ||
3461 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3462 | |
3463 | return 0; | |
3464 | } | |
3465 | ||
abd58f01 BW |
3466 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3467 | { | |
abd58f01 BW |
3468 | /* These are interrupts we'll toggle with the ring mask register */ |
3469 | uint32_t gt_interrupts[] = { | |
3470 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3471 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
abd58f01 | 3472 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
73d477f6 OM |
3473 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3474 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3475 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3476 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3477 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3478 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3479 | 0, |
73d477f6 OM |
3480 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3481 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3482 | }; |
3483 | ||
0961021a | 3484 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3485 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3486 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
3487 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events); | |
3488 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); | |
abd58f01 BW |
3489 | } |
3490 | ||
3491 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3492 | { | |
770de83d DL |
3493 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3494 | uint32_t de_pipe_enables; | |
abd58f01 | 3495 | int pipe; |
88e04703 | 3496 | u32 aux_en = GEN8_AUX_CHANNEL_A; |
770de83d | 3497 | |
88e04703 | 3498 | if (IS_GEN9(dev_priv)) { |
770de83d DL |
3499 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3500 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
88e04703 JB |
3501 | aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3502 | GEN9_AUX_CHANNEL_D; | |
3503 | } else | |
770de83d DL |
3504 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3505 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3506 | ||
3507 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3508 | GEN8_PIPE_FIFO_UNDERRUN; | |
3509 | ||
13b3a0a7 DV |
3510 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3511 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3512 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3513 | |
055e393f | 3514 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3515 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3516 | POWER_DOMAIN_PIPE(pipe))) |
3517 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3518 | dev_priv->de_irq_mask[pipe], | |
3519 | de_pipe_enables); | |
abd58f01 | 3520 | |
88e04703 | 3521 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en); |
abd58f01 BW |
3522 | } |
3523 | ||
3524 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3525 | { | |
3526 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3527 | ||
622364b6 PZ |
3528 | ibx_irq_pre_postinstall(dev); |
3529 | ||
abd58f01 BW |
3530 | gen8_gt_irq_postinstall(dev_priv); |
3531 | gen8_de_irq_postinstall(dev_priv); | |
3532 | ||
3533 | ibx_irq_postinstall(dev); | |
3534 | ||
3535 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3536 | POSTING_READ(GEN8_MASTER_IRQ); | |
3537 | ||
3538 | return 0; | |
3539 | } | |
3540 | ||
43f328d7 VS |
3541 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3542 | { | |
3543 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3544 | u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3545 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
43f328d7 | 3546 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
3278f67f VS |
3547 | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
3548 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3549 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
43f328d7 VS |
3550 | int pipe; |
3551 | ||
3552 | /* | |
3553 | * Leave vblank interrupts masked initially. enable/disable will | |
3554 | * toggle them based on usage. | |
3555 | */ | |
3278f67f | 3556 | dev_priv->irq_mask = ~enable_mask; |
43f328d7 | 3557 | |
055e393f | 3558 | for_each_pipe(dev_priv, pipe) |
43f328d7 VS |
3559 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3560 | ||
d6207435 | 3561 | spin_lock_irq(&dev_priv->irq_lock); |
3278f67f | 3562 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
055e393f | 3563 | for_each_pipe(dev_priv, pipe) |
43f328d7 | 3564 | i915_enable_pipestat(dev_priv, pipe, pipestat_enable); |
d6207435 | 3565 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3566 | |
3567 | I915_WRITE(VLV_IIR, 0xffffffff); | |
76e41860 | 3568 | I915_WRITE(VLV_IIR, 0xffffffff); |
43f328d7 | 3569 | I915_WRITE(VLV_IER, enable_mask); |
76e41860 VS |
3570 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3571 | POSTING_READ(VLV_IMR); | |
43f328d7 VS |
3572 | |
3573 | gen8_gt_irq_postinstall(dev_priv); | |
3574 | ||
3575 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3576 | POSTING_READ(GEN8_MASTER_IRQ); | |
3577 | ||
3578 | return 0; | |
3579 | } | |
3580 | ||
abd58f01 BW |
3581 | static void gen8_irq_uninstall(struct drm_device *dev) |
3582 | { | |
3583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3584 | |
3585 | if (!dev_priv) | |
3586 | return; | |
3587 | ||
823f6b38 | 3588 | gen8_irq_reset(dev); |
abd58f01 BW |
3589 | } |
3590 | ||
7e231dbe JB |
3591 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3592 | { | |
2d1013dd | 3593 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3594 | |
3595 | if (!dev_priv) | |
3596 | return; | |
3597 | ||
843d0e7d ID |
3598 | I915_WRITE(VLV_MASTER_IER, 0); |
3599 | ||
893fce8e VS |
3600 | gen5_gt_irq_reset(dev); |
3601 | ||
7e231dbe | 3602 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3603 | |
d6207435 DV |
3604 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3605 | * just to make the assert_spin_locked check happy. */ | |
3606 | spin_lock_irq(&dev_priv->irq_lock); | |
f8b79e58 ID |
3607 | if (dev_priv->display_irqs_enabled) |
3608 | valleyview_display_irqs_uninstall(dev_priv); | |
d6207435 | 3609 | spin_unlock_irq(&dev_priv->irq_lock); |
f8b79e58 | 3610 | |
70591a41 | 3611 | vlv_display_irq_reset(dev_priv); |
f8b79e58 | 3612 | |
70591a41 | 3613 | dev_priv->irq_mask = 0; |
7e231dbe JB |
3614 | } |
3615 | ||
43f328d7 VS |
3616 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3617 | { | |
3618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3619 | int pipe; | |
3620 | ||
3621 | if (!dev_priv) | |
3622 | return; | |
3623 | ||
3624 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3625 | POSTING_READ(GEN8_MASTER_IRQ); | |
3626 | ||
a2c30fba | 3627 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3628 | |
a2c30fba | 3629 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 VS |
3630 | |
3631 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3632 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3633 | ||
055e393f | 3634 | for_each_pipe(dev_priv, pipe) |
43f328d7 VS |
3635 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3636 | ||
23a09c76 | 3637 | GEN5_IRQ_RESET(VLV_); |
43f328d7 VS |
3638 | } |
3639 | ||
f71d4af4 | 3640 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3641 | { |
2d1013dd | 3642 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3643 | |
3644 | if (!dev_priv) | |
3645 | return; | |
3646 | ||
be30b29f | 3647 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3648 | } |
3649 | ||
a266c7d5 | 3650 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3651 | { |
2d1013dd | 3652 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3653 | int pipe; |
91e3738e | 3654 | |
055e393f | 3655 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3656 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3657 | I915_WRITE16(IMR, 0xffff); |
3658 | I915_WRITE16(IER, 0x0); | |
3659 | POSTING_READ16(IER); | |
c2798b19 CW |
3660 | } |
3661 | ||
3662 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3663 | { | |
2d1013dd | 3664 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3665 | |
c2798b19 CW |
3666 | I915_WRITE16(EMR, |
3667 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3668 | ||
3669 | /* Unmask the interrupts that we always want on. */ | |
3670 | dev_priv->irq_mask = | |
3671 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3672 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3673 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3674 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3675 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3676 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3677 | ||
3678 | I915_WRITE16(IER, | |
3679 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3680 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3681 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3682 | I915_USER_INTERRUPT); | |
3683 | POSTING_READ16(IER); | |
3684 | ||
379ef82d DV |
3685 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3686 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3687 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3688 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3689 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3690 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3691 | |
c2798b19 CW |
3692 | return 0; |
3693 | } | |
3694 | ||
90a72f87 VS |
3695 | /* |
3696 | * Returns true when a page flip has completed. | |
3697 | */ | |
3698 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3699 | int plane, int pipe, u32 iir) |
90a72f87 | 3700 | { |
2d1013dd | 3701 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3702 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3703 | |
8d7849db | 3704 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3705 | return false; |
3706 | ||
3707 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3708 | goto check_page_flip; |
90a72f87 | 3709 | |
1f1c2e24 | 3710 | intel_prepare_page_flip(dev, plane); |
90a72f87 VS |
3711 | |
3712 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3713 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3714 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3715 | * the flip is completed (no longer pending). Since this doesn't raise | |
3716 | * an interrupt per se, we watch for the change at vblank. | |
3717 | */ | |
3718 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 3719 | goto check_page_flip; |
90a72f87 VS |
3720 | |
3721 | intel_finish_page_flip(dev, pipe); | |
90a72f87 | 3722 | return true; |
d6bbafa1 CW |
3723 | |
3724 | check_page_flip: | |
3725 | intel_check_page_flip(dev, pipe); | |
3726 | return false; | |
90a72f87 VS |
3727 | } |
3728 | ||
ff1f525e | 3729 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3730 | { |
45a83f84 | 3731 | struct drm_device *dev = arg; |
2d1013dd | 3732 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3733 | u16 iir, new_iir; |
3734 | u32 pipe_stats[2]; | |
c2798b19 CW |
3735 | int pipe; |
3736 | u16 flip_mask = | |
3737 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3738 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3739 | ||
c2798b19 CW |
3740 | iir = I915_READ16(IIR); |
3741 | if (iir == 0) | |
3742 | return IRQ_NONE; | |
3743 | ||
3744 | while (iir & ~flip_mask) { | |
3745 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3746 | * have been cleared after the pipestat interrupt was received. | |
3747 | * It doesn't set the bit in iir again, but it still produces | |
3748 | * interrupts (for non-MSI). | |
3749 | */ | |
222c7f51 | 3750 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3751 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
58174462 MK |
3752 | i915_handle_error(dev, false, |
3753 | "Command parser error, iir 0x%08x", | |
3754 | iir); | |
c2798b19 | 3755 | |
055e393f | 3756 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3757 | int reg = PIPESTAT(pipe); |
3758 | pipe_stats[pipe] = I915_READ(reg); | |
3759 | ||
3760 | /* | |
3761 | * Clear the PIPE*STAT regs before the IIR | |
3762 | */ | |
2d9d2b0b | 3763 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3764 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3765 | } |
222c7f51 | 3766 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3767 | |
3768 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3769 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3770 | ||
d05c617e | 3771 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
3772 | |
3773 | if (iir & I915_USER_INTERRUPT) | |
3774 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3775 | ||
055e393f | 3776 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 3777 | int plane = pipe; |
3a77c4c4 | 3778 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3779 | plane = !plane; |
3780 | ||
4356d586 | 3781 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3782 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3783 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3784 | |
4356d586 | 3785 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3786 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3787 | |
1f7247c0 DV |
3788 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3789 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3790 | pipe); | |
4356d586 | 3791 | } |
c2798b19 CW |
3792 | |
3793 | iir = new_iir; | |
3794 | } | |
3795 | ||
3796 | return IRQ_HANDLED; | |
3797 | } | |
3798 | ||
3799 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3800 | { | |
2d1013dd | 3801 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3802 | int pipe; |
3803 | ||
055e393f | 3804 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3805 | /* Clear enable bits; then clear status bits */ |
3806 | I915_WRITE(PIPESTAT(pipe), 0); | |
3807 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3808 | } | |
3809 | I915_WRITE16(IMR, 0xffff); | |
3810 | I915_WRITE16(IER, 0x0); | |
3811 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3812 | } | |
3813 | ||
a266c7d5 CW |
3814 | static void i915_irq_preinstall(struct drm_device * dev) |
3815 | { | |
2d1013dd | 3816 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3817 | int pipe; |
3818 | ||
a266c7d5 CW |
3819 | if (I915_HAS_HOTPLUG(dev)) { |
3820 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3821 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3822 | } | |
3823 | ||
00d98ebd | 3824 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3825 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3826 | I915_WRITE(PIPESTAT(pipe), 0); |
3827 | I915_WRITE(IMR, 0xffffffff); | |
3828 | I915_WRITE(IER, 0x0); | |
3829 | POSTING_READ(IER); | |
3830 | } | |
3831 | ||
3832 | static int i915_irq_postinstall(struct drm_device *dev) | |
3833 | { | |
2d1013dd | 3834 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3835 | u32 enable_mask; |
a266c7d5 | 3836 | |
38bde180 CW |
3837 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3838 | ||
3839 | /* Unmask the interrupts that we always want on. */ | |
3840 | dev_priv->irq_mask = | |
3841 | ~(I915_ASLE_INTERRUPT | | |
3842 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3843 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3844 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3845 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3846 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3847 | ||
3848 | enable_mask = | |
3849 | I915_ASLE_INTERRUPT | | |
3850 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3851 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3852 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3853 | I915_USER_INTERRUPT; | |
3854 | ||
a266c7d5 | 3855 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3856 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3857 | POSTING_READ(PORT_HOTPLUG_EN); | |
3858 | ||
a266c7d5 CW |
3859 | /* Enable in IER... */ |
3860 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3861 | /* and unmask in IMR */ | |
3862 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3863 | } | |
3864 | ||
a266c7d5 CW |
3865 | I915_WRITE(IMR, dev_priv->irq_mask); |
3866 | I915_WRITE(IER, enable_mask); | |
3867 | POSTING_READ(IER); | |
3868 | ||
f49e38dd | 3869 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3870 | |
379ef82d DV |
3871 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3872 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3873 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3874 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3875 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3876 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3877 | |
20afbda2 DV |
3878 | return 0; |
3879 | } | |
3880 | ||
90a72f87 VS |
3881 | /* |
3882 | * Returns true when a page flip has completed. | |
3883 | */ | |
3884 | static bool i915_handle_vblank(struct drm_device *dev, | |
3885 | int plane, int pipe, u32 iir) | |
3886 | { | |
2d1013dd | 3887 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3888 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3889 | ||
8d7849db | 3890 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3891 | return false; |
3892 | ||
3893 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3894 | goto check_page_flip; |
90a72f87 VS |
3895 | |
3896 | intel_prepare_page_flip(dev, plane); | |
3897 | ||
3898 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3899 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3900 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3901 | * the flip is completed (no longer pending). Since this doesn't raise | |
3902 | * an interrupt per se, we watch for the change at vblank. | |
3903 | */ | |
3904 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 3905 | goto check_page_flip; |
90a72f87 VS |
3906 | |
3907 | intel_finish_page_flip(dev, pipe); | |
90a72f87 | 3908 | return true; |
d6bbafa1 CW |
3909 | |
3910 | check_page_flip: | |
3911 | intel_check_page_flip(dev, pipe); | |
3912 | return false; | |
90a72f87 VS |
3913 | } |
3914 | ||
ff1f525e | 3915 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3916 | { |
45a83f84 | 3917 | struct drm_device *dev = arg; |
2d1013dd | 3918 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3919 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
3920 | u32 flip_mask = |
3921 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3922 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3923 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3924 | |
a266c7d5 | 3925 | iir = I915_READ(IIR); |
38bde180 CW |
3926 | do { |
3927 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3928 | bool blc_event = false; |
a266c7d5 CW |
3929 | |
3930 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3931 | * have been cleared after the pipestat interrupt was received. | |
3932 | * It doesn't set the bit in iir again, but it still produces | |
3933 | * interrupts (for non-MSI). | |
3934 | */ | |
222c7f51 | 3935 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3936 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
58174462 MK |
3937 | i915_handle_error(dev, false, |
3938 | "Command parser error, iir 0x%08x", | |
3939 | iir); | |
a266c7d5 | 3940 | |
055e393f | 3941 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
3942 | int reg = PIPESTAT(pipe); |
3943 | pipe_stats[pipe] = I915_READ(reg); | |
3944 | ||
38bde180 | 3945 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3946 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3947 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3948 | irq_received = true; |
a266c7d5 CW |
3949 | } |
3950 | } | |
222c7f51 | 3951 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
3952 | |
3953 | if (!irq_received) | |
3954 | break; | |
3955 | ||
a266c7d5 | 3956 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
3957 | if (I915_HAS_HOTPLUG(dev) && |
3958 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
3959 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3960 | |
38bde180 | 3961 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3962 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3963 | ||
a266c7d5 CW |
3964 | if (iir & I915_USER_INTERRUPT) |
3965 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3966 | |
055e393f | 3967 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 3968 | int plane = pipe; |
3a77c4c4 | 3969 | if (HAS_FBC(dev)) |
38bde180 | 3970 | plane = !plane; |
90a72f87 | 3971 | |
8291ee90 | 3972 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3973 | i915_handle_vblank(dev, plane, pipe, iir)) |
3974 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3975 | |
3976 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3977 | blc_event = true; | |
4356d586 DV |
3978 | |
3979 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3980 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3981 | |
1f7247c0 DV |
3982 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3983 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3984 | pipe); | |
a266c7d5 CW |
3985 | } |
3986 | ||
a266c7d5 CW |
3987 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3988 | intel_opregion_asle_intr(dev); | |
3989 | ||
3990 | /* With MSI, interrupts are only generated when iir | |
3991 | * transitions from zero to nonzero. If another bit got | |
3992 | * set while we were handling the existing iir bits, then | |
3993 | * we would never get another interrupt. | |
3994 | * | |
3995 | * This is fine on non-MSI as well, as if we hit this path | |
3996 | * we avoid exiting the interrupt handler only to generate | |
3997 | * another one. | |
3998 | * | |
3999 | * Note that for MSI this could cause a stray interrupt report | |
4000 | * if an interrupt landed in the time between writing IIR and | |
4001 | * the posting read. This should be rare enough to never | |
4002 | * trigger the 99% of 100,000 interrupts test for disabling | |
4003 | * stray interrupts. | |
4004 | */ | |
38bde180 | 4005 | ret = IRQ_HANDLED; |
a266c7d5 | 4006 | iir = new_iir; |
38bde180 | 4007 | } while (iir & ~flip_mask); |
a266c7d5 | 4008 | |
d05c617e | 4009 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 4010 | |
a266c7d5 CW |
4011 | return ret; |
4012 | } | |
4013 | ||
4014 | static void i915_irq_uninstall(struct drm_device * dev) | |
4015 | { | |
2d1013dd | 4016 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4017 | int pipe; |
4018 | ||
a266c7d5 CW |
4019 | if (I915_HAS_HOTPLUG(dev)) { |
4020 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
4021 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
4022 | } | |
4023 | ||
00d98ebd | 4024 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 4025 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 4026 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 4027 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4028 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4029 | } | |
a266c7d5 CW |
4030 | I915_WRITE(IMR, 0xffffffff); |
4031 | I915_WRITE(IER, 0x0); | |
4032 | ||
a266c7d5 CW |
4033 | I915_WRITE(IIR, I915_READ(IIR)); |
4034 | } | |
4035 | ||
4036 | static void i965_irq_preinstall(struct drm_device * dev) | |
4037 | { | |
2d1013dd | 4038 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4039 | int pipe; |
4040 | ||
adca4730 CW |
4041 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4042 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4043 | |
4044 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4045 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4046 | I915_WRITE(PIPESTAT(pipe), 0); |
4047 | I915_WRITE(IMR, 0xffffffff); | |
4048 | I915_WRITE(IER, 0x0); | |
4049 | POSTING_READ(IER); | |
4050 | } | |
4051 | ||
4052 | static int i965_irq_postinstall(struct drm_device *dev) | |
4053 | { | |
2d1013dd | 4054 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4055 | u32 enable_mask; |
a266c7d5 CW |
4056 | u32 error_mask; |
4057 | ||
a266c7d5 | 4058 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4059 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4060 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4061 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4062 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4063 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4064 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4065 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4066 | ||
4067 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4068 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4069 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4070 | enable_mask |= I915_USER_INTERRUPT; |
4071 | ||
4072 | if (IS_G4X(dev)) | |
4073 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 4074 | |
b79480ba DV |
4075 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4076 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4077 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4078 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4079 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4080 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4081 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4082 | |
a266c7d5 CW |
4083 | /* |
4084 | * Enable some error detection, note the instruction error mask | |
4085 | * bit is reserved, so we leave it masked. | |
4086 | */ | |
4087 | if (IS_G4X(dev)) { | |
4088 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4089 | GM45_ERROR_MEM_PRIV | | |
4090 | GM45_ERROR_CP_PRIV | | |
4091 | I915_ERROR_MEMORY_REFRESH); | |
4092 | } else { | |
4093 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4094 | I915_ERROR_MEMORY_REFRESH); | |
4095 | } | |
4096 | I915_WRITE(EMR, error_mask); | |
4097 | ||
4098 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4099 | I915_WRITE(IER, enable_mask); | |
4100 | POSTING_READ(IER); | |
4101 | ||
20afbda2 DV |
4102 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4103 | POSTING_READ(PORT_HOTPLUG_EN); | |
4104 | ||
f49e38dd | 4105 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4106 | |
4107 | return 0; | |
4108 | } | |
4109 | ||
bac56d5b | 4110 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4111 | { |
2d1013dd | 4112 | struct drm_i915_private *dev_priv = dev->dev_private; |
cd569aed | 4113 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
4114 | u32 hotplug_en; |
4115 | ||
b5ea2d56 DV |
4116 | assert_spin_locked(&dev_priv->irq_lock); |
4117 | ||
bac56d5b EE |
4118 | if (I915_HAS_HOTPLUG(dev)) { |
4119 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
4120 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
4121 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 4122 | /* enable bits are the same for all generations */ |
b2784e15 | 4123 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed EE |
4124 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
4125 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
4126 | /* Programming the CRT detection parameters tends |
4127 | to generate a spurious hotplug event about three | |
4128 | seconds later. So just do it once. | |
4129 | */ | |
4130 | if (IS_G4X(dev)) | |
4131 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 4132 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 4133 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 4134 | |
bac56d5b EE |
4135 | /* Ignore TV since it's buggy */ |
4136 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
4137 | } | |
a266c7d5 CW |
4138 | } |
4139 | ||
ff1f525e | 4140 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4141 | { |
45a83f84 | 4142 | struct drm_device *dev = arg; |
2d1013dd | 4143 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4144 | u32 iir, new_iir; |
4145 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4146 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4147 | u32 flip_mask = |
4148 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4149 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4150 | |
a266c7d5 CW |
4151 | iir = I915_READ(IIR); |
4152 | ||
a266c7d5 | 4153 | for (;;) { |
501e01d7 | 4154 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4155 | bool blc_event = false; |
4156 | ||
a266c7d5 CW |
4157 | /* Can't rely on pipestat interrupt bit in iir as it might |
4158 | * have been cleared after the pipestat interrupt was received. | |
4159 | * It doesn't set the bit in iir again, but it still produces | |
4160 | * interrupts (for non-MSI). | |
4161 | */ | |
222c7f51 | 4162 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4163 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
58174462 MK |
4164 | i915_handle_error(dev, false, |
4165 | "Command parser error, iir 0x%08x", | |
4166 | iir); | |
a266c7d5 | 4167 | |
055e393f | 4168 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4169 | int reg = PIPESTAT(pipe); |
4170 | pipe_stats[pipe] = I915_READ(reg); | |
4171 | ||
4172 | /* | |
4173 | * Clear the PIPE*STAT regs before the IIR | |
4174 | */ | |
4175 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4176 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4177 | irq_received = true; |
a266c7d5 CW |
4178 | } |
4179 | } | |
222c7f51 | 4180 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4181 | |
4182 | if (!irq_received) | |
4183 | break; | |
4184 | ||
4185 | ret = IRQ_HANDLED; | |
4186 | ||
4187 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
4188 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
4189 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4190 | |
21ad8330 | 4191 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4192 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4193 | ||
a266c7d5 CW |
4194 | if (iir & I915_USER_INTERRUPT) |
4195 | notify_ring(dev, &dev_priv->ring[RCS]); | |
4196 | if (iir & I915_BSD_USER_INTERRUPT) | |
4197 | notify_ring(dev, &dev_priv->ring[VCS]); | |
4198 | ||
055e393f | 4199 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 4200 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4201 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4202 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4203 | |
4204 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4205 | blc_event = true; | |
4356d586 DV |
4206 | |
4207 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4208 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4209 | |
1f7247c0 DV |
4210 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4211 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4212 | } |
a266c7d5 CW |
4213 | |
4214 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4215 | intel_opregion_asle_intr(dev); | |
4216 | ||
515ac2bb DV |
4217 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4218 | gmbus_irq_handler(dev); | |
4219 | ||
a266c7d5 CW |
4220 | /* With MSI, interrupts are only generated when iir |
4221 | * transitions from zero to nonzero. If another bit got | |
4222 | * set while we were handling the existing iir bits, then | |
4223 | * we would never get another interrupt. | |
4224 | * | |
4225 | * This is fine on non-MSI as well, as if we hit this path | |
4226 | * we avoid exiting the interrupt handler only to generate | |
4227 | * another one. | |
4228 | * | |
4229 | * Note that for MSI this could cause a stray interrupt report | |
4230 | * if an interrupt landed in the time between writing IIR and | |
4231 | * the posting read. This should be rare enough to never | |
4232 | * trigger the 99% of 100,000 interrupts test for disabling | |
4233 | * stray interrupts. | |
4234 | */ | |
4235 | iir = new_iir; | |
4236 | } | |
4237 | ||
d05c617e | 4238 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 4239 | |
a266c7d5 CW |
4240 | return ret; |
4241 | } | |
4242 | ||
4243 | static void i965_irq_uninstall(struct drm_device * dev) | |
4244 | { | |
2d1013dd | 4245 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4246 | int pipe; |
4247 | ||
4248 | if (!dev_priv) | |
4249 | return; | |
4250 | ||
adca4730 CW |
4251 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4252 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4253 | |
4254 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4255 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4256 | I915_WRITE(PIPESTAT(pipe), 0); |
4257 | I915_WRITE(IMR, 0xffffffff); | |
4258 | I915_WRITE(IER, 0x0); | |
4259 | ||
055e393f | 4260 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4261 | I915_WRITE(PIPESTAT(pipe), |
4262 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4263 | I915_WRITE(IIR, I915_READ(IIR)); | |
4264 | } | |
4265 | ||
4cb21832 | 4266 | static void intel_hpd_irq_reenable_work(struct work_struct *work) |
ac4c16c5 | 4267 | { |
6323751d ID |
4268 | struct drm_i915_private *dev_priv = |
4269 | container_of(work, typeof(*dev_priv), | |
4270 | hotplug_reenable_work.work); | |
ac4c16c5 EE |
4271 | struct drm_device *dev = dev_priv->dev; |
4272 | struct drm_mode_config *mode_config = &dev->mode_config; | |
ac4c16c5 EE |
4273 | int i; |
4274 | ||
6323751d ID |
4275 | intel_runtime_pm_get(dev_priv); |
4276 | ||
4cb21832 | 4277 | spin_lock_irq(&dev_priv->irq_lock); |
ac4c16c5 EE |
4278 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
4279 | struct drm_connector *connector; | |
4280 | ||
4281 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
4282 | continue; | |
4283 | ||
4284 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4285 | ||
4286 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4287 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4288 | ||
4289 | if (intel_connector->encoder->hpd_pin == i) { | |
4290 | if (connector->polled != intel_connector->polled) | |
4291 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
c23cc417 | 4292 | connector->name); |
ac4c16c5 EE |
4293 | connector->polled = intel_connector->polled; |
4294 | if (!connector->polled) | |
4295 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4296 | } | |
4297 | } | |
4298 | } | |
4299 | if (dev_priv->display.hpd_irq_setup) | |
4300 | dev_priv->display.hpd_irq_setup(dev); | |
4cb21832 | 4301 | spin_unlock_irq(&dev_priv->irq_lock); |
6323751d ID |
4302 | |
4303 | intel_runtime_pm_put(dev_priv); | |
ac4c16c5 EE |
4304 | } |
4305 | ||
fca52a55 DV |
4306 | /** |
4307 | * intel_irq_init - initializes irq support | |
4308 | * @dev_priv: i915 device instance | |
4309 | * | |
4310 | * This function initializes all the irq support including work items, timers | |
4311 | * and all the vtables. It does not setup the interrupt itself though. | |
4312 | */ | |
b963291c | 4313 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4314 | { |
b963291c | 4315 | struct drm_device *dev = dev_priv->dev; |
8b2e326d CW |
4316 | |
4317 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
13cf5504 | 4318 | INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func); |
99584db3 | 4319 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 4320 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4321 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4322 | |
a6706b45 | 4323 | /* Let's track the enabled rps events */ |
b963291c | 4324 | if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6c65a587 | 4325 | /* WaGsvRC0ResidencyMethod:vlv */ |
31685c25 D |
4326 | dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; |
4327 | else | |
4328 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4329 | |
99584db3 DV |
4330 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
4331 | i915_hangcheck_elapsed, | |
61bac78e | 4332 | (unsigned long) dev); |
6323751d | 4333 | INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, |
4cb21832 | 4334 | intel_hpd_irq_reenable_work); |
61bac78e | 4335 | |
97a19a24 | 4336 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4337 | |
b963291c | 4338 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4339 | dev->max_vblank_count = 0; |
4340 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4341 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 JB |
4342 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4343 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4344 | } else { |
4345 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4346 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4347 | } |
4348 | ||
21da2700 VS |
4349 | /* |
4350 | * Opt out of the vblank disable timer on everything except gen2. | |
4351 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4352 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4353 | */ | |
b963291c | 4354 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4355 | dev->vblank_disable_immediate = true; |
4356 | ||
c2baf4b7 | 4357 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 4358 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
4359 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
4360 | } | |
f71d4af4 | 4361 | |
b963291c | 4362 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4363 | dev->driver->irq_handler = cherryview_irq_handler; |
4364 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4365 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4366 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4367 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4368 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4369 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4370 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4371 | dev->driver->irq_handler = valleyview_irq_handler; |
4372 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4373 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4374 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4375 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4376 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4377 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4378 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4379 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4380 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4381 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4382 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4383 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4384 | dev->driver->disable_vblank = gen8_disable_vblank; | |
4385 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
4386 | } else if (HAS_PCH_SPLIT(dev)) { |
4387 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4388 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4389 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4390 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4391 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4392 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4393 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4394 | } else { |
b963291c | 4395 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4396 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4397 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4398 | dev->driver->irq_handler = i8xx_irq_handler; | |
4399 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4400 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4401 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4402 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4403 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4404 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 4405 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4406 | } else { |
a266c7d5 CW |
4407 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4408 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4409 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4410 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 4411 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4412 | } |
f71d4af4 JB |
4413 | dev->driver->enable_vblank = i915_enable_vblank; |
4414 | dev->driver->disable_vblank = i915_disable_vblank; | |
4415 | } | |
4416 | } | |
20afbda2 | 4417 | |
fca52a55 DV |
4418 | /** |
4419 | * intel_hpd_init - initializes and enables hpd support | |
4420 | * @dev_priv: i915 device instance | |
4421 | * | |
4422 | * This function enables the hotplug support. It requires that interrupts have | |
4423 | * already been enabled with intel_irq_init_hw(). From this point on hotplug and | |
4424 | * poll request can run concurrently to other code, so locking rules must be | |
4425 | * obeyed. | |
4426 | * | |
4427 | * This is a separate step from interrupt enabling to simplify the locking rules | |
4428 | * in the driver load and resume code. | |
4429 | */ | |
b963291c | 4430 | void intel_hpd_init(struct drm_i915_private *dev_priv) |
20afbda2 | 4431 | { |
b963291c | 4432 | struct drm_device *dev = dev_priv->dev; |
821450c6 EE |
4433 | struct drm_mode_config *mode_config = &dev->mode_config; |
4434 | struct drm_connector *connector; | |
4435 | int i; | |
20afbda2 | 4436 | |
821450c6 EE |
4437 | for (i = 1; i < HPD_NUM_PINS; i++) { |
4438 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
4439 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4440 | } | |
4441 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4442 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4443 | connector->polled = intel_connector->polled; | |
0e32b39c DA |
4444 | if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) |
4445 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4446 | if (intel_connector->mst_port) | |
821450c6 EE |
4447 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
4448 | } | |
b5ea2d56 DV |
4449 | |
4450 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
4451 | * just to make the assert_spin_locked checks happy. */ | |
d6207435 | 4452 | spin_lock_irq(&dev_priv->irq_lock); |
20afbda2 DV |
4453 | if (dev_priv->display.hpd_irq_setup) |
4454 | dev_priv->display.hpd_irq_setup(dev); | |
d6207435 | 4455 | spin_unlock_irq(&dev_priv->irq_lock); |
20afbda2 | 4456 | } |
c67a470b | 4457 | |
fca52a55 DV |
4458 | /** |
4459 | * intel_irq_install - enables the hardware interrupt | |
4460 | * @dev_priv: i915 device instance | |
4461 | * | |
4462 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4463 | * handling still disabled. It is called after intel_irq_init(). | |
4464 | * | |
4465 | * In the driver load and resume code we need working interrupts in a few places | |
4466 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4467 | * workers. Hence the split into this two-stage approach. | |
4468 | */ | |
2aeb7d3a DV |
4469 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4470 | { | |
4471 | /* | |
4472 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4473 | * interrupts as enabled _before_ actually enabling them to avoid | |
4474 | * special cases in our ordering checks. | |
4475 | */ | |
4476 | dev_priv->pm.irqs_enabled = true; | |
4477 | ||
4478 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4479 | } | |
4480 | ||
fca52a55 DV |
4481 | /** |
4482 | * intel_irq_uninstall - finilizes all irq handling | |
4483 | * @dev_priv: i915 device instance | |
4484 | * | |
4485 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4486 | * resources acquired in the init functions. | |
4487 | */ | |
2aeb7d3a DV |
4488 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4489 | { | |
4490 | drm_irq_uninstall(dev_priv->dev); | |
4491 | intel_hpd_cancel_work(dev_priv); | |
4492 | dev_priv->pm.irqs_enabled = false; | |
4493 | } | |
4494 | ||
fca52a55 DV |
4495 | /** |
4496 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4497 | * @dev_priv: i915 device instance | |
4498 | * | |
4499 | * This function is used to disable interrupts at runtime, both in the runtime | |
4500 | * pm and the system suspend/resume code. | |
4501 | */ | |
b963291c | 4502 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4503 | { |
b963291c | 4504 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4505 | dev_priv->pm.irqs_enabled = false; |
c67a470b PZ |
4506 | } |
4507 | ||
fca52a55 DV |
4508 | /** |
4509 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4510 | * @dev_priv: i915 device instance | |
4511 | * | |
4512 | * This function is used to enable interrupts at runtime, both in the runtime | |
4513 | * pm and the system suspend/resume code. | |
4514 | */ | |
b963291c | 4515 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4516 | { |
2aeb7d3a | 4517 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4518 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4519 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4520 | } |