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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/i915_drm.h> | |
1da177e4 | 35 | #include "i915_drv.h" |
1c5d22f7 | 36 | #include "i915_trace.h" |
79e53945 | 37 | #include "intel_drv.h" |
1da177e4 | 38 | |
e5868a31 EE |
39 | static const u32 hpd_ibx[] = { |
40 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
41 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
42 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
43 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
44 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
45 | }; | |
46 | ||
47 | static const u32 hpd_cpt[] = { | |
48 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 49 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
50 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
51 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
52 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
53 | }; | |
54 | ||
55 | static const u32 hpd_mask_i915[] = { | |
56 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
57 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
58 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
59 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
60 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
61 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
62 | }; | |
63 | ||
64 | static const u32 hpd_status_gen4[] = { | |
65 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
71 | }; | |
72 | ||
73 | static const u32 hpd_status_i965[] = { | |
74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965, | |
76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965, | |
77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
80 | }; | |
81 | ||
82 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ | |
83 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
84 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
85 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
86 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
87 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
88 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
89 | }; | |
90 | ||
cd569aed EE |
91 | static void ibx_hpd_irq_setup(struct drm_device *dev); |
92 | static void i915_hpd_irq_setup(struct drm_device *dev); | |
e5868a31 | 93 | |
036a4a7d | 94 | /* For display hotplug interrupt */ |
995b6762 | 95 | static void |
f2b115e6 | 96 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 97 | { |
1ec14ad3 CW |
98 | if ((dev_priv->irq_mask & mask) != 0) { |
99 | dev_priv->irq_mask &= ~mask; | |
100 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 101 | POSTING_READ(DEIMR); |
036a4a7d ZW |
102 | } |
103 | } | |
104 | ||
0ff9800a | 105 | static void |
f2b115e6 | 106 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 107 | { |
1ec14ad3 CW |
108 | if ((dev_priv->irq_mask & mask) != mask) { |
109 | dev_priv->irq_mask |= mask; | |
110 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 111 | POSTING_READ(DEIMR); |
036a4a7d ZW |
112 | } |
113 | } | |
114 | ||
8664281b PZ |
115 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
116 | { | |
117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
118 | struct intel_crtc *crtc; | |
119 | enum pipe pipe; | |
120 | ||
121 | for_each_pipe(pipe) { | |
122 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
123 | ||
124 | if (crtc->cpu_fifo_underrun_disabled) | |
125 | return false; | |
126 | } | |
127 | ||
128 | return true; | |
129 | } | |
130 | ||
131 | static bool cpt_can_enable_serr_int(struct drm_device *dev) | |
132 | { | |
133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
134 | enum pipe pipe; | |
135 | struct intel_crtc *crtc; | |
136 | ||
137 | for_each_pipe(pipe) { | |
138 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
139 | ||
140 | if (crtc->pch_fifo_underrun_disabled) | |
141 | return false; | |
142 | } | |
143 | ||
144 | return true; | |
145 | } | |
146 | ||
147 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, | |
148 | enum pipe pipe, bool enable) | |
149 | { | |
150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
151 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : | |
152 | DE_PIPEB_FIFO_UNDERRUN; | |
153 | ||
154 | if (enable) | |
155 | ironlake_enable_display_irq(dev_priv, bit); | |
156 | else | |
157 | ironlake_disable_display_irq(dev_priv, bit); | |
158 | } | |
159 | ||
160 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, | |
161 | bool enable) | |
162 | { | |
163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
164 | ||
165 | if (enable) { | |
166 | if (!ivb_can_enable_err_int(dev)) | |
167 | return; | |
168 | ||
169 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A | | |
170 | ERR_INT_FIFO_UNDERRUN_B | | |
171 | ERR_INT_FIFO_UNDERRUN_C); | |
172 | ||
173 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); | |
174 | } else { | |
175 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); | |
176 | } | |
177 | } | |
178 | ||
179 | static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc, | |
180 | bool enable) | |
181 | { | |
182 | struct drm_device *dev = crtc->base.dev; | |
183 | struct drm_i915_private *dev_priv = dev->dev_private; | |
184 | uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER : | |
185 | SDE_TRANSB_FIFO_UNDER; | |
186 | ||
187 | if (enable) | |
188 | I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit); | |
189 | else | |
190 | I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit); | |
191 | ||
192 | POSTING_READ(SDEIMR); | |
193 | } | |
194 | ||
195 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, | |
196 | enum transcoder pch_transcoder, | |
197 | bool enable) | |
198 | { | |
199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
200 | ||
201 | if (enable) { | |
202 | if (!cpt_can_enable_serr_int(dev)) | |
203 | return; | |
204 | ||
205 | I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN | | |
206 | SERR_INT_TRANS_B_FIFO_UNDERRUN | | |
207 | SERR_INT_TRANS_C_FIFO_UNDERRUN); | |
208 | ||
209 | I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT); | |
210 | } else { | |
211 | I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT); | |
212 | } | |
213 | ||
214 | POSTING_READ(SDEIMR); | |
215 | } | |
216 | ||
217 | /** | |
218 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
219 | * @dev: drm device | |
220 | * @pipe: pipe | |
221 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
222 | * | |
223 | * This function makes us disable or enable CPU fifo underruns for a specific | |
224 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun | |
225 | * reporting for one pipe may also disable all the other CPU error interruts for | |
226 | * the other pipes, due to the fact that there's just one interrupt mask/enable | |
227 | * bit for all the pipes. | |
228 | * | |
229 | * Returns the previous state of underrun reporting. | |
230 | */ | |
231 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, | |
232 | enum pipe pipe, bool enable) | |
233 | { | |
234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
235 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
236 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
237 | unsigned long flags; | |
238 | bool ret; | |
239 | ||
240 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
241 | ||
242 | ret = !intel_crtc->cpu_fifo_underrun_disabled; | |
243 | ||
244 | if (enable == ret) | |
245 | goto done; | |
246 | ||
247 | intel_crtc->cpu_fifo_underrun_disabled = !enable; | |
248 | ||
249 | if (IS_GEN5(dev) || IS_GEN6(dev)) | |
250 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); | |
251 | else if (IS_GEN7(dev)) | |
252 | ivybridge_set_fifo_underrun_reporting(dev, enable); | |
253 | ||
254 | done: | |
255 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
256 | return ret; | |
257 | } | |
258 | ||
259 | /** | |
260 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
261 | * @dev: drm device | |
262 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
263 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
264 | * | |
265 | * This function makes us disable or enable PCH fifo underruns for a specific | |
266 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
267 | * underrun reporting for one transcoder may also disable all the other PCH | |
268 | * error interruts for the other transcoders, due to the fact that there's just | |
269 | * one interrupt mask/enable bit for all the transcoders. | |
270 | * | |
271 | * Returns the previous state of underrun reporting. | |
272 | */ | |
273 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
274 | enum transcoder pch_transcoder, | |
275 | bool enable) | |
276 | { | |
277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
278 | enum pipe p; | |
279 | struct drm_crtc *crtc; | |
280 | struct intel_crtc *intel_crtc; | |
281 | unsigned long flags; | |
282 | bool ret; | |
283 | ||
284 | if (HAS_PCH_LPT(dev)) { | |
285 | crtc = NULL; | |
286 | for_each_pipe(p) { | |
287 | struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p]; | |
288 | if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) { | |
289 | crtc = c; | |
290 | break; | |
291 | } | |
292 | } | |
293 | if (!crtc) { | |
294 | DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n"); | |
295 | return false; | |
296 | } | |
297 | } else { | |
298 | crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; | |
299 | } | |
300 | intel_crtc = to_intel_crtc(crtc); | |
301 | ||
302 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
303 | ||
304 | ret = !intel_crtc->pch_fifo_underrun_disabled; | |
305 | ||
306 | if (enable == ret) | |
307 | goto done; | |
308 | ||
309 | intel_crtc->pch_fifo_underrun_disabled = !enable; | |
310 | ||
311 | if (HAS_PCH_IBX(dev)) | |
312 | ibx_set_fifo_underrun_reporting(intel_crtc, enable); | |
313 | else | |
314 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); | |
315 | ||
316 | done: | |
317 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
318 | return ret; | |
319 | } | |
320 | ||
321 | ||
7c463586 KP |
322 | void |
323 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
324 | { | |
46c06a30 VS |
325 | u32 reg = PIPESTAT(pipe); |
326 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
7c463586 | 327 | |
46c06a30 VS |
328 | if ((pipestat & mask) == mask) |
329 | return; | |
330 | ||
331 | /* Enable the interrupt, clear any pending status */ | |
332 | pipestat |= mask | (mask >> 16); | |
333 | I915_WRITE(reg, pipestat); | |
334 | POSTING_READ(reg); | |
7c463586 KP |
335 | } |
336 | ||
337 | void | |
338 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
339 | { | |
46c06a30 VS |
340 | u32 reg = PIPESTAT(pipe); |
341 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
7c463586 | 342 | |
46c06a30 VS |
343 | if ((pipestat & mask) == 0) |
344 | return; | |
345 | ||
346 | pipestat &= ~mask; | |
347 | I915_WRITE(reg, pipestat); | |
348 | POSTING_READ(reg); | |
7c463586 KP |
349 | } |
350 | ||
01c66889 | 351 | /** |
f49e38dd | 352 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 353 | */ |
f49e38dd | 354 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 355 | { |
1ec14ad3 CW |
356 | drm_i915_private_t *dev_priv = dev->dev_private; |
357 | unsigned long irqflags; | |
358 | ||
f49e38dd JN |
359 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
360 | return; | |
361 | ||
1ec14ad3 | 362 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 363 | |
f898780b JN |
364 | i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE); |
365 | if (INTEL_INFO(dev)->gen >= 4) | |
366 | i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE); | |
1ec14ad3 CW |
367 | |
368 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
369 | } |
370 | ||
0a3e67a4 JB |
371 | /** |
372 | * i915_pipe_enabled - check if a pipe is enabled | |
373 | * @dev: DRM device | |
374 | * @pipe: pipe to check | |
375 | * | |
376 | * Reading certain registers when the pipe is disabled can hang the chip. | |
377 | * Use this routine to make sure the PLL is running and the pipe is active | |
378 | * before reading such registers if unsure. | |
379 | */ | |
380 | static int | |
381 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
382 | { | |
383 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
702e7a56 | 384 | |
a01025af DV |
385 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
386 | /* Locking is horribly broken here, but whatever. */ | |
387 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
388 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 389 | |
a01025af DV |
390 | return intel_crtc->active; |
391 | } else { | |
392 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
393 | } | |
0a3e67a4 JB |
394 | } |
395 | ||
42f52ef8 KP |
396 | /* Called from drm generic code, passed a 'crtc', which |
397 | * we use as a pipe index | |
398 | */ | |
f71d4af4 | 399 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
400 | { |
401 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
402 | unsigned long high_frame; | |
403 | unsigned long low_frame; | |
5eddb70b | 404 | u32 high1, high2, low; |
0a3e67a4 JB |
405 | |
406 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 407 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 408 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
409 | return 0; |
410 | } | |
411 | ||
9db4a9c7 JB |
412 | high_frame = PIPEFRAME(pipe); |
413 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 414 | |
0a3e67a4 JB |
415 | /* |
416 | * High & low register fields aren't synchronized, so make sure | |
417 | * we get a low value that's stable across two reads of the high | |
418 | * register. | |
419 | */ | |
420 | do { | |
5eddb70b CW |
421 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
422 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; | |
423 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
424 | } while (high1 != high2); |
425 | ||
5eddb70b CW |
426 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
427 | low >>= PIPE_FRAME_LOW_SHIFT; | |
428 | return (high1 << 8) | low; | |
0a3e67a4 JB |
429 | } |
430 | ||
f71d4af4 | 431 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 JB |
432 | { |
433 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 434 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
435 | |
436 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 437 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 438 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
439 | return 0; |
440 | } | |
441 | ||
442 | return I915_READ(reg); | |
443 | } | |
444 | ||
f71d4af4 | 445 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
0af7e4df MK |
446 | int *vpos, int *hpos) |
447 | { | |
448 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
449 | u32 vbl = 0, position = 0; | |
450 | int vbl_start, vbl_end, htotal, vtotal; | |
451 | bool in_vbl = true; | |
452 | int ret = 0; | |
fe2b8f9d PZ |
453 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
454 | pipe); | |
0af7e4df MK |
455 | |
456 | if (!i915_pipe_enabled(dev, pipe)) { | |
457 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " | |
9db4a9c7 | 458 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
459 | return 0; |
460 | } | |
461 | ||
462 | /* Get vtotal. */ | |
fe2b8f9d | 463 | vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff); |
0af7e4df MK |
464 | |
465 | if (INTEL_INFO(dev)->gen >= 4) { | |
466 | /* No obvious pixelcount register. Only query vertical | |
467 | * scanout position from Display scan line register. | |
468 | */ | |
469 | position = I915_READ(PIPEDSL(pipe)); | |
470 | ||
471 | /* Decode into vertical scanout position. Don't have | |
472 | * horizontal scanout position. | |
473 | */ | |
474 | *vpos = position & 0x1fff; | |
475 | *hpos = 0; | |
476 | } else { | |
477 | /* Have access to pixelcount since start of frame. | |
478 | * We can split this into vertical and horizontal | |
479 | * scanout position. | |
480 | */ | |
481 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; | |
482 | ||
fe2b8f9d | 483 | htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff); |
0af7e4df MK |
484 | *vpos = position / htotal; |
485 | *hpos = position - (*vpos * htotal); | |
486 | } | |
487 | ||
488 | /* Query vblank area. */ | |
fe2b8f9d | 489 | vbl = I915_READ(VBLANK(cpu_transcoder)); |
0af7e4df MK |
490 | |
491 | /* Test position against vblank region. */ | |
492 | vbl_start = vbl & 0x1fff; | |
493 | vbl_end = (vbl >> 16) & 0x1fff; | |
494 | ||
495 | if ((*vpos < vbl_start) || (*vpos > vbl_end)) | |
496 | in_vbl = false; | |
497 | ||
498 | /* Inside "upper part" of vblank area? Apply corrective offset: */ | |
499 | if (in_vbl && (*vpos >= vbl_start)) | |
500 | *vpos = *vpos - vtotal; | |
501 | ||
502 | /* Readouts valid? */ | |
503 | if (vbl > 0) | |
504 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; | |
505 | ||
506 | /* In vblank? */ | |
507 | if (in_vbl) | |
508 | ret |= DRM_SCANOUTPOS_INVBL; | |
509 | ||
510 | return ret; | |
511 | } | |
512 | ||
f71d4af4 | 513 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
514 | int *max_error, |
515 | struct timeval *vblank_time, | |
516 | unsigned flags) | |
517 | { | |
4041b853 | 518 | struct drm_crtc *crtc; |
0af7e4df | 519 | |
7eb552ae | 520 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 521 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
522 | return -EINVAL; |
523 | } | |
524 | ||
525 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
526 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
527 | if (crtc == NULL) { | |
528 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
529 | return -EINVAL; | |
530 | } | |
531 | ||
532 | if (!crtc->enabled) { | |
533 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
534 | return -EBUSY; | |
535 | } | |
0af7e4df MK |
536 | |
537 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
538 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
539 | vblank_time, flags, | |
540 | crtc); | |
0af7e4df MK |
541 | } |
542 | ||
321a1b30 EE |
543 | static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector) |
544 | { | |
545 | enum drm_connector_status old_status; | |
546 | ||
547 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
548 | old_status = connector->status; | |
549 | ||
550 | connector->status = connector->funcs->detect(connector, false); | |
551 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n", | |
552 | connector->base.id, | |
553 | drm_get_connector_name(connector), | |
554 | old_status, connector->status); | |
555 | return (old_status != connector->status); | |
556 | } | |
557 | ||
5ca58282 JB |
558 | /* |
559 | * Handle hotplug events outside the interrupt handler proper. | |
560 | */ | |
ac4c16c5 EE |
561 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
562 | ||
5ca58282 JB |
563 | static void i915_hotplug_work_func(struct work_struct *work) |
564 | { | |
565 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
566 | hotplug_work); | |
567 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 568 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
569 | struct intel_connector *intel_connector; |
570 | struct intel_encoder *intel_encoder; | |
571 | struct drm_connector *connector; | |
572 | unsigned long irqflags; | |
573 | bool hpd_disabled = false; | |
321a1b30 | 574 | bool changed = false; |
142e2398 | 575 | u32 hpd_event_bits; |
4ef69c7a | 576 | |
52d7eced DV |
577 | /* HPD irq before everything is fully set up. */ |
578 | if (!dev_priv->enable_hotplug_processing) | |
579 | return; | |
580 | ||
a65e34c7 | 581 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
582 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
583 | ||
cd569aed | 584 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
142e2398 EE |
585 | |
586 | hpd_event_bits = dev_priv->hpd_event_bits; | |
587 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
588 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
589 | intel_connector = to_intel_connector(connector); | |
590 | intel_encoder = intel_connector->encoder; | |
591 | if (intel_encoder->hpd_pin > HPD_NONE && | |
592 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
593 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
594 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
595 | "switching from hotplug detection to polling\n", | |
596 | drm_get_connector_name(connector)); | |
597 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; | |
598 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
599 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
600 | hpd_disabled = true; | |
601 | } | |
142e2398 EE |
602 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
603 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
604 | drm_get_connector_name(connector), intel_encoder->hpd_pin); | |
605 | } | |
cd569aed EE |
606 | } |
607 | /* if there were no outputs to poll, poll was disabled, | |
608 | * therefore make sure it's enabled when disabling HPD on | |
609 | * some connectors */ | |
ac4c16c5 | 610 | if (hpd_disabled) { |
cd569aed | 611 | drm_kms_helper_poll_enable(dev); |
ac4c16c5 EE |
612 | mod_timer(&dev_priv->hotplug_reenable_timer, |
613 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
614 | } | |
cd569aed EE |
615 | |
616 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
617 | ||
321a1b30 EE |
618 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
619 | intel_connector = to_intel_connector(connector); | |
620 | intel_encoder = intel_connector->encoder; | |
621 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
622 | if (intel_encoder->hot_plug) | |
623 | intel_encoder->hot_plug(intel_encoder); | |
624 | if (intel_hpd_irq_event(dev, connector)) | |
625 | changed = true; | |
626 | } | |
627 | } | |
40ee3381 KP |
628 | mutex_unlock(&mode_config->mutex); |
629 | ||
321a1b30 EE |
630 | if (changed) |
631 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
632 | } |
633 | ||
73edd18f | 634 | static void ironlake_handle_rps_change(struct drm_device *dev) |
f97108d1 JB |
635 | { |
636 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 637 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e DV |
638 | u8 new_delay; |
639 | unsigned long flags; | |
640 | ||
641 | spin_lock_irqsave(&mchdev_lock, flags); | |
f97108d1 | 642 | |
73edd18f DV |
643 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
644 | ||
20e4d407 | 645 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 646 | |
7648fa99 | 647 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
648 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
649 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
650 | max_avg = I915_READ(RCBMAXAVG); |
651 | min_avg = I915_READ(RCBMINAVG); | |
652 | ||
653 | /* Handle RCS change request from hw */ | |
b5b72e89 | 654 | if (busy_up > max_avg) { |
20e4d407 DV |
655 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
656 | new_delay = dev_priv->ips.cur_delay - 1; | |
657 | if (new_delay < dev_priv->ips.max_delay) | |
658 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 659 | } else if (busy_down < min_avg) { |
20e4d407 DV |
660 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
661 | new_delay = dev_priv->ips.cur_delay + 1; | |
662 | if (new_delay > dev_priv->ips.min_delay) | |
663 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
664 | } |
665 | ||
7648fa99 | 666 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 667 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 668 | |
9270388e DV |
669 | spin_unlock_irqrestore(&mchdev_lock, flags); |
670 | ||
f97108d1 JB |
671 | return; |
672 | } | |
673 | ||
549f7365 CW |
674 | static void notify_ring(struct drm_device *dev, |
675 | struct intel_ring_buffer *ring) | |
676 | { | |
677 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9862e600 | 678 | |
475553de CW |
679 | if (ring->obj == NULL) |
680 | return; | |
681 | ||
b2eadbc8 | 682 | trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false)); |
9862e600 | 683 | |
549f7365 | 684 | wake_up_all(&ring->irq_queue); |
3e0dc6b0 | 685 | if (i915_enable_hangcheck) { |
99584db3 | 686 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
cecc21fe | 687 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
3e0dc6b0 | 688 | } |
549f7365 CW |
689 | } |
690 | ||
4912d041 | 691 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 692 | { |
4912d041 | 693 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
c6a828d3 | 694 | rps.work); |
4912d041 | 695 | u32 pm_iir, pm_imr; |
7b9e0ae6 | 696 | u8 new_delay; |
4912d041 | 697 | |
c6a828d3 DV |
698 | spin_lock_irq(&dev_priv->rps.lock); |
699 | pm_iir = dev_priv->rps.pm_iir; | |
700 | dev_priv->rps.pm_iir = 0; | |
4912d041 | 701 | pm_imr = I915_READ(GEN6_PMIMR); |
4848405c BW |
702 | /* Make sure not to corrupt PMIMR state used by ringbuffer code */ |
703 | I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS); | |
c6a828d3 | 704 | spin_unlock_irq(&dev_priv->rps.lock); |
3b8d8d91 | 705 | |
4848405c | 706 | if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0) |
3b8d8d91 JB |
707 | return; |
708 | ||
4fc688ce | 709 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 CW |
710 | |
711 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) | |
c6a828d3 | 712 | new_delay = dev_priv->rps.cur_delay + 1; |
7b9e0ae6 | 713 | else |
c6a828d3 | 714 | new_delay = dev_priv->rps.cur_delay - 1; |
3b8d8d91 | 715 | |
79249636 BW |
716 | /* sysfs frequency interfaces may have snuck in while servicing the |
717 | * interrupt | |
718 | */ | |
719 | if (!(new_delay > dev_priv->rps.max_delay || | |
720 | new_delay < dev_priv->rps.min_delay)) { | |
0a073b84 JB |
721 | if (IS_VALLEYVIEW(dev_priv->dev)) |
722 | valleyview_set_rps(dev_priv->dev, new_delay); | |
723 | else | |
724 | gen6_set_rps(dev_priv->dev, new_delay); | |
79249636 | 725 | } |
3b8d8d91 | 726 | |
52ceb908 JB |
727 | if (IS_VALLEYVIEW(dev_priv->dev)) { |
728 | /* | |
729 | * On VLV, when we enter RC6 we may not be at the minimum | |
730 | * voltage level, so arm a timer to check. It should only | |
731 | * fire when there's activity or once after we've entered | |
732 | * RC6, and then won't be re-armed until the next RPS interrupt. | |
733 | */ | |
734 | mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work, | |
735 | msecs_to_jiffies(100)); | |
736 | } | |
737 | ||
4fc688ce | 738 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
739 | } |
740 | ||
e3689190 BW |
741 | |
742 | /** | |
743 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
744 | * occurred. | |
745 | * @work: workqueue struct | |
746 | * | |
747 | * Doesn't actually do anything except notify userspace. As a consequence of | |
748 | * this event, userspace should try to remap the bad rows since statistically | |
749 | * it is likely the same row is more likely to go bad again. | |
750 | */ | |
751 | static void ivybridge_parity_work(struct work_struct *work) | |
752 | { | |
753 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
a4da4fa4 | 754 | l3_parity.error_work); |
e3689190 BW |
755 | u32 error_status, row, bank, subbank; |
756 | char *parity_event[5]; | |
757 | uint32_t misccpctl; | |
758 | unsigned long flags; | |
759 | ||
760 | /* We must turn off DOP level clock gating to access the L3 registers. | |
761 | * In order to prevent a get/put style interface, acquire struct mutex | |
762 | * any time we access those registers. | |
763 | */ | |
764 | mutex_lock(&dev_priv->dev->struct_mutex); | |
765 | ||
766 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
767 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
768 | POSTING_READ(GEN7_MISCCPCTL); | |
769 | ||
770 | error_status = I915_READ(GEN7_L3CDERRST1); | |
771 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
772 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
773 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
774 | ||
775 | I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID | | |
776 | GEN7_L3CDERRST1_ENABLE); | |
777 | POSTING_READ(GEN7_L3CDERRST1); | |
778 | ||
779 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
780 | ||
781 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
cc609d5d | 782 | dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
e3689190 BW |
783 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
784 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
785 | ||
786 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
787 | ||
788 | parity_event[0] = "L3_PARITY_ERROR=1"; | |
789 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
790 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
791 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
792 | parity_event[4] = NULL; | |
793 | ||
794 | kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj, | |
795 | KOBJ_CHANGE, parity_event); | |
796 | ||
797 | DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n", | |
798 | row, bank, subbank); | |
799 | ||
800 | kfree(parity_event[3]); | |
801 | kfree(parity_event[2]); | |
802 | kfree(parity_event[1]); | |
803 | } | |
804 | ||
d2ba8470 | 805 | static void ivybridge_handle_parity_error(struct drm_device *dev) |
e3689190 BW |
806 | { |
807 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
808 | unsigned long flags; | |
809 | ||
e1ef7cc2 | 810 | if (!HAS_L3_GPU_CACHE(dev)) |
e3689190 BW |
811 | return; |
812 | ||
813 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
cc609d5d | 814 | dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
e3689190 BW |
815 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
816 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
817 | ||
a4da4fa4 | 818 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
819 | } |
820 | ||
e7b4c6b1 DV |
821 | static void snb_gt_irq_handler(struct drm_device *dev, |
822 | struct drm_i915_private *dev_priv, | |
823 | u32 gt_iir) | |
824 | { | |
825 | ||
cc609d5d BW |
826 | if (gt_iir & |
827 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 828 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 829 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 830 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 831 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
832 | notify_ring(dev, &dev_priv->ring[BCS]); |
833 | ||
cc609d5d BW |
834 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
835 | GT_BSD_CS_ERROR_INTERRUPT | | |
836 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
e7b4c6b1 DV |
837 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); |
838 | i915_handle_error(dev, false); | |
839 | } | |
e3689190 | 840 | |
cc609d5d | 841 | if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) |
e3689190 | 842 | ivybridge_handle_parity_error(dev); |
e7b4c6b1 DV |
843 | } |
844 | ||
baf02a1f | 845 | /* Legacy way of handling PM interrupts */ |
fc6826d1 CW |
846 | static void gen6_queue_rps_work(struct drm_i915_private *dev_priv, |
847 | u32 pm_iir) | |
848 | { | |
849 | unsigned long flags; | |
850 | ||
851 | /* | |
852 | * IIR bits should never already be set because IMR should | |
853 | * prevent an interrupt from being shown in IIR. The warning | |
854 | * displays a case where we've unsafely cleared | |
c6a828d3 | 855 | * dev_priv->rps.pm_iir. Although missing an interrupt of the same |
fc6826d1 CW |
856 | * type is not a problem, it displays a problem in the logic. |
857 | * | |
c6a828d3 | 858 | * The mask bit in IMR is cleared by dev_priv->rps.work. |
fc6826d1 CW |
859 | */ |
860 | ||
c6a828d3 | 861 | spin_lock_irqsave(&dev_priv->rps.lock, flags); |
c6a828d3 DV |
862 | dev_priv->rps.pm_iir |= pm_iir; |
863 | I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir); | |
fc6826d1 | 864 | POSTING_READ(GEN6_PMIMR); |
c6a828d3 | 865 | spin_unlock_irqrestore(&dev_priv->rps.lock, flags); |
fc6826d1 | 866 | |
c6a828d3 | 867 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
fc6826d1 CW |
868 | } |
869 | ||
b543fb04 EE |
870 | #define HPD_STORM_DETECT_PERIOD 1000 |
871 | #define HPD_STORM_THRESHOLD 5 | |
872 | ||
cd569aed | 873 | static inline bool hotplug_irq_storm_detect(struct drm_device *dev, |
b543fb04 EE |
874 | u32 hotplug_trigger, |
875 | const u32 *hpd) | |
876 | { | |
877 | drm_i915_private_t *dev_priv = dev->dev_private; | |
878 | unsigned long irqflags; | |
879 | int i; | |
cd569aed | 880 | bool ret = false; |
b543fb04 EE |
881 | |
882 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
883 | ||
884 | for (i = 1; i < HPD_NUM_PINS; i++) { | |
821450c6 | 885 | |
b543fb04 EE |
886 | if (!(hpd[i] & hotplug_trigger) || |
887 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
888 | continue; | |
889 | ||
bc5ead8c | 890 | dev_priv->hpd_event_bits |= (1 << i); |
b543fb04 EE |
891 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
892 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
893 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
894 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
895 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
896 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { | |
897 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 898 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 899 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
cd569aed | 900 | ret = true; |
b543fb04 EE |
901 | } else { |
902 | dev_priv->hpd_stats[i].hpd_cnt++; | |
903 | } | |
904 | } | |
905 | ||
906 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
cd569aed EE |
907 | |
908 | return ret; | |
b543fb04 EE |
909 | } |
910 | ||
515ac2bb DV |
911 | static void gmbus_irq_handler(struct drm_device *dev) |
912 | { | |
28c70f16 DV |
913 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
914 | ||
28c70f16 | 915 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
916 | } |
917 | ||
ce99c256 DV |
918 | static void dp_aux_irq_handler(struct drm_device *dev) |
919 | { | |
9ee32fea DV |
920 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
921 | ||
9ee32fea | 922 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
923 | } |
924 | ||
baf02a1f BW |
925 | /* Unlike gen6_queue_rps_work() from which this function is originally derived, |
926 | * we must be able to deal with other PM interrupts. This is complicated because | |
927 | * of the way in which we use the masks to defer the RPS work (which for | |
928 | * posterity is necessary because of forcewake). | |
929 | */ | |
930 | static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv, | |
931 | u32 pm_iir) | |
932 | { | |
933 | unsigned long flags; | |
934 | ||
935 | spin_lock_irqsave(&dev_priv->rps.lock, flags); | |
4848405c | 936 | dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS; |
baf02a1f BW |
937 | if (dev_priv->rps.pm_iir) { |
938 | I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir); | |
939 | /* never want to mask useful interrupts. (also posting read) */ | |
4848405c | 940 | WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS); |
baf02a1f BW |
941 | /* TODO: if queue_work is slow, move it out of the spinlock */ |
942 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
943 | } | |
944 | spin_unlock_irqrestore(&dev_priv->rps.lock, flags); | |
945 | ||
12638c57 BW |
946 | if (pm_iir & ~GEN6_PM_RPS_EVENTS) { |
947 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
948 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
949 | ||
950 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { | |
951 | DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir); | |
952 | i915_handle_error(dev_priv->dev, false); | |
953 | } | |
954 | } | |
baf02a1f BW |
955 | } |
956 | ||
ff1f525e | 957 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe JB |
958 | { |
959 | struct drm_device *dev = (struct drm_device *) arg; | |
960 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
961 | u32 iir, gt_iir, pm_iir; | |
962 | irqreturn_t ret = IRQ_NONE; | |
963 | unsigned long irqflags; | |
964 | int pipe; | |
965 | u32 pipe_stats[I915_MAX_PIPES]; | |
7e231dbe JB |
966 | |
967 | atomic_inc(&dev_priv->irq_received); | |
968 | ||
7e231dbe JB |
969 | while (true) { |
970 | iir = I915_READ(VLV_IIR); | |
971 | gt_iir = I915_READ(GTIIR); | |
972 | pm_iir = I915_READ(GEN6_PMIIR); | |
973 | ||
974 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
975 | goto out; | |
976 | ||
977 | ret = IRQ_HANDLED; | |
978 | ||
e7b4c6b1 | 979 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe JB |
980 | |
981 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
982 | for_each_pipe(pipe) { | |
983 | int reg = PIPESTAT(pipe); | |
984 | pipe_stats[pipe] = I915_READ(reg); | |
985 | ||
986 | /* | |
987 | * Clear the PIPE*STAT regs before the IIR | |
988 | */ | |
989 | if (pipe_stats[pipe] & 0x8000ffff) { | |
990 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
991 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
992 | pipe_name(pipe)); | |
993 | I915_WRITE(reg, pipe_stats[pipe]); | |
994 | } | |
995 | } | |
996 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
997 | ||
31acc7f5 JB |
998 | for_each_pipe(pipe) { |
999 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) | |
1000 | drm_handle_vblank(dev, pipe); | |
1001 | ||
1002 | if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { | |
1003 | intel_prepare_page_flip(dev, pipe); | |
1004 | intel_finish_page_flip(dev, pipe); | |
1005 | } | |
1006 | } | |
1007 | ||
7e231dbe JB |
1008 | /* Consume port. Then clear IIR or we'll miss events */ |
1009 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { | |
1010 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 1011 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
7e231dbe JB |
1012 | |
1013 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
1014 | hotplug_status); | |
b543fb04 | 1015 | if (hotplug_trigger) { |
cd569aed EE |
1016 | if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915)) |
1017 | i915_hpd_irq_setup(dev); | |
7e231dbe JB |
1018 | queue_work(dev_priv->wq, |
1019 | &dev_priv->hotplug_work); | |
b543fb04 | 1020 | } |
7e231dbe JB |
1021 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
1022 | I915_READ(PORT_HOTPLUG_STAT); | |
1023 | } | |
1024 | ||
515ac2bb DV |
1025 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
1026 | gmbus_irq_handler(dev); | |
7e231dbe | 1027 | |
4848405c | 1028 | if (pm_iir & GEN6_PM_RPS_EVENTS) |
fc6826d1 | 1029 | gen6_queue_rps_work(dev_priv, pm_iir); |
7e231dbe JB |
1030 | |
1031 | I915_WRITE(GTIIR, gt_iir); | |
1032 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1033 | I915_WRITE(VLV_IIR, iir); | |
1034 | } | |
1035 | ||
1036 | out: | |
1037 | return ret; | |
1038 | } | |
1039 | ||
23e81d69 | 1040 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 JB |
1041 | { |
1042 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 1043 | int pipe; |
b543fb04 | 1044 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
776ad806 | 1045 | |
b543fb04 | 1046 | if (hotplug_trigger) { |
cd569aed EE |
1047 | if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx)) |
1048 | ibx_hpd_irq_setup(dev); | |
76e43830 | 1049 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
b543fb04 | 1050 | } |
cfc33bf7 VS |
1051 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1052 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1053 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1054 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1055 | port_name(port)); |
1056 | } | |
776ad806 | 1057 | |
ce99c256 DV |
1058 | if (pch_iir & SDE_AUX_MASK) |
1059 | dp_aux_irq_handler(dev); | |
1060 | ||
776ad806 | 1061 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1062 | gmbus_irq_handler(dev); |
776ad806 JB |
1063 | |
1064 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1065 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1066 | ||
1067 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1068 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1069 | ||
1070 | if (pch_iir & SDE_POISON) | |
1071 | DRM_ERROR("PCH poison interrupt\n"); | |
1072 | ||
9db4a9c7 JB |
1073 | if (pch_iir & SDE_FDI_MASK) |
1074 | for_each_pipe(pipe) | |
1075 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1076 | pipe_name(pipe), | |
1077 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1078 | |
1079 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1080 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1081 | ||
1082 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1083 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1084 | ||
776ad806 | 1085 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
8664281b PZ |
1086 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
1087 | false)) | |
1088 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); | |
1089 | ||
1090 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1091 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1092 | false)) | |
1093 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); | |
1094 | } | |
1095 | ||
1096 | static void ivb_err_int_handler(struct drm_device *dev) | |
1097 | { | |
1098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1099 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
1100 | ||
de032bf4 PZ |
1101 | if (err_int & ERR_INT_POISON) |
1102 | DRM_ERROR("Poison interrupt\n"); | |
1103 | ||
8664281b PZ |
1104 | if (err_int & ERR_INT_FIFO_UNDERRUN_A) |
1105 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) | |
1106 | DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); | |
1107 | ||
1108 | if (err_int & ERR_INT_FIFO_UNDERRUN_B) | |
1109 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) | |
1110 | DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n"); | |
1111 | ||
1112 | if (err_int & ERR_INT_FIFO_UNDERRUN_C) | |
1113 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false)) | |
1114 | DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n"); | |
1115 | ||
1116 | I915_WRITE(GEN7_ERR_INT, err_int); | |
1117 | } | |
1118 | ||
1119 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1120 | { | |
1121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1122 | u32 serr_int = I915_READ(SERR_INT); | |
1123 | ||
de032bf4 PZ |
1124 | if (serr_int & SERR_INT_POISON) |
1125 | DRM_ERROR("PCH poison interrupt\n"); | |
1126 | ||
8664281b PZ |
1127 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1128 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, | |
1129 | false)) | |
1130 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); | |
1131 | ||
1132 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1133 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1134 | false)) | |
1135 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); | |
1136 | ||
1137 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1138 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, | |
1139 | false)) | |
1140 | DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n"); | |
1141 | ||
1142 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1143 | } |
1144 | ||
23e81d69 AJ |
1145 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1146 | { | |
1147 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1148 | int pipe; | |
b543fb04 | 1149 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
23e81d69 | 1150 | |
b543fb04 | 1151 | if (hotplug_trigger) { |
cd569aed EE |
1152 | if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt)) |
1153 | ibx_hpd_irq_setup(dev); | |
76e43830 | 1154 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
b543fb04 | 1155 | } |
cfc33bf7 VS |
1156 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1157 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1158 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1159 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1160 | port_name(port)); | |
1161 | } | |
23e81d69 AJ |
1162 | |
1163 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1164 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1165 | |
1166 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1167 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1168 | |
1169 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1170 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1171 | ||
1172 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1173 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1174 | ||
1175 | if (pch_iir & SDE_FDI_MASK_CPT) | |
1176 | for_each_pipe(pipe) | |
1177 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1178 | pipe_name(pipe), | |
1179 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1180 | |
1181 | if (pch_iir & SDE_ERROR_CPT) | |
1182 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1183 | } |
1184 | ||
ff1f525e | 1185 | static irqreturn_t ivybridge_irq_handler(int irq, void *arg) |
b1f14ad0 JB |
1186 | { |
1187 | struct drm_device *dev = (struct drm_device *) arg; | |
1188 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
ab5c608b | 1189 | u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0; |
0e43406b CW |
1190 | irqreturn_t ret = IRQ_NONE; |
1191 | int i; | |
b1f14ad0 JB |
1192 | |
1193 | atomic_inc(&dev_priv->irq_received); | |
1194 | ||
8664281b PZ |
1195 | /* We get interrupts on unclaimed registers, so check for this before we |
1196 | * do any I915_{READ,WRITE}. */ | |
1197 | if (IS_HASWELL(dev) && | |
1198 | (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { | |
1199 | DRM_ERROR("Unclaimed register before interrupt\n"); | |
1200 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
1201 | } | |
1202 | ||
b1f14ad0 JB |
1203 | /* disable master interrupt before clearing iir */ |
1204 | de_ier = I915_READ(DEIER); | |
1205 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
b1f14ad0 | 1206 | |
44498aea PZ |
1207 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
1208 | * interrupts will will be stored on its back queue, and then we'll be | |
1209 | * able to process them after we restore SDEIER (as soon as we restore | |
1210 | * it, we'll get an interrupt if SDEIIR still has something to process | |
1211 | * due to its back queue). */ | |
ab5c608b BW |
1212 | if (!HAS_PCH_NOP(dev)) { |
1213 | sde_ier = I915_READ(SDEIER); | |
1214 | I915_WRITE(SDEIER, 0); | |
1215 | POSTING_READ(SDEIER); | |
1216 | } | |
44498aea | 1217 | |
8664281b PZ |
1218 | /* On Haswell, also mask ERR_INT because we don't want to risk |
1219 | * generating "unclaimed register" interrupts from inside the interrupt | |
1220 | * handler. */ | |
1221 | if (IS_HASWELL(dev)) | |
1222 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); | |
1223 | ||
b1f14ad0 | 1224 | gt_iir = I915_READ(GTIIR); |
0e43406b CW |
1225 | if (gt_iir) { |
1226 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
1227 | I915_WRITE(GTIIR, gt_iir); | |
1228 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1229 | } |
1230 | ||
0e43406b CW |
1231 | de_iir = I915_READ(DEIIR); |
1232 | if (de_iir) { | |
8664281b PZ |
1233 | if (de_iir & DE_ERR_INT_IVB) |
1234 | ivb_err_int_handler(dev); | |
1235 | ||
ce99c256 DV |
1236 | if (de_iir & DE_AUX_CHANNEL_A_IVB) |
1237 | dp_aux_irq_handler(dev); | |
1238 | ||
0e43406b | 1239 | if (de_iir & DE_GSE_IVB) |
81a07809 | 1240 | intel_opregion_asle_intr(dev); |
0e43406b CW |
1241 | |
1242 | for (i = 0; i < 3; i++) { | |
74d44445 DV |
1243 | if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i))) |
1244 | drm_handle_vblank(dev, i); | |
0e43406b CW |
1245 | if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) { |
1246 | intel_prepare_page_flip(dev, i); | |
1247 | intel_finish_page_flip_plane(dev, i); | |
1248 | } | |
0e43406b | 1249 | } |
b615b57a | 1250 | |
0e43406b | 1251 | /* check event from PCH */ |
ab5c608b | 1252 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { |
0e43406b | 1253 | u32 pch_iir = I915_READ(SDEIIR); |
b1f14ad0 | 1254 | |
23e81d69 | 1255 | cpt_irq_handler(dev, pch_iir); |
b1f14ad0 | 1256 | |
0e43406b CW |
1257 | /* clear PCH hotplug event before clear CPU irq */ |
1258 | I915_WRITE(SDEIIR, pch_iir); | |
1259 | } | |
b615b57a | 1260 | |
0e43406b CW |
1261 | I915_WRITE(DEIIR, de_iir); |
1262 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1263 | } |
1264 | ||
0e43406b CW |
1265 | pm_iir = I915_READ(GEN6_PMIIR); |
1266 | if (pm_iir) { | |
baf02a1f BW |
1267 | if (IS_HASWELL(dev)) |
1268 | hsw_pm_irq_handler(dev_priv, pm_iir); | |
4848405c | 1269 | else if (pm_iir & GEN6_PM_RPS_EVENTS) |
0e43406b CW |
1270 | gen6_queue_rps_work(dev_priv, pm_iir); |
1271 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1272 | ret = IRQ_HANDLED; | |
1273 | } | |
b1f14ad0 | 1274 | |
8664281b PZ |
1275 | if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev)) |
1276 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); | |
1277 | ||
b1f14ad0 JB |
1278 | I915_WRITE(DEIER, de_ier); |
1279 | POSTING_READ(DEIER); | |
ab5c608b BW |
1280 | if (!HAS_PCH_NOP(dev)) { |
1281 | I915_WRITE(SDEIER, sde_ier); | |
1282 | POSTING_READ(SDEIER); | |
1283 | } | |
b1f14ad0 JB |
1284 | |
1285 | return ret; | |
1286 | } | |
1287 | ||
e7b4c6b1 DV |
1288 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1289 | struct drm_i915_private *dev_priv, | |
1290 | u32 gt_iir) | |
1291 | { | |
cc609d5d BW |
1292 | if (gt_iir & |
1293 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1294 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1295 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
e7b4c6b1 DV |
1296 | notify_ring(dev, &dev_priv->ring[VCS]); |
1297 | } | |
1298 | ||
ff1f525e | 1299 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
036a4a7d | 1300 | { |
4697995b | 1301 | struct drm_device *dev = (struct drm_device *) arg; |
036a4a7d ZW |
1302 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1303 | int ret = IRQ_NONE; | |
44498aea | 1304 | u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier; |
881f47b6 | 1305 | |
4697995b JB |
1306 | atomic_inc(&dev_priv->irq_received); |
1307 | ||
2d109a84 ZN |
1308 | /* disable master interrupt before clearing iir */ |
1309 | de_ier = I915_READ(DEIER); | |
1310 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
3143a2bf | 1311 | POSTING_READ(DEIER); |
2d109a84 | 1312 | |
44498aea PZ |
1313 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
1314 | * interrupts will will be stored on its back queue, and then we'll be | |
1315 | * able to process them after we restore SDEIER (as soon as we restore | |
1316 | * it, we'll get an interrupt if SDEIIR still has something to process | |
1317 | * due to its back queue). */ | |
1318 | sde_ier = I915_READ(SDEIER); | |
1319 | I915_WRITE(SDEIER, 0); | |
1320 | POSTING_READ(SDEIER); | |
1321 | ||
036a4a7d ZW |
1322 | de_iir = I915_READ(DEIIR); |
1323 | gt_iir = I915_READ(GTIIR); | |
3b8d8d91 | 1324 | pm_iir = I915_READ(GEN6_PMIIR); |
036a4a7d | 1325 | |
acd15b6c | 1326 | if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0)) |
c7c85101 | 1327 | goto done; |
036a4a7d | 1328 | |
c7c85101 | 1329 | ret = IRQ_HANDLED; |
036a4a7d | 1330 | |
e7b4c6b1 DV |
1331 | if (IS_GEN5(dev)) |
1332 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
1333 | else | |
1334 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
01c66889 | 1335 | |
ce99c256 DV |
1336 | if (de_iir & DE_AUX_CHANNEL_A) |
1337 | dp_aux_irq_handler(dev); | |
1338 | ||
c7c85101 | 1339 | if (de_iir & DE_GSE) |
81a07809 | 1340 | intel_opregion_asle_intr(dev); |
c650156a | 1341 | |
74d44445 DV |
1342 | if (de_iir & DE_PIPEA_VBLANK) |
1343 | drm_handle_vblank(dev, 0); | |
1344 | ||
1345 | if (de_iir & DE_PIPEB_VBLANK) | |
1346 | drm_handle_vblank(dev, 1); | |
1347 | ||
de032bf4 PZ |
1348 | if (de_iir & DE_POISON) |
1349 | DRM_ERROR("Poison interrupt\n"); | |
1350 | ||
8664281b PZ |
1351 | if (de_iir & DE_PIPEA_FIFO_UNDERRUN) |
1352 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) | |
1353 | DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); | |
1354 | ||
1355 | if (de_iir & DE_PIPEB_FIFO_UNDERRUN) | |
1356 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) | |
1357 | DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n"); | |
1358 | ||
f072d2e7 | 1359 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 1360 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 1361 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 1362 | } |
013d5aa2 | 1363 | |
f072d2e7 | 1364 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 1365 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 1366 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 1367 | } |
013d5aa2 | 1368 | |
c7c85101 | 1369 | /* check event from PCH */ |
776ad806 | 1370 | if (de_iir & DE_PCH_EVENT) { |
acd15b6c DV |
1371 | u32 pch_iir = I915_READ(SDEIIR); |
1372 | ||
23e81d69 AJ |
1373 | if (HAS_PCH_CPT(dev)) |
1374 | cpt_irq_handler(dev, pch_iir); | |
1375 | else | |
1376 | ibx_irq_handler(dev, pch_iir); | |
acd15b6c DV |
1377 | |
1378 | /* should clear PCH hotplug event before clear CPU irq */ | |
1379 | I915_WRITE(SDEIIR, pch_iir); | |
776ad806 | 1380 | } |
036a4a7d | 1381 | |
73edd18f DV |
1382 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) |
1383 | ironlake_handle_rps_change(dev); | |
f97108d1 | 1384 | |
4848405c | 1385 | if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS) |
fc6826d1 | 1386 | gen6_queue_rps_work(dev_priv, pm_iir); |
3b8d8d91 | 1387 | |
c7c85101 ZN |
1388 | I915_WRITE(GTIIR, gt_iir); |
1389 | I915_WRITE(DEIIR, de_iir); | |
4912d041 | 1390 | I915_WRITE(GEN6_PMIIR, pm_iir); |
c7c85101 ZN |
1391 | |
1392 | done: | |
2d109a84 | 1393 | I915_WRITE(DEIER, de_ier); |
3143a2bf | 1394 | POSTING_READ(DEIER); |
44498aea PZ |
1395 | I915_WRITE(SDEIER, sde_ier); |
1396 | POSTING_READ(SDEIER); | |
2d109a84 | 1397 | |
036a4a7d ZW |
1398 | return ret; |
1399 | } | |
1400 | ||
8a905236 JB |
1401 | /** |
1402 | * i915_error_work_func - do process context error handling work | |
1403 | * @work: work struct | |
1404 | * | |
1405 | * Fire an error uevent so userspace can see that a hang or error | |
1406 | * was detected. | |
1407 | */ | |
1408 | static void i915_error_work_func(struct work_struct *work) | |
1409 | { | |
1f83fee0 DV |
1410 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
1411 | work); | |
1412 | drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, | |
1413 | gpu_error); | |
8a905236 | 1414 | struct drm_device *dev = dev_priv->dev; |
f69061be | 1415 | struct intel_ring_buffer *ring; |
f316a42c BG |
1416 | char *error_event[] = { "ERROR=1", NULL }; |
1417 | char *reset_event[] = { "RESET=1", NULL }; | |
1418 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
f69061be | 1419 | int i, ret; |
8a905236 | 1420 | |
f316a42c BG |
1421 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
1422 | ||
7db0ba24 DV |
1423 | /* |
1424 | * Note that there's only one work item which does gpu resets, so we | |
1425 | * need not worry about concurrent gpu resets potentially incrementing | |
1426 | * error->reset_counter twice. We only need to take care of another | |
1427 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
1428 | * quick check for that is good enough: schedule_work ensures the | |
1429 | * correct ordering between hang detection and this work item, and since | |
1430 | * the reset in-progress bit is only ever set by code outside of this | |
1431 | * work we don't need to worry about any other races. | |
1432 | */ | |
1433 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 1434 | DRM_DEBUG_DRIVER("resetting chip\n"); |
7db0ba24 DV |
1435 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, |
1436 | reset_event); | |
1f83fee0 | 1437 | |
f69061be DV |
1438 | ret = i915_reset(dev); |
1439 | ||
1440 | if (ret == 0) { | |
1441 | /* | |
1442 | * After all the gem state is reset, increment the reset | |
1443 | * counter and wake up everyone waiting for the reset to | |
1444 | * complete. | |
1445 | * | |
1446 | * Since unlock operations are a one-sided barrier only, | |
1447 | * we need to insert a barrier here to order any seqno | |
1448 | * updates before | |
1449 | * the counter increment. | |
1450 | */ | |
1451 | smp_mb__before_atomic_inc(); | |
1452 | atomic_inc(&dev_priv->gpu_error.reset_counter); | |
1453 | ||
1454 | kobject_uevent_env(&dev->primary->kdev.kobj, | |
1455 | KOBJ_CHANGE, reset_done_event); | |
1f83fee0 DV |
1456 | } else { |
1457 | atomic_set(&error->reset_counter, I915_WEDGED); | |
f316a42c | 1458 | } |
1f83fee0 | 1459 | |
f69061be DV |
1460 | for_each_ring(ring, dev_priv, i) |
1461 | wake_up_all(&ring->irq_queue); | |
1462 | ||
96a02917 VS |
1463 | intel_display_handle_reset(dev); |
1464 | ||
1f83fee0 | 1465 | wake_up_all(&dev_priv->gpu_error.reset_queue); |
f316a42c | 1466 | } |
8a905236 JB |
1467 | } |
1468 | ||
85f9e50d DV |
1469 | /* NB: please notice the memset */ |
1470 | static void i915_get_extra_instdone(struct drm_device *dev, | |
1471 | uint32_t *instdone) | |
1472 | { | |
1473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1474 | memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); | |
1475 | ||
1476 | switch(INTEL_INFO(dev)->gen) { | |
1477 | case 2: | |
1478 | case 3: | |
1479 | instdone[0] = I915_READ(INSTDONE); | |
1480 | break; | |
1481 | case 4: | |
1482 | case 5: | |
1483 | case 6: | |
1484 | instdone[0] = I915_READ(INSTDONE_I965); | |
1485 | instdone[1] = I915_READ(INSTDONE1); | |
1486 | break; | |
1487 | default: | |
1488 | WARN_ONCE(1, "Unsupported platform\n"); | |
1489 | case 7: | |
1490 | instdone[0] = I915_READ(GEN7_INSTDONE_1); | |
1491 | instdone[1] = I915_READ(GEN7_SC_INSTDONE); | |
1492 | instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); | |
1493 | instdone[3] = I915_READ(GEN7_ROW_INSTDONE); | |
1494 | break; | |
1495 | } | |
1496 | } | |
1497 | ||
3bd3c932 | 1498 | #ifdef CONFIG_DEBUG_FS |
9df30794 | 1499 | static struct drm_i915_error_object * |
d0d045e8 BW |
1500 | i915_error_object_create_sized(struct drm_i915_private *dev_priv, |
1501 | struct drm_i915_gem_object *src, | |
1502 | const int num_pages) | |
9df30794 CW |
1503 | { |
1504 | struct drm_i915_error_object *dst; | |
d0d045e8 | 1505 | int i; |
e56660dd | 1506 | u32 reloc_offset; |
9df30794 | 1507 | |
05394f39 | 1508 | if (src == NULL || src->pages == NULL) |
9df30794 CW |
1509 | return NULL; |
1510 | ||
d0d045e8 | 1511 | dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); |
9df30794 CW |
1512 | if (dst == NULL) |
1513 | return NULL; | |
1514 | ||
05394f39 | 1515 | reloc_offset = src->gtt_offset; |
d0d045e8 | 1516 | for (i = 0; i < num_pages; i++) { |
788885ae | 1517 | unsigned long flags; |
e56660dd | 1518 | void *d; |
788885ae | 1519 | |
e56660dd | 1520 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
1521 | if (d == NULL) |
1522 | goto unwind; | |
e56660dd | 1523 | |
788885ae | 1524 | local_irq_save(flags); |
5d4545ae | 1525 | if (reloc_offset < dev_priv->gtt.mappable_end && |
74898d7e | 1526 | src->has_global_gtt_mapping) { |
172975aa CW |
1527 | void __iomem *s; |
1528 | ||
1529 | /* Simply ignore tiling or any overlapping fence. | |
1530 | * It's part of the error state, and this hopefully | |
1531 | * captures what the GPU read. | |
1532 | */ | |
1533 | ||
5d4545ae | 1534 | s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
172975aa CW |
1535 | reloc_offset); |
1536 | memcpy_fromio(d, s, PAGE_SIZE); | |
1537 | io_mapping_unmap_atomic(s); | |
960e3564 CW |
1538 | } else if (src->stolen) { |
1539 | unsigned long offset; | |
1540 | ||
1541 | offset = dev_priv->mm.stolen_base; | |
1542 | offset += src->stolen->start; | |
1543 | offset += i << PAGE_SHIFT; | |
1544 | ||
1a240d4d | 1545 | memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE); |
172975aa | 1546 | } else { |
9da3da66 | 1547 | struct page *page; |
172975aa CW |
1548 | void *s; |
1549 | ||
9da3da66 | 1550 | page = i915_gem_object_get_page(src, i); |
172975aa | 1551 | |
9da3da66 CW |
1552 | drm_clflush_pages(&page, 1); |
1553 | ||
1554 | s = kmap_atomic(page); | |
172975aa CW |
1555 | memcpy(d, s, PAGE_SIZE); |
1556 | kunmap_atomic(s); | |
1557 | ||
9da3da66 | 1558 | drm_clflush_pages(&page, 1); |
172975aa | 1559 | } |
788885ae | 1560 | local_irq_restore(flags); |
e56660dd | 1561 | |
9da3da66 | 1562 | dst->pages[i] = d; |
e56660dd CW |
1563 | |
1564 | reloc_offset += PAGE_SIZE; | |
9df30794 | 1565 | } |
d0d045e8 | 1566 | dst->page_count = num_pages; |
05394f39 | 1567 | dst->gtt_offset = src->gtt_offset; |
9df30794 CW |
1568 | |
1569 | return dst; | |
1570 | ||
1571 | unwind: | |
9da3da66 CW |
1572 | while (i--) |
1573 | kfree(dst->pages[i]); | |
9df30794 CW |
1574 | kfree(dst); |
1575 | return NULL; | |
1576 | } | |
d0d045e8 BW |
1577 | #define i915_error_object_create(dev_priv, src) \ |
1578 | i915_error_object_create_sized((dev_priv), (src), \ | |
1579 | (src)->base.size>>PAGE_SHIFT) | |
9df30794 CW |
1580 | |
1581 | static void | |
1582 | i915_error_object_free(struct drm_i915_error_object *obj) | |
1583 | { | |
1584 | int page; | |
1585 | ||
1586 | if (obj == NULL) | |
1587 | return; | |
1588 | ||
1589 | for (page = 0; page < obj->page_count; page++) | |
1590 | kfree(obj->pages[page]); | |
1591 | ||
1592 | kfree(obj); | |
1593 | } | |
1594 | ||
742cbee8 DV |
1595 | void |
1596 | i915_error_state_free(struct kref *error_ref) | |
9df30794 | 1597 | { |
742cbee8 DV |
1598 | struct drm_i915_error_state *error = container_of(error_ref, |
1599 | typeof(*error), ref); | |
e2f973d5 CW |
1600 | int i; |
1601 | ||
52d39a21 CW |
1602 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
1603 | i915_error_object_free(error->ring[i].batchbuffer); | |
1604 | i915_error_object_free(error->ring[i].ringbuffer); | |
7ed73da0 | 1605 | i915_error_object_free(error->ring[i].ctx); |
52d39a21 CW |
1606 | kfree(error->ring[i].requests); |
1607 | } | |
e2f973d5 | 1608 | |
9df30794 | 1609 | kfree(error->active_bo); |
6ef3d427 | 1610 | kfree(error->overlay); |
7ed73da0 | 1611 | kfree(error->display); |
9df30794 CW |
1612 | kfree(error); |
1613 | } | |
1b50247a CW |
1614 | static void capture_bo(struct drm_i915_error_buffer *err, |
1615 | struct drm_i915_gem_object *obj) | |
1616 | { | |
1617 | err->size = obj->base.size; | |
1618 | err->name = obj->base.name; | |
0201f1ec CW |
1619 | err->rseqno = obj->last_read_seqno; |
1620 | err->wseqno = obj->last_write_seqno; | |
1b50247a CW |
1621 | err->gtt_offset = obj->gtt_offset; |
1622 | err->read_domains = obj->base.read_domains; | |
1623 | err->write_domain = obj->base.write_domain; | |
1624 | err->fence_reg = obj->fence_reg; | |
1625 | err->pinned = 0; | |
1626 | if (obj->pin_count > 0) | |
1627 | err->pinned = 1; | |
1628 | if (obj->user_pin_count > 0) | |
1629 | err->pinned = -1; | |
1630 | err->tiling = obj->tiling_mode; | |
1631 | err->dirty = obj->dirty; | |
1632 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
1633 | err->ring = obj->ring ? obj->ring->id : -1; | |
1634 | err->cache_level = obj->cache_level; | |
1635 | } | |
9df30794 | 1636 | |
1b50247a CW |
1637 | static u32 capture_active_bo(struct drm_i915_error_buffer *err, |
1638 | int count, struct list_head *head) | |
c724e8a9 CW |
1639 | { |
1640 | struct drm_i915_gem_object *obj; | |
1641 | int i = 0; | |
1642 | ||
1643 | list_for_each_entry(obj, head, mm_list) { | |
1b50247a | 1644 | capture_bo(err++, obj); |
c724e8a9 CW |
1645 | if (++i == count) |
1646 | break; | |
1b50247a CW |
1647 | } |
1648 | ||
1649 | return i; | |
1650 | } | |
1651 | ||
1652 | static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, | |
1653 | int count, struct list_head *head) | |
1654 | { | |
1655 | struct drm_i915_gem_object *obj; | |
1656 | int i = 0; | |
1657 | ||
35c20a60 | 1658 | list_for_each_entry(obj, head, global_list) { |
1b50247a CW |
1659 | if (obj->pin_count == 0) |
1660 | continue; | |
c724e8a9 | 1661 | |
1b50247a CW |
1662 | capture_bo(err++, obj); |
1663 | if (++i == count) | |
1664 | break; | |
c724e8a9 CW |
1665 | } |
1666 | ||
1667 | return i; | |
1668 | } | |
1669 | ||
748ebc60 CW |
1670 | static void i915_gem_record_fences(struct drm_device *dev, |
1671 | struct drm_i915_error_state *error) | |
1672 | { | |
1673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1674 | int i; | |
1675 | ||
1676 | /* Fences */ | |
1677 | switch (INTEL_INFO(dev)->gen) { | |
775d17b6 | 1678 | case 7: |
748ebc60 | 1679 | case 6: |
42b5aeab | 1680 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
748ebc60 CW |
1681 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); |
1682 | break; | |
1683 | case 5: | |
1684 | case 4: | |
1685 | for (i = 0; i < 16; i++) | |
1686 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
1687 | break; | |
1688 | case 3: | |
1689 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
1690 | for (i = 0; i < 8; i++) | |
1691 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
1692 | case 2: | |
1693 | for (i = 0; i < 8; i++) | |
1694 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
1695 | break; | |
1696 | ||
7dbf9d6e BW |
1697 | default: |
1698 | BUG(); | |
748ebc60 CW |
1699 | } |
1700 | } | |
1701 | ||
bcfb2e28 CW |
1702 | static struct drm_i915_error_object * |
1703 | i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, | |
1704 | struct intel_ring_buffer *ring) | |
1705 | { | |
1706 | struct drm_i915_gem_object *obj; | |
1707 | u32 seqno; | |
1708 | ||
1709 | if (!ring->get_seqno) | |
1710 | return NULL; | |
1711 | ||
b45305fc DV |
1712 | if (HAS_BROKEN_CS_TLB(dev_priv->dev)) { |
1713 | u32 acthd = I915_READ(ACTHD); | |
1714 | ||
1715 | if (WARN_ON(ring->id != RCS)) | |
1716 | return NULL; | |
1717 | ||
1718 | obj = ring->private; | |
1719 | if (acthd >= obj->gtt_offset && | |
1720 | acthd < obj->gtt_offset + obj->base.size) | |
1721 | return i915_error_object_create(dev_priv, obj); | |
1722 | } | |
1723 | ||
b2eadbc8 | 1724 | seqno = ring->get_seqno(ring, false); |
bcfb2e28 CW |
1725 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { |
1726 | if (obj->ring != ring) | |
1727 | continue; | |
1728 | ||
0201f1ec | 1729 | if (i915_seqno_passed(seqno, obj->last_read_seqno)) |
bcfb2e28 CW |
1730 | continue; |
1731 | ||
1732 | if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) | |
1733 | continue; | |
1734 | ||
1735 | /* We need to copy these to an anonymous buffer as the simplest | |
1736 | * method to avoid being overwritten by userspace. | |
1737 | */ | |
1738 | return i915_error_object_create(dev_priv, obj); | |
1739 | } | |
1740 | ||
1741 | return NULL; | |
1742 | } | |
1743 | ||
d27b1e0e DV |
1744 | static void i915_record_ring_state(struct drm_device *dev, |
1745 | struct drm_i915_error_state *error, | |
1746 | struct intel_ring_buffer *ring) | |
1747 | { | |
1748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1749 | ||
33f3f518 | 1750 | if (INTEL_INFO(dev)->gen >= 6) { |
12f55818 | 1751 | error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50); |
33f3f518 | 1752 | error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); |
7e3b8737 DV |
1753 | error->semaphore_mboxes[ring->id][0] |
1754 | = I915_READ(RING_SYNC_0(ring->mmio_base)); | |
1755 | error->semaphore_mboxes[ring->id][1] | |
1756 | = I915_READ(RING_SYNC_1(ring->mmio_base)); | |
df2b23d9 CW |
1757 | error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0]; |
1758 | error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1]; | |
33f3f518 | 1759 | } |
c1cd90ed | 1760 | |
d27b1e0e | 1761 | if (INTEL_INFO(dev)->gen >= 4) { |
9d2f41fa | 1762 | error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); |
d27b1e0e DV |
1763 | error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); |
1764 | error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); | |
1765 | error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); | |
c1cd90ed | 1766 | error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); |
050ee91f | 1767 | if (ring->id == RCS) |
d27b1e0e | 1768 | error->bbaddr = I915_READ64(BB_ADDR); |
d27b1e0e | 1769 | } else { |
9d2f41fa | 1770 | error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX); |
d27b1e0e DV |
1771 | error->ipeir[ring->id] = I915_READ(IPEIR); |
1772 | error->ipehr[ring->id] = I915_READ(IPEHR); | |
1773 | error->instdone[ring->id] = I915_READ(INSTDONE); | |
d27b1e0e DV |
1774 | } |
1775 | ||
9574b3fe | 1776 | error->waiting[ring->id] = waitqueue_active(&ring->irq_queue); |
c1cd90ed | 1777 | error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); |
b2eadbc8 | 1778 | error->seqno[ring->id] = ring->get_seqno(ring, false); |
d27b1e0e | 1779 | error->acthd[ring->id] = intel_ring_get_active_head(ring); |
c1cd90ed DV |
1780 | error->head[ring->id] = I915_READ_HEAD(ring); |
1781 | error->tail[ring->id] = I915_READ_TAIL(ring); | |
0f3b6849 | 1782 | error->ctl[ring->id] = I915_READ_CTL(ring); |
7e3b8737 DV |
1783 | |
1784 | error->cpu_ring_head[ring->id] = ring->head; | |
1785 | error->cpu_ring_tail[ring->id] = ring->tail; | |
d27b1e0e DV |
1786 | } |
1787 | ||
8c123e54 BW |
1788 | |
1789 | static void i915_gem_record_active_context(struct intel_ring_buffer *ring, | |
1790 | struct drm_i915_error_state *error, | |
1791 | struct drm_i915_error_ring *ering) | |
1792 | { | |
1793 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1794 | struct drm_i915_gem_object *obj; | |
1795 | ||
1796 | /* Currently render ring is the only HW context user */ | |
1797 | if (ring->id != RCS || !error->ccid) | |
1798 | return; | |
1799 | ||
35c20a60 | 1800 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
8c123e54 BW |
1801 | if ((error->ccid & PAGE_MASK) == obj->gtt_offset) { |
1802 | ering->ctx = i915_error_object_create_sized(dev_priv, | |
1803 | obj, 1); | |
1804 | } | |
1805 | } | |
1806 | } | |
1807 | ||
52d39a21 CW |
1808 | static void i915_gem_record_rings(struct drm_device *dev, |
1809 | struct drm_i915_error_state *error) | |
1810 | { | |
1811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b4519513 | 1812 | struct intel_ring_buffer *ring; |
52d39a21 CW |
1813 | struct drm_i915_gem_request *request; |
1814 | int i, count; | |
1815 | ||
b4519513 | 1816 | for_each_ring(ring, dev_priv, i) { |
52d39a21 CW |
1817 | i915_record_ring_state(dev, error, ring); |
1818 | ||
1819 | error->ring[i].batchbuffer = | |
1820 | i915_error_first_batchbuffer(dev_priv, ring); | |
1821 | ||
1822 | error->ring[i].ringbuffer = | |
1823 | i915_error_object_create(dev_priv, ring->obj); | |
1824 | ||
8c123e54 BW |
1825 | |
1826 | i915_gem_record_active_context(ring, error, &error->ring[i]); | |
1827 | ||
52d39a21 CW |
1828 | count = 0; |
1829 | list_for_each_entry(request, &ring->request_list, list) | |
1830 | count++; | |
1831 | ||
1832 | error->ring[i].num_requests = count; | |
1833 | error->ring[i].requests = | |
1834 | kmalloc(count*sizeof(struct drm_i915_error_request), | |
1835 | GFP_ATOMIC); | |
1836 | if (error->ring[i].requests == NULL) { | |
1837 | error->ring[i].num_requests = 0; | |
1838 | continue; | |
1839 | } | |
1840 | ||
1841 | count = 0; | |
1842 | list_for_each_entry(request, &ring->request_list, list) { | |
1843 | struct drm_i915_error_request *erq; | |
1844 | ||
1845 | erq = &error->ring[i].requests[count++]; | |
1846 | erq->seqno = request->seqno; | |
1847 | erq->jiffies = request->emitted_jiffies; | |
ee4f42b1 | 1848 | erq->tail = request->tail; |
52d39a21 CW |
1849 | } |
1850 | } | |
1851 | } | |
1852 | ||
8a905236 JB |
1853 | /** |
1854 | * i915_capture_error_state - capture an error record for later analysis | |
1855 | * @dev: drm device | |
1856 | * | |
1857 | * Should be called when an error is detected (either a hang or an error | |
1858 | * interrupt) to capture error state from the time of the error. Fills | |
1859 | * out a structure which becomes available in debugfs for user level tools | |
1860 | * to pick up. | |
1861 | */ | |
63eeaf38 JB |
1862 | static void i915_capture_error_state(struct drm_device *dev) |
1863 | { | |
1864 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1865 | struct drm_i915_gem_object *obj; |
63eeaf38 JB |
1866 | struct drm_i915_error_state *error; |
1867 | unsigned long flags; | |
9db4a9c7 | 1868 | int i, pipe; |
63eeaf38 | 1869 | |
99584db3 DV |
1870 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
1871 | error = dev_priv->gpu_error.first_error; | |
1872 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); | |
9df30794 CW |
1873 | if (error) |
1874 | return; | |
63eeaf38 | 1875 | |
9db4a9c7 | 1876 | /* Account for pipe specific data like PIPE*STAT */ |
33f3f518 | 1877 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
63eeaf38 | 1878 | if (!error) { |
9df30794 CW |
1879 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
1880 | return; | |
63eeaf38 JB |
1881 | } |
1882 | ||
5d83d294 | 1883 | DRM_INFO("capturing error event; look for more information in " |
2f86f191 | 1884 | "/sys/kernel/debug/dri/%d/i915_error_state\n", |
b6f7833b | 1885 | dev->primary->index); |
2fa772f3 | 1886 | |
742cbee8 | 1887 | kref_init(&error->ref); |
63eeaf38 JB |
1888 | error->eir = I915_READ(EIR); |
1889 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
211816ec BW |
1890 | if (HAS_HW_CONTEXTS(dev)) |
1891 | error->ccid = I915_READ(CCID); | |
be998e2e BW |
1892 | |
1893 | if (HAS_PCH_SPLIT(dev)) | |
1894 | error->ier = I915_READ(DEIER) | I915_READ(GTIER); | |
1895 | else if (IS_VALLEYVIEW(dev)) | |
1896 | error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); | |
1897 | else if (IS_GEN2(dev)) | |
1898 | error->ier = I915_READ16(IER); | |
1899 | else | |
1900 | error->ier = I915_READ(IER); | |
1901 | ||
0f3b6849 CW |
1902 | if (INTEL_INFO(dev)->gen >= 6) |
1903 | error->derrmr = I915_READ(DERRMR); | |
1904 | ||
1905 | if (IS_VALLEYVIEW(dev)) | |
1906 | error->forcewake = I915_READ(FORCEWAKE_VLV); | |
1907 | else if (INTEL_INFO(dev)->gen >= 7) | |
1908 | error->forcewake = I915_READ(FORCEWAKE_MT); | |
1909 | else if (INTEL_INFO(dev)->gen == 6) | |
1910 | error->forcewake = I915_READ(FORCEWAKE); | |
1911 | ||
4f3308b9 PZ |
1912 | if (!HAS_PCH_SPLIT(dev)) |
1913 | for_each_pipe(pipe) | |
1914 | error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); | |
d27b1e0e | 1915 | |
33f3f518 | 1916 | if (INTEL_INFO(dev)->gen >= 6) { |
f406839f | 1917 | error->error = I915_READ(ERROR_GEN6); |
33f3f518 DV |
1918 | error->done_reg = I915_READ(DONE_REG); |
1919 | } | |
d27b1e0e | 1920 | |
71e172e8 BW |
1921 | if (INTEL_INFO(dev)->gen == 7) |
1922 | error->err_int = I915_READ(GEN7_ERR_INT); | |
1923 | ||
050ee91f BW |
1924 | i915_get_extra_instdone(dev, error->extra_instdone); |
1925 | ||
748ebc60 | 1926 | i915_gem_record_fences(dev, error); |
52d39a21 | 1927 | i915_gem_record_rings(dev, error); |
9df30794 | 1928 | |
c724e8a9 | 1929 | /* Record buffers on the active and pinned lists. */ |
9df30794 | 1930 | error->active_bo = NULL; |
c724e8a9 | 1931 | error->pinned_bo = NULL; |
9df30794 | 1932 | |
bcfb2e28 CW |
1933 | i = 0; |
1934 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) | |
1935 | i++; | |
1936 | error->active_bo_count = i; | |
35c20a60 | 1937 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
1b50247a CW |
1938 | if (obj->pin_count) |
1939 | i++; | |
bcfb2e28 | 1940 | error->pinned_bo_count = i - error->active_bo_count; |
c724e8a9 | 1941 | |
8e934dbf CW |
1942 | error->active_bo = NULL; |
1943 | error->pinned_bo = NULL; | |
bcfb2e28 CW |
1944 | if (i) { |
1945 | error->active_bo = kmalloc(sizeof(*error->active_bo)*i, | |
9df30794 | 1946 | GFP_ATOMIC); |
c724e8a9 CW |
1947 | if (error->active_bo) |
1948 | error->pinned_bo = | |
1949 | error->active_bo + error->active_bo_count; | |
9df30794 CW |
1950 | } |
1951 | ||
c724e8a9 CW |
1952 | if (error->active_bo) |
1953 | error->active_bo_count = | |
1b50247a CW |
1954 | capture_active_bo(error->active_bo, |
1955 | error->active_bo_count, | |
1956 | &dev_priv->mm.active_list); | |
c724e8a9 CW |
1957 | |
1958 | if (error->pinned_bo) | |
1959 | error->pinned_bo_count = | |
1b50247a CW |
1960 | capture_pinned_bo(error->pinned_bo, |
1961 | error->pinned_bo_count, | |
6c085a72 | 1962 | &dev_priv->mm.bound_list); |
c724e8a9 | 1963 | |
9df30794 CW |
1964 | do_gettimeofday(&error->time); |
1965 | ||
6ef3d427 | 1966 | error->overlay = intel_overlay_capture_error_state(dev); |
c4a1d9e4 | 1967 | error->display = intel_display_capture_error_state(dev); |
6ef3d427 | 1968 | |
99584db3 DV |
1969 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
1970 | if (dev_priv->gpu_error.first_error == NULL) { | |
1971 | dev_priv->gpu_error.first_error = error; | |
9df30794 CW |
1972 | error = NULL; |
1973 | } | |
99584db3 | 1974 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); |
9df30794 CW |
1975 | |
1976 | if (error) | |
742cbee8 | 1977 | i915_error_state_free(&error->ref); |
9df30794 CW |
1978 | } |
1979 | ||
1980 | void i915_destroy_error_state(struct drm_device *dev) | |
1981 | { | |
1982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1983 | struct drm_i915_error_state *error; | |
6dc0e816 | 1984 | unsigned long flags; |
9df30794 | 1985 | |
99584db3 DV |
1986 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
1987 | error = dev_priv->gpu_error.first_error; | |
1988 | dev_priv->gpu_error.first_error = NULL; | |
1989 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); | |
9df30794 CW |
1990 | |
1991 | if (error) | |
742cbee8 | 1992 | kref_put(&error->ref, i915_error_state_free); |
63eeaf38 | 1993 | } |
3bd3c932 CW |
1994 | #else |
1995 | #define i915_capture_error_state(x) | |
1996 | #endif | |
63eeaf38 | 1997 | |
35aed2e6 | 1998 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
1999 | { |
2000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2001 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2002 | u32 eir = I915_READ(EIR); |
050ee91f | 2003 | int pipe, i; |
8a905236 | 2004 | |
35aed2e6 CW |
2005 | if (!eir) |
2006 | return; | |
8a905236 | 2007 | |
a70491cc | 2008 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2009 | |
bd9854f9 BW |
2010 | i915_get_extra_instdone(dev, instdone); |
2011 | ||
8a905236 JB |
2012 | if (IS_G4X(dev)) { |
2013 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2014 | u32 ipeir = I915_READ(IPEIR_I965); | |
2015 | ||
a70491cc JP |
2016 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2017 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2018 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2019 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2020 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2021 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2022 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2023 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2024 | } |
2025 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2026 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2027 | pr_err("page table error\n"); |
2028 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2029 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2030 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2031 | } |
2032 | } | |
2033 | ||
a6c45cf0 | 2034 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2035 | if (eir & I915_ERROR_PAGE_TABLE) { |
2036 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2037 | pr_err("page table error\n"); |
2038 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2039 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2040 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2041 | } |
2042 | } | |
2043 | ||
2044 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2045 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 2046 | for_each_pipe(pipe) |
a70491cc | 2047 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2048 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2049 | /* pipestat has already been acked */ |
2050 | } | |
2051 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2052 | pr_err("instruction error\n"); |
2053 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2054 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2055 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2056 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2057 | u32 ipeir = I915_READ(IPEIR); |
2058 | ||
a70491cc JP |
2059 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2060 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2061 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2062 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2063 | POSTING_READ(IPEIR); |
8a905236 JB |
2064 | } else { |
2065 | u32 ipeir = I915_READ(IPEIR_I965); | |
2066 | ||
a70491cc JP |
2067 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2068 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2069 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2070 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2071 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2072 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2073 | } |
2074 | } | |
2075 | ||
2076 | I915_WRITE(EIR, eir); | |
3143a2bf | 2077 | POSTING_READ(EIR); |
8a905236 JB |
2078 | eir = I915_READ(EIR); |
2079 | if (eir) { | |
2080 | /* | |
2081 | * some errors might have become stuck, | |
2082 | * mask them. | |
2083 | */ | |
2084 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2085 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2086 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2087 | } | |
35aed2e6 CW |
2088 | } |
2089 | ||
2090 | /** | |
2091 | * i915_handle_error - handle an error interrupt | |
2092 | * @dev: drm device | |
2093 | * | |
2094 | * Do some basic checking of regsiter state at error interrupt time and | |
2095 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2096 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2097 | * so userspace knows something bad happened (should trigger collection | |
2098 | * of a ring dump etc.). | |
2099 | */ | |
527f9e90 | 2100 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
2101 | { |
2102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b4519513 CW |
2103 | struct intel_ring_buffer *ring; |
2104 | int i; | |
35aed2e6 CW |
2105 | |
2106 | i915_capture_error_state(dev); | |
2107 | i915_report_and_clear_eir(dev); | |
8a905236 | 2108 | |
ba1234d1 | 2109 | if (wedged) { |
f69061be DV |
2110 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2111 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2112 | |
11ed50ec | 2113 | /* |
1f83fee0 DV |
2114 | * Wakeup waiting processes so that the reset work item |
2115 | * doesn't deadlock trying to grab various locks. | |
11ed50ec | 2116 | */ |
b4519513 CW |
2117 | for_each_ring(ring, dev_priv, i) |
2118 | wake_up_all(&ring->irq_queue); | |
11ed50ec BG |
2119 | } |
2120 | ||
99584db3 | 2121 | queue_work(dev_priv->wq, &dev_priv->gpu_error.work); |
8a905236 JB |
2122 | } |
2123 | ||
21ad8330 | 2124 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
4e5359cd SF |
2125 | { |
2126 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2127 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
2128 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 2129 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
2130 | struct intel_unpin_work *work; |
2131 | unsigned long flags; | |
2132 | bool stall_detected; | |
2133 | ||
2134 | /* Ignore early vblank irqs */ | |
2135 | if (intel_crtc == NULL) | |
2136 | return; | |
2137 | ||
2138 | spin_lock_irqsave(&dev->event_lock, flags); | |
2139 | work = intel_crtc->unpin_work; | |
2140 | ||
e7d841ca CW |
2141 | if (work == NULL || |
2142 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || | |
2143 | !work->enable_stall_check) { | |
4e5359cd SF |
2144 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
2145 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2146 | return; | |
2147 | } | |
2148 | ||
2149 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 2150 | obj = work->pending_flip_obj; |
a6c45cf0 | 2151 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 2152 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 AR |
2153 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
2154 | obj->gtt_offset; | |
4e5359cd | 2155 | } else { |
9db4a9c7 | 2156 | int dspaddr = DSPADDR(intel_crtc->plane); |
05394f39 | 2157 | stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |
01f2c773 | 2158 | crtc->y * crtc->fb->pitches[0] + |
4e5359cd SF |
2159 | crtc->x * crtc->fb->bits_per_pixel/8); |
2160 | } | |
2161 | ||
2162 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2163 | ||
2164 | if (stall_detected) { | |
2165 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
2166 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
2167 | } | |
2168 | } | |
2169 | ||
42f52ef8 KP |
2170 | /* Called from drm generic code, passed 'crtc' which |
2171 | * we use as a pipe index | |
2172 | */ | |
f71d4af4 | 2173 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
2174 | { |
2175 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 2176 | unsigned long irqflags; |
71e0ffa5 | 2177 | |
5eddb70b | 2178 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2179 | return -EINVAL; |
0a3e67a4 | 2180 | |
1ec14ad3 | 2181 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2182 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
2183 | i915_enable_pipestat(dev_priv, pipe, |
2184 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 2185 | else |
7c463586 KP |
2186 | i915_enable_pipestat(dev_priv, pipe, |
2187 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
8692d00e CW |
2188 | |
2189 | /* maintain vblank delivery even in deep C-states */ | |
2190 | if (dev_priv->info->gen == 3) | |
6b26c86d | 2191 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 2192 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2193 | |
0a3e67a4 JB |
2194 | return 0; |
2195 | } | |
2196 | ||
f71d4af4 | 2197 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
2198 | { |
2199 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2200 | unsigned long irqflags; | |
2201 | ||
2202 | if (!i915_pipe_enabled(dev, pipe)) | |
2203 | return -EINVAL; | |
2204 | ||
2205 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
2206 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | |
0206e353 | 2207 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
f796cf8f JB |
2208 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2209 | ||
2210 | return 0; | |
2211 | } | |
2212 | ||
f71d4af4 | 2213 | static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) |
b1f14ad0 JB |
2214 | { |
2215 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2216 | unsigned long irqflags; | |
2217 | ||
2218 | if (!i915_pipe_enabled(dev, pipe)) | |
2219 | return -EINVAL; | |
2220 | ||
2221 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b615b57a CW |
2222 | ironlake_enable_display_irq(dev_priv, |
2223 | DE_PIPEA_VBLANK_IVB << (5 * pipe)); | |
b1f14ad0 JB |
2224 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2225 | ||
2226 | return 0; | |
2227 | } | |
2228 | ||
7e231dbe JB |
2229 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2230 | { | |
2231 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2232 | unsigned long irqflags; | |
31acc7f5 | 2233 | u32 imr; |
7e231dbe JB |
2234 | |
2235 | if (!i915_pipe_enabled(dev, pipe)) | |
2236 | return -EINVAL; | |
2237 | ||
2238 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7e231dbe | 2239 | imr = I915_READ(VLV_IMR); |
31acc7f5 | 2240 | if (pipe == 0) |
7e231dbe | 2241 | imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 2242 | else |
7e231dbe | 2243 | imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 2244 | I915_WRITE(VLV_IMR, imr); |
31acc7f5 JB |
2245 | i915_enable_pipestat(dev_priv, pipe, |
2246 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe JB |
2247 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2248 | ||
2249 | return 0; | |
2250 | } | |
2251 | ||
42f52ef8 KP |
2252 | /* Called from drm generic code, passed 'crtc' which |
2253 | * we use as a pipe index | |
2254 | */ | |
f71d4af4 | 2255 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
2256 | { |
2257 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 2258 | unsigned long irqflags; |
0a3e67a4 | 2259 | |
1ec14ad3 | 2260 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8692d00e | 2261 | if (dev_priv->info->gen == 3) |
6b26c86d | 2262 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 2263 | |
f796cf8f JB |
2264 | i915_disable_pipestat(dev_priv, pipe, |
2265 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
2266 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
2267 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2268 | } | |
2269 | ||
f71d4af4 | 2270 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
2271 | { |
2272 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2273 | unsigned long irqflags; | |
2274 | ||
2275 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
2276 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? | |
0206e353 | 2277 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
1ec14ad3 | 2278 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
0a3e67a4 JB |
2279 | } |
2280 | ||
f71d4af4 | 2281 | static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) |
b1f14ad0 JB |
2282 | { |
2283 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2284 | unsigned long irqflags; | |
2285 | ||
2286 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b615b57a CW |
2287 | ironlake_disable_display_irq(dev_priv, |
2288 | DE_PIPEA_VBLANK_IVB << (pipe * 5)); | |
b1f14ad0 JB |
2289 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2290 | } | |
2291 | ||
7e231dbe JB |
2292 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2293 | { | |
2294 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2295 | unsigned long irqflags; | |
31acc7f5 | 2296 | u32 imr; |
7e231dbe JB |
2297 | |
2298 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 JB |
2299 | i915_disable_pipestat(dev_priv, pipe, |
2300 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe | 2301 | imr = I915_READ(VLV_IMR); |
31acc7f5 | 2302 | if (pipe == 0) |
7e231dbe | 2303 | imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 2304 | else |
7e231dbe | 2305 | imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 2306 | I915_WRITE(VLV_IMR, imr); |
7e231dbe JB |
2307 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2308 | } | |
2309 | ||
893eead0 CW |
2310 | static u32 |
2311 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 2312 | { |
893eead0 CW |
2313 | return list_entry(ring->request_list.prev, |
2314 | struct drm_i915_gem_request, list)->seqno; | |
2315 | } | |
2316 | ||
9107e9d2 CW |
2317 | static bool |
2318 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) | |
2319 | { | |
2320 | return (list_empty(&ring->request_list) || | |
2321 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2322 | } |
2323 | ||
6274f212 CW |
2324 | static struct intel_ring_buffer * |
2325 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) | |
a24a11e6 CW |
2326 | { |
2327 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6274f212 | 2328 | u32 cmd, ipehr, acthd, acthd_min; |
a24a11e6 CW |
2329 | |
2330 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
2331 | if ((ipehr & ~(0x3 << 16)) != | |
2332 | (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) | |
6274f212 | 2333 | return NULL; |
a24a11e6 CW |
2334 | |
2335 | /* ACTHD is likely pointing to the dword after the actual command, | |
2336 | * so scan backwards until we find the MBOX. | |
2337 | */ | |
6274f212 | 2338 | acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; |
a24a11e6 CW |
2339 | acthd_min = max((int)acthd - 3 * 4, 0); |
2340 | do { | |
2341 | cmd = ioread32(ring->virtual_start + acthd); | |
2342 | if (cmd == ipehr) | |
2343 | break; | |
2344 | ||
2345 | acthd -= 4; | |
2346 | if (acthd < acthd_min) | |
6274f212 | 2347 | return NULL; |
a24a11e6 CW |
2348 | } while (1); |
2349 | ||
6274f212 CW |
2350 | *seqno = ioread32(ring->virtual_start+acthd+4)+1; |
2351 | return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; | |
a24a11e6 CW |
2352 | } |
2353 | ||
6274f212 CW |
2354 | static int semaphore_passed(struct intel_ring_buffer *ring) |
2355 | { | |
2356 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2357 | struct intel_ring_buffer *signaller; | |
2358 | u32 seqno, ctl; | |
2359 | ||
2360 | ring->hangcheck.deadlock = true; | |
2361 | ||
2362 | signaller = semaphore_waits_for(ring, &seqno); | |
2363 | if (signaller == NULL || signaller->hangcheck.deadlock) | |
2364 | return -1; | |
2365 | ||
2366 | /* cursory check for an unkickable deadlock */ | |
2367 | ctl = I915_READ_CTL(signaller); | |
2368 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) | |
2369 | return -1; | |
2370 | ||
2371 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); | |
2372 | } | |
2373 | ||
2374 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2375 | { | |
2376 | struct intel_ring_buffer *ring; | |
2377 | int i; | |
2378 | ||
2379 | for_each_ring(ring, dev_priv, i) | |
2380 | ring->hangcheck.deadlock = false; | |
2381 | } | |
2382 | ||
2383 | static enum { wait, active, kick, hung } ring_stuck(struct intel_ring_buffer *ring, u32 acthd) | |
1ec14ad3 CW |
2384 | { |
2385 | struct drm_device *dev = ring->dev; | |
2386 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2387 | u32 tmp; |
2388 | ||
6274f212 CW |
2389 | if (ring->hangcheck.acthd != acthd) |
2390 | return active; | |
2391 | ||
9107e9d2 | 2392 | if (IS_GEN2(dev)) |
6274f212 | 2393 | return hung; |
9107e9d2 CW |
2394 | |
2395 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2396 | * If so we can simply poke the RB_WAIT bit | |
2397 | * and break the hang. This should work on | |
2398 | * all but the second generation chipsets. | |
2399 | */ | |
2400 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 CW |
2401 | if (tmp & RING_WAIT) { |
2402 | DRM_ERROR("Kicking stuck wait on %s\n", | |
2403 | ring->name); | |
2404 | I915_WRITE_CTL(ring, tmp); | |
6274f212 CW |
2405 | return kick; |
2406 | } | |
2407 | ||
2408 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2409 | switch (semaphore_passed(ring)) { | |
2410 | default: | |
2411 | return hung; | |
2412 | case 1: | |
2413 | DRM_ERROR("Kicking stuck semaphore on %s\n", | |
2414 | ring->name); | |
2415 | I915_WRITE_CTL(ring, tmp); | |
2416 | return kick; | |
2417 | case 0: | |
2418 | return wait; | |
2419 | } | |
9107e9d2 | 2420 | } |
ed5cbb03 | 2421 | |
6274f212 | 2422 | return hung; |
ed5cbb03 MK |
2423 | } |
2424 | ||
f65d9421 BG |
2425 | /** |
2426 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2427 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2428 | * if there are no progress, hangcheck score for that ring is increased. | |
2429 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2430 | * we kick the ring. If we see no progress on three subsequent calls | |
2431 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 BG |
2432 | */ |
2433 | void i915_hangcheck_elapsed(unsigned long data) | |
2434 | { | |
2435 | struct drm_device *dev = (struct drm_device *)data; | |
2436 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2437 | struct intel_ring_buffer *ring; |
b4519513 | 2438 | int i; |
05407ff8 | 2439 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2440 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2441 | #define BUSY 1 | |
2442 | #define KICK 5 | |
2443 | #define HUNG 20 | |
2444 | #define FIRE 30 | |
893eead0 | 2445 | |
3e0dc6b0 BW |
2446 | if (!i915_enable_hangcheck) |
2447 | return; | |
2448 | ||
b4519513 | 2449 | for_each_ring(ring, dev_priv, i) { |
05407ff8 | 2450 | u32 seqno, acthd; |
9107e9d2 | 2451 | bool busy = true; |
05407ff8 | 2452 | |
6274f212 CW |
2453 | semaphore_clear_deadlocks(dev_priv); |
2454 | ||
05407ff8 MK |
2455 | seqno = ring->get_seqno(ring, false); |
2456 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2457 | |
9107e9d2 CW |
2458 | if (ring->hangcheck.seqno == seqno) { |
2459 | if (ring_idle(ring, seqno)) { | |
2460 | if (waitqueue_active(&ring->irq_queue)) { | |
2461 | /* Issue a wake-up to catch stuck h/w. */ | |
2462 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2463 | ring->name); | |
2464 | wake_up_all(&ring->irq_queue); | |
2465 | ring->hangcheck.score += HUNG; | |
2466 | } else | |
2467 | busy = false; | |
05407ff8 | 2468 | } else { |
9107e9d2 CW |
2469 | int score; |
2470 | ||
6274f212 CW |
2471 | /* We always increment the hangcheck score |
2472 | * if the ring is busy and still processing | |
2473 | * the same request, so that no single request | |
2474 | * can run indefinitely (such as a chain of | |
2475 | * batches). The only time we do not increment | |
2476 | * the hangcheck score on this ring, if this | |
2477 | * ring is in a legitimate wait for another | |
2478 | * ring. In that case the waiting ring is a | |
2479 | * victim and we want to be sure we catch the | |
2480 | * right culprit. Then every time we do kick | |
2481 | * the ring, add a small increment to the | |
2482 | * score so that we can catch a batch that is | |
2483 | * being repeatedly kicked and so responsible | |
2484 | * for stalling the machine. | |
2485 | */ | |
2486 | switch (ring_stuck(ring, acthd)) { | |
2487 | case wait: | |
2488 | score = 0; | |
2489 | break; | |
2490 | case active: | |
9107e9d2 | 2491 | score = BUSY; |
6274f212 CW |
2492 | break; |
2493 | case kick: | |
2494 | score = KICK; | |
2495 | break; | |
2496 | case hung: | |
2497 | score = HUNG; | |
2498 | stuck[i] = true; | |
2499 | break; | |
2500 | } | |
9107e9d2 | 2501 | ring->hangcheck.score += score; |
05407ff8 | 2502 | } |
9107e9d2 CW |
2503 | } else { |
2504 | /* Gradually reduce the count so that we catch DoS | |
2505 | * attempts across multiple batches. | |
2506 | */ | |
2507 | if (ring->hangcheck.score > 0) | |
2508 | ring->hangcheck.score--; | |
d1e61e7f CW |
2509 | } |
2510 | ||
05407ff8 MK |
2511 | ring->hangcheck.seqno = seqno; |
2512 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2513 | busy_count += busy; |
893eead0 | 2514 | } |
b9201c14 | 2515 | |
92cab734 | 2516 | for_each_ring(ring, dev_priv, i) { |
9107e9d2 | 2517 | if (ring->hangcheck.score > FIRE) { |
05407ff8 MK |
2518 | rings_hung++; |
2519 | DRM_ERROR("%s: %s on %s 0x%x\n", ring->name, | |
2520 | stuck[i] ? "stuck" : "no progress", | |
2521 | stuck[i] ? "addr" : "seqno", | |
2522 | stuck[i] ? ring->hangcheck.acthd & HEAD_ADDR : | |
2523 | ring->hangcheck.seqno); | |
92cab734 MK |
2524 | } |
2525 | } | |
2526 | ||
05407ff8 MK |
2527 | if (rings_hung) |
2528 | return i915_handle_error(dev, true); | |
f65d9421 | 2529 | |
05407ff8 MK |
2530 | if (busy_count) |
2531 | /* Reset timer case chip hangs without another request | |
2532 | * being added */ | |
2533 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
2534 | round_jiffies_up(jiffies + | |
2535 | DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2536 | } |
2537 | ||
91738a95 PZ |
2538 | static void ibx_irq_preinstall(struct drm_device *dev) |
2539 | { | |
2540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2541 | ||
2542 | if (HAS_PCH_NOP(dev)) | |
2543 | return; | |
2544 | ||
2545 | /* south display irq */ | |
2546 | I915_WRITE(SDEIMR, 0xffffffff); | |
2547 | /* | |
2548 | * SDEIER is also touched by the interrupt handler to work around missed | |
2549 | * PCH interrupts. Hence we can't update it after the interrupt handler | |
2550 | * is enabled - instead we unconditionally enable all PCH interrupt | |
2551 | * sources here, but then only unmask them as needed with SDEIMR. | |
2552 | */ | |
2553 | I915_WRITE(SDEIER, 0xffffffff); | |
2554 | POSTING_READ(SDEIER); | |
2555 | } | |
2556 | ||
1da177e4 LT |
2557 | /* drm_dma.h hooks |
2558 | */ | |
f71d4af4 | 2559 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
2560 | { |
2561 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2562 | ||
4697995b JB |
2563 | atomic_set(&dev_priv->irq_received, 0); |
2564 | ||
036a4a7d | 2565 | I915_WRITE(HWSTAM, 0xeffe); |
bdfcdb63 | 2566 | |
036a4a7d ZW |
2567 | /* XXX hotplug from PCH */ |
2568 | ||
2569 | I915_WRITE(DEIMR, 0xffffffff); | |
2570 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 2571 | POSTING_READ(DEIER); |
036a4a7d ZW |
2572 | |
2573 | /* and GT */ | |
2574 | I915_WRITE(GTIMR, 0xffffffff); | |
2575 | I915_WRITE(GTIER, 0x0); | |
3143a2bf | 2576 | POSTING_READ(GTIER); |
c650156a | 2577 | |
91738a95 | 2578 | ibx_irq_preinstall(dev); |
7d99163d BW |
2579 | } |
2580 | ||
2581 | static void ivybridge_irq_preinstall(struct drm_device *dev) | |
2582 | { | |
2583 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2584 | ||
2585 | atomic_set(&dev_priv->irq_received, 0); | |
2586 | ||
2587 | I915_WRITE(HWSTAM, 0xeffe); | |
2588 | ||
2589 | /* XXX hotplug from PCH */ | |
2590 | ||
2591 | I915_WRITE(DEIMR, 0xffffffff); | |
2592 | I915_WRITE(DEIER, 0x0); | |
2593 | POSTING_READ(DEIER); | |
2594 | ||
2595 | /* and GT */ | |
2596 | I915_WRITE(GTIMR, 0xffffffff); | |
2597 | I915_WRITE(GTIER, 0x0); | |
2598 | POSTING_READ(GTIER); | |
2599 | ||
eda63ffb BW |
2600 | /* Power management */ |
2601 | I915_WRITE(GEN6_PMIMR, 0xffffffff); | |
2602 | I915_WRITE(GEN6_PMIER, 0x0); | |
2603 | POSTING_READ(GEN6_PMIER); | |
2604 | ||
91738a95 | 2605 | ibx_irq_preinstall(dev); |
036a4a7d ZW |
2606 | } |
2607 | ||
7e231dbe JB |
2608 | static void valleyview_irq_preinstall(struct drm_device *dev) |
2609 | { | |
2610 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2611 | int pipe; | |
2612 | ||
2613 | atomic_set(&dev_priv->irq_received, 0); | |
2614 | ||
7e231dbe JB |
2615 | /* VLV magic */ |
2616 | I915_WRITE(VLV_IMR, 0); | |
2617 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
2618 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
2619 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
2620 | ||
7e231dbe JB |
2621 | /* and GT */ |
2622 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2623 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2624 | I915_WRITE(GTIMR, 0xffffffff); | |
2625 | I915_WRITE(GTIER, 0x0); | |
2626 | POSTING_READ(GTIER); | |
2627 | ||
2628 | I915_WRITE(DPINVGTT, 0xff); | |
2629 | ||
2630 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2631 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2632 | for_each_pipe(pipe) | |
2633 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2634 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2635 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2636 | I915_WRITE(VLV_IER, 0x0); | |
2637 | POSTING_READ(VLV_IER); | |
2638 | } | |
2639 | ||
82a28bcf | 2640 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 KP |
2641 | { |
2642 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
82a28bcf DV |
2643 | struct drm_mode_config *mode_config = &dev->mode_config; |
2644 | struct intel_encoder *intel_encoder; | |
2645 | u32 mask = ~I915_READ(SDEIMR); | |
2646 | u32 hotplug; | |
2647 | ||
2648 | if (HAS_PCH_IBX(dev)) { | |
995e6b3d | 2649 | mask &= ~SDE_HOTPLUG_MASK; |
82a28bcf | 2650 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed EE |
2651 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
2652 | mask |= hpd_ibx[intel_encoder->hpd_pin]; | |
82a28bcf | 2653 | } else { |
995e6b3d | 2654 | mask &= ~SDE_HOTPLUG_MASK_CPT; |
82a28bcf | 2655 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed EE |
2656 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
2657 | mask |= hpd_cpt[intel_encoder->hpd_pin]; | |
82a28bcf | 2658 | } |
7fe0b973 | 2659 | |
82a28bcf DV |
2660 | I915_WRITE(SDEIMR, ~mask); |
2661 | ||
2662 | /* | |
2663 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
2664 | * duration to 2ms (which is the minimum in the Display Port spec) | |
2665 | * | |
2666 | * This register is the same on all known PCH chips. | |
2667 | */ | |
7fe0b973 KP |
2668 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
2669 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
2670 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
2671 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
2672 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
2673 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
2674 | } | |
2675 | ||
d46da437 PZ |
2676 | static void ibx_irq_postinstall(struct drm_device *dev) |
2677 | { | |
2678 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
82a28bcf | 2679 | u32 mask; |
e5868a31 | 2680 | |
692a04cf DV |
2681 | if (HAS_PCH_NOP(dev)) |
2682 | return; | |
2683 | ||
8664281b PZ |
2684 | if (HAS_PCH_IBX(dev)) { |
2685 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER | | |
de032bf4 | 2686 | SDE_TRANSA_FIFO_UNDER | SDE_POISON; |
8664281b PZ |
2687 | } else { |
2688 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT; | |
2689 | ||
2690 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
2691 | } | |
ab5c608b | 2692 | |
d46da437 PZ |
2693 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
2694 | I915_WRITE(SDEIMR, ~mask); | |
d46da437 PZ |
2695 | } |
2696 | ||
f71d4af4 | 2697 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
2698 | { |
2699 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2700 | /* enable kind of interrupts always enabled */ | |
013d5aa2 | 2701 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
ce99c256 | 2702 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | |
8664281b | 2703 | DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN | |
de032bf4 | 2704 | DE_PIPEA_FIFO_UNDERRUN | DE_POISON; |
cc609d5d | 2705 | u32 gt_irqs; |
036a4a7d | 2706 | |
1ec14ad3 | 2707 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
2708 | |
2709 | /* should always can generate irq */ | |
2710 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 CW |
2711 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
2712 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); | |
3143a2bf | 2713 | POSTING_READ(DEIER); |
036a4a7d | 2714 | |
1ec14ad3 | 2715 | dev_priv->gt_irq_mask = ~0; |
036a4a7d ZW |
2716 | |
2717 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1ec14ad3 | 2718 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
881f47b6 | 2719 | |
cc609d5d BW |
2720 | gt_irqs = GT_RENDER_USER_INTERRUPT; |
2721 | ||
1ec14ad3 | 2722 | if (IS_GEN6(dev)) |
cc609d5d | 2723 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; |
1ec14ad3 | 2724 | else |
cc609d5d BW |
2725 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | |
2726 | ILK_BSD_USER_INTERRUPT; | |
2727 | ||
2728 | I915_WRITE(GTIER, gt_irqs); | |
3143a2bf | 2729 | POSTING_READ(GTIER); |
036a4a7d | 2730 | |
d46da437 | 2731 | ibx_irq_postinstall(dev); |
7fe0b973 | 2732 | |
f97108d1 JB |
2733 | if (IS_IRONLAKE_M(dev)) { |
2734 | /* Clear & enable PCU event interrupts */ | |
2735 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
2736 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
2737 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
2738 | } | |
2739 | ||
036a4a7d ZW |
2740 | return 0; |
2741 | } | |
2742 | ||
f71d4af4 | 2743 | static int ivybridge_irq_postinstall(struct drm_device *dev) |
b1f14ad0 JB |
2744 | { |
2745 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2746 | /* enable kind of interrupts always enabled */ | |
b615b57a CW |
2747 | u32 display_mask = |
2748 | DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | | |
2749 | DE_PLANEC_FLIP_DONE_IVB | | |
2750 | DE_PLANEB_FLIP_DONE_IVB | | |
ce99c256 | 2751 | DE_PLANEA_FLIP_DONE_IVB | |
8664281b PZ |
2752 | DE_AUX_CHANNEL_A_IVB | |
2753 | DE_ERR_INT_IVB; | |
12638c57 | 2754 | u32 pm_irqs = GEN6_PM_RPS_EVENTS; |
cc609d5d | 2755 | u32 gt_irqs; |
b1f14ad0 | 2756 | |
b1f14ad0 JB |
2757 | dev_priv->irq_mask = ~display_mask; |
2758 | ||
2759 | /* should always can generate irq */ | |
8664281b | 2760 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); |
b1f14ad0 JB |
2761 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
2762 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
b615b57a CW |
2763 | I915_WRITE(DEIER, |
2764 | display_mask | | |
2765 | DE_PIPEC_VBLANK_IVB | | |
2766 | DE_PIPEB_VBLANK_IVB | | |
2767 | DE_PIPEA_VBLANK_IVB); | |
b1f14ad0 JB |
2768 | POSTING_READ(DEIER); |
2769 | ||
cc609d5d | 2770 | dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
b1f14ad0 JB |
2771 | |
2772 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2773 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
2774 | ||
cc609d5d BW |
2775 | gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT | |
2776 | GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
2777 | I915_WRITE(GTIER, gt_irqs); | |
b1f14ad0 JB |
2778 | POSTING_READ(GTIER); |
2779 | ||
12638c57 BW |
2780 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
2781 | if (HAS_VEBOX(dev)) | |
2782 | pm_irqs |= PM_VEBOX_USER_INTERRUPT | | |
2783 | PM_VEBOX_CS_ERROR_INTERRUPT; | |
2784 | ||
2785 | /* Our enable/disable rps functions may touch these registers so | |
2786 | * make sure to set a known state for only the non-RPS bits. | |
2787 | * The RMW is extra paranoia since this should be called after being set | |
2788 | * to a known state in preinstall. | |
2789 | * */ | |
2790 | I915_WRITE(GEN6_PMIMR, | |
2791 | (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs); | |
2792 | I915_WRITE(GEN6_PMIER, | |
2793 | (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs); | |
2794 | POSTING_READ(GEN6_PMIER); | |
eda63ffb | 2795 | |
d46da437 | 2796 | ibx_irq_postinstall(dev); |
7fe0b973 | 2797 | |
b1f14ad0 JB |
2798 | return 0; |
2799 | } | |
2800 | ||
7e231dbe JB |
2801 | static int valleyview_irq_postinstall(struct drm_device *dev) |
2802 | { | |
2803 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
cc609d5d | 2804 | u32 gt_irqs; |
7e231dbe | 2805 | u32 enable_mask; |
31acc7f5 | 2806 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; |
7e231dbe JB |
2807 | |
2808 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; | |
31acc7f5 JB |
2809 | enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
2810 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2811 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
7e231dbe JB |
2812 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
2813 | ||
31acc7f5 JB |
2814 | /* |
2815 | *Leave vblank interrupts masked initially. enable/disable will | |
2816 | * toggle them based on usage. | |
2817 | */ | |
2818 | dev_priv->irq_mask = (~enable_mask) | | |
2819 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2820 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
7e231dbe | 2821 | |
20afbda2 DV |
2822 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2823 | POSTING_READ(PORT_HOTPLUG_EN); | |
2824 | ||
7e231dbe JB |
2825 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
2826 | I915_WRITE(VLV_IER, enable_mask); | |
2827 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2828 | I915_WRITE(PIPESTAT(0), 0xffff); | |
2829 | I915_WRITE(PIPESTAT(1), 0xffff); | |
2830 | POSTING_READ(VLV_IER); | |
2831 | ||
31acc7f5 | 2832 | i915_enable_pipestat(dev_priv, 0, pipestat_enable); |
515ac2bb | 2833 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); |
31acc7f5 JB |
2834 | i915_enable_pipestat(dev_priv, 1, pipestat_enable); |
2835 | ||
7e231dbe JB |
2836 | I915_WRITE(VLV_IIR, 0xffffffff); |
2837 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2838 | ||
7e231dbe | 2839 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
31acc7f5 | 2840 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
3bcedbe5 | 2841 | |
cc609d5d BW |
2842 | gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT | |
2843 | GT_BLT_USER_INTERRUPT; | |
2844 | I915_WRITE(GTIER, gt_irqs); | |
7e231dbe JB |
2845 | POSTING_READ(GTIER); |
2846 | ||
2847 | /* ack & enable invalid PTE error interrupts */ | |
2848 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
2849 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
2850 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
2851 | #endif | |
2852 | ||
2853 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
2854 | |
2855 | return 0; | |
2856 | } | |
2857 | ||
7e231dbe JB |
2858 | static void valleyview_irq_uninstall(struct drm_device *dev) |
2859 | { | |
2860 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2861 | int pipe; | |
2862 | ||
2863 | if (!dev_priv) | |
2864 | return; | |
2865 | ||
ac4c16c5 EE |
2866 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
2867 | ||
7e231dbe JB |
2868 | for_each_pipe(pipe) |
2869 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2870 | ||
2871 | I915_WRITE(HWSTAM, 0xffffffff); | |
2872 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2873 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2874 | for_each_pipe(pipe) | |
2875 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2876 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2877 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2878 | I915_WRITE(VLV_IER, 0x0); | |
2879 | POSTING_READ(VLV_IER); | |
2880 | } | |
2881 | ||
f71d4af4 | 2882 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
2883 | { |
2884 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
4697995b JB |
2885 | |
2886 | if (!dev_priv) | |
2887 | return; | |
2888 | ||
ac4c16c5 EE |
2889 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
2890 | ||
036a4a7d ZW |
2891 | I915_WRITE(HWSTAM, 0xffffffff); |
2892 | ||
2893 | I915_WRITE(DEIMR, 0xffffffff); | |
2894 | I915_WRITE(DEIER, 0x0); | |
2895 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
8664281b PZ |
2896 | if (IS_GEN7(dev)) |
2897 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
036a4a7d ZW |
2898 | |
2899 | I915_WRITE(GTIMR, 0xffffffff); | |
2900 | I915_WRITE(GTIER, 0x0); | |
2901 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
192aac1f | 2902 | |
ab5c608b BW |
2903 | if (HAS_PCH_NOP(dev)) |
2904 | return; | |
2905 | ||
192aac1f KP |
2906 | I915_WRITE(SDEIMR, 0xffffffff); |
2907 | I915_WRITE(SDEIER, 0x0); | |
2908 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
8664281b PZ |
2909 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) |
2910 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
036a4a7d ZW |
2911 | } |
2912 | ||
a266c7d5 | 2913 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
2914 | { |
2915 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 2916 | int pipe; |
91e3738e | 2917 | |
a266c7d5 | 2918 | atomic_set(&dev_priv->irq_received, 0); |
5ca58282 | 2919 | |
9db4a9c7 JB |
2920 | for_each_pipe(pipe) |
2921 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
2922 | I915_WRITE16(IMR, 0xffff); |
2923 | I915_WRITE16(IER, 0x0); | |
2924 | POSTING_READ16(IER); | |
c2798b19 CW |
2925 | } |
2926 | ||
2927 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
2928 | { | |
2929 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2930 | ||
c2798b19 CW |
2931 | I915_WRITE16(EMR, |
2932 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
2933 | ||
2934 | /* Unmask the interrupts that we always want on. */ | |
2935 | dev_priv->irq_mask = | |
2936 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2937 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2938 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2939 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
2940 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2941 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
2942 | ||
2943 | I915_WRITE16(IER, | |
2944 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2945 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2946 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
2947 | I915_USER_INTERRUPT); | |
2948 | POSTING_READ16(IER); | |
2949 | ||
2950 | return 0; | |
2951 | } | |
2952 | ||
90a72f87 VS |
2953 | /* |
2954 | * Returns true when a page flip has completed. | |
2955 | */ | |
2956 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
2957 | int pipe, u16 iir) | |
2958 | { | |
2959 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2960 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe); | |
2961 | ||
2962 | if (!drm_handle_vblank(dev, pipe)) | |
2963 | return false; | |
2964 | ||
2965 | if ((iir & flip_pending) == 0) | |
2966 | return false; | |
2967 | ||
2968 | intel_prepare_page_flip(dev, pipe); | |
2969 | ||
2970 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
2971 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
2972 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
2973 | * the flip is completed (no longer pending). Since this doesn't raise | |
2974 | * an interrupt per se, we watch for the change at vblank. | |
2975 | */ | |
2976 | if (I915_READ16(ISR) & flip_pending) | |
2977 | return false; | |
2978 | ||
2979 | intel_finish_page_flip(dev, pipe); | |
2980 | ||
2981 | return true; | |
2982 | } | |
2983 | ||
ff1f525e | 2984 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 CW |
2985 | { |
2986 | struct drm_device *dev = (struct drm_device *) arg; | |
2987 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
c2798b19 CW |
2988 | u16 iir, new_iir; |
2989 | u32 pipe_stats[2]; | |
2990 | unsigned long irqflags; | |
2991 | int irq_received; | |
2992 | int pipe; | |
2993 | u16 flip_mask = | |
2994 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2995 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
2996 | ||
2997 | atomic_inc(&dev_priv->irq_received); | |
2998 | ||
2999 | iir = I915_READ16(IIR); | |
3000 | if (iir == 0) | |
3001 | return IRQ_NONE; | |
3002 | ||
3003 | while (iir & ~flip_mask) { | |
3004 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3005 | * have been cleared after the pipestat interrupt was received. | |
3006 | * It doesn't set the bit in iir again, but it still produces | |
3007 | * interrupts (for non-MSI). | |
3008 | */ | |
3009 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3010 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3011 | i915_handle_error(dev, false); | |
3012 | ||
3013 | for_each_pipe(pipe) { | |
3014 | int reg = PIPESTAT(pipe); | |
3015 | pipe_stats[pipe] = I915_READ(reg); | |
3016 | ||
3017 | /* | |
3018 | * Clear the PIPE*STAT regs before the IIR | |
3019 | */ | |
3020 | if (pipe_stats[pipe] & 0x8000ffff) { | |
3021 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
3022 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
3023 | pipe_name(pipe)); | |
3024 | I915_WRITE(reg, pipe_stats[pipe]); | |
3025 | irq_received = 1; | |
3026 | } | |
3027 | } | |
3028 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3029 | ||
3030 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3031 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3032 | ||
d05c617e | 3033 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
3034 | |
3035 | if (iir & I915_USER_INTERRUPT) | |
3036 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3037 | ||
3038 | if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && | |
90a72f87 VS |
3039 | i8xx_handle_vblank(dev, 0, iir)) |
3040 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0); | |
c2798b19 CW |
3041 | |
3042 | if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && | |
90a72f87 VS |
3043 | i8xx_handle_vblank(dev, 1, iir)) |
3044 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1); | |
c2798b19 CW |
3045 | |
3046 | iir = new_iir; | |
3047 | } | |
3048 | ||
3049 | return IRQ_HANDLED; | |
3050 | } | |
3051 | ||
3052 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3053 | { | |
3054 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3055 | int pipe; | |
3056 | ||
c2798b19 CW |
3057 | for_each_pipe(pipe) { |
3058 | /* Clear enable bits; then clear status bits */ | |
3059 | I915_WRITE(PIPESTAT(pipe), 0); | |
3060 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3061 | } | |
3062 | I915_WRITE16(IMR, 0xffff); | |
3063 | I915_WRITE16(IER, 0x0); | |
3064 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3065 | } | |
3066 | ||
a266c7d5 CW |
3067 | static void i915_irq_preinstall(struct drm_device * dev) |
3068 | { | |
3069 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3070 | int pipe; | |
3071 | ||
3072 | atomic_set(&dev_priv->irq_received, 0); | |
3073 | ||
3074 | if (I915_HAS_HOTPLUG(dev)) { | |
3075 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3076 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3077 | } | |
3078 | ||
00d98ebd | 3079 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
3080 | for_each_pipe(pipe) |
3081 | I915_WRITE(PIPESTAT(pipe), 0); | |
3082 | I915_WRITE(IMR, 0xffffffff); | |
3083 | I915_WRITE(IER, 0x0); | |
3084 | POSTING_READ(IER); | |
3085 | } | |
3086 | ||
3087 | static int i915_irq_postinstall(struct drm_device *dev) | |
3088 | { | |
3089 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
38bde180 | 3090 | u32 enable_mask; |
a266c7d5 | 3091 | |
38bde180 CW |
3092 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3093 | ||
3094 | /* Unmask the interrupts that we always want on. */ | |
3095 | dev_priv->irq_mask = | |
3096 | ~(I915_ASLE_INTERRUPT | | |
3097 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3098 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3099 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3100 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3101 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3102 | ||
3103 | enable_mask = | |
3104 | I915_ASLE_INTERRUPT | | |
3105 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3106 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3107 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3108 | I915_USER_INTERRUPT; | |
3109 | ||
a266c7d5 | 3110 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3111 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3112 | POSTING_READ(PORT_HOTPLUG_EN); | |
3113 | ||
a266c7d5 CW |
3114 | /* Enable in IER... */ |
3115 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3116 | /* and unmask in IMR */ | |
3117 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3118 | } | |
3119 | ||
a266c7d5 CW |
3120 | I915_WRITE(IMR, dev_priv->irq_mask); |
3121 | I915_WRITE(IER, enable_mask); | |
3122 | POSTING_READ(IER); | |
3123 | ||
f49e38dd | 3124 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
3125 | |
3126 | return 0; | |
3127 | } | |
3128 | ||
90a72f87 VS |
3129 | /* |
3130 | * Returns true when a page flip has completed. | |
3131 | */ | |
3132 | static bool i915_handle_vblank(struct drm_device *dev, | |
3133 | int plane, int pipe, u32 iir) | |
3134 | { | |
3135 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3136 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
3137 | ||
3138 | if (!drm_handle_vblank(dev, pipe)) | |
3139 | return false; | |
3140 | ||
3141 | if ((iir & flip_pending) == 0) | |
3142 | return false; | |
3143 | ||
3144 | intel_prepare_page_flip(dev, plane); | |
3145 | ||
3146 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3147 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3148 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3149 | * the flip is completed (no longer pending). Since this doesn't raise | |
3150 | * an interrupt per se, we watch for the change at vblank. | |
3151 | */ | |
3152 | if (I915_READ(ISR) & flip_pending) | |
3153 | return false; | |
3154 | ||
3155 | intel_finish_page_flip(dev, pipe); | |
3156 | ||
3157 | return true; | |
3158 | } | |
3159 | ||
ff1f525e | 3160 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3161 | { |
3162 | struct drm_device *dev = (struct drm_device *) arg; | |
3163 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8291ee90 | 3164 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 3165 | unsigned long irqflags; |
38bde180 CW |
3166 | u32 flip_mask = |
3167 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3168 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3169 | int pipe, ret = IRQ_NONE; |
a266c7d5 CW |
3170 | |
3171 | atomic_inc(&dev_priv->irq_received); | |
3172 | ||
3173 | iir = I915_READ(IIR); | |
38bde180 CW |
3174 | do { |
3175 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3176 | bool blc_event = false; |
a266c7d5 CW |
3177 | |
3178 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3179 | * have been cleared after the pipestat interrupt was received. | |
3180 | * It doesn't set the bit in iir again, but it still produces | |
3181 | * interrupts (for non-MSI). | |
3182 | */ | |
3183 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3184 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3185 | i915_handle_error(dev, false); | |
3186 | ||
3187 | for_each_pipe(pipe) { | |
3188 | int reg = PIPESTAT(pipe); | |
3189 | pipe_stats[pipe] = I915_READ(reg); | |
3190 | ||
38bde180 | 3191 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 CW |
3192 | if (pipe_stats[pipe] & 0x8000ffff) { |
3193 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
3194 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
3195 | pipe_name(pipe)); | |
3196 | I915_WRITE(reg, pipe_stats[pipe]); | |
38bde180 | 3197 | irq_received = true; |
a266c7d5 CW |
3198 | } |
3199 | } | |
3200 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3201 | ||
3202 | if (!irq_received) | |
3203 | break; | |
3204 | ||
a266c7d5 CW |
3205 | /* Consume port. Then clear IIR or we'll miss events */ |
3206 | if ((I915_HAS_HOTPLUG(dev)) && | |
3207 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
3208 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 3209 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
a266c7d5 CW |
3210 | |
3211 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
3212 | hotplug_status); | |
b543fb04 | 3213 | if (hotplug_trigger) { |
cd569aed EE |
3214 | if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915)) |
3215 | i915_hpd_irq_setup(dev); | |
a266c7d5 CW |
3216 | queue_work(dev_priv->wq, |
3217 | &dev_priv->hotplug_work); | |
b543fb04 | 3218 | } |
a266c7d5 | 3219 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
38bde180 | 3220 | POSTING_READ(PORT_HOTPLUG_STAT); |
a266c7d5 CW |
3221 | } |
3222 | ||
38bde180 | 3223 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3224 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3225 | ||
a266c7d5 CW |
3226 | if (iir & I915_USER_INTERRUPT) |
3227 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3228 | |
a266c7d5 | 3229 | for_each_pipe(pipe) { |
38bde180 CW |
3230 | int plane = pipe; |
3231 | if (IS_MOBILE(dev)) | |
3232 | plane = !plane; | |
90a72f87 | 3233 | |
8291ee90 | 3234 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3235 | i915_handle_vblank(dev, plane, pipe, iir)) |
3236 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3237 | |
3238 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3239 | blc_event = true; | |
3240 | } | |
3241 | ||
a266c7d5 CW |
3242 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3243 | intel_opregion_asle_intr(dev); | |
3244 | ||
3245 | /* With MSI, interrupts are only generated when iir | |
3246 | * transitions from zero to nonzero. If another bit got | |
3247 | * set while we were handling the existing iir bits, then | |
3248 | * we would never get another interrupt. | |
3249 | * | |
3250 | * This is fine on non-MSI as well, as if we hit this path | |
3251 | * we avoid exiting the interrupt handler only to generate | |
3252 | * another one. | |
3253 | * | |
3254 | * Note that for MSI this could cause a stray interrupt report | |
3255 | * if an interrupt landed in the time between writing IIR and | |
3256 | * the posting read. This should be rare enough to never | |
3257 | * trigger the 99% of 100,000 interrupts test for disabling | |
3258 | * stray interrupts. | |
3259 | */ | |
38bde180 | 3260 | ret = IRQ_HANDLED; |
a266c7d5 | 3261 | iir = new_iir; |
38bde180 | 3262 | } while (iir & ~flip_mask); |
a266c7d5 | 3263 | |
d05c617e | 3264 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 3265 | |
a266c7d5 CW |
3266 | return ret; |
3267 | } | |
3268 | ||
3269 | static void i915_irq_uninstall(struct drm_device * dev) | |
3270 | { | |
3271 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3272 | int pipe; | |
3273 | ||
ac4c16c5 EE |
3274 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3275 | ||
a266c7d5 CW |
3276 | if (I915_HAS_HOTPLUG(dev)) { |
3277 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3278 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3279 | } | |
3280 | ||
00d98ebd | 3281 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
3282 | for_each_pipe(pipe) { |
3283 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 3284 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3285 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3286 | } | |
a266c7d5 CW |
3287 | I915_WRITE(IMR, 0xffffffff); |
3288 | I915_WRITE(IER, 0x0); | |
3289 | ||
a266c7d5 CW |
3290 | I915_WRITE(IIR, I915_READ(IIR)); |
3291 | } | |
3292 | ||
3293 | static void i965_irq_preinstall(struct drm_device * dev) | |
3294 | { | |
3295 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3296 | int pipe; | |
3297 | ||
3298 | atomic_set(&dev_priv->irq_received, 0); | |
3299 | ||
adca4730 CW |
3300 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3301 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3302 | |
3303 | I915_WRITE(HWSTAM, 0xeffe); | |
3304 | for_each_pipe(pipe) | |
3305 | I915_WRITE(PIPESTAT(pipe), 0); | |
3306 | I915_WRITE(IMR, 0xffffffff); | |
3307 | I915_WRITE(IER, 0x0); | |
3308 | POSTING_READ(IER); | |
3309 | } | |
3310 | ||
3311 | static int i965_irq_postinstall(struct drm_device *dev) | |
3312 | { | |
3313 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
bbba0a97 | 3314 | u32 enable_mask; |
a266c7d5 CW |
3315 | u32 error_mask; |
3316 | ||
a266c7d5 | 3317 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 3318 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 3319 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
3320 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3321 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3322 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3323 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3324 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3325 | ||
3326 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
3327 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
3328 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
3329 | enable_mask |= I915_USER_INTERRUPT; |
3330 | ||
3331 | if (IS_G4X(dev)) | |
3332 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 3333 | |
515ac2bb | 3334 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); |
a266c7d5 | 3335 | |
a266c7d5 CW |
3336 | /* |
3337 | * Enable some error detection, note the instruction error mask | |
3338 | * bit is reserved, so we leave it masked. | |
3339 | */ | |
3340 | if (IS_G4X(dev)) { | |
3341 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
3342 | GM45_ERROR_MEM_PRIV | | |
3343 | GM45_ERROR_CP_PRIV | | |
3344 | I915_ERROR_MEMORY_REFRESH); | |
3345 | } else { | |
3346 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
3347 | I915_ERROR_MEMORY_REFRESH); | |
3348 | } | |
3349 | I915_WRITE(EMR, error_mask); | |
3350 | ||
3351 | I915_WRITE(IMR, dev_priv->irq_mask); | |
3352 | I915_WRITE(IER, enable_mask); | |
3353 | POSTING_READ(IER); | |
3354 | ||
20afbda2 DV |
3355 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3356 | POSTING_READ(PORT_HOTPLUG_EN); | |
3357 | ||
f49e38dd | 3358 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
3359 | |
3360 | return 0; | |
3361 | } | |
3362 | ||
bac56d5b | 3363 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 DV |
3364 | { |
3365 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e5868a31 | 3366 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed | 3367 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
3368 | u32 hotplug_en; |
3369 | ||
bac56d5b EE |
3370 | if (I915_HAS_HOTPLUG(dev)) { |
3371 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
3372 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
3373 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 3374 | /* enable bits are the same for all generations */ |
cd569aed EE |
3375 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
3376 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
3377 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
3378 | /* Programming the CRT detection parameters tends |
3379 | to generate a spurious hotplug event about three | |
3380 | seconds later. So just do it once. | |
3381 | */ | |
3382 | if (IS_G4X(dev)) | |
3383 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 3384 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 3385 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 3386 | |
bac56d5b EE |
3387 | /* Ignore TV since it's buggy */ |
3388 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
3389 | } | |
a266c7d5 CW |
3390 | } |
3391 | ||
ff1f525e | 3392 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3393 | { |
3394 | struct drm_device *dev = (struct drm_device *) arg; | |
3395 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
a266c7d5 CW |
3396 | u32 iir, new_iir; |
3397 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 CW |
3398 | unsigned long irqflags; |
3399 | int irq_received; | |
3400 | int ret = IRQ_NONE, pipe; | |
21ad8330 VS |
3401 | u32 flip_mask = |
3402 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3403 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 CW |
3404 | |
3405 | atomic_inc(&dev_priv->irq_received); | |
3406 | ||
3407 | iir = I915_READ(IIR); | |
3408 | ||
a266c7d5 | 3409 | for (;;) { |
2c8ba29f CW |
3410 | bool blc_event = false; |
3411 | ||
21ad8330 | 3412 | irq_received = (iir & ~flip_mask) != 0; |
a266c7d5 CW |
3413 | |
3414 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3415 | * have been cleared after the pipestat interrupt was received. | |
3416 | * It doesn't set the bit in iir again, but it still produces | |
3417 | * interrupts (for non-MSI). | |
3418 | */ | |
3419 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3420 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3421 | i915_handle_error(dev, false); | |
3422 | ||
3423 | for_each_pipe(pipe) { | |
3424 | int reg = PIPESTAT(pipe); | |
3425 | pipe_stats[pipe] = I915_READ(reg); | |
3426 | ||
3427 | /* | |
3428 | * Clear the PIPE*STAT regs before the IIR | |
3429 | */ | |
3430 | if (pipe_stats[pipe] & 0x8000ffff) { | |
3431 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
3432 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
3433 | pipe_name(pipe)); | |
3434 | I915_WRITE(reg, pipe_stats[pipe]); | |
3435 | irq_received = 1; | |
3436 | } | |
3437 | } | |
3438 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3439 | ||
3440 | if (!irq_received) | |
3441 | break; | |
3442 | ||
3443 | ret = IRQ_HANDLED; | |
3444 | ||
3445 | /* Consume port. Then clear IIR or we'll miss events */ | |
adca4730 | 3446 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
a266c7d5 | 3447 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
b543fb04 EE |
3448 | u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? |
3449 | HOTPLUG_INT_STATUS_G4X : | |
3450 | HOTPLUG_INT_STATUS_I965); | |
a266c7d5 CW |
3451 | |
3452 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
3453 | hotplug_status); | |
b543fb04 | 3454 | if (hotplug_trigger) { |
cd569aed EE |
3455 | if (hotplug_irq_storm_detect(dev, hotplug_trigger, |
3456 | IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965)) | |
3457 | i915_hpd_irq_setup(dev); | |
a266c7d5 CW |
3458 | queue_work(dev_priv->wq, |
3459 | &dev_priv->hotplug_work); | |
b543fb04 | 3460 | } |
a266c7d5 CW |
3461 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
3462 | I915_READ(PORT_HOTPLUG_STAT); | |
3463 | } | |
3464 | ||
21ad8330 | 3465 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3466 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3467 | ||
a266c7d5 CW |
3468 | if (iir & I915_USER_INTERRUPT) |
3469 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3470 | if (iir & I915_BSD_USER_INTERRUPT) | |
3471 | notify_ring(dev, &dev_priv->ring[VCS]); | |
3472 | ||
a266c7d5 | 3473 | for_each_pipe(pipe) { |
2c8ba29f | 3474 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3475 | i915_handle_vblank(dev, pipe, pipe, iir)) |
3476 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
3477 | |
3478 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3479 | blc_event = true; | |
3480 | } | |
3481 | ||
3482 | ||
3483 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3484 | intel_opregion_asle_intr(dev); | |
3485 | ||
515ac2bb DV |
3486 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
3487 | gmbus_irq_handler(dev); | |
3488 | ||
a266c7d5 CW |
3489 | /* With MSI, interrupts are only generated when iir |
3490 | * transitions from zero to nonzero. If another bit got | |
3491 | * set while we were handling the existing iir bits, then | |
3492 | * we would never get another interrupt. | |
3493 | * | |
3494 | * This is fine on non-MSI as well, as if we hit this path | |
3495 | * we avoid exiting the interrupt handler only to generate | |
3496 | * another one. | |
3497 | * | |
3498 | * Note that for MSI this could cause a stray interrupt report | |
3499 | * if an interrupt landed in the time between writing IIR and | |
3500 | * the posting read. This should be rare enough to never | |
3501 | * trigger the 99% of 100,000 interrupts test for disabling | |
3502 | * stray interrupts. | |
3503 | */ | |
3504 | iir = new_iir; | |
3505 | } | |
3506 | ||
d05c617e | 3507 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 3508 | |
a266c7d5 CW |
3509 | return ret; |
3510 | } | |
3511 | ||
3512 | static void i965_irq_uninstall(struct drm_device * dev) | |
3513 | { | |
3514 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3515 | int pipe; | |
3516 | ||
3517 | if (!dev_priv) | |
3518 | return; | |
3519 | ||
ac4c16c5 EE |
3520 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3521 | ||
adca4730 CW |
3522 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3523 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3524 | |
3525 | I915_WRITE(HWSTAM, 0xffffffff); | |
3526 | for_each_pipe(pipe) | |
3527 | I915_WRITE(PIPESTAT(pipe), 0); | |
3528 | I915_WRITE(IMR, 0xffffffff); | |
3529 | I915_WRITE(IER, 0x0); | |
3530 | ||
3531 | for_each_pipe(pipe) | |
3532 | I915_WRITE(PIPESTAT(pipe), | |
3533 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
3534 | I915_WRITE(IIR, I915_READ(IIR)); | |
3535 | } | |
3536 | ||
ac4c16c5 EE |
3537 | static void i915_reenable_hotplug_timer_func(unsigned long data) |
3538 | { | |
3539 | drm_i915_private_t *dev_priv = (drm_i915_private_t *)data; | |
3540 | struct drm_device *dev = dev_priv->dev; | |
3541 | struct drm_mode_config *mode_config = &dev->mode_config; | |
3542 | unsigned long irqflags; | |
3543 | int i; | |
3544 | ||
3545 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3546 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | |
3547 | struct drm_connector *connector; | |
3548 | ||
3549 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
3550 | continue; | |
3551 | ||
3552 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3553 | ||
3554 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3555 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3556 | ||
3557 | if (intel_connector->encoder->hpd_pin == i) { | |
3558 | if (connector->polled != intel_connector->polled) | |
3559 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
3560 | drm_get_connector_name(connector)); | |
3561 | connector->polled = intel_connector->polled; | |
3562 | if (!connector->polled) | |
3563 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3564 | } | |
3565 | } | |
3566 | } | |
3567 | if (dev_priv->display.hpd_irq_setup) | |
3568 | dev_priv->display.hpd_irq_setup(dev); | |
3569 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3570 | } | |
3571 | ||
f71d4af4 JB |
3572 | void intel_irq_init(struct drm_device *dev) |
3573 | { | |
8b2e326d CW |
3574 | struct drm_i915_private *dev_priv = dev->dev_private; |
3575 | ||
3576 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
99584db3 | 3577 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 3578 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 3579 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 3580 | |
99584db3 DV |
3581 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
3582 | i915_hangcheck_elapsed, | |
61bac78e | 3583 | (unsigned long) dev); |
ac4c16c5 EE |
3584 | setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func, |
3585 | (unsigned long) dev_priv); | |
61bac78e | 3586 | |
97a19a24 | 3587 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 3588 | |
f71d4af4 JB |
3589 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
3590 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
7d4e146f | 3591 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
f71d4af4 JB |
3592 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
3593 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
3594 | } | |
3595 | ||
c3613de9 KP |
3596 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3597 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; | |
3598 | else | |
3599 | dev->driver->get_vblank_timestamp = NULL; | |
f71d4af4 JB |
3600 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
3601 | ||
7e231dbe JB |
3602 | if (IS_VALLEYVIEW(dev)) { |
3603 | dev->driver->irq_handler = valleyview_irq_handler; | |
3604 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
3605 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
3606 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
3607 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
3608 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 3609 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
4a06e201 | 3610 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
7d99163d | 3611 | /* Share uninstall handlers with ILK/SNB */ |
f71d4af4 | 3612 | dev->driver->irq_handler = ivybridge_irq_handler; |
7d99163d | 3613 | dev->driver->irq_preinstall = ivybridge_irq_preinstall; |
f71d4af4 JB |
3614 | dev->driver->irq_postinstall = ivybridge_irq_postinstall; |
3615 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
3616 | dev->driver->enable_vblank = ivybridge_enable_vblank; | |
3617 | dev->driver->disable_vblank = ivybridge_disable_vblank; | |
82a28bcf | 3618 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 JB |
3619 | } else if (HAS_PCH_SPLIT(dev)) { |
3620 | dev->driver->irq_handler = ironlake_irq_handler; | |
3621 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
3622 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
3623 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
3624 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
3625 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 3626 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 3627 | } else { |
c2798b19 CW |
3628 | if (INTEL_INFO(dev)->gen == 2) { |
3629 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
3630 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
3631 | dev->driver->irq_handler = i8xx_irq_handler; | |
3632 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 CW |
3633 | } else if (INTEL_INFO(dev)->gen == 3) { |
3634 | dev->driver->irq_preinstall = i915_irq_preinstall; | |
3635 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
3636 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
3637 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 3638 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 3639 | } else { |
a266c7d5 CW |
3640 | dev->driver->irq_preinstall = i965_irq_preinstall; |
3641 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
3642 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
3643 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 3644 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 3645 | } |
f71d4af4 JB |
3646 | dev->driver->enable_vblank = i915_enable_vblank; |
3647 | dev->driver->disable_vblank = i915_disable_vblank; | |
3648 | } | |
3649 | } | |
20afbda2 DV |
3650 | |
3651 | void intel_hpd_init(struct drm_device *dev) | |
3652 | { | |
3653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821450c6 EE |
3654 | struct drm_mode_config *mode_config = &dev->mode_config; |
3655 | struct drm_connector *connector; | |
3656 | int i; | |
20afbda2 | 3657 | |
821450c6 EE |
3658 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3659 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
3660 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3661 | } | |
3662 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3663 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3664 | connector->polled = intel_connector->polled; | |
3665 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) | |
3666 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3667 | } | |
20afbda2 DV |
3668 | if (dev_priv->display.hpd_irq_setup) |
3669 | dev_priv->display.hpd_irq_setup(dev); | |
3670 | } |