Commit | Line | Data |
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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
1da177e4 LT |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "i915_drm.h" | |
33 | #include "i915_drv.h" | |
1c5d22f7 | 34 | #include "i915_trace.h" |
79e53945 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
1da177e4 | 37 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 38 | |
7c463586 KP |
39 | /** |
40 | * Interrupts that are always left unmasked. | |
41 | * | |
42 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
43 | * we leave them always unmasked in IMR and then control enabling them through | |
44 | * PIPESTAT alone. | |
45 | */ | |
63eeaf38 JB |
46 | #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ |
47 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
48 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
49 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
50 | |
51 | /** Interrupts that we mask and unmask at runtime. */ | |
52 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) | |
53 | ||
79e53945 JB |
54 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
55 | PIPE_VBLANK_INTERRUPT_STATUS) | |
56 | ||
57 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
58 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
59 | ||
60 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
61 | DRM_I915_VBLANK_PIPE_B) | |
62 | ||
036a4a7d ZW |
63 | void |
64 | igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) | |
65 | { | |
66 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { | |
67 | dev_priv->gt_irq_mask_reg &= ~mask; | |
68 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
69 | (void) I915_READ(GTIMR); | |
70 | } | |
71 | } | |
72 | ||
73 | static inline void | |
74 | igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) | |
75 | { | |
76 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { | |
77 | dev_priv->gt_irq_mask_reg |= mask; | |
78 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
79 | (void) I915_READ(GTIMR); | |
80 | } | |
81 | } | |
82 | ||
83 | /* For display hotplug interrupt */ | |
84 | void | |
85 | igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) | |
86 | { | |
87 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
88 | dev_priv->irq_mask_reg &= ~mask; | |
89 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
90 | (void) I915_READ(DEIMR); | |
91 | } | |
92 | } | |
93 | ||
94 | static inline void | |
95 | igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) | |
96 | { | |
97 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
98 | dev_priv->irq_mask_reg |= mask; | |
99 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
100 | (void) I915_READ(DEIMR); | |
101 | } | |
102 | } | |
103 | ||
8ee1c3db | 104 | void |
ed4cb414 EA |
105 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
106 | { | |
107 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
108 | dev_priv->irq_mask_reg &= ~mask; | |
109 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
110 | (void) I915_READ(IMR); | |
111 | } | |
112 | } | |
113 | ||
114 | static inline void | |
115 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
116 | { | |
117 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
118 | dev_priv->irq_mask_reg |= mask; | |
119 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
120 | (void) I915_READ(IMR); | |
121 | } | |
122 | } | |
123 | ||
7c463586 KP |
124 | static inline u32 |
125 | i915_pipestat(int pipe) | |
126 | { | |
127 | if (pipe == 0) | |
128 | return PIPEASTAT; | |
129 | if (pipe == 1) | |
130 | return PIPEBSTAT; | |
9c84ba4e | 131 | BUG(); |
7c463586 KP |
132 | } |
133 | ||
134 | void | |
135 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
136 | { | |
137 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
138 | u32 reg = i915_pipestat(pipe); | |
139 | ||
140 | dev_priv->pipestat[pipe] |= mask; | |
141 | /* Enable the interrupt, clear any pending status */ | |
142 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
143 | (void) I915_READ(reg); | |
144 | } | |
145 | } | |
146 | ||
147 | void | |
148 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
149 | { | |
150 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
151 | u32 reg = i915_pipestat(pipe); | |
152 | ||
153 | dev_priv->pipestat[pipe] &= ~mask; | |
154 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
155 | (void) I915_READ(reg); | |
156 | } | |
157 | } | |
158 | ||
0a3e67a4 JB |
159 | /** |
160 | * i915_pipe_enabled - check if a pipe is enabled | |
161 | * @dev: DRM device | |
162 | * @pipe: pipe to check | |
163 | * | |
164 | * Reading certain registers when the pipe is disabled can hang the chip. | |
165 | * Use this routine to make sure the PLL is running and the pipe is active | |
166 | * before reading such registers if unsure. | |
167 | */ | |
168 | static int | |
169 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
170 | { | |
171 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
172 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; | |
173 | ||
174 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) | |
175 | return 1; | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
42f52ef8 KP |
180 | /* Called from drm generic code, passed a 'crtc', which |
181 | * we use as a pipe index | |
182 | */ | |
183 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
184 | { |
185 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
186 | unsigned long high_frame; | |
187 | unsigned long low_frame; | |
188 | u32 high1, high2, low, count; | |
0a3e67a4 | 189 | |
0a3e67a4 JB |
190 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
191 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
192 | ||
193 | if (!i915_pipe_enabled(dev, pipe)) { | |
6cb504c2 | 194 | DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe); |
0a3e67a4 JB |
195 | return 0; |
196 | } | |
197 | ||
198 | /* | |
199 | * High & low register fields aren't synchronized, so make sure | |
200 | * we get a low value that's stable across two reads of the high | |
201 | * register. | |
202 | */ | |
203 | do { | |
204 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
205 | PIPE_FRAME_HIGH_SHIFT); | |
206 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> | |
207 | PIPE_FRAME_LOW_SHIFT); | |
208 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
209 | PIPE_FRAME_HIGH_SHIFT); | |
210 | } while (high1 != high2); | |
211 | ||
212 | count = (high1 << 8) | low; | |
213 | ||
214 | return count; | |
215 | } | |
216 | ||
9880b7a5 JB |
217 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
218 | { | |
219 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
220 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | |
221 | ||
222 | if (!i915_pipe_enabled(dev, pipe)) { | |
6cb504c2 | 223 | DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe); |
9880b7a5 JB |
224 | return 0; |
225 | } | |
226 | ||
227 | return I915_READ(reg); | |
228 | } | |
229 | ||
5ca58282 JB |
230 | /* |
231 | * Handle hotplug events outside the interrupt handler proper. | |
232 | */ | |
233 | static void i915_hotplug_work_func(struct work_struct *work) | |
234 | { | |
235 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
236 | hotplug_work); | |
237 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 KP |
238 | struct drm_mode_config *mode_config = &dev->mode_config; |
239 | struct drm_connector *connector; | |
240 | ||
241 | if (mode_config->num_connector) { | |
242 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
243 | struct intel_output *intel_output = to_intel_output(connector); | |
244 | ||
245 | if (intel_output->hot_plug) | |
246 | (*intel_output->hot_plug) (intel_output); | |
247 | } | |
248 | } | |
5ca58282 JB |
249 | /* Just fire off a uevent and let userspace tell us what to do */ |
250 | drm_sysfs_hotplug_event(dev); | |
251 | } | |
252 | ||
036a4a7d ZW |
253 | irqreturn_t igdng_irq_handler(struct drm_device *dev) |
254 | { | |
255 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
256 | int ret = IRQ_NONE; | |
257 | u32 de_iir, gt_iir; | |
258 | u32 new_de_iir, new_gt_iir; | |
259 | struct drm_i915_master_private *master_priv; | |
260 | ||
261 | de_iir = I915_READ(DEIIR); | |
262 | gt_iir = I915_READ(GTIIR); | |
263 | ||
264 | for (;;) { | |
265 | if (de_iir == 0 && gt_iir == 0) | |
266 | break; | |
267 | ||
268 | ret = IRQ_HANDLED; | |
269 | ||
270 | I915_WRITE(DEIIR, de_iir); | |
271 | new_de_iir = I915_READ(DEIIR); | |
272 | I915_WRITE(GTIIR, gt_iir); | |
273 | new_gt_iir = I915_READ(GTIIR); | |
274 | ||
275 | if (dev->primary->master) { | |
276 | master_priv = dev->primary->master->driver_priv; | |
277 | if (master_priv->sarea_priv) | |
278 | master_priv->sarea_priv->last_dispatch = | |
279 | READ_BREADCRUMB(dev_priv); | |
280 | } | |
281 | ||
282 | if (gt_iir & GT_USER_INTERRUPT) { | |
1c5d22f7 CW |
283 | u32 seqno = i915_get_gem_seqno(dev); |
284 | dev_priv->mm.irq_gem_seqno = seqno; | |
285 | trace_i915_gem_request_complete(dev, seqno); | |
036a4a7d ZW |
286 | DRM_WAKEUP(&dev_priv->irq_queue); |
287 | } | |
288 | ||
289 | de_iir = new_de_iir; | |
290 | gt_iir = new_gt_iir; | |
291 | } | |
292 | ||
293 | return ret; | |
294 | } | |
295 | ||
8a905236 JB |
296 | /** |
297 | * i915_error_work_func - do process context error handling work | |
298 | * @work: work struct | |
299 | * | |
300 | * Fire an error uevent so userspace can see that a hang or error | |
301 | * was detected. | |
302 | */ | |
303 | static void i915_error_work_func(struct work_struct *work) | |
304 | { | |
305 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
306 | error_work); | |
307 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
308 | char *error_event[] = { "ERROR=1", NULL }; |
309 | char *reset_event[] = { "RESET=1", NULL }; | |
310 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 JB |
311 | |
312 | DRM_DEBUG("generating error event\n"); | |
f316a42c BG |
313 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
314 | ||
ba1234d1 | 315 | if (atomic_read(&dev_priv->mm.wedged)) { |
f316a42c BG |
316 | if (IS_I965G(dev)) { |
317 | DRM_DEBUG("resetting chip\n"); | |
318 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | |
319 | if (!i965_reset(dev, GDRST_RENDER)) { | |
ba1234d1 | 320 | atomic_set(&dev_priv->mm.wedged, 0); |
f316a42c BG |
321 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
322 | } | |
323 | } else { | |
324 | printk("reboot required\n"); | |
325 | } | |
326 | } | |
8a905236 JB |
327 | } |
328 | ||
329 | /** | |
330 | * i915_capture_error_state - capture an error record for later analysis | |
331 | * @dev: drm device | |
332 | * | |
333 | * Should be called when an error is detected (either a hang or an error | |
334 | * interrupt) to capture error state from the time of the error. Fills | |
335 | * out a structure which becomes available in debugfs for user level tools | |
336 | * to pick up. | |
337 | */ | |
63eeaf38 JB |
338 | static void i915_capture_error_state(struct drm_device *dev) |
339 | { | |
340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
341 | struct drm_i915_error_state *error; | |
342 | unsigned long flags; | |
343 | ||
344 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
345 | if (dev_priv->first_error) | |
346 | goto out; | |
347 | ||
348 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
349 | if (!error) { | |
350 | DRM_DEBUG("out ot memory, not capturing error state\n"); | |
351 | goto out; | |
352 | } | |
353 | ||
354 | error->eir = I915_READ(EIR); | |
355 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
356 | error->pipeastat = I915_READ(PIPEASTAT); | |
357 | error->pipebstat = I915_READ(PIPEBSTAT); | |
358 | error->instpm = I915_READ(INSTPM); | |
359 | if (!IS_I965G(dev)) { | |
360 | error->ipeir = I915_READ(IPEIR); | |
361 | error->ipehr = I915_READ(IPEHR); | |
362 | error->instdone = I915_READ(INSTDONE); | |
363 | error->acthd = I915_READ(ACTHD); | |
364 | } else { | |
365 | error->ipeir = I915_READ(IPEIR_I965); | |
366 | error->ipehr = I915_READ(IPEHR_I965); | |
367 | error->instdone = I915_READ(INSTDONE_I965); | |
368 | error->instps = I915_READ(INSTPS); | |
369 | error->instdone1 = I915_READ(INSTDONE1); | |
370 | error->acthd = I915_READ(ACTHD_I965); | |
371 | } | |
372 | ||
8a905236 JB |
373 | do_gettimeofday(&error->time); |
374 | ||
63eeaf38 JB |
375 | dev_priv->first_error = error; |
376 | ||
377 | out: | |
378 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
379 | } | |
380 | ||
8a905236 JB |
381 | /** |
382 | * i915_handle_error - handle an error interrupt | |
383 | * @dev: drm device | |
384 | * | |
385 | * Do some basic checking of regsiter state at error interrupt time and | |
386 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
387 | * sure we get a record and make it available in debugfs. Fire a uevent | |
388 | * so userspace knows something bad happened (should trigger collection | |
389 | * of a ring dump etc.). | |
390 | */ | |
ba1234d1 | 391 | static void i915_handle_error(struct drm_device *dev, bool wedged) |
8a905236 JB |
392 | { |
393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
394 | u32 eir = I915_READ(EIR); | |
395 | u32 pipea_stats = I915_READ(PIPEASTAT); | |
396 | u32 pipeb_stats = I915_READ(PIPEBSTAT); | |
397 | ||
398 | i915_capture_error_state(dev); | |
399 | ||
400 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
401 | eir); | |
402 | ||
403 | if (IS_G4X(dev)) { | |
404 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
405 | u32 ipeir = I915_READ(IPEIR_I965); | |
406 | ||
407 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
408 | I915_READ(IPEIR_I965)); | |
409 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
410 | I915_READ(IPEHR_I965)); | |
411 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
412 | I915_READ(INSTDONE_I965)); | |
413 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
414 | I915_READ(INSTPS)); | |
415 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
416 | I915_READ(INSTDONE1)); | |
417 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
418 | I915_READ(ACTHD_I965)); | |
419 | I915_WRITE(IPEIR_I965, ipeir); | |
420 | (void)I915_READ(IPEIR_I965); | |
421 | } | |
422 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
423 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
424 | printk(KERN_ERR "page table error\n"); | |
425 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
426 | pgtbl_err); | |
427 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
428 | (void)I915_READ(PGTBL_ER); | |
429 | } | |
430 | } | |
431 | ||
432 | if (IS_I9XX(dev)) { | |
433 | if (eir & I915_ERROR_PAGE_TABLE) { | |
434 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
435 | printk(KERN_ERR "page table error\n"); | |
436 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
437 | pgtbl_err); | |
438 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
439 | (void)I915_READ(PGTBL_ER); | |
440 | } | |
441 | } | |
442 | ||
443 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
444 | printk(KERN_ERR "memory refresh error\n"); | |
445 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", | |
446 | pipea_stats); | |
447 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", | |
448 | pipeb_stats); | |
449 | /* pipestat has already been acked */ | |
450 | } | |
451 | if (eir & I915_ERROR_INSTRUCTION) { | |
452 | printk(KERN_ERR "instruction error\n"); | |
453 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
454 | I915_READ(INSTPM)); | |
455 | if (!IS_I965G(dev)) { | |
456 | u32 ipeir = I915_READ(IPEIR); | |
457 | ||
458 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
459 | I915_READ(IPEIR)); | |
460 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
461 | I915_READ(IPEHR)); | |
462 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
463 | I915_READ(INSTDONE)); | |
464 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
465 | I915_READ(ACTHD)); | |
466 | I915_WRITE(IPEIR, ipeir); | |
467 | (void)I915_READ(IPEIR); | |
468 | } else { | |
469 | u32 ipeir = I915_READ(IPEIR_I965); | |
470 | ||
471 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
472 | I915_READ(IPEIR_I965)); | |
473 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
474 | I915_READ(IPEHR_I965)); | |
475 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
476 | I915_READ(INSTDONE_I965)); | |
477 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
478 | I915_READ(INSTPS)); | |
479 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
480 | I915_READ(INSTDONE1)); | |
481 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
482 | I915_READ(ACTHD_I965)); | |
483 | I915_WRITE(IPEIR_I965, ipeir); | |
484 | (void)I915_READ(IPEIR_I965); | |
485 | } | |
486 | } | |
487 | ||
488 | I915_WRITE(EIR, eir); | |
489 | (void)I915_READ(EIR); | |
490 | eir = I915_READ(EIR); | |
491 | if (eir) { | |
492 | /* | |
493 | * some errors might have become stuck, | |
494 | * mask them. | |
495 | */ | |
496 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
497 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
498 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
499 | } | |
500 | ||
ba1234d1 BG |
501 | if (wedged) { |
502 | atomic_set(&dev_priv->mm.wedged, 1); | |
503 | ||
11ed50ec BG |
504 | /* |
505 | * Wakeup waiting processes so they don't hang | |
506 | */ | |
507 | printk("i915: Waking up sleeping processes\n"); | |
508 | DRM_WAKEUP(&dev_priv->irq_queue); | |
509 | } | |
510 | ||
9c9fe1f8 | 511 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
512 | } |
513 | ||
1da177e4 LT |
514 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
515 | { | |
84b1fd10 | 516 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 517 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 518 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
519 | u32 iir, new_iir; |
520 | u32 pipea_stats, pipeb_stats; | |
05eff845 KP |
521 | u32 vblank_status; |
522 | u32 vblank_enable; | |
0a3e67a4 | 523 | int vblank = 0; |
7c463586 | 524 | unsigned long irqflags; |
05eff845 KP |
525 | int irq_received; |
526 | int ret = IRQ_NONE; | |
6e5fca53 | 527 | |
630681d9 EA |
528 | atomic_inc(&dev_priv->irq_received); |
529 | ||
036a4a7d ZW |
530 | if (IS_IGDNG(dev)) |
531 | return igdng_irq_handler(dev); | |
532 | ||
ed4cb414 | 533 | iir = I915_READ(IIR); |
a6b54f3f | 534 | |
05eff845 KP |
535 | if (IS_I965G(dev)) { |
536 | vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; | |
537 | vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; | |
538 | } else { | |
539 | vblank_status = I915_VBLANK_INTERRUPT_STATUS; | |
540 | vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; | |
541 | } | |
af6061af | 542 | |
05eff845 KP |
543 | for (;;) { |
544 | irq_received = iir != 0; | |
545 | ||
546 | /* Can't rely on pipestat interrupt bit in iir as it might | |
547 | * have been cleared after the pipestat interrupt was received. | |
548 | * It doesn't set the bit in iir again, but it still produces | |
549 | * interrupts (for non-MSI). | |
550 | */ | |
551 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
552 | pipea_stats = I915_READ(PIPEASTAT); | |
553 | pipeb_stats = I915_READ(PIPEBSTAT); | |
79e53945 | 554 | |
8a905236 | 555 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 556 | i915_handle_error(dev, false); |
8a905236 | 557 | |
cdfbc41f EA |
558 | /* |
559 | * Clear the PIPE(A|B)STAT regs before the IIR | |
560 | */ | |
05eff845 | 561 | if (pipea_stats & 0x8000ffff) { |
7662c8bd SL |
562 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
563 | DRM_DEBUG("pipe a underrun\n"); | |
cdfbc41f | 564 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 565 | irq_received = 1; |
cdfbc41f | 566 | } |
1da177e4 | 567 | |
05eff845 | 568 | if (pipeb_stats & 0x8000ffff) { |
7662c8bd SL |
569 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
570 | DRM_DEBUG("pipe b underrun\n"); | |
cdfbc41f | 571 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 572 | irq_received = 1; |
cdfbc41f | 573 | } |
05eff845 KP |
574 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
575 | ||
576 | if (!irq_received) | |
577 | break; | |
578 | ||
579 | ret = IRQ_HANDLED; | |
8ee1c3db | 580 | |
5ca58282 JB |
581 | /* Consume port. Then clear IIR or we'll miss events */ |
582 | if ((I915_HAS_HOTPLUG(dev)) && | |
583 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
584 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
585 | ||
586 | DRM_DEBUG("hotplug event received, stat 0x%08x\n", | |
587 | hotplug_status); | |
588 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
589 | queue_work(dev_priv->wq, |
590 | &dev_priv->hotplug_work); | |
5ca58282 JB |
591 | |
592 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
593 | I915_READ(PORT_HOTPLUG_STAT); | |
04302965 SL |
594 | |
595 | /* EOS interrupts occurs */ | |
596 | if (IS_IGD(dev) && | |
597 | (hotplug_status & CRT_EOS_INT_STATUS)) { | |
598 | u32 temp; | |
599 | ||
600 | DRM_DEBUG("EOS interrupt occurs\n"); | |
601 | /* status is already cleared */ | |
602 | temp = I915_READ(ADPA); | |
603 | temp &= ~ADPA_DAC_ENABLE; | |
604 | I915_WRITE(ADPA, temp); | |
605 | ||
606 | temp = I915_READ(PORT_HOTPLUG_EN); | |
607 | temp &= ~CRT_EOS_INT_EN; | |
608 | I915_WRITE(PORT_HOTPLUG_EN, temp); | |
609 | ||
610 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
611 | if (temp & CRT_EOS_INT_STATUS) | |
612 | I915_WRITE(PORT_HOTPLUG_STAT, | |
613 | CRT_EOS_INT_STATUS); | |
614 | } | |
5ca58282 JB |
615 | } |
616 | ||
cdfbc41f EA |
617 | I915_WRITE(IIR, iir); |
618 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 619 | |
7c1c2871 DA |
620 | if (dev->primary->master) { |
621 | master_priv = dev->primary->master->driver_priv; | |
622 | if (master_priv->sarea_priv) | |
623 | master_priv->sarea_priv->last_dispatch = | |
624 | READ_BREADCRUMB(dev_priv); | |
625 | } | |
0a3e67a4 | 626 | |
cdfbc41f | 627 | if (iir & I915_USER_INTERRUPT) { |
1c5d22f7 CW |
628 | u32 seqno = i915_get_gem_seqno(dev); |
629 | dev_priv->mm.irq_gem_seqno = seqno; | |
630 | trace_i915_gem_request_complete(dev, seqno); | |
cdfbc41f | 631 | DRM_WAKEUP(&dev_priv->irq_queue); |
f65d9421 BG |
632 | dev_priv->hangcheck_count = 0; |
633 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
cdfbc41f | 634 | } |
673a394b | 635 | |
05eff845 | 636 | if (pipea_stats & vblank_status) { |
cdfbc41f EA |
637 | vblank++; |
638 | drm_handle_vblank(dev, 0); | |
639 | } | |
7c463586 | 640 | |
05eff845 | 641 | if (pipeb_stats & vblank_status) { |
cdfbc41f EA |
642 | vblank++; |
643 | drm_handle_vblank(dev, 1); | |
644 | } | |
7c463586 | 645 | |
cdfbc41f EA |
646 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || |
647 | (iir & I915_ASLE_INTERRUPT)) | |
648 | opregion_asle_intr(dev); | |
649 | ||
650 | /* With MSI, interrupts are only generated when iir | |
651 | * transitions from zero to nonzero. If another bit got | |
652 | * set while we were handling the existing iir bits, then | |
653 | * we would never get another interrupt. | |
654 | * | |
655 | * This is fine on non-MSI as well, as if we hit this path | |
656 | * we avoid exiting the interrupt handler only to generate | |
657 | * another one. | |
658 | * | |
659 | * Note that for MSI this could cause a stray interrupt report | |
660 | * if an interrupt landed in the time between writing IIR and | |
661 | * the posting read. This should be rare enough to never | |
662 | * trigger the 99% of 100,000 interrupts test for disabling | |
663 | * stray interrupts. | |
664 | */ | |
665 | iir = new_iir; | |
05eff845 | 666 | } |
0a3e67a4 | 667 | |
05eff845 | 668 | return ret; |
1da177e4 LT |
669 | } |
670 | ||
af6061af | 671 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
672 | { |
673 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 674 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
675 | RING_LOCALS; |
676 | ||
677 | i915_kernel_lost_context(dev); | |
678 | ||
3e684eae | 679 | DRM_DEBUG("\n"); |
1da177e4 | 680 | |
c99b058f | 681 | dev_priv->counter++; |
c29b669c | 682 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 683 | dev_priv->counter = 1; |
7c1c2871 DA |
684 | if (master_priv->sarea_priv) |
685 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 686 | |
0baf823a | 687 | BEGIN_LP_RING(4); |
585fb111 | 688 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 689 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
c29b669c | 690 | OUT_RING(dev_priv->counter); |
585fb111 | 691 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 692 | ADVANCE_LP_RING(); |
bc5f4523 | 693 | |
c29b669c | 694 | return dev_priv->counter; |
1da177e4 LT |
695 | } |
696 | ||
673a394b | 697 | void i915_user_irq_get(struct drm_device *dev) |
ed4cb414 EA |
698 | { |
699 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 700 | unsigned long irqflags; |
ed4cb414 | 701 | |
e9d21d7f | 702 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
036a4a7d ZW |
703 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { |
704 | if (IS_IGDNG(dev)) | |
705 | igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); | |
706 | else | |
707 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
708 | } | |
e9d21d7f | 709 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
710 | } |
711 | ||
0a3e67a4 | 712 | void i915_user_irq_put(struct drm_device *dev) |
ed4cb414 EA |
713 | { |
714 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 715 | unsigned long irqflags; |
ed4cb414 | 716 | |
e9d21d7f | 717 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 | 718 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
036a4a7d ZW |
719 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { |
720 | if (IS_IGDNG(dev)) | |
721 | igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); | |
722 | else | |
723 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
724 | } | |
e9d21d7f | 725 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
726 | } |
727 | ||
9d34e5db CW |
728 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
729 | { | |
730 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
731 | ||
732 | if (dev_priv->trace_irq_seqno == 0) | |
733 | i915_user_irq_get(dev); | |
734 | ||
735 | dev_priv->trace_irq_seqno = seqno; | |
736 | } | |
737 | ||
84b1fd10 | 738 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
739 | { |
740 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 741 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
742 | int ret = 0; |
743 | ||
3e684eae | 744 | DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
745 | READ_BREADCRUMB(dev_priv)); |
746 | ||
ed4cb414 | 747 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
748 | if (master_priv->sarea_priv) |
749 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 750 | return 0; |
ed4cb414 | 751 | } |
1da177e4 | 752 | |
7c1c2871 DA |
753 | if (master_priv->sarea_priv) |
754 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 755 | |
ed4cb414 | 756 | i915_user_irq_get(dev); |
1da177e4 LT |
757 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
758 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
ed4cb414 | 759 | i915_user_irq_put(dev); |
1da177e4 | 760 | |
20caafa6 | 761 | if (ret == -EBUSY) { |
3e684eae | 762 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
763 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
764 | } | |
765 | ||
af6061af DA |
766 | return ret; |
767 | } | |
768 | ||
1da177e4 LT |
769 | /* Needs the lock as it touches the ring. |
770 | */ | |
c153f45f EA |
771 | int i915_irq_emit(struct drm_device *dev, void *data, |
772 | struct drm_file *file_priv) | |
1da177e4 | 773 | { |
1da177e4 | 774 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 775 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
776 | int result; |
777 | ||
07f4f8bf | 778 | if (!dev_priv || !dev_priv->ring.virtual_start) { |
3e684eae | 779 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 780 | return -EINVAL; |
1da177e4 | 781 | } |
299eb93c EA |
782 | |
783 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
784 | ||
546b0974 | 785 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 786 | result = i915_emit_irq(dev); |
546b0974 | 787 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 788 | |
c153f45f | 789 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 790 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 791 | return -EFAULT; |
1da177e4 LT |
792 | } |
793 | ||
794 | return 0; | |
795 | } | |
796 | ||
797 | /* Doesn't need the hardware lock. | |
798 | */ | |
c153f45f EA |
799 | int i915_irq_wait(struct drm_device *dev, void *data, |
800 | struct drm_file *file_priv) | |
1da177e4 | 801 | { |
1da177e4 | 802 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 803 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
804 | |
805 | if (!dev_priv) { | |
3e684eae | 806 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 807 | return -EINVAL; |
1da177e4 LT |
808 | } |
809 | ||
c153f45f | 810 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
811 | } |
812 | ||
42f52ef8 KP |
813 | /* Called from drm generic code, passed 'crtc' which |
814 | * we use as a pipe index | |
815 | */ | |
816 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
817 | { |
818 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 819 | unsigned long irqflags; |
71e0ffa5 JB |
820 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
821 | u32 pipeconf; | |
822 | ||
823 | pipeconf = I915_READ(pipeconf_reg); | |
824 | if (!(pipeconf & PIPEACONF_ENABLE)) | |
825 | return -EINVAL; | |
0a3e67a4 | 826 | |
036a4a7d ZW |
827 | if (IS_IGDNG(dev)) |
828 | return 0; | |
829 | ||
e9d21d7f | 830 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
e9d21d7f | 831 | if (IS_I965G(dev)) |
7c463586 KP |
832 | i915_enable_pipestat(dev_priv, pipe, |
833 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 834 | else |
7c463586 KP |
835 | i915_enable_pipestat(dev_priv, pipe, |
836 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 837 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
838 | return 0; |
839 | } | |
840 | ||
42f52ef8 KP |
841 | /* Called from drm generic code, passed 'crtc' which |
842 | * we use as a pipe index | |
843 | */ | |
844 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
845 | { |
846 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 847 | unsigned long irqflags; |
0a3e67a4 | 848 | |
036a4a7d ZW |
849 | if (IS_IGDNG(dev)) |
850 | return; | |
851 | ||
e9d21d7f | 852 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
7c463586 KP |
853 | i915_disable_pipestat(dev_priv, pipe, |
854 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
855 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 856 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
857 | } |
858 | ||
79e53945 JB |
859 | void i915_enable_interrupt (struct drm_device *dev) |
860 | { | |
861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e170b030 ZW |
862 | |
863 | if (!IS_IGDNG(dev)) | |
864 | opregion_enable_asle(dev); | |
79e53945 JB |
865 | dev_priv->irq_enabled = 1; |
866 | } | |
867 | ||
868 | ||
702880f2 DA |
869 | /* Set the vblank monitor pipe |
870 | */ | |
c153f45f EA |
871 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
872 | struct drm_file *file_priv) | |
702880f2 | 873 | { |
702880f2 | 874 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
875 | |
876 | if (!dev_priv) { | |
3e684eae | 877 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 878 | return -EINVAL; |
702880f2 DA |
879 | } |
880 | ||
5b51694a | 881 | return 0; |
702880f2 DA |
882 | } |
883 | ||
c153f45f EA |
884 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
885 | struct drm_file *file_priv) | |
702880f2 | 886 | { |
702880f2 | 887 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 888 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
889 | |
890 | if (!dev_priv) { | |
3e684eae | 891 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 892 | return -EINVAL; |
702880f2 DA |
893 | } |
894 | ||
0a3e67a4 | 895 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 896 | |
702880f2 DA |
897 | return 0; |
898 | } | |
899 | ||
a6b54f3f MCA |
900 | /** |
901 | * Schedule buffer swap at given vertical blank. | |
902 | */ | |
c153f45f EA |
903 | int i915_vblank_swap(struct drm_device *dev, void *data, |
904 | struct drm_file *file_priv) | |
a6b54f3f | 905 | { |
bd95e0a4 EA |
906 | /* The delayed swap mechanism was fundamentally racy, and has been |
907 | * removed. The model was that the client requested a delayed flip/swap | |
908 | * from the kernel, then waited for vblank before continuing to perform | |
909 | * rendering. The problem was that the kernel might wake the client | |
910 | * up before it dispatched the vblank swap (since the lock has to be | |
911 | * held while touching the ringbuffer), in which case the client would | |
912 | * clear and start the next frame before the swap occurred, and | |
913 | * flicker would occur in addition to likely missing the vblank. | |
914 | * | |
915 | * In the absence of this ioctl, userland falls back to a correct path | |
916 | * of waiting for a vblank, then dispatching the swap on its own. | |
917 | * Context switching to userland and back is plenty fast enough for | |
918 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 919 | */ |
bd95e0a4 | 920 | return -EINVAL; |
a6b54f3f MCA |
921 | } |
922 | ||
f65d9421 BG |
923 | struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) { |
924 | drm_i915_private_t *dev_priv = dev->dev_private; | |
925 | return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list); | |
926 | } | |
927 | ||
928 | /** | |
929 | * This is called when the chip hasn't reported back with completed | |
930 | * batchbuffers in a long time. The first time this is called we simply record | |
931 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
932 | * again, we assume the chip is wedged and try to fix it. | |
933 | */ | |
934 | void i915_hangcheck_elapsed(unsigned long data) | |
935 | { | |
936 | struct drm_device *dev = (struct drm_device *)data; | |
937 | drm_i915_private_t *dev_priv = dev->dev_private; | |
938 | uint32_t acthd; | |
939 | ||
940 | if (!IS_I965G(dev)) | |
941 | acthd = I915_READ(ACTHD); | |
942 | else | |
943 | acthd = I915_READ(ACTHD_I965); | |
944 | ||
945 | /* If all work is done then ACTHD clearly hasn't advanced. */ | |
946 | if (list_empty(&dev_priv->mm.request_list) || | |
947 | i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) { | |
948 | dev_priv->hangcheck_count = 0; | |
949 | return; | |
950 | } | |
951 | ||
952 | if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) { | |
953 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
ba1234d1 | 954 | i915_handle_error(dev, true); |
f65d9421 BG |
955 | return; |
956 | } | |
957 | ||
958 | /* Reset timer case chip hangs without another request being added */ | |
959 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
960 | ||
961 | if (acthd != dev_priv->last_acthd) | |
962 | dev_priv->hangcheck_count = 0; | |
963 | else | |
964 | dev_priv->hangcheck_count++; | |
965 | ||
966 | dev_priv->last_acthd = acthd; | |
967 | } | |
968 | ||
1da177e4 LT |
969 | /* drm_dma.h hooks |
970 | */ | |
036a4a7d ZW |
971 | static void igdng_irq_preinstall(struct drm_device *dev) |
972 | { | |
973 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
974 | ||
975 | I915_WRITE(HWSTAM, 0xeffe); | |
976 | ||
977 | /* XXX hotplug from PCH */ | |
978 | ||
979 | I915_WRITE(DEIMR, 0xffffffff); | |
980 | I915_WRITE(DEIER, 0x0); | |
981 | (void) I915_READ(DEIER); | |
982 | ||
983 | /* and GT */ | |
984 | I915_WRITE(GTIMR, 0xffffffff); | |
985 | I915_WRITE(GTIER, 0x0); | |
986 | (void) I915_READ(GTIER); | |
987 | } | |
988 | ||
989 | static int igdng_irq_postinstall(struct drm_device *dev) | |
990 | { | |
991 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
992 | /* enable kind of interrupts always enabled */ | |
993 | u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */; | |
994 | u32 render_mask = GT_USER_INTERRUPT; | |
995 | ||
996 | dev_priv->irq_mask_reg = ~display_mask; | |
997 | dev_priv->de_irq_enable_reg = display_mask; | |
998 | ||
999 | /* should always can generate irq */ | |
1000 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1001 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
1002 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); | |
1003 | (void) I915_READ(DEIER); | |
1004 | ||
1005 | /* user interrupt should be enabled, but masked initial */ | |
1006 | dev_priv->gt_irq_mask_reg = 0xffffffff; | |
1007 | dev_priv->gt_irq_enable_reg = render_mask; | |
1008 | ||
1009 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1010 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
1011 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); | |
1012 | (void) I915_READ(GTIER); | |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | ||
84b1fd10 | 1017 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1018 | { |
1019 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1020 | ||
79e53945 JB |
1021 | atomic_set(&dev_priv->irq_received, 0); |
1022 | ||
036a4a7d | 1023 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1024 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
036a4a7d ZW |
1025 | |
1026 | if (IS_IGDNG(dev)) { | |
1027 | igdng_irq_preinstall(dev); | |
1028 | return; | |
1029 | } | |
1030 | ||
5ca58282 JB |
1031 | if (I915_HAS_HOTPLUG(dev)) { |
1032 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1033 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1034 | } | |
1035 | ||
0a3e67a4 | 1036 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
1037 | I915_WRITE(PIPEASTAT, 0); |
1038 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1039 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1040 | I915_WRITE(IER, 0x0); |
7c463586 | 1041 | (void) I915_READ(IER); |
1da177e4 LT |
1042 | } |
1043 | ||
0a3e67a4 | 1044 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
1045 | { |
1046 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 1047 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 1048 | u32 error_mask; |
0a3e67a4 | 1049 | |
036a4a7d ZW |
1050 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
1051 | ||
0a3e67a4 | 1052 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 1053 | |
036a4a7d ZW |
1054 | if (IS_IGDNG(dev)) |
1055 | return igdng_irq_postinstall(dev); | |
1056 | ||
7c463586 KP |
1057 | /* Unmask the interrupts that we always want on. */ |
1058 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
1059 | ||
1060 | dev_priv->pipestat[0] = 0; | |
1061 | dev_priv->pipestat[1] = 0; | |
1062 | ||
5ca58282 JB |
1063 | if (I915_HAS_HOTPLUG(dev)) { |
1064 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
1065 | ||
1066 | /* Leave other bits alone */ | |
1067 | hotplug_en |= HOTPLUG_EN_MASK; | |
1068 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
1069 | ||
1070 | dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS | | |
1071 | TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS | | |
1072 | SDVOB_HOTPLUG_INT_STATUS; | |
1073 | if (IS_G4X(dev)) { | |
1074 | dev_priv->hotplug_supported_mask |= | |
1075 | HDMIB_HOTPLUG_INT_STATUS | | |
1076 | HDMIC_HOTPLUG_INT_STATUS | | |
1077 | HDMID_HOTPLUG_INT_STATUS; | |
1078 | } | |
1079 | /* Enable in IER... */ | |
1080 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
1081 | /* and unmask in IMR */ | |
1082 | i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT); | |
1083 | } | |
1084 | ||
63eeaf38 JB |
1085 | /* |
1086 | * Enable some error detection, note the instruction error mask | |
1087 | * bit is reserved, so we leave it masked. | |
1088 | */ | |
1089 | if (IS_G4X(dev)) { | |
1090 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
1091 | GM45_ERROR_MEM_PRIV | | |
1092 | GM45_ERROR_CP_PRIV | | |
1093 | I915_ERROR_MEMORY_REFRESH); | |
1094 | } else { | |
1095 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
1096 | I915_ERROR_MEMORY_REFRESH); | |
1097 | } | |
1098 | I915_WRITE(EMR, error_mask); | |
1099 | ||
7c463586 KP |
1100 | /* Disable pipe interrupt enables, clear pending pipe status */ |
1101 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); | |
1102 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1103 | /* Clear pending interrupt status */ | |
1104 | I915_WRITE(IIR, I915_READ(IIR)); | |
8ee1c3db | 1105 | |
5ca58282 | 1106 | I915_WRITE(IER, enable_mask); |
7c463586 | 1107 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
ed4cb414 EA |
1108 | (void) I915_READ(IER); |
1109 | ||
8ee1c3db | 1110 | opregion_enable_asle(dev); |
0a3e67a4 JB |
1111 | |
1112 | return 0; | |
1da177e4 LT |
1113 | } |
1114 | ||
036a4a7d ZW |
1115 | static void igdng_irq_uninstall(struct drm_device *dev) |
1116 | { | |
1117 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1118 | I915_WRITE(HWSTAM, 0xffffffff); | |
1119 | ||
1120 | I915_WRITE(DEIMR, 0xffffffff); | |
1121 | I915_WRITE(DEIER, 0x0); | |
1122 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1123 | ||
1124 | I915_WRITE(GTIMR, 0xffffffff); | |
1125 | I915_WRITE(GTIER, 0x0); | |
1126 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1127 | } | |
1128 | ||
84b1fd10 | 1129 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
1130 | { |
1131 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 1132 | |
1da177e4 LT |
1133 | if (!dev_priv) |
1134 | return; | |
1135 | ||
0a3e67a4 JB |
1136 | dev_priv->vblank_pipe = 0; |
1137 | ||
036a4a7d ZW |
1138 | if (IS_IGDNG(dev)) { |
1139 | igdng_irq_uninstall(dev); | |
1140 | return; | |
1141 | } | |
1142 | ||
5ca58282 JB |
1143 | if (I915_HAS_HOTPLUG(dev)) { |
1144 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1145 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1146 | } | |
1147 | ||
0a3e67a4 | 1148 | I915_WRITE(HWSTAM, 0xffffffff); |
7c463586 KP |
1149 | I915_WRITE(PIPEASTAT, 0); |
1150 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1151 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1152 | I915_WRITE(IER, 0x0); |
af6061af | 1153 | |
7c463586 KP |
1154 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
1155 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1156 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 1157 | } |