Commit | Line | Data |
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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
1da177e4 LT |
33 | #include "drmP.h" |
34 | #include "drm.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
1da177e4 | 40 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 41 | |
7c463586 KP |
42 | /** |
43 | * Interrupts that are always left unmasked. | |
44 | * | |
45 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
46 | * we leave them always unmasked in IMR and then control enabling them through | |
47 | * PIPESTAT alone. | |
48 | */ | |
6b95a207 KH |
49 | #define I915_INTERRUPT_ENABLE_FIX \ |
50 | (I915_ASLE_INTERRUPT | \ | |
51 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
52 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
53 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | |
54 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | |
55 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
56 | |
57 | /** Interrupts that we mask and unmask at runtime. */ | |
d1b851fc | 58 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
7c463586 | 59 | |
79e53945 JB |
60 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
61 | PIPE_VBLANK_INTERRUPT_STATUS) | |
62 | ||
63 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
64 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
65 | ||
66 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
67 | DRM_I915_VBLANK_PIPE_B) | |
68 | ||
036a4a7d | 69 | /* For display hotplug interrupt */ |
995b6762 | 70 | static void |
f2b115e6 | 71 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 72 | { |
1ec14ad3 CW |
73 | if ((dev_priv->irq_mask & mask) != 0) { |
74 | dev_priv->irq_mask &= ~mask; | |
75 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 76 | POSTING_READ(DEIMR); |
036a4a7d ZW |
77 | } |
78 | } | |
79 | ||
80 | static inline void | |
f2b115e6 | 81 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 82 | { |
1ec14ad3 CW |
83 | if ((dev_priv->irq_mask & mask) != mask) { |
84 | dev_priv->irq_mask |= mask; | |
85 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 86 | POSTING_READ(DEIMR); |
036a4a7d ZW |
87 | } |
88 | } | |
89 | ||
7c463586 KP |
90 | void |
91 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
92 | { | |
93 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
9db4a9c7 | 94 | u32 reg = PIPESTAT(pipe); |
7c463586 KP |
95 | |
96 | dev_priv->pipestat[pipe] |= mask; | |
97 | /* Enable the interrupt, clear any pending status */ | |
98 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
3143a2bf | 99 | POSTING_READ(reg); |
7c463586 KP |
100 | } |
101 | } | |
102 | ||
103 | void | |
104 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
105 | { | |
106 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
9db4a9c7 | 107 | u32 reg = PIPESTAT(pipe); |
7c463586 KP |
108 | |
109 | dev_priv->pipestat[pipe] &= ~mask; | |
110 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
3143a2bf | 111 | POSTING_READ(reg); |
7c463586 KP |
112 | } |
113 | } | |
114 | ||
01c66889 ZY |
115 | /** |
116 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
117 | */ | |
1ec14ad3 | 118 | void intel_enable_asle(struct drm_device *dev) |
01c66889 | 119 | { |
1ec14ad3 CW |
120 | drm_i915_private_t *dev_priv = dev->dev_private; |
121 | unsigned long irqflags; | |
122 | ||
7e231dbe JB |
123 | /* FIXME: opregion/asle for VLV */ |
124 | if (IS_VALLEYVIEW(dev)) | |
125 | return; | |
126 | ||
1ec14ad3 | 127 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 128 | |
c619eed4 | 129 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 130 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 131 | else { |
01c66889 | 132 | i915_enable_pipestat(dev_priv, 1, |
d874bcff | 133 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
a6c45cf0 | 134 | if (INTEL_INFO(dev)->gen >= 4) |
edcb49ca | 135 | i915_enable_pipestat(dev_priv, 0, |
d874bcff | 136 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca | 137 | } |
1ec14ad3 CW |
138 | |
139 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
140 | } |
141 | ||
0a3e67a4 JB |
142 | /** |
143 | * i915_pipe_enabled - check if a pipe is enabled | |
144 | * @dev: DRM device | |
145 | * @pipe: pipe to check | |
146 | * | |
147 | * Reading certain registers when the pipe is disabled can hang the chip. | |
148 | * Use this routine to make sure the PLL is running and the pipe is active | |
149 | * before reading such registers if unsure. | |
150 | */ | |
151 | static int | |
152 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
153 | { | |
154 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5eddb70b | 155 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
0a3e67a4 JB |
156 | } |
157 | ||
42f52ef8 KP |
158 | /* Called from drm generic code, passed a 'crtc', which |
159 | * we use as a pipe index | |
160 | */ | |
f71d4af4 | 161 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
162 | { |
163 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
164 | unsigned long high_frame; | |
165 | unsigned long low_frame; | |
5eddb70b | 166 | u32 high1, high2, low; |
0a3e67a4 JB |
167 | |
168 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 169 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 170 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
171 | return 0; |
172 | } | |
173 | ||
9db4a9c7 JB |
174 | high_frame = PIPEFRAME(pipe); |
175 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 176 | |
0a3e67a4 JB |
177 | /* |
178 | * High & low register fields aren't synchronized, so make sure | |
179 | * we get a low value that's stable across two reads of the high | |
180 | * register. | |
181 | */ | |
182 | do { | |
5eddb70b CW |
183 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
184 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; | |
185 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
186 | } while (high1 != high2); |
187 | ||
5eddb70b CW |
188 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
189 | low >>= PIPE_FRAME_LOW_SHIFT; | |
190 | return (high1 << 8) | low; | |
0a3e67a4 JB |
191 | } |
192 | ||
f71d4af4 | 193 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 JB |
194 | { |
195 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 196 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
197 | |
198 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 199 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 200 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
201 | return 0; |
202 | } | |
203 | ||
204 | return I915_READ(reg); | |
205 | } | |
206 | ||
f71d4af4 | 207 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
0af7e4df MK |
208 | int *vpos, int *hpos) |
209 | { | |
210 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
211 | u32 vbl = 0, position = 0; | |
212 | int vbl_start, vbl_end, htotal, vtotal; | |
213 | bool in_vbl = true; | |
214 | int ret = 0; | |
215 | ||
216 | if (!i915_pipe_enabled(dev, pipe)) { | |
217 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " | |
9db4a9c7 | 218 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
219 | return 0; |
220 | } | |
221 | ||
222 | /* Get vtotal. */ | |
223 | vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); | |
224 | ||
225 | if (INTEL_INFO(dev)->gen >= 4) { | |
226 | /* No obvious pixelcount register. Only query vertical | |
227 | * scanout position from Display scan line register. | |
228 | */ | |
229 | position = I915_READ(PIPEDSL(pipe)); | |
230 | ||
231 | /* Decode into vertical scanout position. Don't have | |
232 | * horizontal scanout position. | |
233 | */ | |
234 | *vpos = position & 0x1fff; | |
235 | *hpos = 0; | |
236 | } else { | |
237 | /* Have access to pixelcount since start of frame. | |
238 | * We can split this into vertical and horizontal | |
239 | * scanout position. | |
240 | */ | |
241 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; | |
242 | ||
243 | htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); | |
244 | *vpos = position / htotal; | |
245 | *hpos = position - (*vpos * htotal); | |
246 | } | |
247 | ||
248 | /* Query vblank area. */ | |
249 | vbl = I915_READ(VBLANK(pipe)); | |
250 | ||
251 | /* Test position against vblank region. */ | |
252 | vbl_start = vbl & 0x1fff; | |
253 | vbl_end = (vbl >> 16) & 0x1fff; | |
254 | ||
255 | if ((*vpos < vbl_start) || (*vpos > vbl_end)) | |
256 | in_vbl = false; | |
257 | ||
258 | /* Inside "upper part" of vblank area? Apply corrective offset: */ | |
259 | if (in_vbl && (*vpos >= vbl_start)) | |
260 | *vpos = *vpos - vtotal; | |
261 | ||
262 | /* Readouts valid? */ | |
263 | if (vbl > 0) | |
264 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; | |
265 | ||
266 | /* In vblank? */ | |
267 | if (in_vbl) | |
268 | ret |= DRM_SCANOUTPOS_INVBL; | |
269 | ||
270 | return ret; | |
271 | } | |
272 | ||
f71d4af4 | 273 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
274 | int *max_error, |
275 | struct timeval *vblank_time, | |
276 | unsigned flags) | |
277 | { | |
4041b853 CW |
278 | struct drm_i915_private *dev_priv = dev->dev_private; |
279 | struct drm_crtc *crtc; | |
0af7e4df | 280 | |
4041b853 CW |
281 | if (pipe < 0 || pipe >= dev_priv->num_pipe) { |
282 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
0af7e4df MK |
283 | return -EINVAL; |
284 | } | |
285 | ||
286 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
287 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
288 | if (crtc == NULL) { | |
289 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
290 | return -EINVAL; | |
291 | } | |
292 | ||
293 | if (!crtc->enabled) { | |
294 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
295 | return -EBUSY; | |
296 | } | |
0af7e4df MK |
297 | |
298 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
299 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
300 | vblank_time, flags, | |
301 | crtc); | |
0af7e4df MK |
302 | } |
303 | ||
5ca58282 JB |
304 | /* |
305 | * Handle hotplug events outside the interrupt handler proper. | |
306 | */ | |
307 | static void i915_hotplug_work_func(struct work_struct *work) | |
308 | { | |
309 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
310 | hotplug_work); | |
311 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 312 | struct drm_mode_config *mode_config = &dev->mode_config; |
4ef69c7a CW |
313 | struct intel_encoder *encoder; |
314 | ||
a65e34c7 | 315 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
316 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
317 | ||
4ef69c7a CW |
318 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) |
319 | if (encoder->hot_plug) | |
320 | encoder->hot_plug(encoder); | |
321 | ||
40ee3381 KP |
322 | mutex_unlock(&mode_config->mutex); |
323 | ||
5ca58282 | 324 | /* Just fire off a uevent and let userspace tell us what to do */ |
eb1f8e4f | 325 | drm_helper_hpd_irq_event(dev); |
5ca58282 JB |
326 | } |
327 | ||
f97108d1 JB |
328 | static void i915_handle_rps_change(struct drm_device *dev) |
329 | { | |
330 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 331 | u32 busy_up, busy_down, max_avg, min_avg; |
f97108d1 JB |
332 | u8 new_delay = dev_priv->cur_delay; |
333 | ||
7648fa99 | 334 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
335 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
336 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
337 | max_avg = I915_READ(RCBMAXAVG); |
338 | min_avg = I915_READ(RCBMINAVG); | |
339 | ||
340 | /* Handle RCS change request from hw */ | |
b5b72e89 | 341 | if (busy_up > max_avg) { |
f97108d1 JB |
342 | if (dev_priv->cur_delay != dev_priv->max_delay) |
343 | new_delay = dev_priv->cur_delay - 1; | |
344 | if (new_delay < dev_priv->max_delay) | |
345 | new_delay = dev_priv->max_delay; | |
b5b72e89 | 346 | } else if (busy_down < min_avg) { |
f97108d1 JB |
347 | if (dev_priv->cur_delay != dev_priv->min_delay) |
348 | new_delay = dev_priv->cur_delay + 1; | |
349 | if (new_delay > dev_priv->min_delay) | |
350 | new_delay = dev_priv->min_delay; | |
351 | } | |
352 | ||
7648fa99 JB |
353 | if (ironlake_set_drps(dev, new_delay)) |
354 | dev_priv->cur_delay = new_delay; | |
f97108d1 JB |
355 | |
356 | return; | |
357 | } | |
358 | ||
549f7365 CW |
359 | static void notify_ring(struct drm_device *dev, |
360 | struct intel_ring_buffer *ring) | |
361 | { | |
362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
475553de | 363 | u32 seqno; |
9862e600 | 364 | |
475553de CW |
365 | if (ring->obj == NULL) |
366 | return; | |
367 | ||
368 | seqno = ring->get_seqno(ring); | |
db53a302 | 369 | trace_i915_gem_request_complete(ring, seqno); |
9862e600 CW |
370 | |
371 | ring->irq_seqno = seqno; | |
549f7365 | 372 | wake_up_all(&ring->irq_queue); |
3e0dc6b0 BW |
373 | if (i915_enable_hangcheck) { |
374 | dev_priv->hangcheck_count = 0; | |
375 | mod_timer(&dev_priv->hangcheck_timer, | |
376 | jiffies + | |
377 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
378 | } | |
549f7365 CW |
379 | } |
380 | ||
4912d041 | 381 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 382 | { |
4912d041 BW |
383 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
384 | rps_work); | |
3b8d8d91 | 385 | u8 new_delay = dev_priv->cur_delay; |
4912d041 BW |
386 | u32 pm_iir, pm_imr; |
387 | ||
388 | spin_lock_irq(&dev_priv->rps_lock); | |
389 | pm_iir = dev_priv->pm_iir; | |
390 | dev_priv->pm_iir = 0; | |
391 | pm_imr = I915_READ(GEN6_PMIMR); | |
a9e2641d | 392 | I915_WRITE(GEN6_PMIMR, 0); |
4912d041 | 393 | spin_unlock_irq(&dev_priv->rps_lock); |
3b8d8d91 | 394 | |
3b8d8d91 JB |
395 | if (!pm_iir) |
396 | return; | |
397 | ||
4912d041 | 398 | mutex_lock(&dev_priv->dev->struct_mutex); |
3b8d8d91 JB |
399 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
400 | if (dev_priv->cur_delay != dev_priv->max_delay) | |
401 | new_delay = dev_priv->cur_delay + 1; | |
402 | if (new_delay > dev_priv->max_delay) | |
403 | new_delay = dev_priv->max_delay; | |
404 | } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) { | |
4912d041 | 405 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 JB |
406 | if (dev_priv->cur_delay != dev_priv->min_delay) |
407 | new_delay = dev_priv->cur_delay - 1; | |
408 | if (new_delay < dev_priv->min_delay) { | |
409 | new_delay = dev_priv->min_delay; | |
410 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
411 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) | | |
412 | ((new_delay << 16) & 0x3f0000)); | |
413 | } else { | |
414 | /* Make sure we continue to get down interrupts | |
415 | * until we hit the minimum frequency */ | |
416 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
417 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000); | |
418 | } | |
4912d041 | 419 | gen6_gt_force_wake_put(dev_priv); |
3b8d8d91 JB |
420 | } |
421 | ||
4912d041 | 422 | gen6_set_rps(dev_priv->dev, new_delay); |
3b8d8d91 JB |
423 | dev_priv->cur_delay = new_delay; |
424 | ||
4912d041 BW |
425 | /* |
426 | * rps_lock not held here because clearing is non-destructive. There is | |
427 | * an *extremely* unlikely race with gen6_rps_enable() that is prevented | |
428 | * by holding struct_mutex for the duration of the write. | |
429 | */ | |
4912d041 | 430 | mutex_unlock(&dev_priv->dev->struct_mutex); |
3b8d8d91 JB |
431 | } |
432 | ||
e7b4c6b1 DV |
433 | static void snb_gt_irq_handler(struct drm_device *dev, |
434 | struct drm_i915_private *dev_priv, | |
435 | u32 gt_iir) | |
436 | { | |
437 | ||
438 | if (gt_iir & (GEN6_RENDER_USER_INTERRUPT | | |
439 | GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT)) | |
440 | notify_ring(dev, &dev_priv->ring[RCS]); | |
441 | if (gt_iir & GEN6_BSD_USER_INTERRUPT) | |
442 | notify_ring(dev, &dev_priv->ring[VCS]); | |
443 | if (gt_iir & GEN6_BLITTER_USER_INTERRUPT) | |
444 | notify_ring(dev, &dev_priv->ring[BCS]); | |
445 | ||
446 | if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT | | |
447 | GT_GEN6_BSD_CS_ERROR_INTERRUPT | | |
448 | GT_RENDER_CS_ERROR_INTERRUPT)) { | |
449 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); | |
450 | i915_handle_error(dev, false); | |
451 | } | |
452 | } | |
453 | ||
7e231dbe JB |
454 | static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS) |
455 | { | |
456 | struct drm_device *dev = (struct drm_device *) arg; | |
457 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
458 | u32 iir, gt_iir, pm_iir; | |
459 | irqreturn_t ret = IRQ_NONE; | |
460 | unsigned long irqflags; | |
461 | int pipe; | |
462 | u32 pipe_stats[I915_MAX_PIPES]; | |
463 | u32 vblank_status; | |
464 | int vblank = 0; | |
465 | bool blc_event; | |
466 | ||
467 | atomic_inc(&dev_priv->irq_received); | |
468 | ||
469 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS | | |
470 | PIPE_VBLANK_INTERRUPT_STATUS; | |
471 | ||
472 | while (true) { | |
473 | iir = I915_READ(VLV_IIR); | |
474 | gt_iir = I915_READ(GTIIR); | |
475 | pm_iir = I915_READ(GEN6_PMIIR); | |
476 | ||
477 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
478 | goto out; | |
479 | ||
480 | ret = IRQ_HANDLED; | |
481 | ||
e7b4c6b1 | 482 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe JB |
483 | |
484 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
485 | for_each_pipe(pipe) { | |
486 | int reg = PIPESTAT(pipe); | |
487 | pipe_stats[pipe] = I915_READ(reg); | |
488 | ||
489 | /* | |
490 | * Clear the PIPE*STAT regs before the IIR | |
491 | */ | |
492 | if (pipe_stats[pipe] & 0x8000ffff) { | |
493 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
494 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
495 | pipe_name(pipe)); | |
496 | I915_WRITE(reg, pipe_stats[pipe]); | |
497 | } | |
498 | } | |
499 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
500 | ||
501 | /* Consume port. Then clear IIR or we'll miss events */ | |
502 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { | |
503 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
504 | ||
505 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
506 | hotplug_status); | |
507 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
508 | queue_work(dev_priv->wq, | |
509 | &dev_priv->hotplug_work); | |
510 | ||
511 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
512 | I915_READ(PORT_HOTPLUG_STAT); | |
513 | } | |
514 | ||
515 | ||
516 | if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) { | |
517 | drm_handle_vblank(dev, 0); | |
518 | vblank++; | |
519 | if (!dev_priv->flip_pending_is_done) { | |
520 | intel_finish_page_flip(dev, 0); | |
521 | } | |
522 | } | |
523 | ||
524 | if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) { | |
525 | drm_handle_vblank(dev, 1); | |
526 | vblank++; | |
527 | if (!dev_priv->flip_pending_is_done) { | |
528 | intel_finish_page_flip(dev, 0); | |
529 | } | |
530 | } | |
531 | ||
532 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
533 | blc_event = true; | |
534 | ||
535 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) { | |
536 | unsigned long flags; | |
537 | spin_lock_irqsave(&dev_priv->rps_lock, flags); | |
538 | WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); | |
539 | dev_priv->pm_iir |= pm_iir; | |
540 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); | |
541 | POSTING_READ(GEN6_PMIMR); | |
542 | spin_unlock_irqrestore(&dev_priv->rps_lock, flags); | |
543 | queue_work(dev_priv->wq, &dev_priv->rps_work); | |
544 | } | |
545 | ||
546 | I915_WRITE(GTIIR, gt_iir); | |
547 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
548 | I915_WRITE(VLV_IIR, iir); | |
549 | } | |
550 | ||
551 | out: | |
552 | return ret; | |
553 | } | |
554 | ||
776ad806 JB |
555 | static void pch_irq_handler(struct drm_device *dev) |
556 | { | |
557 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
558 | u32 pch_iir; | |
9db4a9c7 | 559 | int pipe; |
776ad806 JB |
560 | |
561 | pch_iir = I915_READ(SDEIIR); | |
562 | ||
563 | if (pch_iir & SDE_AUDIO_POWER_MASK) | |
564 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", | |
565 | (pch_iir & SDE_AUDIO_POWER_MASK) >> | |
566 | SDE_AUDIO_POWER_SHIFT); | |
567 | ||
568 | if (pch_iir & SDE_GMBUS) | |
569 | DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); | |
570 | ||
571 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
572 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
573 | ||
574 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
575 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
576 | ||
577 | if (pch_iir & SDE_POISON) | |
578 | DRM_ERROR("PCH poison interrupt\n"); | |
579 | ||
9db4a9c7 JB |
580 | if (pch_iir & SDE_FDI_MASK) |
581 | for_each_pipe(pipe) | |
582 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
583 | pipe_name(pipe), | |
584 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
585 | |
586 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
587 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
588 | ||
589 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
590 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
591 | ||
592 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
593 | DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); | |
594 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) | |
595 | DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); | |
596 | } | |
597 | ||
f71d4af4 | 598 | static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) |
b1f14ad0 JB |
599 | { |
600 | struct drm_device *dev = (struct drm_device *) arg; | |
601 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
602 | int ret = IRQ_NONE; | |
603 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; | |
604 | struct drm_i915_master_private *master_priv; | |
605 | ||
606 | atomic_inc(&dev_priv->irq_received); | |
607 | ||
608 | /* disable master interrupt before clearing iir */ | |
609 | de_ier = I915_READ(DEIER); | |
610 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
611 | POSTING_READ(DEIER); | |
612 | ||
613 | de_iir = I915_READ(DEIIR); | |
614 | gt_iir = I915_READ(GTIIR); | |
615 | pch_iir = I915_READ(SDEIIR); | |
616 | pm_iir = I915_READ(GEN6_PMIIR); | |
617 | ||
618 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0) | |
619 | goto done; | |
620 | ||
621 | ret = IRQ_HANDLED; | |
622 | ||
623 | if (dev->primary->master) { | |
624 | master_priv = dev->primary->master->driver_priv; | |
625 | if (master_priv->sarea_priv) | |
626 | master_priv->sarea_priv->last_dispatch = | |
627 | READ_BREADCRUMB(dev_priv); | |
628 | } | |
629 | ||
e7b4c6b1 | 630 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
b1f14ad0 JB |
631 | |
632 | if (de_iir & DE_GSE_IVB) | |
633 | intel_opregion_gse_intr(dev); | |
634 | ||
635 | if (de_iir & DE_PLANEA_FLIP_DONE_IVB) { | |
636 | intel_prepare_page_flip(dev, 0); | |
637 | intel_finish_page_flip_plane(dev, 0); | |
638 | } | |
639 | ||
640 | if (de_iir & DE_PLANEB_FLIP_DONE_IVB) { | |
641 | intel_prepare_page_flip(dev, 1); | |
642 | intel_finish_page_flip_plane(dev, 1); | |
643 | } | |
644 | ||
645 | if (de_iir & DE_PIPEA_VBLANK_IVB) | |
646 | drm_handle_vblank(dev, 0); | |
647 | ||
f6b07f45 | 648 | if (de_iir & DE_PIPEB_VBLANK_IVB) |
b1f14ad0 JB |
649 | drm_handle_vblank(dev, 1); |
650 | ||
651 | /* check event from PCH */ | |
652 | if (de_iir & DE_PCH_EVENT_IVB) { | |
653 | if (pch_iir & SDE_HOTPLUG_MASK_CPT) | |
654 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
655 | pch_irq_handler(dev); | |
656 | } | |
657 | ||
658 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) { | |
659 | unsigned long flags; | |
660 | spin_lock_irqsave(&dev_priv->rps_lock, flags); | |
661 | WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); | |
b1f14ad0 | 662 | dev_priv->pm_iir |= pm_iir; |
4fb066ab DV |
663 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); |
664 | POSTING_READ(GEN6_PMIMR); | |
b1f14ad0 JB |
665 | spin_unlock_irqrestore(&dev_priv->rps_lock, flags); |
666 | queue_work(dev_priv->wq, &dev_priv->rps_work); | |
667 | } | |
668 | ||
669 | /* should clear PCH hotplug event before clear CPU irq */ | |
670 | I915_WRITE(SDEIIR, pch_iir); | |
671 | I915_WRITE(GTIIR, gt_iir); | |
672 | I915_WRITE(DEIIR, de_iir); | |
673 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
674 | ||
675 | done: | |
676 | I915_WRITE(DEIER, de_ier); | |
677 | POSTING_READ(DEIER); | |
678 | ||
679 | return ret; | |
680 | } | |
681 | ||
e7b4c6b1 DV |
682 | static void ilk_gt_irq_handler(struct drm_device *dev, |
683 | struct drm_i915_private *dev_priv, | |
684 | u32 gt_iir) | |
685 | { | |
686 | if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) | |
687 | notify_ring(dev, &dev_priv->ring[RCS]); | |
688 | if (gt_iir & GT_BSD_USER_INTERRUPT) | |
689 | notify_ring(dev, &dev_priv->ring[VCS]); | |
690 | } | |
691 | ||
f71d4af4 | 692 | static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) |
036a4a7d | 693 | { |
4697995b | 694 | struct drm_device *dev = (struct drm_device *) arg; |
036a4a7d ZW |
695 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
696 | int ret = IRQ_NONE; | |
3b8d8d91 | 697 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; |
2d7b8366 | 698 | u32 hotplug_mask; |
036a4a7d | 699 | struct drm_i915_master_private *master_priv; |
881f47b6 | 700 | |
4697995b JB |
701 | atomic_inc(&dev_priv->irq_received); |
702 | ||
2d109a84 ZN |
703 | /* disable master interrupt before clearing iir */ |
704 | de_ier = I915_READ(DEIER); | |
705 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
3143a2bf | 706 | POSTING_READ(DEIER); |
2d109a84 | 707 | |
036a4a7d ZW |
708 | de_iir = I915_READ(DEIIR); |
709 | gt_iir = I915_READ(GTIIR); | |
c650156a | 710 | pch_iir = I915_READ(SDEIIR); |
3b8d8d91 | 711 | pm_iir = I915_READ(GEN6_PMIIR); |
036a4a7d | 712 | |
3b8d8d91 JB |
713 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && |
714 | (!IS_GEN6(dev) || pm_iir == 0)) | |
c7c85101 | 715 | goto done; |
036a4a7d | 716 | |
2d7b8366 YL |
717 | if (HAS_PCH_CPT(dev)) |
718 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; | |
719 | else | |
720 | hotplug_mask = SDE_HOTPLUG_MASK; | |
721 | ||
c7c85101 | 722 | ret = IRQ_HANDLED; |
036a4a7d | 723 | |
c7c85101 ZN |
724 | if (dev->primary->master) { |
725 | master_priv = dev->primary->master->driver_priv; | |
726 | if (master_priv->sarea_priv) | |
727 | master_priv->sarea_priv->last_dispatch = | |
728 | READ_BREADCRUMB(dev_priv); | |
729 | } | |
036a4a7d | 730 | |
e7b4c6b1 DV |
731 | if (IS_GEN5(dev)) |
732 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
733 | else | |
734 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
01c66889 | 735 | |
c7c85101 | 736 | if (de_iir & DE_GSE) |
3b617967 | 737 | intel_opregion_gse_intr(dev); |
c650156a | 738 | |
f072d2e7 | 739 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 740 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 741 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 742 | } |
013d5aa2 | 743 | |
f072d2e7 | 744 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 745 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 746 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 747 | } |
013d5aa2 | 748 | |
f072d2e7 | 749 | if (de_iir & DE_PIPEA_VBLANK) |
c062df61 LP |
750 | drm_handle_vblank(dev, 0); |
751 | ||
f072d2e7 | 752 | if (de_iir & DE_PIPEB_VBLANK) |
c062df61 LP |
753 | drm_handle_vblank(dev, 1); |
754 | ||
c7c85101 | 755 | /* check event from PCH */ |
776ad806 JB |
756 | if (de_iir & DE_PCH_EVENT) { |
757 | if (pch_iir & hotplug_mask) | |
758 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
759 | pch_irq_handler(dev); | |
760 | } | |
036a4a7d | 761 | |
f97108d1 | 762 | if (de_iir & DE_PCU_EVENT) { |
7648fa99 | 763 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
f97108d1 JB |
764 | i915_handle_rps_change(dev); |
765 | } | |
766 | ||
4912d041 BW |
767 | if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) { |
768 | /* | |
769 | * IIR bits should never already be set because IMR should | |
770 | * prevent an interrupt from being shown in IIR. The warning | |
771 | * displays a case where we've unsafely cleared | |
772 | * dev_priv->pm_iir. Although missing an interrupt of the same | |
773 | * type is not a problem, it displays a problem in the logic. | |
774 | * | |
775 | * The mask bit in IMR is cleared by rps_work. | |
776 | */ | |
777 | unsigned long flags; | |
778 | spin_lock_irqsave(&dev_priv->rps_lock, flags); | |
779 | WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); | |
4912d041 | 780 | dev_priv->pm_iir |= pm_iir; |
4fb066ab DV |
781 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); |
782 | POSTING_READ(GEN6_PMIMR); | |
4912d041 BW |
783 | spin_unlock_irqrestore(&dev_priv->rps_lock, flags); |
784 | queue_work(dev_priv->wq, &dev_priv->rps_work); | |
785 | } | |
3b8d8d91 | 786 | |
c7c85101 ZN |
787 | /* should clear PCH hotplug event before clear CPU irq */ |
788 | I915_WRITE(SDEIIR, pch_iir); | |
789 | I915_WRITE(GTIIR, gt_iir); | |
790 | I915_WRITE(DEIIR, de_iir); | |
4912d041 | 791 | I915_WRITE(GEN6_PMIIR, pm_iir); |
c7c85101 ZN |
792 | |
793 | done: | |
2d109a84 | 794 | I915_WRITE(DEIER, de_ier); |
3143a2bf | 795 | POSTING_READ(DEIER); |
2d109a84 | 796 | |
036a4a7d ZW |
797 | return ret; |
798 | } | |
799 | ||
8a905236 JB |
800 | /** |
801 | * i915_error_work_func - do process context error handling work | |
802 | * @work: work struct | |
803 | * | |
804 | * Fire an error uevent so userspace can see that a hang or error | |
805 | * was detected. | |
806 | */ | |
807 | static void i915_error_work_func(struct work_struct *work) | |
808 | { | |
809 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
810 | error_work); | |
811 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
812 | char *error_event[] = { "ERROR=1", NULL }; |
813 | char *reset_event[] = { "RESET=1", NULL }; | |
814 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 815 | |
f316a42c BG |
816 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
817 | ||
ba1234d1 | 818 | if (atomic_read(&dev_priv->mm.wedged)) { |
f803aa55 CW |
819 | DRM_DEBUG_DRIVER("resetting chip\n"); |
820 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | |
821 | if (!i915_reset(dev, GRDOM_RENDER)) { | |
822 | atomic_set(&dev_priv->mm.wedged, 0); | |
823 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); | |
f316a42c | 824 | } |
30dbf0c0 | 825 | complete_all(&dev_priv->error_completion); |
f316a42c | 826 | } |
8a905236 JB |
827 | } |
828 | ||
3bd3c932 | 829 | #ifdef CONFIG_DEBUG_FS |
9df30794 | 830 | static struct drm_i915_error_object * |
bcfb2e28 | 831 | i915_error_object_create(struct drm_i915_private *dev_priv, |
05394f39 | 832 | struct drm_i915_gem_object *src) |
9df30794 CW |
833 | { |
834 | struct drm_i915_error_object *dst; | |
9df30794 | 835 | int page, page_count; |
e56660dd | 836 | u32 reloc_offset; |
9df30794 | 837 | |
05394f39 | 838 | if (src == NULL || src->pages == NULL) |
9df30794 CW |
839 | return NULL; |
840 | ||
05394f39 | 841 | page_count = src->base.size / PAGE_SIZE; |
9df30794 | 842 | |
0206e353 | 843 | dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC); |
9df30794 CW |
844 | if (dst == NULL) |
845 | return NULL; | |
846 | ||
05394f39 | 847 | reloc_offset = src->gtt_offset; |
9df30794 | 848 | for (page = 0; page < page_count; page++) { |
788885ae | 849 | unsigned long flags; |
e56660dd | 850 | void *d; |
788885ae | 851 | |
e56660dd | 852 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
853 | if (d == NULL) |
854 | goto unwind; | |
e56660dd | 855 | |
788885ae | 856 | local_irq_save(flags); |
74898d7e DV |
857 | if (reloc_offset < dev_priv->mm.gtt_mappable_end && |
858 | src->has_global_gtt_mapping) { | |
172975aa CW |
859 | void __iomem *s; |
860 | ||
861 | /* Simply ignore tiling or any overlapping fence. | |
862 | * It's part of the error state, and this hopefully | |
863 | * captures what the GPU read. | |
864 | */ | |
865 | ||
866 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
867 | reloc_offset); | |
868 | memcpy_fromio(d, s, PAGE_SIZE); | |
869 | io_mapping_unmap_atomic(s); | |
870 | } else { | |
871 | void *s; | |
872 | ||
873 | drm_clflush_pages(&src->pages[page], 1); | |
874 | ||
875 | s = kmap_atomic(src->pages[page]); | |
876 | memcpy(d, s, PAGE_SIZE); | |
877 | kunmap_atomic(s); | |
878 | ||
879 | drm_clflush_pages(&src->pages[page], 1); | |
880 | } | |
788885ae | 881 | local_irq_restore(flags); |
e56660dd | 882 | |
9df30794 | 883 | dst->pages[page] = d; |
e56660dd CW |
884 | |
885 | reloc_offset += PAGE_SIZE; | |
9df30794 CW |
886 | } |
887 | dst->page_count = page_count; | |
05394f39 | 888 | dst->gtt_offset = src->gtt_offset; |
9df30794 CW |
889 | |
890 | return dst; | |
891 | ||
892 | unwind: | |
893 | while (page--) | |
894 | kfree(dst->pages[page]); | |
895 | kfree(dst); | |
896 | return NULL; | |
897 | } | |
898 | ||
899 | static void | |
900 | i915_error_object_free(struct drm_i915_error_object *obj) | |
901 | { | |
902 | int page; | |
903 | ||
904 | if (obj == NULL) | |
905 | return; | |
906 | ||
907 | for (page = 0; page < obj->page_count; page++) | |
908 | kfree(obj->pages[page]); | |
909 | ||
910 | kfree(obj); | |
911 | } | |
912 | ||
913 | static void | |
914 | i915_error_state_free(struct drm_device *dev, | |
915 | struct drm_i915_error_state *error) | |
916 | { | |
e2f973d5 CW |
917 | int i; |
918 | ||
52d39a21 CW |
919 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
920 | i915_error_object_free(error->ring[i].batchbuffer); | |
921 | i915_error_object_free(error->ring[i].ringbuffer); | |
922 | kfree(error->ring[i].requests); | |
923 | } | |
e2f973d5 | 924 | |
9df30794 | 925 | kfree(error->active_bo); |
6ef3d427 | 926 | kfree(error->overlay); |
9df30794 CW |
927 | kfree(error); |
928 | } | |
929 | ||
c724e8a9 CW |
930 | static u32 capture_bo_list(struct drm_i915_error_buffer *err, |
931 | int count, | |
932 | struct list_head *head) | |
933 | { | |
934 | struct drm_i915_gem_object *obj; | |
935 | int i = 0; | |
936 | ||
937 | list_for_each_entry(obj, head, mm_list) { | |
938 | err->size = obj->base.size; | |
939 | err->name = obj->base.name; | |
940 | err->seqno = obj->last_rendering_seqno; | |
941 | err->gtt_offset = obj->gtt_offset; | |
942 | err->read_domains = obj->base.read_domains; | |
943 | err->write_domain = obj->base.write_domain; | |
944 | err->fence_reg = obj->fence_reg; | |
945 | err->pinned = 0; | |
946 | if (obj->pin_count > 0) | |
947 | err->pinned = 1; | |
948 | if (obj->user_pin_count > 0) | |
949 | err->pinned = -1; | |
950 | err->tiling = obj->tiling_mode; | |
951 | err->dirty = obj->dirty; | |
952 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
96154f2f | 953 | err->ring = obj->ring ? obj->ring->id : -1; |
93dfb40c | 954 | err->cache_level = obj->cache_level; |
c724e8a9 CW |
955 | |
956 | if (++i == count) | |
957 | break; | |
958 | ||
959 | err++; | |
960 | } | |
961 | ||
962 | return i; | |
963 | } | |
964 | ||
748ebc60 CW |
965 | static void i915_gem_record_fences(struct drm_device *dev, |
966 | struct drm_i915_error_state *error) | |
967 | { | |
968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
969 | int i; | |
970 | ||
971 | /* Fences */ | |
972 | switch (INTEL_INFO(dev)->gen) { | |
775d17b6 | 973 | case 7: |
748ebc60 CW |
974 | case 6: |
975 | for (i = 0; i < 16; i++) | |
976 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); | |
977 | break; | |
978 | case 5: | |
979 | case 4: | |
980 | for (i = 0; i < 16; i++) | |
981 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
982 | break; | |
983 | case 3: | |
984 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
985 | for (i = 0; i < 8; i++) | |
986 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
987 | case 2: | |
988 | for (i = 0; i < 8; i++) | |
989 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
990 | break; | |
991 | ||
992 | } | |
993 | } | |
994 | ||
bcfb2e28 CW |
995 | static struct drm_i915_error_object * |
996 | i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, | |
997 | struct intel_ring_buffer *ring) | |
998 | { | |
999 | struct drm_i915_gem_object *obj; | |
1000 | u32 seqno; | |
1001 | ||
1002 | if (!ring->get_seqno) | |
1003 | return NULL; | |
1004 | ||
1005 | seqno = ring->get_seqno(ring); | |
1006 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { | |
1007 | if (obj->ring != ring) | |
1008 | continue; | |
1009 | ||
c37d9a5d | 1010 | if (i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
bcfb2e28 CW |
1011 | continue; |
1012 | ||
1013 | if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) | |
1014 | continue; | |
1015 | ||
1016 | /* We need to copy these to an anonymous buffer as the simplest | |
1017 | * method to avoid being overwritten by userspace. | |
1018 | */ | |
1019 | return i915_error_object_create(dev_priv, obj); | |
1020 | } | |
1021 | ||
1022 | return NULL; | |
1023 | } | |
1024 | ||
d27b1e0e DV |
1025 | static void i915_record_ring_state(struct drm_device *dev, |
1026 | struct drm_i915_error_state *error, | |
1027 | struct intel_ring_buffer *ring) | |
1028 | { | |
1029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1030 | ||
33f3f518 | 1031 | if (INTEL_INFO(dev)->gen >= 6) { |
33f3f518 | 1032 | error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); |
7e3b8737 DV |
1033 | error->semaphore_mboxes[ring->id][0] |
1034 | = I915_READ(RING_SYNC_0(ring->mmio_base)); | |
1035 | error->semaphore_mboxes[ring->id][1] | |
1036 | = I915_READ(RING_SYNC_1(ring->mmio_base)); | |
33f3f518 | 1037 | } |
c1cd90ed | 1038 | |
d27b1e0e | 1039 | if (INTEL_INFO(dev)->gen >= 4) { |
9d2f41fa | 1040 | error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); |
d27b1e0e DV |
1041 | error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); |
1042 | error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); | |
1043 | error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); | |
c1cd90ed | 1044 | error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); |
d27b1e0e | 1045 | if (ring->id == RCS) { |
d27b1e0e DV |
1046 | error->instdone1 = I915_READ(INSTDONE1); |
1047 | error->bbaddr = I915_READ64(BB_ADDR); | |
1048 | } | |
1049 | } else { | |
9d2f41fa | 1050 | error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX); |
d27b1e0e DV |
1051 | error->ipeir[ring->id] = I915_READ(IPEIR); |
1052 | error->ipehr[ring->id] = I915_READ(IPEHR); | |
1053 | error->instdone[ring->id] = I915_READ(INSTDONE); | |
d27b1e0e DV |
1054 | } |
1055 | ||
c1cd90ed | 1056 | error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); |
d27b1e0e DV |
1057 | error->seqno[ring->id] = ring->get_seqno(ring); |
1058 | error->acthd[ring->id] = intel_ring_get_active_head(ring); | |
c1cd90ed DV |
1059 | error->head[ring->id] = I915_READ_HEAD(ring); |
1060 | error->tail[ring->id] = I915_READ_TAIL(ring); | |
7e3b8737 DV |
1061 | |
1062 | error->cpu_ring_head[ring->id] = ring->head; | |
1063 | error->cpu_ring_tail[ring->id] = ring->tail; | |
d27b1e0e DV |
1064 | } |
1065 | ||
52d39a21 CW |
1066 | static void i915_gem_record_rings(struct drm_device *dev, |
1067 | struct drm_i915_error_state *error) | |
1068 | { | |
1069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070 | struct drm_i915_gem_request *request; | |
1071 | int i, count; | |
1072 | ||
1073 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1074 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1075 | ||
1076 | if (ring->obj == NULL) | |
1077 | continue; | |
1078 | ||
1079 | i915_record_ring_state(dev, error, ring); | |
1080 | ||
1081 | error->ring[i].batchbuffer = | |
1082 | i915_error_first_batchbuffer(dev_priv, ring); | |
1083 | ||
1084 | error->ring[i].ringbuffer = | |
1085 | i915_error_object_create(dev_priv, ring->obj); | |
1086 | ||
1087 | count = 0; | |
1088 | list_for_each_entry(request, &ring->request_list, list) | |
1089 | count++; | |
1090 | ||
1091 | error->ring[i].num_requests = count; | |
1092 | error->ring[i].requests = | |
1093 | kmalloc(count*sizeof(struct drm_i915_error_request), | |
1094 | GFP_ATOMIC); | |
1095 | if (error->ring[i].requests == NULL) { | |
1096 | error->ring[i].num_requests = 0; | |
1097 | continue; | |
1098 | } | |
1099 | ||
1100 | count = 0; | |
1101 | list_for_each_entry(request, &ring->request_list, list) { | |
1102 | struct drm_i915_error_request *erq; | |
1103 | ||
1104 | erq = &error->ring[i].requests[count++]; | |
1105 | erq->seqno = request->seqno; | |
1106 | erq->jiffies = request->emitted_jiffies; | |
ee4f42b1 | 1107 | erq->tail = request->tail; |
52d39a21 CW |
1108 | } |
1109 | } | |
1110 | } | |
1111 | ||
8a905236 JB |
1112 | /** |
1113 | * i915_capture_error_state - capture an error record for later analysis | |
1114 | * @dev: drm device | |
1115 | * | |
1116 | * Should be called when an error is detected (either a hang or an error | |
1117 | * interrupt) to capture error state from the time of the error. Fills | |
1118 | * out a structure which becomes available in debugfs for user level tools | |
1119 | * to pick up. | |
1120 | */ | |
63eeaf38 JB |
1121 | static void i915_capture_error_state(struct drm_device *dev) |
1122 | { | |
1123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1124 | struct drm_i915_gem_object *obj; |
63eeaf38 JB |
1125 | struct drm_i915_error_state *error; |
1126 | unsigned long flags; | |
9db4a9c7 | 1127 | int i, pipe; |
63eeaf38 JB |
1128 | |
1129 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
9df30794 CW |
1130 | error = dev_priv->first_error; |
1131 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
1132 | if (error) | |
1133 | return; | |
63eeaf38 | 1134 | |
9db4a9c7 | 1135 | /* Account for pipe specific data like PIPE*STAT */ |
33f3f518 | 1136 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
63eeaf38 | 1137 | if (!error) { |
9df30794 CW |
1138 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
1139 | return; | |
63eeaf38 JB |
1140 | } |
1141 | ||
b6f7833b CW |
1142 | DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", |
1143 | dev->primary->index); | |
2fa772f3 | 1144 | |
63eeaf38 JB |
1145 | error->eir = I915_READ(EIR); |
1146 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
9db4a9c7 JB |
1147 | for_each_pipe(pipe) |
1148 | error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); | |
d27b1e0e | 1149 | |
33f3f518 | 1150 | if (INTEL_INFO(dev)->gen >= 6) { |
f406839f | 1151 | error->error = I915_READ(ERROR_GEN6); |
33f3f518 DV |
1152 | error->done_reg = I915_READ(DONE_REG); |
1153 | } | |
d27b1e0e | 1154 | |
748ebc60 | 1155 | i915_gem_record_fences(dev, error); |
52d39a21 | 1156 | i915_gem_record_rings(dev, error); |
9df30794 | 1157 | |
c724e8a9 | 1158 | /* Record buffers on the active and pinned lists. */ |
9df30794 | 1159 | error->active_bo = NULL; |
c724e8a9 | 1160 | error->pinned_bo = NULL; |
9df30794 | 1161 | |
bcfb2e28 CW |
1162 | i = 0; |
1163 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) | |
1164 | i++; | |
1165 | error->active_bo_count = i; | |
05394f39 | 1166 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
bcfb2e28 CW |
1167 | i++; |
1168 | error->pinned_bo_count = i - error->active_bo_count; | |
c724e8a9 | 1169 | |
8e934dbf CW |
1170 | error->active_bo = NULL; |
1171 | error->pinned_bo = NULL; | |
bcfb2e28 CW |
1172 | if (i) { |
1173 | error->active_bo = kmalloc(sizeof(*error->active_bo)*i, | |
9df30794 | 1174 | GFP_ATOMIC); |
c724e8a9 CW |
1175 | if (error->active_bo) |
1176 | error->pinned_bo = | |
1177 | error->active_bo + error->active_bo_count; | |
9df30794 CW |
1178 | } |
1179 | ||
c724e8a9 CW |
1180 | if (error->active_bo) |
1181 | error->active_bo_count = | |
1182 | capture_bo_list(error->active_bo, | |
1183 | error->active_bo_count, | |
1184 | &dev_priv->mm.active_list); | |
1185 | ||
1186 | if (error->pinned_bo) | |
1187 | error->pinned_bo_count = | |
1188 | capture_bo_list(error->pinned_bo, | |
1189 | error->pinned_bo_count, | |
1190 | &dev_priv->mm.pinned_list); | |
1191 | ||
9df30794 CW |
1192 | do_gettimeofday(&error->time); |
1193 | ||
6ef3d427 | 1194 | error->overlay = intel_overlay_capture_error_state(dev); |
c4a1d9e4 | 1195 | error->display = intel_display_capture_error_state(dev); |
6ef3d427 | 1196 | |
9df30794 CW |
1197 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
1198 | if (dev_priv->first_error == NULL) { | |
1199 | dev_priv->first_error = error; | |
1200 | error = NULL; | |
1201 | } | |
63eeaf38 | 1202 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
1203 | |
1204 | if (error) | |
1205 | i915_error_state_free(dev, error); | |
1206 | } | |
1207 | ||
1208 | void i915_destroy_error_state(struct drm_device *dev) | |
1209 | { | |
1210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1211 | struct drm_i915_error_state *error; | |
6dc0e816 | 1212 | unsigned long flags; |
9df30794 | 1213 | |
6dc0e816 | 1214 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
9df30794 CW |
1215 | error = dev_priv->first_error; |
1216 | dev_priv->first_error = NULL; | |
6dc0e816 | 1217 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
1218 | |
1219 | if (error) | |
1220 | i915_error_state_free(dev, error); | |
63eeaf38 | 1221 | } |
3bd3c932 CW |
1222 | #else |
1223 | #define i915_capture_error_state(x) | |
1224 | #endif | |
63eeaf38 | 1225 | |
35aed2e6 | 1226 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
1227 | { |
1228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1229 | u32 eir = I915_READ(EIR); | |
9db4a9c7 | 1230 | int pipe; |
8a905236 | 1231 | |
35aed2e6 CW |
1232 | if (!eir) |
1233 | return; | |
8a905236 | 1234 | |
a70491cc | 1235 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 JB |
1236 | |
1237 | if (IS_G4X(dev)) { | |
1238 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
1239 | u32 ipeir = I915_READ(IPEIR_I965); | |
1240 | ||
a70491cc JP |
1241 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
1242 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
1243 | pr_err(" INSTDONE: 0x%08x\n", | |
8a905236 | 1244 | I915_READ(INSTDONE_I965)); |
a70491cc JP |
1245 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
1246 | pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1)); | |
1247 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); | |
8a905236 | 1248 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 1249 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1250 | } |
1251 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
1252 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
1253 | pr_err("page table error\n"); |
1254 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 1255 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 1256 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1257 | } |
1258 | } | |
1259 | ||
a6c45cf0 | 1260 | if (!IS_GEN2(dev)) { |
8a905236 JB |
1261 | if (eir & I915_ERROR_PAGE_TABLE) { |
1262 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
1263 | pr_err("page table error\n"); |
1264 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 1265 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 1266 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1267 | } |
1268 | } | |
1269 | ||
1270 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 1271 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 1272 | for_each_pipe(pipe) |
a70491cc | 1273 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 1274 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
1275 | /* pipestat has already been acked */ |
1276 | } | |
1277 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
1278 | pr_err("instruction error\n"); |
1279 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
a6c45cf0 | 1280 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
1281 | u32 ipeir = I915_READ(IPEIR); |
1282 | ||
a70491cc JP |
1283 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
1284 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
1285 | pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE)); | |
1286 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); | |
8a905236 | 1287 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 1288 | POSTING_READ(IPEIR); |
8a905236 JB |
1289 | } else { |
1290 | u32 ipeir = I915_READ(IPEIR_I965); | |
1291 | ||
a70491cc JP |
1292 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
1293 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
1294 | pr_err(" INSTDONE: 0x%08x\n", | |
8a905236 | 1295 | I915_READ(INSTDONE_I965)); |
a70491cc JP |
1296 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
1297 | pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1)); | |
1298 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); | |
8a905236 | 1299 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 1300 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1301 | } |
1302 | } | |
1303 | ||
1304 | I915_WRITE(EIR, eir); | |
3143a2bf | 1305 | POSTING_READ(EIR); |
8a905236 JB |
1306 | eir = I915_READ(EIR); |
1307 | if (eir) { | |
1308 | /* | |
1309 | * some errors might have become stuck, | |
1310 | * mask them. | |
1311 | */ | |
1312 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
1313 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
1314 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
1315 | } | |
35aed2e6 CW |
1316 | } |
1317 | ||
1318 | /** | |
1319 | * i915_handle_error - handle an error interrupt | |
1320 | * @dev: drm device | |
1321 | * | |
1322 | * Do some basic checking of regsiter state at error interrupt time and | |
1323 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
1324 | * sure we get a record and make it available in debugfs. Fire a uevent | |
1325 | * so userspace knows something bad happened (should trigger collection | |
1326 | * of a ring dump etc.). | |
1327 | */ | |
527f9e90 | 1328 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
1329 | { |
1330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1331 | ||
1332 | i915_capture_error_state(dev); | |
1333 | i915_report_and_clear_eir(dev); | |
8a905236 | 1334 | |
ba1234d1 | 1335 | if (wedged) { |
30dbf0c0 | 1336 | INIT_COMPLETION(dev_priv->error_completion); |
ba1234d1 BG |
1337 | atomic_set(&dev_priv->mm.wedged, 1); |
1338 | ||
11ed50ec BG |
1339 | /* |
1340 | * Wakeup waiting processes so they don't hang | |
1341 | */ | |
1ec14ad3 | 1342 | wake_up_all(&dev_priv->ring[RCS].irq_queue); |
f787a5f5 | 1343 | if (HAS_BSD(dev)) |
1ec14ad3 | 1344 | wake_up_all(&dev_priv->ring[VCS].irq_queue); |
549f7365 | 1345 | if (HAS_BLT(dev)) |
1ec14ad3 | 1346 | wake_up_all(&dev_priv->ring[BCS].irq_queue); |
11ed50ec BG |
1347 | } |
1348 | ||
9c9fe1f8 | 1349 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
1350 | } |
1351 | ||
4e5359cd SF |
1352 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
1353 | { | |
1354 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1355 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1356 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 1357 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
1358 | struct intel_unpin_work *work; |
1359 | unsigned long flags; | |
1360 | bool stall_detected; | |
1361 | ||
1362 | /* Ignore early vblank irqs */ | |
1363 | if (intel_crtc == NULL) | |
1364 | return; | |
1365 | ||
1366 | spin_lock_irqsave(&dev->event_lock, flags); | |
1367 | work = intel_crtc->unpin_work; | |
1368 | ||
1369 | if (work == NULL || work->pending || !work->enable_stall_check) { | |
1370 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ | |
1371 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1372 | return; | |
1373 | } | |
1374 | ||
1375 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 1376 | obj = work->pending_flip_obj; |
a6c45cf0 | 1377 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 1378 | int dspsurf = DSPSURF(intel_crtc->plane); |
05394f39 | 1379 | stall_detected = I915_READ(dspsurf) == obj->gtt_offset; |
4e5359cd | 1380 | } else { |
9db4a9c7 | 1381 | int dspaddr = DSPADDR(intel_crtc->plane); |
05394f39 | 1382 | stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |
01f2c773 | 1383 | crtc->y * crtc->fb->pitches[0] + |
4e5359cd SF |
1384 | crtc->x * crtc->fb->bits_per_pixel/8); |
1385 | } | |
1386 | ||
1387 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1388 | ||
1389 | if (stall_detected) { | |
1390 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
1391 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
1392 | } | |
1393 | } | |
1394 | ||
f71d4af4 | 1395 | static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
1da177e4 | 1396 | { |
84b1fd10 | 1397 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 1398 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 1399 | struct drm_i915_master_private *master_priv; |
cdfbc41f | 1400 | u32 iir, new_iir; |
9db4a9c7 | 1401 | u32 pipe_stats[I915_MAX_PIPES]; |
05eff845 | 1402 | u32 vblank_status; |
0a3e67a4 | 1403 | int vblank = 0; |
7c463586 | 1404 | unsigned long irqflags; |
05eff845 | 1405 | int irq_received; |
9db4a9c7 JB |
1406 | int ret = IRQ_NONE, pipe; |
1407 | bool blc_event = false; | |
6e5fca53 | 1408 | |
630681d9 EA |
1409 | atomic_inc(&dev_priv->irq_received); |
1410 | ||
ed4cb414 | 1411 | iir = I915_READ(IIR); |
a6b54f3f | 1412 | |
a6c45cf0 | 1413 | if (INTEL_INFO(dev)->gen >= 4) |
d874bcff | 1414 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
e25e6601 | 1415 | else |
d874bcff | 1416 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
af6061af | 1417 | |
05eff845 KP |
1418 | for (;;) { |
1419 | irq_received = iir != 0; | |
1420 | ||
1421 | /* Can't rely on pipestat interrupt bit in iir as it might | |
1422 | * have been cleared after the pipestat interrupt was received. | |
1423 | * It doesn't set the bit in iir again, but it still produces | |
1424 | * interrupts (for non-MSI). | |
1425 | */ | |
1ec14ad3 | 1426 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8a905236 | 1427 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 1428 | i915_handle_error(dev, false); |
8a905236 | 1429 | |
9db4a9c7 JB |
1430 | for_each_pipe(pipe) { |
1431 | int reg = PIPESTAT(pipe); | |
1432 | pipe_stats[pipe] = I915_READ(reg); | |
1433 | ||
1434 | /* | |
1435 | * Clear the PIPE*STAT regs before the IIR | |
1436 | */ | |
1437 | if (pipe_stats[pipe] & 0x8000ffff) { | |
1438 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
1439 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
1440 | pipe_name(pipe)); | |
1441 | I915_WRITE(reg, pipe_stats[pipe]); | |
1442 | irq_received = 1; | |
1443 | } | |
cdfbc41f | 1444 | } |
1ec14ad3 | 1445 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
05eff845 KP |
1446 | |
1447 | if (!irq_received) | |
1448 | break; | |
1449 | ||
1450 | ret = IRQ_HANDLED; | |
8ee1c3db | 1451 | |
5ca58282 JB |
1452 | /* Consume port. Then clear IIR or we'll miss events */ |
1453 | if ((I915_HAS_HOTPLUG(dev)) && | |
1454 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
1455 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1456 | ||
44d98a61 | 1457 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
1458 | hotplug_status); |
1459 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
1460 | queue_work(dev_priv->wq, |
1461 | &dev_priv->hotplug_work); | |
5ca58282 JB |
1462 | |
1463 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1464 | I915_READ(PORT_HOTPLUG_STAT); | |
1465 | } | |
1466 | ||
cdfbc41f EA |
1467 | I915_WRITE(IIR, iir); |
1468 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 1469 | |
7c1c2871 DA |
1470 | if (dev->primary->master) { |
1471 | master_priv = dev->primary->master->driver_priv; | |
1472 | if (master_priv->sarea_priv) | |
1473 | master_priv->sarea_priv->last_dispatch = | |
1474 | READ_BREADCRUMB(dev_priv); | |
1475 | } | |
0a3e67a4 | 1476 | |
549f7365 | 1477 | if (iir & I915_USER_INTERRUPT) |
1ec14ad3 CW |
1478 | notify_ring(dev, &dev_priv->ring[RCS]); |
1479 | if (iir & I915_BSD_USER_INTERRUPT) | |
1480 | notify_ring(dev, &dev_priv->ring[VCS]); | |
d1b851fc | 1481 | |
1afe3e9d | 1482 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
6b95a207 | 1483 | intel_prepare_page_flip(dev, 0); |
1afe3e9d JB |
1484 | if (dev_priv->flip_pending_is_done) |
1485 | intel_finish_page_flip_plane(dev, 0); | |
1486 | } | |
6b95a207 | 1487 | |
1afe3e9d | 1488 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
70565d00 | 1489 | intel_prepare_page_flip(dev, 1); |
1afe3e9d JB |
1490 | if (dev_priv->flip_pending_is_done) |
1491 | intel_finish_page_flip_plane(dev, 1); | |
1afe3e9d | 1492 | } |
6b95a207 | 1493 | |
9db4a9c7 JB |
1494 | for_each_pipe(pipe) { |
1495 | if (pipe_stats[pipe] & vblank_status && | |
1496 | drm_handle_vblank(dev, pipe)) { | |
1497 | vblank++; | |
1498 | if (!dev_priv->flip_pending_is_done) { | |
1499 | i915_pageflip_stall_check(dev, pipe); | |
1500 | intel_finish_page_flip(dev, pipe); | |
1501 | } | |
4e5359cd | 1502 | } |
7c463586 | 1503 | |
9db4a9c7 JB |
1504 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
1505 | blc_event = true; | |
cdfbc41f | 1506 | } |
7c463586 | 1507 | |
9db4a9c7 JB |
1508 | |
1509 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3b617967 | 1510 | intel_opregion_asle_intr(dev); |
cdfbc41f EA |
1511 | |
1512 | /* With MSI, interrupts are only generated when iir | |
1513 | * transitions from zero to nonzero. If another bit got | |
1514 | * set while we were handling the existing iir bits, then | |
1515 | * we would never get another interrupt. | |
1516 | * | |
1517 | * This is fine on non-MSI as well, as if we hit this path | |
1518 | * we avoid exiting the interrupt handler only to generate | |
1519 | * another one. | |
1520 | * | |
1521 | * Note that for MSI this could cause a stray interrupt report | |
1522 | * if an interrupt landed in the time between writing IIR and | |
1523 | * the posting read. This should be rare enough to never | |
1524 | * trigger the 99% of 100,000 interrupts test for disabling | |
1525 | * stray interrupts. | |
1526 | */ | |
1527 | iir = new_iir; | |
05eff845 | 1528 | } |
0a3e67a4 | 1529 | |
05eff845 | 1530 | return ret; |
1da177e4 LT |
1531 | } |
1532 | ||
af6061af | 1533 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
1534 | { |
1535 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 1536 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
1537 | |
1538 | i915_kernel_lost_context(dev); | |
1539 | ||
44d98a61 | 1540 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 1541 | |
c99b058f | 1542 | dev_priv->counter++; |
c29b669c | 1543 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 1544 | dev_priv->counter = 1; |
7c1c2871 DA |
1545 | if (master_priv->sarea_priv) |
1546 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 1547 | |
e1f99ce6 CW |
1548 | if (BEGIN_LP_RING(4) == 0) { |
1549 | OUT_RING(MI_STORE_DWORD_INDEX); | |
1550 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1551 | OUT_RING(dev_priv->counter); | |
1552 | OUT_RING(MI_USER_INTERRUPT); | |
1553 | ADVANCE_LP_RING(); | |
1554 | } | |
bc5f4523 | 1555 | |
c29b669c | 1556 | return dev_priv->counter; |
1da177e4 LT |
1557 | } |
1558 | ||
84b1fd10 | 1559 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
1560 | { |
1561 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 1562 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 1563 | int ret = 0; |
1ec14ad3 | 1564 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 1565 | |
44d98a61 | 1566 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
1567 | READ_BREADCRUMB(dev_priv)); |
1568 | ||
ed4cb414 | 1569 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
1570 | if (master_priv->sarea_priv) |
1571 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 1572 | return 0; |
ed4cb414 | 1573 | } |
1da177e4 | 1574 | |
7c1c2871 DA |
1575 | if (master_priv->sarea_priv) |
1576 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 1577 | |
b13c2b96 CW |
1578 | if (ring->irq_get(ring)) { |
1579 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, | |
1580 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
1581 | ring->irq_put(ring); | |
5a9a8d1a CW |
1582 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) |
1583 | ret = -EBUSY; | |
1da177e4 | 1584 | |
20caafa6 | 1585 | if (ret == -EBUSY) { |
3e684eae | 1586 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
1587 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
1588 | } | |
1589 | ||
af6061af DA |
1590 | return ret; |
1591 | } | |
1592 | ||
1da177e4 LT |
1593 | /* Needs the lock as it touches the ring. |
1594 | */ | |
c153f45f EA |
1595 | int i915_irq_emit(struct drm_device *dev, void *data, |
1596 | struct drm_file *file_priv) | |
1da177e4 | 1597 | { |
1da177e4 | 1598 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1599 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
1600 | int result; |
1601 | ||
1ec14ad3 | 1602 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { |
3e684eae | 1603 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1604 | return -EINVAL; |
1da177e4 | 1605 | } |
299eb93c EA |
1606 | |
1607 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1608 | ||
546b0974 | 1609 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 1610 | result = i915_emit_irq(dev); |
546b0974 | 1611 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 1612 | |
c153f45f | 1613 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 1614 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 1615 | return -EFAULT; |
1da177e4 LT |
1616 | } |
1617 | ||
1618 | return 0; | |
1619 | } | |
1620 | ||
1621 | /* Doesn't need the hardware lock. | |
1622 | */ | |
c153f45f EA |
1623 | int i915_irq_wait(struct drm_device *dev, void *data, |
1624 | struct drm_file *file_priv) | |
1da177e4 | 1625 | { |
1da177e4 | 1626 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1627 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
1628 | |
1629 | if (!dev_priv) { | |
3e684eae | 1630 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1631 | return -EINVAL; |
1da177e4 LT |
1632 | } |
1633 | ||
c153f45f | 1634 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
1635 | } |
1636 | ||
42f52ef8 KP |
1637 | /* Called from drm generic code, passed 'crtc' which |
1638 | * we use as a pipe index | |
1639 | */ | |
f71d4af4 | 1640 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1641 | { |
1642 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1643 | unsigned long irqflags; |
71e0ffa5 | 1644 | |
5eddb70b | 1645 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1646 | return -EINVAL; |
0a3e67a4 | 1647 | |
1ec14ad3 | 1648 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 1649 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1650 | i915_enable_pipestat(dev_priv, pipe, |
1651 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1652 | else |
7c463586 KP |
1653 | i915_enable_pipestat(dev_priv, pipe, |
1654 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
8692d00e CW |
1655 | |
1656 | /* maintain vblank delivery even in deep C-states */ | |
1657 | if (dev_priv->info->gen == 3) | |
1658 | I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16); | |
1ec14ad3 | 1659 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 1660 | |
0a3e67a4 JB |
1661 | return 0; |
1662 | } | |
1663 | ||
f71d4af4 | 1664 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1665 | { |
1666 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1667 | unsigned long irqflags; | |
1668 | ||
1669 | if (!i915_pipe_enabled(dev, pipe)) | |
1670 | return -EINVAL; | |
1671 | ||
1672 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1673 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | |
0206e353 | 1674 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
f796cf8f JB |
1675 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1676 | ||
1677 | return 0; | |
1678 | } | |
1679 | ||
f71d4af4 | 1680 | static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) |
b1f14ad0 JB |
1681 | { |
1682 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1683 | unsigned long irqflags; | |
1684 | ||
1685 | if (!i915_pipe_enabled(dev, pipe)) | |
1686 | return -EINVAL; | |
1687 | ||
1688 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1689 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | |
1690 | DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); | |
1691 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1692 | ||
1693 | return 0; | |
1694 | } | |
1695 | ||
7e231dbe JB |
1696 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
1697 | { | |
1698 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1699 | unsigned long irqflags; | |
1700 | u32 dpfl, imr; | |
1701 | ||
1702 | if (!i915_pipe_enabled(dev, pipe)) | |
1703 | return -EINVAL; | |
1704 | ||
1705 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1706 | dpfl = I915_READ(VLV_DPFLIPSTAT); | |
1707 | imr = I915_READ(VLV_IMR); | |
1708 | if (pipe == 0) { | |
1709 | dpfl |= PIPEA_VBLANK_INT_EN; | |
1710 | imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; | |
1711 | } else { | |
1712 | dpfl |= PIPEA_VBLANK_INT_EN; | |
1713 | imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
1714 | } | |
1715 | I915_WRITE(VLV_DPFLIPSTAT, dpfl); | |
1716 | I915_WRITE(VLV_IMR, imr); | |
1717 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1718 | ||
1719 | return 0; | |
1720 | } | |
1721 | ||
42f52ef8 KP |
1722 | /* Called from drm generic code, passed 'crtc' which |
1723 | * we use as a pipe index | |
1724 | */ | |
f71d4af4 | 1725 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1726 | { |
1727 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1728 | unsigned long irqflags; |
0a3e67a4 | 1729 | |
1ec14ad3 | 1730 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8692d00e CW |
1731 | if (dev_priv->info->gen == 3) |
1732 | I915_WRITE(INSTPM, | |
1733 | INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS); | |
1734 | ||
f796cf8f JB |
1735 | i915_disable_pipestat(dev_priv, pipe, |
1736 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1737 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
1738 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1739 | } | |
1740 | ||
f71d4af4 | 1741 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1742 | { |
1743 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1744 | unsigned long irqflags; | |
1745 | ||
1746 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1747 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? | |
0206e353 | 1748 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
1ec14ad3 | 1749 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
0a3e67a4 JB |
1750 | } |
1751 | ||
f71d4af4 | 1752 | static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) |
b1f14ad0 JB |
1753 | { |
1754 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1755 | unsigned long irqflags; | |
1756 | ||
1757 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1758 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? | |
1759 | DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); | |
1760 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1761 | } | |
1762 | ||
7e231dbe JB |
1763 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
1764 | { | |
1765 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1766 | unsigned long irqflags; | |
1767 | u32 dpfl, imr; | |
1768 | ||
1769 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1770 | dpfl = I915_READ(VLV_DPFLIPSTAT); | |
1771 | imr = I915_READ(VLV_IMR); | |
1772 | if (pipe == 0) { | |
1773 | dpfl &= ~PIPEA_VBLANK_INT_EN; | |
1774 | imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; | |
1775 | } else { | |
1776 | dpfl &= ~PIPEB_VBLANK_INT_EN; | |
1777 | imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
1778 | } | |
1779 | I915_WRITE(VLV_IMR, imr); | |
1780 | I915_WRITE(VLV_DPFLIPSTAT, dpfl); | |
1781 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1782 | } | |
1783 | ||
1784 | ||
702880f2 DA |
1785 | /* Set the vblank monitor pipe |
1786 | */ | |
c153f45f EA |
1787 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1788 | struct drm_file *file_priv) | |
702880f2 | 1789 | { |
702880f2 | 1790 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
1791 | |
1792 | if (!dev_priv) { | |
3e684eae | 1793 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1794 | return -EINVAL; |
702880f2 DA |
1795 | } |
1796 | ||
5b51694a | 1797 | return 0; |
702880f2 DA |
1798 | } |
1799 | ||
c153f45f EA |
1800 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1801 | struct drm_file *file_priv) | |
702880f2 | 1802 | { |
702880f2 | 1803 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1804 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
1805 | |
1806 | if (!dev_priv) { | |
3e684eae | 1807 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1808 | return -EINVAL; |
702880f2 DA |
1809 | } |
1810 | ||
0a3e67a4 | 1811 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 1812 | |
702880f2 DA |
1813 | return 0; |
1814 | } | |
1815 | ||
a6b54f3f MCA |
1816 | /** |
1817 | * Schedule buffer swap at given vertical blank. | |
1818 | */ | |
c153f45f EA |
1819 | int i915_vblank_swap(struct drm_device *dev, void *data, |
1820 | struct drm_file *file_priv) | |
a6b54f3f | 1821 | { |
bd95e0a4 EA |
1822 | /* The delayed swap mechanism was fundamentally racy, and has been |
1823 | * removed. The model was that the client requested a delayed flip/swap | |
1824 | * from the kernel, then waited for vblank before continuing to perform | |
1825 | * rendering. The problem was that the kernel might wake the client | |
1826 | * up before it dispatched the vblank swap (since the lock has to be | |
1827 | * held while touching the ringbuffer), in which case the client would | |
1828 | * clear and start the next frame before the swap occurred, and | |
1829 | * flicker would occur in addition to likely missing the vblank. | |
1830 | * | |
1831 | * In the absence of this ioctl, userland falls back to a correct path | |
1832 | * of waiting for a vblank, then dispatching the swap on its own. | |
1833 | * Context switching to userland and back is plenty fast enough for | |
1834 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 1835 | */ |
bd95e0a4 | 1836 | return -EINVAL; |
a6b54f3f MCA |
1837 | } |
1838 | ||
893eead0 CW |
1839 | static u32 |
1840 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 1841 | { |
893eead0 CW |
1842 | return list_entry(ring->request_list.prev, |
1843 | struct drm_i915_gem_request, list)->seqno; | |
1844 | } | |
1845 | ||
1846 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) | |
1847 | { | |
1848 | if (list_empty(&ring->request_list) || | |
1849 | i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { | |
1850 | /* Issue a wake-up to catch stuck h/w. */ | |
b2223497 | 1851 | if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { |
893eead0 CW |
1852 | DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", |
1853 | ring->name, | |
b2223497 | 1854 | ring->waiting_seqno, |
893eead0 CW |
1855 | ring->get_seqno(ring)); |
1856 | wake_up_all(&ring->irq_queue); | |
1857 | *err = true; | |
1858 | } | |
1859 | return true; | |
1860 | } | |
1861 | return false; | |
f65d9421 BG |
1862 | } |
1863 | ||
1ec14ad3 CW |
1864 | static bool kick_ring(struct intel_ring_buffer *ring) |
1865 | { | |
1866 | struct drm_device *dev = ring->dev; | |
1867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1868 | u32 tmp = I915_READ_CTL(ring); | |
1869 | if (tmp & RING_WAIT) { | |
1870 | DRM_ERROR("Kicking stuck wait on %s\n", | |
1871 | ring->name); | |
1872 | I915_WRITE_CTL(ring, tmp); | |
1873 | return true; | |
1874 | } | |
1ec14ad3 CW |
1875 | return false; |
1876 | } | |
1877 | ||
f65d9421 BG |
1878 | /** |
1879 | * This is called when the chip hasn't reported back with completed | |
1880 | * batchbuffers in a long time. The first time this is called we simply record | |
1881 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1882 | * again, we assume the chip is wedged and try to fix it. | |
1883 | */ | |
1884 | void i915_hangcheck_elapsed(unsigned long data) | |
1885 | { | |
1886 | struct drm_device *dev = (struct drm_device *)data; | |
1887 | drm_i915_private_t *dev_priv = dev->dev_private; | |
097354eb | 1888 | uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt; |
893eead0 CW |
1889 | bool err = false; |
1890 | ||
3e0dc6b0 BW |
1891 | if (!i915_enable_hangcheck) |
1892 | return; | |
1893 | ||
893eead0 | 1894 | /* If all work is done then ACTHD clearly hasn't advanced. */ |
1ec14ad3 CW |
1895 | if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) && |
1896 | i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) && | |
1897 | i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) { | |
893eead0 CW |
1898 | dev_priv->hangcheck_count = 0; |
1899 | if (err) | |
1900 | goto repeat; | |
1901 | return; | |
1902 | } | |
b9201c14 | 1903 | |
a6c45cf0 | 1904 | if (INTEL_INFO(dev)->gen < 4) { |
cbb465e7 CW |
1905 | instdone = I915_READ(INSTDONE); |
1906 | instdone1 = 0; | |
1907 | } else { | |
cbb465e7 CW |
1908 | instdone = I915_READ(INSTDONE_I965); |
1909 | instdone1 = I915_READ(INSTDONE1); | |
1910 | } | |
097354eb DV |
1911 | acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]); |
1912 | acthd_bsd = HAS_BSD(dev) ? | |
1913 | intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0; | |
1914 | acthd_blt = HAS_BLT(dev) ? | |
1915 | intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0; | |
f65d9421 | 1916 | |
cbb465e7 | 1917 | if (dev_priv->last_acthd == acthd && |
097354eb DV |
1918 | dev_priv->last_acthd_bsd == acthd_bsd && |
1919 | dev_priv->last_acthd_blt == acthd_blt && | |
cbb465e7 CW |
1920 | dev_priv->last_instdone == instdone && |
1921 | dev_priv->last_instdone1 == instdone1) { | |
1922 | if (dev_priv->hangcheck_count++ > 1) { | |
1923 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
653d7bed | 1924 | i915_handle_error(dev, true); |
8c80b59b CW |
1925 | |
1926 | if (!IS_GEN2(dev)) { | |
1927 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
1928 | * If so we can simply poke the RB_WAIT bit | |
1929 | * and break the hang. This should work on | |
1930 | * all but the second generation chipsets. | |
1931 | */ | |
1ec14ad3 CW |
1932 | if (kick_ring(&dev_priv->ring[RCS])) |
1933 | goto repeat; | |
1934 | ||
1935 | if (HAS_BSD(dev) && | |
1936 | kick_ring(&dev_priv->ring[VCS])) | |
1937 | goto repeat; | |
1938 | ||
1939 | if (HAS_BLT(dev) && | |
1940 | kick_ring(&dev_priv->ring[BCS])) | |
893eead0 | 1941 | goto repeat; |
8c80b59b CW |
1942 | } |
1943 | ||
cbb465e7 CW |
1944 | return; |
1945 | } | |
1946 | } else { | |
1947 | dev_priv->hangcheck_count = 0; | |
1948 | ||
1949 | dev_priv->last_acthd = acthd; | |
097354eb DV |
1950 | dev_priv->last_acthd_bsd = acthd_bsd; |
1951 | dev_priv->last_acthd_blt = acthd_blt; | |
cbb465e7 CW |
1952 | dev_priv->last_instdone = instdone; |
1953 | dev_priv->last_instdone1 = instdone1; | |
1954 | } | |
f65d9421 | 1955 | |
893eead0 | 1956 | repeat: |
f65d9421 | 1957 | /* Reset timer case chip hangs without another request being added */ |
b3b079db CW |
1958 | mod_timer(&dev_priv->hangcheck_timer, |
1959 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 BG |
1960 | } |
1961 | ||
1da177e4 LT |
1962 | /* drm_dma.h hooks |
1963 | */ | |
f71d4af4 | 1964 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1965 | { |
1966 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1967 | ||
4697995b JB |
1968 | atomic_set(&dev_priv->irq_received, 0); |
1969 | ||
1970 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
1971 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); | |
9e3c256d JB |
1972 | if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
1973 | INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); | |
4697995b | 1974 | |
036a4a7d | 1975 | I915_WRITE(HWSTAM, 0xeffe); |
bdfcdb63 | 1976 | |
036a4a7d ZW |
1977 | /* XXX hotplug from PCH */ |
1978 | ||
1979 | I915_WRITE(DEIMR, 0xffffffff); | |
1980 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 1981 | POSTING_READ(DEIER); |
036a4a7d ZW |
1982 | |
1983 | /* and GT */ | |
1984 | I915_WRITE(GTIMR, 0xffffffff); | |
1985 | I915_WRITE(GTIER, 0x0); | |
3143a2bf | 1986 | POSTING_READ(GTIER); |
c650156a ZW |
1987 | |
1988 | /* south display irq */ | |
1989 | I915_WRITE(SDEIMR, 0xffffffff); | |
1990 | I915_WRITE(SDEIER, 0x0); | |
3143a2bf | 1991 | POSTING_READ(SDEIER); |
036a4a7d ZW |
1992 | } |
1993 | ||
7e231dbe JB |
1994 | static void valleyview_irq_preinstall(struct drm_device *dev) |
1995 | { | |
1996 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1997 | int pipe; | |
1998 | ||
1999 | atomic_set(&dev_priv->irq_received, 0); | |
2000 | ||
2001 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
2002 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); | |
2003 | ||
2004 | /* VLV magic */ | |
2005 | I915_WRITE(VLV_IMR, 0); | |
2006 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
2007 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
2008 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
2009 | ||
7e231dbe JB |
2010 | /* and GT */ |
2011 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2012 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2013 | I915_WRITE(GTIMR, 0xffffffff); | |
2014 | I915_WRITE(GTIER, 0x0); | |
2015 | POSTING_READ(GTIER); | |
2016 | ||
2017 | I915_WRITE(DPINVGTT, 0xff); | |
2018 | ||
2019 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2020 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2021 | for_each_pipe(pipe) | |
2022 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2023 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2024 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2025 | I915_WRITE(VLV_IER, 0x0); | |
2026 | POSTING_READ(VLV_IER); | |
2027 | } | |
2028 | ||
7fe0b973 KP |
2029 | /* |
2030 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
2031 | * duration to 2ms (which is the minimum in the Display Port spec) | |
2032 | * | |
2033 | * This register is the same on all known PCH chips. | |
2034 | */ | |
2035 | ||
2036 | static void ironlake_enable_pch_hotplug(struct drm_device *dev) | |
2037 | { | |
2038 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2039 | u32 hotplug; | |
2040 | ||
2041 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
2042 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
2043 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
2044 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
2045 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
2046 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
2047 | } | |
2048 | ||
f71d4af4 | 2049 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
2050 | { |
2051 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2052 | /* enable kind of interrupts always enabled */ | |
013d5aa2 JB |
2053 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
2054 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | |
1ec14ad3 | 2055 | u32 render_irqs; |
2d7b8366 | 2056 | u32 hotplug_mask; |
036a4a7d | 2057 | |
4697995b JB |
2058 | DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); |
2059 | if (HAS_BSD(dev)) | |
2060 | DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); | |
2061 | if (HAS_BLT(dev)) | |
2062 | DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); | |
2063 | ||
2064 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
1ec14ad3 | 2065 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
2066 | |
2067 | /* should always can generate irq */ | |
2068 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 CW |
2069 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
2070 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); | |
3143a2bf | 2071 | POSTING_READ(DEIER); |
036a4a7d | 2072 | |
1ec14ad3 | 2073 | dev_priv->gt_irq_mask = ~0; |
036a4a7d ZW |
2074 | |
2075 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1ec14ad3 | 2076 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
881f47b6 | 2077 | |
1ec14ad3 CW |
2078 | if (IS_GEN6(dev)) |
2079 | render_irqs = | |
2080 | GT_USER_INTERRUPT | | |
e2a1e2f0 BW |
2081 | GEN6_BSD_USER_INTERRUPT | |
2082 | GEN6_BLITTER_USER_INTERRUPT; | |
1ec14ad3 CW |
2083 | else |
2084 | render_irqs = | |
88f23b8f | 2085 | GT_USER_INTERRUPT | |
c6df541c | 2086 | GT_PIPE_NOTIFY | |
1ec14ad3 CW |
2087 | GT_BSD_USER_INTERRUPT; |
2088 | I915_WRITE(GTIER, render_irqs); | |
3143a2bf | 2089 | POSTING_READ(GTIER); |
036a4a7d | 2090 | |
2d7b8366 | 2091 | if (HAS_PCH_CPT(dev)) { |
9035a97a CW |
2092 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | |
2093 | SDE_PORTB_HOTPLUG_CPT | | |
2094 | SDE_PORTC_HOTPLUG_CPT | | |
2095 | SDE_PORTD_HOTPLUG_CPT); | |
2d7b8366 | 2096 | } else { |
9035a97a CW |
2097 | hotplug_mask = (SDE_CRT_HOTPLUG | |
2098 | SDE_PORTB_HOTPLUG | | |
2099 | SDE_PORTC_HOTPLUG | | |
2100 | SDE_PORTD_HOTPLUG | | |
2101 | SDE_AUX_MASK); | |
2d7b8366 YL |
2102 | } |
2103 | ||
1ec14ad3 | 2104 | dev_priv->pch_irq_mask = ~hotplug_mask; |
c650156a ZW |
2105 | |
2106 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1ec14ad3 CW |
2107 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); |
2108 | I915_WRITE(SDEIER, hotplug_mask); | |
3143a2bf | 2109 | POSTING_READ(SDEIER); |
c650156a | 2110 | |
7fe0b973 KP |
2111 | ironlake_enable_pch_hotplug(dev); |
2112 | ||
f97108d1 JB |
2113 | if (IS_IRONLAKE_M(dev)) { |
2114 | /* Clear & enable PCU event interrupts */ | |
2115 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
2116 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
2117 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
2118 | } | |
2119 | ||
036a4a7d ZW |
2120 | return 0; |
2121 | } | |
2122 | ||
f71d4af4 | 2123 | static int ivybridge_irq_postinstall(struct drm_device *dev) |
b1f14ad0 JB |
2124 | { |
2125 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2126 | /* enable kind of interrupts always enabled */ | |
2127 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
2128 | DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB | | |
2129 | DE_PLANEB_FLIP_DONE_IVB; | |
2130 | u32 render_irqs; | |
2131 | u32 hotplug_mask; | |
2132 | ||
2133 | DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); | |
2134 | if (HAS_BSD(dev)) | |
2135 | DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); | |
2136 | if (HAS_BLT(dev)) | |
2137 | DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); | |
2138 | ||
2139 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
2140 | dev_priv->irq_mask = ~display_mask; | |
2141 | ||
2142 | /* should always can generate irq */ | |
2143 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
2144 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
2145 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB | | |
2146 | DE_PIPEB_VBLANK_IVB); | |
2147 | POSTING_READ(DEIER); | |
2148 | ||
2149 | dev_priv->gt_irq_mask = ~0; | |
2150 | ||
2151 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2152 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
2153 | ||
e2a1e2f0 BW |
2154 | render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | |
2155 | GEN6_BLITTER_USER_INTERRUPT; | |
b1f14ad0 JB |
2156 | I915_WRITE(GTIER, render_irqs); |
2157 | POSTING_READ(GTIER); | |
2158 | ||
2159 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | | |
2160 | SDE_PORTB_HOTPLUG_CPT | | |
2161 | SDE_PORTC_HOTPLUG_CPT | | |
2162 | SDE_PORTD_HOTPLUG_CPT); | |
2163 | dev_priv->pch_irq_mask = ~hotplug_mask; | |
2164 | ||
2165 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
2166 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); | |
2167 | I915_WRITE(SDEIER, hotplug_mask); | |
2168 | POSTING_READ(SDEIER); | |
2169 | ||
7fe0b973 KP |
2170 | ironlake_enable_pch_hotplug(dev); |
2171 | ||
b1f14ad0 JB |
2172 | return 0; |
2173 | } | |
2174 | ||
7e231dbe JB |
2175 | static int valleyview_irq_postinstall(struct drm_device *dev) |
2176 | { | |
2177 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2178 | u32 render_irqs; | |
2179 | u32 enable_mask; | |
2180 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
2181 | u16 msid; | |
2182 | ||
2183 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; | |
2184 | enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2185 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
2186 | ||
2187 | dev_priv->irq_mask = ~enable_mask; | |
2188 | ||
2189 | ||
2190 | DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); | |
2191 | DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); | |
2192 | DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); | |
2193 | ||
2194 | dev_priv->pipestat[0] = 0; | |
2195 | dev_priv->pipestat[1] = 0; | |
2196 | ||
2197 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
2198 | ||
2199 | /* Hack for broken MSIs on VLV */ | |
2200 | pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000); | |
2201 | pci_read_config_word(dev->pdev, 0x98, &msid); | |
2202 | msid &= 0xff; /* mask out delivery bits */ | |
2203 | msid |= (1<<14); | |
2204 | pci_write_config_word(dev_priv->dev->pdev, 0x98, msid); | |
2205 | ||
2206 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
2207 | I915_WRITE(VLV_IER, enable_mask); | |
2208 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2209 | I915_WRITE(PIPESTAT(0), 0xffff); | |
2210 | I915_WRITE(PIPESTAT(1), 0xffff); | |
2211 | POSTING_READ(VLV_IER); | |
2212 | ||
2213 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2214 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2215 | ||
2216 | render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT | | |
2217 | GT_GEN6_BLT_CS_ERROR_INTERRUPT | | |
e2a1e2f0 | 2218 | GT_GEN6_BLT_USER_INTERRUPT | |
7e231dbe JB |
2219 | GT_GEN6_BSD_USER_INTERRUPT | |
2220 | GT_GEN6_BSD_CS_ERROR_INTERRUPT | | |
2221 | GT_GEN7_L3_PARITY_ERROR_INTERRUPT | | |
2222 | GT_PIPE_NOTIFY | | |
2223 | GT_RENDER_CS_ERROR_INTERRUPT | | |
2224 | GT_SYNC_STATUS | | |
2225 | GT_USER_INTERRUPT; | |
2226 | ||
2227 | dev_priv->gt_irq_mask = ~render_irqs; | |
2228 | ||
2229 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2230 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2231 | I915_WRITE(GTIMR, 0); | |
2232 | I915_WRITE(GTIER, render_irqs); | |
2233 | POSTING_READ(GTIER); | |
2234 | ||
2235 | /* ack & enable invalid PTE error interrupts */ | |
2236 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
2237 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
2238 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
2239 | #endif | |
2240 | ||
2241 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
2242 | #if 0 /* FIXME: check register definitions; some have moved */ | |
2243 | /* Note HDMI and DP share bits */ | |
2244 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
2245 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
2246 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
2247 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
2248 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
2249 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
2250 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
2251 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
2252 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
2253 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2254 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { | |
2255 | hotplug_en |= CRT_HOTPLUG_INT_EN; | |
2256 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
2257 | } | |
2258 | #endif | |
2259 | ||
2260 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
2261 | ||
2262 | return 0; | |
2263 | } | |
2264 | ||
f71d4af4 | 2265 | static void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
2266 | { |
2267 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 2268 | int pipe; |
1da177e4 | 2269 | |
79e53945 JB |
2270 | atomic_set(&dev_priv->irq_received, 0); |
2271 | ||
036a4a7d | 2272 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 2273 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
036a4a7d | 2274 | |
5ca58282 JB |
2275 | if (I915_HAS_HOTPLUG(dev)) { |
2276 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2277 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2278 | } | |
2279 | ||
0a3e67a4 | 2280 | I915_WRITE(HWSTAM, 0xeffe); |
9db4a9c7 JB |
2281 | for_each_pipe(pipe) |
2282 | I915_WRITE(PIPESTAT(pipe), 0); | |
0a3e67a4 | 2283 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 2284 | I915_WRITE(IER, 0x0); |
3143a2bf | 2285 | POSTING_READ(IER); |
1da177e4 LT |
2286 | } |
2287 | ||
b01f2c3a JB |
2288 | /* |
2289 | * Must be called after intel_modeset_init or hotplug interrupts won't be | |
2290 | * enabled correctly. | |
2291 | */ | |
f71d4af4 | 2292 | static int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
2293 | { |
2294 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 2295 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 2296 | u32 error_mask; |
0a3e67a4 JB |
2297 | |
2298 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
0a3e67a4 | 2299 | |
7c463586 | 2300 | /* Unmask the interrupts that we always want on. */ |
1ec14ad3 | 2301 | dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX; |
7c463586 KP |
2302 | |
2303 | dev_priv->pipestat[0] = 0; | |
2304 | dev_priv->pipestat[1] = 0; | |
2305 | ||
5ca58282 | 2306 | if (I915_HAS_HOTPLUG(dev)) { |
5ca58282 JB |
2307 | /* Enable in IER... */ |
2308 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
2309 | /* and unmask in IMR */ | |
1ec14ad3 | 2310 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
5ca58282 JB |
2311 | } |
2312 | ||
63eeaf38 JB |
2313 | /* |
2314 | * Enable some error detection, note the instruction error mask | |
2315 | * bit is reserved, so we leave it masked. | |
2316 | */ | |
2317 | if (IS_G4X(dev)) { | |
2318 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
2319 | GM45_ERROR_MEM_PRIV | | |
2320 | GM45_ERROR_CP_PRIV | | |
2321 | I915_ERROR_MEMORY_REFRESH); | |
2322 | } else { | |
2323 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
2324 | I915_ERROR_MEMORY_REFRESH); | |
2325 | } | |
2326 | I915_WRITE(EMR, error_mask); | |
2327 | ||
1ec14ad3 | 2328 | I915_WRITE(IMR, dev_priv->irq_mask); |
c496fa1f | 2329 | I915_WRITE(IER, enable_mask); |
3143a2bf | 2330 | POSTING_READ(IER); |
ed4cb414 | 2331 | |
c496fa1f AJ |
2332 | if (I915_HAS_HOTPLUG(dev)) { |
2333 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
2334 | ||
2335 | /* Note HDMI and DP share bits */ | |
2336 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
2337 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
2338 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
2339 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
2340 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
2341 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
2342 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
2343 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
2344 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
2345 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2d1c9752 | 2346 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
c496fa1f | 2347 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
2d1c9752 AL |
2348 | |
2349 | /* Programming the CRT detection parameters tends | |
2350 | to generate a spurious hotplug event about three | |
2351 | seconds later. So just do it once. | |
2352 | */ | |
2353 | if (IS_G4X(dev)) | |
2354 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
2355 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
2356 | } | |
2357 | ||
c496fa1f AJ |
2358 | /* Ignore TV since it's buggy */ |
2359 | ||
2360 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
2361 | } | |
2362 | ||
3b617967 | 2363 | intel_opregion_enable_asle(dev); |
0a3e67a4 JB |
2364 | |
2365 | return 0; | |
1da177e4 LT |
2366 | } |
2367 | ||
7e231dbe JB |
2368 | static void valleyview_irq_uninstall(struct drm_device *dev) |
2369 | { | |
2370 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2371 | int pipe; | |
2372 | ||
2373 | if (!dev_priv) | |
2374 | return; | |
2375 | ||
2376 | dev_priv->vblank_pipe = 0; | |
2377 | ||
2378 | for_each_pipe(pipe) | |
2379 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2380 | ||
2381 | I915_WRITE(HWSTAM, 0xffffffff); | |
2382 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2383 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2384 | for_each_pipe(pipe) | |
2385 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2386 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2387 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2388 | I915_WRITE(VLV_IER, 0x0); | |
2389 | POSTING_READ(VLV_IER); | |
2390 | } | |
2391 | ||
f71d4af4 | 2392 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
2393 | { |
2394 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
4697995b JB |
2395 | |
2396 | if (!dev_priv) | |
2397 | return; | |
2398 | ||
2399 | dev_priv->vblank_pipe = 0; | |
2400 | ||
036a4a7d ZW |
2401 | I915_WRITE(HWSTAM, 0xffffffff); |
2402 | ||
2403 | I915_WRITE(DEIMR, 0xffffffff); | |
2404 | I915_WRITE(DEIER, 0x0); | |
2405 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
2406 | ||
2407 | I915_WRITE(GTIMR, 0xffffffff); | |
2408 | I915_WRITE(GTIER, 0x0); | |
2409 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
192aac1f KP |
2410 | |
2411 | I915_WRITE(SDEIMR, 0xffffffff); | |
2412 | I915_WRITE(SDEIER, 0x0); | |
2413 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
036a4a7d ZW |
2414 | } |
2415 | ||
f71d4af4 | 2416 | static void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
2417 | { |
2418 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 2419 | int pipe; |
91e3738e | 2420 | |
1da177e4 LT |
2421 | if (!dev_priv) |
2422 | return; | |
2423 | ||
0a3e67a4 JB |
2424 | dev_priv->vblank_pipe = 0; |
2425 | ||
5ca58282 JB |
2426 | if (I915_HAS_HOTPLUG(dev)) { |
2427 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2428 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2429 | } | |
2430 | ||
0a3e67a4 | 2431 | I915_WRITE(HWSTAM, 0xffffffff); |
9db4a9c7 JB |
2432 | for_each_pipe(pipe) |
2433 | I915_WRITE(PIPESTAT(pipe), 0); | |
0a3e67a4 | 2434 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 2435 | I915_WRITE(IER, 0x0); |
af6061af | 2436 | |
9db4a9c7 JB |
2437 | for_each_pipe(pipe) |
2438 | I915_WRITE(PIPESTAT(pipe), | |
2439 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
7c463586 | 2440 | I915_WRITE(IIR, I915_READ(IIR)); |
1da177e4 | 2441 | } |
f71d4af4 JB |
2442 | |
2443 | void intel_irq_init(struct drm_device *dev) | |
2444 | { | |
2445 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
2446 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
7e231dbe JB |
2447 | if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) || |
2448 | IS_VALLEYVIEW(dev)) { | |
f71d4af4 JB |
2449 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
2450 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
2451 | } | |
2452 | ||
c3613de9 KP |
2453 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
2454 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; | |
2455 | else | |
2456 | dev->driver->get_vblank_timestamp = NULL; | |
f71d4af4 JB |
2457 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
2458 | ||
7e231dbe JB |
2459 | if (IS_VALLEYVIEW(dev)) { |
2460 | dev->driver->irq_handler = valleyview_irq_handler; | |
2461 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
2462 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
2463 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
2464 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
2465 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
2466 | } else if (IS_IVYBRIDGE(dev)) { | |
f71d4af4 JB |
2467 | /* Share pre & uninstall handlers with ILK/SNB */ |
2468 | dev->driver->irq_handler = ivybridge_irq_handler; | |
2469 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
2470 | dev->driver->irq_postinstall = ivybridge_irq_postinstall; | |
2471 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
2472 | dev->driver->enable_vblank = ivybridge_enable_vblank; | |
2473 | dev->driver->disable_vblank = ivybridge_disable_vblank; | |
2474 | } else if (HAS_PCH_SPLIT(dev)) { | |
2475 | dev->driver->irq_handler = ironlake_irq_handler; | |
2476 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
2477 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
2478 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
2479 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
2480 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
2481 | } else { | |
2482 | dev->driver->irq_preinstall = i915_driver_irq_preinstall; | |
2483 | dev->driver->irq_postinstall = i915_driver_irq_postinstall; | |
2484 | dev->driver->irq_uninstall = i915_driver_irq_uninstall; | |
2485 | dev->driver->irq_handler = i915_driver_irq_handler; | |
2486 | dev->driver->enable_vblank = i915_enable_vblank; | |
2487 | dev->driver->disable_vblank = i915_disable_vblank; | |
2488 | } | |
2489 | } |