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drm/i915/chv: Add CHV HW status to SSEU status
[linux-block.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
b2c88f5b 33#include <linux/circ_buf.h>
760285e7
DH		 34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
1da177e4 36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
fca52a55
DV		 40/**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
7c7e10db 48static const u32 hpd_ibx[HPD_NUM_PINS] = {
e5868a31
EE		 49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54};
55
7c7e10db 56static const u32 hpd_cpt[HPD_NUM_PINS] = {
e5868a31 57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 58 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 59 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62};
63
7c7e10db 64static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
e5868a31
EE		 65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71};
72
7c7e10db 73static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
e5868a31
EE		 74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
7c7e10db 82static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are the same */
e5868a31
EE		 83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89};
90
5c502442 91/* IIR can theoretically queue up two events. Be paranoid. */
f86f3fb0 92#define GEN8_IRQ_RESET_NDX(type, which) do { \
5c502442
PZ		 93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
100} while (0)
101
f86f3fb0 102#define GEN5_IRQ_RESET(type) do { \
a9d356a6 103 I915_WRITE(type##IMR, 0xffffffff); \
5c502442 104 POSTING_READ(type##IMR); \
a9d356a6 105 I915_WRITE(type##IER, 0); \
5c502442
PZ		 106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
a9d356a6
PZ		 110} while (0)
111
337ba017
PZ		 112/*
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
114 */
115#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
117 if (val) { \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
119 (reg), val); \
120 I915_WRITE((reg), 0xffffffff); \
121 POSTING_READ(reg); \
122 I915_WRITE((reg), 0xffffffff); \
123 POSTING_READ(reg); \
124 } \
125} while (0)
126
35079899 127#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
337ba017 128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
35079899 129 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
7d1bd539
VS		 130 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
35079899
PZ		 132} while (0)
133
134#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
337ba017 135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
35079899 136 I915_WRITE(type##IER, (ier_val)); \
7d1bd539
VS		 137 I915_WRITE(type##IMR, (imr_val)); \
138 POSTING_READ(type##IMR); \
35079899
PZ		 139} while (0)
140
c9a9a268
ID		 141static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
142
036a4a7d 143/* For display hotplug interrupt */
47339cd9 144void
2d1013dd 145ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 146{
4bc9d430
DV		 147 assert_spin_locked(&dev_priv->irq_lock);
148
9df7575f 149 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 150 return;
c67a470b 151
1ec14ad3
CW		 152 if ((dev_priv->irq_mask & mask) != 0) {
153 dev_priv->irq_mask &= ~mask;
154 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 155 POSTING_READ(DEIMR);
036a4a7d
ZW		 156 }
157}
158
47339cd9 159void
2d1013dd 160ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 161{
4bc9d430
DV		 162 assert_spin_locked(&dev_priv->irq_lock);
163
06ffc778 164 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 165 return;
c67a470b 166
1ec14ad3
CW		 167 if ((dev_priv->irq_mask & mask) != mask) {
168 dev_priv->irq_mask |= mask;
169 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 170 POSTING_READ(DEIMR);
036a4a7d
ZW		 171 }
172}
173
43eaea13
PZ		 174/**
175 * ilk_update_gt_irq - update GTIMR
176 * @dev_priv: driver private
177 * @interrupt_mask: mask of interrupt bits to update
178 * @enabled_irq_mask: mask of interrupt bits to enable
179 */
180static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
181 uint32_t interrupt_mask,
182 uint32_t enabled_irq_mask)
183{
184 assert_spin_locked(&dev_priv->irq_lock);
185
15a17aae
DV		 186 WARN_ON(enabled_irq_mask & ~interrupt_mask);
187
9df7575f 188 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 189 return;
c67a470b 190
43eaea13
PZ		 191 dev_priv->gt_irq_mask &= ~interrupt_mask;
192 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
193 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
194 POSTING_READ(GTIMR);
195}
196
480c8033 197void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
43eaea13
PZ		 198{
199 ilk_update_gt_irq(dev_priv, mask, mask);
200}
201
480c8033 202void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
43eaea13
PZ		 203{
204 ilk_update_gt_irq(dev_priv, mask, 0);
205}
206
b900b949
ID		 207static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
208{
209 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
210}
211
a72fbc3a
ID		 212static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
213{
214 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
215}
216
b900b949
ID		 217static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
218{
219 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
220}
221
edbfdb45
PZ		 222/**
223 * snb_update_pm_irq - update GEN6_PMIMR
224 * @dev_priv: driver private
225 * @interrupt_mask: mask of interrupt bits to update
226 * @enabled_irq_mask: mask of interrupt bits to enable
227 */
228static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
229 uint32_t interrupt_mask,
230 uint32_t enabled_irq_mask)
231{
605cd25b 232 uint32_t new_val;
edbfdb45 233
15a17aae
DV		 234 WARN_ON(enabled_irq_mask & ~interrupt_mask);
235
edbfdb45
PZ		 236 assert_spin_locked(&dev_priv->irq_lock);
237
605cd25b 238 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 239 new_val &= ~interrupt_mask;
240 new_val |= (~enabled_irq_mask & interrupt_mask);
241
605cd25b
PZ		 242 if (new_val != dev_priv->pm_irq_mask) {
243 dev_priv->pm_irq_mask = new_val;
a72fbc3a
ID		 244 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
245 POSTING_READ(gen6_pm_imr(dev_priv));
f52ecbcf 246 }
edbfdb45
PZ		 247}
248
480c8033 249void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
edbfdb45 250{
9939fba2
ID		 251 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
252 return;
253
edbfdb45
PZ		 254 snb_update_pm_irq(dev_priv, mask, mask);
255}
256
9939fba2
ID		 257static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
258 uint32_t mask)
edbfdb45
PZ		 259{
260 snb_update_pm_irq(dev_priv, mask, 0);
261}
262
9939fba2
ID		 263void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
264{
265 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
266 return;
267
268 __gen6_disable_pm_irq(dev_priv, mask);
269}
270
3cc134e3
ID		 271void gen6_reset_rps_interrupts(struct drm_device *dev)
272{
273 struct drm_i915_private *dev_priv = dev->dev_private;
274 uint32_t reg = gen6_pm_iir(dev_priv);
275
276 spin_lock_irq(&dev_priv->irq_lock);
277 I915_WRITE(reg, dev_priv->pm_rps_events);
278 I915_WRITE(reg, dev_priv->pm_rps_events);
279 POSTING_READ(reg);
280 spin_unlock_irq(&dev_priv->irq_lock);
281}
282
b900b949
ID		 283void gen6_enable_rps_interrupts(struct drm_device *dev)
284{
285 struct drm_i915_private *dev_priv = dev->dev_private;
286
287 spin_lock_irq(&dev_priv->irq_lock);
78e68d36 288
b900b949 289 WARN_ON(dev_priv->rps.pm_iir);
3cc134e3 290 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
d4d70aa5 291 dev_priv->rps.interrupts_enabled = true;
78e68d36
ID		 292 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
293 dev_priv->pm_rps_events);
b900b949 294 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
78e68d36 295
b900b949
ID		 296 spin_unlock_irq(&dev_priv->irq_lock);
297}
298
59d02a1f
ID		 299u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
300{
301 /*
f24eeb19 302 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
59d02a1f 303 * if GEN6_PM_UP_EI_EXPIRED is masked.
f24eeb19
ID		 304 *
305 * TODO: verify if this can be reproduced on VLV,CHV.
59d02a1f
ID		 306 */
307 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
308 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
309
310 if (INTEL_INFO(dev_priv)->gen >= 8)
311 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
312
313 return mask;
314}
315
b900b949
ID		 316void gen6_disable_rps_interrupts(struct drm_device *dev)
317{
318 struct drm_i915_private *dev_priv = dev->dev_private;
319
d4d70aa5
ID		 320 spin_lock_irq(&dev_priv->irq_lock);
321 dev_priv->rps.interrupts_enabled = false;
322 spin_unlock_irq(&dev_priv->irq_lock);
323
324 cancel_work_sync(&dev_priv->rps.work);
325
9939fba2
ID		 326 spin_lock_irq(&dev_priv->irq_lock);
327
59d02a1f 328 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
9939fba2
ID		 329
330 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
b900b949
ID		 331 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
332 ~dev_priv->pm_rps_events);
9939fba2
ID		 333 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
334 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
b900b949 335
b900b949 336 dev_priv->rps.pm_iir = 0;
b900b949 337
9939fba2 338 spin_unlock_irq(&dev_priv->irq_lock);
b900b949
ID		 339}
340
fee884ed
DV		 341/**
342 * ibx_display_interrupt_update - update SDEIMR
343 * @dev_priv: driver private
344 * @interrupt_mask: mask of interrupt bits to update
345 * @enabled_irq_mask: mask of interrupt bits to enable
346 */
47339cd9
DV		 347void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
348 uint32_t interrupt_mask,
349 uint32_t enabled_irq_mask)
fee884ed
DV		 350{
351 uint32_t sdeimr = I915_READ(SDEIMR);
352 sdeimr &= ~interrupt_mask;
353 sdeimr |= (~enabled_irq_mask & interrupt_mask);
354
15a17aae
DV		 355 WARN_ON(enabled_irq_mask & ~interrupt_mask);
356
fee884ed
DV		 357 assert_spin_locked(&dev_priv->irq_lock);
358
9df7575f 359 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 360 return;
c67a470b 361
fee884ed
DV		 362 I915_WRITE(SDEIMR, sdeimr);
363 POSTING_READ(SDEIMR);
364}
8664281b 365
b5ea642a 366static void
755e9019
ID		 367__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
368 u32 enable_mask, u32 status_mask)
7c463586 369{
46c06a30 370 u32 reg = PIPESTAT(pipe);
755e9019 371 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 372
b79480ba 373 assert_spin_locked(&dev_priv->irq_lock);
d518ce50 374 WARN_ON(!intel_irqs_enabled(dev_priv));
b79480ba 375
04feced9
VS		 376 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
377 status_mask & ~PIPESTAT_INT_STATUS_MASK,
378 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
379 pipe_name(pipe), enable_mask, status_mask))
755e9019
ID		 380 return;
381
382 if ((pipestat & enable_mask) == enable_mask)
46c06a30
VS		 383 return;
384
91d181dd
ID		 385 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
386
46c06a30 387 /* Enable the interrupt, clear any pending status */
755e9019 388 pipestat |= enable_mask | status_mask;
46c06a30
VS		 389 I915_WRITE(reg, pipestat);
390 POSTING_READ(reg);
7c463586
KP		 391}
392
b5ea642a 393static void
755e9019
ID		 394__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
395 u32 enable_mask, u32 status_mask)
7c463586 396{
46c06a30 397 u32 reg = PIPESTAT(pipe);
755e9019 398 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 399
b79480ba 400 assert_spin_locked(&dev_priv->irq_lock);
d518ce50 401 WARN_ON(!intel_irqs_enabled(dev_priv));
b79480ba 402
04feced9
VS		 403 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
404 status_mask & ~PIPESTAT_INT_STATUS_MASK,
405 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
406 pipe_name(pipe), enable_mask, status_mask))
46c06a30
VS		 407 return;
408
755e9019
ID		 409 if ((pipestat & enable_mask) == 0)
410 return;
411
91d181dd
ID		 412 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
413
755e9019 414 pipestat &= ~enable_mask;
46c06a30
VS		 415 I915_WRITE(reg, pipestat);
416 POSTING_READ(reg);
7c463586
KP		 417}
418
10c59c51
ID		 419static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
420{
421 u32 enable_mask = status_mask << 16;
422
423 /*
724a6905
VS		 424 * On pipe A we don't support the PSR interrupt yet,
425 * on pipe B and C the same bit MBZ.
10c59c51
ID		 426 */
427 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
428 return 0;
724a6905
VS		 429 /*
430 * On pipe B and C we don't support the PSR interrupt yet, on pipe
431 * A the same bit is for perf counters which we don't use either.
432 */
433 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
434 return 0;
10c59c51
ID		 435
436 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
437 SPRITE0_FLIP_DONE_INT_EN_VLV |
438 SPRITE1_FLIP_DONE_INT_EN_VLV);
439 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
440 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
441 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
442 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
443
444 return enable_mask;
445}
446
755e9019
ID		 447void
448i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
449 u32 status_mask)
450{
451 u32 enable_mask;
452
10c59c51
ID		 453 if (IS_VALLEYVIEW(dev_priv->dev))
454 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
455 status_mask);
456 else
457 enable_mask = status_mask << 16;
755e9019
ID		 458 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
459}
460
461void
462i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
463 u32 status_mask)
464{
465 u32 enable_mask;
466
10c59c51
ID		 467 if (IS_VALLEYVIEW(dev_priv->dev))
468 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
469 status_mask);
470 else
471 enable_mask = status_mask << 16;
755e9019
ID		 472 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
473}
474
01c66889 475/**
f49e38dd 476 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 477 */
f49e38dd 478static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 479{
2d1013dd 480 struct drm_i915_private *dev_priv = dev->dev_private;
1ec14ad3 481
f49e38dd
JN		 482 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
483 return;
484
13321786 485 spin_lock_irq(&dev_priv->irq_lock);
01c66889 486
755e9019 487 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
f898780b 488 if (INTEL_INFO(dev)->gen >= 4)
3b6c42e8 489 i915_enable_pipestat(dev_priv, PIPE_A,
755e9019 490 PIPE_LEGACY_BLC_EVENT_STATUS);
1ec14ad3 491
13321786 492 spin_unlock_irq(&dev_priv->irq_lock);
01c66889
ZY		 493}
494
f75f3746
VS		 495/*
496 * This timing diagram depicts the video signal in and
497 * around the vertical blanking period.
498 *
499 * Assumptions about the fictitious mode used in this example:
500 * vblank_start >= 3
501 * vsync_start = vblank_start + 1
502 * vsync_end = vblank_start + 2
503 * vtotal = vblank_start + 3
504 *
505 * start of vblank:
506 * latch double buffered registers
507 * increment frame counter (ctg+)
508 * generate start of vblank interrupt (gen4+)
509 * |
510 * | frame start:
511 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
512 * | may be shifted forward 1-3 extra lines via PIPECONF
513 * | |
514 * | | start of vsync:
515 * | | generate vsync interrupt
516 * | | |
517 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
518 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
519 * ----va---> <-----------------vb--------------------> <--------va-------------
520 * | | <----vs-----> |
521 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
522 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
523 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
524 * | | |
525 * last visible pixel first visible pixel
526 * | increment frame counter (gen3/4)
527 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
528 *
529 * x = horizontal active
530 * _ = horizontal blanking
531 * hs = horizontal sync
532 * va = vertical active
533 * vb = vertical blanking
534 * vs = vertical sync
535 * vbs = vblank_start (number)
536 *
537 * Summary:
538 * - most events happen at the start of horizontal sync
539 * - frame start happens at the start of horizontal blank, 1-4 lines
540 * (depending on PIPECONF settings) after the start of vblank
541 * - gen3/4 pixel and frame counter are synchronized with the start
542 * of horizontal active on the first line of vertical active
543 */
544
4cdb83ec
VS		 545static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
546{
547 /* Gen2 doesn't have a hardware frame counter */
548 return 0;
549}
550
42f52ef8
KP		 551/* Called from drm generic code, passed a 'crtc', which
552 * we use as a pipe index
553 */
f71d4af4 554static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4 555{
2d1013dd 556 struct drm_i915_private *dev_priv = dev->dev_private;
0a3e67a4
JB		 557 unsigned long high_frame;
558 unsigned long low_frame;
0b2a8e09 559 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
f3a5c3f6
DV		 560 struct intel_crtc *intel_crtc =
561 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
562 const struct drm_display_mode *mode =
563 &intel_crtc->config->base.adjusted_mode;
0a3e67a4 564
f3a5c3f6
DV		 565 htotal = mode->crtc_htotal;
566 hsync_start = mode->crtc_hsync_start;
567 vbl_start = mode->crtc_vblank_start;
568 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
569 vbl_start = DIV_ROUND_UP(vbl_start, 2);
391f75e2 570
0b2a8e09
VS		 571 /* Convert to pixel count */
572 vbl_start *= htotal;
573
574 /* Start of vblank event occurs at start of hsync */
575 vbl_start -= htotal - hsync_start;
576
9db4a9c7
JB		 577 high_frame = PIPEFRAME(pipe);
578 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 579
0a3e67a4
JB		 580 /*
581 * High & low register fields aren't synchronized, so make sure
582 * we get a low value that's stable across two reads of the high
583 * register.
584 */
585 do {
5eddb70b 586 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 587 low = I915_READ(low_frame);
5eddb70b 588 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 589 } while (high1 != high2);
590
5eddb70b 591 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 592 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 593 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 594
595 /*
596 * The frame counter increments at beginning of active.
597 * Cook up a vblank counter by also checking the pixel
598 * counter against vblank start.
599 */
edc08d0a 600 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
0a3e67a4
JB		 601}
602
f71d4af4 603static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5 604{
2d1013dd 605 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 606 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5 607
9880b7a5
JB		 608 return I915_READ(reg);
609}
610
ad3543ed
MK		 611/* raw reads, only for fast reads of display block, no need for forcewake etc. */
612#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
ad3543ed 613
a225f079
VS		 614static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
615{
616 struct drm_device *dev = crtc->base.dev;
617 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 618 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
a225f079 619 enum pipe pipe = crtc->pipe;
80715b2f 620 int position, vtotal;
a225f079 621
80715b2f 622 vtotal = mode->crtc_vtotal;
a225f079
VS		 623 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
624 vtotal /= 2;
625
626 if (IS_GEN2(dev))
627 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
628 else
629 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
630
631 /*
80715b2f
VS		 632 * See update_scanline_offset() for the details on the
633 * scanline_offset adjustment.
a225f079 634 */
80715b2f 635 return (position + crtc->scanline_offset) % vtotal;
a225f079
VS		 636}
637
f71d4af4 638static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
abca9e45
VS		 639 unsigned int flags, int *vpos, int *hpos,
640 ktime_t *stime, ktime_t *etime)
0af7e4df 641{
c2baf4b7
VS		 642 struct drm_i915_private *dev_priv = dev->dev_private;
643 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 645 const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
3aa18df8 646 int position;
78e8fc6b 647 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
0af7e4df
MK		 648 bool in_vbl = true;
649 int ret = 0;
ad3543ed 650 unsigned long irqflags;
0af7e4df 651
c2baf4b7 652 if (!intel_crtc->active) {
0af7e4df 653 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 654 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 655 return 0;
656 }
657
c2baf4b7 658 htotal = mode->crtc_htotal;
78e8fc6b 659 hsync_start = mode->crtc_hsync_start;
c2baf4b7
VS		 660 vtotal = mode->crtc_vtotal;
661 vbl_start = mode->crtc_vblank_start;
662 vbl_end = mode->crtc_vblank_end;
0af7e4df 663
d31faf65
VS		 664 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
665 vbl_start = DIV_ROUND_UP(vbl_start, 2);
666 vbl_end /= 2;
667 vtotal /= 2;
668 }
669
c2baf4b7
VS		 670 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
671
ad3543ed
MK		 672 /*
673 * Lock uncore.lock, as we will do multiple timing critical raw
674 * register reads, potentially with preemption disabled, so the
675 * following code must not block on uncore.lock.
676 */
677 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
78e8fc6b 678
ad3543ed
MK		 679 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
680
681 /* Get optional system timestamp before query. */
682 if (stime)
683 *stime = ktime_get();
684
7c06b08a 685 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 686 /* No obvious pixelcount register. Only query vertical
687 * scanout position from Display scan line register.
688 */
a225f079 689 position = __intel_get_crtc_scanline(intel_crtc);
0af7e4df
MK		 690 } else {
691 /* Have access to pixelcount since start of frame.
692 * We can split this into vertical and horizontal
693 * scanout position.
694 */
ad3543ed 695 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
0af7e4df 696
3aa18df8
VS		 697 /* convert to pixel counts */
698 vbl_start *= htotal;
699 vbl_end *= htotal;
700 vtotal *= htotal;
78e8fc6b 701
7e78f1cb
VS		 702 /*
703 * In interlaced modes, the pixel counter counts all pixels,
704 * so one field will have htotal more pixels. In order to avoid
705 * the reported position from jumping backwards when the pixel
706 * counter is beyond the length of the shorter field, just
707 * clamp the position the length of the shorter field. This
708 * matches how the scanline counter based position works since
709 * the scanline counter doesn't count the two half lines.
710 */
711 if (position >= vtotal)
712 position = vtotal - 1;
713
78e8fc6b
VS		 714 /*
715 * Start of vblank interrupt is triggered at start of hsync,
716 * just prior to the first active line of vblank. However we
717 * consider lines to start at the leading edge of horizontal
718 * active. So, should we get here before we've crossed into
719 * the horizontal active of the first line in vblank, we would
720 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
721 * always add htotal-hsync_start to the current pixel position.
722 */
723 position = (position + htotal - hsync_start) % vtotal;
0af7e4df
MK		 724 }
725
ad3543ed
MK		 726 /* Get optional system timestamp after query. */
727 if (etime)
728 *etime = ktime_get();
729
730 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
731
732 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
733
3aa18df8
VS		 734 in_vbl = position >= vbl_start && position < vbl_end;
735
736 /*
737 * While in vblank, position will be negative
738 * counting up towards 0 at vbl_end. And outside
739 * vblank, position will be positive counting
740 * up since vbl_end.
741 */
742 if (position >= vbl_start)
743 position -= vbl_end;
744 else
745 position += vtotal - vbl_end;
0af7e4df 746
7c06b08a 747 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3aa18df8
VS		 748 *vpos = position;
749 *hpos = 0;
750 } else {
751 *vpos = position / htotal;
752 *hpos = position - (*vpos * htotal);
753 }
0af7e4df 754
0af7e4df
MK		 755 /* In vblank? */
756 if (in_vbl)
3d3cbd84 757 ret |= DRM_SCANOUTPOS_IN_VBLANK;
0af7e4df
MK		 758
759 return ret;
760}
761
a225f079
VS		 762int intel_get_crtc_scanline(struct intel_crtc *crtc)
763{
764 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
765 unsigned long irqflags;
766 int position;
767
768 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
769 position = __intel_get_crtc_scanline(crtc);
770 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
771
772 return position;
773}
774
f71d4af4 775static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 776 int *max_error,
777 struct timeval *vblank_time,
778 unsigned flags)
779{
4041b853 780 struct drm_crtc *crtc;
0af7e4df 781
7eb552ae 782 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 783 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 784 return -EINVAL;
785 }
786
787 /* Get drm_crtc to timestamp: */
4041b853
CW		 788 crtc = intel_get_crtc_for_pipe(dev, pipe);
789 if (crtc == NULL) {
790 DRM_ERROR("Invalid crtc %d\n", pipe);
791 return -EINVAL;
792 }
793
83d65738 794 if (!crtc->state->enable) {
4041b853
CW		 795 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
796 return -EBUSY;
797 }
0af7e4df
MK		 798
799 /* Helper routine in DRM core does all the work: */
4041b853
CW		 800 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
801 vblank_time, flags,
7da903ef 802 crtc,
6e3c9717 803 &to_intel_crtc(crtc)->config->base.adjusted_mode);
0af7e4df
MK		 804}
805
67c347ff
JN		 806static bool intel_hpd_irq_event(struct drm_device *dev,
807 struct drm_connector *connector)
321a1b30
EE		 808{
809 enum drm_connector_status old_status;
810
811 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
812 old_status = connector->status;
813
814 connector->status = connector->funcs->detect(connector, false);
67c347ff
JN		 815 if (old_status == connector->status)
816 return false;
817
818 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
321a1b30 819 connector->base.id,
c23cc417 820 connector->name,
67c347ff
JN		 821 drm_get_connector_status_name(old_status),
822 drm_get_connector_status_name(connector->status));
823
824 return true;
321a1b30
EE		 825}
826
13cf5504
DA		 827static void i915_digport_work_func(struct work_struct *work)
828{
829 struct drm_i915_private *dev_priv =
830 container_of(work, struct drm_i915_private, dig_port_work);
13cf5504
DA		 831 u32 long_port_mask, short_port_mask;
832 struct intel_digital_port *intel_dig_port;
b2c5c181 833 int i;
13cf5504
DA		 834 u32 old_bits = 0;
835
4cb21832 836 spin_lock_irq(&dev_priv->irq_lock);
13cf5504
DA		 837 long_port_mask = dev_priv->long_hpd_port_mask;
838 dev_priv->long_hpd_port_mask = 0;
839 short_port_mask = dev_priv->short_hpd_port_mask;
840 dev_priv->short_hpd_port_mask = 0;
4cb21832 841 spin_unlock_irq(&dev_priv->irq_lock);
13cf5504
DA		 842
843 for (i = 0; i < I915_MAX_PORTS; i++) {
844 bool valid = false;
845 bool long_hpd = false;
846 intel_dig_port = dev_priv->hpd_irq_port[i];
847 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
848 continue;
849
850 if (long_port_mask & (1 << i)) {
851 valid = true;
852 long_hpd = true;
853 } else if (short_port_mask & (1 << i))
854 valid = true;
855
856 if (valid) {
b2c5c181
DV		 857 enum irqreturn ret;
858
13cf5504 859 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
b2c5c181
DV		 860 if (ret == IRQ_NONE) {
861 /* fall back to old school hpd */
13cf5504
DA		 862 old_bits |= (1 << intel_dig_port->base.hpd_pin);
863 }
864 }
865 }
866
867 if (old_bits) {
4cb21832 868 spin_lock_irq(&dev_priv->irq_lock);
13cf5504 869 dev_priv->hpd_event_bits |= old_bits;
4cb21832 870 spin_unlock_irq(&dev_priv->irq_lock);
13cf5504
DA		 871 schedule_work(&dev_priv->hotplug_work);
872 }
873}
874
5ca58282
JB		 875/*
876 * Handle hotplug events outside the interrupt handler proper.
877 */
ac4c16c5
EE		 878#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
879
5ca58282
JB		 880static void i915_hotplug_work_func(struct work_struct *work)
881{
2d1013dd
JN		 882 struct drm_i915_private *dev_priv =
883 container_of(work, struct drm_i915_private, hotplug_work);
5ca58282 884 struct drm_device *dev = dev_priv->dev;
c31c4ba3 885 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 886 struct intel_connector *intel_connector;
887 struct intel_encoder *intel_encoder;
888 struct drm_connector *connector;
cd569aed 889 bool hpd_disabled = false;
321a1b30 890 bool changed = false;
142e2398 891 u32 hpd_event_bits;
4ef69c7a 892
a65e34c7 893 mutex_lock(&mode_config->mutex);
e67189ab
JB		 894 DRM_DEBUG_KMS("running encoder hotplug functions\n");
895
4cb21832 896 spin_lock_irq(&dev_priv->irq_lock);
142e2398
EE		 897
898 hpd_event_bits = dev_priv->hpd_event_bits;
899 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 900 list_for_each_entry(connector, &mode_config->connector_list, head) {
901 intel_connector = to_intel_connector(connector);
36cd7444
DA		 902 if (!intel_connector->encoder)
903 continue;
cd569aed
EE		 904 intel_encoder = intel_connector->encoder;
905 if (intel_encoder->hpd_pin > HPD_NONE &&
906 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
907 connector->polled == DRM_CONNECTOR_POLL_HPD) {
908 DRM_INFO("HPD interrupt storm detected on connector %s: "
909 "switching from hotplug detection to polling\n",
c23cc417 910 connector->name);
cd569aed
EE		 911 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
912 connector->polled = DRM_CONNECTOR_POLL_CONNECT
913 | DRM_CONNECTOR_POLL_DISCONNECT;
914 hpd_disabled = true;
915 }
142e2398
EE		 916 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
917 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
c23cc417 918 connector->name, intel_encoder->hpd_pin);
142e2398 919 }
cd569aed
EE		 920 }
921 /* if there were no outputs to poll, poll was disabled,
922 * therefore make sure it's enabled when disabling HPD on
923 * some connectors */
ac4c16c5 924 if (hpd_disabled) {
cd569aed 925 drm_kms_helper_poll_enable(dev);
6323751d
ID		 926 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
927 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
ac4c16c5 928 }
cd569aed 929
4cb21832 930 spin_unlock_irq(&dev_priv->irq_lock);
cd569aed 931
321a1b30
EE		 932 list_for_each_entry(connector, &mode_config->connector_list, head) {
933 intel_connector = to_intel_connector(connector);
36cd7444
DA		 934 if (!intel_connector->encoder)
935 continue;
321a1b30
EE		 936 intel_encoder = intel_connector->encoder;
937 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
938 if (intel_encoder->hot_plug)
939 intel_encoder->hot_plug(intel_encoder);
940 if (intel_hpd_irq_event(dev, connector))
941 changed = true;
942 }
943 }
40ee3381
KP		 944 mutex_unlock(&mode_config->mutex);
945
321a1b30
EE		 946 if (changed)
947 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 948}
949
d0ecd7e2 950static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1 951{
2d1013dd 952 struct drm_i915_private *dev_priv = dev->dev_private;
b5b72e89 953 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 954 u8 new_delay;
9270388e 955
d0ecd7e2 956 spin_lock(&mchdev_lock);
f97108d1 957
73edd18f
DV		 958 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
959
20e4d407 960 new_delay = dev_priv->ips.cur_delay;
9270388e 961
7648fa99 962 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 963 busy_up = I915_READ(RCPREVBSYTUPAVG);
964 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 965 max_avg = I915_READ(RCBMAXAVG);
966 min_avg = I915_READ(RCBMINAVG);
967
968 /* Handle RCS change request from hw */
b5b72e89 969 if (busy_up > max_avg) {
20e4d407
DV		 970 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
971 new_delay = dev_priv->ips.cur_delay - 1;
972 if (new_delay < dev_priv->ips.max_delay)
973 new_delay = dev_priv->ips.max_delay;
b5b72e89 974 } else if (busy_down < min_avg) {
20e4d407
DV		 975 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
976 new_delay = dev_priv->ips.cur_delay + 1;
977 if (new_delay > dev_priv->ips.min_delay)
978 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 979 }
980
7648fa99 981 if (ironlake_set_drps(dev, new_delay))
20e4d407 982 dev_priv->ips.cur_delay = new_delay;
f97108d1 983
d0ecd7e2 984 spin_unlock(&mchdev_lock);
9270388e 985
f97108d1
JB		 986 return;
987}
988
549f7365 989static void notify_ring(struct drm_device *dev,
a4872ba6 990 struct intel_engine_cs *ring)
549f7365 991{
93b0a4e0 992 if (!intel_ring_initialized(ring))
475553de
CW		 993 return;
994
bcfcc8ba 995 trace_i915_gem_request_notify(ring);
9862e600 996
549f7365 997 wake_up_all(&ring->irq_queue);
549f7365
CW		 998}
999
31685c25 1000static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
bf225f20 1001 struct intel_rps_ei *rps_ei)
31685c25
D		 1002{
1003 u32 cz_ts, cz_freq_khz;
1004 u32 render_count, media_count;
1005 u32 elapsed_render, elapsed_media, elapsed_time;
1006 u32 residency = 0;
1007
1008 cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1009 cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
1010
1011 render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1012 media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1013
bf225f20
CW		 1014 if (rps_ei->cz_clock == 0) {
1015 rps_ei->cz_clock = cz_ts;
1016 rps_ei->render_c0 = render_count;
1017 rps_ei->media_c0 = media_count;
31685c25
D		 1018
1019 return dev_priv->rps.cur_freq;
1020 }
1021
bf225f20
CW		 1022 elapsed_time = cz_ts - rps_ei->cz_clock;
1023 rps_ei->cz_clock = cz_ts;
31685c25 1024
bf225f20
CW		 1025 elapsed_render = render_count - rps_ei->render_c0;
1026 rps_ei->render_c0 = render_count;
31685c25 1027
bf225f20
CW		 1028 elapsed_media = media_count - rps_ei->media_c0;
1029 rps_ei->media_c0 = media_count;
31685c25
D		 1030
1031 /* Convert all the counters into common unit of milli sec */
1032 elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1033 elapsed_render /= cz_freq_khz;
1034 elapsed_media /= cz_freq_khz;
1035
1036 /*
1037 * Calculate overall C0 residency percentage
1038 * only if elapsed time is non zero
1039 */
1040 if (elapsed_time) {
1041 residency =
1042 ((max(elapsed_render, elapsed_media) * 100)
1043 / elapsed_time);
1044 }
1045
1046 return residency;
1047}
1048
1049/**
1050 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1051 * busy-ness calculated from C0 counters of render & media power wells
1052 * @dev_priv: DRM device private
1053 *
1054 */
4fa79042 1055static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
31685c25
D		 1056{
1057 u32 residency_C0_up = 0, residency_C0_down = 0;
4fa79042 1058 int new_delay, adj;
31685c25
D		 1059
1060 dev_priv->rps.ei_interrupt_count++;
1061
1062 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1063
1064
bf225f20
CW		 1065 if (dev_priv->rps.up_ei.cz_clock == 0) {
1066 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1067 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
31685c25
D		 1068 return dev_priv->rps.cur_freq;
1069 }
1070
1071
1072 /*
1073 * To down throttle, C0 residency should be less than down threshold
1074 * for continous EI intervals. So calculate down EI counters
1075 * once in VLV_INT_COUNT_FOR_DOWN_EI
1076 */
1077 if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1078
1079 dev_priv->rps.ei_interrupt_count = 0;
1080
1081 residency_C0_down = vlv_c0_residency(dev_priv,
bf225f20 1082 &dev_priv->rps.down_ei);
31685c25
D		 1083 } else {
1084 residency_C0_up = vlv_c0_residency(dev_priv,
bf225f20 1085 &dev_priv->rps.up_ei);
31685c25
D		 1086 }
1087
1088 new_delay = dev_priv->rps.cur_freq;
1089
1090 adj = dev_priv->rps.last_adj;
1091 /* C0 residency is greater than UP threshold. Increase Frequency */
1092 if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1093 if (adj > 0)
1094 adj *= 2;
1095 else
1096 adj = 1;
1097
1098 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1099 new_delay = dev_priv->rps.cur_freq + adj;
1100
1101 /*
1102 * For better performance, jump directly
1103 * to RPe if we're below it.
1104 */
1105 if (new_delay < dev_priv->rps.efficient_freq)
1106 new_delay = dev_priv->rps.efficient_freq;
1107
1108 } else if (!dev_priv->rps.ei_interrupt_count &&
1109 (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1110 if (adj < 0)
1111 adj *= 2;
1112 else
1113 adj = -1;
1114 /*
1115 * This means, C0 residency is less than down threshold over
1116 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1117 */
1118 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1119 new_delay = dev_priv->rps.cur_freq + adj;
1120 }
1121
1122 return new_delay;
1123}
1124
4912d041 1125static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 1126{
2d1013dd
JN		 1127 struct drm_i915_private *dev_priv =
1128 container_of(work, struct drm_i915_private, rps.work);
edbfdb45 1129 u32 pm_iir;
dd75fdc8 1130 int new_delay, adj;
4912d041 1131
59cdb63d 1132 spin_lock_irq(&dev_priv->irq_lock);
d4d70aa5
ID		 1133 /* Speed up work cancelation during disabling rps interrupts. */
1134 if (!dev_priv->rps.interrupts_enabled) {
1135 spin_unlock_irq(&dev_priv->irq_lock);
1136 return;
1137 }
c6a828d3
DV		 1138 pm_iir = dev_priv->rps.pm_iir;
1139 dev_priv->rps.pm_iir = 0;
a72fbc3a
ID		 1140 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1141 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
59cdb63d 1142 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 1143
60611c13 1144 /* Make sure we didn't queue anything we're not going to process. */
a6706b45 1145 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
60611c13 1146
a6706b45 1147 if ((pm_iir & dev_priv->pm_rps_events) == 0)
3b8d8d91
JB		 1148 return;
1149
4fc688ce 1150 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 1151
dd75fdc8 1152 adj = dev_priv->rps.last_adj;
7425034a 1153 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 1154 if (adj > 0)
1155 adj *= 2;
13a5660c
D		 1156 else {
1157 /* CHV needs even encode values */
1158 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1159 }
b39fb297 1160 new_delay = dev_priv->rps.cur_freq + adj;
7425034a
VS		 1161
1162 /*
1163 * For better performance, jump directly
1164 * to RPe if we're below it.
1165 */
b39fb297
BW		 1166 if (new_delay < dev_priv->rps.efficient_freq)
1167 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 1168 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
b39fb297
BW		 1169 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1170 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 1171 else
b39fb297 1172 new_delay = dev_priv->rps.min_freq_softlimit;
dd75fdc8 1173 adj = 0;
31685c25
D		 1174 } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1175 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
dd75fdc8
CW		 1176 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1177 if (adj < 0)
1178 adj *= 2;
13a5660c
D		 1179 else {
1180 /* CHV needs even encode values */
1181 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1182 }
b39fb297 1183 new_delay = dev_priv->rps.cur_freq + adj;
dd75fdc8 1184 } else { /* unknown event */
b39fb297 1185 new_delay = dev_priv->rps.cur_freq;
dd75fdc8 1186 }
3b8d8d91 1187
79249636
BW		 1188 /* sysfs frequency interfaces may have snuck in while servicing the
1189 * interrupt
1190 */
1272e7b8 1191 new_delay = clamp_t(int, new_delay,
b39fb297
BW		 1192 dev_priv->rps.min_freq_softlimit,
1193 dev_priv->rps.max_freq_softlimit);
27544369 1194
b39fb297 1195 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
dd75fdc8 1196
ffe02b40 1197 intel_set_rps(dev_priv->dev, new_delay);
3b8d8d91 1198
4fc688ce 1199 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 1200}
1201
e3689190
BW		 1202
1203/**
1204 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1205 * occurred.
1206 * @work: workqueue struct
1207 *
1208 * Doesn't actually do anything except notify userspace. As a consequence of
1209 * this event, userspace should try to remap the bad rows since statistically
1210 * it is likely the same row is more likely to go bad again.
1211 */
1212static void ivybridge_parity_work(struct work_struct *work)
1213{
2d1013dd
JN		 1214 struct drm_i915_private *dev_priv =
1215 container_of(work, struct drm_i915_private, l3_parity.error_work);
e3689190 1216 u32 error_status, row, bank, subbank;
35a85ac6 1217 char *parity_event[6];
e3689190 1218 uint32_t misccpctl;
35a85ac6 1219 uint8_t slice = 0;
e3689190
BW		 1220
1221 /* We must turn off DOP level clock gating to access the L3 registers.
1222 * In order to prevent a get/put style interface, acquire struct mutex
1223 * any time we access those registers.
1224 */
1225 mutex_lock(&dev_priv->dev->struct_mutex);
1226
35a85ac6
BW		 1227 /* If we've screwed up tracking, just let the interrupt fire again */
1228 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1229 goto out;
1230
e3689190
BW		 1231 misccpctl = I915_READ(GEN7_MISCCPCTL);
1232 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1233 POSTING_READ(GEN7_MISCCPCTL);
1234
35a85ac6
BW		 1235 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1236 u32 reg;
e3689190 1237
35a85ac6
BW		 1238 slice--;
1239 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1240 break;
e3689190 1241
35a85ac6 1242 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 1243
35a85ac6 1244 reg = GEN7_L3CDERRST1 + (slice * 0x200);
e3689190 1245
35a85ac6
BW		 1246 error_status = I915_READ(reg);
1247 row = GEN7_PARITY_ERROR_ROW(error_status);
1248 bank = GEN7_PARITY_ERROR_BANK(error_status);
1249 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1250
1251 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1252 POSTING_READ(reg);
1253
1254 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1255 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1256 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1257 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1258 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1259 parity_event[5] = NULL;
1260
5bdebb18 1261 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
35a85ac6 1262 KOBJ_CHANGE, parity_event);
e3689190 1263
35a85ac6
BW		 1264 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1265 slice, row, bank, subbank);
e3689190 1266
35a85ac6
BW		 1267 kfree(parity_event[4]);
1268 kfree(parity_event[3]);
1269 kfree(parity_event[2]);
1270 kfree(parity_event[1]);
1271 }
e3689190 1272
35a85ac6 1273 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 1274
35a85ac6
BW		 1275out:
1276 WARN_ON(dev_priv->l3_parity.which_slice);
4cb21832 1277 spin_lock_irq(&dev_priv->irq_lock);
480c8033 1278 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
4cb21832 1279 spin_unlock_irq(&dev_priv->irq_lock);
35a85ac6
BW		 1280
1281 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 1282}
1283
35a85ac6 1284static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190 1285{
2d1013dd 1286 struct drm_i915_private *dev_priv = dev->dev_private;
e3689190 1287
040d2baa 1288 if (!HAS_L3_DPF(dev))
e3689190
BW		 1289 return;
1290
d0ecd7e2 1291 spin_lock(&dev_priv->irq_lock);
480c8033 1292 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 1293 spin_unlock(&dev_priv->irq_lock);
e3689190 1294
35a85ac6
BW		 1295 iir &= GT_PARITY_ERROR(dev);
1296 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1297 dev_priv->l3_parity.which_slice |= 1 << 1;
1298
1299 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1300 dev_priv->l3_parity.which_slice |= 1 << 0;
1301
a4da4fa4 1302 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1303}
1304
f1af8fc1
PZ		 1305static void ilk_gt_irq_handler(struct drm_device *dev,
1306 struct drm_i915_private *dev_priv,
1307 u32 gt_iir)
1308{
1309 if (gt_iir &
1310 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1311 notify_ring(dev, &dev_priv->ring[RCS]);
1312 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1313 notify_ring(dev, &dev_priv->ring[VCS]);
1314}
1315
e7b4c6b1
DV		 1316static void snb_gt_irq_handler(struct drm_device *dev,
1317 struct drm_i915_private *dev_priv,
1318 u32 gt_iir)
1319{
1320
cc609d5d
BW		 1321 if (gt_iir &
1322 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1323 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1324 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 1325 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 1326 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 1327 notify_ring(dev, &dev_priv->ring[BCS]);
1328
cc609d5d
BW		 1329 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1330 GT_BSD_CS_ERROR_INTERRUPT |
aaecdf61
DV		 1331 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1332 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
e3689190 1333
35a85ac6
BW		 1334 if (gt_iir & GT_PARITY_ERROR(dev))
1335 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1336}
1337
abd58f01
BW		 1338static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1339 struct drm_i915_private *dev_priv,
1340 u32 master_ctl)
1341{
e981e7b1 1342 struct intel_engine_cs *ring;
abd58f01
BW		 1343 u32 rcs, bcs, vcs;
1344 uint32_t tmp = 0;
1345 irqreturn_t ret = IRQ_NONE;
1346
1347 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1348 tmp = I915_READ(GEN8_GT_IIR(0));
1349 if (tmp) {
38cc46d7 1350 I915_WRITE(GEN8_GT_IIR(0), tmp);
abd58f01 1351 ret = IRQ_HANDLED;
e981e7b1 1352
abd58f01 1353 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
e981e7b1 1354 ring = &dev_priv->ring[RCS];
abd58f01 1355 if (rcs & GT_RENDER_USER_INTERRUPT)
e981e7b1
TD		 1356 notify_ring(dev, ring);
1357 if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
3f7531c3 1358 intel_lrc_irq_handler(ring);
e981e7b1
TD		 1359
1360 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1361 ring = &dev_priv->ring[BCS];
abd58f01 1362 if (bcs & GT_RENDER_USER_INTERRUPT)
e981e7b1
TD		 1363 notify_ring(dev, ring);
1364 if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
3f7531c3 1365 intel_lrc_irq_handler(ring);
abd58f01
BW		 1366 } else
1367 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1368 }
1369
85f9b5f9 1370 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
abd58f01
BW		 1371 tmp = I915_READ(GEN8_GT_IIR(1));
1372 if (tmp) {
38cc46d7 1373 I915_WRITE(GEN8_GT_IIR(1), tmp);
abd58f01 1374 ret = IRQ_HANDLED;
e981e7b1 1375
abd58f01 1376 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
e981e7b1 1377 ring = &dev_priv->ring[VCS];
abd58f01 1378 if (vcs & GT_RENDER_USER_INTERRUPT)
e981e7b1 1379 notify_ring(dev, ring);
73d477f6 1380 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
3f7531c3 1381 intel_lrc_irq_handler(ring);
e981e7b1 1382
85f9b5f9 1383 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
e981e7b1 1384 ring = &dev_priv->ring[VCS2];
85f9b5f9 1385 if (vcs & GT_RENDER_USER_INTERRUPT)
e981e7b1 1386 notify_ring(dev, ring);
73d477f6 1387 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
3f7531c3 1388 intel_lrc_irq_handler(ring);
abd58f01
BW		 1389 } else
1390 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1391 }
1392
0961021a
BW		 1393 if (master_ctl & GEN8_GT_PM_IRQ) {
1394 tmp = I915_READ(GEN8_GT_IIR(2));
1395 if (tmp & dev_priv->pm_rps_events) {
0961021a
BW		 1396 I915_WRITE(GEN8_GT_IIR(2),
1397 tmp & dev_priv->pm_rps_events);
38cc46d7 1398 ret = IRQ_HANDLED;
c9a9a268 1399 gen6_rps_irq_handler(dev_priv, tmp);
0961021a
BW		 1400 } else
1401 DRM_ERROR("The master control interrupt lied (PM)!\n");
1402 }
1403
abd58f01
BW		 1404 if (master_ctl & GEN8_GT_VECS_IRQ) {
1405 tmp = I915_READ(GEN8_GT_IIR(3));
1406 if (tmp) {
38cc46d7 1407 I915_WRITE(GEN8_GT_IIR(3), tmp);
abd58f01 1408 ret = IRQ_HANDLED;
e981e7b1 1409
abd58f01 1410 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
e981e7b1 1411 ring = &dev_priv->ring[VECS];
abd58f01 1412 if (vcs & GT_RENDER_USER_INTERRUPT)
e981e7b1 1413 notify_ring(dev, ring);
73d477f6 1414 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
3f7531c3 1415 intel_lrc_irq_handler(ring);
abd58f01
BW		 1416 } else
1417 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1418 }
1419
1420 return ret;
1421}
1422
b543fb04
EE		 1423#define HPD_STORM_DETECT_PERIOD 1000
1424#define HPD_STORM_THRESHOLD 5
1425
07c338ce 1426static int pch_port_to_hotplug_shift(enum port port)
13cf5504
DA		 1427{
1428 switch (port) {
1429 case PORT_A:
1430 case PORT_E:
1431 default:
1432 return -1;
1433 case PORT_B:
1434 return 0;
1435 case PORT_C:
1436 return 8;
1437 case PORT_D:
1438 return 16;
1439 }
1440}
1441
07c338ce 1442static int i915_port_to_hotplug_shift(enum port port)
13cf5504
DA		 1443{
1444 switch (port) {
1445 case PORT_A:
1446 case PORT_E:
1447 default:
1448 return -1;
1449 case PORT_B:
1450 return 17;
1451 case PORT_C:
1452 return 19;
1453 case PORT_D:
1454 return 21;
1455 }
1456}
1457
1458static inline enum port get_port_from_pin(enum hpd_pin pin)
1459{
1460 switch (pin) {
1461 case HPD_PORT_B:
1462 return PORT_B;
1463 case HPD_PORT_C:
1464 return PORT_C;
1465 case HPD_PORT_D:
1466 return PORT_D;
1467 default:
1468 return PORT_A; /* no hpd */
1469 }
1470}
1471
10a504de 1472static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba 1473 u32 hotplug_trigger,
13cf5504 1474 u32 dig_hotplug_reg,
7c7e10db 1475 const u32 hpd[HPD_NUM_PINS])
b543fb04 1476{
2d1013dd 1477 struct drm_i915_private *dev_priv = dev->dev_private;
b543fb04 1478 int i;
13cf5504 1479 enum port port;
10a504de 1480 bool storm_detected = false;
13cf5504
DA		 1481 bool queue_dig = false, queue_hp = false;
1482 u32 dig_shift;
1483 u32 dig_port_mask = 0;
b543fb04 1484
91d131d2
DV		 1485 if (!hotplug_trigger)
1486 return;
1487
13cf5504
DA		 1488 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1489 hotplug_trigger, dig_hotplug_reg);
cc9bd499 1490
b5ea2d56 1491 spin_lock(&dev_priv->irq_lock);
b543fb04 1492 for (i = 1; i < HPD_NUM_PINS; i++) {
13cf5504
DA		 1493 if (!(hpd[i] & hotplug_trigger))
1494 continue;
1495
1496 port = get_port_from_pin(i);
1497 if (port && dev_priv->hpd_irq_port[port]) {
1498 bool long_hpd;
1499
07c338ce
JN		 1500 if (HAS_PCH_SPLIT(dev)) {
1501 dig_shift = pch_port_to_hotplug_shift(port);
13cf5504 1502 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
07c338ce
JN		 1503 } else {
1504 dig_shift = i915_port_to_hotplug_shift(port);
1505 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
13cf5504
DA		 1506 }
1507
26fbb774
VS		 1508 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1509 port_name(port),
1510 long_hpd ? "long" : "short");
13cf5504
DA		 1511 /* for long HPD pulses we want to have the digital queue happen,
1512 but we still want HPD storm detection to function. */
1513 if (long_hpd) {
1514 dev_priv->long_hpd_port_mask |= (1 << port);
1515 dig_port_mask |= hpd[i];
1516 } else {
1517 /* for short HPD just trigger the digital queue */
1518 dev_priv->short_hpd_port_mask |= (1 << port);
1519 hotplug_trigger &= ~hpd[i];
1520 }
1521 queue_dig = true;
1522 }
1523 }
821450c6 1524
13cf5504 1525 for (i = 1; i < HPD_NUM_PINS; i++) {
3ff04a16
DV		 1526 if (hpd[i] & hotplug_trigger &&
1527 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1528 /*
1529 * On GMCH platforms the interrupt mask bits only
1530 * prevent irq generation, not the setting of the
1531 * hotplug bits itself. So only WARN about unexpected
1532 * interrupts on saner platforms.
1533 */
1534 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1535 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1536 hotplug_trigger, i, hpd[i]);
1537
1538 continue;
1539 }
b8f102e8 1540
b543fb04
EE		 1541 if (!(hpd[i] & hotplug_trigger) ||
1542 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1543 continue;
1544
13cf5504
DA		 1545 if (!(dig_port_mask & hpd[i])) {
1546 dev_priv->hpd_event_bits |= (1 << i);
1547 queue_hp = true;
1548 }
1549
b543fb04
EE		 1550 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1551 dev_priv->hpd_stats[i].hpd_last_jiffies
1552 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1553 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1554 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1555 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1556 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1557 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1558 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1559 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1560 storm_detected = true;
b543fb04
EE		 1561 } else {
1562 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1563 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1564 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1565 }
1566 }
1567
10a504de
DV		 1568 if (storm_detected)
1569 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1570 spin_unlock(&dev_priv->irq_lock);
5876fa0d 1571
645416f5
DV		 1572 /*
1573 * Our hotplug handler can grab modeset locks (by calling down into the
1574 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1575 * queue for otherwise the flush_work in the pageflip code will
1576 * deadlock.
1577 */
13cf5504 1578 if (queue_dig)
0e32b39c 1579 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
13cf5504
DA		 1580 if (queue_hp)
1581 schedule_work(&dev_priv->hotplug_work);
b543fb04
EE		 1582}
1583
515ac2bb
DV		 1584static void gmbus_irq_handler(struct drm_device *dev)
1585{
2d1013dd 1586 struct drm_i915_private *dev_priv = dev->dev_private;
28c70f16 1587
28c70f16 1588 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1589}
1590
ce99c256
DV		 1591static void dp_aux_irq_handler(struct drm_device *dev)
1592{
2d1013dd 1593 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 1594
9ee32fea 1595 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1596}
1597
8bf1e9f1 1598#if defined(CONFIG_DEBUG_FS)
277de95e
DV		 1599static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1600 uint32_t crc0, uint32_t crc1,
1601 uint32_t crc2, uint32_t crc3,
1602 uint32_t crc4)
8bf1e9f1
SH		 1603{
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1606 struct intel_pipe_crc_entry *entry;
ac2300d4 1607 int head, tail;
b2c88f5b 1608
d538bbdf
DL		 1609 spin_lock(&pipe_crc->lock);
1610
0c912c79 1611 if (!pipe_crc->entries) {
d538bbdf 1612 spin_unlock(&pipe_crc->lock);
34273620 1613 DRM_DEBUG_KMS("spurious interrupt\n");
0c912c79
DL		 1614 return;
1615 }
1616
d538bbdf
DL		 1617 head = pipe_crc->head;
1618 tail = pipe_crc->tail;
b2c88f5b
DL		 1619
1620 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
d538bbdf 1621 spin_unlock(&pipe_crc->lock);
b2c88f5b
DL		 1622 DRM_ERROR("CRC buffer overflowing\n");
1623 return;
1624 }
1625
1626 entry = &pipe_crc->entries[head];
8bf1e9f1 1627
8bc5e955 1628 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
eba94eb9
DV		 1629 entry->crc[0] = crc0;
1630 entry->crc[1] = crc1;
1631 entry->crc[2] = crc2;
1632 entry->crc[3] = crc3;
1633 entry->crc[4] = crc4;
b2c88f5b
DL		 1634
1635 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
d538bbdf
DL		 1636 pipe_crc->head = head;
1637
1638 spin_unlock(&pipe_crc->lock);
07144428
DL		 1639
1640 wake_up_interruptible(&pipe_crc->wq);
8bf1e9f1 1641}
277de95e
DV		 1642#else
1643static inline void
1644display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1645 uint32_t crc0, uint32_t crc1,
1646 uint32_t crc2, uint32_t crc3,
1647 uint32_t crc4) {}
1648#endif
1649
eba94eb9 1650
277de95e 1651static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5a69b89f
DV		 1652{
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654
277de95e
DV		 1655 display_pipe_crc_irq_handler(dev, pipe,
1656 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1657 0, 0, 0, 0);
5a69b89f
DV		 1658}
1659
277de95e 1660static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
eba94eb9
DV		 1661{
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663
277de95e
DV		 1664 display_pipe_crc_irq_handler(dev, pipe,
1665 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1666 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1667 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1668 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1669 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
eba94eb9 1670}
5b3a856b 1671
277de95e 1672static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5b3a856b
DV		 1673{
1674 struct drm_i915_private *dev_priv = dev->dev_private;
0b5c5ed0
DV		 1675 uint32_t res1, res2;
1676
1677 if (INTEL_INFO(dev)->gen >= 3)
1678 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1679 else
1680 res1 = 0;
1681
1682 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1683 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1684 else
1685 res2 = 0;
5b3a856b 1686
277de95e
DV		 1687 display_pipe_crc_irq_handler(dev, pipe,
1688 I915_READ(PIPE_CRC_RES_RED(pipe)),
1689 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1690 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1691 res1, res2);
5b3a856b 1692}
8bf1e9f1 1693
1403c0d4
PZ		 1694/* The RPS events need forcewake, so we add them to a work queue and mask their
1695 * IMR bits until the work is done. Other interrupts can be processed without
1696 * the work queue. */
1697static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1698{
4a74de82
ID		 1699 /* TODO: RPS on GEN9+ is not supported yet. */
1700 if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
1701 "GEN9+: unexpected RPS IRQ\n"))
132f3f17
ID		 1702 return;
1703
a6706b45 1704 if (pm_iir & dev_priv->pm_rps_events) {
59cdb63d 1705 spin_lock(&dev_priv->irq_lock);
480c8033 1706 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
d4d70aa5
ID		 1707 if (dev_priv->rps.interrupts_enabled) {
1708 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1709 queue_work(dev_priv->wq, &dev_priv->rps.work);
1710 }
59cdb63d 1711 spin_unlock(&dev_priv->irq_lock);
baf02a1f 1712 }
baf02a1f 1713
c9a9a268
ID		 1714 if (INTEL_INFO(dev_priv)->gen >= 8)
1715 return;
1716
1403c0d4
PZ		 1717 if (HAS_VEBOX(dev_priv->dev)) {
1718 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1719 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 1720
aaecdf61
DV		 1721 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1722 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
12638c57 1723 }
baf02a1f
BW		 1724}
1725
8d7849db
VS		 1726static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1727{
8d7849db
VS		 1728 if (!drm_handle_vblank(dev, pipe))
1729 return false;
1730
8d7849db
VS		 1731 return true;
1732}
1733
c1874ed7
ID		 1734static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1735{
1736 struct drm_i915_private *dev_priv = dev->dev_private;
91d181dd 1737 u32 pipe_stats[I915_MAX_PIPES] = { };
c1874ed7
ID		 1738 int pipe;
1739
58ead0d7 1740 spin_lock(&dev_priv->irq_lock);
055e393f 1741 for_each_pipe(dev_priv, pipe) {
91d181dd 1742 int reg;
bbb5eebf 1743 u32 mask, iir_bit = 0;
91d181dd 1744
bbb5eebf
DV		 1745 /*
1746 * PIPESTAT bits get signalled even when the interrupt is
1747 * disabled with the mask bits, and some of the status bits do
1748 * not generate interrupts at all (like the underrun bit). Hence
1749 * we need to be careful that we only handle what we want to
1750 * handle.
1751 */
0f239f4c
DV		 1752
1753 /* fifo underruns are filterered in the underrun handler. */
1754 mask = PIPE_FIFO_UNDERRUN_STATUS;
bbb5eebf
DV		 1755
1756 switch (pipe) {
1757 case PIPE_A:
1758 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1759 break;
1760 case PIPE_B:
1761 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1762 break;
3278f67f
VS		 1763 case PIPE_C:
1764 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1765 break;
bbb5eebf
DV		 1766 }
1767 if (iir & iir_bit)
1768 mask |= dev_priv->pipestat_irq_mask[pipe];
1769
1770 if (!mask)
91d181dd
ID		 1771 continue;
1772
1773 reg = PIPESTAT(pipe);
bbb5eebf
DV		 1774 mask |= PIPESTAT_INT_ENABLE_MASK;
1775 pipe_stats[pipe] = I915_READ(reg) & mask;
c1874ed7
ID		 1776
1777 /*
1778 * Clear the PIPE*STAT regs before the IIR
1779 */
91d181dd
ID		 1780 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1781 PIPESTAT_INT_STATUS_MASK))
c1874ed7
ID		 1782 I915_WRITE(reg, pipe_stats[pipe]);
1783 }
58ead0d7 1784 spin_unlock(&dev_priv->irq_lock);
c1874ed7 1785
055e393f 1786 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 1787 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1788 intel_pipe_handle_vblank(dev, pipe))
1789 intel_check_page_flip(dev, pipe);
c1874ed7 1790
579a9b0e 1791 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
c1874ed7
ID		 1792 intel_prepare_page_flip(dev, pipe);
1793 intel_finish_page_flip(dev, pipe);
1794 }
1795
1796 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1797 i9xx_pipe_crc_irq_handler(dev, pipe);
1798
1f7247c0
DV		 1799 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1800 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
c1874ed7
ID		 1801 }
1802
1803 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1804 gmbus_irq_handler(dev);
1805}
1806
16c6c56b
VS		 1807static void i9xx_hpd_irq_handler(struct drm_device *dev)
1808{
1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1811
3ff60f89
OM		 1812 if (hotplug_status) {
1813 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1814 /*
1815 * Make sure hotplug status is cleared before we clear IIR, or else we
1816 * may miss hotplug events.
1817 */
1818 POSTING_READ(PORT_HOTPLUG_STAT);
16c6c56b 1819
3ff60f89
OM		 1820 if (IS_G4X(dev)) {
1821 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
16c6c56b 1822
13cf5504 1823 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
3ff60f89
OM		 1824 } else {
1825 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
16c6c56b 1826
13cf5504 1827 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
3ff60f89 1828 }
16c6c56b 1829
3ff60f89
OM		 1830 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1831 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1832 dp_aux_irq_handler(dev);
1833 }
16c6c56b
VS		 1834}
1835
ff1f525e 1836static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe 1837{
45a83f84 1838 struct drm_device *dev = arg;
2d1013dd 1839 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 1840 u32 iir, gt_iir, pm_iir;
1841 irqreturn_t ret = IRQ_NONE;
7e231dbe 1842
2dd2a883
ID		 1843 if (!intel_irqs_enabled(dev_priv))
1844 return IRQ_NONE;
1845
7e231dbe 1846 while (true) {
3ff60f89
OM		 1847 /* Find, clear, then process each source of interrupt */
1848
7e231dbe 1849 gt_iir = I915_READ(GTIIR);
3ff60f89
OM		 1850 if (gt_iir)
1851 I915_WRITE(GTIIR, gt_iir);
1852
7e231dbe 1853 pm_iir = I915_READ(GEN6_PMIIR);
3ff60f89
OM		 1854 if (pm_iir)
1855 I915_WRITE(GEN6_PMIIR, pm_iir);
1856
1857 iir = I915_READ(VLV_IIR);
1858 if (iir) {
1859 /* Consume port before clearing IIR or we'll miss events */
1860 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1861 i9xx_hpd_irq_handler(dev);
1862 I915_WRITE(VLV_IIR, iir);
1863 }
7e231dbe
JB		 1864
1865 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1866 goto out;
1867
1868 ret = IRQ_HANDLED;
1869
3ff60f89
OM		 1870 if (gt_iir)
1871 snb_gt_irq_handler(dev, dev_priv, gt_iir);
60611c13 1872 if (pm_iir)
d0ecd7e2 1873 gen6_rps_irq_handler(dev_priv, pm_iir);
3ff60f89
OM		 1874 /* Call regardless, as some status bits might not be
1875 * signalled in iir */
1876 valleyview_pipestat_irq_handler(dev, iir);
7e231dbe
JB		 1877 }
1878
1879out:
1880 return ret;
1881}
1882
43f328d7
VS		 1883static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1884{
45a83f84 1885 struct drm_device *dev = arg;
43f328d7
VS		 1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 u32 master_ctl, iir;
1888 irqreturn_t ret = IRQ_NONE;
43f328d7 1889
2dd2a883
ID		 1890 if (!intel_irqs_enabled(dev_priv))
1891 return IRQ_NONE;
1892
8e5fd599
VS		 1893 for (;;) {
1894 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1895 iir = I915_READ(VLV_IIR);
43f328d7 1896
8e5fd599
VS		 1897 if (master_ctl == 0 && iir == 0)
1898 break;
43f328d7 1899
27b6c122
OM		 1900 ret = IRQ_HANDLED;
1901
8e5fd599 1902 I915_WRITE(GEN8_MASTER_IRQ, 0);
43f328d7 1903
27b6c122 1904 /* Find, clear, then process each source of interrupt */
43f328d7 1905
27b6c122
OM		 1906 if (iir) {
1907 /* Consume port before clearing IIR or we'll miss events */
1908 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1909 i9xx_hpd_irq_handler(dev);
1910 I915_WRITE(VLV_IIR, iir);
1911 }
43f328d7 1912
27b6c122 1913 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
43f328d7 1914
27b6c122
OM		 1915 /* Call regardless, as some status bits might not be
1916 * signalled in iir */
1917 valleyview_pipestat_irq_handler(dev, iir);
43f328d7 1918
8e5fd599
VS		 1919 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1920 POSTING_READ(GEN8_MASTER_IRQ);
8e5fd599 1921 }
3278f67f 1922
43f328d7
VS		 1923 return ret;
1924}
1925
23e81d69 1926static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806 1927{
2d1013dd 1928 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 1929 int pipe;
b543fb04 1930 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
13cf5504
DA		 1931 u32 dig_hotplug_reg;
1932
1933 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1934 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
776ad806 1935
13cf5504 1936 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
91d131d2 1937
cfc33bf7
VS		 1938 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1939 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1940 SDE_AUDIO_POWER_SHIFT);
776ad806 1941 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1942 port_name(port));
1943 }
776ad806 1944
ce99c256
DV		 1945 if (pch_iir & SDE_AUX_MASK)
1946 dp_aux_irq_handler(dev);
1947
776ad806 1948 if (pch_iir & SDE_GMBUS)
515ac2bb 1949 gmbus_irq_handler(dev);
776ad806
JB		 1950
1951 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1952 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1953
1954 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1955 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1956
1957 if (pch_iir & SDE_POISON)
1958 DRM_ERROR("PCH poison interrupt\n");
1959
9db4a9c7 1960 if (pch_iir & SDE_FDI_MASK)
055e393f 1961 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 1962 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1963 pipe_name(pipe),
1964 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1965
1966 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1967 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1968
1969 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1970 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1971
776ad806 1972 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1f7247c0 1973 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
8664281b
PZ		 1974
1975 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1f7247c0 1976 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
8664281b
PZ		 1977}
1978
1979static void ivb_err_int_handler(struct drm_device *dev)
1980{
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982 u32 err_int = I915_READ(GEN7_ERR_INT);
5a69b89f 1983 enum pipe pipe;
8664281b 1984
de032bf4
PZ		 1985 if (err_int & ERR_INT_POISON)
1986 DRM_ERROR("Poison interrupt\n");
1987
055e393f 1988 for_each_pipe(dev_priv, pipe) {
1f7247c0
DV		 1989 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1990 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
8bf1e9f1 1991
5a69b89f
DV		 1992 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1993 if (IS_IVYBRIDGE(dev))
277de95e 1994 ivb_pipe_crc_irq_handler(dev, pipe);
5a69b89f 1995 else
277de95e 1996 hsw_pipe_crc_irq_handler(dev, pipe);
5a69b89f
DV		 1997 }
1998 }
8bf1e9f1 1999
8664281b
PZ		 2000 I915_WRITE(GEN7_ERR_INT, err_int);
2001}
2002
2003static void cpt_serr_int_handler(struct drm_device *dev)
2004{
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006 u32 serr_int = I915_READ(SERR_INT);
2007
de032bf4
PZ		 2008 if (serr_int & SERR_INT_POISON)
2009 DRM_ERROR("PCH poison interrupt\n");
2010
8664281b 2011 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1f7247c0 2012 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
8664281b
PZ		 2013
2014 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1f7247c0 2015 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
8664281b
PZ		 2016
2017 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1f7247c0 2018 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
8664281b
PZ		 2019
2020 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 2021}
2022
23e81d69
AJ		 2023static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2024{
2d1013dd 2025 struct drm_i915_private *dev_priv = dev->dev_private;
23e81d69 2026 int pipe;
b543fb04 2027 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
13cf5504
DA		 2028 u32 dig_hotplug_reg;
2029
2030 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2031 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
23e81d69 2032
13cf5504 2033 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
91d131d2 2034
cfc33bf7
VS		 2035 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2036 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2037 SDE_AUDIO_POWER_SHIFT_CPT);
2038 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2039 port_name(port));
2040 }
23e81d69
AJ		 2041
2042 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 2043 dp_aux_irq_handler(dev);
23e81d69
AJ		 2044
2045 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 2046 gmbus_irq_handler(dev);
23e81d69
AJ		 2047
2048 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2049 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2050
2051 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2052 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2053
2054 if (pch_iir & SDE_FDI_MASK_CPT)
055e393f 2055 for_each_pipe(dev_priv, pipe)
23e81d69
AJ		 2056 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2057 pipe_name(pipe),
2058 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 2059
2060 if (pch_iir & SDE_ERROR_CPT)
2061 cpt_serr_int_handler(dev);
23e81d69
AJ		 2062}
2063
c008bc6e
PZ		 2064static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2065{
2066 struct drm_i915_private *dev_priv = dev->dev_private;
40da17c2 2067 enum pipe pipe;
c008bc6e
PZ		 2068
2069 if (de_iir & DE_AUX_CHANNEL_A)
2070 dp_aux_irq_handler(dev);
2071
2072 if (de_iir & DE_GSE)
2073 intel_opregion_asle_intr(dev);
2074
c008bc6e
PZ		 2075 if (de_iir & DE_POISON)
2076 DRM_ERROR("Poison interrupt\n");
2077
055e393f 2078 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 2079 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2080 intel_pipe_handle_vblank(dev, pipe))
2081 intel_check_page_flip(dev, pipe);
5b3a856b 2082
40da17c2 2083 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1f7247c0 2084 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
5b3a856b 2085
40da17c2
DV		 2086 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2087 i9xx_pipe_crc_irq_handler(dev, pipe);
c008bc6e 2088
40da17c2
DV		 2089 /* plane/pipes map 1:1 on ilk+ */
2090 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2091 intel_prepare_page_flip(dev, pipe);
2092 intel_finish_page_flip_plane(dev, pipe);
2093 }
c008bc6e
PZ		 2094 }
2095
2096 /* check event from PCH */
2097 if (de_iir & DE_PCH_EVENT) {
2098 u32 pch_iir = I915_READ(SDEIIR);
2099
2100 if (HAS_PCH_CPT(dev))
2101 cpt_irq_handler(dev, pch_iir);
2102 else
2103 ibx_irq_handler(dev, pch_iir);
2104
2105 /* should clear PCH hotplug event before clear CPU irq */
2106 I915_WRITE(SDEIIR, pch_iir);
2107 }
2108
2109 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2110 ironlake_rps_change_irq_handler(dev);
2111}
2112
9719fb98
PZ		 2113static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2114{
2115 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 2116 enum pipe pipe;
9719fb98
PZ		 2117
2118 if (de_iir & DE_ERR_INT_IVB)
2119 ivb_err_int_handler(dev);
2120
2121 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2122 dp_aux_irq_handler(dev);
2123
2124 if (de_iir & DE_GSE_IVB)
2125 intel_opregion_asle_intr(dev);
2126
055e393f 2127 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 2128 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2129 intel_pipe_handle_vblank(dev, pipe))
2130 intel_check_page_flip(dev, pipe);
40da17c2
DV		 2131
2132 /* plane/pipes map 1:1 on ilk+ */
07d27e20
DL		 2133 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2134 intel_prepare_page_flip(dev, pipe);
2135 intel_finish_page_flip_plane(dev, pipe);
9719fb98
PZ		 2136 }
2137 }
2138
2139 /* check event from PCH */
2140 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2141 u32 pch_iir = I915_READ(SDEIIR);
2142
2143 cpt_irq_handler(dev, pch_iir);
2144
2145 /* clear PCH hotplug event before clear CPU irq */
2146 I915_WRITE(SDEIIR, pch_iir);
2147 }
2148}
2149
72c90f62
OM		 2150/*
2151 * To handle irqs with the minimum potential races with fresh interrupts, we:
2152 * 1 - Disable Master Interrupt Control.
2153 * 2 - Find the source(s) of the interrupt.
2154 * 3 - Clear the Interrupt Identity bits (IIR).
2155 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2156 * 5 - Re-enable Master Interrupt Control.
2157 */
f1af8fc1 2158static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0 2159{
45a83f84 2160 struct drm_device *dev = arg;
2d1013dd 2161 struct drm_i915_private *dev_priv = dev->dev_private;
f1af8fc1 2162 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 2163 irqreturn_t ret = IRQ_NONE;
b1f14ad0 2164
2dd2a883
ID		 2165 if (!intel_irqs_enabled(dev_priv))
2166 return IRQ_NONE;
2167
8664281b
PZ		 2168 /* We get interrupts on unclaimed registers, so check for this before we
2169 * do any I915_{READ,WRITE}. */
907b28c5 2170 intel_uncore_check_errors(dev);
8664281b 2171
b1f14ad0
JB		 2172 /* disable master interrupt before clearing iir */
2173 de_ier = I915_READ(DEIER);
2174 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 2175 POSTING_READ(DEIER);
b1f14ad0 2176
44498aea
PZ		 2177 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2178 * interrupts will will be stored on its back queue, and then we'll be
2179 * able to process them after we restore SDEIER (as soon as we restore
2180 * it, we'll get an interrupt if SDEIIR still has something to process
2181 * due to its back queue). */
ab5c608b
BW		 2182 if (!HAS_PCH_NOP(dev)) {
2183 sde_ier = I915_READ(SDEIER);
2184 I915_WRITE(SDEIER, 0);
2185 POSTING_READ(SDEIER);
2186 }
44498aea 2187
72c90f62
OM		 2188 /* Find, clear, then process each source of interrupt */
2189
b1f14ad0 2190 gt_iir = I915_READ(GTIIR);
0e43406b 2191 if (gt_iir) {
72c90f62
OM		 2192 I915_WRITE(GTIIR, gt_iir);
2193 ret = IRQ_HANDLED;
d8fc8a47 2194 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 2195 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 2196 else
2197 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 2198 }
2199
0e43406b
CW		 2200 de_iir = I915_READ(DEIIR);
2201 if (de_iir) {
72c90f62
OM		 2202 I915_WRITE(DEIIR, de_iir);
2203 ret = IRQ_HANDLED;
f1af8fc1
PZ		 2204 if (INTEL_INFO(dev)->gen >= 7)
2205 ivb_display_irq_handler(dev, de_iir);
2206 else
2207 ilk_display_irq_handler(dev, de_iir);
b1f14ad0
JB		 2208 }
2209
f1af8fc1
PZ		 2210 if (INTEL_INFO(dev)->gen >= 6) {
2211 u32 pm_iir = I915_READ(GEN6_PMIIR);
2212 if (pm_iir) {
f1af8fc1
PZ		 2213 I915_WRITE(GEN6_PMIIR, pm_iir);
2214 ret = IRQ_HANDLED;
72c90f62 2215 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1 2216 }
0e43406b 2217 }
b1f14ad0 2218
b1f14ad0
JB		 2219 I915_WRITE(DEIER, de_ier);
2220 POSTING_READ(DEIER);
ab5c608b
BW		 2221 if (!HAS_PCH_NOP(dev)) {
2222 I915_WRITE(SDEIER, sde_ier);
2223 POSTING_READ(SDEIER);
2224 }
b1f14ad0
JB		 2225
2226 return ret;
2227}
2228
abd58f01
BW		 2229static irqreturn_t gen8_irq_handler(int irq, void *arg)
2230{
2231 struct drm_device *dev = arg;
2232 struct drm_i915_private *dev_priv = dev->dev_private;
2233 u32 master_ctl;
2234 irqreturn_t ret = IRQ_NONE;
2235 uint32_t tmp = 0;
c42664cc 2236 enum pipe pipe;
88e04703
JB		 2237 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2238
2dd2a883
ID		 2239 if (!intel_irqs_enabled(dev_priv))
2240 return IRQ_NONE;
2241
88e04703
JB		 2242 if (IS_GEN9(dev))
2243 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2244 GEN9_AUX_CHANNEL_D;
abd58f01 2245
abd58f01
BW		 2246 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2247 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2248 if (!master_ctl)
2249 return IRQ_NONE;
2250
2251 I915_WRITE(GEN8_MASTER_IRQ, 0);
2252 POSTING_READ(GEN8_MASTER_IRQ);
2253
38cc46d7
OM		 2254 /* Find, clear, then process each source of interrupt */
2255
abd58f01
BW		 2256 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2257
2258 if (master_ctl & GEN8_DE_MISC_IRQ) {
2259 tmp = I915_READ(GEN8_DE_MISC_IIR);
abd58f01
BW		 2260 if (tmp) {
2261 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2262 ret = IRQ_HANDLED;
38cc46d7
OM		 2263 if (tmp & GEN8_DE_MISC_GSE)
2264 intel_opregion_asle_intr(dev);
2265 else
2266 DRM_ERROR("Unexpected DE Misc interrupt\n");
abd58f01 2267 }
38cc46d7
OM		 2268 else
2269 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
abd58f01
BW		 2270 }
2271
6d766f02
DV		 2272 if (master_ctl & GEN8_DE_PORT_IRQ) {
2273 tmp = I915_READ(GEN8_DE_PORT_IIR);
6d766f02
DV		 2274 if (tmp) {
2275 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2276 ret = IRQ_HANDLED;
88e04703
JB		 2277
2278 if (tmp & aux_mask)
38cc46d7
OM		 2279 dp_aux_irq_handler(dev);
2280 else
2281 DRM_ERROR("Unexpected DE Port interrupt\n");
6d766f02 2282 }
38cc46d7
OM		 2283 else
2284 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
6d766f02
DV		 2285 }
2286
055e393f 2287 for_each_pipe(dev_priv, pipe) {
770de83d 2288 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
abd58f01 2289
c42664cc
DV		 2290 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2291 continue;
abd58f01 2292
c42664cc 2293 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
c42664cc
DV		 2294 if (pipe_iir) {
2295 ret = IRQ_HANDLED;
2296 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
770de83d 2297
d6bbafa1
CW		 2298 if (pipe_iir & GEN8_PIPE_VBLANK &&
2299 intel_pipe_handle_vblank(dev, pipe))
2300 intel_check_page_flip(dev, pipe);
38cc46d7 2301
770de83d
DL		 2302 if (IS_GEN9(dev))
2303 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2304 else
2305 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2306
2307 if (flip_done) {
38cc46d7
OM		 2308 intel_prepare_page_flip(dev, pipe);
2309 intel_finish_page_flip_plane(dev, pipe);
2310 }
2311
2312 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2313 hsw_pipe_crc_irq_handler(dev, pipe);
2314
1f7247c0
DV		 2315 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2316 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2317 pipe);
38cc46d7 2318
770de83d
DL		 2319
2320 if (IS_GEN9(dev))
2321 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2322 else
2323 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2324
2325 if (fault_errors)
38cc46d7
OM		 2326 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2327 pipe_name(pipe),
2328 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
c42664cc 2329 } else
abd58f01
BW		 2330 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2331 }
2332
92d03a80
DV		 2333 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2334 /*
2335 * FIXME(BDW): Assume for now that the new interrupt handling
2336 * scheme also closed the SDE interrupt handling race we've seen
2337 * on older pch-split platforms. But this needs testing.
2338 */
2339 u32 pch_iir = I915_READ(SDEIIR);
92d03a80
DV		 2340 if (pch_iir) {
2341 I915_WRITE(SDEIIR, pch_iir);
2342 ret = IRQ_HANDLED;
38cc46d7
OM		 2343 cpt_irq_handler(dev, pch_iir);
2344 } else
2345 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2346
92d03a80
DV		 2347 }
2348
abd58f01
BW		 2349 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2350 POSTING_READ(GEN8_MASTER_IRQ);
2351
2352 return ret;
2353}
2354
17e1df07
DV		 2355static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2356 bool reset_completed)
2357{
a4872ba6 2358 struct intel_engine_cs *ring;
17e1df07
DV		 2359 int i;
2360
2361 /*
2362 * Notify all waiters for GPU completion events that reset state has
2363 * been changed, and that they need to restart their wait after
2364 * checking for potential errors (and bail out to drop locks if there is
2365 * a gpu reset pending so that i915_error_work_func can acquire them).
2366 */
2367
2368 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2369 for_each_ring(ring, dev_priv, i)
2370 wake_up_all(&ring->irq_queue);
2371
2372 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2373 wake_up_all(&dev_priv->pending_flip_queue);
2374
2375 /*
2376 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2377 * reset state is cleared.
2378 */
2379 if (reset_completed)
2380 wake_up_all(&dev_priv->gpu_error.reset_queue);
2381}
2382
8a905236 2383/**
b8d24a06 2384 * i915_reset_and_wakeup - do process context error handling work
8a905236
JB		 2385 *
2386 * Fire an error uevent so userspace can see that a hang or error
2387 * was detected.
2388 */
b8d24a06 2389static void i915_reset_and_wakeup(struct drm_device *dev)
8a905236 2390{
b8d24a06
MK		 2391 struct drm_i915_private *dev_priv = to_i915(dev);
2392 struct i915_gpu_error *error = &dev_priv->gpu_error;
cce723ed
BW		 2393 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2394 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2395 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 2396 int ret;
8a905236 2397
5bdebb18 2398 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
f316a42c 2399
7db0ba24
DV		 2400 /*
2401 * Note that there's only one work item which does gpu resets, so we
2402 * need not worry about concurrent gpu resets potentially incrementing
2403 * error->reset_counter twice. We only need to take care of another
2404 * racing irq/hangcheck declaring the gpu dead for a second time. A
2405 * quick check for that is good enough: schedule_work ensures the
2406 * correct ordering between hang detection and this work item, and since
2407 * the reset in-progress bit is only ever set by code outside of this
2408 * work we don't need to worry about any other races.
2409 */
2410 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 2411 DRM_DEBUG_DRIVER("resetting chip\n");
5bdebb18 2412 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
7db0ba24 2413 reset_event);
1f83fee0 2414
f454c694
ID		 2415 /*
2416 * In most cases it's guaranteed that we get here with an RPM
2417 * reference held, for example because there is a pending GPU
2418 * request that won't finish until the reset is done. This
2419 * isn't the case at least when we get here by doing a
2420 * simulated reset via debugs, so get an RPM reference.
2421 */
2422 intel_runtime_pm_get(dev_priv);
7514747d
VS		 2423
2424 intel_prepare_reset(dev);
2425
17e1df07
DV		 2426 /*
2427 * All state reset _must_ be completed before we update the
2428 * reset counter, for otherwise waiters might miss the reset
2429 * pending state and not properly drop locks, resulting in
2430 * deadlocks with the reset work.
2431 */
f69061be
DV		 2432 ret = i915_reset(dev);
2433
7514747d 2434 intel_finish_reset(dev);
17e1df07 2435
f454c694
ID		 2436 intel_runtime_pm_put(dev_priv);
2437
f69061be
DV		 2438 if (ret == 0) {
2439 /*
2440 * After all the gem state is reset, increment the reset
2441 * counter and wake up everyone waiting for the reset to
2442 * complete.
2443 *
2444 * Since unlock operations are a one-sided barrier only,
2445 * we need to insert a barrier here to order any seqno
2446 * updates before
2447 * the counter increment.
2448 */
4e857c58 2449 smp_mb__before_atomic();
f69061be
DV		 2450 atomic_inc(&dev_priv->gpu_error.reset_counter);
2451
5bdebb18 2452 kobject_uevent_env(&dev->primary->kdev->kobj,
f69061be 2453 KOBJ_CHANGE, reset_done_event);
1f83fee0 2454 } else {
2ac0f450 2455 atomic_set_mask(I915_WEDGED, &error->reset_counter);
f316a42c 2456 }
1f83fee0 2457
17e1df07
DV		 2458 /*
2459 * Note: The wake_up also serves as a memory barrier so that
2460 * waiters see the update value of the reset counter atomic_t.
2461 */
2462 i915_error_wake_up(dev_priv, true);
f316a42c 2463 }
8a905236
JB		 2464}
2465
35aed2e6 2466static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2467{
2468 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2469 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2470 u32 eir = I915_READ(EIR);
050ee91f 2471 int pipe, i;
8a905236 2472
35aed2e6
CW		 2473 if (!eir)
2474 return;
8a905236 2475
a70491cc 2476 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2477
bd9854f9
BW		 2478 i915_get_extra_instdone(dev, instdone);
2479
8a905236
JB		 2480 if (IS_G4X(dev)) {
2481 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2482 u32 ipeir = I915_READ(IPEIR_I965);
2483
a70491cc
JP		 2484 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2485 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2486 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2487 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2488 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2489 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2490 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2491 POSTING_READ(IPEIR_I965);
8a905236
JB		 2492 }
2493 if (eir & GM45_ERROR_PAGE_TABLE) {
2494 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2495 pr_err("page table error\n");
2496 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2497 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2498 POSTING_READ(PGTBL_ER);
8a905236
JB		 2499 }
2500 }
2501
a6c45cf0 2502 if (!IS_GEN2(dev)) {
8a905236
JB		 2503 if (eir & I915_ERROR_PAGE_TABLE) {
2504 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2505 pr_err("page table error\n");
2506 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2507 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2508 POSTING_READ(PGTBL_ER);
8a905236
JB		 2509 }
2510 }
2511
2512 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2513 pr_err("memory refresh error:\n");
055e393f 2514 for_each_pipe(dev_priv, pipe)
a70491cc 2515 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2516 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2517 /* pipestat has already been acked */
2518 }
2519 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2520 pr_err("instruction error\n");
2521 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2522 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2523 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2524 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2525 u32 ipeir = I915_READ(IPEIR);
2526
a70491cc
JP		 2527 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2528 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2529 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2530 I915_WRITE(IPEIR, ipeir);
3143a2bf 2531 POSTING_READ(IPEIR);
8a905236
JB		 2532 } else {
2533 u32 ipeir = I915_READ(IPEIR_I965);
2534
a70491cc
JP		 2535 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2536 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2537 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2538 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2539 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2540 POSTING_READ(IPEIR_I965);
8a905236
JB		 2541 }
2542 }
2543
2544 I915_WRITE(EIR, eir);
3143a2bf 2545 POSTING_READ(EIR);
8a905236
JB		 2546 eir = I915_READ(EIR);
2547 if (eir) {
2548 /*
2549 * some errors might have become stuck,
2550 * mask them.
2551 */
2552 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2553 I915_WRITE(EMR, I915_READ(EMR) | eir);
2554 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2555 }
35aed2e6
CW		 2556}
2557
2558/**
b8d24a06 2559 * i915_handle_error - handle a gpu error
35aed2e6
CW		 2560 * @dev: drm device
2561 *
b8d24a06 2562 * Do some basic checking of regsiter state at error time and
35aed2e6
CW		 2563 * dump it to the syslog. Also call i915_capture_error_state() to make
2564 * sure we get a record and make it available in debugfs. Fire a uevent
2565 * so userspace knows something bad happened (should trigger collection
2566 * of a ring dump etc.).
2567 */
58174462
MK		 2568void i915_handle_error(struct drm_device *dev, bool wedged,
2569 const char *fmt, ...)
35aed2e6
CW		 2570{
2571 struct drm_i915_private *dev_priv = dev->dev_private;
58174462
MK		 2572 va_list args;
2573 char error_msg[80];
35aed2e6 2574
58174462
MK		 2575 va_start(args, fmt);
2576 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2577 va_end(args);
2578
2579 i915_capture_error_state(dev, wedged, error_msg);
35aed2e6 2580 i915_report_and_clear_eir(dev);
8a905236 2581
ba1234d1 2582 if (wedged) {
f69061be
DV		 2583 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2584 &dev_priv->gpu_error.reset_counter);
ba1234d1 2585
11ed50ec 2586 /*
b8d24a06
MK		 2587 * Wakeup waiting processes so that the reset function
2588 * i915_reset_and_wakeup doesn't deadlock trying to grab
2589 * various locks. By bumping the reset counter first, the woken
17e1df07
DV		 2590 * processes will see a reset in progress and back off,
2591 * releasing their locks and then wait for the reset completion.
2592 * We must do this for _all_ gpu waiters that might hold locks
2593 * that the reset work needs to acquire.
2594 *
2595 * Note: The wake_up serves as the required memory barrier to
2596 * ensure that the waiters see the updated value of the reset
2597 * counter atomic_t.
11ed50ec 2598 */
17e1df07 2599 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 2600 }
2601
b8d24a06 2602 i915_reset_and_wakeup(dev);
8a905236
JB		 2603}
2604
42f52ef8
KP		 2605/* Called from drm generic code, passed 'crtc' which
2606 * we use as a pipe index
2607 */
f71d4af4 2608static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2609{
2d1013dd 2610 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2611 unsigned long irqflags;
71e0ffa5 2612
1ec14ad3 2613 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2614 if (INTEL_INFO(dev)->gen >= 4)
7c463586 2615 i915_enable_pipestat(dev_priv, pipe,
755e9019 2616 PIPE_START_VBLANK_INTERRUPT_STATUS);
e9d21d7f 2617 else
7c463586 2618 i915_enable_pipestat(dev_priv, pipe,
755e9019 2619 PIPE_VBLANK_INTERRUPT_STATUS);
1ec14ad3 2620 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2621
0a3e67a4
JB		 2622 return 0;
2623}
2624
f71d4af4 2625static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2626{
2d1013dd 2627 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2628 unsigned long irqflags;
b518421f 2629 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2630 DE_PIPE_VBLANK(pipe);
f796cf8f 2631
f796cf8f 2632 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2633 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2634 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2635
2636 return 0;
2637}
2638
7e231dbe
JB		 2639static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2640{
2d1013dd 2641 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2642 unsigned long irqflags;
7e231dbe 2643
7e231dbe 2644 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2645 i915_enable_pipestat(dev_priv, pipe,
755e9019 2646 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2647 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2648
2649 return 0;
2650}
2651
abd58f01
BW		 2652static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2653{
2654 struct drm_i915_private *dev_priv = dev->dev_private;
2655 unsigned long irqflags;
abd58f01 2656
abd58f01 2657 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2658 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2659 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2660 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2661 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2662 return 0;
2663}
2664
42f52ef8
KP		 2665/* Called from drm generic code, passed 'crtc' which
2666 * we use as a pipe index
2667 */
f71d4af4 2668static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2669{
2d1013dd 2670 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2671 unsigned long irqflags;
0a3e67a4 2672
1ec14ad3 2673 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2674 i915_disable_pipestat(dev_priv, pipe,
755e9019
ID		 2675 PIPE_VBLANK_INTERRUPT_STATUS |
2676 PIPE_START_VBLANK_INTERRUPT_STATUS);
f796cf8f
JB		 2677 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2678}
2679
f71d4af4 2680static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2681{
2d1013dd 2682 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2683 unsigned long irqflags;
b518421f 2684 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2685 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2686
2687 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2688 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2689 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2690}
2691
7e231dbe
JB		 2692static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2693{
2d1013dd 2694 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2695 unsigned long irqflags;
7e231dbe
JB		 2696
2697 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2698 i915_disable_pipestat(dev_priv, pipe,
755e9019 2699 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2700 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2701}
2702
abd58f01
BW		 2703static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2704{
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 unsigned long irqflags;
abd58f01 2707
abd58f01 2708 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2709 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2710 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2711 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2712 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2713}
2714
44cdd6d2
JH		 2715static struct drm_i915_gem_request *
2716ring_last_request(struct intel_engine_cs *ring)
852835f3 2717{
893eead0 2718 return list_entry(ring->request_list.prev,
44cdd6d2 2719 struct drm_i915_gem_request, list);
893eead0
CW		 2720}
2721
9107e9d2 2722static bool
44cdd6d2 2723ring_idle(struct intel_engine_cs *ring)
9107e9d2
CW		 2724{
2725 return (list_empty(&ring->request_list) ||
1b5a433a 2726 i915_gem_request_completed(ring_last_request(ring), false));
f65d9421
BG		 2727}
2728
a028c4b0
DV		 2729static bool
2730ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2731{
2732 if (INTEL_INFO(dev)->gen >= 8) {
a6cdb93a 2733 return (ipehr >> 23) == 0x1c;
a028c4b0
DV		 2734 } else {
2735 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2736 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2737 MI_SEMAPHORE_REGISTER);
2738 }
2739}
2740
a4872ba6 2741static struct intel_engine_cs *
a6cdb93a 2742semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
921d42ea
DV		 2743{
2744 struct drm_i915_private *dev_priv = ring->dev->dev_private;
a4872ba6 2745 struct intel_engine_cs *signaller;
921d42ea
DV		 2746 int i;
2747
2748 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
a6cdb93a
RV		 2749 for_each_ring(signaller, dev_priv, i) {
2750 if (ring == signaller)
2751 continue;
2752
2753 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2754 return signaller;
2755 }
921d42ea
DV		 2756 } else {
2757 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2758
2759 for_each_ring(signaller, dev_priv, i) {
2760 if(ring == signaller)
2761 continue;
2762
ebc348b2 2763 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
921d42ea
DV		 2764 return signaller;
2765 }
2766 }
2767
a6cdb93a
RV		 2768 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2769 ring->id, ipehr, offset);
921d42ea
DV		 2770
2771 return NULL;
2772}
2773
a4872ba6
OM		 2774static struct intel_engine_cs *
2775semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
a24a11e6
CW		 2776{
2777 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88fe429d 2778 u32 cmd, ipehr, head;
a6cdb93a
RV		 2779 u64 offset = 0;
2780 int i, backwards;
a24a11e6
CW		 2781
2782 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
a028c4b0 2783 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
6274f212 2784 return NULL;
a24a11e6 2785
88fe429d
DV		 2786 /*
2787 * HEAD is likely pointing to the dword after the actual command,
2788 * so scan backwards until we find the MBOX. But limit it to just 3
a6cdb93a
RV		 2789 * or 4 dwords depending on the semaphore wait command size.
2790 * Note that we don't care about ACTHD here since that might
88fe429d
DV		 2791 * point at at batch, and semaphores are always emitted into the
2792 * ringbuffer itself.
a24a11e6 2793 */
88fe429d 2794 head = I915_READ_HEAD(ring) & HEAD_ADDR;
a6cdb93a 2795 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
88fe429d 2796
a6cdb93a 2797 for (i = backwards; i; --i) {
88fe429d
DV		 2798 /*
2799 * Be paranoid and presume the hw has gone off into the wild -
2800 * our ring is smaller than what the hardware (and hence
2801 * HEAD_ADDR) allows. Also handles wrap-around.
2802 */
ee1b1e5e 2803 head &= ring->buffer->size - 1;
88fe429d
DV		 2804
2805 /* This here seems to blow up */
ee1b1e5e 2806 cmd = ioread32(ring->buffer->virtual_start + head);
a24a11e6
CW		 2807 if (cmd == ipehr)
2808 break;
2809
88fe429d
DV		 2810 head -= 4;
2811 }
a24a11e6 2812
88fe429d
DV		 2813 if (!i)
2814 return NULL;
a24a11e6 2815
ee1b1e5e 2816 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
a6cdb93a
RV		 2817 if (INTEL_INFO(ring->dev)->gen >= 8) {
2818 offset = ioread32(ring->buffer->virtual_start + head + 12);
2819 offset <<= 32;
2820 offset = ioread32(ring->buffer->virtual_start + head + 8);
2821 }
2822 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
a24a11e6
CW		 2823}
2824
a4872ba6 2825static int semaphore_passed(struct intel_engine_cs *ring)
6274f212
CW		 2826{
2827 struct drm_i915_private *dev_priv = ring->dev->dev_private;
a4872ba6 2828 struct intel_engine_cs *signaller;
a0d036b0 2829 u32 seqno;
6274f212 2830
4be17381 2831 ring->hangcheck.deadlock++;
6274f212
CW		 2832
2833 signaller = semaphore_waits_for(ring, &seqno);
4be17381
CW		 2834 if (signaller == NULL)
2835 return -1;
2836
2837 /* Prevent pathological recursion due to driver bugs */
2838 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
6274f212
CW		 2839 return -1;
2840
4be17381
CW		 2841 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2842 return 1;
2843
a0d036b0
CW		 2844 /* cursory check for an unkickable deadlock */
2845 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2846 semaphore_passed(signaller) < 0)
4be17381
CW		 2847 return -1;
2848
2849 return 0;
6274f212
CW		 2850}
2851
2852static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2853{
a4872ba6 2854 struct intel_engine_cs *ring;
6274f212
CW		 2855 int i;
2856
2857 for_each_ring(ring, dev_priv, i)
4be17381 2858 ring->hangcheck.deadlock = 0;
6274f212
CW		 2859}
2860
ad8beaea 2861static enum intel_ring_hangcheck_action
a4872ba6 2862ring_stuck(struct intel_engine_cs *ring, u64 acthd)
1ec14ad3
CW		 2863{
2864 struct drm_device *dev = ring->dev;
2865 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2866 u32 tmp;
2867
f260fe7b
MK		 2868 if (acthd != ring->hangcheck.acthd) {
2869 if (acthd > ring->hangcheck.max_acthd) {
2870 ring->hangcheck.max_acthd = acthd;
2871 return HANGCHECK_ACTIVE;
2872 }
2873
2874 return HANGCHECK_ACTIVE_LOOP;
2875 }
6274f212 2876
9107e9d2 2877 if (IS_GEN2(dev))
f2f4d82f 2878 return HANGCHECK_HUNG;
9107e9d2
CW		 2879
2880 /* Is the chip hanging on a WAIT_FOR_EVENT?
2881 * If so we can simply poke the RB_WAIT bit
2882 * and break the hang. This should work on
2883 * all but the second generation chipsets.
2884 */
2885 tmp = I915_READ_CTL(ring);
1ec14ad3 2886 if (tmp & RING_WAIT) {
58174462
MK		 2887 i915_handle_error(dev, false,
2888 "Kicking stuck wait on %s",
2889 ring->name);
1ec14ad3 2890 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2891 return HANGCHECK_KICK;
6274f212
CW		 2892 }
2893
2894 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2895 switch (semaphore_passed(ring)) {
2896 default:
f2f4d82f 2897 return HANGCHECK_HUNG;
6274f212 2898 case 1:
58174462
MK		 2899 i915_handle_error(dev, false,
2900 "Kicking stuck semaphore on %s",
2901 ring->name);
6274f212 2902 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2903 return HANGCHECK_KICK;
6274f212 2904 case 0:
f2f4d82f 2905 return HANGCHECK_WAIT;
6274f212 2906 }
9107e9d2 2907 }
ed5cbb03 2908
f2f4d82f 2909 return HANGCHECK_HUNG;
ed5cbb03
MK		 2910}
2911
737b1506 2912/*
f65d9421 2913 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2914 * batchbuffers in a long time. We keep track per ring seqno progress and
2915 * if there are no progress, hangcheck score for that ring is increased.
2916 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2917 * we kick the ring. If we see no progress on three subsequent calls
2918 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 2919 */
737b1506 2920static void i915_hangcheck_elapsed(struct work_struct *work)
f65d9421 2921{
737b1506
CW		 2922 struct drm_i915_private *dev_priv =
2923 container_of(work, typeof(*dev_priv),
2924 gpu_error.hangcheck_work.work);
2925 struct drm_device *dev = dev_priv->dev;
a4872ba6 2926 struct intel_engine_cs *ring;
b4519513 2927 int i;
05407ff8 2928 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2929 bool stuck[I915_NUM_RINGS] = { 0 };
2930#define BUSY 1
2931#define KICK 5
2932#define HUNG 20
893eead0 2933
d330a953 2934 if (!i915.enable_hangcheck)
3e0dc6b0
BW		 2935 return;
2936
b4519513 2937 for_each_ring(ring, dev_priv, i) {
50877445
CW		 2938 u64 acthd;
2939 u32 seqno;
9107e9d2 2940 bool busy = true;
05407ff8 2941
6274f212
CW		 2942 semaphore_clear_deadlocks(dev_priv);
2943
05407ff8
MK		 2944 seqno = ring->get_seqno(ring, false);
2945 acthd = intel_ring_get_active_head(ring);
b4519513 2946
9107e9d2 2947 if (ring->hangcheck.seqno == seqno) {
44cdd6d2 2948 if (ring_idle(ring)) {
da661464
MK		 2949 ring->hangcheck.action = HANGCHECK_IDLE;
2950
9107e9d2
CW		 2951 if (waitqueue_active(&ring->irq_queue)) {
2952 /* Issue a wake-up to catch stuck h/w. */
094f9a54 2953 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
f4adcd24
DV		 2954 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2955 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2956 ring->name);
2957 else
2958 DRM_INFO("Fake missed irq on %s\n",
2959 ring->name);
094f9a54
CW		 2960 wake_up_all(&ring->irq_queue);
2961 }
2962 /* Safeguard against driver failure */
2963 ring->hangcheck.score += BUSY;
9107e9d2
CW		 2964 } else
2965 busy = false;
05407ff8 2966 } else {
6274f212
CW		 2967 /* We always increment the hangcheck score
2968 * if the ring is busy and still processing
2969 * the same request, so that no single request
2970 * can run indefinitely (such as a chain of
2971 * batches). The only time we do not increment
2972 * the hangcheck score on this ring, if this
2973 * ring is in a legitimate wait for another
2974 * ring. In that case the waiting ring is a
2975 * victim and we want to be sure we catch the
2976 * right culprit. Then every time we do kick
2977 * the ring, add a small increment to the
2978 * score so that we can catch a batch that is
2979 * being repeatedly kicked and so responsible
2980 * for stalling the machine.
2981 */
ad8beaea
MK		 2982 ring->hangcheck.action = ring_stuck(ring,
2983 acthd);
2984
2985 switch (ring->hangcheck.action) {
da661464 2986 case HANGCHECK_IDLE:
f2f4d82f 2987 case HANGCHECK_WAIT:
f2f4d82f 2988 case HANGCHECK_ACTIVE:
f260fe7b
MK		 2989 break;
2990 case HANGCHECK_ACTIVE_LOOP:
ea04cb31 2991 ring->hangcheck.score += BUSY;
6274f212 2992 break;
f2f4d82f 2993 case HANGCHECK_KICK:
ea04cb31 2994 ring->hangcheck.score += KICK;
6274f212 2995 break;
f2f4d82f 2996 case HANGCHECK_HUNG:
ea04cb31 2997 ring->hangcheck.score += HUNG;
6274f212
CW		 2998 stuck[i] = true;
2999 break;
3000 }
05407ff8 3001 }
9107e9d2 3002 } else {
da661464
MK		 3003 ring->hangcheck.action = HANGCHECK_ACTIVE;
3004
9107e9d2
CW		 3005 /* Gradually reduce the count so that we catch DoS
3006 * attempts across multiple batches.
3007 */
3008 if (ring->hangcheck.score > 0)
3009 ring->hangcheck.score--;
f260fe7b
MK		 3010
3011 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
d1e61e7f
CW		 3012 }
3013
05407ff8
MK		 3014 ring->hangcheck.seqno = seqno;
3015 ring->hangcheck.acthd = acthd;
9107e9d2 3016 busy_count += busy;
893eead0 3017 }
b9201c14 3018
92cab734 3019 for_each_ring(ring, dev_priv, i) {
b6b0fac0 3020 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
b8d88d1d
DV		 3021 DRM_INFO("%s on %s\n",
3022 stuck[i] ? "stuck" : "no progress",
3023 ring->name);
a43adf07 3024 rings_hung++;
92cab734
MK		 3025 }
3026 }
3027
05407ff8 3028 if (rings_hung)
58174462 3029 return i915_handle_error(dev, true, "Ring hung");
f65d9421 3030
05407ff8
MK		 3031 if (busy_count)
3032 /* Reset timer case chip hangs without another request
3033 * being added */
10cd45b6
MK		 3034 i915_queue_hangcheck(dev);
3035}
3036
3037void i915_queue_hangcheck(struct drm_device *dev)
3038{
737b1506 3039 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
672e7b7c 3040
d330a953 3041 if (!i915.enable_hangcheck)
10cd45b6
MK		 3042 return;
3043
737b1506
CW		 3044 /* Don't continually defer the hangcheck so that it is always run at
3045 * least once after work has been scheduled on any ring. Otherwise,
3046 * we will ignore a hung ring if a second ring is kept busy.
3047 */
3048
3049 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3050 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 3051}
3052
1c69eb42 3053static void ibx_irq_reset(struct drm_device *dev)
91738a95
PZ		 3054{
3055 struct drm_i915_private *dev_priv = dev->dev_private;
3056
3057 if (HAS_PCH_NOP(dev))
3058 return;
3059
f86f3fb0 3060 GEN5_IRQ_RESET(SDE);
105b122e
PZ		 3061
3062 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3063 I915_WRITE(SERR_INT, 0xffffffff);
622364b6 3064}
105b122e 3065
622364b6
PZ		 3066/*
3067 * SDEIER is also touched by the interrupt handler to work around missed PCH
3068 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3069 * instead we unconditionally enable all PCH interrupt sources here, but then
3070 * only unmask them as needed with SDEIMR.
3071 *
3072 * This function needs to be called before interrupts are enabled.
3073 */
3074static void ibx_irq_pre_postinstall(struct drm_device *dev)
3075{
3076 struct drm_i915_private *dev_priv = dev->dev_private;
3077
3078 if (HAS_PCH_NOP(dev))
3079 return;
3080
3081 WARN_ON(I915_READ(SDEIER) != 0);
91738a95
PZ		 3082 I915_WRITE(SDEIER, 0xffffffff);
3083 POSTING_READ(SDEIER);
3084}
3085
7c4d664e 3086static void gen5_gt_irq_reset(struct drm_device *dev)
d18ea1b5
DV		 3087{
3088 struct drm_i915_private *dev_priv = dev->dev_private;
3089
f86f3fb0 3090 GEN5_IRQ_RESET(GT);
a9d356a6 3091 if (INTEL_INFO(dev)->gen >= 6)
f86f3fb0 3092 GEN5_IRQ_RESET(GEN6_PM);
d18ea1b5
DV		 3093}
3094
1da177e4
LT		 3095/* drm_dma.h hooks
3096*/
be30b29f 3097static void ironlake_irq_reset(struct drm_device *dev)
036a4a7d 3098{
2d1013dd 3099 struct drm_i915_private *dev_priv = dev->dev_private;
036a4a7d 3100
0c841212 3101 I915_WRITE(HWSTAM, 0xffffffff);
bdfcdb63 3102
f86f3fb0 3103 GEN5_IRQ_RESET(DE);
c6d954c1
PZ		 3104 if (IS_GEN7(dev))
3105 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
036a4a7d 3106
7c4d664e 3107 gen5_gt_irq_reset(dev);
c650156a 3108
1c69eb42 3109 ibx_irq_reset(dev);
7d99163d 3110}
c650156a 3111
70591a41
VS		 3112static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3113{
3114 enum pipe pipe;
3115
3116 I915_WRITE(PORT_HOTPLUG_EN, 0);
3117 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3118
3119 for_each_pipe(dev_priv, pipe)
3120 I915_WRITE(PIPESTAT(pipe), 0xffff);
3121
3122 GEN5_IRQ_RESET(VLV_);
3123}
3124
7e231dbe
JB		 3125static void valleyview_irq_preinstall(struct drm_device *dev)
3126{
2d1013dd 3127 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 3128
7e231dbe
JB		 3129 /* VLV magic */
3130 I915_WRITE(VLV_IMR, 0);
3131 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3132 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3133 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3134
7c4d664e 3135 gen5_gt_irq_reset(dev);
7e231dbe 3136
7c4cde39 3137 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
7e231dbe 3138
70591a41 3139 vlv_display_irq_reset(dev_priv);
7e231dbe
JB		 3140}
3141
d6e3cca3
DV		 3142static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3143{
3144 GEN8_IRQ_RESET_NDX(GT, 0);
3145 GEN8_IRQ_RESET_NDX(GT, 1);
3146 GEN8_IRQ_RESET_NDX(GT, 2);
3147 GEN8_IRQ_RESET_NDX(GT, 3);
3148}
3149
823f6b38 3150static void gen8_irq_reset(struct drm_device *dev)
abd58f01
BW		 3151{
3152 struct drm_i915_private *dev_priv = dev->dev_private;
3153 int pipe;
3154
abd58f01
BW		 3155 I915_WRITE(GEN8_MASTER_IRQ, 0);
3156 POSTING_READ(GEN8_MASTER_IRQ);
3157
d6e3cca3 3158 gen8_gt_irq_reset(dev_priv);
abd58f01 3159
055e393f 3160 for_each_pipe(dev_priv, pipe)
f458ebbc
DV		 3161 if (intel_display_power_is_enabled(dev_priv,
3162 POWER_DOMAIN_PIPE(pipe)))
813bde43 3163 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
abd58f01 3164
f86f3fb0
PZ		 3165 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3166 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3167 GEN5_IRQ_RESET(GEN8_PCU_);
abd58f01 3168
1c69eb42 3169 ibx_irq_reset(dev);
abd58f01 3170}
09f2344d 3171
d49bdb0e
PZ		 3172void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3173{
1180e206 3174 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
d49bdb0e 3175
13321786 3176 spin_lock_irq(&dev_priv->irq_lock);
d49bdb0e 3177 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
1180e206 3178 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
d49bdb0e 3179 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
1180e206 3180 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
13321786 3181 spin_unlock_irq(&dev_priv->irq_lock);
d49bdb0e
PZ		 3182}
3183
43f328d7
VS		 3184static void cherryview_irq_preinstall(struct drm_device *dev)
3185{
3186 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7
VS		 3187
3188 I915_WRITE(GEN8_MASTER_IRQ, 0);
3189 POSTING_READ(GEN8_MASTER_IRQ);
3190
d6e3cca3 3191 gen8_gt_irq_reset(dev_priv);
43f328d7
VS		 3192
3193 GEN5_IRQ_RESET(GEN8_PCU_);
3194
43f328d7
VS		 3195 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3196
70591a41 3197 vlv_display_irq_reset(dev_priv);
43f328d7
VS		 3198}
3199
82a28bcf 3200static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973 3201{
2d1013dd 3202 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 3203 struct intel_encoder *intel_encoder;
fee884ed 3204 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 3205
3206 if (HAS_PCH_IBX(dev)) {
fee884ed 3207 hotplug_irqs = SDE_HOTPLUG_MASK;
b2784e15 3208 for_each_intel_encoder(dev, intel_encoder)
cd569aed 3209 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 3210 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 3211 } else {
fee884ed 3212 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
b2784e15 3213 for_each_intel_encoder(dev, intel_encoder)
cd569aed 3214 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 3215 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 3216 }
7fe0b973 3217
fee884ed 3218 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 3219
3220 /*
3221 * Enable digital hotplug on the PCH, and configure the DP short pulse
3222 * duration to 2ms (which is the minimum in the Display Port spec)
3223 *
3224 * This register is the same on all known PCH chips.
3225 */
7fe0b973
KP		 3226 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3227 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3228 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3229 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3230 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3231 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3232}
3233
d46da437
PZ		 3234static void ibx_irq_postinstall(struct drm_device *dev)
3235{
2d1013dd 3236 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 3237 u32 mask;
e5868a31 3238
692a04cf
DV		 3239 if (HAS_PCH_NOP(dev))
3240 return;
3241
105b122e 3242 if (HAS_PCH_IBX(dev))
5c673b60 3243 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
105b122e 3244 else
5c673b60 3245 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
8664281b 3246
337ba017 3247 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
d46da437 3248 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 3249}
3250
0a9a8c91
DV		 3251static void gen5_gt_irq_postinstall(struct drm_device *dev)
3252{
3253 struct drm_i915_private *dev_priv = dev->dev_private;
3254 u32 pm_irqs, gt_irqs;
3255
3256 pm_irqs = gt_irqs = 0;
3257
3258 dev_priv->gt_irq_mask = ~0;
040d2baa 3259 if (HAS_L3_DPF(dev)) {
0a9a8c91 3260 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 3261 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3262 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 3263 }
3264
3265 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3266 if (IS_GEN5(dev)) {
3267 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3268 ILK_BSD_USER_INTERRUPT;
3269 } else {
3270 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3271 }
3272
35079899 3273 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
0a9a8c91
DV		 3274
3275 if (INTEL_INFO(dev)->gen >= 6) {
78e68d36
ID		 3276 /*
3277 * RPS interrupts will get enabled/disabled on demand when RPS
3278 * itself is enabled/disabled.
3279 */
0a9a8c91
DV		 3280 if (HAS_VEBOX(dev))
3281 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3282
605cd25b 3283 dev_priv->pm_irq_mask = 0xffffffff;
35079899 3284 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
0a9a8c91
DV		 3285 }
3286}
3287
f71d4af4 3288static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 3289{
2d1013dd 3290 struct drm_i915_private *dev_priv = dev->dev_private;
8e76f8dc
PZ		 3291 u32 display_mask, extra_mask;
3292
3293 if (INTEL_INFO(dev)->gen >= 7) {
3294 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3295 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3296 DE_PLANEB_FLIP_DONE_IVB |
5c673b60 3297 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
8e76f8dc 3298 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
5c673b60 3299 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
8e76f8dc
PZ		 3300 } else {
3301 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3302 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
5b3a856b 3303 DE_AUX_CHANNEL_A |
5b3a856b
DV		 3304 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3305 DE_POISON);
5c673b60
DV		 3306 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3307 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
8e76f8dc 3308 }
036a4a7d 3309
1ec14ad3 3310 dev_priv->irq_mask = ~display_mask;
036a4a7d 3311
0c841212
PZ		 3312 I915_WRITE(HWSTAM, 0xeffe);
3313
622364b6
PZ		 3314 ibx_irq_pre_postinstall(dev);
3315
35079899 3316 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
036a4a7d 3317
0a9a8c91 3318 gen5_gt_irq_postinstall(dev);
036a4a7d 3319
d46da437 3320 ibx_irq_postinstall(dev);
7fe0b973 3321
f97108d1 3322 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 3323 /* Enable PCU event interrupts
3324 *
3325 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 3326 * setup is guaranteed to run in single-threaded context. But we
3327 * need it to make the assert_spin_locked happy. */
d6207435 3328 spin_lock_irq(&dev_priv->irq_lock);
f97108d1 3329 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
d6207435 3330 spin_unlock_irq(&dev_priv->irq_lock);
f97108d1
JB		 3331 }
3332
036a4a7d
ZW		 3333 return 0;
3334}
3335
f8b79e58
ID		 3336static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3337{
3338 u32 pipestat_mask;
3339 u32 iir_mask;
120dda4f 3340 enum pipe pipe;
f8b79e58
ID		 3341
3342 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3343 PIPE_FIFO_UNDERRUN_STATUS;
3344
120dda4f
VS		 3345 for_each_pipe(dev_priv, pipe)
3346 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
f8b79e58
ID		 3347 POSTING_READ(PIPESTAT(PIPE_A));
3348
3349 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3350 PIPE_CRC_DONE_INTERRUPT_STATUS;
3351
120dda4f
VS		 3352 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3353 for_each_pipe(dev_priv, pipe)
3354 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
f8b79e58
ID		 3355
3356 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3357 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3358 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
120dda4f
VS		 3359 if (IS_CHERRYVIEW(dev_priv))
3360 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
f8b79e58
ID		 3361 dev_priv->irq_mask &= ~iir_mask;
3362
3363 I915_WRITE(VLV_IIR, iir_mask);
3364 I915_WRITE(VLV_IIR, iir_mask);
f8b79e58 3365 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
76e41860
VS		 3366 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3367 POSTING_READ(VLV_IMR);
f8b79e58
ID		 3368}
3369
3370static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3371{
3372 u32 pipestat_mask;
3373 u32 iir_mask;
120dda4f 3374 enum pipe pipe;
f8b79e58
ID		 3375
3376 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3377 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
6c7fba04 3378 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
120dda4f
VS		 3379 if (IS_CHERRYVIEW(dev_priv))
3380 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
f8b79e58
ID		 3381
3382 dev_priv->irq_mask |= iir_mask;
f8b79e58 3383 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
76e41860 3384 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
f8b79e58
ID		 3385 I915_WRITE(VLV_IIR, iir_mask);
3386 I915_WRITE(VLV_IIR, iir_mask);
3387 POSTING_READ(VLV_IIR);
3388
3389 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3390 PIPE_CRC_DONE_INTERRUPT_STATUS;
3391
120dda4f
VS		 3392 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3393 for_each_pipe(dev_priv, pipe)
3394 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
f8b79e58
ID		 3395
3396 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3397 PIPE_FIFO_UNDERRUN_STATUS;
120dda4f
VS		 3398
3399 for_each_pipe(dev_priv, pipe)
3400 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
f8b79e58
ID		 3401 POSTING_READ(PIPESTAT(PIPE_A));
3402}
3403
3404void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3405{
3406 assert_spin_locked(&dev_priv->irq_lock);
3407
3408 if (dev_priv->display_irqs_enabled)
3409 return;
3410
3411 dev_priv->display_irqs_enabled = true;
3412
950eabaf 3413 if (intel_irqs_enabled(dev_priv))
f8b79e58
ID		 3414 valleyview_display_irqs_install(dev_priv);
3415}
3416
3417void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3418{
3419 assert_spin_locked(&dev_priv->irq_lock);
3420
3421 if (!dev_priv->display_irqs_enabled)
3422 return;
3423
3424 dev_priv->display_irqs_enabled = false;
3425
950eabaf 3426 if (intel_irqs_enabled(dev_priv))
f8b79e58
ID		 3427 valleyview_display_irqs_uninstall(dev_priv);
3428}
3429
0e6c9a9e 3430static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
7e231dbe 3431{
f8b79e58 3432 dev_priv->irq_mask = ~0;
7e231dbe 3433
20afbda2
DV		 3434 I915_WRITE(PORT_HOTPLUG_EN, 0);
3435 POSTING_READ(PORT_HOTPLUG_EN);
3436
7e231dbe 3437 I915_WRITE(VLV_IIR, 0xffffffff);
76e41860
VS		 3438 I915_WRITE(VLV_IIR, 0xffffffff);
3439 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3440 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3441 POSTING_READ(VLV_IMR);
7e231dbe 3442
b79480ba
DV		 3443 /* Interrupt setup is already guaranteed to be single-threaded, this is
3444 * just to make the assert_spin_locked check happy. */
d6207435 3445 spin_lock_irq(&dev_priv->irq_lock);
f8b79e58
ID		 3446 if (dev_priv->display_irqs_enabled)
3447 valleyview_display_irqs_install(dev_priv);
d6207435 3448 spin_unlock_irq(&dev_priv->irq_lock);
0e6c9a9e
VS		 3449}
3450
3451static int valleyview_irq_postinstall(struct drm_device *dev)
3452{
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454
3455 vlv_display_irq_postinstall(dev_priv);
7e231dbe 3456
0a9a8c91 3457 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 3458
3459 /* ack & enable invalid PTE error interrupts */
3460#if 0 /* FIXME: add support to irq handler for checking these bits */
3461 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3462 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3463#endif
3464
3465 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 3466
3467 return 0;
3468}
3469
abd58f01
BW		 3470static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3471{
abd58f01
BW		 3472 /* These are interrupts we'll toggle with the ring mask register */
3473 uint32_t gt_interrupts[] = {
3474 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
73d477f6 3475 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
abd58f01 3476 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
73d477f6
OM		 3477 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3478 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
abd58f01 3479 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
73d477f6
OM		 3480 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3481 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3482 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
abd58f01 3483 0,
73d477f6
OM		 3484 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3485 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
abd58f01
BW		 3486 };
3487
0961021a 3488 dev_priv->pm_irq_mask = 0xffffffff;
9a2d2d87
D		 3489 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3490 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
78e68d36
ID		 3491 /*
3492 * RPS interrupts will get enabled/disabled on demand when RPS itself
3493 * is enabled/disabled.
3494 */
3495 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
9a2d2d87 3496 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
abd58f01
BW		 3497}
3498
3499static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3500{
770de83d
DL		 3501 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3502 uint32_t de_pipe_enables;
abd58f01 3503 int pipe;
88e04703 3504 u32 aux_en = GEN8_AUX_CHANNEL_A;
770de83d 3505
88e04703 3506 if (IS_GEN9(dev_priv)) {
770de83d
DL		 3507 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3508 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
88e04703
JB		 3509 aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3510 GEN9_AUX_CHANNEL_D;
3511 } else
770de83d
DL		 3512 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3513 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3514
3515 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3516 GEN8_PIPE_FIFO_UNDERRUN;
3517
13b3a0a7
DV		 3518 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3519 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3520 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
abd58f01 3521
055e393f 3522 for_each_pipe(dev_priv, pipe)
f458ebbc 3523 if (intel_display_power_is_enabled(dev_priv,
813bde43
PZ		 3524 POWER_DOMAIN_PIPE(pipe)))
3525 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3526 dev_priv->de_irq_mask[pipe],
3527 de_pipe_enables);
abd58f01 3528
88e04703 3529 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
abd58f01
BW		 3530}
3531
3532static int gen8_irq_postinstall(struct drm_device *dev)
3533{
3534 struct drm_i915_private *dev_priv = dev->dev_private;
3535
622364b6
PZ		 3536 ibx_irq_pre_postinstall(dev);
3537
abd58f01
BW		 3538 gen8_gt_irq_postinstall(dev_priv);
3539 gen8_de_irq_postinstall(dev_priv);
3540
3541 ibx_irq_postinstall(dev);
3542
3543 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3544 POSTING_READ(GEN8_MASTER_IRQ);
3545
3546 return 0;
3547}
3548
43f328d7
VS		 3549static int cherryview_irq_postinstall(struct drm_device *dev)
3550{
3551 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7 3552
c2b66797 3553 vlv_display_irq_postinstall(dev_priv);
43f328d7
VS		 3554
3555 gen8_gt_irq_postinstall(dev_priv);
3556
3557 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3558 POSTING_READ(GEN8_MASTER_IRQ);
3559
3560 return 0;
3561}
3562
abd58f01
BW		 3563static void gen8_irq_uninstall(struct drm_device *dev)
3564{
3565 struct drm_i915_private *dev_priv = dev->dev_private;
abd58f01
BW		 3566
3567 if (!dev_priv)
3568 return;
3569
823f6b38 3570 gen8_irq_reset(dev);
abd58f01
BW		 3571}
3572
8ea0be4f
VS		 3573static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3574{
3575 /* Interrupt setup is already guaranteed to be single-threaded, this is
3576 * just to make the assert_spin_locked check happy. */
3577 spin_lock_irq(&dev_priv->irq_lock);
3578 if (dev_priv->display_irqs_enabled)
3579 valleyview_display_irqs_uninstall(dev_priv);
3580 spin_unlock_irq(&dev_priv->irq_lock);
3581
3582 vlv_display_irq_reset(dev_priv);
3583
c352d1ba 3584 dev_priv->irq_mask = ~0;
8ea0be4f
VS		 3585}
3586
7e231dbe
JB		 3587static void valleyview_irq_uninstall(struct drm_device *dev)
3588{
2d1013dd 3589 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 3590
3591 if (!dev_priv)
3592 return;
3593
843d0e7d
ID		 3594 I915_WRITE(VLV_MASTER_IER, 0);
3595
893fce8e
VS		 3596 gen5_gt_irq_reset(dev);
3597
7e231dbe 3598 I915_WRITE(HWSTAM, 0xffffffff);
f8b79e58 3599
8ea0be4f 3600 vlv_display_irq_uninstall(dev_priv);
7e231dbe
JB		 3601}
3602
43f328d7
VS		 3603static void cherryview_irq_uninstall(struct drm_device *dev)
3604{
3605 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7
VS		 3606
3607 if (!dev_priv)
3608 return;
3609
3610 I915_WRITE(GEN8_MASTER_IRQ, 0);
3611 POSTING_READ(GEN8_MASTER_IRQ);
3612
a2c30fba 3613 gen8_gt_irq_reset(dev_priv);
43f328d7 3614
a2c30fba 3615 GEN5_IRQ_RESET(GEN8_PCU_);
43f328d7 3616
c2b66797 3617 vlv_display_irq_uninstall(dev_priv);
43f328d7
VS		 3618}
3619
f71d4af4 3620static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d 3621{
2d1013dd 3622 struct drm_i915_private *dev_priv = dev->dev_private;
4697995b
JB		 3623
3624 if (!dev_priv)
3625 return;
3626
be30b29f 3627 ironlake_irq_reset(dev);
036a4a7d
ZW		 3628}
3629
a266c7d5 3630static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4 3631{
2d1013dd 3632 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 3633 int pipe;
91e3738e 3634
055e393f 3635 for_each_pipe(dev_priv, pipe)
9db4a9c7 3636 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 3637 I915_WRITE16(IMR, 0xffff);
3638 I915_WRITE16(IER, 0x0);
3639 POSTING_READ16(IER);
c2798b19
CW		 3640}
3641
3642static int i8xx_irq_postinstall(struct drm_device *dev)
3643{
2d1013dd 3644 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19 3645
c2798b19
CW		 3646 I915_WRITE16(EMR,
3647 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3648
3649 /* Unmask the interrupts that we always want on. */
3650 dev_priv->irq_mask =
3651 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3652 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3653 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3654 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3655 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3656 I915_WRITE16(IMR, dev_priv->irq_mask);
3657
3658 I915_WRITE16(IER,
3659 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3660 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3661 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3662 I915_USER_INTERRUPT);
3663 POSTING_READ16(IER);
3664
379ef82d
DV		 3665 /* Interrupt setup is already guaranteed to be single-threaded, this is
3666 * just to make the assert_spin_locked check happy. */
d6207435 3667 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 3668 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3669 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 3670 spin_unlock_irq(&dev_priv->irq_lock);
379ef82d 3671
c2798b19
CW		 3672 return 0;
3673}
3674
90a72f87
VS		 3675/*
3676 * Returns true when a page flip has completed.
3677 */
3678static bool i8xx_handle_vblank(struct drm_device *dev,
1f1c2e24 3679 int plane, int pipe, u32 iir)
90a72f87 3680{
2d1013dd 3681 struct drm_i915_private *dev_priv = dev->dev_private;
1f1c2e24 3682 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
90a72f87 3683
8d7849db 3684 if (!intel_pipe_handle_vblank(dev, pipe))
90a72f87
VS		 3685 return false;
3686
3687 if ((iir & flip_pending) == 0)
d6bbafa1 3688 goto check_page_flip;
90a72f87 3689
90a72f87
VS		 3690 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3691 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3692 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3693 * the flip is completed (no longer pending). Since this doesn't raise
3694 * an interrupt per se, we watch for the change at vblank.
3695 */
3696 if (I915_READ16(ISR) & flip_pending)
d6bbafa1 3697 goto check_page_flip;
90a72f87 3698
7d47559e 3699 intel_prepare_page_flip(dev, plane);
90a72f87 3700 intel_finish_page_flip(dev, pipe);
90a72f87 3701 return true;
d6bbafa1
CW		 3702
3703check_page_flip:
3704 intel_check_page_flip(dev, pipe);
3705 return false;
90a72f87
VS		 3706}
3707
ff1f525e 3708static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19 3709{
45a83f84 3710 struct drm_device *dev = arg;
2d1013dd 3711 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3712 u16 iir, new_iir;
3713 u32 pipe_stats[2];
c2798b19
CW		 3714 int pipe;
3715 u16 flip_mask =
3716 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3717 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3718
2dd2a883
ID		 3719 if (!intel_irqs_enabled(dev_priv))
3720 return IRQ_NONE;
3721
c2798b19
CW		 3722 iir = I915_READ16(IIR);
3723 if (iir == 0)
3724 return IRQ_NONE;
3725
3726 while (iir & ~flip_mask) {
3727 /* Can't rely on pipestat interrupt bit in iir as it might
3728 * have been cleared after the pipestat interrupt was received.
3729 * It doesn't set the bit in iir again, but it still produces
3730 * interrupts (for non-MSI).
3731 */
222c7f51 3732 spin_lock(&dev_priv->irq_lock);
c2798b19 3733 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 3734 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
c2798b19 3735
055e393f 3736 for_each_pipe(dev_priv, pipe) {
c2798b19
CW		 3737 int reg = PIPESTAT(pipe);
3738 pipe_stats[pipe] = I915_READ(reg);
3739
3740 /*
3741 * Clear the PIPE*STAT regs before the IIR
3742 */
2d9d2b0b 3743 if (pipe_stats[pipe] & 0x8000ffff)
c2798b19 3744 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19 3745 }
222c7f51 3746 spin_unlock(&dev_priv->irq_lock);
c2798b19
CW		 3747
3748 I915_WRITE16(IIR, iir & ~flip_mask);
3749 new_iir = I915_READ16(IIR); /* Flush posted writes */
3750
c2798b19
CW		 3751 if (iir & I915_USER_INTERRUPT)
3752 notify_ring(dev, &dev_priv->ring[RCS]);
3753
055e393f 3754 for_each_pipe(dev_priv, pipe) {
1f1c2e24 3755 int plane = pipe;
3a77c4c4 3756 if (HAS_FBC(dev))
1f1c2e24
VS		 3757 plane = !plane;
3758
4356d586 3759 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
1f1c2e24
VS		 3760 i8xx_handle_vblank(dev, plane, pipe, iir))
3761 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
c2798b19 3762
4356d586 3763 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3764 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b 3765
1f7247c0
DV		 3766 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3767 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3768 pipe);
4356d586 3769 }
c2798b19
CW		 3770
3771 iir = new_iir;
3772 }
3773
3774 return IRQ_HANDLED;
3775}
3776
3777static void i8xx_irq_uninstall(struct drm_device * dev)
3778{
2d1013dd 3779 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3780 int pipe;
3781
055e393f 3782 for_each_pipe(dev_priv, pipe) {
c2798b19
CW		 3783 /* Clear enable bits; then clear status bits */
3784 I915_WRITE(PIPESTAT(pipe), 0);
3785 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3786 }
3787 I915_WRITE16(IMR, 0xffff);
3788 I915_WRITE16(IER, 0x0);
3789 I915_WRITE16(IIR, I915_READ16(IIR));
3790}
3791
a266c7d5
CW		 3792static void i915_irq_preinstall(struct drm_device * dev)
3793{
2d1013dd 3794 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3795 int pipe;
3796
a266c7d5
CW		 3797 if (I915_HAS_HOTPLUG(dev)) {
3798 I915_WRITE(PORT_HOTPLUG_EN, 0);
3799 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3800 }
3801
00d98ebd 3802 I915_WRITE16(HWSTAM, 0xeffe);
055e393f 3803 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 3804 I915_WRITE(PIPESTAT(pipe), 0);
3805 I915_WRITE(IMR, 0xffffffff);
3806 I915_WRITE(IER, 0x0);
3807 POSTING_READ(IER);
3808}
3809
3810static int i915_irq_postinstall(struct drm_device *dev)
3811{
2d1013dd 3812 struct drm_i915_private *dev_priv = dev->dev_private;
38bde180 3813 u32 enable_mask;
a266c7d5 3814
38bde180
CW		 3815 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3816
3817 /* Unmask the interrupts that we always want on. */
3818 dev_priv->irq_mask =
3819 ~(I915_ASLE_INTERRUPT |
3820 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3821 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3822 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3823 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3824 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3825
3826 enable_mask =
3827 I915_ASLE_INTERRUPT |
3828 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3829 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3830 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3831 I915_USER_INTERRUPT;
3832
a266c7d5 3833 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3834 I915_WRITE(PORT_HOTPLUG_EN, 0);
3835 POSTING_READ(PORT_HOTPLUG_EN);
3836
a266c7d5
CW		 3837 /* Enable in IER... */
3838 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3839 /* and unmask in IMR */
3840 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3841 }
3842
a266c7d5
CW		 3843 I915_WRITE(IMR, dev_priv->irq_mask);
3844 I915_WRITE(IER, enable_mask);
3845 POSTING_READ(IER);
3846
f49e38dd 3847 i915_enable_asle_pipestat(dev);
20afbda2 3848
379ef82d
DV		 3849 /* Interrupt setup is already guaranteed to be single-threaded, this is
3850 * just to make the assert_spin_locked check happy. */
d6207435 3851 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 3852 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3853 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 3854 spin_unlock_irq(&dev_priv->irq_lock);
379ef82d 3855
20afbda2
DV		 3856 return 0;
3857}
3858
90a72f87
VS		 3859/*
3860 * Returns true when a page flip has completed.
3861 */
3862static bool i915_handle_vblank(struct drm_device *dev,
3863 int plane, int pipe, u32 iir)
3864{
2d1013dd 3865 struct drm_i915_private *dev_priv = dev->dev_private;
90a72f87
VS		 3866 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3867
8d7849db 3868 if (!intel_pipe_handle_vblank(dev, pipe))
90a72f87
VS		 3869 return false;
3870
3871 if ((iir & flip_pending) == 0)
d6bbafa1 3872 goto check_page_flip;
90a72f87 3873
90a72f87
VS		 3874 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3875 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3876 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3877 * the flip is completed (no longer pending). Since this doesn't raise
3878 * an interrupt per se, we watch for the change at vblank.
3879 */
3880 if (I915_READ(ISR) & flip_pending)
d6bbafa1 3881 goto check_page_flip;
90a72f87 3882
7d47559e 3883 intel_prepare_page_flip(dev, plane);
90a72f87 3884 intel_finish_page_flip(dev, pipe);
90a72f87 3885 return true;
d6bbafa1
CW		 3886
3887check_page_flip:
3888 intel_check_page_flip(dev, pipe);
3889 return false;
90a72f87
VS		 3890}
3891
ff1f525e 3892static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5 3893{
45a83f84 3894 struct drm_device *dev = arg;
2d1013dd 3895 struct drm_i915_private *dev_priv = dev->dev_private;
8291ee90 3896 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
38bde180
CW		 3897 u32 flip_mask =
3898 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3899 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3900 int pipe, ret = IRQ_NONE;
a266c7d5 3901
2dd2a883
ID		 3902 if (!intel_irqs_enabled(dev_priv))
3903 return IRQ_NONE;
3904
a266c7d5 3905 iir = I915_READ(IIR);
38bde180
CW		 3906 do {
3907 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3908 bool blc_event = false;
a266c7d5
CW		 3909
3910 /* Can't rely on pipestat interrupt bit in iir as it might
3911 * have been cleared after the pipestat interrupt was received.
3912 * It doesn't set the bit in iir again, but it still produces
3913 * interrupts (for non-MSI).
3914 */
222c7f51 3915 spin_lock(&dev_priv->irq_lock);
a266c7d5 3916 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 3917 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
a266c7d5 3918
055e393f 3919 for_each_pipe(dev_priv, pipe) {
a266c7d5
CW		 3920 int reg = PIPESTAT(pipe);
3921 pipe_stats[pipe] = I915_READ(reg);
3922
38bde180 3923 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5 3924 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3925 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3926 irq_received = true;
a266c7d5
CW		 3927 }
3928 }
222c7f51 3929 spin_unlock(&dev_priv->irq_lock);
a266c7d5
CW		 3930
3931 if (!irq_received)
3932 break;
3933
a266c7d5 3934 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 3935 if (I915_HAS_HOTPLUG(dev) &&
3936 iir & I915_DISPLAY_PORT_INTERRUPT)
3937 i9xx_hpd_irq_handler(dev);
a266c7d5 3938
38bde180 3939 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3940 new_iir = I915_READ(IIR); /* Flush posted writes */
3941
a266c7d5
CW		 3942 if (iir & I915_USER_INTERRUPT)
3943 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3944
055e393f 3945 for_each_pipe(dev_priv, pipe) {
38bde180 3946 int plane = pipe;
3a77c4c4 3947 if (HAS_FBC(dev))
38bde180 3948 plane = !plane;
90a72f87 3949
8291ee90 3950 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3951 i915_handle_vblank(dev, plane, pipe, iir))
3952 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3953
3954 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3955 blc_event = true;
4356d586
DV		 3956
3957 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3958 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b 3959
1f7247c0
DV		 3960 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3961 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3962 pipe);
a266c7d5
CW		 3963 }
3964
a266c7d5
CW		 3965 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3966 intel_opregion_asle_intr(dev);
3967
3968 /* With MSI, interrupts are only generated when iir
3969 * transitions from zero to nonzero. If another bit got
3970 * set while we were handling the existing iir bits, then
3971 * we would never get another interrupt.
3972 *
3973 * This is fine on non-MSI as well, as if we hit this path
3974 * we avoid exiting the interrupt handler only to generate
3975 * another one.
3976 *
3977 * Note that for MSI this could cause a stray interrupt report
3978 * if an interrupt landed in the time between writing IIR and
3979 * the posting read. This should be rare enough to never
3980 * trigger the 99% of 100,000 interrupts test for disabling
3981 * stray interrupts.
3982 */
38bde180 3983 ret = IRQ_HANDLED;
a266c7d5 3984 iir = new_iir;
38bde180 3985 } while (iir & ~flip_mask);
a266c7d5
CW		 3986
3987 return ret;
3988}
3989
3990static void i915_irq_uninstall(struct drm_device * dev)
3991{
2d1013dd 3992 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3993 int pipe;
3994
a266c7d5
CW		 3995 if (I915_HAS_HOTPLUG(dev)) {
3996 I915_WRITE(PORT_HOTPLUG_EN, 0);
3997 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3998 }
3999
00d98ebd 4000 I915_WRITE16(HWSTAM, 0xffff);
055e393f 4001 for_each_pipe(dev_priv, pipe) {
55b39755 4002 /* Clear enable bits; then clear status bits */
a266c7d5 4003 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 4004 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4005 }
a266c7d5
CW		 4006 I915_WRITE(IMR, 0xffffffff);
4007 I915_WRITE(IER, 0x0);
4008
a266c7d5
CW		 4009 I915_WRITE(IIR, I915_READ(IIR));
4010}
4011
4012static void i965_irq_preinstall(struct drm_device * dev)
4013{
2d1013dd 4014 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4015 int pipe;
4016
adca4730
CW		 4017 I915_WRITE(PORT_HOTPLUG_EN, 0);
4018 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 4019
4020 I915_WRITE(HWSTAM, 0xeffe);
055e393f 4021 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4022 I915_WRITE(PIPESTAT(pipe), 0);
4023 I915_WRITE(IMR, 0xffffffff);
4024 I915_WRITE(IER, 0x0);
4025 POSTING_READ(IER);
4026}
4027
4028static int i965_irq_postinstall(struct drm_device *dev)
4029{
2d1013dd 4030 struct drm_i915_private *dev_priv = dev->dev_private;
bbba0a97 4031 u32 enable_mask;
a266c7d5
CW		 4032 u32 error_mask;
4033
a266c7d5 4034 /* Unmask the interrupts that we always want on. */
bbba0a97 4035 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 4036 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 4037 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4038 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4039 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4040 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4041 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4042
4043 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 4044 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4045 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 4046 enable_mask |= I915_USER_INTERRUPT;
4047
4048 if (IS_G4X(dev))
4049 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 4050
b79480ba
DV		 4051 /* Interrupt setup is already guaranteed to be single-threaded, this is
4052 * just to make the assert_spin_locked check happy. */
d6207435 4053 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 4054 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4055 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4056 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 4057 spin_unlock_irq(&dev_priv->irq_lock);
a266c7d5 4058
a266c7d5
CW		 4059 /*
4060 * Enable some error detection, note the instruction error mask
4061 * bit is reserved, so we leave it masked.
4062 */
4063 if (IS_G4X(dev)) {
4064 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4065 GM45_ERROR_MEM_PRIV |
4066 GM45_ERROR_CP_PRIV |
4067 I915_ERROR_MEMORY_REFRESH);
4068 } else {
4069 error_mask = ~(I915_ERROR_PAGE_TABLE |
4070 I915_ERROR_MEMORY_REFRESH);
4071 }
4072 I915_WRITE(EMR, error_mask);
4073
4074 I915_WRITE(IMR, dev_priv->irq_mask);
4075 I915_WRITE(IER, enable_mask);
4076 POSTING_READ(IER);
4077
20afbda2
DV		 4078 I915_WRITE(PORT_HOTPLUG_EN, 0);
4079 POSTING_READ(PORT_HOTPLUG_EN);
4080
f49e38dd 4081 i915_enable_asle_pipestat(dev);
20afbda2
DV		 4082
4083 return 0;
4084}
4085
bac56d5b 4086static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2 4087{
2d1013dd 4088 struct drm_i915_private *dev_priv = dev->dev_private;
cd569aed 4089 struct intel_encoder *intel_encoder;
20afbda2
DV		 4090 u32 hotplug_en;
4091
b5ea2d56
DV		 4092 assert_spin_locked(&dev_priv->irq_lock);
4093
778eb334
VS		 4094 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4095 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4096 /* Note HDMI and DP share hotplug bits */
4097 /* enable bits are the same for all generations */
4098 for_each_intel_encoder(dev, intel_encoder)
4099 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4100 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4101 /* Programming the CRT detection parameters tends
4102 to generate a spurious hotplug event about three
4103 seconds later. So just do it once.
4104 */
4105 if (IS_G4X(dev))
4106 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4107 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4108 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4109
4110 /* Ignore TV since it's buggy */
4111 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 4112}
4113
ff1f525e 4114static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5 4115{
45a83f84 4116 struct drm_device *dev = arg;
2d1013dd 4117 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4118 u32 iir, new_iir;
4119 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5 4120 int ret = IRQ_NONE, pipe;
21ad8330
VS		 4121 u32 flip_mask =
4122 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4123 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5 4124
2dd2a883
ID		 4125 if (!intel_irqs_enabled(dev_priv))
4126 return IRQ_NONE;
4127
a266c7d5
CW		 4128 iir = I915_READ(IIR);
4129
a266c7d5 4130 for (;;) {
501e01d7 4131 bool irq_received = (iir & ~flip_mask) != 0;
2c8ba29f
CW		 4132 bool blc_event = false;
4133
a266c7d5
CW		 4134 /* Can't rely on pipestat interrupt bit in iir as it might
4135 * have been cleared after the pipestat interrupt was received.
4136 * It doesn't set the bit in iir again, but it still produces
4137 * interrupts (for non-MSI).
4138 */
222c7f51 4139 spin_lock(&dev_priv->irq_lock);
a266c7d5 4140 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 4141 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
a266c7d5 4142
055e393f 4143 for_each_pipe(dev_priv, pipe) {
a266c7d5
CW		 4144 int reg = PIPESTAT(pipe);
4145 pipe_stats[pipe] = I915_READ(reg);
4146
4147 /*
4148 * Clear the PIPE*STAT regs before the IIR
4149 */
4150 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 4151 I915_WRITE(reg, pipe_stats[pipe]);
501e01d7 4152 irq_received = true;
a266c7d5
CW		 4153 }
4154 }
222c7f51 4155 spin_unlock(&dev_priv->irq_lock);
a266c7d5
CW		 4156
4157 if (!irq_received)
4158 break;
4159
4160 ret = IRQ_HANDLED;
4161
4162 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 4163 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4164 i9xx_hpd_irq_handler(dev);
a266c7d5 4165
21ad8330 4166 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 4167 new_iir = I915_READ(IIR); /* Flush posted writes */
4168
a266c7d5
CW		 4169 if (iir & I915_USER_INTERRUPT)
4170 notify_ring(dev, &dev_priv->ring[RCS]);
4171 if (iir & I915_BSD_USER_INTERRUPT)
4172 notify_ring(dev, &dev_priv->ring[VCS]);
4173
055e393f 4174 for_each_pipe(dev_priv, pipe) {
2c8ba29f 4175 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 4176 i915_handle_vblank(dev, pipe, pipe, iir))
4177 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 4178
4179 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4180 blc_event = true;
4356d586
DV		 4181
4182 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 4183 i9xx_pipe_crc_irq_handler(dev, pipe);
a266c7d5 4184
1f7247c0
DV		 4185 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4186 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2d9d2b0b 4187 }
a266c7d5
CW		 4188
4189 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4190 intel_opregion_asle_intr(dev);
4191
515ac2bb
DV		 4192 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4193 gmbus_irq_handler(dev);
4194
a266c7d5
CW		 4195 /* With MSI, interrupts are only generated when iir
4196 * transitions from zero to nonzero. If another bit got
4197 * set while we were handling the existing iir bits, then
4198 * we would never get another interrupt.
4199 *
4200 * This is fine on non-MSI as well, as if we hit this path
4201 * we avoid exiting the interrupt handler only to generate
4202 * another one.
4203 *
4204 * Note that for MSI this could cause a stray interrupt report
4205 * if an interrupt landed in the time between writing IIR and
4206 * the posting read. This should be rare enough to never
4207 * trigger the 99% of 100,000 interrupts test for disabling
4208 * stray interrupts.
4209 */
4210 iir = new_iir;
4211 }
4212
4213 return ret;
4214}
4215
4216static void i965_irq_uninstall(struct drm_device * dev)
4217{
2d1013dd 4218 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4219 int pipe;
4220
4221 if (!dev_priv)
4222 return;
4223
adca4730
CW		 4224 I915_WRITE(PORT_HOTPLUG_EN, 0);
4225 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 4226
4227 I915_WRITE(HWSTAM, 0xffffffff);
055e393f 4228 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4229 I915_WRITE(PIPESTAT(pipe), 0);
4230 I915_WRITE(IMR, 0xffffffff);
4231 I915_WRITE(IER, 0x0);
4232
055e393f 4233 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4234 I915_WRITE(PIPESTAT(pipe),
4235 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4236 I915_WRITE(IIR, I915_READ(IIR));
4237}
4238
4cb21832 4239static void intel_hpd_irq_reenable_work(struct work_struct *work)
ac4c16c5 4240{
6323751d
ID		 4241 struct drm_i915_private *dev_priv =
4242 container_of(work, typeof(*dev_priv),
4243 hotplug_reenable_work.work);
ac4c16c5
EE		 4244 struct drm_device *dev = dev_priv->dev;
4245 struct drm_mode_config *mode_config = &dev->mode_config;
ac4c16c5
EE		 4246 int i;
4247
6323751d
ID		 4248 intel_runtime_pm_get(dev_priv);
4249
4cb21832 4250 spin_lock_irq(&dev_priv->irq_lock);
ac4c16c5
EE		 4251 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4252 struct drm_connector *connector;
4253
4254 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4255 continue;
4256
4257 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4258
4259 list_for_each_entry(connector, &mode_config->connector_list, head) {
4260 struct intel_connector *intel_connector = to_intel_connector(connector);
4261
4262 if (intel_connector->encoder->hpd_pin == i) {
4263 if (connector->polled != intel_connector->polled)
4264 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
c23cc417 4265 connector->name);
ac4c16c5
EE		 4266 connector->polled = intel_connector->polled;
4267 if (!connector->polled)
4268 connector->polled = DRM_CONNECTOR_POLL_HPD;
4269 }
4270 }
4271 }
4272 if (dev_priv->display.hpd_irq_setup)
4273 dev_priv->display.hpd_irq_setup(dev);
4cb21832 4274 spin_unlock_irq(&dev_priv->irq_lock);
6323751d
ID		 4275
4276 intel_runtime_pm_put(dev_priv);
ac4c16c5
EE		 4277}
4278
fca52a55
DV		 4279/**
4280 * intel_irq_init - initializes irq support
4281 * @dev_priv: i915 device instance
4282 *
4283 * This function initializes all the irq support including work items, timers
4284 * and all the vtables. It does not setup the interrupt itself though.
4285 */
b963291c 4286void intel_irq_init(struct drm_i915_private *dev_priv)
f71d4af4 4287{
b963291c 4288 struct drm_device *dev = dev_priv->dev;
8b2e326d
CW		 4289
4290 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
13cf5504 4291 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
c6a828d3 4292 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 4293 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 4294
a6706b45 4295 /* Let's track the enabled rps events */
b963291c 4296 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
6c65a587 4297 /* WaGsvRC0ResidencyMethod:vlv */
31685c25
D		 4298 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4299 else
4300 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
a6706b45 4301
737b1506
CW		 4302 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4303 i915_hangcheck_elapsed);
6323751d 4304 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4cb21832 4305 intel_hpd_irq_reenable_work);
61bac78e 4306
97a19a24 4307 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 4308
b963291c 4309 if (IS_GEN2(dev_priv)) {
4cdb83ec
VS		 4310 dev->max_vblank_count = 0;
4311 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
b963291c 4312 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
f71d4af4
JB		 4313 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4314 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
391f75e2
VS		 4315 } else {
4316 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4317 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 4318 }
4319
21da2700
VS		 4320 /*
4321 * Opt out of the vblank disable timer on everything except gen2.
4322 * Gen2 doesn't have a hardware frame counter and so depends on
4323 * vblank interrupts to produce sane vblank seuquence numbers.
4324 */
b963291c 4325 if (!IS_GEN2(dev_priv))
21da2700
VS		 4326 dev->vblank_disable_immediate = true;
4327
f3a5c3f6
DV		 4328 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4329 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
f71d4af4 4330
b963291c 4331 if (IS_CHERRYVIEW(dev_priv)) {
43f328d7
VS		 4332 dev->driver->irq_handler = cherryview_irq_handler;
4333 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4334 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4335 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4336 dev->driver->enable_vblank = valleyview_enable_vblank;
4337 dev->driver->disable_vblank = valleyview_disable_vblank;
4338 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
b963291c 4339 } else if (IS_VALLEYVIEW(dev_priv)) {
7e231dbe
JB		 4340 dev->driver->irq_handler = valleyview_irq_handler;
4341 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4342 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4343 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4344 dev->driver->enable_vblank = valleyview_enable_vblank;
4345 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 4346 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
b963291c 4347 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
abd58f01 4348 dev->driver->irq_handler = gen8_irq_handler;
723761b8 4349 dev->driver->irq_preinstall = gen8_irq_reset;
abd58f01
BW		 4350 dev->driver->irq_postinstall = gen8_irq_postinstall;
4351 dev->driver->irq_uninstall = gen8_irq_uninstall;
4352 dev->driver->enable_vblank = gen8_enable_vblank;
4353 dev->driver->disable_vblank = gen8_disable_vblank;
4354 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 4355 } else if (HAS_PCH_SPLIT(dev)) {
4356 dev->driver->irq_handler = ironlake_irq_handler;
723761b8 4357 dev->driver->irq_preinstall = ironlake_irq_reset;
f71d4af4
JB		 4358 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4359 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4360 dev->driver->enable_vblank = ironlake_enable_vblank;
4361 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 4362 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 4363 } else {
b963291c 4364 if (INTEL_INFO(dev_priv)->gen == 2) {
c2798b19
CW		 4365 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4366 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4367 dev->driver->irq_handler = i8xx_irq_handler;
4368 dev->driver->irq_uninstall = i8xx_irq_uninstall;
b963291c 4369 } else if (INTEL_INFO(dev_priv)->gen == 3) {
a266c7d5
CW		 4370 dev->driver->irq_preinstall = i915_irq_preinstall;
4371 dev->driver->irq_postinstall = i915_irq_postinstall;
4372 dev->driver->irq_uninstall = i915_irq_uninstall;
4373 dev->driver->irq_handler = i915_irq_handler;
c2798b19 4374 } else {
a266c7d5
CW		 4375 dev->driver->irq_preinstall = i965_irq_preinstall;
4376 dev->driver->irq_postinstall = i965_irq_postinstall;
4377 dev->driver->irq_uninstall = i965_irq_uninstall;
4378 dev->driver->irq_handler = i965_irq_handler;
c2798b19 4379 }
778eb334
VS		 4380 if (I915_HAS_HOTPLUG(dev_priv))
4381 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
f71d4af4
JB		 4382 dev->driver->enable_vblank = i915_enable_vblank;
4383 dev->driver->disable_vblank = i915_disable_vblank;
4384 }
4385}
20afbda2 4386
fca52a55
DV		 4387/**
4388 * intel_hpd_init - initializes and enables hpd support
4389 * @dev_priv: i915 device instance
4390 *
4391 * This function enables the hotplug support. It requires that interrupts have
4392 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4393 * poll request can run concurrently to other code, so locking rules must be
4394 * obeyed.
4395 *
4396 * This is a separate step from interrupt enabling to simplify the locking rules
4397 * in the driver load and resume code.
4398 */
b963291c 4399void intel_hpd_init(struct drm_i915_private *dev_priv)
20afbda2 4400{
b963291c 4401 struct drm_device *dev = dev_priv->dev;
821450c6
EE		 4402 struct drm_mode_config *mode_config = &dev->mode_config;
4403 struct drm_connector *connector;
4404 int i;
20afbda2 4405
821450c6
EE		 4406 for (i = 1; i < HPD_NUM_PINS; i++) {
4407 dev_priv->hpd_stats[i].hpd_cnt = 0;
4408 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4409 }
4410 list_for_each_entry(connector, &mode_config->connector_list, head) {
4411 struct intel_connector *intel_connector = to_intel_connector(connector);
4412 connector->polled = intel_connector->polled;
0e32b39c
DA		 4413 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4414 connector->polled = DRM_CONNECTOR_POLL_HPD;
4415 if (intel_connector->mst_port)
821450c6
EE		 4416 connector->polled = DRM_CONNECTOR_POLL_HPD;
4417 }
b5ea2d56
DV		 4418
4419 /* Interrupt setup is already guaranteed to be single-threaded, this is
4420 * just to make the assert_spin_locked checks happy. */
d6207435 4421 spin_lock_irq(&dev_priv->irq_lock);
20afbda2
DV		 4422 if (dev_priv->display.hpd_irq_setup)
4423 dev_priv->display.hpd_irq_setup(dev);
d6207435 4424 spin_unlock_irq(&dev_priv->irq_lock);
20afbda2 4425}
c67a470b 4426
fca52a55
DV		 4427/**
4428 * intel_irq_install - enables the hardware interrupt
4429 * @dev_priv: i915 device instance
4430 *
4431 * This function enables the hardware interrupt handling, but leaves the hotplug
4432 * handling still disabled. It is called after intel_irq_init().
4433 *
4434 * In the driver load and resume code we need working interrupts in a few places
4435 * but don't want to deal with the hassle of concurrent probe and hotplug
4436 * workers. Hence the split into this two-stage approach.
4437 */
2aeb7d3a
DV		 4438int intel_irq_install(struct drm_i915_private *dev_priv)
4439{
4440 /*
4441 * We enable some interrupt sources in our postinstall hooks, so mark
4442 * interrupts as enabled _before_ actually enabling them to avoid
4443 * special cases in our ordering checks.
4444 */
4445 dev_priv->pm.irqs_enabled = true;
4446
4447 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4448}
4449
fca52a55
DV		 4450/**
4451 * intel_irq_uninstall - finilizes all irq handling
4452 * @dev_priv: i915 device instance
4453 *
4454 * This stops interrupt and hotplug handling and unregisters and frees all
4455 * resources acquired in the init functions.
4456 */
2aeb7d3a
DV		 4457void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4458{
4459 drm_irq_uninstall(dev_priv->dev);
4460 intel_hpd_cancel_work(dev_priv);
4461 dev_priv->pm.irqs_enabled = false;
4462}
4463
fca52a55
DV		 4464/**
4465 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4466 * @dev_priv: i915 device instance
4467 *
4468 * This function is used to disable interrupts at runtime, both in the runtime
4469 * pm and the system suspend/resume code.
4470 */
b963291c 4471void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
c67a470b 4472{
b963291c 4473 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
2aeb7d3a 4474 dev_priv->pm.irqs_enabled = false;
2dd2a883 4475 synchronize_irq(dev_priv->dev->irq);
c67a470b
PZ		 4476}
4477
fca52a55
DV		 4478/**
4479 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4480 * @dev_priv: i915 device instance
4481 *
4482 * This function is used to enable interrupts at runtime, both in the runtime
4483 * pm and the system suspend/resume code.
4484 */
b963291c 4485void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
c67a470b 4486{
2aeb7d3a 4487 dev_priv->pm.irqs_enabled = true;
b963291c
DV		 4488 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4489 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
c67a470b 4490}
Linux 6.x block layer and io_uring tree(s)