Commit | Line | Data |
---|---|---|
0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e4ce95aa VS |
48 | static const u32 hpd_ilk[HPD_NUM_PINS] = { |
49 | [HPD_PORT_A] = DE_DP_A_HOTPLUG, | |
50 | }; | |
51 | ||
23bb4cb5 VS |
52 | static const u32 hpd_ivb[HPD_NUM_PINS] = { |
53 | [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, | |
54 | }; | |
55 | ||
3a3b3c7d VS |
56 | static const u32 hpd_bdw[HPD_NUM_PINS] = { |
57 | [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG, | |
58 | }; | |
59 | ||
7c7e10db | 60 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
e5868a31 EE |
61 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
62 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
63 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
64 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
65 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
66 | }; | |
67 | ||
7c7e10db | 68 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
e5868a31 | 69 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
73c352a2 | 70 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
71 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
72 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
73 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
74 | }; | |
75 | ||
26951caf XZ |
76 | static const u32 hpd_spt[HPD_NUM_PINS] = { |
77 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, | |
78 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
79 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, | |
80 | [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT | |
81 | }; | |
82 | ||
7c7e10db | 83 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
84 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
85 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
86 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
87 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
88 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
89 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
90 | }; | |
91 | ||
7c7e10db | 92 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
e5868a31 EE |
93 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
94 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
95 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
96 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
97 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
98 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
99 | }; | |
100 | ||
4bca26d0 | 101 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
102 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
103 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
104 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
105 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
106 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
107 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
108 | }; | |
109 | ||
e0a20ad7 SS |
110 | /* BXT hpd list */ |
111 | static const u32 hpd_bxt[HPD_NUM_PINS] = { | |
7f3561be | 112 | [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, |
e0a20ad7 SS |
113 | [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, |
114 | [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC | |
115 | }; | |
116 | ||
5c502442 | 117 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 118 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
119 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
120 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
121 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
122 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
123 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
124 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
125 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
126 | } while (0) | |
127 | ||
f86f3fb0 | 128 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 129 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 130 | POSTING_READ(type##IMR); \ |
a9d356a6 | 131 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
132 | I915_WRITE(type##IIR, 0xffffffff); \ |
133 | POSTING_READ(type##IIR); \ | |
134 | I915_WRITE(type##IIR, 0xffffffff); \ | |
135 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
136 | } while (0) |
137 | ||
337ba017 PZ |
138 | /* |
139 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
140 | */ | |
141 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
142 | u32 val = I915_READ(reg); \ | |
143 | if (val) { \ | |
144 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
145 | (reg), val); \ | |
146 | I915_WRITE((reg), 0xffffffff); \ | |
147 | POSTING_READ(reg); \ | |
148 | I915_WRITE((reg), 0xffffffff); \ | |
149 | POSTING_READ(reg); \ | |
150 | } \ | |
151 | } while (0) | |
152 | ||
35079899 | 153 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 154 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 | 155 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
156 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
157 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
158 | } while (0) |
159 | ||
160 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 161 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 | 162 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
163 | I915_WRITE(type##IMR, (imr_val)); \ |
164 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
165 | } while (0) |
166 | ||
c9a9a268 ID |
167 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
168 | ||
d9dc34f1 VS |
169 | /** |
170 | * ilk_update_display_irq - update DEIMR | |
171 | * @dev_priv: driver private | |
172 | * @interrupt_mask: mask of interrupt bits to update | |
173 | * @enabled_irq_mask: mask of interrupt bits to enable | |
174 | */ | |
175 | static void ilk_update_display_irq(struct drm_i915_private *dev_priv, | |
176 | uint32_t interrupt_mask, | |
177 | uint32_t enabled_irq_mask) | |
036a4a7d | 178 | { |
d9dc34f1 VS |
179 | uint32_t new_val; |
180 | ||
4bc9d430 DV |
181 | assert_spin_locked(&dev_priv->irq_lock); |
182 | ||
d9dc34f1 VS |
183 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
184 | ||
9df7575f | 185 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 186 | return; |
c67a470b | 187 | |
d9dc34f1 VS |
188 | new_val = dev_priv->irq_mask; |
189 | new_val &= ~interrupt_mask; | |
190 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
191 | ||
192 | if (new_val != dev_priv->irq_mask) { | |
193 | dev_priv->irq_mask = new_val; | |
1ec14ad3 | 194 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
3143a2bf | 195 | POSTING_READ(DEIMR); |
036a4a7d ZW |
196 | } |
197 | } | |
198 | ||
47339cd9 | 199 | void |
d9dc34f1 | 200 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 201 | { |
d9dc34f1 VS |
202 | ilk_update_display_irq(dev_priv, mask, mask); |
203 | } | |
c67a470b | 204 | |
d9dc34f1 VS |
205 | void |
206 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) | |
207 | { | |
208 | ilk_update_display_irq(dev_priv, mask, 0); | |
036a4a7d ZW |
209 | } |
210 | ||
43eaea13 PZ |
211 | /** |
212 | * ilk_update_gt_irq - update GTIMR | |
213 | * @dev_priv: driver private | |
214 | * @interrupt_mask: mask of interrupt bits to update | |
215 | * @enabled_irq_mask: mask of interrupt bits to enable | |
216 | */ | |
217 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
218 | uint32_t interrupt_mask, | |
219 | uint32_t enabled_irq_mask) | |
220 | { | |
221 | assert_spin_locked(&dev_priv->irq_lock); | |
222 | ||
15a17aae DV |
223 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
224 | ||
9df7575f | 225 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 226 | return; |
c67a470b | 227 | |
43eaea13 PZ |
228 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
229 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
230 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
231 | POSTING_READ(GTIMR); | |
232 | } | |
233 | ||
480c8033 | 234 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
235 | { |
236 | ilk_update_gt_irq(dev_priv, mask, mask); | |
237 | } | |
238 | ||
480c8033 | 239 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
240 | { |
241 | ilk_update_gt_irq(dev_priv, mask, 0); | |
242 | } | |
243 | ||
b900b949 ID |
244 | static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) |
245 | { | |
246 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
247 | } | |
248 | ||
a72fbc3a ID |
249 | static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) |
250 | { | |
251 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
252 | } | |
253 | ||
b900b949 ID |
254 | static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) |
255 | { | |
256 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
257 | } | |
258 | ||
edbfdb45 PZ |
259 | /** |
260 | * snb_update_pm_irq - update GEN6_PMIMR | |
261 | * @dev_priv: driver private | |
262 | * @interrupt_mask: mask of interrupt bits to update | |
263 | * @enabled_irq_mask: mask of interrupt bits to enable | |
264 | */ | |
265 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
266 | uint32_t interrupt_mask, | |
267 | uint32_t enabled_irq_mask) | |
268 | { | |
605cd25b | 269 | uint32_t new_val; |
edbfdb45 | 270 | |
15a17aae DV |
271 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
272 | ||
edbfdb45 PZ |
273 | assert_spin_locked(&dev_priv->irq_lock); |
274 | ||
605cd25b | 275 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
276 | new_val &= ~interrupt_mask; |
277 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
278 | ||
605cd25b PZ |
279 | if (new_val != dev_priv->pm_irq_mask) { |
280 | dev_priv->pm_irq_mask = new_val; | |
a72fbc3a ID |
281 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
282 | POSTING_READ(gen6_pm_imr(dev_priv)); | |
f52ecbcf | 283 | } |
edbfdb45 PZ |
284 | } |
285 | ||
480c8033 | 286 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 | 287 | { |
9939fba2 ID |
288 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
289 | return; | |
290 | ||
edbfdb45 PZ |
291 | snb_update_pm_irq(dev_priv, mask, mask); |
292 | } | |
293 | ||
9939fba2 ID |
294 | static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, |
295 | uint32_t mask) | |
edbfdb45 PZ |
296 | { |
297 | snb_update_pm_irq(dev_priv, mask, 0); | |
298 | } | |
299 | ||
9939fba2 ID |
300 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
301 | { | |
302 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
303 | return; | |
304 | ||
305 | __gen6_disable_pm_irq(dev_priv, mask); | |
306 | } | |
307 | ||
3cc134e3 ID |
308 | void gen6_reset_rps_interrupts(struct drm_device *dev) |
309 | { | |
310 | struct drm_i915_private *dev_priv = dev->dev_private; | |
311 | uint32_t reg = gen6_pm_iir(dev_priv); | |
312 | ||
313 | spin_lock_irq(&dev_priv->irq_lock); | |
314 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
315 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
316 | POSTING_READ(reg); | |
096fad9e | 317 | dev_priv->rps.pm_iir = 0; |
3cc134e3 ID |
318 | spin_unlock_irq(&dev_priv->irq_lock); |
319 | } | |
320 | ||
b900b949 ID |
321 | void gen6_enable_rps_interrupts(struct drm_device *dev) |
322 | { | |
323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
324 | ||
325 | spin_lock_irq(&dev_priv->irq_lock); | |
78e68d36 | 326 | |
b900b949 | 327 | WARN_ON(dev_priv->rps.pm_iir); |
3cc134e3 | 328 | WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
d4d70aa5 | 329 | dev_priv->rps.interrupts_enabled = true; |
78e68d36 ID |
330 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | |
331 | dev_priv->pm_rps_events); | |
b900b949 | 332 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 333 | |
b900b949 ID |
334 | spin_unlock_irq(&dev_priv->irq_lock); |
335 | } | |
336 | ||
59d02a1f ID |
337 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) |
338 | { | |
339 | /* | |
f24eeb19 | 340 | * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer |
59d02a1f | 341 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
f24eeb19 ID |
342 | * |
343 | * TODO: verify if this can be reproduced on VLV,CHV. | |
59d02a1f ID |
344 | */ |
345 | if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) | |
346 | mask &= ~GEN6_PM_RP_UP_EI_EXPIRED; | |
347 | ||
348 | if (INTEL_INFO(dev_priv)->gen >= 8) | |
349 | mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
350 | ||
351 | return mask; | |
352 | } | |
353 | ||
b900b949 ID |
354 | void gen6_disable_rps_interrupts(struct drm_device *dev) |
355 | { | |
356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
357 | ||
d4d70aa5 ID |
358 | spin_lock_irq(&dev_priv->irq_lock); |
359 | dev_priv->rps.interrupts_enabled = false; | |
360 | spin_unlock_irq(&dev_priv->irq_lock); | |
361 | ||
362 | cancel_work_sync(&dev_priv->rps.work); | |
363 | ||
9939fba2 ID |
364 | spin_lock_irq(&dev_priv->irq_lock); |
365 | ||
59d02a1f | 366 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); |
9939fba2 ID |
367 | |
368 | __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
b900b949 ID |
369 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & |
370 | ~dev_priv->pm_rps_events); | |
58072ccb ID |
371 | |
372 | spin_unlock_irq(&dev_priv->irq_lock); | |
373 | ||
374 | synchronize_irq(dev->irq); | |
b900b949 ID |
375 | } |
376 | ||
3a3b3c7d VS |
377 | /** |
378 | * bdw_update_port_irq - update DE port interrupt | |
379 | * @dev_priv: driver private | |
380 | * @interrupt_mask: mask of interrupt bits to update | |
381 | * @enabled_irq_mask: mask of interrupt bits to enable | |
382 | */ | |
383 | static void bdw_update_port_irq(struct drm_i915_private *dev_priv, | |
384 | uint32_t interrupt_mask, | |
385 | uint32_t enabled_irq_mask) | |
386 | { | |
387 | uint32_t new_val; | |
388 | uint32_t old_val; | |
389 | ||
390 | assert_spin_locked(&dev_priv->irq_lock); | |
391 | ||
392 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
393 | ||
394 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
395 | return; | |
396 | ||
397 | old_val = I915_READ(GEN8_DE_PORT_IMR); | |
398 | ||
399 | new_val = old_val; | |
400 | new_val &= ~interrupt_mask; | |
401 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
402 | ||
403 | if (new_val != old_val) { | |
404 | I915_WRITE(GEN8_DE_PORT_IMR, new_val); | |
405 | POSTING_READ(GEN8_DE_PORT_IMR); | |
406 | } | |
407 | } | |
408 | ||
fee884ed DV |
409 | /** |
410 | * ibx_display_interrupt_update - update SDEIMR | |
411 | * @dev_priv: driver private | |
412 | * @interrupt_mask: mask of interrupt bits to update | |
413 | * @enabled_irq_mask: mask of interrupt bits to enable | |
414 | */ | |
47339cd9 DV |
415 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
416 | uint32_t interrupt_mask, | |
417 | uint32_t enabled_irq_mask) | |
fee884ed DV |
418 | { |
419 | uint32_t sdeimr = I915_READ(SDEIMR); | |
420 | sdeimr &= ~interrupt_mask; | |
421 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
422 | ||
15a17aae DV |
423 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
424 | ||
fee884ed DV |
425 | assert_spin_locked(&dev_priv->irq_lock); |
426 | ||
9df7575f | 427 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 428 | return; |
c67a470b | 429 | |
fee884ed DV |
430 | I915_WRITE(SDEIMR, sdeimr); |
431 | POSTING_READ(SDEIMR); | |
432 | } | |
8664281b | 433 | |
b5ea642a | 434 | static void |
755e9019 ID |
435 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
436 | u32 enable_mask, u32 status_mask) | |
7c463586 | 437 | { |
46c06a30 | 438 | u32 reg = PIPESTAT(pipe); |
755e9019 | 439 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 440 | |
b79480ba | 441 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 442 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 443 | |
04feced9 VS |
444 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
445 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
446 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
447 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
448 | return; |
449 | ||
450 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
451 | return; |
452 | ||
91d181dd ID |
453 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
454 | ||
46c06a30 | 455 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 456 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
457 | I915_WRITE(reg, pipestat); |
458 | POSTING_READ(reg); | |
7c463586 KP |
459 | } |
460 | ||
b5ea642a | 461 | static void |
755e9019 ID |
462 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
463 | u32 enable_mask, u32 status_mask) | |
7c463586 | 464 | { |
46c06a30 | 465 | u32 reg = PIPESTAT(pipe); |
755e9019 | 466 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 467 | |
b79480ba | 468 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 469 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 470 | |
04feced9 VS |
471 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
472 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
473 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
474 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
475 | return; |
476 | ||
755e9019 ID |
477 | if ((pipestat & enable_mask) == 0) |
478 | return; | |
479 | ||
91d181dd ID |
480 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
481 | ||
755e9019 | 482 | pipestat &= ~enable_mask; |
46c06a30 VS |
483 | I915_WRITE(reg, pipestat); |
484 | POSTING_READ(reg); | |
7c463586 KP |
485 | } |
486 | ||
10c59c51 ID |
487 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
488 | { | |
489 | u32 enable_mask = status_mask << 16; | |
490 | ||
491 | /* | |
724a6905 VS |
492 | * On pipe A we don't support the PSR interrupt yet, |
493 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
494 | */ |
495 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
496 | return 0; | |
724a6905 VS |
497 | /* |
498 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
499 | * A the same bit is for perf counters which we don't use either. | |
500 | */ | |
501 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
502 | return 0; | |
10c59c51 ID |
503 | |
504 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
505 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
506 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
507 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
508 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
509 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
510 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
511 | ||
512 | return enable_mask; | |
513 | } | |
514 | ||
755e9019 ID |
515 | void |
516 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
517 | u32 status_mask) | |
518 | { | |
519 | u32 enable_mask; | |
520 | ||
10c59c51 ID |
521 | if (IS_VALLEYVIEW(dev_priv->dev)) |
522 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
523 | status_mask); | |
524 | else | |
525 | enable_mask = status_mask << 16; | |
755e9019 ID |
526 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
527 | } | |
528 | ||
529 | void | |
530 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
531 | u32 status_mask) | |
532 | { | |
533 | u32 enable_mask; | |
534 | ||
10c59c51 ID |
535 | if (IS_VALLEYVIEW(dev_priv->dev)) |
536 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
537 | status_mask); | |
538 | else | |
539 | enable_mask = status_mask << 16; | |
755e9019 ID |
540 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
541 | } | |
542 | ||
01c66889 | 543 | /** |
f49e38dd | 544 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 545 | */ |
f49e38dd | 546 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 547 | { |
2d1013dd | 548 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 549 | |
f49e38dd JN |
550 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
551 | return; | |
552 | ||
13321786 | 553 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 554 | |
755e9019 | 555 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 556 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 557 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 558 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 559 | |
13321786 | 560 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
561 | } |
562 | ||
f75f3746 VS |
563 | /* |
564 | * This timing diagram depicts the video signal in and | |
565 | * around the vertical blanking period. | |
566 | * | |
567 | * Assumptions about the fictitious mode used in this example: | |
568 | * vblank_start >= 3 | |
569 | * vsync_start = vblank_start + 1 | |
570 | * vsync_end = vblank_start + 2 | |
571 | * vtotal = vblank_start + 3 | |
572 | * | |
573 | * start of vblank: | |
574 | * latch double buffered registers | |
575 | * increment frame counter (ctg+) | |
576 | * generate start of vblank interrupt (gen4+) | |
577 | * | | |
578 | * | frame start: | |
579 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
580 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
581 | * | | | |
582 | * | | start of vsync: | |
583 | * | | generate vsync interrupt | |
584 | * | | | | |
585 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
586 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
587 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
588 | * | | <----vs-----> | | |
589 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
590 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
591 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
592 | * | | | | |
593 | * last visible pixel first visible pixel | |
594 | * | increment frame counter (gen3/4) | |
595 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
596 | * | |
597 | * x = horizontal active | |
598 | * _ = horizontal blanking | |
599 | * hs = horizontal sync | |
600 | * va = vertical active | |
601 | * vb = vertical blanking | |
602 | * vs = vertical sync | |
603 | * vbs = vblank_start (number) | |
604 | * | |
605 | * Summary: | |
606 | * - most events happen at the start of horizontal sync | |
607 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
608 | * (depending on PIPECONF settings) after the start of vblank | |
609 | * - gen3/4 pixel and frame counter are synchronized with the start | |
610 | * of horizontal active on the first line of vertical active | |
611 | */ | |
612 | ||
4cdb83ec VS |
613 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
614 | { | |
615 | /* Gen2 doesn't have a hardware frame counter */ | |
616 | return 0; | |
617 | } | |
618 | ||
42f52ef8 KP |
619 | /* Called from drm generic code, passed a 'crtc', which |
620 | * we use as a pipe index | |
621 | */ | |
f71d4af4 | 622 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 623 | { |
2d1013dd | 624 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
625 | unsigned long high_frame; |
626 | unsigned long low_frame; | |
0b2a8e09 | 627 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
f3a5c3f6 DV |
628 | struct intel_crtc *intel_crtc = |
629 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
fc467a22 | 630 | const struct drm_display_mode *mode = &intel_crtc->base.hwmode; |
0a3e67a4 | 631 | |
f3a5c3f6 DV |
632 | htotal = mode->crtc_htotal; |
633 | hsync_start = mode->crtc_hsync_start; | |
634 | vbl_start = mode->crtc_vblank_start; | |
635 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
636 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 637 | |
0b2a8e09 VS |
638 | /* Convert to pixel count */ |
639 | vbl_start *= htotal; | |
640 | ||
641 | /* Start of vblank event occurs at start of hsync */ | |
642 | vbl_start -= htotal - hsync_start; | |
643 | ||
9db4a9c7 JB |
644 | high_frame = PIPEFRAME(pipe); |
645 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 646 | |
0a3e67a4 JB |
647 | /* |
648 | * High & low register fields aren't synchronized, so make sure | |
649 | * we get a low value that's stable across two reads of the high | |
650 | * register. | |
651 | */ | |
652 | do { | |
5eddb70b | 653 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 654 | low = I915_READ(low_frame); |
5eddb70b | 655 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
656 | } while (high1 != high2); |
657 | ||
5eddb70b | 658 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 659 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 660 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
661 | |
662 | /* | |
663 | * The frame counter increments at beginning of active. | |
664 | * Cook up a vblank counter by also checking the pixel | |
665 | * counter against vblank start. | |
666 | */ | |
edc08d0a | 667 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
668 | } |
669 | ||
f71d4af4 | 670 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 671 | { |
2d1013dd | 672 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 673 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 | 674 | |
9880b7a5 JB |
675 | return I915_READ(reg); |
676 | } | |
677 | ||
ad3543ed MK |
678 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
679 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 680 | |
a225f079 VS |
681 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
682 | { | |
683 | struct drm_device *dev = crtc->base.dev; | |
684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fc467a22 | 685 | const struct drm_display_mode *mode = &crtc->base.hwmode; |
a225f079 | 686 | enum pipe pipe = crtc->pipe; |
80715b2f | 687 | int position, vtotal; |
a225f079 | 688 | |
80715b2f | 689 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
690 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
691 | vtotal /= 2; | |
692 | ||
693 | if (IS_GEN2(dev)) | |
694 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
695 | else | |
696 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
697 | ||
698 | /* | |
80715b2f VS |
699 | * See update_scanline_offset() for the details on the |
700 | * scanline_offset adjustment. | |
a225f079 | 701 | */ |
80715b2f | 702 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
703 | } |
704 | ||
f71d4af4 | 705 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
706 | unsigned int flags, int *vpos, int *hpos, |
707 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 708 | { |
c2baf4b7 VS |
709 | struct drm_i915_private *dev_priv = dev->dev_private; |
710 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
711 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
fc467a22 | 712 | const struct drm_display_mode *mode = &intel_crtc->base.hwmode; |
3aa18df8 | 713 | int position; |
78e8fc6b | 714 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
715 | bool in_vbl = true; |
716 | int ret = 0; | |
ad3543ed | 717 | unsigned long irqflags; |
0af7e4df | 718 | |
fc467a22 | 719 | if (WARN_ON(!mode->crtc_clock)) { |
0af7e4df | 720 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 721 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
722 | return 0; |
723 | } | |
724 | ||
c2baf4b7 | 725 | htotal = mode->crtc_htotal; |
78e8fc6b | 726 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
727 | vtotal = mode->crtc_vtotal; |
728 | vbl_start = mode->crtc_vblank_start; | |
729 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 730 | |
d31faf65 VS |
731 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
732 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
733 | vbl_end /= 2; | |
734 | vtotal /= 2; | |
735 | } | |
736 | ||
c2baf4b7 VS |
737 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
738 | ||
ad3543ed MK |
739 | /* |
740 | * Lock uncore.lock, as we will do multiple timing critical raw | |
741 | * register reads, potentially with preemption disabled, so the | |
742 | * following code must not block on uncore.lock. | |
743 | */ | |
744 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 745 | |
ad3543ed MK |
746 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
747 | ||
748 | /* Get optional system timestamp before query. */ | |
749 | if (stime) | |
750 | *stime = ktime_get(); | |
751 | ||
7c06b08a | 752 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
753 | /* No obvious pixelcount register. Only query vertical |
754 | * scanout position from Display scan line register. | |
755 | */ | |
a225f079 | 756 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
757 | } else { |
758 | /* Have access to pixelcount since start of frame. | |
759 | * We can split this into vertical and horizontal | |
760 | * scanout position. | |
761 | */ | |
ad3543ed | 762 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 763 | |
3aa18df8 VS |
764 | /* convert to pixel counts */ |
765 | vbl_start *= htotal; | |
766 | vbl_end *= htotal; | |
767 | vtotal *= htotal; | |
78e8fc6b | 768 | |
7e78f1cb VS |
769 | /* |
770 | * In interlaced modes, the pixel counter counts all pixels, | |
771 | * so one field will have htotal more pixels. In order to avoid | |
772 | * the reported position from jumping backwards when the pixel | |
773 | * counter is beyond the length of the shorter field, just | |
774 | * clamp the position the length of the shorter field. This | |
775 | * matches how the scanline counter based position works since | |
776 | * the scanline counter doesn't count the two half lines. | |
777 | */ | |
778 | if (position >= vtotal) | |
779 | position = vtotal - 1; | |
780 | ||
78e8fc6b VS |
781 | /* |
782 | * Start of vblank interrupt is triggered at start of hsync, | |
783 | * just prior to the first active line of vblank. However we | |
784 | * consider lines to start at the leading edge of horizontal | |
785 | * active. So, should we get here before we've crossed into | |
786 | * the horizontal active of the first line in vblank, we would | |
787 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
788 | * always add htotal-hsync_start to the current pixel position. | |
789 | */ | |
790 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
791 | } |
792 | ||
ad3543ed MK |
793 | /* Get optional system timestamp after query. */ |
794 | if (etime) | |
795 | *etime = ktime_get(); | |
796 | ||
797 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
798 | ||
799 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
800 | ||
3aa18df8 VS |
801 | in_vbl = position >= vbl_start && position < vbl_end; |
802 | ||
803 | /* | |
804 | * While in vblank, position will be negative | |
805 | * counting up towards 0 at vbl_end. And outside | |
806 | * vblank, position will be positive counting | |
807 | * up since vbl_end. | |
808 | */ | |
809 | if (position >= vbl_start) | |
810 | position -= vbl_end; | |
811 | else | |
812 | position += vtotal - vbl_end; | |
0af7e4df | 813 | |
7c06b08a | 814 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
815 | *vpos = position; |
816 | *hpos = 0; | |
817 | } else { | |
818 | *vpos = position / htotal; | |
819 | *hpos = position - (*vpos * htotal); | |
820 | } | |
0af7e4df | 821 | |
0af7e4df MK |
822 | /* In vblank? */ |
823 | if (in_vbl) | |
3d3cbd84 | 824 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
825 | |
826 | return ret; | |
827 | } | |
828 | ||
a225f079 VS |
829 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
830 | { | |
831 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
832 | unsigned long irqflags; | |
833 | int position; | |
834 | ||
835 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
836 | position = __intel_get_crtc_scanline(crtc); | |
837 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
838 | ||
839 | return position; | |
840 | } | |
841 | ||
f71d4af4 | 842 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
843 | int *max_error, |
844 | struct timeval *vblank_time, | |
845 | unsigned flags) | |
846 | { | |
4041b853 | 847 | struct drm_crtc *crtc; |
0af7e4df | 848 | |
7eb552ae | 849 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 850 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
851 | return -EINVAL; |
852 | } | |
853 | ||
854 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
855 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
856 | if (crtc == NULL) { | |
857 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
858 | return -EINVAL; | |
859 | } | |
860 | ||
fc467a22 | 861 | if (!crtc->hwmode.crtc_clock) { |
4041b853 CW |
862 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
863 | return -EBUSY; | |
864 | } | |
0af7e4df MK |
865 | |
866 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
867 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
868 | vblank_time, flags, | |
7da903ef | 869 | crtc, |
fc467a22 | 870 | &crtc->hwmode); |
0af7e4df MK |
871 | } |
872 | ||
d0ecd7e2 | 873 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 874 | { |
2d1013dd | 875 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 876 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 877 | u8 new_delay; |
9270388e | 878 | |
d0ecd7e2 | 879 | spin_lock(&mchdev_lock); |
f97108d1 | 880 | |
73edd18f DV |
881 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
882 | ||
20e4d407 | 883 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 884 | |
7648fa99 | 885 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
886 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
887 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
888 | max_avg = I915_READ(RCBMAXAVG); |
889 | min_avg = I915_READ(RCBMINAVG); | |
890 | ||
891 | /* Handle RCS change request from hw */ | |
b5b72e89 | 892 | if (busy_up > max_avg) { |
20e4d407 DV |
893 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
894 | new_delay = dev_priv->ips.cur_delay - 1; | |
895 | if (new_delay < dev_priv->ips.max_delay) | |
896 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 897 | } else if (busy_down < min_avg) { |
20e4d407 DV |
898 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
899 | new_delay = dev_priv->ips.cur_delay + 1; | |
900 | if (new_delay > dev_priv->ips.min_delay) | |
901 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
902 | } |
903 | ||
7648fa99 | 904 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 905 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 906 | |
d0ecd7e2 | 907 | spin_unlock(&mchdev_lock); |
9270388e | 908 | |
f97108d1 JB |
909 | return; |
910 | } | |
911 | ||
74cdb337 | 912 | static void notify_ring(struct intel_engine_cs *ring) |
549f7365 | 913 | { |
93b0a4e0 | 914 | if (!intel_ring_initialized(ring)) |
475553de CW |
915 | return; |
916 | ||
bcfcc8ba | 917 | trace_i915_gem_request_notify(ring); |
9862e600 | 918 | |
549f7365 | 919 | wake_up_all(&ring->irq_queue); |
549f7365 CW |
920 | } |
921 | ||
43cf3bf0 CW |
922 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
923 | struct intel_rps_ei *ei) | |
31685c25 | 924 | { |
43cf3bf0 CW |
925 | ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); |
926 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); | |
927 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); | |
928 | } | |
31685c25 | 929 | |
43cf3bf0 CW |
930 | static bool vlv_c0_above(struct drm_i915_private *dev_priv, |
931 | const struct intel_rps_ei *old, | |
932 | const struct intel_rps_ei *now, | |
933 | int threshold) | |
934 | { | |
935 | u64 time, c0; | |
31685c25 | 936 | |
43cf3bf0 CW |
937 | if (old->cz_clock == 0) |
938 | return false; | |
31685c25 | 939 | |
43cf3bf0 CW |
940 | time = now->cz_clock - old->cz_clock; |
941 | time *= threshold * dev_priv->mem_freq; | |
31685c25 | 942 | |
43cf3bf0 CW |
943 | /* Workload can be split between render + media, e.g. SwapBuffers |
944 | * being blitted in X after being rendered in mesa. To account for | |
945 | * this we need to combine both engines into our activity counter. | |
31685c25 | 946 | */ |
43cf3bf0 CW |
947 | c0 = now->render_c0 - old->render_c0; |
948 | c0 += now->media_c0 - old->media_c0; | |
949 | c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000; | |
31685c25 | 950 | |
43cf3bf0 | 951 | return c0 >= time; |
31685c25 D |
952 | } |
953 | ||
43cf3bf0 | 954 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
31685c25 | 955 | { |
43cf3bf0 CW |
956 | vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); |
957 | dev_priv->rps.up_ei = dev_priv->rps.down_ei; | |
43cf3bf0 | 958 | } |
31685c25 | 959 | |
43cf3bf0 CW |
960 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
961 | { | |
962 | struct intel_rps_ei now; | |
963 | u32 events = 0; | |
31685c25 | 964 | |
6f4b12f8 | 965 | if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0) |
43cf3bf0 | 966 | return 0; |
31685c25 | 967 | |
43cf3bf0 CW |
968 | vlv_c0_read(dev_priv, &now); |
969 | if (now.cz_clock == 0) | |
970 | return 0; | |
31685c25 | 971 | |
43cf3bf0 CW |
972 | if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { |
973 | if (!vlv_c0_above(dev_priv, | |
974 | &dev_priv->rps.down_ei, &now, | |
8fb55197 | 975 | dev_priv->rps.down_threshold)) |
43cf3bf0 CW |
976 | events |= GEN6_PM_RP_DOWN_THRESHOLD; |
977 | dev_priv->rps.down_ei = now; | |
978 | } | |
31685c25 | 979 | |
43cf3bf0 CW |
980 | if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
981 | if (vlv_c0_above(dev_priv, | |
982 | &dev_priv->rps.up_ei, &now, | |
8fb55197 | 983 | dev_priv->rps.up_threshold)) |
43cf3bf0 CW |
984 | events |= GEN6_PM_RP_UP_THRESHOLD; |
985 | dev_priv->rps.up_ei = now; | |
31685c25 D |
986 | } |
987 | ||
43cf3bf0 | 988 | return events; |
31685c25 D |
989 | } |
990 | ||
f5a4c67d CW |
991 | static bool any_waiters(struct drm_i915_private *dev_priv) |
992 | { | |
993 | struct intel_engine_cs *ring; | |
994 | int i; | |
995 | ||
996 | for_each_ring(ring, dev_priv, i) | |
997 | if (ring->irq_refcount) | |
998 | return true; | |
999 | ||
1000 | return false; | |
1001 | } | |
1002 | ||
4912d041 | 1003 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1004 | { |
2d1013dd JN |
1005 | struct drm_i915_private *dev_priv = |
1006 | container_of(work, struct drm_i915_private, rps.work); | |
8d3afd7d CW |
1007 | bool client_boost; |
1008 | int new_delay, adj, min, max; | |
edbfdb45 | 1009 | u32 pm_iir; |
4912d041 | 1010 | |
59cdb63d | 1011 | spin_lock_irq(&dev_priv->irq_lock); |
d4d70aa5 ID |
1012 | /* Speed up work cancelation during disabling rps interrupts. */ |
1013 | if (!dev_priv->rps.interrupts_enabled) { | |
1014 | spin_unlock_irq(&dev_priv->irq_lock); | |
1015 | return; | |
1016 | } | |
c6a828d3 DV |
1017 | pm_iir = dev_priv->rps.pm_iir; |
1018 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a ID |
1019 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
1020 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
8d3afd7d CW |
1021 | client_boost = dev_priv->rps.client_boost; |
1022 | dev_priv->rps.client_boost = false; | |
59cdb63d | 1023 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1024 | |
60611c13 | 1025 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1026 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1027 | |
8d3afd7d | 1028 | if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) |
3b8d8d91 JB |
1029 | return; |
1030 | ||
4fc688ce | 1031 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1032 | |
43cf3bf0 CW |
1033 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
1034 | ||
dd75fdc8 | 1035 | adj = dev_priv->rps.last_adj; |
edcf284b | 1036 | new_delay = dev_priv->rps.cur_freq; |
8d3afd7d CW |
1037 | min = dev_priv->rps.min_freq_softlimit; |
1038 | max = dev_priv->rps.max_freq_softlimit; | |
1039 | ||
1040 | if (client_boost) { | |
1041 | new_delay = dev_priv->rps.max_freq_softlimit; | |
1042 | adj = 0; | |
1043 | } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
dd75fdc8 CW |
1044 | if (adj > 0) |
1045 | adj *= 2; | |
edcf284b CW |
1046 | else /* CHV needs even encode values */ |
1047 | adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; | |
7425034a VS |
1048 | /* |
1049 | * For better performance, jump directly | |
1050 | * to RPe if we're below it. | |
1051 | */ | |
edcf284b | 1052 | if (new_delay < dev_priv->rps.efficient_freq - adj) { |
b39fb297 | 1053 | new_delay = dev_priv->rps.efficient_freq; |
edcf284b CW |
1054 | adj = 0; |
1055 | } | |
f5a4c67d CW |
1056 | } else if (any_waiters(dev_priv)) { |
1057 | adj = 0; | |
dd75fdc8 | 1058 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1059 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1060 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1061 | else |
b39fb297 | 1062 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1063 | adj = 0; |
1064 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1065 | if (adj < 0) | |
1066 | adj *= 2; | |
edcf284b CW |
1067 | else /* CHV needs even encode values */ |
1068 | adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; | |
dd75fdc8 | 1069 | } else { /* unknown event */ |
edcf284b | 1070 | adj = 0; |
dd75fdc8 | 1071 | } |
3b8d8d91 | 1072 | |
edcf284b CW |
1073 | dev_priv->rps.last_adj = adj; |
1074 | ||
79249636 BW |
1075 | /* sysfs frequency interfaces may have snuck in while servicing the |
1076 | * interrupt | |
1077 | */ | |
edcf284b | 1078 | new_delay += adj; |
8d3afd7d | 1079 | new_delay = clamp_t(int, new_delay, min, max); |
27544369 | 1080 | |
ffe02b40 | 1081 | intel_set_rps(dev_priv->dev, new_delay); |
3b8d8d91 | 1082 | |
4fc688ce | 1083 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1084 | } |
1085 | ||
e3689190 BW |
1086 | |
1087 | /** | |
1088 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1089 | * occurred. | |
1090 | * @work: workqueue struct | |
1091 | * | |
1092 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1093 | * this event, userspace should try to remap the bad rows since statistically | |
1094 | * it is likely the same row is more likely to go bad again. | |
1095 | */ | |
1096 | static void ivybridge_parity_work(struct work_struct *work) | |
1097 | { | |
2d1013dd JN |
1098 | struct drm_i915_private *dev_priv = |
1099 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1100 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1101 | char *parity_event[6]; |
e3689190 | 1102 | uint32_t misccpctl; |
35a85ac6 | 1103 | uint8_t slice = 0; |
e3689190 BW |
1104 | |
1105 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1106 | * In order to prevent a get/put style interface, acquire struct mutex | |
1107 | * any time we access those registers. | |
1108 | */ | |
1109 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1110 | ||
35a85ac6 BW |
1111 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1112 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1113 | goto out; | |
1114 | ||
e3689190 BW |
1115 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1116 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1117 | POSTING_READ(GEN7_MISCCPCTL); | |
1118 | ||
35a85ac6 BW |
1119 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1120 | u32 reg; | |
e3689190 | 1121 | |
35a85ac6 BW |
1122 | slice--; |
1123 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1124 | break; | |
e3689190 | 1125 | |
35a85ac6 | 1126 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1127 | |
35a85ac6 | 1128 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1129 | |
35a85ac6 BW |
1130 | error_status = I915_READ(reg); |
1131 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1132 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1133 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1134 | ||
1135 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1136 | POSTING_READ(reg); | |
1137 | ||
1138 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1139 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1140 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1141 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1142 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1143 | parity_event[5] = NULL; | |
1144 | ||
5bdebb18 | 1145 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1146 | KOBJ_CHANGE, parity_event); |
e3689190 | 1147 | |
35a85ac6 BW |
1148 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1149 | slice, row, bank, subbank); | |
e3689190 | 1150 | |
35a85ac6 BW |
1151 | kfree(parity_event[4]); |
1152 | kfree(parity_event[3]); | |
1153 | kfree(parity_event[2]); | |
1154 | kfree(parity_event[1]); | |
1155 | } | |
e3689190 | 1156 | |
35a85ac6 | 1157 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1158 | |
35a85ac6 BW |
1159 | out: |
1160 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1161 | spin_lock_irq(&dev_priv->irq_lock); |
480c8033 | 1162 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
4cb21832 | 1163 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1164 | |
1165 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1166 | } |
1167 | ||
35a85ac6 | 1168 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1169 | { |
2d1013dd | 1170 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1171 | |
040d2baa | 1172 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1173 | return; |
1174 | ||
d0ecd7e2 | 1175 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1176 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1177 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1178 | |
35a85ac6 BW |
1179 | iir &= GT_PARITY_ERROR(dev); |
1180 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1181 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1182 | ||
1183 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1184 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1185 | ||
a4da4fa4 | 1186 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1187 | } |
1188 | ||
f1af8fc1 PZ |
1189 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1190 | struct drm_i915_private *dev_priv, | |
1191 | u32 gt_iir) | |
1192 | { | |
1193 | if (gt_iir & | |
1194 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
74cdb337 | 1195 | notify_ring(&dev_priv->ring[RCS]); |
f1af8fc1 | 1196 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
74cdb337 | 1197 | notify_ring(&dev_priv->ring[VCS]); |
f1af8fc1 PZ |
1198 | } |
1199 | ||
e7b4c6b1 DV |
1200 | static void snb_gt_irq_handler(struct drm_device *dev, |
1201 | struct drm_i915_private *dev_priv, | |
1202 | u32 gt_iir) | |
1203 | { | |
1204 | ||
cc609d5d BW |
1205 | if (gt_iir & |
1206 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
74cdb337 | 1207 | notify_ring(&dev_priv->ring[RCS]); |
cc609d5d | 1208 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
74cdb337 | 1209 | notify_ring(&dev_priv->ring[VCS]); |
cc609d5d | 1210 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
74cdb337 | 1211 | notify_ring(&dev_priv->ring[BCS]); |
e7b4c6b1 | 1212 | |
cc609d5d BW |
1213 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1214 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1215 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1216 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1217 | |
35a85ac6 BW |
1218 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1219 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1220 | } |
1221 | ||
74cdb337 | 1222 | static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv, |
abd58f01 BW |
1223 | u32 master_ctl) |
1224 | { | |
abd58f01 BW |
1225 | irqreturn_t ret = IRQ_NONE; |
1226 | ||
1227 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
74cdb337 | 1228 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(0)); |
abd58f01 | 1229 | if (tmp) { |
cb0d205e | 1230 | I915_WRITE_FW(GEN8_GT_IIR(0), tmp); |
abd58f01 | 1231 | ret = IRQ_HANDLED; |
e981e7b1 | 1232 | |
74cdb337 CW |
1233 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT)) |
1234 | intel_lrc_irq_handler(&dev_priv->ring[RCS]); | |
1235 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT)) | |
1236 | notify_ring(&dev_priv->ring[RCS]); | |
1237 | ||
1238 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT)) | |
1239 | intel_lrc_irq_handler(&dev_priv->ring[BCS]); | |
1240 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT)) | |
1241 | notify_ring(&dev_priv->ring[BCS]); | |
abd58f01 BW |
1242 | } else |
1243 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1244 | } | |
1245 | ||
85f9b5f9 | 1246 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
74cdb337 | 1247 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(1)); |
abd58f01 | 1248 | if (tmp) { |
cb0d205e | 1249 | I915_WRITE_FW(GEN8_GT_IIR(1), tmp); |
abd58f01 | 1250 | ret = IRQ_HANDLED; |
e981e7b1 | 1251 | |
74cdb337 CW |
1252 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT)) |
1253 | intel_lrc_irq_handler(&dev_priv->ring[VCS]); | |
1254 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT)) | |
1255 | notify_ring(&dev_priv->ring[VCS]); | |
abd58f01 | 1256 | |
74cdb337 CW |
1257 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT)) |
1258 | intel_lrc_irq_handler(&dev_priv->ring[VCS2]); | |
1259 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT)) | |
1260 | notify_ring(&dev_priv->ring[VCS2]); | |
0961021a | 1261 | } else |
abd58f01 | 1262 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
0961021a BW |
1263 | } |
1264 | ||
abd58f01 | 1265 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
74cdb337 | 1266 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(3)); |
abd58f01 | 1267 | if (tmp) { |
74cdb337 | 1268 | I915_WRITE_FW(GEN8_GT_IIR(3), tmp); |
abd58f01 | 1269 | ret = IRQ_HANDLED; |
e981e7b1 | 1270 | |
74cdb337 CW |
1271 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)) |
1272 | intel_lrc_irq_handler(&dev_priv->ring[VECS]); | |
1273 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT)) | |
1274 | notify_ring(&dev_priv->ring[VECS]); | |
abd58f01 BW |
1275 | } else |
1276 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1277 | } | |
1278 | ||
0961021a | 1279 | if (master_ctl & GEN8_GT_PM_IRQ) { |
74cdb337 | 1280 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(2)); |
0961021a | 1281 | if (tmp & dev_priv->pm_rps_events) { |
cb0d205e CW |
1282 | I915_WRITE_FW(GEN8_GT_IIR(2), |
1283 | tmp & dev_priv->pm_rps_events); | |
38cc46d7 | 1284 | ret = IRQ_HANDLED; |
c9a9a268 | 1285 | gen6_rps_irq_handler(dev_priv, tmp); |
0961021a BW |
1286 | } else |
1287 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1288 | } | |
1289 | ||
abd58f01 BW |
1290 | return ret; |
1291 | } | |
1292 | ||
63c88d22 ID |
1293 | static bool bxt_port_hotplug_long_detect(enum port port, u32 val) |
1294 | { | |
1295 | switch (port) { | |
1296 | case PORT_A: | |
195baa06 | 1297 | return val & PORTA_HOTPLUG_LONG_DETECT; |
63c88d22 ID |
1298 | case PORT_B: |
1299 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1300 | case PORT_C: | |
1301 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
1302 | case PORT_D: | |
1303 | return val & PORTD_HOTPLUG_LONG_DETECT; | |
1304 | default: | |
1305 | return false; | |
1306 | } | |
1307 | } | |
1308 | ||
6dbf30ce VS |
1309 | static bool spt_port_hotplug2_long_detect(enum port port, u32 val) |
1310 | { | |
1311 | switch (port) { | |
1312 | case PORT_E: | |
1313 | return val & PORTE_HOTPLUG_LONG_DETECT; | |
1314 | default: | |
1315 | return false; | |
1316 | } | |
1317 | } | |
1318 | ||
e4ce95aa VS |
1319 | static bool ilk_port_hotplug_long_detect(enum port port, u32 val) |
1320 | { | |
1321 | switch (port) { | |
1322 | case PORT_A: | |
1323 | return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; | |
1324 | default: | |
1325 | return false; | |
1326 | } | |
1327 | } | |
1328 | ||
676574df | 1329 | static bool pch_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1330 | { |
1331 | switch (port) { | |
13cf5504 | 1332 | case PORT_B: |
676574df | 1333 | return val & PORTB_HOTPLUG_LONG_DETECT; |
13cf5504 | 1334 | case PORT_C: |
676574df | 1335 | return val & PORTC_HOTPLUG_LONG_DETECT; |
13cf5504 | 1336 | case PORT_D: |
676574df JN |
1337 | return val & PORTD_HOTPLUG_LONG_DETECT; |
1338 | default: | |
1339 | return false; | |
13cf5504 DA |
1340 | } |
1341 | } | |
1342 | ||
676574df | 1343 | static bool i9xx_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1344 | { |
1345 | switch (port) { | |
13cf5504 | 1346 | case PORT_B: |
676574df | 1347 | return val & PORTB_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1348 | case PORT_C: |
676574df | 1349 | return val & PORTC_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1350 | case PORT_D: |
676574df JN |
1351 | return val & PORTD_HOTPLUG_INT_LONG_PULSE; |
1352 | default: | |
1353 | return false; | |
13cf5504 DA |
1354 | } |
1355 | } | |
1356 | ||
42db67d6 VS |
1357 | /* |
1358 | * Get a bit mask of pins that have triggered, and which ones may be long. | |
1359 | * This can be called multiple times with the same masks to accumulate | |
1360 | * hotplug detection results from several registers. | |
1361 | * | |
1362 | * Note that the caller is expected to zero out the masks initially. | |
1363 | */ | |
fd63e2a9 | 1364 | static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, |
8c841e57 | 1365 | u32 hotplug_trigger, u32 dig_hotplug_reg, |
fd63e2a9 ID |
1366 | const u32 hpd[HPD_NUM_PINS], |
1367 | bool long_pulse_detect(enum port port, u32 val)) | |
676574df | 1368 | { |
8c841e57 | 1369 | enum port port; |
676574df JN |
1370 | int i; |
1371 | ||
676574df | 1372 | for_each_hpd_pin(i) { |
8c841e57 JN |
1373 | if ((hpd[i] & hotplug_trigger) == 0) |
1374 | continue; | |
676574df | 1375 | |
8c841e57 JN |
1376 | *pin_mask |= BIT(i); |
1377 | ||
cc24fcdc ID |
1378 | if (!intel_hpd_pin_to_port(i, &port)) |
1379 | continue; | |
1380 | ||
fd63e2a9 | 1381 | if (long_pulse_detect(port, dig_hotplug_reg)) |
8c841e57 | 1382 | *long_mask |= BIT(i); |
676574df JN |
1383 | } |
1384 | ||
1385 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n", | |
1386 | hotplug_trigger, dig_hotplug_reg, *pin_mask); | |
1387 | ||
1388 | } | |
1389 | ||
515ac2bb DV |
1390 | static void gmbus_irq_handler(struct drm_device *dev) |
1391 | { | |
2d1013dd | 1392 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1393 | |
28c70f16 | 1394 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1395 | } |
1396 | ||
ce99c256 DV |
1397 | static void dp_aux_irq_handler(struct drm_device *dev) |
1398 | { | |
2d1013dd | 1399 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1400 | |
9ee32fea | 1401 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1402 | } |
1403 | ||
8bf1e9f1 | 1404 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1405 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1406 | uint32_t crc0, uint32_t crc1, | |
1407 | uint32_t crc2, uint32_t crc3, | |
1408 | uint32_t crc4) | |
8bf1e9f1 SH |
1409 | { |
1410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1411 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1412 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1413 | int head, tail; |
b2c88f5b | 1414 | |
d538bbdf DL |
1415 | spin_lock(&pipe_crc->lock); |
1416 | ||
0c912c79 | 1417 | if (!pipe_crc->entries) { |
d538bbdf | 1418 | spin_unlock(&pipe_crc->lock); |
34273620 | 1419 | DRM_DEBUG_KMS("spurious interrupt\n"); |
0c912c79 DL |
1420 | return; |
1421 | } | |
1422 | ||
d538bbdf DL |
1423 | head = pipe_crc->head; |
1424 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1425 | |
1426 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1427 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1428 | DRM_ERROR("CRC buffer overflowing\n"); |
1429 | return; | |
1430 | } | |
1431 | ||
1432 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1433 | |
8bc5e955 | 1434 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1435 | entry->crc[0] = crc0; |
1436 | entry->crc[1] = crc1; | |
1437 | entry->crc[2] = crc2; | |
1438 | entry->crc[3] = crc3; | |
1439 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1440 | |
1441 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1442 | pipe_crc->head = head; |
1443 | ||
1444 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1445 | |
1446 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1447 | } |
277de95e DV |
1448 | #else |
1449 | static inline void | |
1450 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1451 | uint32_t crc0, uint32_t crc1, | |
1452 | uint32_t crc2, uint32_t crc3, | |
1453 | uint32_t crc4) {} | |
1454 | #endif | |
1455 | ||
eba94eb9 | 1456 | |
277de95e | 1457 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1458 | { |
1459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1460 | ||
277de95e DV |
1461 | display_pipe_crc_irq_handler(dev, pipe, |
1462 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1463 | 0, 0, 0, 0); | |
5a69b89f DV |
1464 | } |
1465 | ||
277de95e | 1466 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1467 | { |
1468 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1469 | ||
277de95e DV |
1470 | display_pipe_crc_irq_handler(dev, pipe, |
1471 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1472 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1473 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1474 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1475 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1476 | } |
5b3a856b | 1477 | |
277de95e | 1478 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1479 | { |
1480 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1481 | uint32_t res1, res2; |
1482 | ||
1483 | if (INTEL_INFO(dev)->gen >= 3) | |
1484 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1485 | else | |
1486 | res1 = 0; | |
1487 | ||
1488 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1489 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1490 | else | |
1491 | res2 = 0; | |
5b3a856b | 1492 | |
277de95e DV |
1493 | display_pipe_crc_irq_handler(dev, pipe, |
1494 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1495 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1496 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1497 | res1, res2); | |
5b3a856b | 1498 | } |
8bf1e9f1 | 1499 | |
1403c0d4 PZ |
1500 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1501 | * IMR bits until the work is done. Other interrupts can be processed without | |
1502 | * the work queue. */ | |
1503 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1504 | { |
a6706b45 | 1505 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1506 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1507 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1508 | if (dev_priv->rps.interrupts_enabled) { |
1509 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1510 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1511 | } | |
59cdb63d | 1512 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1513 | } |
baf02a1f | 1514 | |
c9a9a268 ID |
1515 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1516 | return; | |
1517 | ||
1403c0d4 PZ |
1518 | if (HAS_VEBOX(dev_priv->dev)) { |
1519 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
74cdb337 | 1520 | notify_ring(&dev_priv->ring[VECS]); |
12638c57 | 1521 | |
aaecdf61 DV |
1522 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1523 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1524 | } |
baf02a1f BW |
1525 | } |
1526 | ||
8d7849db VS |
1527 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1528 | { | |
8d7849db VS |
1529 | if (!drm_handle_vblank(dev, pipe)) |
1530 | return false; | |
1531 | ||
8d7849db VS |
1532 | return true; |
1533 | } | |
1534 | ||
c1874ed7 ID |
1535 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1536 | { | |
1537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1538 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1539 | int pipe; |
1540 | ||
58ead0d7 | 1541 | spin_lock(&dev_priv->irq_lock); |
055e393f | 1542 | for_each_pipe(dev_priv, pipe) { |
91d181dd | 1543 | int reg; |
bbb5eebf | 1544 | u32 mask, iir_bit = 0; |
91d181dd | 1545 | |
bbb5eebf DV |
1546 | /* |
1547 | * PIPESTAT bits get signalled even when the interrupt is | |
1548 | * disabled with the mask bits, and some of the status bits do | |
1549 | * not generate interrupts at all (like the underrun bit). Hence | |
1550 | * we need to be careful that we only handle what we want to | |
1551 | * handle. | |
1552 | */ | |
0f239f4c DV |
1553 | |
1554 | /* fifo underruns are filterered in the underrun handler. */ | |
1555 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1556 | |
1557 | switch (pipe) { | |
1558 | case PIPE_A: | |
1559 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1560 | break; | |
1561 | case PIPE_B: | |
1562 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1563 | break; | |
3278f67f VS |
1564 | case PIPE_C: |
1565 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1566 | break; | |
bbb5eebf DV |
1567 | } |
1568 | if (iir & iir_bit) | |
1569 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1570 | ||
1571 | if (!mask) | |
91d181dd ID |
1572 | continue; |
1573 | ||
1574 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1575 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1576 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1577 | |
1578 | /* | |
1579 | * Clear the PIPE*STAT regs before the IIR | |
1580 | */ | |
91d181dd ID |
1581 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1582 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1583 | I915_WRITE(reg, pipe_stats[pipe]); |
1584 | } | |
58ead0d7 | 1585 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 | 1586 | |
055e393f | 1587 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1588 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1589 | intel_pipe_handle_vblank(dev, pipe)) | |
1590 | intel_check_page_flip(dev, pipe); | |
c1874ed7 | 1591 | |
579a9b0e | 1592 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1593 | intel_prepare_page_flip(dev, pipe); |
1594 | intel_finish_page_flip(dev, pipe); | |
1595 | } | |
1596 | ||
1597 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1598 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1599 | ||
1f7247c0 DV |
1600 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1601 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1602 | } |
1603 | ||
1604 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1605 | gmbus_irq_handler(dev); | |
1606 | } | |
1607 | ||
16c6c56b VS |
1608 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1609 | { | |
1610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1611 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
42db67d6 | 1612 | u32 pin_mask = 0, long_mask = 0; |
16c6c56b | 1613 | |
0d2e4297 JN |
1614 | if (!hotplug_status) |
1615 | return; | |
16c6c56b | 1616 | |
0d2e4297 JN |
1617 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
1618 | /* | |
1619 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1620 | * may miss hotplug events. | |
1621 | */ | |
1622 | POSTING_READ(PORT_HOTPLUG_STAT); | |
16c6c56b | 1623 | |
0d2e4297 JN |
1624 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
1625 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
16c6c56b | 1626 | |
fd63e2a9 ID |
1627 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, |
1628 | hotplug_trigger, hpd_status_g4x, | |
1629 | i9xx_port_hotplug_long_detect); | |
676574df | 1630 | intel_hpd_irq_handler(dev, pin_mask, long_mask); |
369712e8 JN |
1631 | |
1632 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1633 | dp_aux_irq_handler(dev); | |
0d2e4297 JN |
1634 | } else { |
1635 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1636 | |
fd63e2a9 ID |
1637 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, |
1638 | hotplug_trigger, hpd_status_g4x, | |
1639 | i9xx_port_hotplug_long_detect); | |
676574df | 1640 | intel_hpd_irq_handler(dev, pin_mask, long_mask); |
3ff60f89 | 1641 | } |
16c6c56b VS |
1642 | } |
1643 | ||
ff1f525e | 1644 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1645 | { |
45a83f84 | 1646 | struct drm_device *dev = arg; |
2d1013dd | 1647 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1648 | u32 iir, gt_iir, pm_iir; |
1649 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1650 | |
2dd2a883 ID |
1651 | if (!intel_irqs_enabled(dev_priv)) |
1652 | return IRQ_NONE; | |
1653 | ||
7e231dbe | 1654 | while (true) { |
3ff60f89 OM |
1655 | /* Find, clear, then process each source of interrupt */ |
1656 | ||
7e231dbe | 1657 | gt_iir = I915_READ(GTIIR); |
3ff60f89 OM |
1658 | if (gt_iir) |
1659 | I915_WRITE(GTIIR, gt_iir); | |
1660 | ||
7e231dbe | 1661 | pm_iir = I915_READ(GEN6_PMIIR); |
3ff60f89 OM |
1662 | if (pm_iir) |
1663 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1664 | ||
1665 | iir = I915_READ(VLV_IIR); | |
1666 | if (iir) { | |
1667 | /* Consume port before clearing IIR or we'll miss events */ | |
1668 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1669 | i9xx_hpd_irq_handler(dev); | |
1670 | I915_WRITE(VLV_IIR, iir); | |
1671 | } | |
7e231dbe JB |
1672 | |
1673 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1674 | goto out; | |
1675 | ||
1676 | ret = IRQ_HANDLED; | |
1677 | ||
3ff60f89 OM |
1678 | if (gt_iir) |
1679 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
60611c13 | 1680 | if (pm_iir) |
d0ecd7e2 | 1681 | gen6_rps_irq_handler(dev_priv, pm_iir); |
3ff60f89 OM |
1682 | /* Call regardless, as some status bits might not be |
1683 | * signalled in iir */ | |
1684 | valleyview_pipestat_irq_handler(dev, iir); | |
7e231dbe JB |
1685 | } |
1686 | ||
1687 | out: | |
1688 | return ret; | |
1689 | } | |
1690 | ||
43f328d7 VS |
1691 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1692 | { | |
45a83f84 | 1693 | struct drm_device *dev = arg; |
43f328d7 VS |
1694 | struct drm_i915_private *dev_priv = dev->dev_private; |
1695 | u32 master_ctl, iir; | |
1696 | irqreturn_t ret = IRQ_NONE; | |
43f328d7 | 1697 | |
2dd2a883 ID |
1698 | if (!intel_irqs_enabled(dev_priv)) |
1699 | return IRQ_NONE; | |
1700 | ||
8e5fd599 VS |
1701 | for (;;) { |
1702 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; | |
1703 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1704 | |
8e5fd599 VS |
1705 | if (master_ctl == 0 && iir == 0) |
1706 | break; | |
43f328d7 | 1707 | |
27b6c122 OM |
1708 | ret = IRQ_HANDLED; |
1709 | ||
8e5fd599 | 1710 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
43f328d7 | 1711 | |
27b6c122 | 1712 | /* Find, clear, then process each source of interrupt */ |
43f328d7 | 1713 | |
27b6c122 OM |
1714 | if (iir) { |
1715 | /* Consume port before clearing IIR or we'll miss events */ | |
1716 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1717 | i9xx_hpd_irq_handler(dev); | |
1718 | I915_WRITE(VLV_IIR, iir); | |
1719 | } | |
43f328d7 | 1720 | |
74cdb337 | 1721 | gen8_gt_irq_handler(dev_priv, master_ctl); |
43f328d7 | 1722 | |
27b6c122 OM |
1723 | /* Call regardless, as some status bits might not be |
1724 | * signalled in iir */ | |
1725 | valleyview_pipestat_irq_handler(dev, iir); | |
43f328d7 | 1726 | |
8e5fd599 VS |
1727 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
1728 | POSTING_READ(GEN8_MASTER_IRQ); | |
8e5fd599 | 1729 | } |
3278f67f | 1730 | |
43f328d7 VS |
1731 | return ret; |
1732 | } | |
1733 | ||
23e81d69 | 1734 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1735 | { |
2d1013dd | 1736 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1737 | int pipe; |
b543fb04 | 1738 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 | 1739 | |
aaf5ec2e | 1740 | if (hotplug_trigger) { |
42db67d6 | 1741 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
aaf5ec2e SJ |
1742 | |
1743 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1744 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
776ad806 | 1745 | |
fd63e2a9 ID |
1746 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, |
1747 | dig_hotplug_reg, hpd_ibx, | |
1748 | pch_port_hotplug_long_detect); | |
aaf5ec2e SJ |
1749 | intel_hpd_irq_handler(dev, pin_mask, long_mask); |
1750 | } | |
91d131d2 | 1751 | |
cfc33bf7 VS |
1752 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1753 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1754 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1755 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1756 | port_name(port)); |
1757 | } | |
776ad806 | 1758 | |
ce99c256 DV |
1759 | if (pch_iir & SDE_AUX_MASK) |
1760 | dp_aux_irq_handler(dev); | |
1761 | ||
776ad806 | 1762 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1763 | gmbus_irq_handler(dev); |
776ad806 JB |
1764 | |
1765 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1766 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1767 | ||
1768 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1769 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1770 | ||
1771 | if (pch_iir & SDE_POISON) | |
1772 | DRM_ERROR("PCH poison interrupt\n"); | |
1773 | ||
9db4a9c7 | 1774 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 1775 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
1776 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1777 | pipe_name(pipe), | |
1778 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1779 | |
1780 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1781 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1782 | ||
1783 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1784 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1785 | ||
776ad806 | 1786 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 1787 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1788 | |
1789 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 1790 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1791 | } |
1792 | ||
1793 | static void ivb_err_int_handler(struct drm_device *dev) | |
1794 | { | |
1795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1796 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1797 | enum pipe pipe; |
8664281b | 1798 | |
de032bf4 PZ |
1799 | if (err_int & ERR_INT_POISON) |
1800 | DRM_ERROR("Poison interrupt\n"); | |
1801 | ||
055e393f | 1802 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
1803 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
1804 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 1805 | |
5a69b89f DV |
1806 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1807 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1808 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1809 | else |
277de95e | 1810 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1811 | } |
1812 | } | |
8bf1e9f1 | 1813 | |
8664281b PZ |
1814 | I915_WRITE(GEN7_ERR_INT, err_int); |
1815 | } | |
1816 | ||
1817 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1818 | { | |
1819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1820 | u32 serr_int = I915_READ(SERR_INT); | |
1821 | ||
de032bf4 PZ |
1822 | if (serr_int & SERR_INT_POISON) |
1823 | DRM_ERROR("PCH poison interrupt\n"); | |
1824 | ||
8664281b | 1825 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 1826 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1827 | |
1828 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 1829 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1830 | |
1831 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 1832 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
1833 | |
1834 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1835 | } |
1836 | ||
23e81d69 AJ |
1837 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1838 | { | |
2d1013dd | 1839 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 1840 | int pipe; |
6dbf30ce | 1841 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 | 1842 | |
aaf5ec2e | 1843 | if (hotplug_trigger) { |
42db67d6 | 1844 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
23e81d69 | 1845 | |
aaf5ec2e SJ |
1846 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
1847 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
fd63e2a9 | 1848 | |
6dbf30ce VS |
1849 | intel_get_hpd_pins(&pin_mask, &long_mask, |
1850 | hotplug_trigger, | |
1851 | dig_hotplug_reg, hpd_cpt, | |
1852 | pch_port_hotplug_long_detect); | |
26951caf | 1853 | |
aaf5ec2e SJ |
1854 | intel_hpd_irq_handler(dev, pin_mask, long_mask); |
1855 | } | |
91d131d2 | 1856 | |
cfc33bf7 VS |
1857 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1858 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1859 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1860 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1861 | port_name(port)); | |
1862 | } | |
23e81d69 AJ |
1863 | |
1864 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1865 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1866 | |
1867 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1868 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1869 | |
1870 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1871 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1872 | ||
1873 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1874 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1875 | ||
1876 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 1877 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
1878 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1879 | pipe_name(pipe), | |
1880 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1881 | |
1882 | if (pch_iir & SDE_ERROR_CPT) | |
1883 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1884 | } |
1885 | ||
6dbf30ce VS |
1886 | static void spt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1887 | { | |
1888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1889 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & | |
1890 | ~SDE_PORTE_HOTPLUG_SPT; | |
1891 | u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; | |
1892 | u32 pin_mask = 0, long_mask = 0; | |
1893 | ||
1894 | if (hotplug_trigger) { | |
1895 | u32 dig_hotplug_reg; | |
1896 | ||
1897 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1898 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
1899 | ||
1900 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1901 | dig_hotplug_reg, hpd_spt, | |
1902 | pch_port_hotplug_long_detect); | |
1903 | } | |
1904 | ||
1905 | if (hotplug2_trigger) { | |
1906 | u32 dig_hotplug_reg; | |
1907 | ||
1908 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2); | |
1909 | I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg); | |
1910 | ||
1911 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger, | |
1912 | dig_hotplug_reg, hpd_spt, | |
1913 | spt_port_hotplug2_long_detect); | |
1914 | } | |
1915 | ||
1916 | if (pin_mask) | |
1917 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
1918 | ||
1919 | if (pch_iir & SDE_GMBUS_CPT) | |
1920 | gmbus_irq_handler(dev); | |
1921 | } | |
1922 | ||
c008bc6e PZ |
1923 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1924 | { | |
1925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 1926 | enum pipe pipe; |
e4ce95aa VS |
1927 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; |
1928 | ||
1929 | if (hotplug_trigger) { | |
1930 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; | |
1931 | ||
1932 | dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
1933 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); | |
1934 | ||
1935 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1936 | dig_hotplug_reg, hpd_ilk, | |
1937 | ilk_port_hotplug_long_detect); | |
1938 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
1939 | } | |
c008bc6e PZ |
1940 | |
1941 | if (de_iir & DE_AUX_CHANNEL_A) | |
1942 | dp_aux_irq_handler(dev); | |
1943 | ||
1944 | if (de_iir & DE_GSE) | |
1945 | intel_opregion_asle_intr(dev); | |
1946 | ||
c008bc6e PZ |
1947 | if (de_iir & DE_POISON) |
1948 | DRM_ERROR("Poison interrupt\n"); | |
1949 | ||
055e393f | 1950 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1951 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
1952 | intel_pipe_handle_vblank(dev, pipe)) | |
1953 | intel_check_page_flip(dev, pipe); | |
5b3a856b | 1954 | |
40da17c2 | 1955 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 1956 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 1957 | |
40da17c2 DV |
1958 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
1959 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 1960 | |
40da17c2 DV |
1961 | /* plane/pipes map 1:1 on ilk+ */ |
1962 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
1963 | intel_prepare_page_flip(dev, pipe); | |
1964 | intel_finish_page_flip_plane(dev, pipe); | |
1965 | } | |
c008bc6e PZ |
1966 | } |
1967 | ||
1968 | /* check event from PCH */ | |
1969 | if (de_iir & DE_PCH_EVENT) { | |
1970 | u32 pch_iir = I915_READ(SDEIIR); | |
1971 | ||
1972 | if (HAS_PCH_CPT(dev)) | |
1973 | cpt_irq_handler(dev, pch_iir); | |
1974 | else | |
1975 | ibx_irq_handler(dev, pch_iir); | |
1976 | ||
1977 | /* should clear PCH hotplug event before clear CPU irq */ | |
1978 | I915_WRITE(SDEIIR, pch_iir); | |
1979 | } | |
1980 | ||
1981 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
1982 | ironlake_rps_change_irq_handler(dev); | |
1983 | } | |
1984 | ||
9719fb98 PZ |
1985 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1986 | { | |
1987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 1988 | enum pipe pipe; |
23bb4cb5 VS |
1989 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; |
1990 | ||
1991 | if (hotplug_trigger) { | |
1992 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; | |
1993 | ||
1994 | dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
1995 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); | |
1996 | ||
1997 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1998 | dig_hotplug_reg, hpd_ivb, | |
1999 | ilk_port_hotplug_long_detect); | |
2000 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
2001 | } | |
9719fb98 PZ |
2002 | |
2003 | if (de_iir & DE_ERR_INT_IVB) | |
2004 | ivb_err_int_handler(dev); | |
2005 | ||
2006 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2007 | dp_aux_irq_handler(dev); | |
2008 | ||
2009 | if (de_iir & DE_GSE_IVB) | |
2010 | intel_opregion_asle_intr(dev); | |
2011 | ||
055e393f | 2012 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2013 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2014 | intel_pipe_handle_vblank(dev, pipe)) | |
2015 | intel_check_page_flip(dev, pipe); | |
40da17c2 DV |
2016 | |
2017 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2018 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2019 | intel_prepare_page_flip(dev, pipe); | |
2020 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2021 | } |
2022 | } | |
2023 | ||
2024 | /* check event from PCH */ | |
2025 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2026 | u32 pch_iir = I915_READ(SDEIIR); | |
2027 | ||
2028 | cpt_irq_handler(dev, pch_iir); | |
2029 | ||
2030 | /* clear PCH hotplug event before clear CPU irq */ | |
2031 | I915_WRITE(SDEIIR, pch_iir); | |
2032 | } | |
2033 | } | |
2034 | ||
72c90f62 OM |
2035 | /* |
2036 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2037 | * 1 - Disable Master Interrupt Control. | |
2038 | * 2 - Find the source(s) of the interrupt. | |
2039 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2040 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2041 | * 5 - Re-enable Master Interrupt Control. | |
2042 | */ | |
f1af8fc1 | 2043 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2044 | { |
45a83f84 | 2045 | struct drm_device *dev = arg; |
2d1013dd | 2046 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2047 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2048 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2049 | |
2dd2a883 ID |
2050 | if (!intel_irqs_enabled(dev_priv)) |
2051 | return IRQ_NONE; | |
2052 | ||
8664281b PZ |
2053 | /* We get interrupts on unclaimed registers, so check for this before we |
2054 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 2055 | intel_uncore_check_errors(dev); |
8664281b | 2056 | |
b1f14ad0 JB |
2057 | /* disable master interrupt before clearing iir */ |
2058 | de_ier = I915_READ(DEIER); | |
2059 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2060 | POSTING_READ(DEIER); |
b1f14ad0 | 2061 | |
44498aea PZ |
2062 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2063 | * interrupts will will be stored on its back queue, and then we'll be | |
2064 | * able to process them after we restore SDEIER (as soon as we restore | |
2065 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2066 | * due to its back queue). */ | |
ab5c608b BW |
2067 | if (!HAS_PCH_NOP(dev)) { |
2068 | sde_ier = I915_READ(SDEIER); | |
2069 | I915_WRITE(SDEIER, 0); | |
2070 | POSTING_READ(SDEIER); | |
2071 | } | |
44498aea | 2072 | |
72c90f62 OM |
2073 | /* Find, clear, then process each source of interrupt */ |
2074 | ||
b1f14ad0 | 2075 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2076 | if (gt_iir) { |
72c90f62 OM |
2077 | I915_WRITE(GTIIR, gt_iir); |
2078 | ret = IRQ_HANDLED; | |
d8fc8a47 | 2079 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 2080 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
2081 | else |
2082 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
b1f14ad0 JB |
2083 | } |
2084 | ||
0e43406b CW |
2085 | de_iir = I915_READ(DEIIR); |
2086 | if (de_iir) { | |
72c90f62 OM |
2087 | I915_WRITE(DEIIR, de_iir); |
2088 | ret = IRQ_HANDLED; | |
f1af8fc1 PZ |
2089 | if (INTEL_INFO(dev)->gen >= 7) |
2090 | ivb_display_irq_handler(dev, de_iir); | |
2091 | else | |
2092 | ilk_display_irq_handler(dev, de_iir); | |
b1f14ad0 JB |
2093 | } |
2094 | ||
f1af8fc1 PZ |
2095 | if (INTEL_INFO(dev)->gen >= 6) { |
2096 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2097 | if (pm_iir) { | |
f1af8fc1 PZ |
2098 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2099 | ret = IRQ_HANDLED; | |
72c90f62 | 2100 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2101 | } |
0e43406b | 2102 | } |
b1f14ad0 | 2103 | |
b1f14ad0 JB |
2104 | I915_WRITE(DEIER, de_ier); |
2105 | POSTING_READ(DEIER); | |
ab5c608b BW |
2106 | if (!HAS_PCH_NOP(dev)) { |
2107 | I915_WRITE(SDEIER, sde_ier); | |
2108 | POSTING_READ(SDEIER); | |
2109 | } | |
b1f14ad0 JB |
2110 | |
2111 | return ret; | |
2112 | } | |
2113 | ||
d04a492d SS |
2114 | static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status) |
2115 | { | |
2116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
676574df | 2117 | u32 hp_control, hp_trigger; |
42db67d6 | 2118 | u32 pin_mask = 0, long_mask = 0; |
d04a492d SS |
2119 | |
2120 | /* Get the status */ | |
2121 | hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK; | |
2122 | hp_control = I915_READ(BXT_HOTPLUG_CTL); | |
2123 | ||
2124 | /* Hotplug not enabled ? */ | |
2125 | if (!(hp_control & BXT_HOTPLUG_CTL_MASK)) { | |
2126 | DRM_ERROR("Interrupt when HPD disabled\n"); | |
2127 | return; | |
2128 | } | |
2129 | ||
475c2e3b JN |
2130 | /* Clear sticky bits in hpd status */ |
2131 | I915_WRITE(BXT_HOTPLUG_CTL, hp_control); | |
d04a492d | 2132 | |
fd63e2a9 | 2133 | intel_get_hpd_pins(&pin_mask, &long_mask, hp_trigger, hp_control, |
63c88d22 | 2134 | hpd_bxt, bxt_port_hotplug_long_detect); |
676574df | 2135 | intel_hpd_irq_handler(dev, pin_mask, long_mask); |
d04a492d SS |
2136 | } |
2137 | ||
abd58f01 BW |
2138 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2139 | { | |
2140 | struct drm_device *dev = arg; | |
2141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2142 | u32 master_ctl; | |
2143 | irqreturn_t ret = IRQ_NONE; | |
2144 | uint32_t tmp = 0; | |
c42664cc | 2145 | enum pipe pipe; |
88e04703 JB |
2146 | u32 aux_mask = GEN8_AUX_CHANNEL_A; |
2147 | ||
2dd2a883 ID |
2148 | if (!intel_irqs_enabled(dev_priv)) |
2149 | return IRQ_NONE; | |
2150 | ||
88e04703 JB |
2151 | if (IS_GEN9(dev)) |
2152 | aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | | |
2153 | GEN9_AUX_CHANNEL_D; | |
abd58f01 | 2154 | |
cb0d205e | 2155 | master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); |
abd58f01 BW |
2156 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; |
2157 | if (!master_ctl) | |
2158 | return IRQ_NONE; | |
2159 | ||
cb0d205e | 2160 | I915_WRITE_FW(GEN8_MASTER_IRQ, 0); |
abd58f01 | 2161 | |
38cc46d7 OM |
2162 | /* Find, clear, then process each source of interrupt */ |
2163 | ||
74cdb337 | 2164 | ret = gen8_gt_irq_handler(dev_priv, master_ctl); |
abd58f01 BW |
2165 | |
2166 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2167 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
abd58f01 BW |
2168 | if (tmp) { |
2169 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2170 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2171 | if (tmp & GEN8_DE_MISC_GSE) |
2172 | intel_opregion_asle_intr(dev); | |
2173 | else | |
2174 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2175 | } |
38cc46d7 OM |
2176 | else |
2177 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2178 | } |
2179 | ||
6d766f02 DV |
2180 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2181 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
6d766f02 | 2182 | if (tmp) { |
d04a492d | 2183 | bool found = false; |
3a3b3c7d | 2184 | u32 hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG; |
d04a492d | 2185 | |
6d766f02 DV |
2186 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); |
2187 | ret = IRQ_HANDLED; | |
88e04703 | 2188 | |
3a3b3c7d VS |
2189 | if (IS_BROADWELL(dev) && hotplug_trigger) { |
2190 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; | |
2191 | ||
2192 | dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
2193 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); | |
2194 | ||
2195 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2196 | dig_hotplug_reg, hpd_bdw, | |
2197 | ilk_port_hotplug_long_detect); | |
2198 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
2199 | found = true; | |
2200 | } | |
2201 | ||
d04a492d | 2202 | if (tmp & aux_mask) { |
38cc46d7 | 2203 | dp_aux_irq_handler(dev); |
d04a492d SS |
2204 | found = true; |
2205 | } | |
2206 | ||
2207 | if (IS_BROXTON(dev) && tmp & BXT_DE_PORT_HOTPLUG_MASK) { | |
2208 | bxt_hpd_handler(dev, tmp); | |
2209 | found = true; | |
2210 | } | |
2211 | ||
9e63743e SS |
2212 | if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) { |
2213 | gmbus_irq_handler(dev); | |
2214 | found = true; | |
2215 | } | |
2216 | ||
d04a492d | 2217 | if (!found) |
38cc46d7 | 2218 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
6d766f02 | 2219 | } |
38cc46d7 OM |
2220 | else |
2221 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2222 | } |
2223 | ||
055e393f | 2224 | for_each_pipe(dev_priv, pipe) { |
770de83d | 2225 | uint32_t pipe_iir, flip_done = 0, fault_errors = 0; |
abd58f01 | 2226 | |
c42664cc DV |
2227 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2228 | continue; | |
abd58f01 | 2229 | |
c42664cc | 2230 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
c42664cc DV |
2231 | if (pipe_iir) { |
2232 | ret = IRQ_HANDLED; | |
2233 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
770de83d | 2234 | |
d6bbafa1 CW |
2235 | if (pipe_iir & GEN8_PIPE_VBLANK && |
2236 | intel_pipe_handle_vblank(dev, pipe)) | |
2237 | intel_check_page_flip(dev, pipe); | |
38cc46d7 | 2238 | |
770de83d DL |
2239 | if (IS_GEN9(dev)) |
2240 | flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; | |
2241 | else | |
2242 | flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; | |
2243 | ||
2244 | if (flip_done) { | |
38cc46d7 OM |
2245 | intel_prepare_page_flip(dev, pipe); |
2246 | intel_finish_page_flip_plane(dev, pipe); | |
2247 | } | |
2248 | ||
2249 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) | |
2250 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2251 | ||
1f7247c0 DV |
2252 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) |
2253 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
2254 | pipe); | |
38cc46d7 | 2255 | |
770de83d DL |
2256 | |
2257 | if (IS_GEN9(dev)) | |
2258 | fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2259 | else | |
2260 | fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2261 | ||
2262 | if (fault_errors) | |
38cc46d7 OM |
2263 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
2264 | pipe_name(pipe), | |
2265 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
c42664cc | 2266 | } else |
abd58f01 BW |
2267 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2268 | } | |
2269 | ||
266ea3d9 SS |
2270 | if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) && |
2271 | master_ctl & GEN8_DE_PCH_IRQ) { | |
92d03a80 DV |
2272 | /* |
2273 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2274 | * scheme also closed the SDE interrupt handling race we've seen | |
2275 | * on older pch-split platforms. But this needs testing. | |
2276 | */ | |
2277 | u32 pch_iir = I915_READ(SDEIIR); | |
92d03a80 DV |
2278 | if (pch_iir) { |
2279 | I915_WRITE(SDEIIR, pch_iir); | |
2280 | ret = IRQ_HANDLED; | |
6dbf30ce VS |
2281 | |
2282 | if (HAS_PCH_SPT(dev_priv)) | |
2283 | spt_irq_handler(dev, pch_iir); | |
2284 | else | |
2285 | cpt_irq_handler(dev, pch_iir); | |
38cc46d7 OM |
2286 | } else |
2287 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); | |
2288 | ||
92d03a80 DV |
2289 | } |
2290 | ||
cb0d205e CW |
2291 | I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2292 | POSTING_READ_FW(GEN8_MASTER_IRQ); | |
abd58f01 BW |
2293 | |
2294 | return ret; | |
2295 | } | |
2296 | ||
17e1df07 DV |
2297 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2298 | bool reset_completed) | |
2299 | { | |
a4872ba6 | 2300 | struct intel_engine_cs *ring; |
17e1df07 DV |
2301 | int i; |
2302 | ||
2303 | /* | |
2304 | * Notify all waiters for GPU completion events that reset state has | |
2305 | * been changed, and that they need to restart their wait after | |
2306 | * checking for potential errors (and bail out to drop locks if there is | |
2307 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2308 | */ | |
2309 | ||
2310 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2311 | for_each_ring(ring, dev_priv, i) | |
2312 | wake_up_all(&ring->irq_queue); | |
2313 | ||
2314 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2315 | wake_up_all(&dev_priv->pending_flip_queue); | |
2316 | ||
2317 | /* | |
2318 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2319 | * reset state is cleared. | |
2320 | */ | |
2321 | if (reset_completed) | |
2322 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2323 | } | |
2324 | ||
8a905236 | 2325 | /** |
b8d24a06 | 2326 | * i915_reset_and_wakeup - do process context error handling work |
8a905236 JB |
2327 | * |
2328 | * Fire an error uevent so userspace can see that a hang or error | |
2329 | * was detected. | |
2330 | */ | |
b8d24a06 | 2331 | static void i915_reset_and_wakeup(struct drm_device *dev) |
8a905236 | 2332 | { |
b8d24a06 MK |
2333 | struct drm_i915_private *dev_priv = to_i915(dev); |
2334 | struct i915_gpu_error *error = &dev_priv->gpu_error; | |
cce723ed BW |
2335 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2336 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2337 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2338 | int ret; |
8a905236 | 2339 | |
5bdebb18 | 2340 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2341 | |
7db0ba24 DV |
2342 | /* |
2343 | * Note that there's only one work item which does gpu resets, so we | |
2344 | * need not worry about concurrent gpu resets potentially incrementing | |
2345 | * error->reset_counter twice. We only need to take care of another | |
2346 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2347 | * quick check for that is good enough: schedule_work ensures the | |
2348 | * correct ordering between hang detection and this work item, and since | |
2349 | * the reset in-progress bit is only ever set by code outside of this | |
2350 | * work we don't need to worry about any other races. | |
2351 | */ | |
2352 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2353 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2354 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2355 | reset_event); |
1f83fee0 | 2356 | |
f454c694 ID |
2357 | /* |
2358 | * In most cases it's guaranteed that we get here with an RPM | |
2359 | * reference held, for example because there is a pending GPU | |
2360 | * request that won't finish until the reset is done. This | |
2361 | * isn't the case at least when we get here by doing a | |
2362 | * simulated reset via debugs, so get an RPM reference. | |
2363 | */ | |
2364 | intel_runtime_pm_get(dev_priv); | |
7514747d VS |
2365 | |
2366 | intel_prepare_reset(dev); | |
2367 | ||
17e1df07 DV |
2368 | /* |
2369 | * All state reset _must_ be completed before we update the | |
2370 | * reset counter, for otherwise waiters might miss the reset | |
2371 | * pending state and not properly drop locks, resulting in | |
2372 | * deadlocks with the reset work. | |
2373 | */ | |
f69061be DV |
2374 | ret = i915_reset(dev); |
2375 | ||
7514747d | 2376 | intel_finish_reset(dev); |
17e1df07 | 2377 | |
f454c694 ID |
2378 | intel_runtime_pm_put(dev_priv); |
2379 | ||
f69061be DV |
2380 | if (ret == 0) { |
2381 | /* | |
2382 | * After all the gem state is reset, increment the reset | |
2383 | * counter and wake up everyone waiting for the reset to | |
2384 | * complete. | |
2385 | * | |
2386 | * Since unlock operations are a one-sided barrier only, | |
2387 | * we need to insert a barrier here to order any seqno | |
2388 | * updates before | |
2389 | * the counter increment. | |
2390 | */ | |
4e857c58 | 2391 | smp_mb__before_atomic(); |
f69061be DV |
2392 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
2393 | ||
5bdebb18 | 2394 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2395 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2396 | } else { |
2ac0f450 | 2397 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2398 | } |
1f83fee0 | 2399 | |
17e1df07 DV |
2400 | /* |
2401 | * Note: The wake_up also serves as a memory barrier so that | |
2402 | * waiters see the update value of the reset counter atomic_t. | |
2403 | */ | |
2404 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2405 | } |
8a905236 JB |
2406 | } |
2407 | ||
35aed2e6 | 2408 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2409 | { |
2410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2411 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2412 | u32 eir = I915_READ(EIR); |
050ee91f | 2413 | int pipe, i; |
8a905236 | 2414 | |
35aed2e6 CW |
2415 | if (!eir) |
2416 | return; | |
8a905236 | 2417 | |
a70491cc | 2418 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2419 | |
bd9854f9 BW |
2420 | i915_get_extra_instdone(dev, instdone); |
2421 | ||
8a905236 JB |
2422 | if (IS_G4X(dev)) { |
2423 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2424 | u32 ipeir = I915_READ(IPEIR_I965); | |
2425 | ||
a70491cc JP |
2426 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2427 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2428 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2429 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2430 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2431 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2432 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2433 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2434 | } |
2435 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2436 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2437 | pr_err("page table error\n"); |
2438 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2439 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2440 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2441 | } |
2442 | } | |
2443 | ||
a6c45cf0 | 2444 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2445 | if (eir & I915_ERROR_PAGE_TABLE) { |
2446 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2447 | pr_err("page table error\n"); |
2448 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2449 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2450 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2451 | } |
2452 | } | |
2453 | ||
2454 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2455 | pr_err("memory refresh error:\n"); |
055e393f | 2456 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2457 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2458 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2459 | /* pipestat has already been acked */ |
2460 | } | |
2461 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2462 | pr_err("instruction error\n"); |
2463 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2464 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2465 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2466 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2467 | u32 ipeir = I915_READ(IPEIR); |
2468 | ||
a70491cc JP |
2469 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2470 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2471 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2472 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2473 | POSTING_READ(IPEIR); |
8a905236 JB |
2474 | } else { |
2475 | u32 ipeir = I915_READ(IPEIR_I965); | |
2476 | ||
a70491cc JP |
2477 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2478 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2479 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2480 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2481 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2482 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2483 | } |
2484 | } | |
2485 | ||
2486 | I915_WRITE(EIR, eir); | |
3143a2bf | 2487 | POSTING_READ(EIR); |
8a905236 JB |
2488 | eir = I915_READ(EIR); |
2489 | if (eir) { | |
2490 | /* | |
2491 | * some errors might have become stuck, | |
2492 | * mask them. | |
2493 | */ | |
2494 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2495 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2496 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2497 | } | |
35aed2e6 CW |
2498 | } |
2499 | ||
2500 | /** | |
b8d24a06 | 2501 | * i915_handle_error - handle a gpu error |
35aed2e6 CW |
2502 | * @dev: drm device |
2503 | * | |
b8d24a06 | 2504 | * Do some basic checking of regsiter state at error time and |
35aed2e6 CW |
2505 | * dump it to the syslog. Also call i915_capture_error_state() to make |
2506 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2507 | * so userspace knows something bad happened (should trigger collection | |
2508 | * of a ring dump etc.). | |
2509 | */ | |
58174462 MK |
2510 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2511 | const char *fmt, ...) | |
35aed2e6 CW |
2512 | { |
2513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2514 | va_list args; |
2515 | char error_msg[80]; | |
35aed2e6 | 2516 | |
58174462 MK |
2517 | va_start(args, fmt); |
2518 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2519 | va_end(args); | |
2520 | ||
2521 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2522 | i915_report_and_clear_eir(dev); |
8a905236 | 2523 | |
ba1234d1 | 2524 | if (wedged) { |
f69061be DV |
2525 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2526 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2527 | |
11ed50ec | 2528 | /* |
b8d24a06 MK |
2529 | * Wakeup waiting processes so that the reset function |
2530 | * i915_reset_and_wakeup doesn't deadlock trying to grab | |
2531 | * various locks. By bumping the reset counter first, the woken | |
17e1df07 DV |
2532 | * processes will see a reset in progress and back off, |
2533 | * releasing their locks and then wait for the reset completion. | |
2534 | * We must do this for _all_ gpu waiters that might hold locks | |
2535 | * that the reset work needs to acquire. | |
2536 | * | |
2537 | * Note: The wake_up serves as the required memory barrier to | |
2538 | * ensure that the waiters see the updated value of the reset | |
2539 | * counter atomic_t. | |
11ed50ec | 2540 | */ |
17e1df07 | 2541 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2542 | } |
2543 | ||
b8d24a06 | 2544 | i915_reset_and_wakeup(dev); |
8a905236 JB |
2545 | } |
2546 | ||
42f52ef8 KP |
2547 | /* Called from drm generic code, passed 'crtc' which |
2548 | * we use as a pipe index | |
2549 | */ | |
f71d4af4 | 2550 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2551 | { |
2d1013dd | 2552 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2553 | unsigned long irqflags; |
71e0ffa5 | 2554 | |
1ec14ad3 | 2555 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2556 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2557 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2558 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2559 | else |
7c463586 | 2560 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2561 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2562 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2563 | |
0a3e67a4 JB |
2564 | return 0; |
2565 | } | |
2566 | ||
f71d4af4 | 2567 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2568 | { |
2d1013dd | 2569 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2570 | unsigned long irqflags; |
b518421f | 2571 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2572 | DE_PIPE_VBLANK(pipe); |
f796cf8f | 2573 | |
f796cf8f | 2574 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
b518421f | 2575 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2576 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2577 | ||
2578 | return 0; | |
2579 | } | |
2580 | ||
7e231dbe JB |
2581 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2582 | { | |
2d1013dd | 2583 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2584 | unsigned long irqflags; |
7e231dbe | 2585 | |
7e231dbe | 2586 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2587 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2588 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2589 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2590 | ||
2591 | return 0; | |
2592 | } | |
2593 | ||
abd58f01 BW |
2594 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2595 | { | |
2596 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2597 | unsigned long irqflags; | |
abd58f01 | 2598 | |
abd58f01 | 2599 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7167d7c6 DV |
2600 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2601 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2602 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2603 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2604 | return 0; | |
2605 | } | |
2606 | ||
42f52ef8 KP |
2607 | /* Called from drm generic code, passed 'crtc' which |
2608 | * we use as a pipe index | |
2609 | */ | |
f71d4af4 | 2610 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2611 | { |
2d1013dd | 2612 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2613 | unsigned long irqflags; |
0a3e67a4 | 2614 | |
1ec14ad3 | 2615 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2616 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2617 | PIPE_VBLANK_INTERRUPT_STATUS | |
2618 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2619 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2620 | } | |
2621 | ||
f71d4af4 | 2622 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2623 | { |
2d1013dd | 2624 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2625 | unsigned long irqflags; |
b518421f | 2626 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2627 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2628 | |
2629 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2630 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2631 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2632 | } | |
2633 | ||
7e231dbe JB |
2634 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2635 | { | |
2d1013dd | 2636 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2637 | unsigned long irqflags; |
7e231dbe JB |
2638 | |
2639 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2640 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2641 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2642 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2643 | } | |
2644 | ||
abd58f01 BW |
2645 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2646 | { | |
2647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2648 | unsigned long irqflags; | |
abd58f01 | 2649 | |
abd58f01 | 2650 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7167d7c6 DV |
2651 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2652 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2653 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2654 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2655 | } | |
2656 | ||
9107e9d2 | 2657 | static bool |
94f7bbe1 | 2658 | ring_idle(struct intel_engine_cs *ring, u32 seqno) |
9107e9d2 CW |
2659 | { |
2660 | return (list_empty(&ring->request_list) || | |
94f7bbe1 | 2661 | i915_seqno_passed(seqno, ring->last_submitted_seqno)); |
f65d9421 BG |
2662 | } |
2663 | ||
a028c4b0 DV |
2664 | static bool |
2665 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2666 | { | |
2667 | if (INTEL_INFO(dev)->gen >= 8) { | |
a6cdb93a | 2668 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2669 | } else { |
2670 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2671 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2672 | MI_SEMAPHORE_REGISTER); | |
2673 | } | |
2674 | } | |
2675 | ||
a4872ba6 | 2676 | static struct intel_engine_cs * |
a6cdb93a | 2677 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
921d42ea DV |
2678 | { |
2679 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2680 | struct intel_engine_cs *signaller; |
921d42ea DV |
2681 | int i; |
2682 | ||
2683 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
a6cdb93a RV |
2684 | for_each_ring(signaller, dev_priv, i) { |
2685 | if (ring == signaller) | |
2686 | continue; | |
2687 | ||
2688 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) | |
2689 | return signaller; | |
2690 | } | |
921d42ea DV |
2691 | } else { |
2692 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2693 | ||
2694 | for_each_ring(signaller, dev_priv, i) { | |
2695 | if(ring == signaller) | |
2696 | continue; | |
2697 | ||
ebc348b2 | 2698 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2699 | return signaller; |
2700 | } | |
2701 | } | |
2702 | ||
a6cdb93a RV |
2703 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
2704 | ring->id, ipehr, offset); | |
921d42ea DV |
2705 | |
2706 | return NULL; | |
2707 | } | |
2708 | ||
a4872ba6 OM |
2709 | static struct intel_engine_cs * |
2710 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) | |
a24a11e6 CW |
2711 | { |
2712 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d | 2713 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2714 | u64 offset = 0; |
2715 | int i, backwards; | |
a24a11e6 CW |
2716 | |
2717 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2718 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2719 | return NULL; |
a24a11e6 | 2720 | |
88fe429d DV |
2721 | /* |
2722 | * HEAD is likely pointing to the dword after the actual command, | |
2723 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2724 | * or 4 dwords depending on the semaphore wait command size. |
2725 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2726 | * point at at batch, and semaphores are always emitted into the |
2727 | * ringbuffer itself. | |
a24a11e6 | 2728 | */ |
88fe429d | 2729 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
a6cdb93a | 2730 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
88fe429d | 2731 | |
a6cdb93a | 2732 | for (i = backwards; i; --i) { |
88fe429d DV |
2733 | /* |
2734 | * Be paranoid and presume the hw has gone off into the wild - | |
2735 | * our ring is smaller than what the hardware (and hence | |
2736 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2737 | */ | |
ee1b1e5e | 2738 | head &= ring->buffer->size - 1; |
88fe429d DV |
2739 | |
2740 | /* This here seems to blow up */ | |
ee1b1e5e | 2741 | cmd = ioread32(ring->buffer->virtual_start + head); |
a24a11e6 CW |
2742 | if (cmd == ipehr) |
2743 | break; | |
2744 | ||
88fe429d DV |
2745 | head -= 4; |
2746 | } | |
a24a11e6 | 2747 | |
88fe429d DV |
2748 | if (!i) |
2749 | return NULL; | |
a24a11e6 | 2750 | |
ee1b1e5e | 2751 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
a6cdb93a RV |
2752 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2753 | offset = ioread32(ring->buffer->virtual_start + head + 12); | |
2754 | offset <<= 32; | |
2755 | offset = ioread32(ring->buffer->virtual_start + head + 8); | |
2756 | } | |
2757 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); | |
a24a11e6 CW |
2758 | } |
2759 | ||
a4872ba6 | 2760 | static int semaphore_passed(struct intel_engine_cs *ring) |
6274f212 CW |
2761 | { |
2762 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2763 | struct intel_engine_cs *signaller; |
a0d036b0 | 2764 | u32 seqno; |
6274f212 | 2765 | |
4be17381 | 2766 | ring->hangcheck.deadlock++; |
6274f212 CW |
2767 | |
2768 | signaller = semaphore_waits_for(ring, &seqno); | |
4be17381 CW |
2769 | if (signaller == NULL) |
2770 | return -1; | |
2771 | ||
2772 | /* Prevent pathological recursion due to driver bugs */ | |
2773 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) | |
6274f212 CW |
2774 | return -1; |
2775 | ||
4be17381 CW |
2776 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
2777 | return 1; | |
2778 | ||
a0d036b0 CW |
2779 | /* cursory check for an unkickable deadlock */ |
2780 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
2781 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
2782 | return -1; |
2783 | ||
2784 | return 0; | |
6274f212 CW |
2785 | } |
2786 | ||
2787 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2788 | { | |
a4872ba6 | 2789 | struct intel_engine_cs *ring; |
6274f212 CW |
2790 | int i; |
2791 | ||
2792 | for_each_ring(ring, dev_priv, i) | |
4be17381 | 2793 | ring->hangcheck.deadlock = 0; |
6274f212 CW |
2794 | } |
2795 | ||
ad8beaea | 2796 | static enum intel_ring_hangcheck_action |
a4872ba6 | 2797 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
1ec14ad3 CW |
2798 | { |
2799 | struct drm_device *dev = ring->dev; | |
2800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2801 | u32 tmp; |
2802 | ||
f260fe7b MK |
2803 | if (acthd != ring->hangcheck.acthd) { |
2804 | if (acthd > ring->hangcheck.max_acthd) { | |
2805 | ring->hangcheck.max_acthd = acthd; | |
2806 | return HANGCHECK_ACTIVE; | |
2807 | } | |
2808 | ||
2809 | return HANGCHECK_ACTIVE_LOOP; | |
2810 | } | |
6274f212 | 2811 | |
9107e9d2 | 2812 | if (IS_GEN2(dev)) |
f2f4d82f | 2813 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2814 | |
2815 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2816 | * If so we can simply poke the RB_WAIT bit | |
2817 | * and break the hang. This should work on | |
2818 | * all but the second generation chipsets. | |
2819 | */ | |
2820 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2821 | if (tmp & RING_WAIT) { |
58174462 MK |
2822 | i915_handle_error(dev, false, |
2823 | "Kicking stuck wait on %s", | |
2824 | ring->name); | |
1ec14ad3 | 2825 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2826 | return HANGCHECK_KICK; |
6274f212 CW |
2827 | } |
2828 | ||
2829 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2830 | switch (semaphore_passed(ring)) { | |
2831 | default: | |
f2f4d82f | 2832 | return HANGCHECK_HUNG; |
6274f212 | 2833 | case 1: |
58174462 MK |
2834 | i915_handle_error(dev, false, |
2835 | "Kicking stuck semaphore on %s", | |
2836 | ring->name); | |
6274f212 | 2837 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2838 | return HANGCHECK_KICK; |
6274f212 | 2839 | case 0: |
f2f4d82f | 2840 | return HANGCHECK_WAIT; |
6274f212 | 2841 | } |
9107e9d2 | 2842 | } |
ed5cbb03 | 2843 | |
f2f4d82f | 2844 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2845 | } |
2846 | ||
737b1506 | 2847 | /* |
f65d9421 | 2848 | * This is called when the chip hasn't reported back with completed |
05407ff8 MK |
2849 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2850 | * if there are no progress, hangcheck score for that ring is increased. | |
2851 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2852 | * we kick the ring. If we see no progress on three subsequent calls | |
2853 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2854 | */ |
737b1506 | 2855 | static void i915_hangcheck_elapsed(struct work_struct *work) |
f65d9421 | 2856 | { |
737b1506 CW |
2857 | struct drm_i915_private *dev_priv = |
2858 | container_of(work, typeof(*dev_priv), | |
2859 | gpu_error.hangcheck_work.work); | |
2860 | struct drm_device *dev = dev_priv->dev; | |
a4872ba6 | 2861 | struct intel_engine_cs *ring; |
b4519513 | 2862 | int i; |
05407ff8 | 2863 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2864 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2865 | #define BUSY 1 | |
2866 | #define KICK 5 | |
2867 | #define HUNG 20 | |
893eead0 | 2868 | |
d330a953 | 2869 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2870 | return; |
2871 | ||
b4519513 | 2872 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2873 | u64 acthd; |
2874 | u32 seqno; | |
9107e9d2 | 2875 | bool busy = true; |
05407ff8 | 2876 | |
6274f212 CW |
2877 | semaphore_clear_deadlocks(dev_priv); |
2878 | ||
05407ff8 MK |
2879 | seqno = ring->get_seqno(ring, false); |
2880 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2881 | |
9107e9d2 | 2882 | if (ring->hangcheck.seqno == seqno) { |
94f7bbe1 | 2883 | if (ring_idle(ring, seqno)) { |
da661464 MK |
2884 | ring->hangcheck.action = HANGCHECK_IDLE; |
2885 | ||
9107e9d2 CW |
2886 | if (waitqueue_active(&ring->irq_queue)) { |
2887 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2888 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2889 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2890 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2891 | ring->name); | |
2892 | else | |
2893 | DRM_INFO("Fake missed irq on %s\n", | |
2894 | ring->name); | |
094f9a54 CW |
2895 | wake_up_all(&ring->irq_queue); |
2896 | } | |
2897 | /* Safeguard against driver failure */ | |
2898 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2899 | } else |
2900 | busy = false; | |
05407ff8 | 2901 | } else { |
6274f212 CW |
2902 | /* We always increment the hangcheck score |
2903 | * if the ring is busy and still processing | |
2904 | * the same request, so that no single request | |
2905 | * can run indefinitely (such as a chain of | |
2906 | * batches). The only time we do not increment | |
2907 | * the hangcheck score on this ring, if this | |
2908 | * ring is in a legitimate wait for another | |
2909 | * ring. In that case the waiting ring is a | |
2910 | * victim and we want to be sure we catch the | |
2911 | * right culprit. Then every time we do kick | |
2912 | * the ring, add a small increment to the | |
2913 | * score so that we can catch a batch that is | |
2914 | * being repeatedly kicked and so responsible | |
2915 | * for stalling the machine. | |
2916 | */ | |
ad8beaea MK |
2917 | ring->hangcheck.action = ring_stuck(ring, |
2918 | acthd); | |
2919 | ||
2920 | switch (ring->hangcheck.action) { | |
da661464 | 2921 | case HANGCHECK_IDLE: |
f2f4d82f | 2922 | case HANGCHECK_WAIT: |
f2f4d82f | 2923 | case HANGCHECK_ACTIVE: |
f260fe7b MK |
2924 | break; |
2925 | case HANGCHECK_ACTIVE_LOOP: | |
ea04cb31 | 2926 | ring->hangcheck.score += BUSY; |
6274f212 | 2927 | break; |
f2f4d82f | 2928 | case HANGCHECK_KICK: |
ea04cb31 | 2929 | ring->hangcheck.score += KICK; |
6274f212 | 2930 | break; |
f2f4d82f | 2931 | case HANGCHECK_HUNG: |
ea04cb31 | 2932 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2933 | stuck[i] = true; |
2934 | break; | |
2935 | } | |
05407ff8 | 2936 | } |
9107e9d2 | 2937 | } else { |
da661464 MK |
2938 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2939 | ||
9107e9d2 CW |
2940 | /* Gradually reduce the count so that we catch DoS |
2941 | * attempts across multiple batches. | |
2942 | */ | |
2943 | if (ring->hangcheck.score > 0) | |
2944 | ring->hangcheck.score--; | |
f260fe7b MK |
2945 | |
2946 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; | |
d1e61e7f CW |
2947 | } |
2948 | ||
05407ff8 MK |
2949 | ring->hangcheck.seqno = seqno; |
2950 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2951 | busy_count += busy; |
893eead0 | 2952 | } |
b9201c14 | 2953 | |
92cab734 | 2954 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 2955 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
2956 | DRM_INFO("%s on %s\n", |
2957 | stuck[i] ? "stuck" : "no progress", | |
2958 | ring->name); | |
a43adf07 | 2959 | rings_hung++; |
92cab734 MK |
2960 | } |
2961 | } | |
2962 | ||
05407ff8 | 2963 | if (rings_hung) |
58174462 | 2964 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 2965 | |
05407ff8 MK |
2966 | if (busy_count) |
2967 | /* Reset timer case chip hangs without another request | |
2968 | * being added */ | |
10cd45b6 MK |
2969 | i915_queue_hangcheck(dev); |
2970 | } | |
2971 | ||
2972 | void i915_queue_hangcheck(struct drm_device *dev) | |
2973 | { | |
737b1506 | 2974 | struct i915_gpu_error *e = &to_i915(dev)->gpu_error; |
672e7b7c | 2975 | |
d330a953 | 2976 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
2977 | return; |
2978 | ||
737b1506 CW |
2979 | /* Don't continually defer the hangcheck so that it is always run at |
2980 | * least once after work has been scheduled on any ring. Otherwise, | |
2981 | * we will ignore a hung ring if a second ring is kept busy. | |
2982 | */ | |
2983 | ||
2984 | queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work, | |
2985 | round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2986 | } |
2987 | ||
1c69eb42 | 2988 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
2989 | { |
2990 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2991 | ||
2992 | if (HAS_PCH_NOP(dev)) | |
2993 | return; | |
2994 | ||
f86f3fb0 | 2995 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
2996 | |
2997 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
2998 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 2999 | } |
105b122e | 3000 | |
622364b6 PZ |
3001 | /* |
3002 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3003 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3004 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3005 | * only unmask them as needed with SDEIMR. | |
3006 | * | |
3007 | * This function needs to be called before interrupts are enabled. | |
3008 | */ | |
3009 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3010 | { | |
3011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3012 | ||
3013 | if (HAS_PCH_NOP(dev)) | |
3014 | return; | |
3015 | ||
3016 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3017 | I915_WRITE(SDEIER, 0xffffffff); |
3018 | POSTING_READ(SDEIER); | |
3019 | } | |
3020 | ||
7c4d664e | 3021 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3022 | { |
3023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3024 | ||
f86f3fb0 | 3025 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3026 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3027 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3028 | } |
3029 | ||
1da177e4 LT |
3030 | /* drm_dma.h hooks |
3031 | */ | |
be30b29f | 3032 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 3033 | { |
2d1013dd | 3034 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 3035 | |
0c841212 | 3036 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 3037 | |
f86f3fb0 | 3038 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
3039 | if (IS_GEN7(dev)) |
3040 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 3041 | |
7c4d664e | 3042 | gen5_gt_irq_reset(dev); |
c650156a | 3043 | |
1c69eb42 | 3044 | ibx_irq_reset(dev); |
7d99163d | 3045 | } |
c650156a | 3046 | |
70591a41 VS |
3047 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
3048 | { | |
3049 | enum pipe pipe; | |
3050 | ||
3051 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3052 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3053 | ||
3054 | for_each_pipe(dev_priv, pipe) | |
3055 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3056 | ||
3057 | GEN5_IRQ_RESET(VLV_); | |
3058 | } | |
3059 | ||
7e231dbe JB |
3060 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3061 | { | |
2d1013dd | 3062 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3063 | |
7e231dbe JB |
3064 | /* VLV magic */ |
3065 | I915_WRITE(VLV_IMR, 0); | |
3066 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
3067 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
3068 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
3069 | ||
7c4d664e | 3070 | gen5_gt_irq_reset(dev); |
7e231dbe | 3071 | |
7c4cde39 | 3072 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
7e231dbe | 3073 | |
70591a41 | 3074 | vlv_display_irq_reset(dev_priv); |
7e231dbe JB |
3075 | } |
3076 | ||
d6e3cca3 DV |
3077 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3078 | { | |
3079 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3080 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3081 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3082 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3083 | } | |
3084 | ||
823f6b38 | 3085 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3086 | { |
3087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3088 | int pipe; | |
3089 | ||
abd58f01 BW |
3090 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3091 | POSTING_READ(GEN8_MASTER_IRQ); | |
3092 | ||
d6e3cca3 | 3093 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3094 | |
055e393f | 3095 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3096 | if (intel_display_power_is_enabled(dev_priv, |
3097 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3098 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3099 | |
f86f3fb0 PZ |
3100 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3101 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3102 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3103 | |
266ea3d9 SS |
3104 | if (HAS_PCH_SPLIT(dev)) |
3105 | ibx_irq_reset(dev); | |
abd58f01 | 3106 | } |
09f2344d | 3107 | |
4c6c03be DL |
3108 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
3109 | unsigned int pipe_mask) | |
d49bdb0e | 3110 | { |
1180e206 | 3111 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
d49bdb0e | 3112 | |
13321786 | 3113 | spin_lock_irq(&dev_priv->irq_lock); |
d14c0343 DL |
3114 | if (pipe_mask & 1 << PIPE_A) |
3115 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A, | |
3116 | dev_priv->de_irq_mask[PIPE_A], | |
3117 | ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); | |
4c6c03be DL |
3118 | if (pipe_mask & 1 << PIPE_B) |
3119 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, | |
3120 | dev_priv->de_irq_mask[PIPE_B], | |
3121 | ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); | |
3122 | if (pipe_mask & 1 << PIPE_C) | |
3123 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, | |
3124 | dev_priv->de_irq_mask[PIPE_C], | |
3125 | ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); | |
13321786 | 3126 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3127 | } |
3128 | ||
43f328d7 VS |
3129 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3130 | { | |
3131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3132 | |
3133 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3134 | POSTING_READ(GEN8_MASTER_IRQ); | |
3135 | ||
d6e3cca3 | 3136 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3137 | |
3138 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3139 | ||
43f328d7 VS |
3140 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
3141 | ||
70591a41 | 3142 | vlv_display_irq_reset(dev_priv); |
43f328d7 VS |
3143 | } |
3144 | ||
87a02106 VS |
3145 | static u32 intel_hpd_enabled_irqs(struct drm_device *dev, |
3146 | const u32 hpd[HPD_NUM_PINS]) | |
3147 | { | |
3148 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3149 | struct intel_encoder *encoder; | |
3150 | u32 enabled_irqs = 0; | |
3151 | ||
3152 | for_each_intel_encoder(dev, encoder) | |
3153 | if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) | |
3154 | enabled_irqs |= hpd[encoder->hpd_pin]; | |
3155 | ||
3156 | return enabled_irqs; | |
3157 | } | |
3158 | ||
82a28bcf | 3159 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3160 | { |
2d1013dd | 3161 | struct drm_i915_private *dev_priv = dev->dev_private; |
87a02106 | 3162 | u32 hotplug_irqs, hotplug, enabled_irqs; |
82a28bcf DV |
3163 | |
3164 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3165 | hotplug_irqs = SDE_HOTPLUG_MASK; |
87a02106 | 3166 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx); |
82a28bcf | 3167 | } else { |
fee884ed | 3168 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
87a02106 | 3169 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt); |
82a28bcf | 3170 | } |
7fe0b973 | 3171 | |
fee884ed | 3172 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3173 | |
3174 | /* | |
3175 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
6dbf30ce VS |
3176 | * duration to 2ms (which is the minimum in the Display Port spec). |
3177 | * The pulse duration bits are reserved on LPT+. | |
82a28bcf | 3178 | */ |
7fe0b973 KP |
3179 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3180 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3181 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3182 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3183 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
0b2eb33e VS |
3184 | /* |
3185 | * When CPU and PCH are on the same package, port A | |
3186 | * HPD must be enabled in both north and south. | |
3187 | */ | |
3188 | if (HAS_PCH_LPT_LP(dev)) | |
3189 | hotplug |= PORTA_HOTPLUG_ENABLE; | |
7fe0b973 | 3190 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
6dbf30ce | 3191 | } |
26951caf | 3192 | |
6dbf30ce VS |
3193 | static void spt_hpd_irq_setup(struct drm_device *dev) |
3194 | { | |
3195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3196 | u32 hotplug_irqs, hotplug, enabled_irqs; | |
3197 | ||
3198 | hotplug_irqs = SDE_HOTPLUG_MASK_SPT; | |
3199 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt); | |
3200 | ||
3201 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); | |
3202 | ||
3203 | /* Enable digital hotplug on the PCH */ | |
3204 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
3205 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE | | |
3206 | PORTB_HOTPLUG_ENABLE; | |
3207 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
3208 | ||
3209 | hotplug = I915_READ(PCH_PORT_HOTPLUG2); | |
3210 | hotplug |= PORTE_HOTPLUG_ENABLE; | |
3211 | I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); | |
7fe0b973 KP |
3212 | } |
3213 | ||
e4ce95aa VS |
3214 | static void ilk_hpd_irq_setup(struct drm_device *dev) |
3215 | { | |
3216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3217 | u32 hotplug_irqs, hotplug, enabled_irqs; | |
3218 | ||
3a3b3c7d VS |
3219 | if (INTEL_INFO(dev)->gen >= 8) { |
3220 | hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; | |
3221 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw); | |
3222 | ||
3223 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
3224 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
23bb4cb5 VS |
3225 | hotplug_irqs = DE_DP_A_HOTPLUG_IVB; |
3226 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb); | |
3a3b3c7d VS |
3227 | |
3228 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
23bb4cb5 VS |
3229 | } else { |
3230 | hotplug_irqs = DE_DP_A_HOTPLUG; | |
3231 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk); | |
e4ce95aa | 3232 | |
3a3b3c7d VS |
3233 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); |
3234 | } | |
e4ce95aa VS |
3235 | |
3236 | /* | |
3237 | * Enable digital hotplug on the CPU, and configure the DP short pulse | |
3238 | * duration to 2ms (which is the minimum in the Display Port spec) | |
23bb4cb5 | 3239 | * The pulse duration bits are reserved on HSW+. |
e4ce95aa VS |
3240 | */ |
3241 | hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
3242 | hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK; | |
3243 | hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms; | |
3244 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); | |
3245 | ||
3246 | ibx_hpd_irq_setup(dev); | |
3247 | } | |
3248 | ||
e0a20ad7 SS |
3249 | static void bxt_hpd_irq_setup(struct drm_device *dev) |
3250 | { | |
3251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87a02106 | 3252 | u32 hotplug_port; |
e0a20ad7 SS |
3253 | u32 hotplug_ctrl; |
3254 | ||
87a02106 | 3255 | hotplug_port = intel_hpd_enabled_irqs(dev, hpd_bxt); |
e0a20ad7 | 3256 | |
e0a20ad7 SS |
3257 | hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK; |
3258 | ||
7f3561be SJ |
3259 | if (hotplug_port & BXT_DE_PORT_HP_DDIA) |
3260 | hotplug_ctrl |= BXT_DDIA_HPD_ENABLE; | |
e0a20ad7 SS |
3261 | if (hotplug_port & BXT_DE_PORT_HP_DDIB) |
3262 | hotplug_ctrl |= BXT_DDIB_HPD_ENABLE; | |
3263 | if (hotplug_port & BXT_DE_PORT_HP_DDIC) | |
3264 | hotplug_ctrl |= BXT_DDIC_HPD_ENABLE; | |
3265 | I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl); | |
3266 | ||
e0a20ad7 SS |
3267 | hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port; |
3268 | I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl); | |
3269 | ||
e0a20ad7 SS |
3270 | hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port; |
3271 | I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl); | |
3272 | POSTING_READ(GEN8_DE_PORT_IER); | |
3273 | } | |
3274 | ||
d46da437 PZ |
3275 | static void ibx_irq_postinstall(struct drm_device *dev) |
3276 | { | |
2d1013dd | 3277 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3278 | u32 mask; |
e5868a31 | 3279 | |
692a04cf DV |
3280 | if (HAS_PCH_NOP(dev)) |
3281 | return; | |
3282 | ||
105b122e | 3283 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3284 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3285 | else |
5c673b60 | 3286 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3287 | |
337ba017 | 3288 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3289 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3290 | } |
3291 | ||
0a9a8c91 DV |
3292 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3293 | { | |
3294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3295 | u32 pm_irqs, gt_irqs; | |
3296 | ||
3297 | pm_irqs = gt_irqs = 0; | |
3298 | ||
3299 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3300 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3301 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3302 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3303 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3304 | } |
3305 | ||
3306 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3307 | if (IS_GEN5(dev)) { | |
3308 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3309 | ILK_BSD_USER_INTERRUPT; | |
3310 | } else { | |
3311 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3312 | } | |
3313 | ||
35079899 | 3314 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3315 | |
3316 | if (INTEL_INFO(dev)->gen >= 6) { | |
78e68d36 ID |
3317 | /* |
3318 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3319 | * itself is enabled/disabled. | |
3320 | */ | |
0a9a8c91 DV |
3321 | if (HAS_VEBOX(dev)) |
3322 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3323 | ||
605cd25b | 3324 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3325 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3326 | } |
3327 | } | |
3328 | ||
f71d4af4 | 3329 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3330 | { |
2d1013dd | 3331 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3332 | u32 display_mask, extra_mask; |
3333 | ||
3334 | if (INTEL_INFO(dev)->gen >= 7) { | |
3335 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3336 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3337 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3338 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3339 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
23bb4cb5 VS |
3340 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | |
3341 | DE_DP_A_HOTPLUG_IVB); | |
8e76f8dc PZ |
3342 | } else { |
3343 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3344 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3345 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3346 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3347 | DE_POISON); | |
e4ce95aa VS |
3348 | extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3349 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | | |
3350 | DE_DP_A_HOTPLUG); | |
8e76f8dc | 3351 | } |
036a4a7d | 3352 | |
1ec14ad3 | 3353 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3354 | |
0c841212 PZ |
3355 | I915_WRITE(HWSTAM, 0xeffe); |
3356 | ||
622364b6 PZ |
3357 | ibx_irq_pre_postinstall(dev); |
3358 | ||
35079899 | 3359 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3360 | |
0a9a8c91 | 3361 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3362 | |
d46da437 | 3363 | ibx_irq_postinstall(dev); |
7fe0b973 | 3364 | |
f97108d1 | 3365 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3366 | /* Enable PCU event interrupts |
3367 | * | |
3368 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3369 | * setup is guaranteed to run in single-threaded context. But we |
3370 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3371 | spin_lock_irq(&dev_priv->irq_lock); |
f97108d1 | 3372 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3373 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3374 | } |
3375 | ||
036a4a7d ZW |
3376 | return 0; |
3377 | } | |
3378 | ||
f8b79e58 ID |
3379 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3380 | { | |
3381 | u32 pipestat_mask; | |
3382 | u32 iir_mask; | |
120dda4f | 3383 | enum pipe pipe; |
f8b79e58 ID |
3384 | |
3385 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3386 | PIPE_FIFO_UNDERRUN_STATUS; | |
3387 | ||
120dda4f VS |
3388 | for_each_pipe(dev_priv, pipe) |
3389 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3390 | POSTING_READ(PIPESTAT(PIPE_A)); |
3391 | ||
3392 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3393 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3394 | ||
120dda4f VS |
3395 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3396 | for_each_pipe(dev_priv, pipe) | |
3397 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3398 | |
3399 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3400 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3401 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
120dda4f VS |
3402 | if (IS_CHERRYVIEW(dev_priv)) |
3403 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3404 | dev_priv->irq_mask &= ~iir_mask; |
3405 | ||
3406 | I915_WRITE(VLV_IIR, iir_mask); | |
3407 | I915_WRITE(VLV_IIR, iir_mask); | |
f8b79e58 | 3408 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
76e41860 VS |
3409 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3410 | POSTING_READ(VLV_IMR); | |
f8b79e58 ID |
3411 | } |
3412 | ||
3413 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3414 | { | |
3415 | u32 pipestat_mask; | |
3416 | u32 iir_mask; | |
120dda4f | 3417 | enum pipe pipe; |
f8b79e58 ID |
3418 | |
3419 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3420 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3421 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
120dda4f VS |
3422 | if (IS_CHERRYVIEW(dev_priv)) |
3423 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3424 | |
3425 | dev_priv->irq_mask |= iir_mask; | |
f8b79e58 | 3426 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
76e41860 | 3427 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
f8b79e58 ID |
3428 | I915_WRITE(VLV_IIR, iir_mask); |
3429 | I915_WRITE(VLV_IIR, iir_mask); | |
3430 | POSTING_READ(VLV_IIR); | |
3431 | ||
3432 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3433 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3434 | ||
120dda4f VS |
3435 | i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3436 | for_each_pipe(dev_priv, pipe) | |
3437 | i915_disable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3438 | |
3439 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3440 | PIPE_FIFO_UNDERRUN_STATUS; | |
120dda4f VS |
3441 | |
3442 | for_each_pipe(dev_priv, pipe) | |
3443 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3444 | POSTING_READ(PIPESTAT(PIPE_A)); |
3445 | } | |
3446 | ||
3447 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3448 | { | |
3449 | assert_spin_locked(&dev_priv->irq_lock); | |
3450 | ||
3451 | if (dev_priv->display_irqs_enabled) | |
3452 | return; | |
3453 | ||
3454 | dev_priv->display_irqs_enabled = true; | |
3455 | ||
950eabaf | 3456 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3457 | valleyview_display_irqs_install(dev_priv); |
3458 | } | |
3459 | ||
3460 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3461 | { | |
3462 | assert_spin_locked(&dev_priv->irq_lock); | |
3463 | ||
3464 | if (!dev_priv->display_irqs_enabled) | |
3465 | return; | |
3466 | ||
3467 | dev_priv->display_irqs_enabled = false; | |
3468 | ||
950eabaf | 3469 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3470 | valleyview_display_irqs_uninstall(dev_priv); |
3471 | } | |
3472 | ||
0e6c9a9e | 3473 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
7e231dbe | 3474 | { |
f8b79e58 | 3475 | dev_priv->irq_mask = ~0; |
7e231dbe | 3476 | |
20afbda2 DV |
3477 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3478 | POSTING_READ(PORT_HOTPLUG_EN); | |
3479 | ||
7e231dbe | 3480 | I915_WRITE(VLV_IIR, 0xffffffff); |
76e41860 VS |
3481 | I915_WRITE(VLV_IIR, 0xffffffff); |
3482 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3483 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3484 | POSTING_READ(VLV_IMR); | |
7e231dbe | 3485 | |
b79480ba DV |
3486 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3487 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3488 | spin_lock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3489 | if (dev_priv->display_irqs_enabled) |
3490 | valleyview_display_irqs_install(dev_priv); | |
d6207435 | 3491 | spin_unlock_irq(&dev_priv->irq_lock); |
0e6c9a9e VS |
3492 | } |
3493 | ||
3494 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3495 | { | |
3496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3497 | ||
3498 | vlv_display_irq_postinstall(dev_priv); | |
7e231dbe | 3499 | |
0a9a8c91 | 3500 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3501 | |
3502 | /* ack & enable invalid PTE error interrupts */ | |
3503 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3504 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3505 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3506 | #endif | |
3507 | ||
3508 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3509 | |
3510 | return 0; | |
3511 | } | |
3512 | ||
abd58f01 BW |
3513 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3514 | { | |
abd58f01 BW |
3515 | /* These are interrupts we'll toggle with the ring mask register */ |
3516 | uint32_t gt_interrupts[] = { | |
3517 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3518 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
abd58f01 | 3519 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
73d477f6 OM |
3520 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3521 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3522 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3523 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3524 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3525 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3526 | 0, |
73d477f6 OM |
3527 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3528 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3529 | }; |
3530 | ||
0961021a | 3531 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3532 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3533 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3534 | /* |
3535 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
3536 | * is enabled/disabled. | |
3537 | */ | |
3538 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0); | |
9a2d2d87 | 3539 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3540 | } |
3541 | ||
3542 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3543 | { | |
770de83d DL |
3544 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3545 | uint32_t de_pipe_enables; | |
3a3b3c7d VS |
3546 | u32 de_port_masked = GEN8_AUX_CHANNEL_A; |
3547 | u32 de_port_enables; | |
3548 | enum pipe pipe; | |
770de83d | 3549 | |
88e04703 | 3550 | if (IS_GEN9(dev_priv)) { |
770de83d DL |
3551 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3552 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d VS |
3553 | de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3554 | GEN9_AUX_CHANNEL_D; | |
9e63743e | 3555 | if (IS_BROXTON(dev_priv)) |
3a3b3c7d VS |
3556 | de_port_masked |= BXT_DE_PORT_GMBUS; |
3557 | } else { | |
770de83d DL |
3558 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3559 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d | 3560 | } |
770de83d DL |
3561 | |
3562 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3563 | GEN8_PIPE_FIFO_UNDERRUN; | |
3564 | ||
3a3b3c7d VS |
3565 | de_port_enables = de_port_masked; |
3566 | if (IS_BROADWELL(dev_priv)) | |
3567 | de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; | |
3568 | ||
13b3a0a7 DV |
3569 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3570 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3571 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3572 | |
055e393f | 3573 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3574 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3575 | POWER_DOMAIN_PIPE(pipe))) |
3576 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3577 | dev_priv->de_irq_mask[pipe], | |
3578 | de_pipe_enables); | |
abd58f01 | 3579 | |
3a3b3c7d | 3580 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); |
abd58f01 BW |
3581 | } |
3582 | ||
3583 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3584 | { | |
3585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3586 | ||
266ea3d9 SS |
3587 | if (HAS_PCH_SPLIT(dev)) |
3588 | ibx_irq_pre_postinstall(dev); | |
622364b6 | 3589 | |
abd58f01 BW |
3590 | gen8_gt_irq_postinstall(dev_priv); |
3591 | gen8_de_irq_postinstall(dev_priv); | |
3592 | ||
266ea3d9 SS |
3593 | if (HAS_PCH_SPLIT(dev)) |
3594 | ibx_irq_postinstall(dev); | |
abd58f01 BW |
3595 | |
3596 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3597 | POSTING_READ(GEN8_MASTER_IRQ); | |
3598 | ||
3599 | return 0; | |
3600 | } | |
3601 | ||
43f328d7 VS |
3602 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3603 | { | |
3604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 | 3605 | |
c2b66797 | 3606 | vlv_display_irq_postinstall(dev_priv); |
43f328d7 VS |
3607 | |
3608 | gen8_gt_irq_postinstall(dev_priv); | |
3609 | ||
3610 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3611 | POSTING_READ(GEN8_MASTER_IRQ); | |
3612 | ||
3613 | return 0; | |
3614 | } | |
3615 | ||
abd58f01 BW |
3616 | static void gen8_irq_uninstall(struct drm_device *dev) |
3617 | { | |
3618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3619 | |
3620 | if (!dev_priv) | |
3621 | return; | |
3622 | ||
823f6b38 | 3623 | gen8_irq_reset(dev); |
abd58f01 BW |
3624 | } |
3625 | ||
8ea0be4f VS |
3626 | static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv) |
3627 | { | |
3628 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3629 | * just to make the assert_spin_locked check happy. */ | |
3630 | spin_lock_irq(&dev_priv->irq_lock); | |
3631 | if (dev_priv->display_irqs_enabled) | |
3632 | valleyview_display_irqs_uninstall(dev_priv); | |
3633 | spin_unlock_irq(&dev_priv->irq_lock); | |
3634 | ||
3635 | vlv_display_irq_reset(dev_priv); | |
3636 | ||
c352d1ba | 3637 | dev_priv->irq_mask = ~0; |
8ea0be4f VS |
3638 | } |
3639 | ||
7e231dbe JB |
3640 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3641 | { | |
2d1013dd | 3642 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3643 | |
3644 | if (!dev_priv) | |
3645 | return; | |
3646 | ||
843d0e7d ID |
3647 | I915_WRITE(VLV_MASTER_IER, 0); |
3648 | ||
893fce8e VS |
3649 | gen5_gt_irq_reset(dev); |
3650 | ||
7e231dbe | 3651 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3652 | |
8ea0be4f | 3653 | vlv_display_irq_uninstall(dev_priv); |
7e231dbe JB |
3654 | } |
3655 | ||
43f328d7 VS |
3656 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3657 | { | |
3658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3659 | |
3660 | if (!dev_priv) | |
3661 | return; | |
3662 | ||
3663 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3664 | POSTING_READ(GEN8_MASTER_IRQ); | |
3665 | ||
a2c30fba | 3666 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3667 | |
a2c30fba | 3668 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3669 | |
c2b66797 | 3670 | vlv_display_irq_uninstall(dev_priv); |
43f328d7 VS |
3671 | } |
3672 | ||
f71d4af4 | 3673 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3674 | { |
2d1013dd | 3675 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3676 | |
3677 | if (!dev_priv) | |
3678 | return; | |
3679 | ||
be30b29f | 3680 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3681 | } |
3682 | ||
a266c7d5 | 3683 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3684 | { |
2d1013dd | 3685 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3686 | int pipe; |
91e3738e | 3687 | |
055e393f | 3688 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3689 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3690 | I915_WRITE16(IMR, 0xffff); |
3691 | I915_WRITE16(IER, 0x0); | |
3692 | POSTING_READ16(IER); | |
c2798b19 CW |
3693 | } |
3694 | ||
3695 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3696 | { | |
2d1013dd | 3697 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3698 | |
c2798b19 CW |
3699 | I915_WRITE16(EMR, |
3700 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3701 | ||
3702 | /* Unmask the interrupts that we always want on. */ | |
3703 | dev_priv->irq_mask = | |
3704 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3705 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3706 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3707 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
c2798b19 CW |
3708 | I915_WRITE16(IMR, dev_priv->irq_mask); |
3709 | ||
3710 | I915_WRITE16(IER, | |
3711 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3712 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
c2798b19 CW |
3713 | I915_USER_INTERRUPT); |
3714 | POSTING_READ16(IER); | |
3715 | ||
379ef82d DV |
3716 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3717 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3718 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3719 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3720 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3721 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3722 | |
c2798b19 CW |
3723 | return 0; |
3724 | } | |
3725 | ||
90a72f87 VS |
3726 | /* |
3727 | * Returns true when a page flip has completed. | |
3728 | */ | |
3729 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3730 | int plane, int pipe, u32 iir) |
90a72f87 | 3731 | { |
2d1013dd | 3732 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3733 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3734 | |
8d7849db | 3735 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3736 | return false; |
3737 | ||
3738 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3739 | goto check_page_flip; |
90a72f87 | 3740 | |
90a72f87 VS |
3741 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3742 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3743 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3744 | * the flip is completed (no longer pending). Since this doesn't raise | |
3745 | * an interrupt per se, we watch for the change at vblank. | |
3746 | */ | |
3747 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 3748 | goto check_page_flip; |
90a72f87 | 3749 | |
7d47559e | 3750 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3751 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3752 | return true; |
d6bbafa1 CW |
3753 | |
3754 | check_page_flip: | |
3755 | intel_check_page_flip(dev, pipe); | |
3756 | return false; | |
90a72f87 VS |
3757 | } |
3758 | ||
ff1f525e | 3759 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3760 | { |
45a83f84 | 3761 | struct drm_device *dev = arg; |
2d1013dd | 3762 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3763 | u16 iir, new_iir; |
3764 | u32 pipe_stats[2]; | |
c2798b19 CW |
3765 | int pipe; |
3766 | u16 flip_mask = | |
3767 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3768 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3769 | ||
2dd2a883 ID |
3770 | if (!intel_irqs_enabled(dev_priv)) |
3771 | return IRQ_NONE; | |
3772 | ||
c2798b19 CW |
3773 | iir = I915_READ16(IIR); |
3774 | if (iir == 0) | |
3775 | return IRQ_NONE; | |
3776 | ||
3777 | while (iir & ~flip_mask) { | |
3778 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3779 | * have been cleared after the pipestat interrupt was received. | |
3780 | * It doesn't set the bit in iir again, but it still produces | |
3781 | * interrupts (for non-MSI). | |
3782 | */ | |
222c7f51 | 3783 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3784 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3785 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 3786 | |
055e393f | 3787 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3788 | int reg = PIPESTAT(pipe); |
3789 | pipe_stats[pipe] = I915_READ(reg); | |
3790 | ||
3791 | /* | |
3792 | * Clear the PIPE*STAT regs before the IIR | |
3793 | */ | |
2d9d2b0b | 3794 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3795 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3796 | } |
222c7f51 | 3797 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3798 | |
3799 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3800 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3801 | ||
c2798b19 | 3802 | if (iir & I915_USER_INTERRUPT) |
74cdb337 | 3803 | notify_ring(&dev_priv->ring[RCS]); |
c2798b19 | 3804 | |
055e393f | 3805 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 3806 | int plane = pipe; |
3a77c4c4 | 3807 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3808 | plane = !plane; |
3809 | ||
4356d586 | 3810 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3811 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3812 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3813 | |
4356d586 | 3814 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3815 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3816 | |
1f7247c0 DV |
3817 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3818 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3819 | pipe); | |
4356d586 | 3820 | } |
c2798b19 CW |
3821 | |
3822 | iir = new_iir; | |
3823 | } | |
3824 | ||
3825 | return IRQ_HANDLED; | |
3826 | } | |
3827 | ||
3828 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3829 | { | |
2d1013dd | 3830 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3831 | int pipe; |
3832 | ||
055e393f | 3833 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3834 | /* Clear enable bits; then clear status bits */ |
3835 | I915_WRITE(PIPESTAT(pipe), 0); | |
3836 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3837 | } | |
3838 | I915_WRITE16(IMR, 0xffff); | |
3839 | I915_WRITE16(IER, 0x0); | |
3840 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3841 | } | |
3842 | ||
a266c7d5 CW |
3843 | static void i915_irq_preinstall(struct drm_device * dev) |
3844 | { | |
2d1013dd | 3845 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3846 | int pipe; |
3847 | ||
a266c7d5 CW |
3848 | if (I915_HAS_HOTPLUG(dev)) { |
3849 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3850 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3851 | } | |
3852 | ||
00d98ebd | 3853 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3854 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3855 | I915_WRITE(PIPESTAT(pipe), 0); |
3856 | I915_WRITE(IMR, 0xffffffff); | |
3857 | I915_WRITE(IER, 0x0); | |
3858 | POSTING_READ(IER); | |
3859 | } | |
3860 | ||
3861 | static int i915_irq_postinstall(struct drm_device *dev) | |
3862 | { | |
2d1013dd | 3863 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3864 | u32 enable_mask; |
a266c7d5 | 3865 | |
38bde180 CW |
3866 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3867 | ||
3868 | /* Unmask the interrupts that we always want on. */ | |
3869 | dev_priv->irq_mask = | |
3870 | ~(I915_ASLE_INTERRUPT | | |
3871 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3872 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3873 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3874 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
38bde180 CW |
3875 | |
3876 | enable_mask = | |
3877 | I915_ASLE_INTERRUPT | | |
3878 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3879 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
38bde180 CW |
3880 | I915_USER_INTERRUPT; |
3881 | ||
a266c7d5 | 3882 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3883 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3884 | POSTING_READ(PORT_HOTPLUG_EN); | |
3885 | ||
a266c7d5 CW |
3886 | /* Enable in IER... */ |
3887 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3888 | /* and unmask in IMR */ | |
3889 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3890 | } | |
3891 | ||
a266c7d5 CW |
3892 | I915_WRITE(IMR, dev_priv->irq_mask); |
3893 | I915_WRITE(IER, enable_mask); | |
3894 | POSTING_READ(IER); | |
3895 | ||
f49e38dd | 3896 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3897 | |
379ef82d DV |
3898 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3899 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3900 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3901 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3902 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3903 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3904 | |
20afbda2 DV |
3905 | return 0; |
3906 | } | |
3907 | ||
90a72f87 VS |
3908 | /* |
3909 | * Returns true when a page flip has completed. | |
3910 | */ | |
3911 | static bool i915_handle_vblank(struct drm_device *dev, | |
3912 | int plane, int pipe, u32 iir) | |
3913 | { | |
2d1013dd | 3914 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3915 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3916 | ||
8d7849db | 3917 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3918 | return false; |
3919 | ||
3920 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3921 | goto check_page_flip; |
90a72f87 | 3922 | |
90a72f87 VS |
3923 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3924 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3925 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3926 | * the flip is completed (no longer pending). Since this doesn't raise | |
3927 | * an interrupt per se, we watch for the change at vblank. | |
3928 | */ | |
3929 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 3930 | goto check_page_flip; |
90a72f87 | 3931 | |
7d47559e | 3932 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3933 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3934 | return true; |
d6bbafa1 CW |
3935 | |
3936 | check_page_flip: | |
3937 | intel_check_page_flip(dev, pipe); | |
3938 | return false; | |
90a72f87 VS |
3939 | } |
3940 | ||
ff1f525e | 3941 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3942 | { |
45a83f84 | 3943 | struct drm_device *dev = arg; |
2d1013dd | 3944 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3945 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
3946 | u32 flip_mask = |
3947 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3948 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3949 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3950 | |
2dd2a883 ID |
3951 | if (!intel_irqs_enabled(dev_priv)) |
3952 | return IRQ_NONE; | |
3953 | ||
a266c7d5 | 3954 | iir = I915_READ(IIR); |
38bde180 CW |
3955 | do { |
3956 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3957 | bool blc_event = false; |
a266c7d5 CW |
3958 | |
3959 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3960 | * have been cleared after the pipestat interrupt was received. | |
3961 | * It doesn't set the bit in iir again, but it still produces | |
3962 | * interrupts (for non-MSI). | |
3963 | */ | |
222c7f51 | 3964 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3965 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3966 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 3967 | |
055e393f | 3968 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
3969 | int reg = PIPESTAT(pipe); |
3970 | pipe_stats[pipe] = I915_READ(reg); | |
3971 | ||
38bde180 | 3972 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3973 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3974 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3975 | irq_received = true; |
a266c7d5 CW |
3976 | } |
3977 | } | |
222c7f51 | 3978 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
3979 | |
3980 | if (!irq_received) | |
3981 | break; | |
3982 | ||
a266c7d5 | 3983 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
3984 | if (I915_HAS_HOTPLUG(dev) && |
3985 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
3986 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3987 | |
38bde180 | 3988 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3989 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3990 | ||
a266c7d5 | 3991 | if (iir & I915_USER_INTERRUPT) |
74cdb337 | 3992 | notify_ring(&dev_priv->ring[RCS]); |
a266c7d5 | 3993 | |
055e393f | 3994 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 3995 | int plane = pipe; |
3a77c4c4 | 3996 | if (HAS_FBC(dev)) |
38bde180 | 3997 | plane = !plane; |
90a72f87 | 3998 | |
8291ee90 | 3999 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4000 | i915_handle_vblank(dev, plane, pipe, iir)) |
4001 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
4002 | |
4003 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4004 | blc_event = true; | |
4356d586 DV |
4005 | |
4006 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4007 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 4008 | |
1f7247c0 DV |
4009 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4010 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
4011 | pipe); | |
a266c7d5 CW |
4012 | } |
4013 | ||
a266c7d5 CW |
4014 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
4015 | intel_opregion_asle_intr(dev); | |
4016 | ||
4017 | /* With MSI, interrupts are only generated when iir | |
4018 | * transitions from zero to nonzero. If another bit got | |
4019 | * set while we were handling the existing iir bits, then | |
4020 | * we would never get another interrupt. | |
4021 | * | |
4022 | * This is fine on non-MSI as well, as if we hit this path | |
4023 | * we avoid exiting the interrupt handler only to generate | |
4024 | * another one. | |
4025 | * | |
4026 | * Note that for MSI this could cause a stray interrupt report | |
4027 | * if an interrupt landed in the time between writing IIR and | |
4028 | * the posting read. This should be rare enough to never | |
4029 | * trigger the 99% of 100,000 interrupts test for disabling | |
4030 | * stray interrupts. | |
4031 | */ | |
38bde180 | 4032 | ret = IRQ_HANDLED; |
a266c7d5 | 4033 | iir = new_iir; |
38bde180 | 4034 | } while (iir & ~flip_mask); |
a266c7d5 CW |
4035 | |
4036 | return ret; | |
4037 | } | |
4038 | ||
4039 | static void i915_irq_uninstall(struct drm_device * dev) | |
4040 | { | |
2d1013dd | 4041 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4042 | int pipe; |
4043 | ||
a266c7d5 CW |
4044 | if (I915_HAS_HOTPLUG(dev)) { |
4045 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
4046 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
4047 | } | |
4048 | ||
00d98ebd | 4049 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 4050 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 4051 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 4052 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4053 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4054 | } | |
a266c7d5 CW |
4055 | I915_WRITE(IMR, 0xffffffff); |
4056 | I915_WRITE(IER, 0x0); | |
4057 | ||
a266c7d5 CW |
4058 | I915_WRITE(IIR, I915_READ(IIR)); |
4059 | } | |
4060 | ||
4061 | static void i965_irq_preinstall(struct drm_device * dev) | |
4062 | { | |
2d1013dd | 4063 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4064 | int pipe; |
4065 | ||
adca4730 CW |
4066 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4067 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4068 | |
4069 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4070 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4071 | I915_WRITE(PIPESTAT(pipe), 0); |
4072 | I915_WRITE(IMR, 0xffffffff); | |
4073 | I915_WRITE(IER, 0x0); | |
4074 | POSTING_READ(IER); | |
4075 | } | |
4076 | ||
4077 | static int i965_irq_postinstall(struct drm_device *dev) | |
4078 | { | |
2d1013dd | 4079 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4080 | u32 enable_mask; |
a266c7d5 CW |
4081 | u32 error_mask; |
4082 | ||
a266c7d5 | 4083 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4084 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4085 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4086 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4087 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4088 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4089 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4090 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4091 | ||
4092 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4093 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4094 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4095 | enable_mask |= I915_USER_INTERRUPT; |
4096 | ||
4097 | if (IS_G4X(dev)) | |
4098 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 4099 | |
b79480ba DV |
4100 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4101 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4102 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4103 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4104 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4105 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4106 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4107 | |
a266c7d5 CW |
4108 | /* |
4109 | * Enable some error detection, note the instruction error mask | |
4110 | * bit is reserved, so we leave it masked. | |
4111 | */ | |
4112 | if (IS_G4X(dev)) { | |
4113 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4114 | GM45_ERROR_MEM_PRIV | | |
4115 | GM45_ERROR_CP_PRIV | | |
4116 | I915_ERROR_MEMORY_REFRESH); | |
4117 | } else { | |
4118 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4119 | I915_ERROR_MEMORY_REFRESH); | |
4120 | } | |
4121 | I915_WRITE(EMR, error_mask); | |
4122 | ||
4123 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4124 | I915_WRITE(IER, enable_mask); | |
4125 | POSTING_READ(IER); | |
4126 | ||
20afbda2 DV |
4127 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4128 | POSTING_READ(PORT_HOTPLUG_EN); | |
4129 | ||
f49e38dd | 4130 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4131 | |
4132 | return 0; | |
4133 | } | |
4134 | ||
bac56d5b | 4135 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4136 | { |
2d1013dd | 4137 | struct drm_i915_private *dev_priv = dev->dev_private; |
20afbda2 DV |
4138 | u32 hotplug_en; |
4139 | ||
b5ea2d56 DV |
4140 | assert_spin_locked(&dev_priv->irq_lock); |
4141 | ||
778eb334 VS |
4142 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
4143 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
4144 | /* Note HDMI and DP share hotplug bits */ | |
4145 | /* enable bits are the same for all generations */ | |
87a02106 | 4146 | hotplug_en |= intel_hpd_enabled_irqs(dev, hpd_mask_i915); |
778eb334 VS |
4147 | /* Programming the CRT detection parameters tends |
4148 | to generate a spurious hotplug event about three | |
4149 | seconds later. So just do it once. | |
4150 | */ | |
4151 | if (IS_G4X(dev)) | |
4152 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
4153 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; | |
4154 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
4155 | ||
4156 | /* Ignore TV since it's buggy */ | |
4157 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
a266c7d5 CW |
4158 | } |
4159 | ||
ff1f525e | 4160 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4161 | { |
45a83f84 | 4162 | struct drm_device *dev = arg; |
2d1013dd | 4163 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4164 | u32 iir, new_iir; |
4165 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4166 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4167 | u32 flip_mask = |
4168 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4169 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4170 | |
2dd2a883 ID |
4171 | if (!intel_irqs_enabled(dev_priv)) |
4172 | return IRQ_NONE; | |
4173 | ||
a266c7d5 CW |
4174 | iir = I915_READ(IIR); |
4175 | ||
a266c7d5 | 4176 | for (;;) { |
501e01d7 | 4177 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4178 | bool blc_event = false; |
4179 | ||
a266c7d5 CW |
4180 | /* Can't rely on pipestat interrupt bit in iir as it might |
4181 | * have been cleared after the pipestat interrupt was received. | |
4182 | * It doesn't set the bit in iir again, but it still produces | |
4183 | * interrupts (for non-MSI). | |
4184 | */ | |
222c7f51 | 4185 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4186 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4187 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4188 | |
055e393f | 4189 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4190 | int reg = PIPESTAT(pipe); |
4191 | pipe_stats[pipe] = I915_READ(reg); | |
4192 | ||
4193 | /* | |
4194 | * Clear the PIPE*STAT regs before the IIR | |
4195 | */ | |
4196 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4197 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4198 | irq_received = true; |
a266c7d5 CW |
4199 | } |
4200 | } | |
222c7f51 | 4201 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4202 | |
4203 | if (!irq_received) | |
4204 | break; | |
4205 | ||
4206 | ret = IRQ_HANDLED; | |
4207 | ||
4208 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
4209 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
4210 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4211 | |
21ad8330 | 4212 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4213 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4214 | ||
a266c7d5 | 4215 | if (iir & I915_USER_INTERRUPT) |
74cdb337 | 4216 | notify_ring(&dev_priv->ring[RCS]); |
a266c7d5 | 4217 | if (iir & I915_BSD_USER_INTERRUPT) |
74cdb337 | 4218 | notify_ring(&dev_priv->ring[VCS]); |
a266c7d5 | 4219 | |
055e393f | 4220 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 4221 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4222 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4223 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4224 | |
4225 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4226 | blc_event = true; | |
4356d586 DV |
4227 | |
4228 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4229 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4230 | |
1f7247c0 DV |
4231 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4232 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4233 | } |
a266c7d5 CW |
4234 | |
4235 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4236 | intel_opregion_asle_intr(dev); | |
4237 | ||
515ac2bb DV |
4238 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4239 | gmbus_irq_handler(dev); | |
4240 | ||
a266c7d5 CW |
4241 | /* With MSI, interrupts are only generated when iir |
4242 | * transitions from zero to nonzero. If another bit got | |
4243 | * set while we were handling the existing iir bits, then | |
4244 | * we would never get another interrupt. | |
4245 | * | |
4246 | * This is fine on non-MSI as well, as if we hit this path | |
4247 | * we avoid exiting the interrupt handler only to generate | |
4248 | * another one. | |
4249 | * | |
4250 | * Note that for MSI this could cause a stray interrupt report | |
4251 | * if an interrupt landed in the time between writing IIR and | |
4252 | * the posting read. This should be rare enough to never | |
4253 | * trigger the 99% of 100,000 interrupts test for disabling | |
4254 | * stray interrupts. | |
4255 | */ | |
4256 | iir = new_iir; | |
4257 | } | |
4258 | ||
4259 | return ret; | |
4260 | } | |
4261 | ||
4262 | static void i965_irq_uninstall(struct drm_device * dev) | |
4263 | { | |
2d1013dd | 4264 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4265 | int pipe; |
4266 | ||
4267 | if (!dev_priv) | |
4268 | return; | |
4269 | ||
adca4730 CW |
4270 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4271 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4272 | |
4273 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4274 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4275 | I915_WRITE(PIPESTAT(pipe), 0); |
4276 | I915_WRITE(IMR, 0xffffffff); | |
4277 | I915_WRITE(IER, 0x0); | |
4278 | ||
055e393f | 4279 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4280 | I915_WRITE(PIPESTAT(pipe), |
4281 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4282 | I915_WRITE(IIR, I915_READ(IIR)); | |
4283 | } | |
4284 | ||
fca52a55 DV |
4285 | /** |
4286 | * intel_irq_init - initializes irq support | |
4287 | * @dev_priv: i915 device instance | |
4288 | * | |
4289 | * This function initializes all the irq support including work items, timers | |
4290 | * and all the vtables. It does not setup the interrupt itself though. | |
4291 | */ | |
b963291c | 4292 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4293 | { |
b963291c | 4294 | struct drm_device *dev = dev_priv->dev; |
8b2e326d | 4295 | |
77913b39 JN |
4296 | intel_hpd_init_work(dev_priv); |
4297 | ||
c6a828d3 | 4298 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4299 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4300 | |
a6706b45 | 4301 | /* Let's track the enabled rps events */ |
b963291c | 4302 | if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6c65a587 | 4303 | /* WaGsvRC0ResidencyMethod:vlv */ |
6f4b12f8 | 4304 | dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; |
31685c25 D |
4305 | else |
4306 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4307 | |
737b1506 CW |
4308 | INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work, |
4309 | i915_hangcheck_elapsed); | |
61bac78e | 4310 | |
97a19a24 | 4311 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4312 | |
b963291c | 4313 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4314 | dev->max_vblank_count = 0; |
4315 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4316 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 JB |
4317 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4318 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4319 | } else { |
4320 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4321 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4322 | } |
4323 | ||
21da2700 VS |
4324 | /* |
4325 | * Opt out of the vblank disable timer on everything except gen2. | |
4326 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4327 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4328 | */ | |
b963291c | 4329 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4330 | dev->vblank_disable_immediate = true; |
4331 | ||
f3a5c3f6 DV |
4332 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
4333 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; | |
f71d4af4 | 4334 | |
b963291c | 4335 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4336 | dev->driver->irq_handler = cherryview_irq_handler; |
4337 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4338 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4339 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4340 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4341 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4342 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4343 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4344 | dev->driver->irq_handler = valleyview_irq_handler; |
4345 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4346 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4347 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4348 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4349 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4350 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4351 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4352 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4353 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4354 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4355 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4356 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4357 | dev->driver->disable_vblank = gen8_disable_vblank; | |
6dbf30ce | 4358 | if (IS_BROXTON(dev)) |
e0a20ad7 | 4359 | dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; |
6dbf30ce VS |
4360 | else if (HAS_PCH_SPT(dev)) |
4361 | dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; | |
4362 | else | |
3a3b3c7d | 4363 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 JB |
4364 | } else if (HAS_PCH_SPLIT(dev)) { |
4365 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4366 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4367 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4368 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4369 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4370 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
23bb4cb5 | 4371 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 | 4372 | } else { |
b963291c | 4373 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4374 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4375 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4376 | dev->driver->irq_handler = i8xx_irq_handler; | |
4377 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4378 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4379 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4380 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4381 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4382 | dev->driver->irq_handler = i915_irq_handler; | |
c2798b19 | 4383 | } else { |
a266c7d5 CW |
4384 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4385 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4386 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4387 | dev->driver->irq_handler = i965_irq_handler; | |
c2798b19 | 4388 | } |
778eb334 VS |
4389 | if (I915_HAS_HOTPLUG(dev_priv)) |
4390 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
f71d4af4 JB |
4391 | dev->driver->enable_vblank = i915_enable_vblank; |
4392 | dev->driver->disable_vblank = i915_disable_vblank; | |
4393 | } | |
4394 | } | |
20afbda2 | 4395 | |
fca52a55 DV |
4396 | /** |
4397 | * intel_irq_install - enables the hardware interrupt | |
4398 | * @dev_priv: i915 device instance | |
4399 | * | |
4400 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4401 | * handling still disabled. It is called after intel_irq_init(). | |
4402 | * | |
4403 | * In the driver load and resume code we need working interrupts in a few places | |
4404 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4405 | * workers. Hence the split into this two-stage approach. | |
4406 | */ | |
2aeb7d3a DV |
4407 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4408 | { | |
4409 | /* | |
4410 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4411 | * interrupts as enabled _before_ actually enabling them to avoid | |
4412 | * special cases in our ordering checks. | |
4413 | */ | |
4414 | dev_priv->pm.irqs_enabled = true; | |
4415 | ||
4416 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4417 | } | |
4418 | ||
fca52a55 DV |
4419 | /** |
4420 | * intel_irq_uninstall - finilizes all irq handling | |
4421 | * @dev_priv: i915 device instance | |
4422 | * | |
4423 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4424 | * resources acquired in the init functions. | |
4425 | */ | |
2aeb7d3a DV |
4426 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4427 | { | |
4428 | drm_irq_uninstall(dev_priv->dev); | |
4429 | intel_hpd_cancel_work(dev_priv); | |
4430 | dev_priv->pm.irqs_enabled = false; | |
4431 | } | |
4432 | ||
fca52a55 DV |
4433 | /** |
4434 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4435 | * @dev_priv: i915 device instance | |
4436 | * | |
4437 | * This function is used to disable interrupts at runtime, both in the runtime | |
4438 | * pm and the system suspend/resume code. | |
4439 | */ | |
b963291c | 4440 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4441 | { |
b963291c | 4442 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4443 | dev_priv->pm.irqs_enabled = false; |
2dd2a883 | 4444 | synchronize_irq(dev_priv->dev->irq); |
c67a470b PZ |
4445 | } |
4446 | ||
fca52a55 DV |
4447 | /** |
4448 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4449 | * @dev_priv: i915 device instance | |
4450 | * | |
4451 | * This function is used to enable interrupts at runtime, both in the runtime | |
4452 | * pm and the system suspend/resume code. | |
4453 | */ | |
b963291c | 4454 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4455 | { |
2aeb7d3a | 4456 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4457 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4458 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4459 | } |