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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
79e53945 | 33 | #include "intel_drv.h" |
1da177e4 | 34 | |
1da177e4 | 35 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 36 | |
7c463586 KP |
37 | /** |
38 | * Interrupts that are always left unmasked. | |
39 | * | |
40 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
41 | * we leave them always unmasked in IMR and then control enabling them through | |
42 | * PIPESTAT alone. | |
43 | */ | |
44 | #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ | |
45 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
46 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) | |
47 | ||
48 | /** Interrupts that we mask and unmask at runtime. */ | |
49 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) | |
50 | ||
79e53945 JB |
51 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
52 | PIPE_VBLANK_INTERRUPT_STATUS) | |
53 | ||
54 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
55 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
56 | ||
57 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
58 | DRM_I915_VBLANK_PIPE_B) | |
59 | ||
036a4a7d ZW |
60 | void |
61 | igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) | |
62 | { | |
63 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { | |
64 | dev_priv->gt_irq_mask_reg &= ~mask; | |
65 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
66 | (void) I915_READ(GTIMR); | |
67 | } | |
68 | } | |
69 | ||
70 | static inline void | |
71 | igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) | |
72 | { | |
73 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { | |
74 | dev_priv->gt_irq_mask_reg |= mask; | |
75 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
76 | (void) I915_READ(GTIMR); | |
77 | } | |
78 | } | |
79 | ||
80 | /* For display hotplug interrupt */ | |
81 | void | |
82 | igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) | |
83 | { | |
84 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
85 | dev_priv->irq_mask_reg &= ~mask; | |
86 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
87 | (void) I915_READ(DEIMR); | |
88 | } | |
89 | } | |
90 | ||
91 | static inline void | |
92 | igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) | |
93 | { | |
94 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
95 | dev_priv->irq_mask_reg |= mask; | |
96 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
97 | (void) I915_READ(DEIMR); | |
98 | } | |
99 | } | |
100 | ||
8ee1c3db | 101 | void |
ed4cb414 EA |
102 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
103 | { | |
104 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
105 | dev_priv->irq_mask_reg &= ~mask; | |
106 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
107 | (void) I915_READ(IMR); | |
108 | } | |
109 | } | |
110 | ||
111 | static inline void | |
112 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
113 | { | |
114 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
115 | dev_priv->irq_mask_reg |= mask; | |
116 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
117 | (void) I915_READ(IMR); | |
118 | } | |
119 | } | |
120 | ||
7c463586 KP |
121 | static inline u32 |
122 | i915_pipestat(int pipe) | |
123 | { | |
124 | if (pipe == 0) | |
125 | return PIPEASTAT; | |
126 | if (pipe == 1) | |
127 | return PIPEBSTAT; | |
9c84ba4e | 128 | BUG(); |
7c463586 KP |
129 | } |
130 | ||
131 | void | |
132 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
133 | { | |
134 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
135 | u32 reg = i915_pipestat(pipe); | |
136 | ||
137 | dev_priv->pipestat[pipe] |= mask; | |
138 | /* Enable the interrupt, clear any pending status */ | |
139 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
140 | (void) I915_READ(reg); | |
141 | } | |
142 | } | |
143 | ||
144 | void | |
145 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
146 | { | |
147 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
148 | u32 reg = i915_pipestat(pipe); | |
149 | ||
150 | dev_priv->pipestat[pipe] &= ~mask; | |
151 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
152 | (void) I915_READ(reg); | |
153 | } | |
154 | } | |
155 | ||
0a3e67a4 JB |
156 | /** |
157 | * i915_pipe_enabled - check if a pipe is enabled | |
158 | * @dev: DRM device | |
159 | * @pipe: pipe to check | |
160 | * | |
161 | * Reading certain registers when the pipe is disabled can hang the chip. | |
162 | * Use this routine to make sure the PLL is running and the pipe is active | |
163 | * before reading such registers if unsure. | |
164 | */ | |
165 | static int | |
166 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
167 | { | |
168 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
169 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; | |
170 | ||
171 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) | |
172 | return 1; | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
42f52ef8 KP |
177 | /* Called from drm generic code, passed a 'crtc', which |
178 | * we use as a pipe index | |
179 | */ | |
180 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
181 | { |
182 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
183 | unsigned long high_frame; | |
184 | unsigned long low_frame; | |
185 | u32 high1, high2, low, count; | |
0a3e67a4 | 186 | |
0a3e67a4 JB |
187 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
188 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
189 | ||
190 | if (!i915_pipe_enabled(dev, pipe)) { | |
191 | DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); | |
192 | return 0; | |
193 | } | |
194 | ||
195 | /* | |
196 | * High & low register fields aren't synchronized, so make sure | |
197 | * we get a low value that's stable across two reads of the high | |
198 | * register. | |
199 | */ | |
200 | do { | |
201 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
202 | PIPE_FRAME_HIGH_SHIFT); | |
203 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> | |
204 | PIPE_FRAME_LOW_SHIFT); | |
205 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
206 | PIPE_FRAME_HIGH_SHIFT); | |
207 | } while (high1 != high2); | |
208 | ||
209 | count = (high1 << 8) | low; | |
210 | ||
211 | return count; | |
212 | } | |
213 | ||
9880b7a5 JB |
214 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
215 | { | |
216 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
217 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | |
218 | ||
219 | if (!i915_pipe_enabled(dev, pipe)) { | |
220 | DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); | |
221 | return 0; | |
222 | } | |
223 | ||
224 | return I915_READ(reg); | |
225 | } | |
226 | ||
5ca58282 JB |
227 | /* |
228 | * Handle hotplug events outside the interrupt handler proper. | |
229 | */ | |
230 | static void i915_hotplug_work_func(struct work_struct *work) | |
231 | { | |
232 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
233 | hotplug_work); | |
234 | struct drm_device *dev = dev_priv->dev; | |
235 | ||
236 | /* Just fire off a uevent and let userspace tell us what to do */ | |
237 | drm_sysfs_hotplug_event(dev); | |
238 | } | |
239 | ||
036a4a7d ZW |
240 | irqreturn_t igdng_irq_handler(struct drm_device *dev) |
241 | { | |
242 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
243 | int ret = IRQ_NONE; | |
244 | u32 de_iir, gt_iir; | |
245 | u32 new_de_iir, new_gt_iir; | |
246 | struct drm_i915_master_private *master_priv; | |
247 | ||
248 | de_iir = I915_READ(DEIIR); | |
249 | gt_iir = I915_READ(GTIIR); | |
250 | ||
251 | for (;;) { | |
252 | if (de_iir == 0 && gt_iir == 0) | |
253 | break; | |
254 | ||
255 | ret = IRQ_HANDLED; | |
256 | ||
257 | I915_WRITE(DEIIR, de_iir); | |
258 | new_de_iir = I915_READ(DEIIR); | |
259 | I915_WRITE(GTIIR, gt_iir); | |
260 | new_gt_iir = I915_READ(GTIIR); | |
261 | ||
262 | if (dev->primary->master) { | |
263 | master_priv = dev->primary->master->driver_priv; | |
264 | if (master_priv->sarea_priv) | |
265 | master_priv->sarea_priv->last_dispatch = | |
266 | READ_BREADCRUMB(dev_priv); | |
267 | } | |
268 | ||
269 | if (gt_iir & GT_USER_INTERRUPT) { | |
270 | dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); | |
271 | DRM_WAKEUP(&dev_priv->irq_queue); | |
272 | } | |
273 | ||
274 | de_iir = new_de_iir; | |
275 | gt_iir = new_gt_iir; | |
276 | } | |
277 | ||
278 | return ret; | |
279 | } | |
280 | ||
1da177e4 LT |
281 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
282 | { | |
84b1fd10 | 283 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 284 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 285 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
286 | u32 iir, new_iir; |
287 | u32 pipea_stats, pipeb_stats; | |
05eff845 KP |
288 | u32 vblank_status; |
289 | u32 vblank_enable; | |
0a3e67a4 | 290 | int vblank = 0; |
7c463586 | 291 | unsigned long irqflags; |
05eff845 KP |
292 | int irq_received; |
293 | int ret = IRQ_NONE; | |
6e5fca53 | 294 | |
630681d9 EA |
295 | atomic_inc(&dev_priv->irq_received); |
296 | ||
036a4a7d ZW |
297 | if (IS_IGDNG(dev)) |
298 | return igdng_irq_handler(dev); | |
299 | ||
ed4cb414 | 300 | iir = I915_READ(IIR); |
a6b54f3f | 301 | |
05eff845 KP |
302 | if (IS_I965G(dev)) { |
303 | vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; | |
304 | vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; | |
305 | } else { | |
306 | vblank_status = I915_VBLANK_INTERRUPT_STATUS; | |
307 | vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; | |
308 | } | |
af6061af | 309 | |
05eff845 KP |
310 | for (;;) { |
311 | irq_received = iir != 0; | |
312 | ||
313 | /* Can't rely on pipestat interrupt bit in iir as it might | |
314 | * have been cleared after the pipestat interrupt was received. | |
315 | * It doesn't set the bit in iir again, but it still produces | |
316 | * interrupts (for non-MSI). | |
317 | */ | |
318 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
319 | pipea_stats = I915_READ(PIPEASTAT); | |
320 | pipeb_stats = I915_READ(PIPEBSTAT); | |
79e53945 | 321 | |
cdfbc41f EA |
322 | /* |
323 | * Clear the PIPE(A|B)STAT regs before the IIR | |
324 | */ | |
05eff845 | 325 | if (pipea_stats & 0x8000ffff) { |
cdfbc41f | 326 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 327 | irq_received = 1; |
cdfbc41f | 328 | } |
1da177e4 | 329 | |
05eff845 | 330 | if (pipeb_stats & 0x8000ffff) { |
cdfbc41f | 331 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 332 | irq_received = 1; |
cdfbc41f | 333 | } |
05eff845 KP |
334 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
335 | ||
336 | if (!irq_received) | |
337 | break; | |
338 | ||
339 | ret = IRQ_HANDLED; | |
8ee1c3db | 340 | |
5ca58282 JB |
341 | /* Consume port. Then clear IIR or we'll miss events */ |
342 | if ((I915_HAS_HOTPLUG(dev)) && | |
343 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
344 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
345 | ||
346 | DRM_DEBUG("hotplug event received, stat 0x%08x\n", | |
347 | hotplug_status); | |
348 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
349 | schedule_work(&dev_priv->hotplug_work); | |
350 | ||
351 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
352 | I915_READ(PORT_HOTPLUG_STAT); | |
353 | } | |
354 | ||
cdfbc41f EA |
355 | I915_WRITE(IIR, iir); |
356 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 357 | |
7c1c2871 DA |
358 | if (dev->primary->master) { |
359 | master_priv = dev->primary->master->driver_priv; | |
360 | if (master_priv->sarea_priv) | |
361 | master_priv->sarea_priv->last_dispatch = | |
362 | READ_BREADCRUMB(dev_priv); | |
363 | } | |
0a3e67a4 | 364 | |
cdfbc41f EA |
365 | if (iir & I915_USER_INTERRUPT) { |
366 | dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); | |
367 | DRM_WAKEUP(&dev_priv->irq_queue); | |
368 | } | |
673a394b | 369 | |
05eff845 | 370 | if (pipea_stats & vblank_status) { |
cdfbc41f EA |
371 | vblank++; |
372 | drm_handle_vblank(dev, 0); | |
373 | } | |
7c463586 | 374 | |
05eff845 | 375 | if (pipeb_stats & vblank_status) { |
cdfbc41f EA |
376 | vblank++; |
377 | drm_handle_vblank(dev, 1); | |
378 | } | |
7c463586 | 379 | |
cdfbc41f EA |
380 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || |
381 | (iir & I915_ASLE_INTERRUPT)) | |
382 | opregion_asle_intr(dev); | |
383 | ||
384 | /* With MSI, interrupts are only generated when iir | |
385 | * transitions from zero to nonzero. If another bit got | |
386 | * set while we were handling the existing iir bits, then | |
387 | * we would never get another interrupt. | |
388 | * | |
389 | * This is fine on non-MSI as well, as if we hit this path | |
390 | * we avoid exiting the interrupt handler only to generate | |
391 | * another one. | |
392 | * | |
393 | * Note that for MSI this could cause a stray interrupt report | |
394 | * if an interrupt landed in the time between writing IIR and | |
395 | * the posting read. This should be rare enough to never | |
396 | * trigger the 99% of 100,000 interrupts test for disabling | |
397 | * stray interrupts. | |
398 | */ | |
399 | iir = new_iir; | |
05eff845 | 400 | } |
0a3e67a4 | 401 | |
05eff845 | 402 | return ret; |
1da177e4 LT |
403 | } |
404 | ||
af6061af | 405 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
406 | { |
407 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 408 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
409 | RING_LOCALS; |
410 | ||
411 | i915_kernel_lost_context(dev); | |
412 | ||
3e684eae | 413 | DRM_DEBUG("\n"); |
1da177e4 | 414 | |
c99b058f | 415 | dev_priv->counter++; |
c29b669c | 416 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 417 | dev_priv->counter = 1; |
7c1c2871 DA |
418 | if (master_priv->sarea_priv) |
419 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 420 | |
0baf823a | 421 | BEGIN_LP_RING(4); |
585fb111 | 422 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 423 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
c29b669c | 424 | OUT_RING(dev_priv->counter); |
585fb111 | 425 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 426 | ADVANCE_LP_RING(); |
bc5f4523 | 427 | |
c29b669c | 428 | return dev_priv->counter; |
1da177e4 LT |
429 | } |
430 | ||
673a394b | 431 | void i915_user_irq_get(struct drm_device *dev) |
ed4cb414 EA |
432 | { |
433 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 434 | unsigned long irqflags; |
ed4cb414 | 435 | |
e9d21d7f | 436 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
036a4a7d ZW |
437 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { |
438 | if (IS_IGDNG(dev)) | |
439 | igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); | |
440 | else | |
441 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
442 | } | |
e9d21d7f | 443 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
444 | } |
445 | ||
0a3e67a4 | 446 | void i915_user_irq_put(struct drm_device *dev) |
ed4cb414 EA |
447 | { |
448 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 449 | unsigned long irqflags; |
ed4cb414 | 450 | |
e9d21d7f | 451 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 | 452 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
036a4a7d ZW |
453 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { |
454 | if (IS_IGDNG(dev)) | |
455 | igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); | |
456 | else | |
457 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
458 | } | |
e9d21d7f | 459 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
460 | } |
461 | ||
84b1fd10 | 462 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
463 | { |
464 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 465 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
466 | int ret = 0; |
467 | ||
3e684eae | 468 | DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
469 | READ_BREADCRUMB(dev_priv)); |
470 | ||
ed4cb414 | 471 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
472 | if (master_priv->sarea_priv) |
473 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 474 | return 0; |
ed4cb414 | 475 | } |
1da177e4 | 476 | |
7c1c2871 DA |
477 | if (master_priv->sarea_priv) |
478 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 479 | |
ed4cb414 | 480 | i915_user_irq_get(dev); |
1da177e4 LT |
481 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
482 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
ed4cb414 | 483 | i915_user_irq_put(dev); |
1da177e4 | 484 | |
20caafa6 | 485 | if (ret == -EBUSY) { |
3e684eae | 486 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
487 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
488 | } | |
489 | ||
af6061af DA |
490 | return ret; |
491 | } | |
492 | ||
1da177e4 LT |
493 | /* Needs the lock as it touches the ring. |
494 | */ | |
c153f45f EA |
495 | int i915_irq_emit(struct drm_device *dev, void *data, |
496 | struct drm_file *file_priv) | |
1da177e4 | 497 | { |
1da177e4 | 498 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 499 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
500 | int result; |
501 | ||
07f4f8bf | 502 | if (!dev_priv || !dev_priv->ring.virtual_start) { |
3e684eae | 503 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 504 | return -EINVAL; |
1da177e4 | 505 | } |
299eb93c EA |
506 | |
507 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
508 | ||
546b0974 | 509 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 510 | result = i915_emit_irq(dev); |
546b0974 | 511 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 512 | |
c153f45f | 513 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 514 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 515 | return -EFAULT; |
1da177e4 LT |
516 | } |
517 | ||
518 | return 0; | |
519 | } | |
520 | ||
521 | /* Doesn't need the hardware lock. | |
522 | */ | |
c153f45f EA |
523 | int i915_irq_wait(struct drm_device *dev, void *data, |
524 | struct drm_file *file_priv) | |
1da177e4 | 525 | { |
1da177e4 | 526 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 527 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
528 | |
529 | if (!dev_priv) { | |
3e684eae | 530 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 531 | return -EINVAL; |
1da177e4 LT |
532 | } |
533 | ||
c153f45f | 534 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
535 | } |
536 | ||
42f52ef8 KP |
537 | /* Called from drm generic code, passed 'crtc' which |
538 | * we use as a pipe index | |
539 | */ | |
540 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
541 | { |
542 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 543 | unsigned long irqflags; |
71e0ffa5 JB |
544 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
545 | u32 pipeconf; | |
546 | ||
547 | pipeconf = I915_READ(pipeconf_reg); | |
548 | if (!(pipeconf & PIPEACONF_ENABLE)) | |
549 | return -EINVAL; | |
0a3e67a4 | 550 | |
036a4a7d ZW |
551 | if (IS_IGDNG(dev)) |
552 | return 0; | |
553 | ||
e9d21d7f | 554 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
e9d21d7f | 555 | if (IS_I965G(dev)) |
7c463586 KP |
556 | i915_enable_pipestat(dev_priv, pipe, |
557 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 558 | else |
7c463586 KP |
559 | i915_enable_pipestat(dev_priv, pipe, |
560 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 561 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
562 | return 0; |
563 | } | |
564 | ||
42f52ef8 KP |
565 | /* Called from drm generic code, passed 'crtc' which |
566 | * we use as a pipe index | |
567 | */ | |
568 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
569 | { |
570 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 571 | unsigned long irqflags; |
0a3e67a4 | 572 | |
036a4a7d ZW |
573 | if (IS_IGDNG(dev)) |
574 | return; | |
575 | ||
e9d21d7f | 576 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
7c463586 KP |
577 | i915_disable_pipestat(dev_priv, pipe, |
578 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
579 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 580 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
581 | } |
582 | ||
79e53945 JB |
583 | void i915_enable_interrupt (struct drm_device *dev) |
584 | { | |
585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e170b030 ZW |
586 | |
587 | if (!IS_IGDNG(dev)) | |
588 | opregion_enable_asle(dev); | |
79e53945 JB |
589 | dev_priv->irq_enabled = 1; |
590 | } | |
591 | ||
592 | ||
702880f2 DA |
593 | /* Set the vblank monitor pipe |
594 | */ | |
c153f45f EA |
595 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
596 | struct drm_file *file_priv) | |
702880f2 | 597 | { |
702880f2 | 598 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
599 | |
600 | if (!dev_priv) { | |
3e684eae | 601 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 602 | return -EINVAL; |
702880f2 DA |
603 | } |
604 | ||
5b51694a | 605 | return 0; |
702880f2 DA |
606 | } |
607 | ||
c153f45f EA |
608 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
609 | struct drm_file *file_priv) | |
702880f2 | 610 | { |
702880f2 | 611 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 612 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
613 | |
614 | if (!dev_priv) { | |
3e684eae | 615 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 616 | return -EINVAL; |
702880f2 DA |
617 | } |
618 | ||
0a3e67a4 | 619 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 620 | |
702880f2 DA |
621 | return 0; |
622 | } | |
623 | ||
a6b54f3f MCA |
624 | /** |
625 | * Schedule buffer swap at given vertical blank. | |
626 | */ | |
c153f45f EA |
627 | int i915_vblank_swap(struct drm_device *dev, void *data, |
628 | struct drm_file *file_priv) | |
a6b54f3f | 629 | { |
bd95e0a4 EA |
630 | /* The delayed swap mechanism was fundamentally racy, and has been |
631 | * removed. The model was that the client requested a delayed flip/swap | |
632 | * from the kernel, then waited for vblank before continuing to perform | |
633 | * rendering. The problem was that the kernel might wake the client | |
634 | * up before it dispatched the vblank swap (since the lock has to be | |
635 | * held while touching the ringbuffer), in which case the client would | |
636 | * clear and start the next frame before the swap occurred, and | |
637 | * flicker would occur in addition to likely missing the vblank. | |
638 | * | |
639 | * In the absence of this ioctl, userland falls back to a correct path | |
640 | * of waiting for a vblank, then dispatching the swap on its own. | |
641 | * Context switching to userland and back is plenty fast enough for | |
642 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 643 | */ |
bd95e0a4 | 644 | return -EINVAL; |
a6b54f3f MCA |
645 | } |
646 | ||
1da177e4 LT |
647 | /* drm_dma.h hooks |
648 | */ | |
036a4a7d ZW |
649 | static void igdng_irq_preinstall(struct drm_device *dev) |
650 | { | |
651 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
652 | ||
653 | I915_WRITE(HWSTAM, 0xeffe); | |
654 | ||
655 | /* XXX hotplug from PCH */ | |
656 | ||
657 | I915_WRITE(DEIMR, 0xffffffff); | |
658 | I915_WRITE(DEIER, 0x0); | |
659 | (void) I915_READ(DEIER); | |
660 | ||
661 | /* and GT */ | |
662 | I915_WRITE(GTIMR, 0xffffffff); | |
663 | I915_WRITE(GTIER, 0x0); | |
664 | (void) I915_READ(GTIER); | |
665 | } | |
666 | ||
667 | static int igdng_irq_postinstall(struct drm_device *dev) | |
668 | { | |
669 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
670 | /* enable kind of interrupts always enabled */ | |
671 | u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */; | |
672 | u32 render_mask = GT_USER_INTERRUPT; | |
673 | ||
674 | dev_priv->irq_mask_reg = ~display_mask; | |
675 | dev_priv->de_irq_enable_reg = display_mask; | |
676 | ||
677 | /* should always can generate irq */ | |
678 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
679 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
680 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); | |
681 | (void) I915_READ(DEIER); | |
682 | ||
683 | /* user interrupt should be enabled, but masked initial */ | |
684 | dev_priv->gt_irq_mask_reg = 0xffffffff; | |
685 | dev_priv->gt_irq_enable_reg = render_mask; | |
686 | ||
687 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
688 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
689 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); | |
690 | (void) I915_READ(GTIER); | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
84b1fd10 | 695 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
696 | { |
697 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
698 | ||
79e53945 JB |
699 | atomic_set(&dev_priv->irq_received, 0); |
700 | ||
036a4a7d ZW |
701 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
702 | ||
703 | if (IS_IGDNG(dev)) { | |
704 | igdng_irq_preinstall(dev); | |
705 | return; | |
706 | } | |
707 | ||
5ca58282 JB |
708 | if (I915_HAS_HOTPLUG(dev)) { |
709 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
710 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
711 | } | |
712 | ||
0a3e67a4 | 713 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
714 | I915_WRITE(PIPEASTAT, 0); |
715 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 716 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 717 | I915_WRITE(IER, 0x0); |
7c463586 | 718 | (void) I915_READ(IER); |
1da177e4 LT |
719 | } |
720 | ||
0a3e67a4 | 721 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
722 | { |
723 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 724 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
0a3e67a4 | 725 | |
036a4a7d ZW |
726 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
727 | ||
0a3e67a4 | 728 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 729 | |
036a4a7d ZW |
730 | if (IS_IGDNG(dev)) |
731 | return igdng_irq_postinstall(dev); | |
732 | ||
7c463586 KP |
733 | /* Unmask the interrupts that we always want on. */ |
734 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
735 | ||
736 | dev_priv->pipestat[0] = 0; | |
737 | dev_priv->pipestat[1] = 0; | |
738 | ||
5ca58282 JB |
739 | if (I915_HAS_HOTPLUG(dev)) { |
740 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
741 | ||
742 | /* Leave other bits alone */ | |
743 | hotplug_en |= HOTPLUG_EN_MASK; | |
744 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
745 | ||
746 | dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS | | |
747 | TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS | | |
748 | SDVOB_HOTPLUG_INT_STATUS; | |
749 | if (IS_G4X(dev)) { | |
750 | dev_priv->hotplug_supported_mask |= | |
751 | HDMIB_HOTPLUG_INT_STATUS | | |
752 | HDMIC_HOTPLUG_INT_STATUS | | |
753 | HDMID_HOTPLUG_INT_STATUS; | |
754 | } | |
755 | /* Enable in IER... */ | |
756 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
757 | /* and unmask in IMR */ | |
758 | i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT); | |
759 | } | |
760 | ||
7c463586 KP |
761 | /* Disable pipe interrupt enables, clear pending pipe status */ |
762 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); | |
763 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
764 | /* Clear pending interrupt status */ | |
765 | I915_WRITE(IIR, I915_READ(IIR)); | |
8ee1c3db | 766 | |
5ca58282 | 767 | I915_WRITE(IER, enable_mask); |
7c463586 | 768 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
ed4cb414 EA |
769 | (void) I915_READ(IER); |
770 | ||
8ee1c3db | 771 | opregion_enable_asle(dev); |
0a3e67a4 JB |
772 | |
773 | return 0; | |
1da177e4 LT |
774 | } |
775 | ||
036a4a7d ZW |
776 | static void igdng_irq_uninstall(struct drm_device *dev) |
777 | { | |
778 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
779 | I915_WRITE(HWSTAM, 0xffffffff); | |
780 | ||
781 | I915_WRITE(DEIMR, 0xffffffff); | |
782 | I915_WRITE(DEIER, 0x0); | |
783 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
784 | ||
785 | I915_WRITE(GTIMR, 0xffffffff); | |
786 | I915_WRITE(GTIER, 0x0); | |
787 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
788 | } | |
789 | ||
84b1fd10 | 790 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
791 | { |
792 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 793 | |
1da177e4 LT |
794 | if (!dev_priv) |
795 | return; | |
796 | ||
0a3e67a4 JB |
797 | dev_priv->vblank_pipe = 0; |
798 | ||
036a4a7d ZW |
799 | if (IS_IGDNG(dev)) { |
800 | igdng_irq_uninstall(dev); | |
801 | return; | |
802 | } | |
803 | ||
5ca58282 JB |
804 | if (I915_HAS_HOTPLUG(dev)) { |
805 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
806 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
807 | } | |
808 | ||
0a3e67a4 | 809 | I915_WRITE(HWSTAM, 0xffffffff); |
7c463586 KP |
810 | I915_WRITE(PIPEASTAT, 0); |
811 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 812 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 813 | I915_WRITE(IER, 0x0); |
af6061af | 814 | |
7c463586 KP |
815 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
816 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
817 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 818 | } |