Commit | Line | Data |
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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
1da177e4 LT |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "i915_drm.h" | |
33 | #include "i915_drv.h" | |
1c5d22f7 | 34 | #include "i915_trace.h" |
79e53945 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
1da177e4 | 37 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 38 | |
7c463586 KP |
39 | /** |
40 | * Interrupts that are always left unmasked. | |
41 | * | |
42 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
43 | * we leave them always unmasked in IMR and then control enabling them through | |
44 | * PIPESTAT alone. | |
45 | */ | |
63eeaf38 JB |
46 | #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ |
47 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
48 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
49 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
50 | |
51 | /** Interrupts that we mask and unmask at runtime. */ | |
52 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) | |
53 | ||
79e53945 JB |
54 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
55 | PIPE_VBLANK_INTERRUPT_STATUS) | |
56 | ||
57 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
58 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
59 | ||
60 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
61 | DRM_I915_VBLANK_PIPE_B) | |
62 | ||
036a4a7d ZW |
63 | void |
64 | igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) | |
65 | { | |
66 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { | |
67 | dev_priv->gt_irq_mask_reg &= ~mask; | |
68 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
69 | (void) I915_READ(GTIMR); | |
70 | } | |
71 | } | |
72 | ||
73 | static inline void | |
74 | igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) | |
75 | { | |
76 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { | |
77 | dev_priv->gt_irq_mask_reg |= mask; | |
78 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
79 | (void) I915_READ(GTIMR); | |
80 | } | |
81 | } | |
82 | ||
83 | /* For display hotplug interrupt */ | |
84 | void | |
85 | igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) | |
86 | { | |
87 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
88 | dev_priv->irq_mask_reg &= ~mask; | |
89 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
90 | (void) I915_READ(DEIMR); | |
91 | } | |
92 | } | |
93 | ||
94 | static inline void | |
95 | igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) | |
96 | { | |
97 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
98 | dev_priv->irq_mask_reg |= mask; | |
99 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
100 | (void) I915_READ(DEIMR); | |
101 | } | |
102 | } | |
103 | ||
8ee1c3db | 104 | void |
ed4cb414 EA |
105 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
106 | { | |
107 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
108 | dev_priv->irq_mask_reg &= ~mask; | |
109 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
110 | (void) I915_READ(IMR); | |
111 | } | |
112 | } | |
113 | ||
114 | static inline void | |
115 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
116 | { | |
117 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
118 | dev_priv->irq_mask_reg |= mask; | |
119 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
120 | (void) I915_READ(IMR); | |
121 | } | |
122 | } | |
123 | ||
7c463586 KP |
124 | static inline u32 |
125 | i915_pipestat(int pipe) | |
126 | { | |
127 | if (pipe == 0) | |
128 | return PIPEASTAT; | |
129 | if (pipe == 1) | |
130 | return PIPEBSTAT; | |
9c84ba4e | 131 | BUG(); |
7c463586 KP |
132 | } |
133 | ||
134 | void | |
135 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
136 | { | |
137 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
138 | u32 reg = i915_pipestat(pipe); | |
139 | ||
140 | dev_priv->pipestat[pipe] |= mask; | |
141 | /* Enable the interrupt, clear any pending status */ | |
142 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
143 | (void) I915_READ(reg); | |
144 | } | |
145 | } | |
146 | ||
147 | void | |
148 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
149 | { | |
150 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
151 | u32 reg = i915_pipestat(pipe); | |
152 | ||
153 | dev_priv->pipestat[pipe] &= ~mask; | |
154 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
155 | (void) I915_READ(reg); | |
156 | } | |
157 | } | |
158 | ||
01c66889 ZY |
159 | /** |
160 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
161 | */ | |
162 | void intel_enable_asle (struct drm_device *dev) | |
163 | { | |
164 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
165 | ||
166 | if (IS_IGDNG(dev)) | |
167 | igdng_enable_display_irq(dev_priv, DE_GSE); | |
168 | else | |
169 | i915_enable_pipestat(dev_priv, 1, | |
170 | I915_LEGACY_BLC_EVENT_ENABLE); | |
171 | } | |
172 | ||
0a3e67a4 JB |
173 | /** |
174 | * i915_pipe_enabled - check if a pipe is enabled | |
175 | * @dev: DRM device | |
176 | * @pipe: pipe to check | |
177 | * | |
178 | * Reading certain registers when the pipe is disabled can hang the chip. | |
179 | * Use this routine to make sure the PLL is running and the pipe is active | |
180 | * before reading such registers if unsure. | |
181 | */ | |
182 | static int | |
183 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
184 | { | |
185 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
186 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; | |
187 | ||
188 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) | |
189 | return 1; | |
190 | ||
191 | return 0; | |
192 | } | |
193 | ||
42f52ef8 KP |
194 | /* Called from drm generic code, passed a 'crtc', which |
195 | * we use as a pipe index | |
196 | */ | |
197 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
198 | { |
199 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
200 | unsigned long high_frame; | |
201 | unsigned long low_frame; | |
202 | u32 high1, high2, low, count; | |
0a3e67a4 | 203 | |
0a3e67a4 JB |
204 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
205 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
206 | ||
207 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
208 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
209 | "pipe %d\n", pipe); | |
0a3e67a4 JB |
210 | return 0; |
211 | } | |
212 | ||
213 | /* | |
214 | * High & low register fields aren't synchronized, so make sure | |
215 | * we get a low value that's stable across two reads of the high | |
216 | * register. | |
217 | */ | |
218 | do { | |
219 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
220 | PIPE_FRAME_HIGH_SHIFT); | |
221 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> | |
222 | PIPE_FRAME_LOW_SHIFT); | |
223 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
224 | PIPE_FRAME_HIGH_SHIFT); | |
225 | } while (high1 != high2); | |
226 | ||
227 | count = (high1 << 8) | low; | |
228 | ||
229 | return count; | |
230 | } | |
231 | ||
9880b7a5 JB |
232 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
233 | { | |
234 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
235 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | |
236 | ||
237 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
238 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
239 | "pipe %d\n", pipe); | |
9880b7a5 JB |
240 | return 0; |
241 | } | |
242 | ||
243 | return I915_READ(reg); | |
244 | } | |
245 | ||
5ca58282 JB |
246 | /* |
247 | * Handle hotplug events outside the interrupt handler proper. | |
248 | */ | |
249 | static void i915_hotplug_work_func(struct work_struct *work) | |
250 | { | |
251 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
252 | hotplug_work); | |
253 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 KP |
254 | struct drm_mode_config *mode_config = &dev->mode_config; |
255 | struct drm_connector *connector; | |
256 | ||
257 | if (mode_config->num_connector) { | |
258 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
259 | struct intel_output *intel_output = to_intel_output(connector); | |
260 | ||
261 | if (intel_output->hot_plug) | |
262 | (*intel_output->hot_plug) (intel_output); | |
263 | } | |
264 | } | |
5ca58282 JB |
265 | /* Just fire off a uevent and let userspace tell us what to do */ |
266 | drm_sysfs_hotplug_event(dev); | |
267 | } | |
268 | ||
036a4a7d ZW |
269 | irqreturn_t igdng_irq_handler(struct drm_device *dev) |
270 | { | |
271 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
272 | int ret = IRQ_NONE; | |
c650156a ZW |
273 | u32 de_iir, gt_iir, pch_iir; |
274 | u32 new_de_iir, new_gt_iir, new_pch_iir; | |
036a4a7d ZW |
275 | struct drm_i915_master_private *master_priv; |
276 | ||
277 | de_iir = I915_READ(DEIIR); | |
278 | gt_iir = I915_READ(GTIIR); | |
c650156a | 279 | pch_iir = I915_READ(SDEIIR); |
036a4a7d ZW |
280 | |
281 | for (;;) { | |
c650156a | 282 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
036a4a7d ZW |
283 | break; |
284 | ||
285 | ret = IRQ_HANDLED; | |
286 | ||
c650156a ZW |
287 | /* should clear PCH hotplug event before clear CPU irq */ |
288 | I915_WRITE(SDEIIR, pch_iir); | |
289 | new_pch_iir = I915_READ(SDEIIR); | |
290 | ||
036a4a7d ZW |
291 | I915_WRITE(DEIIR, de_iir); |
292 | new_de_iir = I915_READ(DEIIR); | |
293 | I915_WRITE(GTIIR, gt_iir); | |
294 | new_gt_iir = I915_READ(GTIIR); | |
295 | ||
296 | if (dev->primary->master) { | |
297 | master_priv = dev->primary->master->driver_priv; | |
298 | if (master_priv->sarea_priv) | |
299 | master_priv->sarea_priv->last_dispatch = | |
300 | READ_BREADCRUMB(dev_priv); | |
301 | } | |
302 | ||
303 | if (gt_iir & GT_USER_INTERRUPT) { | |
1c5d22f7 CW |
304 | u32 seqno = i915_get_gem_seqno(dev); |
305 | dev_priv->mm.irq_gem_seqno = seqno; | |
306 | trace_i915_gem_request_complete(dev, seqno); | |
036a4a7d ZW |
307 | DRM_WAKEUP(&dev_priv->irq_queue); |
308 | } | |
309 | ||
01c66889 ZY |
310 | if (de_iir & DE_GSE) |
311 | ironlake_opregion_gse_intr(dev); | |
312 | ||
c650156a ZW |
313 | /* check event from PCH */ |
314 | if ((de_iir & DE_PCH_EVENT) && | |
315 | (pch_iir & SDE_HOTPLUG_MASK)) { | |
316 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
317 | } | |
318 | ||
036a4a7d ZW |
319 | de_iir = new_de_iir; |
320 | gt_iir = new_gt_iir; | |
c650156a | 321 | pch_iir = new_pch_iir; |
036a4a7d ZW |
322 | } |
323 | ||
324 | return ret; | |
325 | } | |
326 | ||
8a905236 JB |
327 | /** |
328 | * i915_error_work_func - do process context error handling work | |
329 | * @work: work struct | |
330 | * | |
331 | * Fire an error uevent so userspace can see that a hang or error | |
332 | * was detected. | |
333 | */ | |
334 | static void i915_error_work_func(struct work_struct *work) | |
335 | { | |
336 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
337 | error_work); | |
338 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
339 | char *error_event[] = { "ERROR=1", NULL }; |
340 | char *reset_event[] = { "RESET=1", NULL }; | |
341 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 342 | |
44d98a61 | 343 | DRM_DEBUG_DRIVER("generating error event\n"); |
f316a42c BG |
344 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
345 | ||
ba1234d1 | 346 | if (atomic_read(&dev_priv->mm.wedged)) { |
f316a42c | 347 | if (IS_I965G(dev)) { |
44d98a61 | 348 | DRM_DEBUG_DRIVER("resetting chip\n"); |
f316a42c BG |
349 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); |
350 | if (!i965_reset(dev, GDRST_RENDER)) { | |
ba1234d1 | 351 | atomic_set(&dev_priv->mm.wedged, 0); |
f316a42c BG |
352 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
353 | } | |
354 | } else { | |
44d98a61 | 355 | DRM_DEBUG_DRIVER("reboot required\n"); |
f316a42c BG |
356 | } |
357 | } | |
8a905236 JB |
358 | } |
359 | ||
360 | /** | |
361 | * i915_capture_error_state - capture an error record for later analysis | |
362 | * @dev: drm device | |
363 | * | |
364 | * Should be called when an error is detected (either a hang or an error | |
365 | * interrupt) to capture error state from the time of the error. Fills | |
366 | * out a structure which becomes available in debugfs for user level tools | |
367 | * to pick up. | |
368 | */ | |
63eeaf38 JB |
369 | static void i915_capture_error_state(struct drm_device *dev) |
370 | { | |
371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
372 | struct drm_i915_error_state *error; | |
373 | unsigned long flags; | |
374 | ||
375 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
376 | if (dev_priv->first_error) | |
377 | goto out; | |
378 | ||
379 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
380 | if (!error) { | |
44d98a61 | 381 | DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n"); |
63eeaf38 JB |
382 | goto out; |
383 | } | |
384 | ||
385 | error->eir = I915_READ(EIR); | |
386 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
387 | error->pipeastat = I915_READ(PIPEASTAT); | |
388 | error->pipebstat = I915_READ(PIPEBSTAT); | |
389 | error->instpm = I915_READ(INSTPM); | |
390 | if (!IS_I965G(dev)) { | |
391 | error->ipeir = I915_READ(IPEIR); | |
392 | error->ipehr = I915_READ(IPEHR); | |
393 | error->instdone = I915_READ(INSTDONE); | |
394 | error->acthd = I915_READ(ACTHD); | |
395 | } else { | |
396 | error->ipeir = I915_READ(IPEIR_I965); | |
397 | error->ipehr = I915_READ(IPEHR_I965); | |
398 | error->instdone = I915_READ(INSTDONE_I965); | |
399 | error->instps = I915_READ(INSTPS); | |
400 | error->instdone1 = I915_READ(INSTDONE1); | |
401 | error->acthd = I915_READ(ACTHD_I965); | |
402 | } | |
403 | ||
8a905236 JB |
404 | do_gettimeofday(&error->time); |
405 | ||
63eeaf38 JB |
406 | dev_priv->first_error = error; |
407 | ||
408 | out: | |
409 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
410 | } | |
411 | ||
8a905236 JB |
412 | /** |
413 | * i915_handle_error - handle an error interrupt | |
414 | * @dev: drm device | |
415 | * | |
416 | * Do some basic checking of regsiter state at error interrupt time and | |
417 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
418 | * sure we get a record and make it available in debugfs. Fire a uevent | |
419 | * so userspace knows something bad happened (should trigger collection | |
420 | * of a ring dump etc.). | |
421 | */ | |
ba1234d1 | 422 | static void i915_handle_error(struct drm_device *dev, bool wedged) |
8a905236 JB |
423 | { |
424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425 | u32 eir = I915_READ(EIR); | |
426 | u32 pipea_stats = I915_READ(PIPEASTAT); | |
427 | u32 pipeb_stats = I915_READ(PIPEBSTAT); | |
428 | ||
429 | i915_capture_error_state(dev); | |
430 | ||
431 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
432 | eir); | |
433 | ||
434 | if (IS_G4X(dev)) { | |
435 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
436 | u32 ipeir = I915_READ(IPEIR_I965); | |
437 | ||
438 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
439 | I915_READ(IPEIR_I965)); | |
440 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
441 | I915_READ(IPEHR_I965)); | |
442 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
443 | I915_READ(INSTDONE_I965)); | |
444 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
445 | I915_READ(INSTPS)); | |
446 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
447 | I915_READ(INSTDONE1)); | |
448 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
449 | I915_READ(ACTHD_I965)); | |
450 | I915_WRITE(IPEIR_I965, ipeir); | |
451 | (void)I915_READ(IPEIR_I965); | |
452 | } | |
453 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
454 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
455 | printk(KERN_ERR "page table error\n"); | |
456 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
457 | pgtbl_err); | |
458 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
459 | (void)I915_READ(PGTBL_ER); | |
460 | } | |
461 | } | |
462 | ||
463 | if (IS_I9XX(dev)) { | |
464 | if (eir & I915_ERROR_PAGE_TABLE) { | |
465 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
466 | printk(KERN_ERR "page table error\n"); | |
467 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
468 | pgtbl_err); | |
469 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
470 | (void)I915_READ(PGTBL_ER); | |
471 | } | |
472 | } | |
473 | ||
474 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
475 | printk(KERN_ERR "memory refresh error\n"); | |
476 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", | |
477 | pipea_stats); | |
478 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", | |
479 | pipeb_stats); | |
480 | /* pipestat has already been acked */ | |
481 | } | |
482 | if (eir & I915_ERROR_INSTRUCTION) { | |
483 | printk(KERN_ERR "instruction error\n"); | |
484 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
485 | I915_READ(INSTPM)); | |
486 | if (!IS_I965G(dev)) { | |
487 | u32 ipeir = I915_READ(IPEIR); | |
488 | ||
489 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
490 | I915_READ(IPEIR)); | |
491 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
492 | I915_READ(IPEHR)); | |
493 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
494 | I915_READ(INSTDONE)); | |
495 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
496 | I915_READ(ACTHD)); | |
497 | I915_WRITE(IPEIR, ipeir); | |
498 | (void)I915_READ(IPEIR); | |
499 | } else { | |
500 | u32 ipeir = I915_READ(IPEIR_I965); | |
501 | ||
502 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
503 | I915_READ(IPEIR_I965)); | |
504 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
505 | I915_READ(IPEHR_I965)); | |
506 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
507 | I915_READ(INSTDONE_I965)); | |
508 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
509 | I915_READ(INSTPS)); | |
510 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
511 | I915_READ(INSTDONE1)); | |
512 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
513 | I915_READ(ACTHD_I965)); | |
514 | I915_WRITE(IPEIR_I965, ipeir); | |
515 | (void)I915_READ(IPEIR_I965); | |
516 | } | |
517 | } | |
518 | ||
519 | I915_WRITE(EIR, eir); | |
520 | (void)I915_READ(EIR); | |
521 | eir = I915_READ(EIR); | |
522 | if (eir) { | |
523 | /* | |
524 | * some errors might have become stuck, | |
525 | * mask them. | |
526 | */ | |
527 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
528 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
529 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
530 | } | |
531 | ||
ba1234d1 BG |
532 | if (wedged) { |
533 | atomic_set(&dev_priv->mm.wedged, 1); | |
534 | ||
11ed50ec BG |
535 | /* |
536 | * Wakeup waiting processes so they don't hang | |
537 | */ | |
538 | printk("i915: Waking up sleeping processes\n"); | |
539 | DRM_WAKEUP(&dev_priv->irq_queue); | |
540 | } | |
541 | ||
9c9fe1f8 | 542 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
543 | } |
544 | ||
1da177e4 LT |
545 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
546 | { | |
84b1fd10 | 547 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 548 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 549 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
550 | u32 iir, new_iir; |
551 | u32 pipea_stats, pipeb_stats; | |
05eff845 KP |
552 | u32 vblank_status; |
553 | u32 vblank_enable; | |
0a3e67a4 | 554 | int vblank = 0; |
7c463586 | 555 | unsigned long irqflags; |
05eff845 KP |
556 | int irq_received; |
557 | int ret = IRQ_NONE; | |
6e5fca53 | 558 | |
630681d9 EA |
559 | atomic_inc(&dev_priv->irq_received); |
560 | ||
036a4a7d ZW |
561 | if (IS_IGDNG(dev)) |
562 | return igdng_irq_handler(dev); | |
563 | ||
ed4cb414 | 564 | iir = I915_READ(IIR); |
a6b54f3f | 565 | |
05eff845 KP |
566 | if (IS_I965G(dev)) { |
567 | vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; | |
568 | vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; | |
569 | } else { | |
570 | vblank_status = I915_VBLANK_INTERRUPT_STATUS; | |
571 | vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; | |
572 | } | |
af6061af | 573 | |
05eff845 KP |
574 | for (;;) { |
575 | irq_received = iir != 0; | |
576 | ||
577 | /* Can't rely on pipestat interrupt bit in iir as it might | |
578 | * have been cleared after the pipestat interrupt was received. | |
579 | * It doesn't set the bit in iir again, but it still produces | |
580 | * interrupts (for non-MSI). | |
581 | */ | |
582 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
583 | pipea_stats = I915_READ(PIPEASTAT); | |
584 | pipeb_stats = I915_READ(PIPEBSTAT); | |
79e53945 | 585 | |
8a905236 | 586 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 587 | i915_handle_error(dev, false); |
8a905236 | 588 | |
cdfbc41f EA |
589 | /* |
590 | * Clear the PIPE(A|B)STAT regs before the IIR | |
591 | */ | |
05eff845 | 592 | if (pipea_stats & 0x8000ffff) { |
7662c8bd | 593 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 594 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
cdfbc41f | 595 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 596 | irq_received = 1; |
cdfbc41f | 597 | } |
1da177e4 | 598 | |
05eff845 | 599 | if (pipeb_stats & 0x8000ffff) { |
7662c8bd | 600 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 601 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
cdfbc41f | 602 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 603 | irq_received = 1; |
cdfbc41f | 604 | } |
05eff845 KP |
605 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
606 | ||
607 | if (!irq_received) | |
608 | break; | |
609 | ||
610 | ret = IRQ_HANDLED; | |
8ee1c3db | 611 | |
5ca58282 JB |
612 | /* Consume port. Then clear IIR or we'll miss events */ |
613 | if ((I915_HAS_HOTPLUG(dev)) && | |
614 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
615 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
616 | ||
44d98a61 | 617 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
618 | hotplug_status); |
619 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
620 | queue_work(dev_priv->wq, |
621 | &dev_priv->hotplug_work); | |
5ca58282 JB |
622 | |
623 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
624 | I915_READ(PORT_HOTPLUG_STAT); | |
04302965 SL |
625 | |
626 | /* EOS interrupts occurs */ | |
627 | if (IS_IGD(dev) && | |
628 | (hotplug_status & CRT_EOS_INT_STATUS)) { | |
629 | u32 temp; | |
630 | ||
44d98a61 | 631 | DRM_DEBUG_DRIVER("EOS interrupt occurs\n"); |
04302965 SL |
632 | /* status is already cleared */ |
633 | temp = I915_READ(ADPA); | |
634 | temp &= ~ADPA_DAC_ENABLE; | |
635 | I915_WRITE(ADPA, temp); | |
636 | ||
637 | temp = I915_READ(PORT_HOTPLUG_EN); | |
638 | temp &= ~CRT_EOS_INT_EN; | |
639 | I915_WRITE(PORT_HOTPLUG_EN, temp); | |
640 | ||
641 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
642 | if (temp & CRT_EOS_INT_STATUS) | |
643 | I915_WRITE(PORT_HOTPLUG_STAT, | |
644 | CRT_EOS_INT_STATUS); | |
645 | } | |
5ca58282 JB |
646 | } |
647 | ||
cdfbc41f EA |
648 | I915_WRITE(IIR, iir); |
649 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 650 | |
7c1c2871 DA |
651 | if (dev->primary->master) { |
652 | master_priv = dev->primary->master->driver_priv; | |
653 | if (master_priv->sarea_priv) | |
654 | master_priv->sarea_priv->last_dispatch = | |
655 | READ_BREADCRUMB(dev_priv); | |
656 | } | |
0a3e67a4 | 657 | |
cdfbc41f | 658 | if (iir & I915_USER_INTERRUPT) { |
1c5d22f7 CW |
659 | u32 seqno = i915_get_gem_seqno(dev); |
660 | dev_priv->mm.irq_gem_seqno = seqno; | |
661 | trace_i915_gem_request_complete(dev, seqno); | |
cdfbc41f | 662 | DRM_WAKEUP(&dev_priv->irq_queue); |
f65d9421 BG |
663 | dev_priv->hangcheck_count = 0; |
664 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
cdfbc41f | 665 | } |
673a394b | 666 | |
05eff845 | 667 | if (pipea_stats & vblank_status) { |
cdfbc41f EA |
668 | vblank++; |
669 | drm_handle_vblank(dev, 0); | |
670 | } | |
7c463586 | 671 | |
05eff845 | 672 | if (pipeb_stats & vblank_status) { |
cdfbc41f EA |
673 | vblank++; |
674 | drm_handle_vblank(dev, 1); | |
675 | } | |
7c463586 | 676 | |
cdfbc41f EA |
677 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || |
678 | (iir & I915_ASLE_INTERRUPT)) | |
679 | opregion_asle_intr(dev); | |
680 | ||
681 | /* With MSI, interrupts are only generated when iir | |
682 | * transitions from zero to nonzero. If another bit got | |
683 | * set while we were handling the existing iir bits, then | |
684 | * we would never get another interrupt. | |
685 | * | |
686 | * This is fine on non-MSI as well, as if we hit this path | |
687 | * we avoid exiting the interrupt handler only to generate | |
688 | * another one. | |
689 | * | |
690 | * Note that for MSI this could cause a stray interrupt report | |
691 | * if an interrupt landed in the time between writing IIR and | |
692 | * the posting read. This should be rare enough to never | |
693 | * trigger the 99% of 100,000 interrupts test for disabling | |
694 | * stray interrupts. | |
695 | */ | |
696 | iir = new_iir; | |
05eff845 | 697 | } |
0a3e67a4 | 698 | |
05eff845 | 699 | return ret; |
1da177e4 LT |
700 | } |
701 | ||
af6061af | 702 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
703 | { |
704 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 705 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
706 | RING_LOCALS; |
707 | ||
708 | i915_kernel_lost_context(dev); | |
709 | ||
44d98a61 | 710 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 711 | |
c99b058f | 712 | dev_priv->counter++; |
c29b669c | 713 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 714 | dev_priv->counter = 1; |
7c1c2871 DA |
715 | if (master_priv->sarea_priv) |
716 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 717 | |
0baf823a | 718 | BEGIN_LP_RING(4); |
585fb111 | 719 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 720 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
c29b669c | 721 | OUT_RING(dev_priv->counter); |
585fb111 | 722 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 723 | ADVANCE_LP_RING(); |
bc5f4523 | 724 | |
c29b669c | 725 | return dev_priv->counter; |
1da177e4 LT |
726 | } |
727 | ||
673a394b | 728 | void i915_user_irq_get(struct drm_device *dev) |
ed4cb414 EA |
729 | { |
730 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 731 | unsigned long irqflags; |
ed4cb414 | 732 | |
e9d21d7f | 733 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
036a4a7d ZW |
734 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { |
735 | if (IS_IGDNG(dev)) | |
736 | igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); | |
737 | else | |
738 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
739 | } | |
e9d21d7f | 740 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
741 | } |
742 | ||
0a3e67a4 | 743 | void i915_user_irq_put(struct drm_device *dev) |
ed4cb414 EA |
744 | { |
745 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 746 | unsigned long irqflags; |
ed4cb414 | 747 | |
e9d21d7f | 748 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 | 749 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
036a4a7d ZW |
750 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { |
751 | if (IS_IGDNG(dev)) | |
752 | igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); | |
753 | else | |
754 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
755 | } | |
e9d21d7f | 756 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
757 | } |
758 | ||
9d34e5db CW |
759 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
760 | { | |
761 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
762 | ||
763 | if (dev_priv->trace_irq_seqno == 0) | |
764 | i915_user_irq_get(dev); | |
765 | ||
766 | dev_priv->trace_irq_seqno = seqno; | |
767 | } | |
768 | ||
84b1fd10 | 769 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
770 | { |
771 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 772 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
773 | int ret = 0; |
774 | ||
44d98a61 | 775 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
776 | READ_BREADCRUMB(dev_priv)); |
777 | ||
ed4cb414 | 778 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
779 | if (master_priv->sarea_priv) |
780 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 781 | return 0; |
ed4cb414 | 782 | } |
1da177e4 | 783 | |
7c1c2871 DA |
784 | if (master_priv->sarea_priv) |
785 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 786 | |
ed4cb414 | 787 | i915_user_irq_get(dev); |
1da177e4 LT |
788 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
789 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
ed4cb414 | 790 | i915_user_irq_put(dev); |
1da177e4 | 791 | |
20caafa6 | 792 | if (ret == -EBUSY) { |
3e684eae | 793 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
794 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
795 | } | |
796 | ||
af6061af DA |
797 | return ret; |
798 | } | |
799 | ||
1da177e4 LT |
800 | /* Needs the lock as it touches the ring. |
801 | */ | |
c153f45f EA |
802 | int i915_irq_emit(struct drm_device *dev, void *data, |
803 | struct drm_file *file_priv) | |
1da177e4 | 804 | { |
1da177e4 | 805 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 806 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
807 | int result; |
808 | ||
07f4f8bf | 809 | if (!dev_priv || !dev_priv->ring.virtual_start) { |
3e684eae | 810 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 811 | return -EINVAL; |
1da177e4 | 812 | } |
299eb93c EA |
813 | |
814 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
815 | ||
546b0974 | 816 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 817 | result = i915_emit_irq(dev); |
546b0974 | 818 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 819 | |
c153f45f | 820 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 821 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 822 | return -EFAULT; |
1da177e4 LT |
823 | } |
824 | ||
825 | return 0; | |
826 | } | |
827 | ||
828 | /* Doesn't need the hardware lock. | |
829 | */ | |
c153f45f EA |
830 | int i915_irq_wait(struct drm_device *dev, void *data, |
831 | struct drm_file *file_priv) | |
1da177e4 | 832 | { |
1da177e4 | 833 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 834 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
835 | |
836 | if (!dev_priv) { | |
3e684eae | 837 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 838 | return -EINVAL; |
1da177e4 LT |
839 | } |
840 | ||
c153f45f | 841 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
842 | } |
843 | ||
42f52ef8 KP |
844 | /* Called from drm generic code, passed 'crtc' which |
845 | * we use as a pipe index | |
846 | */ | |
847 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
848 | { |
849 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 850 | unsigned long irqflags; |
71e0ffa5 JB |
851 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
852 | u32 pipeconf; | |
853 | ||
854 | pipeconf = I915_READ(pipeconf_reg); | |
855 | if (!(pipeconf & PIPEACONF_ENABLE)) | |
856 | return -EINVAL; | |
0a3e67a4 | 857 | |
036a4a7d ZW |
858 | if (IS_IGDNG(dev)) |
859 | return 0; | |
860 | ||
e9d21d7f | 861 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
e9d21d7f | 862 | if (IS_I965G(dev)) |
7c463586 KP |
863 | i915_enable_pipestat(dev_priv, pipe, |
864 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 865 | else |
7c463586 KP |
866 | i915_enable_pipestat(dev_priv, pipe, |
867 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 868 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
869 | return 0; |
870 | } | |
871 | ||
42f52ef8 KP |
872 | /* Called from drm generic code, passed 'crtc' which |
873 | * we use as a pipe index | |
874 | */ | |
875 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
876 | { |
877 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 878 | unsigned long irqflags; |
0a3e67a4 | 879 | |
036a4a7d ZW |
880 | if (IS_IGDNG(dev)) |
881 | return; | |
882 | ||
e9d21d7f | 883 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
7c463586 KP |
884 | i915_disable_pipestat(dev_priv, pipe, |
885 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
886 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 887 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
888 | } |
889 | ||
79e53945 JB |
890 | void i915_enable_interrupt (struct drm_device *dev) |
891 | { | |
892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e170b030 ZW |
893 | |
894 | if (!IS_IGDNG(dev)) | |
895 | opregion_enable_asle(dev); | |
79e53945 JB |
896 | dev_priv->irq_enabled = 1; |
897 | } | |
898 | ||
899 | ||
702880f2 DA |
900 | /* Set the vblank monitor pipe |
901 | */ | |
c153f45f EA |
902 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
903 | struct drm_file *file_priv) | |
702880f2 | 904 | { |
702880f2 | 905 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
906 | |
907 | if (!dev_priv) { | |
3e684eae | 908 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 909 | return -EINVAL; |
702880f2 DA |
910 | } |
911 | ||
5b51694a | 912 | return 0; |
702880f2 DA |
913 | } |
914 | ||
c153f45f EA |
915 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
916 | struct drm_file *file_priv) | |
702880f2 | 917 | { |
702880f2 | 918 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 919 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
920 | |
921 | if (!dev_priv) { | |
3e684eae | 922 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 923 | return -EINVAL; |
702880f2 DA |
924 | } |
925 | ||
0a3e67a4 | 926 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 927 | |
702880f2 DA |
928 | return 0; |
929 | } | |
930 | ||
a6b54f3f MCA |
931 | /** |
932 | * Schedule buffer swap at given vertical blank. | |
933 | */ | |
c153f45f EA |
934 | int i915_vblank_swap(struct drm_device *dev, void *data, |
935 | struct drm_file *file_priv) | |
a6b54f3f | 936 | { |
bd95e0a4 EA |
937 | /* The delayed swap mechanism was fundamentally racy, and has been |
938 | * removed. The model was that the client requested a delayed flip/swap | |
939 | * from the kernel, then waited for vblank before continuing to perform | |
940 | * rendering. The problem was that the kernel might wake the client | |
941 | * up before it dispatched the vblank swap (since the lock has to be | |
942 | * held while touching the ringbuffer), in which case the client would | |
943 | * clear and start the next frame before the swap occurred, and | |
944 | * flicker would occur in addition to likely missing the vblank. | |
945 | * | |
946 | * In the absence of this ioctl, userland falls back to a correct path | |
947 | * of waiting for a vblank, then dispatching the swap on its own. | |
948 | * Context switching to userland and back is plenty fast enough for | |
949 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 950 | */ |
bd95e0a4 | 951 | return -EINVAL; |
a6b54f3f MCA |
952 | } |
953 | ||
f65d9421 BG |
954 | struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) { |
955 | drm_i915_private_t *dev_priv = dev->dev_private; | |
956 | return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list); | |
957 | } | |
958 | ||
959 | /** | |
960 | * This is called when the chip hasn't reported back with completed | |
961 | * batchbuffers in a long time. The first time this is called we simply record | |
962 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
963 | * again, we assume the chip is wedged and try to fix it. | |
964 | */ | |
965 | void i915_hangcheck_elapsed(unsigned long data) | |
966 | { | |
967 | struct drm_device *dev = (struct drm_device *)data; | |
968 | drm_i915_private_t *dev_priv = dev->dev_private; | |
969 | uint32_t acthd; | |
970 | ||
971 | if (!IS_I965G(dev)) | |
972 | acthd = I915_READ(ACTHD); | |
973 | else | |
974 | acthd = I915_READ(ACTHD_I965); | |
975 | ||
976 | /* If all work is done then ACTHD clearly hasn't advanced. */ | |
977 | if (list_empty(&dev_priv->mm.request_list) || | |
978 | i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) { | |
979 | dev_priv->hangcheck_count = 0; | |
980 | return; | |
981 | } | |
982 | ||
983 | if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) { | |
984 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
ba1234d1 | 985 | i915_handle_error(dev, true); |
f65d9421 BG |
986 | return; |
987 | } | |
988 | ||
989 | /* Reset timer case chip hangs without another request being added */ | |
990 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
991 | ||
992 | if (acthd != dev_priv->last_acthd) | |
993 | dev_priv->hangcheck_count = 0; | |
994 | else | |
995 | dev_priv->hangcheck_count++; | |
996 | ||
997 | dev_priv->last_acthd = acthd; | |
998 | } | |
999 | ||
1da177e4 LT |
1000 | /* drm_dma.h hooks |
1001 | */ | |
036a4a7d ZW |
1002 | static void igdng_irq_preinstall(struct drm_device *dev) |
1003 | { | |
1004 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1005 | ||
1006 | I915_WRITE(HWSTAM, 0xeffe); | |
1007 | ||
1008 | /* XXX hotplug from PCH */ | |
1009 | ||
1010 | I915_WRITE(DEIMR, 0xffffffff); | |
1011 | I915_WRITE(DEIER, 0x0); | |
1012 | (void) I915_READ(DEIER); | |
1013 | ||
1014 | /* and GT */ | |
1015 | I915_WRITE(GTIMR, 0xffffffff); | |
1016 | I915_WRITE(GTIER, 0x0); | |
1017 | (void) I915_READ(GTIER); | |
c650156a ZW |
1018 | |
1019 | /* south display irq */ | |
1020 | I915_WRITE(SDEIMR, 0xffffffff); | |
1021 | I915_WRITE(SDEIER, 0x0); | |
1022 | (void) I915_READ(SDEIER); | |
036a4a7d ZW |
1023 | } |
1024 | ||
1025 | static int igdng_irq_postinstall(struct drm_device *dev) | |
1026 | { | |
1027 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1028 | /* enable kind of interrupts always enabled */ | |
c650156a | 1029 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT; |
036a4a7d | 1030 | u32 render_mask = GT_USER_INTERRUPT; |
c650156a ZW |
1031 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | |
1032 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | |
036a4a7d ZW |
1033 | |
1034 | dev_priv->irq_mask_reg = ~display_mask; | |
1035 | dev_priv->de_irq_enable_reg = display_mask; | |
1036 | ||
1037 | /* should always can generate irq */ | |
1038 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1039 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
1040 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); | |
1041 | (void) I915_READ(DEIER); | |
1042 | ||
1043 | /* user interrupt should be enabled, but masked initial */ | |
1044 | dev_priv->gt_irq_mask_reg = 0xffffffff; | |
1045 | dev_priv->gt_irq_enable_reg = render_mask; | |
1046 | ||
1047 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1048 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
1049 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); | |
1050 | (void) I915_READ(GTIER); | |
1051 | ||
c650156a ZW |
1052 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; |
1053 | dev_priv->pch_irq_enable_reg = hotplug_mask; | |
1054 | ||
1055 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1056 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg); | |
1057 | I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); | |
1058 | (void) I915_READ(SDEIER); | |
1059 | ||
036a4a7d ZW |
1060 | return 0; |
1061 | } | |
1062 | ||
84b1fd10 | 1063 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1064 | { |
1065 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1066 | ||
79e53945 JB |
1067 | atomic_set(&dev_priv->irq_received, 0); |
1068 | ||
036a4a7d | 1069 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1070 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
036a4a7d ZW |
1071 | |
1072 | if (IS_IGDNG(dev)) { | |
1073 | igdng_irq_preinstall(dev); | |
1074 | return; | |
1075 | } | |
1076 | ||
5ca58282 JB |
1077 | if (I915_HAS_HOTPLUG(dev)) { |
1078 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1079 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1080 | } | |
1081 | ||
0a3e67a4 | 1082 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
1083 | I915_WRITE(PIPEASTAT, 0); |
1084 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1085 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1086 | I915_WRITE(IER, 0x0); |
7c463586 | 1087 | (void) I915_READ(IER); |
1da177e4 LT |
1088 | } |
1089 | ||
0a3e67a4 | 1090 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
1091 | { |
1092 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 1093 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 1094 | u32 error_mask; |
0a3e67a4 | 1095 | |
036a4a7d ZW |
1096 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
1097 | ||
0a3e67a4 | 1098 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 1099 | |
036a4a7d ZW |
1100 | if (IS_IGDNG(dev)) |
1101 | return igdng_irq_postinstall(dev); | |
1102 | ||
7c463586 KP |
1103 | /* Unmask the interrupts that we always want on. */ |
1104 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
1105 | ||
1106 | dev_priv->pipestat[0] = 0; | |
1107 | dev_priv->pipestat[1] = 0; | |
1108 | ||
5ca58282 JB |
1109 | if (I915_HAS_HOTPLUG(dev)) { |
1110 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
1111 | ||
1112 | /* Leave other bits alone */ | |
1113 | hotplug_en |= HOTPLUG_EN_MASK; | |
1114 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
1115 | ||
1116 | dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS | | |
1117 | TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS | | |
1118 | SDVOB_HOTPLUG_INT_STATUS; | |
1119 | if (IS_G4X(dev)) { | |
1120 | dev_priv->hotplug_supported_mask |= | |
1121 | HDMIB_HOTPLUG_INT_STATUS | | |
1122 | HDMIC_HOTPLUG_INT_STATUS | | |
1123 | HDMID_HOTPLUG_INT_STATUS; | |
1124 | } | |
1125 | /* Enable in IER... */ | |
1126 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
1127 | /* and unmask in IMR */ | |
1128 | i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT); | |
1129 | } | |
1130 | ||
63eeaf38 JB |
1131 | /* |
1132 | * Enable some error detection, note the instruction error mask | |
1133 | * bit is reserved, so we leave it masked. | |
1134 | */ | |
1135 | if (IS_G4X(dev)) { | |
1136 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
1137 | GM45_ERROR_MEM_PRIV | | |
1138 | GM45_ERROR_CP_PRIV | | |
1139 | I915_ERROR_MEMORY_REFRESH); | |
1140 | } else { | |
1141 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
1142 | I915_ERROR_MEMORY_REFRESH); | |
1143 | } | |
1144 | I915_WRITE(EMR, error_mask); | |
1145 | ||
7c463586 KP |
1146 | /* Disable pipe interrupt enables, clear pending pipe status */ |
1147 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); | |
1148 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1149 | /* Clear pending interrupt status */ | |
1150 | I915_WRITE(IIR, I915_READ(IIR)); | |
8ee1c3db | 1151 | |
5ca58282 | 1152 | I915_WRITE(IER, enable_mask); |
7c463586 | 1153 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
ed4cb414 EA |
1154 | (void) I915_READ(IER); |
1155 | ||
8ee1c3db | 1156 | opregion_enable_asle(dev); |
0a3e67a4 JB |
1157 | |
1158 | return 0; | |
1da177e4 LT |
1159 | } |
1160 | ||
036a4a7d ZW |
1161 | static void igdng_irq_uninstall(struct drm_device *dev) |
1162 | { | |
1163 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1164 | I915_WRITE(HWSTAM, 0xffffffff); | |
1165 | ||
1166 | I915_WRITE(DEIMR, 0xffffffff); | |
1167 | I915_WRITE(DEIER, 0x0); | |
1168 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1169 | ||
1170 | I915_WRITE(GTIMR, 0xffffffff); | |
1171 | I915_WRITE(GTIER, 0x0); | |
1172 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1173 | } | |
1174 | ||
84b1fd10 | 1175 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
1176 | { |
1177 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 1178 | |
1da177e4 LT |
1179 | if (!dev_priv) |
1180 | return; | |
1181 | ||
0a3e67a4 JB |
1182 | dev_priv->vblank_pipe = 0; |
1183 | ||
036a4a7d ZW |
1184 | if (IS_IGDNG(dev)) { |
1185 | igdng_irq_uninstall(dev); | |
1186 | return; | |
1187 | } | |
1188 | ||
5ca58282 JB |
1189 | if (I915_HAS_HOTPLUG(dev)) { |
1190 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1191 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1192 | } | |
1193 | ||
0a3e67a4 | 1194 | I915_WRITE(HWSTAM, 0xffffffff); |
7c463586 KP |
1195 | I915_WRITE(PIPEASTAT, 0); |
1196 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1197 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1198 | I915_WRITE(IER, 0x0); |
af6061af | 1199 | |
7c463586 KP |
1200 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
1201 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1202 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 1203 | } |