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bac427f8 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
bac427f8 AD |
24 | #include <linux/circ_buf.h> |
25 | #include "i915_drv.h" | |
8c4f24f9 | 26 | #include "intel_uc.h" |
bac427f8 | 27 | |
44a28b1d | 28 | /** |
feda33ef | 29 | * DOC: GuC-based command submission |
44a28b1d DG |
30 | * |
31 | * i915_guc_client: | |
32 | * We use the term client to avoid confusion with contexts. A i915_guc_client is | |
33 | * equivalent to GuC object guc_context_desc. This context descriptor is | |
34 | * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell | |
35 | * and workqueue for it. Also the process descriptor (guc_process_desc), which | |
36 | * is mapped to client space. So the client can write Work Item then ring the | |
37 | * doorbell. | |
38 | * | |
39 | * To simplify the implementation, we allocate one gem object that contains all | |
40 | * pages for doorbell, process descriptor and workqueue. | |
41 | * | |
42 | * The Scratch registers: | |
43 | * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes | |
44 | * a value to the action register (SOFT_SCRATCH_0) along with any data. It then | |
45 | * triggers an interrupt on the GuC via another register write (0xC4C8). | |
46 | * Firmware writes a success/fail code back to the action register after | |
47 | * processes the request. The kernel driver polls waiting for this update and | |
48 | * then proceeds. | |
2d803c2d | 49 | * See intel_guc_send() |
44a28b1d DG |
50 | * |
51 | * Doorbells: | |
52 | * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) | |
53 | * mapped into process space. | |
54 | * | |
55 | * Work Items: | |
56 | * There are several types of work items that the host may place into a | |
57 | * workqueue, each with its own requirements and limitations. Currently only | |
58 | * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which | |
59 | * represents in-order queue. The kernel driver packs ring tail pointer and an | |
60 | * ELSP context descriptor dword into Work Item. | |
7a9347f9 | 61 | * See guc_wq_item_append() |
44a28b1d DG |
62 | * |
63 | */ | |
64 | ||
44a28b1d DG |
65 | /* |
66 | * Tell the GuC to allocate or deallocate a specific doorbell | |
67 | */ | |
68 | ||
a80bc45f AH |
69 | static int guc_allocate_doorbell(struct intel_guc *guc, |
70 | struct i915_guc_client *client) | |
44a28b1d | 71 | { |
2d803c2d AH |
72 | u32 action[] = { |
73 | INTEL_GUC_ACTION_ALLOCATE_DOORBELL, | |
74 | client->ctx_index | |
75 | }; | |
44a28b1d | 76 | |
2d803c2d | 77 | return intel_guc_send(guc, action, ARRAY_SIZE(action)); |
44a28b1d DG |
78 | } |
79 | ||
a80bc45f AH |
80 | static int guc_release_doorbell(struct intel_guc *guc, |
81 | struct i915_guc_client *client) | |
44a28b1d | 82 | { |
2d803c2d AH |
83 | u32 action[] = { |
84 | INTEL_GUC_ACTION_DEALLOCATE_DOORBELL, | |
85 | client->ctx_index | |
86 | }; | |
685534ef | 87 | |
2d803c2d | 88 | return intel_guc_send(guc, action, ARRAY_SIZE(action)); |
685534ef SAK |
89 | } |
90 | ||
44a28b1d DG |
91 | /* |
92 | * Initialise, update, or clear doorbell data shared with the GuC | |
93 | * | |
94 | * These functions modify shared data and so need access to the mapped | |
95 | * client object which contains the page being used for the doorbell | |
96 | */ | |
97 | ||
a667429b DG |
98 | static int guc_update_doorbell_id(struct intel_guc *guc, |
99 | struct i915_guc_client *client, | |
100 | u16 new_id) | |
44a28b1d | 101 | { |
8b797af1 | 102 | struct sg_table *sg = guc->ctx_pool_vma->pages; |
a667429b | 103 | void *doorbell_bitmap = guc->doorbell_bitmap; |
44a28b1d | 104 | struct guc_doorbell_info *doorbell; |
a667429b DG |
105 | struct guc_context_desc desc; |
106 | size_t len; | |
44a28b1d | 107 | |
72aa0d89 | 108 | doorbell = client->vaddr + client->doorbell_offset; |
44a28b1d | 109 | |
a667429b DG |
110 | if (client->doorbell_id != GUC_INVALID_DOORBELL_ID && |
111 | test_bit(client->doorbell_id, doorbell_bitmap)) { | |
112 | /* Deactivate the old doorbell */ | |
113 | doorbell->db_status = GUC_DOORBELL_DISABLED; | |
a80bc45f | 114 | (void)guc_release_doorbell(guc, client); |
a667429b DG |
115 | __clear_bit(client->doorbell_id, doorbell_bitmap); |
116 | } | |
117 | ||
118 | /* Update the GuC's idea of the doorbell ID */ | |
119 | len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
120 | sizeof(desc) * client->ctx_index); | |
121 | if (len != sizeof(desc)) | |
122 | return -EFAULT; | |
123 | desc.db_id = new_id; | |
124 | len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
125 | sizeof(desc) * client->ctx_index); | |
126 | if (len != sizeof(desc)) | |
127 | return -EFAULT; | |
128 | ||
129 | client->doorbell_id = new_id; | |
130 | if (new_id == GUC_INVALID_DOORBELL_ID) | |
131 | return 0; | |
132 | ||
133 | /* Activate the new doorbell */ | |
134 | __set_bit(new_id, doorbell_bitmap); | |
a667429b | 135 | doorbell->db_status = GUC_DOORBELL_ENABLED; |
597bdc8b | 136 | doorbell->cookie = client->doorbell_cookie; |
a80bc45f | 137 | return guc_allocate_doorbell(guc, client); |
a667429b DG |
138 | } |
139 | ||
44a28b1d DG |
140 | static void guc_disable_doorbell(struct intel_guc *guc, |
141 | struct i915_guc_client *client) | |
142 | { | |
a667429b | 143 | (void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID); |
44a28b1d | 144 | |
44a28b1d DG |
145 | /* XXX: wait for any interrupts */ |
146 | /* XXX: wait for workqueue to drain */ | |
147 | } | |
148 | ||
f10d69a7 DG |
149 | static uint16_t |
150 | select_doorbell_register(struct intel_guc *guc, uint32_t priority) | |
151 | { | |
152 | /* | |
153 | * The bitmap tracks which doorbell registers are currently in use. | |
154 | * It is split into two halves; the first half is used for normal | |
155 | * priority contexts, the second half for high-priority ones. | |
156 | * Note that logically higher priorities are numerically less than | |
157 | * normal ones, so the test below means "is it high-priority?" | |
158 | */ | |
159 | const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH); | |
160 | const uint16_t half = GUC_MAX_DOORBELLS / 2; | |
161 | const uint16_t start = hi_pri ? half : 0; | |
162 | const uint16_t end = start + half; | |
163 | uint16_t id; | |
164 | ||
165 | id = find_next_zero_bit(guc->doorbell_bitmap, end, start); | |
166 | if (id == end) | |
167 | id = GUC_INVALID_DOORBELL_ID; | |
168 | ||
169 | DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n", | |
170 | hi_pri ? "high" : "normal", id); | |
171 | ||
172 | return id; | |
173 | } | |
174 | ||
44a28b1d DG |
175 | /* |
176 | * Select, assign and relase doorbell cachelines | |
177 | * | |
178 | * These functions track which doorbell cachelines are in use. | |
2d803c2d | 179 | * The data they manipulate is protected by the intel_guc_send lock. |
44a28b1d DG |
180 | */ |
181 | ||
182 | static uint32_t select_doorbell_cacheline(struct intel_guc *guc) | |
183 | { | |
184 | const uint32_t cacheline_size = cache_line_size(); | |
185 | uint32_t offset; | |
186 | ||
44a28b1d DG |
187 | /* Doorbell uses a single cache line within a page */ |
188 | offset = offset_in_page(guc->db_cacheline); | |
189 | ||
190 | /* Moving to next cache line to reduce contention */ | |
191 | guc->db_cacheline += cacheline_size; | |
192 | ||
44a28b1d DG |
193 | DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n", |
194 | offset, guc->db_cacheline, cacheline_size); | |
195 | ||
196 | return offset; | |
197 | } | |
198 | ||
44a28b1d DG |
199 | /* |
200 | * Initialise the process descriptor shared with the GuC firmware. | |
201 | */ | |
7a9347f9 | 202 | static void guc_proc_desc_init(struct intel_guc *guc, |
44a28b1d DG |
203 | struct i915_guc_client *client) |
204 | { | |
205 | struct guc_process_desc *desc; | |
44a28b1d | 206 | |
72aa0d89 | 207 | desc = client->vaddr + client->proc_desc_offset; |
44a28b1d DG |
208 | |
209 | memset(desc, 0, sizeof(*desc)); | |
210 | ||
211 | /* | |
212 | * XXX: pDoorbell and WQVBaseAddress are pointers in process address | |
213 | * space for ring3 clients (set them as in mmap_ioctl) or kernel | |
214 | * space for kernel clients (map on demand instead? May make debug | |
215 | * easier to have it mapped). | |
216 | */ | |
217 | desc->wq_base_addr = 0; | |
218 | desc->db_base_addr = 0; | |
219 | ||
220 | desc->context_id = client->ctx_index; | |
221 | desc->wq_size_bytes = client->wq_size; | |
222 | desc->wq_status = WQ_STATUS_ACTIVE; | |
223 | desc->priority = client->priority; | |
44a28b1d DG |
224 | } |
225 | ||
226 | /* | |
227 | * Initialise/clear the context descriptor shared with the GuC firmware. | |
228 | * | |
229 | * This descriptor tells the GuC where (in GGTT space) to find the important | |
230 | * data structures relating to this client (doorbell, process descriptor, | |
231 | * write queue, etc). | |
232 | */ | |
233 | ||
7a9347f9 | 234 | static void guc_ctx_desc_init(struct intel_guc *guc, |
44a28b1d DG |
235 | struct i915_guc_client *client) |
236 | { | |
397097b0 | 237 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
e2f80391 | 238 | struct intel_engine_cs *engine; |
e2efd130 | 239 | struct i915_gem_context *ctx = client->owner; |
44a28b1d DG |
240 | struct guc_context_desc desc; |
241 | struct sg_table *sg; | |
bafb0fce | 242 | unsigned int tmp; |
86e06cc0 | 243 | u32 gfx_addr; |
44a28b1d DG |
244 | |
245 | memset(&desc, 0, sizeof(desc)); | |
246 | ||
247 | desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL; | |
248 | desc.context_id = client->ctx_index; | |
249 | desc.priority = client->priority; | |
44a28b1d DG |
250 | desc.db_id = client->doorbell_id; |
251 | ||
bafb0fce | 252 | for_each_engine_masked(engine, dev_priv, client->engines, tmp) { |
9021ad03 | 253 | struct intel_context *ce = &ctx->engine[engine->id]; |
c18468c4 DG |
254 | uint32_t guc_engine_id = engine->guc_id; |
255 | struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id]; | |
d1675198 AD |
256 | |
257 | /* TODO: We have a design issue to be solved here. Only when we | |
258 | * receive the first batch, we know which engine is used by the | |
259 | * user. But here GuC expects the lrc and ring to be pinned. It | |
260 | * is not an issue for default context, which is the only one | |
261 | * for now who owns a GuC client. But for future owner of GuC | |
262 | * client, need to make sure lrc is pinned prior to enter here. | |
263 | */ | |
9021ad03 | 264 | if (!ce->state) |
d1675198 AD |
265 | break; /* XXX: continue? */ |
266 | ||
9021ad03 | 267 | lrc->context_desc = lower_32_bits(ce->lrc_desc); |
d1675198 AD |
268 | |
269 | /* The state page is after PPHWSP */ | |
57e88531 | 270 | lrc->ring_lcra = |
4741da92 | 271 | guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE; |
d1675198 | 272 | lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | |
c18468c4 | 273 | (guc_engine_id << GUC_ELC_ENGINE_OFFSET); |
d1675198 | 274 | |
4741da92 | 275 | lrc->ring_begin = guc_ggtt_offset(ce->ring->vma); |
57e88531 CW |
276 | lrc->ring_end = lrc->ring_begin + ce->ring->size - 1; |
277 | lrc->ring_next_free_location = lrc->ring_begin; | |
d1675198 AD |
278 | lrc->ring_current_tail_pointer_value = 0; |
279 | ||
c18468c4 | 280 | desc.engines_used |= (1 << guc_engine_id); |
d1675198 AD |
281 | } |
282 | ||
e02757d9 DG |
283 | DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n", |
284 | client->engines, desc.engines_used); | |
d1675198 AD |
285 | WARN_ON(desc.engines_used == 0); |
286 | ||
44a28b1d | 287 | /* |
86e06cc0 DG |
288 | * The doorbell, process descriptor, and workqueue are all parts |
289 | * of the client object, which the GuC will reference via the GGTT | |
44a28b1d | 290 | */ |
4741da92 | 291 | gfx_addr = guc_ggtt_offset(client->vma); |
8b797af1 | 292 | desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) + |
86e06cc0 | 293 | client->doorbell_offset; |
72aa0d89 CW |
294 | desc.db_trigger_cpu = |
295 | (uintptr_t)client->vaddr + client->doorbell_offset; | |
86e06cc0 DG |
296 | desc.db_trigger_uk = gfx_addr + client->doorbell_offset; |
297 | desc.process_desc = gfx_addr + client->proc_desc_offset; | |
298 | desc.wq_addr = gfx_addr + client->wq_offset; | |
44a28b1d DG |
299 | desc.wq_size = client->wq_size; |
300 | ||
301 | /* | |
e2efd130 | 302 | * XXX: Take LRCs from an existing context if this is not an |
44a28b1d DG |
303 | * IsKMDCreatedContext client |
304 | */ | |
305 | desc.desc_private = (uintptr_t)client; | |
306 | ||
307 | /* Pool context is pinned already */ | |
8b797af1 | 308 | sg = guc->ctx_pool_vma->pages; |
44a28b1d DG |
309 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
310 | sizeof(desc) * client->ctx_index); | |
311 | } | |
312 | ||
7a9347f9 | 313 | static void guc_ctx_desc_fini(struct intel_guc *guc, |
44a28b1d DG |
314 | struct i915_guc_client *client) |
315 | { | |
316 | struct guc_context_desc desc; | |
317 | struct sg_table *sg; | |
318 | ||
319 | memset(&desc, 0, sizeof(desc)); | |
320 | ||
8b797af1 | 321 | sg = guc->ctx_pool_vma->pages; |
44a28b1d DG |
322 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), |
323 | sizeof(desc) * client->ctx_index); | |
324 | } | |
325 | ||
7c2c270d | 326 | /** |
7a9347f9 | 327 | * i915_guc_wq_reserve() - reserve space in the GuC's workqueue |
7c2c270d DG |
328 | * @request: request associated with the commands |
329 | * | |
330 | * Return: 0 if space is available | |
331 | * -EAGAIN if space is not currently available | |
332 | * | |
333 | * This function must be called (and must return 0) before a request | |
334 | * is submitted to the GuC via i915_guc_submit() below. Once a result | |
7a9347f9 DG |
335 | * of 0 has been returned, it must be balanced by a corresponding |
336 | * call to submit(). | |
7c2c270d | 337 | * |
7a9347f9 | 338 | * Reservation allows the caller to determine in advance that space |
7c2c270d DG |
339 | * will be available for the next submission before committing resources |
340 | * to it, and helps avoid late failures with complicated recovery paths. | |
341 | */ | |
7a9347f9 | 342 | int i915_guc_wq_reserve(struct drm_i915_gem_request *request) |
44a28b1d | 343 | { |
551aaecd | 344 | const size_t wqi_size = sizeof(struct guc_wq_item); |
776594d5 MW |
345 | struct i915_guc_client *client = request->i915->guc.execbuf_client; |
346 | struct guc_process_desc *desc = client->vaddr + | |
347 | client->proc_desc_offset; | |
551aaecd | 348 | u32 freespace; |
dadd481b | 349 | int ret; |
44a28b1d | 350 | |
776594d5 MW |
351 | spin_lock(&client->wq_lock); |
352 | freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size); | |
353 | freespace -= client->wq_rsvd; | |
dadd481b | 354 | if (likely(freespace >= wqi_size)) { |
776594d5 | 355 | client->wq_rsvd += wqi_size; |
dadd481b CW |
356 | ret = 0; |
357 | } else { | |
776594d5 | 358 | client->no_wq_space++; |
dadd481b CW |
359 | ret = -EAGAIN; |
360 | } | |
776594d5 | 361 | spin_unlock(&client->wq_lock); |
44a28b1d | 362 | |
dadd481b | 363 | return ret; |
44a28b1d DG |
364 | } |
365 | ||
5ba89908 CW |
366 | void i915_guc_wq_unreserve(struct drm_i915_gem_request *request) |
367 | { | |
368 | const size_t wqi_size = sizeof(struct guc_wq_item); | |
776594d5 | 369 | struct i915_guc_client *client = request->i915->guc.execbuf_client; |
5ba89908 | 370 | |
776594d5 | 371 | GEM_BUG_ON(READ_ONCE(client->wq_rsvd) < wqi_size); |
5ba89908 | 372 | |
776594d5 MW |
373 | spin_lock(&client->wq_lock); |
374 | client->wq_rsvd -= wqi_size; | |
375 | spin_unlock(&client->wq_lock); | |
5ba89908 CW |
376 | } |
377 | ||
7a9347f9 | 378 | /* Construct a Work Item and append it to the GuC's Work Queue */ |
776594d5 | 379 | static void guc_wq_item_append(struct i915_guc_client *client, |
7a9347f9 | 380 | struct drm_i915_gem_request *rq) |
44a28b1d | 381 | { |
0a31afbc DG |
382 | /* wqi_len is in DWords, and does not include the one-word header */ |
383 | const size_t wqi_size = sizeof(struct guc_wq_item); | |
384 | const u32 wqi_len = wqi_size/sizeof(u32) - 1; | |
c18468c4 | 385 | struct intel_engine_cs *engine = rq->engine; |
a5916e8f | 386 | struct guc_process_desc *desc; |
44a28b1d | 387 | struct guc_wq_item *wqi; |
72aa0d89 | 388 | u32 freespace, tail, wq_off; |
a7e02199 | 389 | |
776594d5 | 390 | desc = client->vaddr + client->proc_desc_offset; |
44a28b1d | 391 | |
7a9347f9 | 392 | /* Free space is guaranteed, see i915_guc_wq_reserve() above */ |
776594d5 | 393 | freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size); |
0a31afbc DG |
394 | GEM_BUG_ON(freespace < wqi_size); |
395 | ||
396 | /* The GuC firmware wants the tail index in QWords, not bytes */ | |
397 | tail = rq->tail; | |
398 | GEM_BUG_ON(tail & 7); | |
399 | tail >>= 3; | |
400 | GEM_BUG_ON(tail > WQ_RING_TAIL_MAX); | |
44a28b1d DG |
401 | |
402 | /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we | |
403 | * should not have the case where structure wqi is across page, neither | |
404 | * wrapped to the beginning. This simplifies the implementation below. | |
405 | * | |
406 | * XXX: if not the case, we need save data to a temp wqi and copy it to | |
407 | * workqueue buffer dw by dw. | |
408 | */ | |
0a31afbc | 409 | BUILD_BUG_ON(wqi_size != 16); |
776594d5 | 410 | GEM_BUG_ON(client->wq_rsvd < wqi_size); |
44a28b1d | 411 | |
0a31afbc | 412 | /* postincrement WQ tail for next time */ |
776594d5 | 413 | wq_off = client->wq_tail; |
dadd481b | 414 | GEM_BUG_ON(wq_off & (wqi_size - 1)); |
776594d5 MW |
415 | client->wq_tail += wqi_size; |
416 | client->wq_tail &= client->wq_size - 1; | |
417 | client->wq_rsvd -= wqi_size; | |
0a31afbc DG |
418 | |
419 | /* WQ starts from the page after doorbell / process_desc */ | |
776594d5 | 420 | wqi = client->vaddr + wq_off + GUC_DB_SIZE; |
44a28b1d | 421 | |
0a31afbc | 422 | /* Now fill in the 4-word work queue item */ |
44a28b1d | 423 | wqi->header = WQ_TYPE_INORDER | |
0a31afbc | 424 | (wqi_len << WQ_LEN_SHIFT) | |
c18468c4 | 425 | (engine->guc_id << WQ_TARGET_SHIFT) | |
44a28b1d DG |
426 | WQ_NO_WCFLUSH_WAIT; |
427 | ||
428 | /* The GuC wants only the low-order word of the context descriptor */ | |
c18468c4 | 429 | wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine); |
44a28b1d | 430 | |
44a28b1d | 431 | wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT; |
65e4760e | 432 | wqi->fence_id = rq->global_seqno; |
44a28b1d DG |
433 | } |
434 | ||
776594d5 | 435 | static int guc_ring_doorbell(struct i915_guc_client *client) |
10d2c3e2 DG |
436 | { |
437 | struct guc_process_desc *desc; | |
438 | union guc_doorbell_qw db_cmp, db_exc, db_ret; | |
439 | union guc_doorbell_qw *db; | |
440 | int attempt = 2, ret = -EAGAIN; | |
441 | ||
776594d5 | 442 | desc = client->vaddr + client->proc_desc_offset; |
10d2c3e2 DG |
443 | |
444 | /* Update the tail so it is visible to GuC */ | |
776594d5 | 445 | desc->tail = client->wq_tail; |
10d2c3e2 DG |
446 | |
447 | /* current cookie */ | |
448 | db_cmp.db_status = GUC_DOORBELL_ENABLED; | |
776594d5 | 449 | db_cmp.cookie = client->doorbell_cookie; |
10d2c3e2 DG |
450 | |
451 | /* cookie to be updated */ | |
452 | db_exc.db_status = GUC_DOORBELL_ENABLED; | |
776594d5 | 453 | db_exc.cookie = client->doorbell_cookie + 1; |
10d2c3e2 DG |
454 | if (db_exc.cookie == 0) |
455 | db_exc.cookie = 1; | |
456 | ||
457 | /* pointer of current doorbell cacheline */ | |
776594d5 | 458 | db = client->vaddr + client->doorbell_offset; |
10d2c3e2 DG |
459 | |
460 | while (attempt--) { | |
461 | /* lets ring the doorbell */ | |
462 | db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, | |
463 | db_cmp.value_qw, db_exc.value_qw); | |
464 | ||
465 | /* if the exchange was successfully executed */ | |
466 | if (db_ret.value_qw == db_cmp.value_qw) { | |
467 | /* db was successfully rung */ | |
776594d5 | 468 | client->doorbell_cookie = db_exc.cookie; |
10d2c3e2 DG |
469 | ret = 0; |
470 | break; | |
471 | } | |
472 | ||
473 | /* XXX: doorbell was lost and need to acquire it again */ | |
474 | if (db_ret.db_status == GUC_DOORBELL_DISABLED) | |
475 | break; | |
476 | ||
535b2f5e DG |
477 | DRM_WARN("Cookie mismatch. Expected %d, found %d\n", |
478 | db_cmp.cookie, db_ret.cookie); | |
10d2c3e2 DG |
479 | |
480 | /* update the cookie to newly read cookie from GuC */ | |
481 | db_cmp.cookie = db_ret.cookie; | |
482 | db_exc.cookie = db_ret.cookie + 1; | |
483 | if (db_exc.cookie == 0) | |
484 | db_exc.cookie = 1; | |
485 | } | |
486 | ||
487 | return ret; | |
488 | } | |
489 | ||
44a28b1d | 490 | /** |
34ba5a80 | 491 | * __i915_guc_submit() - Submit commands through GuC |
feda33ef | 492 | * @rq: request associated with the commands |
44a28b1d | 493 | * |
7a9347f9 DG |
494 | * The caller must have already called i915_guc_wq_reserve() above with |
495 | * a result of 0 (success), guaranteeing that there is space in the work | |
496 | * queue for the new request, so enqueuing the item cannot fail. | |
7c2c270d DG |
497 | * |
498 | * Bad Things Will Happen if the caller violates this protocol e.g. calls | |
7a9347f9 DG |
499 | * submit() when _reserve() says there's no space, or calls _submit() |
500 | * a different number of times from (successful) calls to _reserve(). | |
7c2c270d DG |
501 | * |
502 | * The only error here arises if the doorbell hardware isn't functioning | |
503 | * as expected, which really shouln't happen. | |
44a28b1d | 504 | */ |
34ba5a80 | 505 | static void __i915_guc_submit(struct drm_i915_gem_request *rq) |
44a28b1d | 506 | { |
ed4596ea | 507 | struct drm_i915_private *dev_priv = rq->i915; |
d55ac5bf CW |
508 | struct intel_engine_cs *engine = rq->engine; |
509 | unsigned int engine_id = engine->id; | |
7c2c270d DG |
510 | struct intel_guc *guc = &rq->i915->guc; |
511 | struct i915_guc_client *client = guc->execbuf_client; | |
0a31afbc | 512 | int b_ret; |
44a28b1d | 513 | |
dadd481b | 514 | spin_lock(&client->wq_lock); |
7a9347f9 | 515 | guc_wq_item_append(client, rq); |
ed4596ea AG |
516 | |
517 | /* WA to flush out the pending GMADR writes to ring buffer. */ | |
518 | if (i915_vma_is_map_and_fenceable(rq->ring->vma)) | |
519 | POSTING_READ_FW(GUC_STATUS); | |
520 | ||
0a31afbc | 521 | b_ret = guc_ring_doorbell(client); |
44a28b1d | 522 | |
397097b0 | 523 | client->submissions[engine_id] += 1; |
0a31afbc DG |
524 | client->retcode = b_ret; |
525 | if (b_ret) | |
44a28b1d | 526 | client->b_fail += 1; |
0a31afbc | 527 | |
397097b0 | 528 | guc->submissions[engine_id] += 1; |
65e4760e | 529 | guc->last_seqno[engine_id] = rq->global_seqno; |
dadd481b | 530 | spin_unlock(&client->wq_lock); |
44a28b1d DG |
531 | } |
532 | ||
34ba5a80 CW |
533 | static void i915_guc_submit(struct drm_i915_gem_request *rq) |
534 | { | |
34ba5a80 CW |
535 | i915_gem_request_submit(rq); |
536 | __i915_guc_submit(rq); | |
537 | } | |
538 | ||
44a28b1d DG |
539 | /* |
540 | * Everything below here is concerned with setup & teardown, and is | |
541 | * therefore not part of the somewhat time-critical batch-submission | |
542 | * path of i915_guc_submit() above. | |
543 | */ | |
544 | ||
bac427f8 | 545 | /** |
f9cda048 | 546 | * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage |
8b797af1 CW |
547 | * @guc: the guc |
548 | * @size: size of area to allocate (both virtual space and memory) | |
bac427f8 | 549 | * |
8b797af1 CW |
550 | * This is a wrapper to create an object for use with the GuC. In order to |
551 | * use it inside the GuC, an object needs to be pinned lifetime, so we allocate | |
552 | * both some backing storage and a range inside the Global GTT. We must pin | |
553 | * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that | |
554 | * range is reserved inside GuC. | |
bac427f8 | 555 | * |
8b797af1 | 556 | * Return: A i915_vma if successful, otherwise an ERR_PTR. |
bac427f8 | 557 | */ |
f9cda048 | 558 | struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) |
bac427f8 | 559 | { |
8b797af1 | 560 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
bac427f8 | 561 | struct drm_i915_gem_object *obj; |
8b797af1 CW |
562 | struct i915_vma *vma; |
563 | int ret; | |
bac427f8 | 564 | |
12d79d78 | 565 | obj = i915_gem_object_create(dev_priv, size); |
fe3db79b | 566 | if (IS_ERR(obj)) |
8b797af1 | 567 | return ERR_CAST(obj); |
bac427f8 | 568 | |
a01cb37a | 569 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
8b797af1 CW |
570 | if (IS_ERR(vma)) |
571 | goto err; | |
bac427f8 | 572 | |
8b797af1 CW |
573 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, |
574 | PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); | |
575 | if (ret) { | |
576 | vma = ERR_PTR(ret); | |
577 | goto err; | |
bac427f8 AD |
578 | } |
579 | ||
8b797af1 CW |
580 | return vma; |
581 | ||
582 | err: | |
583 | i915_gem_object_put(obj); | |
584 | return vma; | |
bac427f8 AD |
585 | } |
586 | ||
0daf556c DG |
587 | static void |
588 | guc_client_free(struct drm_i915_private *dev_priv, | |
589 | struct i915_guc_client *client) | |
44a28b1d | 590 | { |
44a28b1d DG |
591 | struct intel_guc *guc = &dev_priv->guc; |
592 | ||
593 | if (!client) | |
594 | return; | |
595 | ||
44a28b1d DG |
596 | /* |
597 | * XXX: wait for any outstanding submissions before freeing memory. | |
598 | * Be sure to drop any locks | |
599 | */ | |
600 | ||
72aa0d89 | 601 | if (client->vaddr) { |
0d92a6a4 | 602 | /* |
a667429b DG |
603 | * If we got as far as setting up a doorbell, make sure we |
604 | * shut it down before unmapping & deallocating the memory. | |
0d92a6a4 | 605 | */ |
a667429b | 606 | guc_disable_doorbell(guc, client); |
0d92a6a4 | 607 | |
72aa0d89 | 608 | i915_gem_object_unpin_map(client->vma->obj); |
0d92a6a4 DG |
609 | } |
610 | ||
19880c4a | 611 | i915_vma_unpin_and_release(&client->vma); |
44a28b1d DG |
612 | |
613 | if (client->ctx_index != GUC_INVALID_CTX_ID) { | |
7a9347f9 | 614 | guc_ctx_desc_fini(guc, client); |
44a28b1d DG |
615 | ida_simple_remove(&guc->ctx_ids, client->ctx_index); |
616 | } | |
617 | ||
618 | kfree(client); | |
619 | } | |
620 | ||
84b7f882 DG |
621 | /* Check that a doorbell register is in the expected state */ |
622 | static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id) | |
623 | { | |
624 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
625 | i915_reg_t drbreg = GEN8_DRBREGL(db_id); | |
626 | uint32_t value = I915_READ(drbreg); | |
627 | bool enabled = (value & GUC_DOORBELL_ENABLED) != 0; | |
628 | bool expected = test_bit(db_id, guc->doorbell_bitmap); | |
629 | ||
630 | if (enabled == expected) | |
631 | return true; | |
632 | ||
633 | DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n", | |
634 | db_id, drbreg.reg, value, | |
635 | expected ? "active" : "inactive"); | |
636 | ||
637 | return false; | |
638 | } | |
639 | ||
4d75787b | 640 | /* |
8888cd01 | 641 | * Borrow the first client to set up & tear down each unused doorbell |
4d75787b DG |
642 | * in turn, to ensure that all doorbell h/w is (re)initialised. |
643 | */ | |
644 | static void guc_init_doorbell_hw(struct intel_guc *guc) | |
645 | { | |
4d75787b | 646 | struct i915_guc_client *client = guc->execbuf_client; |
84b7f882 DG |
647 | uint16_t db_id; |
648 | int i, err; | |
4d75787b | 649 | |
4d357af4 | 650 | guc_disable_doorbell(guc, client); |
4d75787b DG |
651 | |
652 | for (i = 0; i < GUC_MAX_DOORBELLS; ++i) { | |
84b7f882 DG |
653 | /* Skip if doorbell is OK */ |
654 | if (guc_doorbell_check(guc, i)) | |
8888cd01 DG |
655 | continue; |
656 | ||
4d75787b | 657 | err = guc_update_doorbell_id(guc, client, i); |
84b7f882 DG |
658 | if (err) |
659 | DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n", | |
660 | i, err); | |
4d75787b DG |
661 | } |
662 | ||
4d357af4 CW |
663 | db_id = select_doorbell_register(guc, client->priority); |
664 | WARN_ON(db_id == GUC_INVALID_DOORBELL_ID); | |
665 | ||
4d75787b DG |
666 | err = guc_update_doorbell_id(guc, client, db_id); |
667 | if (err) | |
535b2f5e DG |
668 | DRM_WARN("Failed to restore doorbell to %d, err %d\n", |
669 | db_id, err); | |
4d75787b | 670 | |
84b7f882 DG |
671 | /* Read back & verify all doorbell registers */ |
672 | for (i = 0; i < GUC_MAX_DOORBELLS; ++i) | |
673 | (void)guc_doorbell_check(guc, i); | |
4d75787b DG |
674 | } |
675 | ||
44a28b1d DG |
676 | /** |
677 | * guc_client_alloc() - Allocate an i915_guc_client | |
0daf556c | 678 | * @dev_priv: driver private data structure |
ceae5317 | 679 | * @engines: The set of engines to enable for this client |
44a28b1d DG |
680 | * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW |
681 | * The kernel client to replace ExecList submission is created with | |
682 | * NORMAL priority. Priority of a client for scheduler can be HIGH, | |
683 | * while a preemption context can use CRITICAL. | |
feda33ef AD |
684 | * @ctx: the context that owns the client (we use the default render |
685 | * context) | |
44a28b1d | 686 | * |
0d92a6a4 | 687 | * Return: An i915_guc_client object if success, else NULL. |
44a28b1d | 688 | */ |
0daf556c DG |
689 | static struct i915_guc_client * |
690 | guc_client_alloc(struct drm_i915_private *dev_priv, | |
e02757d9 | 691 | uint32_t engines, |
0daf556c DG |
692 | uint32_t priority, |
693 | struct i915_gem_context *ctx) | |
44a28b1d DG |
694 | { |
695 | struct i915_guc_client *client; | |
44a28b1d | 696 | struct intel_guc *guc = &dev_priv->guc; |
8b797af1 | 697 | struct i915_vma *vma; |
72aa0d89 | 698 | void *vaddr; |
a667429b | 699 | uint16_t db_id; |
44a28b1d DG |
700 | |
701 | client = kzalloc(sizeof(*client), GFP_KERNEL); | |
702 | if (!client) | |
703 | return NULL; | |
704 | ||
d1675198 | 705 | client->owner = ctx; |
44a28b1d | 706 | client->guc = guc; |
e02757d9 DG |
707 | client->engines = engines; |
708 | client->priority = priority; | |
709 | client->doorbell_id = GUC_INVALID_DOORBELL_ID; | |
44a28b1d DG |
710 | |
711 | client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0, | |
712 | GUC_MAX_GPU_CONTEXTS, GFP_KERNEL); | |
713 | if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) { | |
714 | client->ctx_index = GUC_INVALID_CTX_ID; | |
715 | goto err; | |
716 | } | |
717 | ||
718 | /* The first page is doorbell/proc_desc. Two followed pages are wq. */ | |
f9cda048 | 719 | vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE); |
8b797af1 | 720 | if (IS_ERR(vma)) |
44a28b1d DG |
721 | goto err; |
722 | ||
0d92a6a4 | 723 | /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */ |
8b797af1 | 724 | client->vma = vma; |
72aa0d89 CW |
725 | |
726 | vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); | |
727 | if (IS_ERR(vaddr)) | |
728 | goto err; | |
729 | ||
730 | client->vaddr = vaddr; | |
dadd481b CW |
731 | |
732 | spin_lock_init(&client->wq_lock); | |
44a28b1d DG |
733 | client->wq_offset = GUC_DB_SIZE; |
734 | client->wq_size = GUC_WQ_SIZE; | |
44a28b1d | 735 | |
f10d69a7 DG |
736 | db_id = select_doorbell_register(guc, client->priority); |
737 | if (db_id == GUC_INVALID_DOORBELL_ID) | |
738 | /* XXX: evict a doorbell instead? */ | |
739 | goto err; | |
740 | ||
44a28b1d DG |
741 | client->doorbell_offset = select_doorbell_cacheline(guc); |
742 | ||
743 | /* | |
744 | * Since the doorbell only requires a single cacheline, we can save | |
745 | * space by putting the application process descriptor in the same | |
746 | * page. Use the half of the page that doesn't include the doorbell. | |
747 | */ | |
748 | if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) | |
749 | client->proc_desc_offset = 0; | |
750 | else | |
751 | client->proc_desc_offset = (GUC_DB_SIZE / 2); | |
752 | ||
7a9347f9 DG |
753 | guc_proc_desc_init(guc, client); |
754 | guc_ctx_desc_init(guc, client); | |
4d357af4 CW |
755 | |
756 | /* For runtime client allocation we need to enable the doorbell. Not | |
757 | * required yet for the static execbuf_client as this special kernel | |
758 | * client is enabled from i915_guc_submission_enable(). | |
759 | * | |
760 | * guc_update_doorbell_id(guc, client, db_id); | |
761 | */ | |
44a28b1d | 762 | |
e02757d9 DG |
763 | DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n", |
764 | priority, client, client->engines, client->ctx_index); | |
a667429b DG |
765 | DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n", |
766 | client->doorbell_id, client->doorbell_offset); | |
44a28b1d DG |
767 | |
768 | return client; | |
769 | ||
770 | err: | |
0daf556c | 771 | guc_client_free(dev_priv, client); |
44a28b1d DG |
772 | return NULL; |
773 | } | |
774 | ||
4100b2ab | 775 | |
f8240835 | 776 | |
7a9347f9 | 777 | static void guc_policies_init(struct guc_policies *policies) |
463704d0 AD |
778 | { |
779 | struct guc_policy *policy; | |
780 | u32 p, i; | |
781 | ||
782 | policies->dpc_promote_time = 500000; | |
783 | policies->max_num_work_items = POLICY_MAX_NUM_WI; | |
784 | ||
785 | for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) { | |
397097b0 | 786 | for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) { |
463704d0 AD |
787 | policy = &policies->policy[p][i]; |
788 | ||
789 | policy->execution_quantum = 1000000; | |
790 | policy->preemption_time = 500000; | |
791 | policy->fault_time = 250000; | |
792 | policy->policy_flags = 0; | |
793 | } | |
794 | } | |
795 | ||
796 | policies->is_valid = 1; | |
797 | } | |
798 | ||
7a9347f9 | 799 | static void guc_addon_create(struct intel_guc *guc) |
68371a95 AD |
800 | { |
801 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
8b797af1 | 802 | struct i915_vma *vma; |
68371a95 | 803 | struct guc_ads *ads; |
463704d0 | 804 | struct guc_policies *policies; |
5c148e04 | 805 | struct guc_mmio_reg_state *reg_state; |
e2f80391 | 806 | struct intel_engine_cs *engine; |
3b3f1650 | 807 | enum intel_engine_id id; |
68371a95 | 808 | struct page *page; |
b4ac5afc | 809 | u32 size; |
68371a95 AD |
810 | |
811 | /* The ads obj includes the struct itself and buffers passed to GuC */ | |
5c148e04 AD |
812 | size = sizeof(struct guc_ads) + sizeof(struct guc_policies) + |
813 | sizeof(struct guc_mmio_reg_state) + | |
814 | GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE; | |
68371a95 | 815 | |
8b797af1 CW |
816 | vma = guc->ads_vma; |
817 | if (!vma) { | |
f9cda048 | 818 | vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(size)); |
8b797af1 | 819 | if (IS_ERR(vma)) |
68371a95 AD |
820 | return; |
821 | ||
8b797af1 | 822 | guc->ads_vma = vma; |
68371a95 AD |
823 | } |
824 | ||
8b797af1 | 825 | page = i915_vma_first_page(vma); |
68371a95 AD |
826 | ads = kmap(page); |
827 | ||
828 | /* | |
829 | * The GuC requires a "Golden Context" when it reinitialises | |
830 | * engines after a reset. Here we use the Render ring default | |
831 | * context, which must already exist and be pinned in the GGTT, | |
832 | * so its address won't change after we've told the GuC where | |
833 | * to find it. | |
834 | */ | |
3b3f1650 | 835 | engine = dev_priv->engine[RCS]; |
57e88531 | 836 | ads->golden_context_lrca = engine->status_page.ggtt_offset; |
68371a95 | 837 | |
3b3f1650 | 838 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 839 | ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine); |
68371a95 | 840 | |
463704d0 AD |
841 | /* GuC scheduling policies */ |
842 | policies = (void *)ads + sizeof(struct guc_ads); | |
7a9347f9 | 843 | guc_policies_init(policies); |
463704d0 | 844 | |
bde13ebd | 845 | ads->scheduler_policies = |
4741da92 | 846 | guc_ggtt_offset(vma) + sizeof(struct guc_ads); |
463704d0 | 847 | |
5c148e04 AD |
848 | /* MMIO reg state */ |
849 | reg_state = (void *)policies + sizeof(struct guc_policies); | |
850 | ||
3b3f1650 | 851 | for_each_engine(engine, dev_priv, id) { |
e2f80391 TU |
852 | reg_state->mmio_white_list[engine->guc_id].mmio_start = |
853 | engine->mmio_base + GUC_MMIO_WHITE_LIST_START; | |
5c148e04 AD |
854 | |
855 | /* Nothing to be saved or restored for now. */ | |
e2f80391 | 856 | reg_state->mmio_white_list[engine->guc_id].count = 0; |
5c148e04 AD |
857 | } |
858 | ||
859 | ads->reg_state_addr = ads->scheduler_policies + | |
860 | sizeof(struct guc_policies); | |
861 | ||
862 | ads->reg_state_buffer = ads->reg_state_addr + | |
863 | sizeof(struct guc_mmio_reg_state); | |
864 | ||
68371a95 AD |
865 | kunmap(page); |
866 | } | |
867 | ||
bac427f8 AD |
868 | /* |
869 | * Set up the memory resources to be shared with the GuC. At this point, | |
870 | * we require just one object that can be mapped through the GGTT. | |
871 | */ | |
beffa517 | 872 | int i915_guc_submission_init(struct drm_i915_private *dev_priv) |
bac427f8 | 873 | { |
7a9347f9 DG |
874 | const size_t ctxsize = sizeof(struct guc_context_desc); |
875 | const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize; | |
876 | const size_t gemsize = round_up(poolsize, PAGE_SIZE); | |
bac427f8 | 877 | struct intel_guc *guc = &dev_priv->guc; |
8b797af1 | 878 | struct i915_vma *vma; |
bac427f8 | 879 | |
4d357af4 CW |
880 | if (!HAS_GUC_SCHED(dev_priv)) |
881 | return 0; | |
882 | ||
29fb72c7 DG |
883 | /* Wipe bitmap & delete client in case of reinitialisation */ |
884 | bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS); | |
beffa517 | 885 | i915_guc_submission_disable(dev_priv); |
29fb72c7 | 886 | |
bac427f8 AD |
887 | if (!i915.enable_guc_submission) |
888 | return 0; /* not enabled */ | |
889 | ||
8b797af1 | 890 | if (guc->ctx_pool_vma) |
bac427f8 AD |
891 | return 0; /* already allocated */ |
892 | ||
f9cda048 | 893 | vma = intel_guc_allocate_vma(guc, gemsize); |
8b797af1 CW |
894 | if (IS_ERR(vma)) |
895 | return PTR_ERR(vma); | |
bac427f8 | 896 | |
8b797af1 | 897 | guc->ctx_pool_vma = vma; |
bac427f8 | 898 | ida_init(&guc->ctx_ids); |
f9cda048 | 899 | intel_guc_log_create(guc); |
7a9347f9 | 900 | guc_addon_create(guc); |
68371a95 | 901 | |
4d357af4 CW |
902 | guc->execbuf_client = guc_client_alloc(dev_priv, |
903 | INTEL_INFO(dev_priv)->ring_mask, | |
904 | GUC_CTX_PRIORITY_KMD_NORMAL, | |
905 | dev_priv->kernel_context); | |
906 | if (!guc->execbuf_client) { | |
907 | DRM_ERROR("Failed to create GuC client for execbuf!\n"); | |
908 | goto err; | |
909 | } | |
910 | ||
bac427f8 | 911 | return 0; |
4d357af4 CW |
912 | |
913 | err: | |
914 | i915_guc_submission_fini(dev_priv); | |
915 | return -ENOMEM; | |
916 | } | |
917 | ||
776594d5 | 918 | static void guc_reset_wq(struct i915_guc_client *client) |
4d357af4 | 919 | { |
776594d5 MW |
920 | struct guc_process_desc *desc = client->vaddr + |
921 | client->proc_desc_offset; | |
4d357af4 CW |
922 | |
923 | desc->head = 0; | |
924 | desc->tail = 0; | |
925 | ||
776594d5 | 926 | client->wq_tail = 0; |
bac427f8 AD |
927 | } |
928 | ||
beffa517 | 929 | int i915_guc_submission_enable(struct drm_i915_private *dev_priv) |
44a28b1d | 930 | { |
44a28b1d | 931 | struct intel_guc *guc = &dev_priv->guc; |
4d357af4 | 932 | struct i915_guc_client *client = guc->execbuf_client; |
ddd66c51 | 933 | struct intel_engine_cs *engine; |
3b3f1650 | 934 | enum intel_engine_id id; |
44a28b1d | 935 | |
4d357af4 CW |
936 | if (!client) |
937 | return -ENODEV; | |
44a28b1d | 938 | |
2d803c2d | 939 | intel_guc_sample_forcewake(guc); |
4d357af4 CW |
940 | |
941 | guc_reset_wq(client); | |
4d75787b | 942 | guc_init_doorbell_hw(guc); |
f5d3c3ea | 943 | |
ddd66c51 | 944 | /* Take over from manual control of ELSP (execlists) */ |
3b3f1650 | 945 | for_each_engine(engine, dev_priv, id) { |
4d357af4 CW |
946 | struct drm_i915_gem_request *rq; |
947 | ||
ddd66c51 | 948 | engine->submit_request = i915_guc_submit; |
20311bd3 | 949 | engine->schedule = NULL; |
ddd66c51 | 950 | |
821ed7df | 951 | /* Replay the current set of previously submitted requests */ |
4d357af4 | 952 | list_for_each_entry(rq, &engine->timeline->requests, link) { |
dadd481b | 953 | client->wq_rsvd += sizeof(struct guc_wq_item); |
34ba5a80 | 954 | __i915_guc_submit(rq); |
dadd481b | 955 | } |
821ed7df CW |
956 | } |
957 | ||
44a28b1d DG |
958 | return 0; |
959 | } | |
960 | ||
beffa517 | 961 | void i915_guc_submission_disable(struct drm_i915_private *dev_priv) |
44a28b1d | 962 | { |
44a28b1d DG |
963 | struct intel_guc *guc = &dev_priv->guc; |
964 | ||
ddd66c51 CW |
965 | if (!guc->execbuf_client) |
966 | return; | |
967 | ||
ddd66c51 CW |
968 | /* Revert back to manual ELSP submission */ |
969 | intel_execlists_enable_submission(dev_priv); | |
44a28b1d DG |
970 | } |
971 | ||
beffa517 | 972 | void i915_guc_submission_fini(struct drm_i915_private *dev_priv) |
bac427f8 | 973 | { |
bac427f8 | 974 | struct intel_guc *guc = &dev_priv->guc; |
4d357af4 CW |
975 | struct i915_guc_client *client; |
976 | ||
977 | client = fetch_and_zero(&guc->execbuf_client); | |
978 | if (!client) | |
979 | return; | |
980 | ||
981 | guc_client_free(dev_priv, client); | |
bac427f8 | 982 | |
19880c4a | 983 | i915_vma_unpin_and_release(&guc->ads_vma); |
d6b40b4b | 984 | i915_vma_unpin_and_release(&guc->log.vma); |
4c7e77fc | 985 | |
8b797af1 | 986 | if (guc->ctx_pool_vma) |
bac427f8 | 987 | ida_destroy(&guc->ctx_ids); |
19880c4a | 988 | i915_vma_unpin_and_release(&guc->ctx_pool_vma); |
bac427f8 | 989 | } |
a1c41994 AD |
990 | |
991 | /** | |
992 | * intel_guc_suspend() - notify GuC entering suspend state | |
bf9e8429 | 993 | * @dev_priv: i915 device private |
a1c41994 | 994 | */ |
bf9e8429 | 995 | int intel_guc_suspend(struct drm_i915_private *dev_priv) |
a1c41994 | 996 | { |
a1c41994 | 997 | struct intel_guc *guc = &dev_priv->guc; |
e2efd130 | 998 | struct i915_gem_context *ctx; |
a1c41994 AD |
999 | u32 data[3]; |
1000 | ||
db0a091b | 1001 | if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) |
a1c41994 AD |
1002 | return 0; |
1003 | ||
26705e20 SAK |
1004 | gen9_disable_guc_interrupts(dev_priv); |
1005 | ||
ed54c1a1 | 1006 | ctx = dev_priv->kernel_context; |
a1c41994 | 1007 | |
a80bc45f | 1008 | data[0] = INTEL_GUC_ACTION_ENTER_S_STATE; |
a1c41994 AD |
1009 | /* any value greater than GUC_POWER_D0 */ |
1010 | data[1] = GUC_POWER_D1; | |
1011 | /* first page is shared data with GuC */ | |
4741da92 | 1012 | data[2] = guc_ggtt_offset(ctx->engine[RCS].state); |
a1c41994 | 1013 | |
2d803c2d | 1014 | return intel_guc_send(guc, data, ARRAY_SIZE(data)); |
a1c41994 AD |
1015 | } |
1016 | ||
1017 | ||
1018 | /** | |
1019 | * intel_guc_resume() - notify GuC resuming from suspend state | |
bf9e8429 | 1020 | * @dev_priv: i915 device private |
a1c41994 | 1021 | */ |
bf9e8429 | 1022 | int intel_guc_resume(struct drm_i915_private *dev_priv) |
a1c41994 | 1023 | { |
a1c41994 | 1024 | struct intel_guc *guc = &dev_priv->guc; |
e2efd130 | 1025 | struct i915_gem_context *ctx; |
a1c41994 AD |
1026 | u32 data[3]; |
1027 | ||
db0a091b | 1028 | if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) |
a1c41994 AD |
1029 | return 0; |
1030 | ||
26705e20 SAK |
1031 | if (i915.guc_log_level >= 0) |
1032 | gen9_enable_guc_interrupts(dev_priv); | |
1033 | ||
ed54c1a1 | 1034 | ctx = dev_priv->kernel_context; |
a1c41994 | 1035 | |
a80bc45f | 1036 | data[0] = INTEL_GUC_ACTION_EXIT_S_STATE; |
a1c41994 AD |
1037 | data[1] = GUC_POWER_D0; |
1038 | /* first page is shared data with GuC */ | |
4741da92 | 1039 | data[2] = guc_ggtt_offset(ctx->engine[RCS].state); |
a1c41994 | 1040 | |
2d803c2d | 1041 | return intel_guc_send(guc, data, ARRAY_SIZE(data)); |
a1c41994 | 1042 | } |
4100b2ab | 1043 | |
f8240835 | 1044 |