[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_gpu_error.h

/*
 * SPDX-License-Identifier: MIT
 *
 * Copyright � 2008-2018 Intel Corporation
 */

#ifndef _I915_GPU_ERROR_H_
#define _I915_GPU_ERROR_H_

#include <linux/atomic.h>
#include <linux/kref.h>
#include <linux/ktime.h>
#include <linux/sched.h>

#include <drm/drm_mm.h>

#include "gt/intel_engine.h"
#include "gt/intel_gt_types.h"
#include "gt/uc/intel_uc_fw.h"

#include "intel_device_info.h"

#include "i915_gem.h"
#include "i915_gem_gtt.h"
#include "i915_params.h"
#include "i915_scheduler.h"

struct drm_i915_private;
struct i915_vma_compress;
struct intel_engine_capture_vma;
struct intel_overlay_error_state;
struct intel_display_error_state;

struct i915_vma_coredump {
	struct i915_vma_coredump *next;

	char name[20];

	u64 gtt_offset;
	u64 gtt_size;
	u32 gtt_page_sizes;

	int num_pages;
	int page_count;
	int unused;
	u32 *pages[];
};

struct i915_request_coredump {
	unsigned long flags;
	pid_t pid;
	u32 context;
	u32 seqno;
	u32 head;
	u32 tail;
	struct i915_sched_attr sched_attr;
};

struct intel_engine_coredump {
	const struct intel_engine_cs *engine;

	bool hung;
	bool simulated;
	u32 reset_count;

	/* position of active request inside the ring */
	u32 rq_head, rq_post, rq_tail;

	/* Register state */
	u32 ccid;
	u32 start;
	u32 tail;
	u32 head;
	u32 ctl;
	u32 mode;
	u32 hws;
	u32 ipeir;
	u32 ipehr;
	u32 esr;
	u32 bbstate;
	u32 instpm;
	u32 instps;
	u64 bbaddr;
	u64 acthd;
	u32 fault_reg;
	u64 faddr;
	u32 rc_psmi; /* sleep state */
	struct intel_instdone instdone;

	struct i915_gem_context_coredump {
		char comm[TASK_COMM_LEN];

		u64 total_runtime;
		u32 avg_runtime;

		pid_t pid;
		int active;
		int guilty;
		struct i915_sched_attr sched_attr;
	} context;

	struct i915_vma_coredump *vma;

	struct i915_request_coredump execlist[EXECLIST_MAX_PORTS];
	unsigned int num_ports;

	struct {
		u32 gfx_mode;
		union {
			u64 pdp[4];
			u32 pp_dir_base;
		};
	} vm_info;

	struct intel_engine_coredump *next;
};

struct intel_gt_coredump {
	const struct intel_gt *_gt;
	bool awake;
	bool simulated;

	struct intel_gt_info info;

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
	u32 gtier[6], ngtier;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
	u32 gtt_cache;
	u32 aux_err; /* gen12 */
	u32 sfc_done[GEN12_SFC_DONE_MAX]; /* gen12 */
	u32 gam_done; /* gen12 */

	u32 nfence;
	u64 fence[I915_MAX_NUM_FENCES];

	struct intel_engine_coredump *engine;

	struct intel_uc_coredump {
		struct intel_uc_fw guc_fw;
		struct intel_uc_fw huc_fw;
		struct i915_vma_coredump *guc_log;
	} *uc;

	struct intel_gt_coredump *next;
};

struct i915_gpu_coredump {
	struct kref ref;
	ktime_t time;
	ktime_t boottime;
	ktime_t uptime;
	unsigned long capture;

	struct drm_i915_private *i915;

	struct intel_gt_coredump *gt;

	char error_msg[128];
	bool simulated;
	bool wakelock;
	bool suspended;
	int iommu;
	u32 reset_count;
	u32 suspend_count;

	struct intel_device_info device_info;
	struct intel_runtime_info runtime_info;
	struct intel_driver_caps driver_caps;
	struct i915_params params;

	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;

	struct scatterlist *sgl, *fit;
};

struct i915_gpu_error {
	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct i915_gpu_coredump *first_error;

	atomic_t pending_fb_pin;

	/** Number of times the device has been reset (global) */
	atomic_t reset_count;

	/** Number of times an engine has been reset */
	atomic_t reset_engine_count[I915_NUM_ENGINES];
};

struct drm_i915_error_state_buf {
	struct drm_i915_private *i915;
	struct scatterlist *sgl, *cur, *end;

	char *buf;
	size_t bytes;
	size_t size;
	loff_t iter;

	int err;
};

#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);

struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt,
					    intel_engine_mask_t engine_mask);
void i915_capture_error_state(struct intel_gt *gt,
			      intel_engine_mask_t engine_mask);

struct i915_gpu_coredump *
i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);

struct intel_gt_coredump *
intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp);

struct intel_engine_coredump *
intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp);

struct intel_engine_capture_vma *
intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
				  struct i915_request *rq,
				  gfp_t gfp);

void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
				   struct intel_engine_capture_vma *capture,
				   struct i915_vma_compress *compress);

struct i915_vma_compress *
i915_vma_capture_prepare(struct intel_gt_coredump *gt);

void i915_vma_capture_finish(struct intel_gt_coredump *gt,
			     struct i915_vma_compress *compress);

void i915_error_state_store(struct i915_gpu_coredump *error);

static inline struct i915_gpu_coredump *
i915_gpu_coredump_get(struct i915_gpu_coredump *gpu)
{
	kref_get(&gpu->ref);
	return gpu;
}

ssize_t
i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
				 char *buf, loff_t offset, size_t count);

void __i915_gpu_coredump_free(struct kref *kref);
static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
{
	if (gpu)
		kref_put(&gpu->ref, __i915_gpu_coredump_free);
}

struct i915_gpu_coredump *i915_first_error_state(struct drm_i915_private *i915);
void i915_reset_error_state(struct drm_i915_private *i915);
void i915_disable_error_state(struct drm_i915_private *i915, int err);

#else

static inline void
i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask)
{
}

static inline struct i915_gpu_coredump *
i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
{
	return NULL;
}

static inline struct intel_gt_coredump *
intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp)
{
	return NULL;
}

static inline struct intel_engine_coredump *
intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp)
{
	return NULL;
}

static inline struct intel_engine_capture_vma *
intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
				  struct i915_request *rq,
				  gfp_t gfp)
{
	return NULL;
}

static inline void
intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
			      struct intel_engine_capture_vma *capture,
			      struct i915_vma_compress *compress)
{
}

static inline struct i915_vma_compress *
i915_vma_capture_prepare(struct intel_gt_coredump *gt)
{
	return NULL;
}

static inline void
i915_vma_capture_finish(struct intel_gt_coredump *gt,
			struct i915_vma_compress *compress)
{
}

static inline void
i915_error_state_store(struct i915_gpu_coredump *error)
{
}

static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
{
}

static inline struct i915_gpu_coredump *
i915_first_error_state(struct drm_i915_private *i915)
{
	return ERR_PTR(-ENODEV);
}

static inline void i915_reset_error_state(struct drm_i915_private *i915)
{
}

static inline void i915_disable_error_state(struct drm_i915_private *i915,
					    int err)
{
}

#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */

#endif /* _I915_GPU_ERROR_H_ */
Commit	Line	Data
d897a111 MW	1	/*
	2	* SPDX-License-Identifier: MIT
	3	*
	4	* Copyright � 2008-2018 Intel Corporation
	5	*/
	6
	7	#ifndef _I915_GPU_ERROR_H_
	8	#define _I915_GPU_ERROR_H_
	9
cb823ed9	10	#include <linux/atomic.h>
d897a111 MW	11	#include <linux/kref.h>
	12	#include <linux/ktime.h>
	13	#include <linux/sched.h>
	14
	15	#include <drm/drm_mm.h>
	16
112ed2d3	17	#include "gt/intel_engine.h"
792592e7	18	#include "gt/intel_gt_types.h"
0f261b24	19	#include "gt/uc/intel_uc_fw.h"
112ed2d3	20
d897a111	21	#include "intel_device_info.h"
d897a111 MW	22
	23	#include "i915_gem.h"
	24	#include "i915_gem_gtt.h"
	25	#include "i915_params.h"
b7268c5e	26	#include "i915_scheduler.h"
d897a111 MW	27
d897a111 MW	28	struct drm_i915_private;
742379c0 CW	29	struct i915_vma_compress;
742379c0 CW	30	struct intel_engine_capture_vma;
d897a111 MW	31	struct intel_overlay_error_state;
	32	struct intel_display_error_state;
	33
742379c0 CW	34	struct i915_vma_coredump {
742379c0 CW	35	struct i915_vma_coredump *next;
d897a111	36
742379c0 CW	37	char name[20];
	38
	39	u64 gtt_offset;
	40	u64 gtt_size;
	41	u32 gtt_page_sizes;
	42
	43	int num_pages;
	44	int page_count;
	45	int unused;
f1e79c7e	46	u32 *pages[];
742379c0 CW	47	};
	48
	49	struct i915_request_coredump {
	50	unsigned long flags;
	51	pid_t pid;
	52	u32 context;
	53	u32 seqno;
742379c0 CW	54	u32 head;
	55	u32 tail;
	56	struct i915_sched_attr sched_attr;
	57	};
	58
	59	struct intel_engine_coredump {
	60	const struct intel_engine_cs *engine;
d897a111	61
bda30024	62	bool hung;
d897a111	63	bool simulated;
d897a111	64	u32 reset_count;
d897a111	65
742379c0 CW	66	/* position of active request inside the ring */
	67	u32 rq_head, rq_post, rq_tail;
	68
742379c0 CW	69	/* Register state */
	70	u32 ccid;
	71	u32 start;
	72	u32 tail;
	73	u32 head;
	74	u32 ctl;
	75	u32 mode;
	76	u32 hws;
	77	u32 ipeir;
	78	u32 ipehr;
70a76a9b	79	u32 esr;
742379c0 CW	80	u32 bbstate;
	81	u32 instpm;
	82	u32 instps;
	83	u64 bbaddr;
	84	u64 acthd;
	85	u32 fault_reg;
	86	u64 faddr;
	87	u32 rc_psmi; /* sleep state */
	88	struct intel_instdone instdone;
	89
	90	struct i915_gem_context_coredump {
	91	char comm[TASK_COMM_LEN];
1883a0a4 TU	92
	93	u64 total_runtime;
	94	u32 avg_runtime;
	95
742379c0 CW	96	pid_t pid;
	97	int active;
	98	int guilty;
	99	struct i915_sched_attr sched_attr;
	100	} context;
	101
	102	struct i915_vma_coredump *vma;
	103
1a8585bd	104	struct i915_request_coredump execlist[EXECLIST_MAX_PORTS];
742379c0 CW	105	unsigned int num_ports;
	106
	107	struct {
	108	u32 gfx_mode;
	109	union {
	110	u64 pdp[4];
	111	u32 pp_dir_base;
	112	};
	113	} vm_info;
	114
	115	struct intel_engine_coredump *next;
	116	};
	117
	118	struct intel_gt_coredump {
	119	const struct intel_gt *_gt;
	120	bool awake;
	121	bool simulated;
d897a111	122
792592e7 DCS	123	struct intel_gt_info info;
792592e7 DCS	124
d897a111 MW	125	/* Generic register state */
	126	u32 eir;
	127	u32 pgtbl_er;
	128	u32 ier;
6b7a6a7b	129	u32 gtier[6], ngtier;
d897a111 MW	130	u32 derrmr;
	131	u32 forcewake;
	132	u32 error; /* gen6+ */
	133	u32 err_int; /* gen7 */
	134	u32 fault_data0; /* gen8, gen9 */
	135	u32 fault_data1; /* gen8, gen9 */
	136	u32 done_reg;
	137	u32 gac_eco;
	138	u32 gam_ecochk;
	139	u32 gab_ctl;
	140	u32 gfx_mode;
fd521d3b	141	u32 gtt_cache;
ba1d18e3	142	u32 aux_err; /* gen12 */
e50dbdbf	143	u32 sfc_done[GEN12_SFC_DONE_MAX]; /* gen12 */
811bb3db	144	u32 gam_done; /* gen12 */
d897a111 MW	145
	146	u32 nfence;
	147	u64 fence[I915_MAX_NUM_FENCES];
742379c0 CW	148
	149	struct intel_engine_coredump *engine;
	150
	151	struct intel_uc_coredump {
	152	struct intel_uc_fw guc_fw;
	153	struct intel_uc_fw huc_fw;
	154	struct i915_vma_coredump *guc_log;
	155	} *uc;
	156
	157	struct intel_gt_coredump *next;
	158	};
	159
	160	struct i915_gpu_coredump {
	161	struct kref ref;
	162	ktime_t time;
	163	ktime_t boottime;
	164	ktime_t uptime;
	165	unsigned long capture;
	166
	167	struct drm_i915_private *i915;
	168
	169	struct intel_gt_coredump *gt;
	170
	171	char error_msg[128];
	172	bool simulated;
	173	bool wakelock;
	174	bool suspended;
	175	int iommu;
	176	u32 reset_count;
	177	u32 suspend_count;
	178
	179	struct intel_device_info device_info;
	180	struct intel_runtime_info runtime_info;
	181	struct intel_driver_caps driver_caps;
	182	struct i915_params params;
	183
d897a111 MW	184	struct intel_overlay_error_state *overlay;
	185	struct intel_display_error_state *display;
	186
0e39037b	187	struct scatterlist sgl, fit;
d897a111 MW	188	};
	189
	190	struct i915_gpu_error {
d897a111 MW	191	/* For reset and error_state handling. */
	192	spinlock_t lock;
	193	/* Protected by the above dev->gpu_error.lock. */
742379c0	194	struct i915_gpu_coredump *first_error;
d897a111 MW	195
	196	atomic_t pending_fb_pin;
	197
2caffbf1	198	/** Number of times the device has been reset (global) */
cb823ed9	199	atomic_t reset_count;
2caffbf1	200
d897a111	201	/** Number of times an engine has been reset */
cb823ed9	202	atomic_t reset_engine_count[I915_NUM_ENGINES];
d897a111 MW	203	};
	204
	205	struct drm_i915_error_state_buf {
	206	struct drm_i915_private *i915;
0e39037b CW	207	struct scatterlist sgl, cur, *end;
	208
	209	char *buf;
	210	size_t bytes;
	211	size_t size;
	212	loff_t iter;
	213
d897a111	214	int err;
d897a111 MW	215	};
	216
	217	#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
	218
	219	__printf(2, 3)
	220	void i915_error_printf(struct drm_i915_error_state_buf e, const char f, ...);
d897a111	221
bda30024 TU	222	struct i915_gpu_coredump i915_gpu_coredump(struct intel_gt gt,
	223	intel_engine_mask_t engine_mask);
	224	void i915_capture_error_state(struct intel_gt *gt,
	225	intel_engine_mask_t engine_mask);
742379c0 CW	226
	227	struct i915_gpu_coredump *
	228	i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);
	229
	230	struct intel_gt_coredump *
	231	intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp);
	232
	233	struct intel_engine_coredump *
	234	intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp);
d897a111	235
742379c0 CW	236	struct intel_engine_capture_vma *
	237	intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
	238	struct i915_request *rq,
	239	gfp_t gfp);
	240
	241	void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
	242	struct intel_engine_capture_vma *capture,
	243	struct i915_vma_compress *compress);
	244
	245	struct i915_vma_compress *
	246	i915_vma_capture_prepare(struct intel_gt_coredump *gt);
	247
	248	void i915_vma_capture_finish(struct intel_gt_coredump *gt,
	249	struct i915_vma_compress *compress);
	250
	251	void i915_error_state_store(struct i915_gpu_coredump *error);
	252
	253	static inline struct i915_gpu_coredump *
	254	i915_gpu_coredump_get(struct i915_gpu_coredump *gpu)
d897a111 MW	255	{
	256	kref_get(&gpu->ref);
	257	return gpu;
	258	}
	259
742379c0 CW	260	ssize_t
	261	i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
	262	char *buf, loff_t offset, size_t count);
0e39037b	263
742379c0 CW	264	void __i915_gpu_coredump_free(struct kref *kref);
742379c0 CW	265	static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
d897a111 MW	266	{
d897a111 MW	267	if (gpu)
742379c0	268	kref_put(&gpu->ref, __i915_gpu_coredump_free);
d897a111 MW	269	}
d897a111 MW	270
742379c0	271	struct i915_gpu_coredump i915_first_error_state(struct drm_i915_private i915);
d897a111	272	void i915_reset_error_state(struct drm_i915_private *i915);
fb6f0b64	273	void i915_disable_error_state(struct drm_i915_private *i915, int err);
d897a111 MW	274
	275	#else
	276
bda30024 TU	277	static inline void
bda30024 TU	278	i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask)
d897a111 MW	279	{
	280	}
	281
742379c0 CW	282	static inline struct i915_gpu_coredump *
	283	i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
	284	{
	285	return NULL;
	286	}
	287
	288	static inline struct intel_gt_coredump *
	289	intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp)
	290	{
	291	return NULL;
	292	}
	293
	294	static inline struct intel_engine_coredump *
	295	intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp)
	296	{
	297	return NULL;
	298	}
	299
	300	static inline struct intel_engine_capture_vma *
	301	intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
	302	struct i915_request *rq,
	303	gfp_t gfp)
	304	{
	305	return NULL;
	306	}
	307
	308	static inline void
	309	intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
	310	struct intel_engine_capture_vma *capture,
	311	struct i915_vma_compress *compress)
	312	{
	313	}
	314
	315	static inline struct i915_vma_compress *
d713e3ab	316	i915_vma_capture_prepare(struct intel_gt_coredump *gt)
742379c0 CW	317	{
	318	return NULL;
	319	}
	320
59be9b9c ZX	321	static inline void
	322	i915_vma_capture_finish(struct intel_gt_coredump *gt,
	323	struct i915_vma_compress *compress)
742379c0 CW	324	{
	325	}
	326
	327	static inline void
04062c58	328	i915_error_state_store(struct i915_gpu_coredump *error)
742379c0 CW	329	{
	330	}
	331
7e36505d CW	332	static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
	333	{
	334	}
	335
742379c0	336	static inline struct i915_gpu_coredump *
d897a111 MW	337	i915_first_error_state(struct drm_i915_private *i915)
d897a111 MW	338	{
fb6f0b64	339	return ERR_PTR(-ENODEV);
d897a111 MW	340	}
	341
	342	static inline void i915_reset_error_state(struct drm_i915_private *i915)
	343	{
	344	}
	345
fb6f0b64 CW	346	static inline void i915_disable_error_state(struct drm_i915_private *i915,
	347	int err)
	348	{
	349	}
	350
d897a111 MW	351	#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
	352
	353	#endif /* _I915_GPU_ERROR_H_ */