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drm/i915: Add vm to error BO capture
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
33static const char *yesno(int v)
34{
35 return v ? "yes" : "no";
36}
37
38static const char *ring_str(int ring)
39{
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 default: return "";
46 }
47}
48
49static const char *pin_flag(int pinned)
50{
51 if (pinned > 0)
52 return " P";
53 else if (pinned < 0)
54 return " p";
55 else
56 return "";
57}
58
59static const char *tiling_flag(int tiling)
60{
61 switch (tiling) {
62 default:
63 case I915_TILING_NONE: return "";
64 case I915_TILING_X: return " X";
65 case I915_TILING_Y: return " Y";
66 }
67}
68
69static const char *dirty_flag(int dirty)
70{
71 return dirty ? " dirty" : "";
72}
73
74static const char *purgeable_flag(int purgeable)
75{
76 return purgeable ? " purgeable" : "";
77}
78
79static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
80{
81
82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
83 e->err = -ENOSPC;
84 return false;
85 }
86
87 if (e->bytes == e->size - 1 || e->err)
88 return false;
89
90 return true;
91}
92
93static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
94 unsigned len)
95{
96 if (e->pos + len <= e->start) {
97 e->pos += len;
98 return false;
99 }
100
101 /* First vsnprintf needs to fit in its entirety for memmove */
102 if (len >= e->size) {
103 e->err = -EIO;
104 return false;
105 }
106
107 return true;
108}
109
110static void __i915_error_advance(struct drm_i915_error_state_buf *e,
111 unsigned len)
112{
113 /* If this is first printf in this window, adjust it so that
114 * start position matches start of the buffer
115 */
116
117 if (e->pos < e->start) {
118 const size_t off = e->start - e->pos;
119
120 /* Should not happen but be paranoid */
121 if (off > len || e->bytes) {
122 e->err = -EIO;
123 return;
124 }
125
126 memmove(e->buf, e->buf + off, len - off);
127 e->bytes = len - off;
128 e->pos = e->start;
129 return;
130 }
131
132 e->bytes += len;
133 e->pos += len;
134}
135
136static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
137 const char *f, va_list args)
138{
139 unsigned len;
140
141 if (!__i915_error_ok(e))
142 return;
143
144 /* Seek the first printf which is hits start position */
145 if (e->pos < e->start) {
e29bb4eb
CW		 146 va_list tmp;
147
148 va_copy(tmp, args);
149 if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp)))
84734a04
MK		 150 return;
151 }
152
153 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
154 if (len >= e->size - e->bytes)
155 len = e->size - e->bytes - 1;
156
157 __i915_error_advance(e, len);
158}
159
160static void i915_error_puts(struct drm_i915_error_state_buf *e,
161 const char *str)
162{
163 unsigned len;
164
165 if (!__i915_error_ok(e))
166 return;
167
168 len = strlen(str);
169
170 /* Seek the first printf which is hits start position */
171 if (e->pos < e->start) {
172 if (!__i915_error_seek(e, len))
173 return;
174 }
175
176 if (len >= e->size - e->bytes)
177 len = e->size - e->bytes - 1;
178 memcpy(e->buf + e->bytes, str, len);
179
180 __i915_error_advance(e, len);
181}
182
183#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
184#define err_puts(e, s) i915_error_puts(e, s)
185
186static void print_error_buffers(struct drm_i915_error_state_buf *m,
187 const char *name,
188 struct drm_i915_error_buffer *err,
189 int count)
190{
191 err_printf(m, "%s [%d]:\n", name, count);
192
193 while (count--) {
194 err_printf(m, " %08x %8u %02x %02x %x %x",
195 err->gtt_offset,
196 err->size,
197 err->read_domains,
198 err->write_domain,
199 err->rseqno, err->wseqno);
200 err_puts(m, pin_flag(err->pinned));
201 err_puts(m, tiling_flag(err->tiling));
202 err_puts(m, dirty_flag(err->dirty));
203 err_puts(m, purgeable_flag(err->purgeable));
204 err_puts(m, err->ring != -1 ? " " : "");
205 err_puts(m, ring_str(err->ring));
206 err_puts(m, i915_cache_level_str(err->cache_level));
207
208 if (err->name)
209 err_printf(m, " (name: %d)", err->name);
210 if (err->fence_reg != I915_FENCE_REG_NONE)
211 err_printf(m, " (fence: %d)", err->fence_reg);
212
213 err_puts(m, "\n");
214 err++;
215 }
216}
217
da661464
MK		 218static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
219{
220 switch (a) {
221 case HANGCHECK_IDLE:
222 return "idle";
223 case HANGCHECK_WAIT:
224 return "wait";
225 case HANGCHECK_ACTIVE:
226 return "active";
227 case HANGCHECK_KICK:
228 return "kick";
229 case HANGCHECK_HUNG:
230 return "hung";
231 }
232
233 return "unknown";
234}
235
84734a04
MK		 236static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
237 struct drm_device *dev,
238 struct drm_i915_error_state *error,
239 unsigned ring)
240{
241 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
242 err_printf(m, "%s command stream:\n", ring_str(ring));
243 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
244 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
245 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
246 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
247 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
248 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
249 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
250 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
251 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
94e39e28
CW		 252 if (INTEL_INFO(dev)->gen >= 4)
253 err_printf(m, " BB_STATE: 0x%08x\n", error->bbstate[ring]);
84734a04
MK		 254 if (INTEL_INFO(dev)->gen >= 4)
255 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
256 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
257 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
258 if (INTEL_INFO(dev)->gen >= 6) {
259 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
260 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
261 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
262 error->semaphore_mboxes[ring][0],
263 error->semaphore_seqno[ring][0]);
264 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
265 error->semaphore_mboxes[ring][1],
266 error->semaphore_seqno[ring][1]);
4e5aabfd
BW		 267 if (HAS_VEBOX(dev)) {
268 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
269 error->semaphore_mboxes[ring][2],
270 error->semaphore_seqno[ring][2]);
271 }
84734a04
MK		 272 }
273 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
274 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
275 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
276 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
da661464
MK		 277 err_printf(m, " hangcheck: %s [%d]\n",
278 hangcheck_action_to_str(error->hangcheck_action[ring]),
279 error->hangcheck_score[ring]);
84734a04
MK		 280}
281
282void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
283{
284 va_list args;
285
286 va_start(args, f);
287 i915_error_vprintf(e, f, args);
288 va_end(args);
289}
290
291int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
292 const struct i915_error_state_file_priv *error_priv)
293{
294 struct drm_device *dev = error_priv->dev;
295 drm_i915_private_t *dev_priv = dev->dev_private;
296 struct drm_i915_error_state *error = error_priv->error;
297 struct intel_ring_buffer *ring;
298 int i, j, page, offset, elt;
299
300 if (!error) {
301 err_printf(m, "no error state collected\n");
302 goto out;
303 }
304
305 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
306 error->time.tv_usec);
307 err_printf(m, "Kernel: " UTS_RELEASE "\n");
ffbab09b 308 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
84734a04
MK		 309 err_printf(m, "EIR: 0x%08x\n", error->eir);
310 err_printf(m, "IER: 0x%08x\n", error->ier);
311 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
312 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
313 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
314 err_printf(m, "CCID: 0x%08x\n", error->ccid);
094f9a54 315 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
84734a04
MK		 316
317 for (i = 0; i < dev_priv->num_fence_regs; i++)
318 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
319
320 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
321 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
322 error->extra_instdone[i]);
323
324 if (INTEL_INFO(dev)->gen >= 6) {
325 err_printf(m, "ERROR: 0x%08x\n", error->error);
326 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
327 }
328
329 if (INTEL_INFO(dev)->gen == 7)
330 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
331
332 for_each_ring(ring, dev_priv, i)
333 i915_ring_error_state(m, dev, error, i);
334
335 if (error->active_bo)
336 print_error_buffers(m, "Active",
95f5301d
BW		 337 error->active_bo[0],
338 error->active_bo_count[0]);
84734a04
MK		 339
340 if (error->pinned_bo)
341 print_error_buffers(m, "Pinned",
95f5301d
BW		 342 error->pinned_bo[0],
343 error->pinned_bo_count[0]);
84734a04
MK		 344
345 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
346 struct drm_i915_error_object *obj;
347
348 if ((obj = error->ring[i].batchbuffer)) {
349 err_printf(m, "%s --- gtt_offset = 0x%08x\n",
350 dev_priv->ring[i].name,
351 obj->gtt_offset);
352 offset = 0;
353 for (page = 0; page < obj->page_count; page++) {
354 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
355 err_printf(m, "%08x : %08x\n", offset,
356 obj->pages[page][elt]);
357 offset += 4;
358 }
359 }
360 }
361
362 if (error->ring[i].num_requests) {
363 err_printf(m, "%s --- %d requests\n",
364 dev_priv->ring[i].name,
365 error->ring[i].num_requests);
366 for (j = 0; j < error->ring[i].num_requests; j++) {
367 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
368 error->ring[i].requests[j].seqno,
369 error->ring[i].requests[j].jiffies,
370 error->ring[i].requests[j].tail);
371 }
372 }
373
374 if ((obj = error->ring[i].ringbuffer)) {
375 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
376 dev_priv->ring[i].name,
377 obj->gtt_offset);
378 offset = 0;
379 for (page = 0; page < obj->page_count; page++) {
380 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
381 err_printf(m, "%08x : %08x\n",
382 offset,
383 obj->pages[page][elt]);
384 offset += 4;
385 }
386 }
387 }
388
389 obj = error->ring[i].ctx;
390 if (obj) {
391 err_printf(m, "%s --- HW Context = 0x%08x\n",
392 dev_priv->ring[i].name,
393 obj->gtt_offset);
394 offset = 0;
395 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
396 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
397 offset,
398 obj->pages[0][elt],
399 obj->pages[0][elt+1],
400 obj->pages[0][elt+2],
401 obj->pages[0][elt+3]);
402 offset += 16;
403 }
404 }
405 }
406
407 if (error->overlay)
408 intel_overlay_print_error_state(m, error->overlay);
409
410 if (error->display)
411 intel_display_print_error_state(m, dev, error->display);
412
413out:
414 if (m->bytes == 0 && m->err)
415 return m->err;
416
417 return 0;
418}
419
420int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
421 size_t count, loff_t pos)
422{
423 memset(ebuf, 0, sizeof(*ebuf));
424
425 /* We need to have enough room to store any i915_error_state printf
426 * so that we can move it to start position.
427 */
428 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
429 ebuf->buf = kmalloc(ebuf->size,
430 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
431
432 if (ebuf->buf == NULL) {
433 ebuf->size = PAGE_SIZE;
434 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
435 }
436
437 if (ebuf->buf == NULL) {
438 ebuf->size = 128;
439 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
440 }
441
442 if (ebuf->buf == NULL)
443 return -ENOMEM;
444
445 ebuf->start = pos;
446
447 return 0;
448}
449
450static void i915_error_object_free(struct drm_i915_error_object *obj)
451{
452 int page;
453
454 if (obj == NULL)
455 return;
456
457 for (page = 0; page < obj->page_count; page++)
458 kfree(obj->pages[page]);
459
460 kfree(obj);
461}
462
463static void i915_error_state_free(struct kref *error_ref)
464{
465 struct drm_i915_error_state *error = container_of(error_ref,
466 typeof(*error), ref);
467 int i;
468
469 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
470 i915_error_object_free(error->ring[i].batchbuffer);
471 i915_error_object_free(error->ring[i].ringbuffer);
472 i915_error_object_free(error->ring[i].ctx);
473 kfree(error->ring[i].requests);
474 }
475
476 kfree(error->active_bo);
477 kfree(error->overlay);
478 kfree(error->display);
479 kfree(error);
480}
481
482static struct drm_i915_error_object *
483i915_error_object_create_sized(struct drm_i915_private *dev_priv,
484 struct drm_i915_gem_object *src,
a7b91078 485 struct i915_address_space *vm,
84734a04
MK		 486 const int num_pages)
487{
488 struct drm_i915_error_object *dst;
489 int i;
490 u32 reloc_offset;
491
492 if (src == NULL || src->pages == NULL)
493 return NULL;
494
495 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
496 if (dst == NULL)
497 return NULL;
498
a7b91078 499 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
84734a04
MK		 500 for (i = 0; i < num_pages; i++) {
501 unsigned long flags;
502 void *d;
503
504 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
505 if (d == NULL)
506 goto unwind;
507
508 local_irq_save(flags);
509 if (reloc_offset < dev_priv->gtt.mappable_end &&
510 src->has_global_gtt_mapping) {
511 void __iomem *s;
512
513 /* Simply ignore tiling or any overlapping fence.
514 * It's part of the error state, and this hopefully
515 * captures what the GPU read.
516 */
517
518 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
519 reloc_offset);
520 memcpy_fromio(d, s, PAGE_SIZE);
521 io_mapping_unmap_atomic(s);
522 } else if (src->stolen) {
523 unsigned long offset;
524
525 offset = dev_priv->mm.stolen_base;
526 offset += src->stolen->start;
527 offset += i << PAGE_SHIFT;
528
529 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
530 } else {
531 struct page *page;
532 void *s;
533
534 page = i915_gem_object_get_page(src, i);
535
536 drm_clflush_pages(&page, 1);
537
538 s = kmap_atomic(page);
539 memcpy(d, s, PAGE_SIZE);
540 kunmap_atomic(s);
541
542 drm_clflush_pages(&page, 1);
543 }
544 local_irq_restore(flags);
545
546 dst->pages[i] = d;
547
548 reloc_offset += PAGE_SIZE;
549 }
550 dst->page_count = num_pages;
551
552 return dst;
553
554unwind:
555 while (i--)
556 kfree(dst->pages[i]);
557 kfree(dst);
558 return NULL;
559}
a7b91078
BW		 560#define i915_error_object_create(dev_priv, src, vm) \
561 i915_error_object_create_sized((dev_priv), (src), (vm), \
562 (src)->base.size>>PAGE_SHIFT)
563
564#define i915_error_ggtt_object_create(dev_priv, src) \
565 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
84734a04
MK		 566 (src)->base.size>>PAGE_SHIFT)
567
568static void capture_bo(struct drm_i915_error_buffer *err,
569 struct drm_i915_gem_object *obj)
570{
571 err->size = obj->base.size;
572 err->name = obj->base.name;
573 err->rseqno = obj->last_read_seqno;
574 err->wseqno = obj->last_write_seqno;
575 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
576 err->read_domains = obj->base.read_domains;
577 err->write_domain = obj->base.write_domain;
578 err->fence_reg = obj->fence_reg;
579 err->pinned = 0;
580 if (obj->pin_count > 0)
581 err->pinned = 1;
582 if (obj->user_pin_count > 0)
583 err->pinned = -1;
584 err->tiling = obj->tiling_mode;
585 err->dirty = obj->dirty;
586 err->purgeable = obj->madv != I915_MADV_WILLNEED;
587 err->ring = obj->ring ? obj->ring->id : -1;
588 err->cache_level = obj->cache_level;
589}
590
591static u32 capture_active_bo(struct drm_i915_error_buffer *err,
592 int count, struct list_head *head)
593{
ca191b13 594 struct i915_vma *vma;
84734a04
MK		 595 int i = 0;
596
ca191b13
BW		 597 list_for_each_entry(vma, head, mm_list) {
598 capture_bo(err++, vma->obj);
84734a04
MK		 599 if (++i == count)
600 break;
601 }
602
603 return i;
604}
605
606static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
607 int count, struct list_head *head)
608{
609 struct drm_i915_gem_object *obj;
610 int i = 0;
611
612 list_for_each_entry(obj, head, global_list) {
613 if (obj->pin_count == 0)
614 continue;
615
616 capture_bo(err++, obj);
617 if (++i == count)
618 break;
619 }
620
621 return i;
622}
623
624static void i915_gem_record_fences(struct drm_device *dev,
625 struct drm_i915_error_state *error)
626{
627 struct drm_i915_private *dev_priv = dev->dev_private;
628 int i;
629
630 /* Fences */
631 switch (INTEL_INFO(dev)->gen) {
5ab31333 632 case 8:
84734a04
MK		 633 case 7:
634 case 6:
635 for (i = 0; i < dev_priv->num_fence_regs; i++)
636 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
637 break;
638 case 5:
639 case 4:
640 for (i = 0; i < 16; i++)
641 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
642 break;
643 case 3:
644 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
645 for (i = 0; i < 8; i++)
646 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
647 case 2:
648 for (i = 0; i < 8; i++)
649 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
650 break;
651
652 default:
653 BUG();
654 }
655}
656
657static struct drm_i915_error_object *
658i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
659 struct intel_ring_buffer *ring)
660{
ca191b13
BW		 661 struct i915_address_space *vm;
662 struct i915_vma *vma;
84734a04
MK		 663 struct drm_i915_gem_object *obj;
664 u32 seqno;
665
666 if (!ring->get_seqno)
667 return NULL;
668
669 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
670 u32 acthd = I915_READ(ACTHD);
671
672 if (WARN_ON(ring->id != RCS))
673 return NULL;
674
0d1aacac 675 obj = ring->scratch.obj;
84734a04
MK		 676 if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
677 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
a7b91078 678 return i915_error_ggtt_object_create(dev_priv, obj);
84734a04
MK		 679 }
680
681 seqno = ring->get_seqno(ring, false);
ca191b13
BW		 682 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
683 list_for_each_entry(vma, &vm->active_list, mm_list) {
684 obj = vma->obj;
685 if (obj->ring != ring)
686 continue;
84734a04 687
ca191b13
BW		 688 if (i915_seqno_passed(seqno, obj->last_read_seqno))
689 continue;
84734a04 690
ca191b13
BW		 691 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
692 continue;
84734a04 693
ca191b13
BW		 694 /* We need to copy these to an anonymous buffer as the simplest
695 * method to avoid being overwritten by userspace.
696 */
a7b91078 697 return i915_error_object_create(dev_priv, obj, vm);
ca191b13 698 }
84734a04
MK		 699 }
700
701 return NULL;
702}
703
704static void i915_record_ring_state(struct drm_device *dev,
705 struct drm_i915_error_state *error,
706 struct intel_ring_buffer *ring)
707{
708 struct drm_i915_private *dev_priv = dev->dev_private;
709
710 if (INTEL_INFO(dev)->gen >= 6) {
711 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
712 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
713 error->semaphore_mboxes[ring->id][0]
714 = I915_READ(RING_SYNC_0(ring->mmio_base));
715 error->semaphore_mboxes[ring->id][1]
716 = I915_READ(RING_SYNC_1(ring->mmio_base));
717 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
718 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
719 }
720
4e5aabfd
BW		 721 if (HAS_VEBOX(dev)) {
722 error->semaphore_mboxes[ring->id][2] =
723 I915_READ(RING_SYNC_2(ring->mmio_base));
724 error->semaphore_seqno[ring->id][2] = ring->sync_seqno[2];
725 }
726
84734a04
MK		 727 if (INTEL_INFO(dev)->gen >= 4) {
728 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
729 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
730 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
731 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
732 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
733 if (ring->id == RCS)
734 error->bbaddr = I915_READ64(BB_ADDR);
94e39e28 735 error->bbstate[ring->id] = I915_READ(RING_BBSTATE(ring->mmio_base));
84734a04
MK		 736 } else {
737 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
738 error->ipeir[ring->id] = I915_READ(IPEIR);
739 error->ipehr[ring->id] = I915_READ(IPEHR);
740 error->instdone[ring->id] = I915_READ(INSTDONE);
741 }
742
743 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
744 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
745 error->seqno[ring->id] = ring->get_seqno(ring, false);
746 error->acthd[ring->id] = intel_ring_get_active_head(ring);
747 error->head[ring->id] = I915_READ_HEAD(ring);
748 error->tail[ring->id] = I915_READ_TAIL(ring);
749 error->ctl[ring->id] = I915_READ_CTL(ring);
750
751 error->cpu_ring_head[ring->id] = ring->head;
752 error->cpu_ring_tail[ring->id] = ring->tail;
da661464
MK		 753
754 error->hangcheck_score[ring->id] = ring->hangcheck.score;
755 error->hangcheck_action[ring->id] = ring->hangcheck.action;
84734a04
MK		 756}
757
758
759static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
760 struct drm_i915_error_state *error,
761 struct drm_i915_error_ring *ering)
762{
763 struct drm_i915_private *dev_priv = ring->dev->dev_private;
764 struct drm_i915_gem_object *obj;
765
766 /* Currently render ring is the only HW context user */
767 if (ring->id != RCS || !error->ccid)
768 return;
769
770 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
771 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
772 ering->ctx = i915_error_object_create_sized(dev_priv,
a7b91078
BW		 773 obj,
774 &dev_priv->gtt.base,
775 1);
84734a04
MK		 776 break;
777 }
778 }
779}
780
781static void i915_gem_record_rings(struct drm_device *dev,
782 struct drm_i915_error_state *error)
783{
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 struct intel_ring_buffer *ring;
786 struct drm_i915_gem_request *request;
787 int i, count;
788
789 for_each_ring(ring, dev_priv, i) {
790 i915_record_ring_state(dev, error, ring);
791
792 error->ring[i].batchbuffer =
793 i915_error_first_batchbuffer(dev_priv, ring);
794
795 error->ring[i].ringbuffer =
a7b91078 796 i915_error_ggtt_object_create(dev_priv, ring->obj);
84734a04
MK		 797
798
799 i915_gem_record_active_context(ring, error, &error->ring[i]);
800
801 count = 0;
802 list_for_each_entry(request, &ring->request_list, list)
803 count++;
804
805 error->ring[i].num_requests = count;
806 error->ring[i].requests =
a1e22653 807 kcalloc(count, sizeof(*error->ring[i].requests),
84734a04
MK		 808 GFP_ATOMIC);
809 if (error->ring[i].requests == NULL) {
810 error->ring[i].num_requests = 0;
811 continue;
812 }
813
814 count = 0;
815 list_for_each_entry(request, &ring->request_list, list) {
816 struct drm_i915_error_request *erq;
817
818 erq = &error->ring[i].requests[count++];
819 erq->seqno = request->seqno;
820 erq->jiffies = request->emitted_jiffies;
821 erq->tail = request->tail;
822 }
823 }
824}
825
95f5301d
BW		 826/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
827 * VM.
828 */
829static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
830 struct drm_i915_error_state *error,
831 struct i915_address_space *vm,
832 const int ndx)
84734a04 833{
95f5301d 834 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
84734a04 835 struct drm_i915_gem_object *obj;
95f5301d 836 struct i915_vma *vma;
84734a04
MK		 837 int i;
838
839 i = 0;
ca191b13 840 list_for_each_entry(vma, &vm->active_list, mm_list)
84734a04 841 i++;
95f5301d 842 error->active_bo_count[ndx] = i;
84734a04
MK		 843 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
844 if (obj->pin_count)
845 i++;
95f5301d 846 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
84734a04
MK		 847
848 if (i) {
a1e22653 849 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
95f5301d
BW		 850 if (active_bo)
851 pinned_bo = active_bo + error->active_bo_count[ndx];
84734a04
MK		 852 }
853
95f5301d
BW		 854 if (active_bo)
855 error->active_bo_count[ndx] =
856 capture_active_bo(active_bo,
857 error->active_bo_count[ndx],
5cef07e1 858 &vm->active_list);
84734a04 859
95f5301d
BW		 860 if (pinned_bo)
861 error->pinned_bo_count[ndx] =
862 capture_pinned_bo(pinned_bo,
863 error->pinned_bo_count[ndx],
84734a04 864 &dev_priv->mm.bound_list);
95f5301d
BW		 865 error->active_bo[ndx] = active_bo;
866 error->pinned_bo[ndx] = pinned_bo;
867}
868
869static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
870 struct drm_i915_error_state *error)
871{
872 struct i915_address_space *vm;
873 int cnt = 0, i = 0;
874
875 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
876 cnt++;
877
878 if (WARN(cnt > 1, "Multiple VMs not yet supported\n"))
879 cnt = 1;
880
881 vm = &dev_priv->gtt.base;
882
883 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
884 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
885 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
886 GFP_ATOMIC);
887 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
888 GFP_ATOMIC);
889
890 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
891 i915_gem_capture_vm(dev_priv, error, vm, i++);
84734a04
MK		 892}
893
894/**
895 * i915_capture_error_state - capture an error record for later analysis
896 * @dev: drm device
897 *
898 * Should be called when an error is detected (either a hang or an error
899 * interrupt) to capture error state from the time of the error. Fills
900 * out a structure which becomes available in debugfs for user level tools
901 * to pick up.
902 */
903void i915_capture_error_state(struct drm_device *dev)
904{
905 struct drm_i915_private *dev_priv = dev->dev_private;
906 struct drm_i915_error_state *error;
907 unsigned long flags;
908 int pipe;
909
910 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
911 error = dev_priv->gpu_error.first_error;
912 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
913 if (error)
914 return;
915
916 /* Account for pipe specific data like PIPE*STAT */
917 error = kzalloc(sizeof(*error), GFP_ATOMIC);
918 if (!error) {
919 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
920 return;
921 }
922
f4689801
DV		 923 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
924 dev->primary->index);
925 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
926 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
927 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
928 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
84734a04
MK		 929
930 kref_init(&error->ref);
931 error->eir = I915_READ(EIR);
932 error->pgtbl_er = I915_READ(PGTBL_ER);
933 if (HAS_HW_CONTEXTS(dev))
934 error->ccid = I915_READ(CCID);
935
936 if (HAS_PCH_SPLIT(dev))
937 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
938 else if (IS_VALLEYVIEW(dev))
939 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
940 else if (IS_GEN2(dev))
941 error->ier = I915_READ16(IER);
942 else
943 error->ier = I915_READ(IER);
944
945 if (INTEL_INFO(dev)->gen >= 6)
946 error->derrmr = I915_READ(DERRMR);
947
948 if (IS_VALLEYVIEW(dev))
949 error->forcewake = I915_READ(FORCEWAKE_VLV);
950 else if (INTEL_INFO(dev)->gen >= 7)
951 error->forcewake = I915_READ(FORCEWAKE_MT);
952 else if (INTEL_INFO(dev)->gen == 6)
953 error->forcewake = I915_READ(FORCEWAKE);
954
955 if (!HAS_PCH_SPLIT(dev))
956 for_each_pipe(pipe)
957 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
958
959 if (INTEL_INFO(dev)->gen >= 6) {
960 error->error = I915_READ(ERROR_GEN6);
961 error->done_reg = I915_READ(DONE_REG);
962 }
963
964 if (INTEL_INFO(dev)->gen == 7)
965 error->err_int = I915_READ(GEN7_ERR_INT);
966
967 i915_get_extra_instdone(dev, error->extra_instdone);
968
969 i915_gem_capture_buffers(dev_priv, error);
970 i915_gem_record_fences(dev, error);
971 i915_gem_record_rings(dev, error);
972
973 do_gettimeofday(&error->time);
974
975 error->overlay = intel_overlay_capture_error_state(dev);
976 error->display = intel_display_capture_error_state(dev);
977
978 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
979 if (dev_priv->gpu_error.first_error == NULL) {
980 dev_priv->gpu_error.first_error = error;
981 error = NULL;
982 }
983 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
984
985 if (error)
986 i915_error_state_free(&error->ref);
987}
988
989void i915_error_state_get(struct drm_device *dev,
990 struct i915_error_state_file_priv *error_priv)
991{
992 struct drm_i915_private *dev_priv = dev->dev_private;
993 unsigned long flags;
994
995 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
996 error_priv->error = dev_priv->gpu_error.first_error;
997 if (error_priv->error)
998 kref_get(&error_priv->error->ref);
999 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1000
1001}
1002
1003void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1004{
1005 if (error_priv->error)
1006 kref_put(&error_priv->error->ref, i915_error_state_free);
1007}
1008
1009void i915_destroy_error_state(struct drm_device *dev)
1010{
1011 struct drm_i915_private *dev_priv = dev->dev_private;
1012 struct drm_i915_error_state *error;
1013 unsigned long flags;
1014
1015 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1016 error = dev_priv->gpu_error.first_error;
1017 dev_priv->gpu_error.first_error = NULL;
1018 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1019
1020 if (error)
1021 kref_put(&error->ref, i915_error_state_free);
1022}
1023
1024const char *i915_cache_level_str(int type)
1025{
1026 switch (type) {
1027 case I915_CACHE_NONE: return " uncached";
350ec881
CW		 1028 case I915_CACHE_LLC: return " snooped or LLC";
1029 case I915_CACHE_L3_LLC: return " L3+LLC";
f56383cb 1030 case I915_CACHE_WT: return " WT";
84734a04
MK		 1031 default: return "";
1032 }
1033}
1034
1035/* NB: please notice the memset */
1036void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1037{
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1040
1041 switch (INTEL_INFO(dev)->gen) {
1042 case 2:
1043 case 3:
1044 instdone[0] = I915_READ(INSTDONE);
1045 break;
1046 case 4:
1047 case 5:
1048 case 6:
1049 instdone[0] = I915_READ(INSTDONE_I965);
1050 instdone[1] = I915_READ(INSTDONE1);
1051 break;
1052 default:
1053 WARN_ONCE(1, "Unsupported platform\n");
1054 case 7:
d0582ed2 1055 case 8:
84734a04
MK		 1056 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1057 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1058 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1059 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1060 break;
1061 }
1062}
Linux 6.x block layer and io_uring tree(s)