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drm/i915: warn when a vblank wait times out
[linux-block.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
33static const char *yesno(int v)
34{
35 return v ? "yes" : "no";
36}
37
38static const char *ring_str(int ring)
39{
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 default: return "";
46 }
47}
48
49static const char *pin_flag(int pinned)
50{
51 if (pinned > 0)
52 return " P";
53 else if (pinned < 0)
54 return " p";
55 else
56 return "";
57}
58
59static const char *tiling_flag(int tiling)
60{
61 switch (tiling) {
62 default:
63 case I915_TILING_NONE: return "";
64 case I915_TILING_X: return " X";
65 case I915_TILING_Y: return " Y";
66 }
67}
68
69static const char *dirty_flag(int dirty)
70{
71 return dirty ? " dirty" : "";
72}
73
74static const char *purgeable_flag(int purgeable)
75{
76 return purgeable ? " purgeable" : "";
77}
78
79static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
80{
81
82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
83 e->err = -ENOSPC;
84 return false;
85 }
86
87 if (e->bytes == e->size - 1 || e->err)
88 return false;
89
90 return true;
91}
92
93static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
94 unsigned len)
95{
96 if (e->pos + len <= e->start) {
97 e->pos += len;
98 return false;
99 }
100
101 /* First vsnprintf needs to fit in its entirety for memmove */
102 if (len >= e->size) {
103 e->err = -EIO;
104 return false;
105 }
106
107 return true;
108}
109
110static void __i915_error_advance(struct drm_i915_error_state_buf *e,
111 unsigned len)
112{
113 /* If this is first printf in this window, adjust it so that
114 * start position matches start of the buffer
115 */
116
117 if (e->pos < e->start) {
118 const size_t off = e->start - e->pos;
119
120 /* Should not happen but be paranoid */
121 if (off > len || e->bytes) {
122 e->err = -EIO;
123 return;
124 }
125
126 memmove(e->buf, e->buf + off, len - off);
127 e->bytes = len - off;
128 e->pos = e->start;
129 return;
130 }
131
132 e->bytes += len;
133 e->pos += len;
134}
135
136static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
137 const char *f, va_list args)
138{
139 unsigned len;
140
141 if (!__i915_error_ok(e))
142 return;
143
144 /* Seek the first printf which is hits start position */
145 if (e->pos < e->start) {
e29bb4eb
CW		 146 va_list tmp;
147
148 va_copy(tmp, args);
1d2cb9a5
MK		 149 len = vsnprintf(NULL, 0, f, tmp);
150 va_end(tmp);
151
152 if (!__i915_error_seek(e, len))
84734a04
MK		 153 return;
154 }
155
156 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
157 if (len >= e->size - e->bytes)
158 len = e->size - e->bytes - 1;
159
160 __i915_error_advance(e, len);
161}
162
163static void i915_error_puts(struct drm_i915_error_state_buf *e,
164 const char *str)
165{
166 unsigned len;
167
168 if (!__i915_error_ok(e))
169 return;
170
171 len = strlen(str);
172
173 /* Seek the first printf which is hits start position */
174 if (e->pos < e->start) {
175 if (!__i915_error_seek(e, len))
176 return;
177 }
178
179 if (len >= e->size - e->bytes)
180 len = e->size - e->bytes - 1;
181 memcpy(e->buf + e->bytes, str, len);
182
183 __i915_error_advance(e, len);
184}
185
186#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
187#define err_puts(e, s) i915_error_puts(e, s)
188
189static void print_error_buffers(struct drm_i915_error_state_buf *m,
190 const char *name,
191 struct drm_i915_error_buffer *err,
192 int count)
193{
194 err_printf(m, "%s [%d]:\n", name, count);
195
196 while (count--) {
197 err_printf(m, " %08x %8u %02x %02x %x %x",
198 err->gtt_offset,
199 err->size,
200 err->read_domains,
201 err->write_domain,
202 err->rseqno, err->wseqno);
203 err_puts(m, pin_flag(err->pinned));
204 err_puts(m, tiling_flag(err->tiling));
205 err_puts(m, dirty_flag(err->dirty));
206 err_puts(m, purgeable_flag(err->purgeable));
207 err_puts(m, err->ring != -1 ? " " : "");
208 err_puts(m, ring_str(err->ring));
209 err_puts(m, i915_cache_level_str(err->cache_level));
210
211 if (err->name)
212 err_printf(m, " (name: %d)", err->name);
213 if (err->fence_reg != I915_FENCE_REG_NONE)
214 err_printf(m, " (fence: %d)", err->fence_reg);
215
216 err_puts(m, "\n");
217 err++;
218 }
219}
220
da661464
MK		 221static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
222{
223 switch (a) {
224 case HANGCHECK_IDLE:
225 return "idle";
226 case HANGCHECK_WAIT:
227 return "wait";
228 case HANGCHECK_ACTIVE:
229 return "active";
230 case HANGCHECK_KICK:
231 return "kick";
232 case HANGCHECK_HUNG:
233 return "hung";
234 }
235
236 return "unknown";
237}
238
84734a04
MK		 239static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
240 struct drm_device *dev,
362b8af7 241 struct drm_i915_error_ring *ring)
84734a04 242{
362b8af7 243 if (!ring->valid)
372fbb8e
CW		 244 return;
245
362b8af7
BW		 246 err_printf(m, " HEAD: 0x%08x\n", ring->head);
247 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
248 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
249 err_printf(m, " HWS: 0x%08x\n", ring->hws);
e3243d16 250 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
362b8af7
BW		 251 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
252 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
253 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
3dda20a9 254 if (INTEL_INFO(dev)->gen >= 4) {
e3243d16 255 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
362b8af7
BW		 256 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
257 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
3dda20a9 258 }
362b8af7 259 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
13ffadd1
BW		 260 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
261 lower_32_bits(ring->faddr));
84734a04 262 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 263 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
264 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
84734a04 265 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 266 ring->semaphore_mboxes[0],
267 ring->semaphore_seqno[0]);
84734a04 268 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 269 ring->semaphore_mboxes[1],
270 ring->semaphore_seqno[1]);
4e5aabfd
BW		 271 if (HAS_VEBOX(dev)) {
272 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 273 ring->semaphore_mboxes[2],
274 ring->semaphore_seqno[2]);
4e5aabfd 275 }
84734a04 276 }
6c7a01ec
BW		 277 if (USES_PPGTT(dev)) {
278 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
279
280 if (INTEL_INFO(dev)->gen >= 8) {
281 int i;
282 for (i = 0; i < 4; i++)
283 err_printf(m, " PDP%d: 0x%016llx\n",
284 i, ring->vm_info.pdp[i]);
285 } else {
286 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
287 ring->vm_info.pp_dir_base);
288 }
289 }
362b8af7
BW		 290 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
291 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
292 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
293 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
da661464 294 err_printf(m, " hangcheck: %s [%d]\n",
362b8af7
BW		 295 hangcheck_action_to_str(ring->hangcheck_action),
296 ring->hangcheck_score);
84734a04
MK		 297}
298
299void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
300{
301 va_list args;
302
303 va_start(args, f);
304 i915_error_vprintf(e, f, args);
305 va_end(args);
306}
307
ab0e7ff9
CW		 308static void print_error_obj(struct drm_i915_error_state_buf *m,
309 struct drm_i915_error_object *obj)
310{
311 int page, offset, elt;
312
313 for (page = offset = 0; page < obj->page_count; page++) {
314 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
315 err_printf(m, "%08x : %08x\n", offset,
316 obj->pages[page][elt]);
317 offset += 4;
318 }
319 }
320}
321
84734a04
MK		 322int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
323 const struct i915_error_state_file_priv *error_priv)
324{
325 struct drm_device *dev = error_priv->dev;
50227e1c 326 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04 327 struct drm_i915_error_state *error = error_priv->error;
ab0e7ff9
CW		 328 int i, j, offset, elt;
329 int max_hangcheck_score;
84734a04
MK		 330
331 if (!error) {
332 err_printf(m, "no error state collected\n");
333 goto out;
334 }
335
cb383002 336 err_printf(m, "%s\n", error->error_msg);
84734a04
MK		 337 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
338 error->time.tv_usec);
339 err_printf(m, "Kernel: " UTS_RELEASE "\n");
ab0e7ff9
CW		 340 max_hangcheck_score = 0;
341 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
342 if (error->ring[i].hangcheck_score > max_hangcheck_score)
343 max_hangcheck_score = error->ring[i].hangcheck_score;
344 }
345 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
346 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
347 error->ring[i].pid != -1) {
348 err_printf(m, "Active process (on ring %s): %s [%d]\n",
349 ring_str(i),
350 error->ring[i].comm,
351 error->ring[i].pid);
352 }
353 }
48b031e3 354 err_printf(m, "Reset count: %u\n", error->reset_count);
62d5d69b 355 err_printf(m, "Suspend count: %u\n", error->suspend_count);
ffbab09b 356 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
84734a04
MK		 357 err_printf(m, "EIR: 0x%08x\n", error->eir);
358 err_printf(m, "IER: 0x%08x\n", error->ier);
359 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
360 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
361 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
362 err_printf(m, "CCID: 0x%08x\n", error->ccid);
094f9a54 363 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
84734a04
MK		 364
365 for (i = 0; i < dev_priv->num_fence_regs; i++)
366 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
367
368 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
369 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
370 error->extra_instdone[i]);
371
372 if (INTEL_INFO(dev)->gen >= 6) {
373 err_printf(m, "ERROR: 0x%08x\n", error->error);
374 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
375 }
376
377 if (INTEL_INFO(dev)->gen == 7)
378 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
379
362b8af7
BW		 380 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
381 err_printf(m, "%s command stream:\n", ring_str(i));
382 i915_ring_error_state(m, dev, &error->ring[i]);
383 }
84734a04
MK		 384
385 if (error->active_bo)
386 print_error_buffers(m, "Active",
95f5301d
BW		 387 error->active_bo[0],
388 error->active_bo_count[0]);
84734a04
MK		 389
390 if (error->pinned_bo)
391 print_error_buffers(m, "Pinned",
95f5301d
BW		 392 error->pinned_bo[0],
393 error->pinned_bo_count[0]);
84734a04
MK		 394
395 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
396 struct drm_i915_error_object *obj;
397
ab0e7ff9
CW		 398 obj = error->ring[i].batchbuffer;
399 if (obj) {
400 err_puts(m, dev_priv->ring[i].name);
401 if (error->ring[i].pid != -1)
402 err_printf(m, " (submitted by %s [%d])",
403 error->ring[i].comm,
404 error->ring[i].pid);
405 err_printf(m, " --- gtt_offset = 0x%08x\n",
84734a04 406 obj->gtt_offset);
ab0e7ff9
CW		 407 print_error_obj(m, obj);
408 }
409
410 obj = error->ring[i].wa_batchbuffer;
411 if (obj) {
412 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
413 dev_priv->ring[i].name, obj->gtt_offset);
414 print_error_obj(m, obj);
84734a04
MK		 415 }
416
417 if (error->ring[i].num_requests) {
418 err_printf(m, "%s --- %d requests\n",
419 dev_priv->ring[i].name,
420 error->ring[i].num_requests);
421 for (j = 0; j < error->ring[i].num_requests; j++) {
422 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
423 error->ring[i].requests[j].seqno,
424 error->ring[i].requests[j].jiffies,
425 error->ring[i].requests[j].tail);
426 }
427 }
428
429 if ((obj = error->ring[i].ringbuffer)) {
430 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
431 dev_priv->ring[i].name,
432 obj->gtt_offset);
ab0e7ff9 433 print_error_obj(m, obj);
84734a04
MK		 434 }
435
362b8af7 436 if ((obj = error->ring[i].hws_page)) {
f3ce3821
CW		 437 err_printf(m, "%s --- HW Status = 0x%08x\n",
438 dev_priv->ring[i].name,
439 obj->gtt_offset);
440 offset = 0;
441 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
442 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
443 offset,
444 obj->pages[0][elt],
445 obj->pages[0][elt+1],
446 obj->pages[0][elt+2],
447 obj->pages[0][elt+3]);
448 offset += 16;
449 }
450 }
451
372fbb8e 452 if ((obj = error->ring[i].ctx)) {
84734a04
MK		 453 err_printf(m, "%s --- HW Context = 0x%08x\n",
454 dev_priv->ring[i].name,
455 obj->gtt_offset);
456 offset = 0;
457 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
458 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
459 offset,
460 obj->pages[0][elt],
461 obj->pages[0][elt+1],
462 obj->pages[0][elt+2],
463 obj->pages[0][elt+3]);
464 offset += 16;
465 }
466 }
467 }
468
469 if (error->overlay)
470 intel_overlay_print_error_state(m, error->overlay);
471
472 if (error->display)
473 intel_display_print_error_state(m, dev, error->display);
474
475out:
476 if (m->bytes == 0 && m->err)
477 return m->err;
478
479 return 0;
480}
481
482int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
483 size_t count, loff_t pos)
484{
485 memset(ebuf, 0, sizeof(*ebuf));
486
487 /* We need to have enough room to store any i915_error_state printf
488 * so that we can move it to start position.
489 */
490 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
491 ebuf->buf = kmalloc(ebuf->size,
492 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
493
494 if (ebuf->buf == NULL) {
495 ebuf->size = PAGE_SIZE;
496 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
497 }
498
499 if (ebuf->buf == NULL) {
500 ebuf->size = 128;
501 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
502 }
503
504 if (ebuf->buf == NULL)
505 return -ENOMEM;
506
507 ebuf->start = pos;
508
509 return 0;
510}
511
512static void i915_error_object_free(struct drm_i915_error_object *obj)
513{
514 int page;
515
516 if (obj == NULL)
517 return;
518
519 for (page = 0; page < obj->page_count; page++)
520 kfree(obj->pages[page]);
521
522 kfree(obj);
523}
524
525static void i915_error_state_free(struct kref *error_ref)
526{
527 struct drm_i915_error_state *error = container_of(error_ref,
528 typeof(*error), ref);
529 int i;
530
531 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
532 i915_error_object_free(error->ring[i].batchbuffer);
533 i915_error_object_free(error->ring[i].ringbuffer);
362b8af7 534 i915_error_object_free(error->ring[i].hws_page);
84734a04
MK		 535 i915_error_object_free(error->ring[i].ctx);
536 kfree(error->ring[i].requests);
537 }
538
539 kfree(error->active_bo);
540 kfree(error->overlay);
541 kfree(error->display);
542 kfree(error);
543}
544
545static struct drm_i915_error_object *
546i915_error_object_create_sized(struct drm_i915_private *dev_priv,
547 struct drm_i915_gem_object *src,
a7b91078 548 struct i915_address_space *vm,
84734a04
MK		 549 const int num_pages)
550{
551 struct drm_i915_error_object *dst;
552 int i;
553 u32 reloc_offset;
554
555 if (src == NULL || src->pages == NULL)
556 return NULL;
557
558 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
559 if (dst == NULL)
560 return NULL;
561
a7b91078 562 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
84734a04
MK		 563 for (i = 0; i < num_pages; i++) {
564 unsigned long flags;
565 void *d;
566
567 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
568 if (d == NULL)
569 goto unwind;
570
571 local_irq_save(flags);
8b6124a6
CW		 572 if (src->cache_level == I915_CACHE_NONE &&
573 reloc_offset < dev_priv->gtt.mappable_end &&
496bfcb9
BW		 574 src->has_global_gtt_mapping &&
575 i915_is_ggtt(vm)) {
84734a04
MK		 576 void __iomem *s;
577
578 /* Simply ignore tiling or any overlapping fence.
579 * It's part of the error state, and this hopefully
580 * captures what the GPU read.
581 */
582
583 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
584 reloc_offset);
585 memcpy_fromio(d, s, PAGE_SIZE);
586 io_mapping_unmap_atomic(s);
587 } else if (src->stolen) {
588 unsigned long offset;
589
590 offset = dev_priv->mm.stolen_base;
591 offset += src->stolen->start;
592 offset += i << PAGE_SHIFT;
593
594 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
595 } else {
596 struct page *page;
597 void *s;
598
599 page = i915_gem_object_get_page(src, i);
600
601 drm_clflush_pages(&page, 1);
602
603 s = kmap_atomic(page);
604 memcpy(d, s, PAGE_SIZE);
605 kunmap_atomic(s);
606
607 drm_clflush_pages(&page, 1);
608 }
609 local_irq_restore(flags);
610
611 dst->pages[i] = d;
612
613 reloc_offset += PAGE_SIZE;
614 }
615 dst->page_count = num_pages;
616
617 return dst;
618
619unwind:
620 while (i--)
621 kfree(dst->pages[i]);
622 kfree(dst);
623 return NULL;
624}
a7b91078
BW		 625#define i915_error_object_create(dev_priv, src, vm) \
626 i915_error_object_create_sized((dev_priv), (src), (vm), \
627 (src)->base.size>>PAGE_SHIFT)
628
629#define i915_error_ggtt_object_create(dev_priv, src) \
630 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
84734a04
MK		 631 (src)->base.size>>PAGE_SHIFT)
632
633static void capture_bo(struct drm_i915_error_buffer *err,
634 struct drm_i915_gem_object *obj)
635{
636 err->size = obj->base.size;
637 err->name = obj->base.name;
638 err->rseqno = obj->last_read_seqno;
639 err->wseqno = obj->last_write_seqno;
640 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
641 err->read_domains = obj->base.read_domains;
642 err->write_domain = obj->base.write_domain;
643 err->fence_reg = obj->fence_reg;
644 err->pinned = 0;
d7f46fc4 645 if (i915_gem_obj_is_pinned(obj))
84734a04
MK		 646 err->pinned = 1;
647 if (obj->user_pin_count > 0)
648 err->pinned = -1;
649 err->tiling = obj->tiling_mode;
650 err->dirty = obj->dirty;
651 err->purgeable = obj->madv != I915_MADV_WILLNEED;
652 err->ring = obj->ring ? obj->ring->id : -1;
653 err->cache_level = obj->cache_level;
654}
655
656static u32 capture_active_bo(struct drm_i915_error_buffer *err,
657 int count, struct list_head *head)
658{
ca191b13 659 struct i915_vma *vma;
84734a04
MK		 660 int i = 0;
661
ca191b13
BW		 662 list_for_each_entry(vma, head, mm_list) {
663 capture_bo(err++, vma->obj);
84734a04
MK		 664 if (++i == count)
665 break;
666 }
667
668 return i;
669}
670
671static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
672 int count, struct list_head *head)
673{
674 struct drm_i915_gem_object *obj;
675 int i = 0;
676
677 list_for_each_entry(obj, head, global_list) {
d7f46fc4 678 if (!i915_gem_obj_is_pinned(obj))
84734a04
MK		 679 continue;
680
681 capture_bo(err++, obj);
682 if (++i == count)
683 break;
684 }
685
686 return i;
687}
688
011cf577
BW		 689/* Generate a semi-unique error code. The code is not meant to have meaning, The
690 * code's only purpose is to try to prevent false duplicated bug reports by
691 * grossly estimating a GPU error state.
692 *
693 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
694 * the hang if we could strip the GTT offset information from it.
695 *
696 * It's only a small step better than a random number in its current form.
697 */
698static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
cb383002
MK		 699 struct drm_i915_error_state *error,
700 int *ring_id)
011cf577
BW		 701{
702 uint32_t error_code = 0;
703 int i;
704
705 /* IPEHR would be an ideal way to detect errors, as it's the gross
706 * measure of "the command that hung." However, has some very common
707 * synchronization commands which almost always appear in the case
708 * strictly a client bug. Use instdone to differentiate those some.
709 */
cb383002
MK		 710 for (i = 0; i < I915_NUM_RINGS; i++) {
711 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
712 if (ring_id)
713 *ring_id = i;
714
011cf577 715 return error->ring[i].ipehr ^ error->ring[i].instdone;
cb383002
MK		 716 }
717 }
011cf577
BW		 718
719 return error_code;
720}
721
84734a04
MK		 722static void i915_gem_record_fences(struct drm_device *dev,
723 struct drm_i915_error_state *error)
724{
725 struct drm_i915_private *dev_priv = dev->dev_private;
726 int i;
727
728 /* Fences */
729 switch (INTEL_INFO(dev)->gen) {
5ab31333 730 case 8:
84734a04
MK		 731 case 7:
732 case 6:
733 for (i = 0; i < dev_priv->num_fence_regs; i++)
734 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
735 break;
736 case 5:
737 case 4:
738 for (i = 0; i < 16; i++)
739 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
740 break;
741 case 3:
742 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
743 for (i = 0; i < 8; i++)
744 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
745 case 2:
746 for (i = 0; i < 8; i++)
747 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
748 break;
749
750 default:
751 BUG();
752 }
753}
754
84734a04 755static void i915_record_ring_state(struct drm_device *dev,
362b8af7
BW		 756 struct intel_ring_buffer *ring,
757 struct drm_i915_error_ring *ering)
84734a04
MK		 758{
759 struct drm_i915_private *dev_priv = dev->dev_private;
760
761 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 762 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
763 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
764 ering->semaphore_mboxes[0]
84734a04 765 = I915_READ(RING_SYNC_0(ring->mmio_base));
362b8af7 766 ering->semaphore_mboxes[1]
84734a04 767 = I915_READ(RING_SYNC_1(ring->mmio_base));
362b8af7
BW		 768 ering->semaphore_seqno[0] = ring->sync_seqno[0];
769 ering->semaphore_seqno[1] = ring->sync_seqno[1];
84734a04
MK		 770 }
771
4e5aabfd 772 if (HAS_VEBOX(dev)) {
362b8af7 773 ering->semaphore_mboxes[2] =
4e5aabfd 774 I915_READ(RING_SYNC_2(ring->mmio_base));
362b8af7 775 ering->semaphore_seqno[2] = ring->sync_seqno[2];
4e5aabfd
BW		 776 }
777
84734a04 778 if (INTEL_INFO(dev)->gen >= 4) {
362b8af7
BW		 779 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
780 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
781 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
782 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
783 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
784 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
13ffadd1
BW		 785 if (INTEL_INFO(dev)->gen >= 8) {
786 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
362b8af7 787 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
13ffadd1 788 }
362b8af7 789 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
84734a04 790 } else {
362b8af7
BW		 791 ering->faddr = I915_READ(DMA_FADD_I8XX);
792 ering->ipeir = I915_READ(IPEIR);
793 ering->ipehr = I915_READ(IPEHR);
794 ering->instdone = I915_READ(INSTDONE);
84734a04
MK		 795 }
796
362b8af7
BW		 797 ering->waiting = waitqueue_active(&ring->irq_queue);
798 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
799 ering->seqno = ring->get_seqno(ring, false);
800 ering->acthd = intel_ring_get_active_head(ring);
801 ering->head = I915_READ_HEAD(ring);
802 ering->tail = I915_READ_TAIL(ring);
803 ering->ctl = I915_READ_CTL(ring);
84734a04 804
f3ce3821
CW		 805 if (I915_NEED_GFX_HWS(dev)) {
806 int mmio;
807
808 if (IS_GEN7(dev)) {
809 switch (ring->id) {
810 default:
811 case RCS:
812 mmio = RENDER_HWS_PGA_GEN7;
813 break;
814 case BCS:
815 mmio = BLT_HWS_PGA_GEN7;
816 break;
817 case VCS:
818 mmio = BSD_HWS_PGA_GEN7;
819 break;
820 case VECS:
821 mmio = VEBOX_HWS_PGA_GEN7;
822 break;
823 }
824 } else if (IS_GEN6(ring->dev)) {
825 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
826 } else {
827 /* XXX: gen8 returns to sanity */
828 mmio = RING_HWS_PGA(ring->mmio_base);
829 }
830
362b8af7 831 ering->hws = I915_READ(mmio);
f3ce3821
CW		 832 }
833
362b8af7
BW		 834 ering->cpu_ring_head = ring->head;
835 ering->cpu_ring_tail = ring->tail;
da661464 836
362b8af7
BW		 837 ering->hangcheck_score = ring->hangcheck.score;
838 ering->hangcheck_action = ring->hangcheck.action;
6c7a01ec
BW		 839
840 if (USES_PPGTT(dev)) {
841 int i;
842
843 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
844
845 switch (INTEL_INFO(dev)->gen) {
846 case 8:
847 for (i = 0; i < 4; i++) {
848 ering->vm_info.pdp[i] =
849 I915_READ(GEN8_RING_PDP_UDW(ring, i));
850 ering->vm_info.pdp[i] <<= 32;
851 ering->vm_info.pdp[i] |=
852 I915_READ(GEN8_RING_PDP_LDW(ring, i));
853 }
854 break;
855 case 7:
ae89f44d
BW		 856 ering->vm_info.pp_dir_base =
857 I915_READ(RING_PP_DIR_BASE(ring));
6c7a01ec
BW		 858 break;
859 case 6:
ae89f44d
BW		 860 ering->vm_info.pp_dir_base =
861 I915_READ(RING_PP_DIR_BASE_READ(ring));
6c7a01ec
BW		 862 break;
863 }
864 }
84734a04
MK		 865}
866
867
868static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
869 struct drm_i915_error_state *error,
870 struct drm_i915_error_ring *ering)
871{
872 struct drm_i915_private *dev_priv = ring->dev->dev_private;
873 struct drm_i915_gem_object *obj;
874
875 /* Currently render ring is the only HW context user */
876 if (ring->id != RCS || !error->ccid)
877 return;
878
879 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
880 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
881 ering->ctx = i915_error_object_create_sized(dev_priv,
a7b91078
BW		 882 obj,
883 &dev_priv->gtt.base,
884 1);
84734a04
MK		 885 break;
886 }
887 }
888}
889
890static void i915_gem_record_rings(struct drm_device *dev,
891 struct drm_i915_error_state *error)
892{
893 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04
MK		 894 struct drm_i915_gem_request *request;
895 int i, count;
896
372fbb8e
CW		 897 for (i = 0; i < I915_NUM_RINGS; i++) {
898 struct intel_ring_buffer *ring = &dev_priv->ring[i];
899
900 if (ring->dev == NULL)
901 continue;
902
903 error->ring[i].valid = true;
904
362b8af7 905 i915_record_ring_state(dev, ring, &error->ring[i]);
84734a04 906
ab0e7ff9
CW		 907 error->ring[i].pid = -1;
908 request = i915_gem_find_active_request(ring);
909 if (request) {
910 /* We need to copy these to an anonymous buffer
911 * as the simplest method to avoid being overwritten
912 * by userspace.
913 */
914 error->ring[i].batchbuffer =
915 i915_error_object_create(dev_priv,
916 request->batch_obj,
917 request->ctx ?
918 request->ctx->vm :
919 &dev_priv->gtt.base);
920
921 if (HAS_BROKEN_CS_TLB(dev_priv->dev) &&
922 ring->scratch.obj)
923 error->ring[i].wa_batchbuffer =
924 i915_error_ggtt_object_create(dev_priv,
925 ring->scratch.obj);
926
927 if (request->file_priv) {
928 struct task_struct *task;
929
930 rcu_read_lock();
931 task = pid_task(request->file_priv->file->pid,
932 PIDTYPE_PID);
933 if (task) {
934 strcpy(error->ring[i].comm, task->comm);
935 error->ring[i].pid = task->pid;
936 }
937 rcu_read_unlock();
938 }
939 }
84734a04
MK		 940
941 error->ring[i].ringbuffer =
a7b91078 942 i915_error_ggtt_object_create(dev_priv, ring->obj);
84734a04 943
f3ce3821 944 if (ring->status_page.obj)
362b8af7 945 error->ring[i].hws_page =
f3ce3821 946 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
84734a04
MK		 947
948 i915_gem_record_active_context(ring, error, &error->ring[i]);
949
950 count = 0;
951 list_for_each_entry(request, &ring->request_list, list)
952 count++;
953
954 error->ring[i].num_requests = count;
955 error->ring[i].requests =
a1e22653 956 kcalloc(count, sizeof(*error->ring[i].requests),
84734a04
MK		 957 GFP_ATOMIC);
958 if (error->ring[i].requests == NULL) {
959 error->ring[i].num_requests = 0;
960 continue;
961 }
962
963 count = 0;
964 list_for_each_entry(request, &ring->request_list, list) {
965 struct drm_i915_error_request *erq;
966
967 erq = &error->ring[i].requests[count++];
968 erq->seqno = request->seqno;
969 erq->jiffies = request->emitted_jiffies;
970 erq->tail = request->tail;
971 }
972 }
973}
974
95f5301d
BW		 975/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
976 * VM.
977 */
978static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
979 struct drm_i915_error_state *error,
980 struct i915_address_space *vm,
981 const int ndx)
84734a04 982{
95f5301d 983 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
84734a04 984 struct drm_i915_gem_object *obj;
95f5301d 985 struct i915_vma *vma;
84734a04
MK		 986 int i;
987
988 i = 0;
ca191b13 989 list_for_each_entry(vma, &vm->active_list, mm_list)
84734a04 990 i++;
95f5301d 991 error->active_bo_count[ndx] = i;
84734a04 992 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
d7f46fc4 993 if (i915_gem_obj_is_pinned(obj))
84734a04 994 i++;
95f5301d 995 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
84734a04
MK		 996
997 if (i) {
a1e22653 998 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
95f5301d
BW		 999 if (active_bo)
1000 pinned_bo = active_bo + error->active_bo_count[ndx];
84734a04
MK		 1001 }
1002
95f5301d
BW		 1003 if (active_bo)
1004 error->active_bo_count[ndx] =
1005 capture_active_bo(active_bo,
1006 error->active_bo_count[ndx],
5cef07e1 1007 &vm->active_list);
84734a04 1008
95f5301d
BW		 1009 if (pinned_bo)
1010 error->pinned_bo_count[ndx] =
1011 capture_pinned_bo(pinned_bo,
1012 error->pinned_bo_count[ndx],
84734a04 1013 &dev_priv->mm.bound_list);
95f5301d
BW		 1014 error->active_bo[ndx] = active_bo;
1015 error->pinned_bo[ndx] = pinned_bo;
1016}
1017
1018static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1019 struct drm_i915_error_state *error)
1020{
1021 struct i915_address_space *vm;
1022 int cnt = 0, i = 0;
1023
1024 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1025 cnt++;
1026
95f5301d
BW		 1027 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1028 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1029 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1030 GFP_ATOMIC);
1031 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1032 GFP_ATOMIC);
1033
1034 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1035 i915_gem_capture_vm(dev_priv, error, vm, i++);
84734a04
MK		 1036}
1037
1d762aad
BW		 1038/* Capture all registers which don't fit into another category. */
1039static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1040 struct drm_i915_error_state *error)
84734a04 1041{
1d762aad 1042 struct drm_device *dev = dev_priv->dev;
84734a04
MK		 1043 int pipe;
1044
654c90c6
BW		 1045 /* General organization
1046 * 1. Registers specific to a single generation
1047 * 2. Registers which belong to multiple generations
1048 * 3. Feature specific registers.
1049 * 4. Everything else
1050 * Please try to follow the order.
1051 */
84734a04 1052
654c90c6
BW		 1053 /* 1: Registers specific to a single generation */
1054 if (IS_VALLEYVIEW(dev)) {
84734a04 1055 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
654c90c6
BW		 1056 error->forcewake = I915_READ(FORCEWAKE_VLV);
1057 }
84734a04 1058
654c90c6
BW		 1059 if (IS_GEN7(dev))
1060 error->err_int = I915_READ(GEN7_ERR_INT);
84734a04 1061
91ec5d11 1062 if (IS_GEN6(dev)) {
84734a04 1063 error->forcewake = I915_READ(FORCEWAKE);
91ec5d11
BW		 1064 error->gab_ctl = I915_READ(GAB_CTL);
1065 error->gfx_mode = I915_READ(GFX_MODE);
1066 }
84734a04 1067
654c90c6
BW		 1068 if (IS_GEN2(dev))
1069 error->ier = I915_READ16(IER);
1070
1071 /* 2: Registers which belong to multiple generations */
1072 if (INTEL_INFO(dev)->gen >= 7)
1073 error->forcewake = I915_READ(FORCEWAKE_MT);
84734a04
MK		 1074
1075 if (INTEL_INFO(dev)->gen >= 6) {
654c90c6 1076 error->derrmr = I915_READ(DERRMR);
84734a04
MK		 1077 error->error = I915_READ(ERROR_GEN6);
1078 error->done_reg = I915_READ(DONE_REG);
1079 }
1080
654c90c6 1081 /* 3: Feature specific registers */
91ec5d11
BW		 1082 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1083 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1084 error->gac_eco = I915_READ(GAC_ECO_BITS);
1085 }
1086
1087 /* 4: Everything else */
654c90c6
BW		 1088 if (HAS_HW_CONTEXTS(dev))
1089 error->ccid = I915_READ(CCID);
1090
1091 if (HAS_PCH_SPLIT(dev))
1092 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1093 else {
1094 error->ier = I915_READ(IER);
1095 for_each_pipe(pipe)
1096 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1097 }
1098
1099 /* 4: Everything else */
1100 error->eir = I915_READ(EIR);
1101 error->pgtbl_er = I915_READ(PGTBL_ER);
84734a04
MK		 1102
1103 i915_get_extra_instdone(dev, error->extra_instdone);
1d762aad
BW		 1104}
1105
cb383002 1106static void i915_error_capture_msg(struct drm_device *dev,
58174462
MK		 1107 struct drm_i915_error_state *error,
1108 bool wedged,
1109 const char *error_msg)
cb383002
MK		 1110{
1111 struct drm_i915_private *dev_priv = dev->dev_private;
1112 u32 ecode;
58174462 1113 int ring_id = -1, len;
cb383002
MK		 1114
1115 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1116
58174462
MK		 1117 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1118 "GPU HANG: ecode %d:0x%08x", ring_id, ecode);
1119
1120 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1121 len += scnprintf(error->error_msg + len,
1122 sizeof(error->error_msg) - len,
1123 ", in %s [%d]",
1124 error->ring[ring_id].comm,
1125 error->ring[ring_id].pid);
1126
1127 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1128 ", reason: %s, action: %s",
1129 error_msg,
1130 wedged ? "reset" : "continue");
cb383002
MK		 1131}
1132
48b031e3
MK		 1133static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1134 struct drm_i915_error_state *error)
1135{
1136 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
62d5d69b 1137 error->suspend_count = dev_priv->suspend_count;
48b031e3
MK		 1138}
1139
1d762aad
BW		 1140/**
1141 * i915_capture_error_state - capture an error record for later analysis
1142 * @dev: drm device
1143 *
1144 * Should be called when an error is detected (either a hang or an error
1145 * interrupt) to capture error state from the time of the error. Fills
1146 * out a structure which becomes available in debugfs for user level tools
1147 * to pick up.
1148 */
58174462
MK		 1149void i915_capture_error_state(struct drm_device *dev, bool wedged,
1150 const char *error_msg)
1d762aad 1151{
53a4c6b2 1152 static bool warned;
1d762aad
BW		 1153 struct drm_i915_private *dev_priv = dev->dev_private;
1154 struct drm_i915_error_state *error;
1155 unsigned long flags;
1d762aad
BW		 1156
1157 /* Account for pipe specific data like PIPE*STAT */
1158 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1159 if (!error) {
1160 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1161 return;
1162 }
1163
011cf577
BW		 1164 kref_init(&error->ref);
1165
48b031e3 1166 i915_capture_gen_state(dev_priv, error);
011cf577
BW		 1167 i915_capture_reg_state(dev_priv, error);
1168 i915_gem_capture_buffers(dev_priv, error);
1169 i915_gem_record_fences(dev, error);
1170 i915_gem_record_rings(dev, error);
1d762aad 1171
84734a04
MK		 1172 do_gettimeofday(&error->time);
1173
1174 error->overlay = intel_overlay_capture_error_state(dev);
1175 error->display = intel_display_capture_error_state(dev);
1176
58174462 1177 i915_error_capture_msg(dev, error, wedged, error_msg);
cb383002
MK		 1178 DRM_INFO("%s\n", error->error_msg);
1179
84734a04
MK		 1180 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1181 if (dev_priv->gpu_error.first_error == NULL) {
1182 dev_priv->gpu_error.first_error = error;
1183 error = NULL;
1184 }
1185 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1186
cb383002 1187 if (error) {
84734a04 1188 i915_error_state_free(&error->ref);
cb383002
MK		 1189 return;
1190 }
1191
1192 if (!warned) {
1193 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1194 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1195 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1196 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1197 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1198 warned = true;
1199 }
84734a04
MK		 1200}
1201
1202void i915_error_state_get(struct drm_device *dev,
1203 struct i915_error_state_file_priv *error_priv)
1204{
1205 struct drm_i915_private *dev_priv = dev->dev_private;
1206 unsigned long flags;
1207
1208 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1209 error_priv->error = dev_priv->gpu_error.first_error;
1210 if (error_priv->error)
1211 kref_get(&error_priv->error->ref);
1212 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1213
1214}
1215
1216void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1217{
1218 if (error_priv->error)
1219 kref_put(&error_priv->error->ref, i915_error_state_free);
1220}
1221
1222void i915_destroy_error_state(struct drm_device *dev)
1223{
1224 struct drm_i915_private *dev_priv = dev->dev_private;
1225 struct drm_i915_error_state *error;
1226 unsigned long flags;
1227
1228 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1229 error = dev_priv->gpu_error.first_error;
1230 dev_priv->gpu_error.first_error = NULL;
1231 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1232
1233 if (error)
1234 kref_put(&error->ref, i915_error_state_free);
1235}
1236
1237const char *i915_cache_level_str(int type)
1238{
1239 switch (type) {
1240 case I915_CACHE_NONE: return " uncached";
350ec881
CW		 1241 case I915_CACHE_LLC: return " snooped or LLC";
1242 case I915_CACHE_L3_LLC: return " L3+LLC";
f56383cb 1243 case I915_CACHE_WT: return " WT";
84734a04
MK		 1244 default: return "";
1245 }
1246}
1247
1248/* NB: please notice the memset */
1249void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1250{
1251 struct drm_i915_private *dev_priv = dev->dev_private;
1252 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1253
1254 switch (INTEL_INFO(dev)->gen) {
1255 case 2:
1256 case 3:
1257 instdone[0] = I915_READ(INSTDONE);
1258 break;
1259 case 4:
1260 case 5:
1261 case 6:
1262 instdone[0] = I915_READ(INSTDONE_I965);
1263 instdone[1] = I915_READ(INSTDONE1);
1264 break;
1265 default:
1266 WARN_ONCE(1, "Unsupported platform\n");
1267 case 7:
d0582ed2 1268 case 8:
84734a04
MK		 1269 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1270 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1271 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1272 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1273 break;
1274 }
1275}
Linux 6.x block layer and io_uring tree(s)