Commit | Line | Data |
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84734a04 MK |
1 | /* |
2 | * Copyright (c) 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * Mika Kuoppala <mika.kuoppala@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
0e39037b CW |
30 | #include <linux/ascii85.h> |
31 | #include <linux/nmi.h> | |
32 | #include <linux/scatterlist.h> | |
9f267eb8 | 33 | #include <linux/stop_machine.h> |
0e39037b | 34 | #include <linux/utsname.h> |
0a97015d | 35 | #include <linux/zlib.h> |
0e39037b | 36 | |
7d41ef34 MW |
37 | #include <drm/drm_print.h> |
38 | ||
d897a111 | 39 | #include "i915_gpu_error.h" |
84734a04 MK |
40 | #include "i915_drv.h" |
41 | ||
1edf6958 MT |
42 | static inline const struct intel_engine_cs * |
43 | engine_lookup(const struct drm_i915_private *i915, unsigned int id) | |
44 | { | |
45 | if (id >= I915_NUM_ENGINES) | |
46 | return NULL; | |
47 | ||
48 | return i915->engine[id]; | |
49 | } | |
50 | ||
51 | static inline const char * | |
52 | __engine_name(const struct intel_engine_cs *engine) | |
53 | { | |
54 | return engine ? engine->name : ""; | |
55 | } | |
56 | ||
57 | static const char * | |
58 | engine_name(const struct drm_i915_private *i915, unsigned int id) | |
59 | { | |
60 | return __engine_name(engine_lookup(i915, id)); | |
84734a04 MK |
61 | } |
62 | ||
84734a04 MK |
63 | static const char *tiling_flag(int tiling) |
64 | { | |
65 | switch (tiling) { | |
66 | default: | |
67 | case I915_TILING_NONE: return ""; | |
68 | case I915_TILING_X: return " X"; | |
69 | case I915_TILING_Y: return " Y"; | |
70 | } | |
71 | } | |
72 | ||
73 | static const char *dirty_flag(int dirty) | |
74 | { | |
75 | return dirty ? " dirty" : ""; | |
76 | } | |
77 | ||
78 | static const char *purgeable_flag(int purgeable) | |
79 | { | |
80 | return purgeable ? " purgeable" : ""; | |
81 | } | |
82 | ||
0e39037b CW |
83 | static void __sg_set_buf(struct scatterlist *sg, |
84 | void *addr, unsigned int len, loff_t it) | |
84734a04 | 85 | { |
0e39037b CW |
86 | sg->page_link = (unsigned long)virt_to_page(addr); |
87 | sg->offset = offset_in_page(addr); | |
88 | sg->length = len; | |
89 | sg->dma_address = it; | |
84734a04 MK |
90 | } |
91 | ||
0e39037b | 92 | static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) |
84734a04 | 93 | { |
0e39037b | 94 | if (!len) |
84734a04 | 95 | return false; |
84734a04 | 96 | |
0e39037b CW |
97 | if (e->bytes + len + 1 <= e->size) |
98 | return true; | |
99 | ||
100 | if (e->bytes) { | |
101 | __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); | |
102 | e->iter += e->bytes; | |
103 | e->buf = NULL; | |
104 | e->bytes = 0; | |
84734a04 MK |
105 | } |
106 | ||
0e39037b CW |
107 | if (e->cur == e->end) { |
108 | struct scatterlist *sgl; | |
84734a04 | 109 | |
0e39037b CW |
110 | sgl = (typeof(sgl))__get_free_page(GFP_KERNEL); |
111 | if (!sgl) { | |
112 | e->err = -ENOMEM; | |
113 | return false; | |
114 | } | |
84734a04 | 115 | |
0e39037b CW |
116 | if (e->cur) { |
117 | e->cur->offset = 0; | |
118 | e->cur->length = 0; | |
119 | e->cur->page_link = | |
120 | (unsigned long)sgl | SG_CHAIN; | |
121 | } else { | |
122 | e->sgl = sgl; | |
84734a04 MK |
123 | } |
124 | ||
0e39037b CW |
125 | e->cur = sgl; |
126 | e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; | |
84734a04 MK |
127 | } |
128 | ||
0e39037b CW |
129 | e->size = ALIGN(len + 1, SZ_64K); |
130 | e->buf = kmalloc(e->size, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); | |
131 | if (!e->buf) { | |
132 | e->size = PAGE_ALIGN(len + 1); | |
133 | e->buf = kmalloc(e->size, GFP_KERNEL); | |
134 | } | |
135 | if (!e->buf) { | |
136 | e->err = -ENOMEM; | |
137 | return false; | |
138 | } | |
139 | ||
140 | return true; | |
84734a04 MK |
141 | } |
142 | ||
dda35931 | 143 | __printf(2, 0) |
84734a04 | 144 | static void i915_error_vprintf(struct drm_i915_error_state_buf *e, |
0e39037b | 145 | const char *fmt, va_list args) |
84734a04 | 146 | { |
0e39037b CW |
147 | va_list ap; |
148 | int len; | |
84734a04 | 149 | |
0e39037b | 150 | if (e->err) |
84734a04 MK |
151 | return; |
152 | ||
0e39037b CW |
153 | va_copy(ap, args); |
154 | len = vsnprintf(NULL, 0, fmt, ap); | |
155 | va_end(ap); | |
156 | if (len <= 0) { | |
157 | e->err = len; | |
158 | return; | |
84734a04 MK |
159 | } |
160 | ||
0e39037b CW |
161 | if (!__i915_error_grow(e, len)) |
162 | return; | |
84734a04 | 163 | |
0e39037b CW |
164 | GEM_BUG_ON(e->bytes >= e->size); |
165 | len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); | |
166 | if (len < 0) { | |
167 | e->err = len; | |
168 | return; | |
169 | } | |
170 | e->bytes += len; | |
84734a04 MK |
171 | } |
172 | ||
0e39037b | 173 | static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) |
84734a04 MK |
174 | { |
175 | unsigned len; | |
176 | ||
0e39037b | 177 | if (e->err || !str) |
84734a04 MK |
178 | return; |
179 | ||
180 | len = strlen(str); | |
0e39037b CW |
181 | if (!__i915_error_grow(e, len)) |
182 | return; | |
84734a04 | 183 | |
0e39037b | 184 | GEM_BUG_ON(e->bytes + len > e->size); |
84734a04 | 185 | memcpy(e->buf + e->bytes, str, len); |
0e39037b | 186 | e->bytes += len; |
84734a04 MK |
187 | } |
188 | ||
189 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) | |
190 | #define err_puts(e, s) i915_error_puts(e, s) | |
191 | ||
7d41ef34 MW |
192 | static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) |
193 | { | |
194 | i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); | |
195 | } | |
196 | ||
197 | static inline struct drm_printer | |
198 | i915_error_printer(struct drm_i915_error_state_buf *e) | |
199 | { | |
200 | struct drm_printer p = { | |
201 | .printfn = __i915_printfn_error, | |
202 | .arg = e, | |
203 | }; | |
204 | return p; | |
205 | } | |
206 | ||
0a97015d CW |
207 | #ifdef CONFIG_DRM_I915_COMPRESS_ERROR |
208 | ||
d637c178 CW |
209 | struct compress { |
210 | struct z_stream_s zstream; | |
211 | void *tmp; | |
212 | }; | |
213 | ||
214 | static bool compress_init(struct compress *c) | |
0a97015d | 215 | { |
d637c178 | 216 | struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream)); |
0a97015d CW |
217 | |
218 | zstream->workspace = | |
219 | kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), | |
220 | GFP_ATOMIC | __GFP_NOWARN); | |
221 | if (!zstream->workspace) | |
222 | return false; | |
223 | ||
224 | if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) { | |
225 | kfree(zstream->workspace); | |
226 | return false; | |
227 | } | |
228 | ||
d637c178 | 229 | c->tmp = NULL; |
c4d3ae68 | 230 | if (i915_has_memcpy_from_wc()) |
d637c178 CW |
231 | c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN); |
232 | ||
0a97015d CW |
233 | return true; |
234 | } | |
235 | ||
83bc0f5b CW |
236 | static void *compress_next_page(struct drm_i915_error_object *dst) |
237 | { | |
238 | unsigned long page; | |
239 | ||
240 | if (dst->page_count >= dst->num_pages) | |
241 | return ERR_PTR(-ENOSPC); | |
242 | ||
243 | page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN); | |
244 | if (!page) | |
245 | return ERR_PTR(-ENOMEM); | |
246 | ||
247 | return dst->pages[dst->page_count++] = (void *)page; | |
248 | } | |
249 | ||
d637c178 | 250 | static int compress_page(struct compress *c, |
0a97015d CW |
251 | void *src, |
252 | struct drm_i915_error_object *dst) | |
253 | { | |
d637c178 CW |
254 | struct z_stream_s *zstream = &c->zstream; |
255 | ||
0a97015d | 256 | zstream->next_in = src; |
d637c178 CW |
257 | if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) |
258 | zstream->next_in = c->tmp; | |
0a97015d CW |
259 | zstream->avail_in = PAGE_SIZE; |
260 | ||
261 | do { | |
262 | if (zstream->avail_out == 0) { | |
83bc0f5b CW |
263 | zstream->next_out = compress_next_page(dst); |
264 | if (IS_ERR(zstream->next_out)) | |
265 | return PTR_ERR(zstream->next_out); | |
0a97015d | 266 | |
0a97015d CW |
267 | zstream->avail_out = PAGE_SIZE; |
268 | } | |
269 | ||
83bc0f5b | 270 | if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) |
0a97015d | 271 | return -EIO; |
0e39037b CW |
272 | |
273 | touch_nmi_watchdog(); | |
0a97015d CW |
274 | } while (zstream->avail_in); |
275 | ||
276 | /* Fallback to uncompressed if we increase size? */ | |
277 | if (0 && zstream->total_out > zstream->total_in) | |
278 | return -E2BIG; | |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
83bc0f5b | 283 | static int compress_flush(struct compress *c, |
0a97015d CW |
284 | struct drm_i915_error_object *dst) |
285 | { | |
d637c178 CW |
286 | struct z_stream_s *zstream = &c->zstream; |
287 | ||
83bc0f5b CW |
288 | do { |
289 | switch (zlib_deflate(zstream, Z_FINISH)) { | |
290 | case Z_OK: /* more space requested */ | |
291 | zstream->next_out = compress_next_page(dst); | |
292 | if (IS_ERR(zstream->next_out)) | |
293 | return PTR_ERR(zstream->next_out); | |
294 | ||
295 | zstream->avail_out = PAGE_SIZE; | |
296 | break; | |
297 | ||
298 | case Z_STREAM_END: | |
299 | goto end; | |
300 | ||
301 | default: /* any error */ | |
302 | return -EIO; | |
303 | } | |
304 | } while (1); | |
305 | ||
306 | end: | |
307 | memset(zstream->next_out, 0, zstream->avail_out); | |
308 | dst->unused = zstream->avail_out; | |
309 | return 0; | |
310 | } | |
311 | ||
312 | static void compress_fini(struct compress *c, | |
313 | struct drm_i915_error_object *dst) | |
314 | { | |
315 | struct z_stream_s *zstream = &c->zstream; | |
0a97015d CW |
316 | |
317 | zlib_deflateEnd(zstream); | |
318 | kfree(zstream->workspace); | |
d637c178 CW |
319 | if (c->tmp) |
320 | free_page((unsigned long)c->tmp); | |
0a97015d CW |
321 | } |
322 | ||
323 | static void err_compression_marker(struct drm_i915_error_state_buf *m) | |
324 | { | |
325 | err_puts(m, ":"); | |
326 | } | |
327 | ||
328 | #else | |
329 | ||
d637c178 CW |
330 | struct compress { |
331 | }; | |
332 | ||
333 | static bool compress_init(struct compress *c) | |
0a97015d CW |
334 | { |
335 | return true; | |
336 | } | |
337 | ||
d637c178 | 338 | static int compress_page(struct compress *c, |
0a97015d CW |
339 | void *src, |
340 | struct drm_i915_error_object *dst) | |
341 | { | |
342 | unsigned long page; | |
d637c178 | 343 | void *ptr; |
0a97015d CW |
344 | |
345 | page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN); | |
346 | if (!page) | |
347 | return -ENOMEM; | |
348 | ||
d637c178 CW |
349 | ptr = (void *)page; |
350 | if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE)) | |
351 | memcpy(ptr, src, PAGE_SIZE); | |
352 | dst->pages[dst->page_count++] = ptr; | |
0a97015d CW |
353 | |
354 | return 0; | |
355 | } | |
356 | ||
83bc0f5b CW |
357 | static int compress_flush(struct compress *c, |
358 | struct drm_i915_error_object *dst) | |
359 | { | |
360 | return 0; | |
361 | } | |
362 | ||
d637c178 | 363 | static void compress_fini(struct compress *c, |
0a97015d CW |
364 | struct drm_i915_error_object *dst) |
365 | { | |
366 | } | |
367 | ||
368 | static void err_compression_marker(struct drm_i915_error_state_buf *m) | |
369 | { | |
370 | err_puts(m, "~"); | |
371 | } | |
372 | ||
373 | #endif | |
374 | ||
84734a04 MK |
375 | static void print_error_buffers(struct drm_i915_error_state_buf *m, |
376 | const char *name, | |
377 | struct drm_i915_error_buffer *err, | |
378 | int count) | |
379 | { | |
c0ce4663 | 380 | err_printf(m, "%s [%d]:\n", name, count); |
84734a04 MK |
381 | |
382 | while (count--) { | |
5c3f8c22 | 383 | err_printf(m, " %08x_%08x %8u %02x %02x %02x", |
e1f12325 MT |
384 | upper_32_bits(err->gtt_offset), |
385 | lower_32_bits(err->gtt_offset), | |
84734a04 MK |
386 | err->size, |
387 | err->read_domains, | |
5c3f8c22 CW |
388 | err->write_domain, |
389 | err->wseqno); | |
84734a04 MK |
390 | err_puts(m, tiling_flag(err->tiling)); |
391 | err_puts(m, dirty_flag(err->dirty)); | |
392 | err_puts(m, purgeable_flag(err->purgeable)); | |
5cc9ed4b | 393 | err_puts(m, err->userptr ? " userptr" : ""); |
6361f4ba | 394 | err_puts(m, err->engine != -1 ? " " : ""); |
1edf6958 | 395 | err_puts(m, engine_name(m->i915, err->engine)); |
0a4cd7c8 | 396 | err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); |
84734a04 MK |
397 | |
398 | if (err->name) | |
399 | err_printf(m, " (name: %d)", err->name); | |
400 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
401 | err_printf(m, " (fence: %d)", err->fence_reg); | |
402 | ||
403 | err_puts(m, "\n"); | |
404 | err++; | |
405 | } | |
406 | } | |
407 | ||
d636951e | 408 | static void error_print_instdone(struct drm_i915_error_state_buf *m, |
5a4c6f1b | 409 | const struct drm_i915_error_engine *ee) |
d636951e | 410 | { |
f9e61372 BW |
411 | int slice; |
412 | int subslice; | |
413 | ||
d636951e BW |
414 | err_printf(m, " INSTDONE: 0x%08x\n", |
415 | ee->instdone.instdone); | |
416 | ||
417 | if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3) | |
418 | return; | |
419 | ||
420 | err_printf(m, " SC_INSTDONE: 0x%08x\n", | |
421 | ee->instdone.slice_common); | |
422 | ||
423 | if (INTEL_GEN(m->i915) <= 6) | |
424 | return; | |
425 | ||
f9e61372 BW |
426 | for_each_instdone_slice_subslice(m->i915, slice, subslice) |
427 | err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
428 | slice, subslice, | |
429 | ee->instdone.sampler[slice][subslice]); | |
430 | ||
431 | for_each_instdone_slice_subslice(m->i915, slice, subslice) | |
432 | err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", | |
433 | slice, subslice, | |
434 | ee->instdone.row[slice][subslice]); | |
d636951e BW |
435 | } |
436 | ||
302e55d7 CW |
437 | static const char *bannable(const struct drm_i915_error_context *ctx) |
438 | { | |
439 | return ctx->bannable ? "" : " (unbannable)"; | |
440 | } | |
441 | ||
35ca039e CW |
442 | static void error_print_request(struct drm_i915_error_state_buf *m, |
443 | const char *prefix, | |
043477b0 MK |
444 | const struct drm_i915_error_request *erq, |
445 | const unsigned long epoch) | |
35ca039e CW |
446 | { |
447 | if (!erq->seqno) | |
448 | return; | |
449 | ||
52c0fdb2 | 450 | err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x%s%s, prio %d, emitted %dms, start %08x, head %08x, tail %08x\n", |
84102171 | 451 | prefix, erq->pid, erq->ban_score, |
52c0fdb2 CW |
452 | erq->context, erq->seqno, |
453 | test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, | |
454 | &erq->flags) ? "!" : "", | |
455 | test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, | |
456 | &erq->flags) ? "+" : "", | |
457 | erq->sched_attr.priority, | |
043477b0 | 458 | jiffies_to_msecs(erq->jiffies - epoch), |
3a068721 | 459 | erq->start, erq->head, erq->tail); |
35ca039e CW |
460 | } |
461 | ||
4fa6053e CW |
462 | static void error_print_context(struct drm_i915_error_state_buf *m, |
463 | const char *header, | |
5a4c6f1b | 464 | const struct drm_i915_error_context *ctx) |
4fa6053e | 465 | { |
302e55d7 | 466 | err_printf(m, "%s%s[%d] user_handle %d hw_id %d, prio %d, ban score %d%s guilty %d active %d\n", |
4fa6053e | 467 | header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id, |
b7268c5e | 468 | ctx->sched_attr.priority, ctx->ban_score, bannable(ctx), |
302e55d7 | 469 | ctx->guilty, ctx->active); |
4fa6053e CW |
470 | } |
471 | ||
6361f4ba | 472 | static void error_print_engine(struct drm_i915_error_state_buf *m, |
043477b0 MK |
473 | const struct drm_i915_error_engine *ee, |
474 | const unsigned long epoch) | |
84734a04 | 475 | { |
76e70087 MK |
476 | int n; |
477 | ||
1edf6958 MT |
478 | err_printf(m, "%s command stream:\n", |
479 | engine_name(m->i915, ee->engine_id)); | |
398c8a30 | 480 | err_printf(m, " IDLE?: %s\n", yesno(ee->idle)); |
6361f4ba | 481 | err_printf(m, " START: 0x%08x\n", ee->start); |
06392e3b | 482 | err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); |
cdb324bd CW |
483 | err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", |
484 | ee->tail, ee->rq_post, ee->rq_tail); | |
6361f4ba | 485 | err_printf(m, " CTL: 0x%08x\n", ee->ctl); |
21a2c58a | 486 | err_printf(m, " MODE: 0x%08x\n", ee->mode); |
6361f4ba CW |
487 | err_printf(m, " HWS: 0x%08x\n", ee->hws); |
488 | err_printf(m, " ACTHD: 0x%08x %08x\n", | |
489 | (u32)(ee->acthd>>32), (u32)ee->acthd); | |
490 | err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); | |
491 | err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); | |
d636951e BW |
492 | |
493 | error_print_instdone(m, ee); | |
494 | ||
03382dfb CW |
495 | if (ee->batchbuffer) { |
496 | u64 start = ee->batchbuffer->gtt_offset; | |
497 | u64 end = start + ee->batchbuffer->gtt_size; | |
498 | ||
499 | err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", | |
500 | upper_32_bits(start), lower_32_bits(start), | |
501 | upper_32_bits(end), lower_32_bits(end)); | |
502 | } | |
6361f4ba | 503 | if (INTEL_GEN(m->i915) >= 4) { |
03382dfb | 504 | err_printf(m, " BBADDR: 0x%08x_%08x\n", |
6361f4ba CW |
505 | (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); |
506 | err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); | |
507 | err_printf(m, " INSTPS: 0x%08x\n", ee->instps); | |
3dda20a9 | 508 | } |
6361f4ba CW |
509 | err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); |
510 | err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), | |
511 | lower_32_bits(ee->faddr)); | |
512 | if (INTEL_GEN(m->i915) >= 6) { | |
513 | err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); | |
514 | err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); | |
85e17f59 CW |
515 | err_printf(m, " SYNC_0: 0x%08x\n", |
516 | ee->semaphore_mboxes[0]); | |
517 | err_printf(m, " SYNC_1: 0x%08x\n", | |
518 | ee->semaphore_mboxes[1]); | |
519 | if (HAS_VEBOX(m->i915)) | |
520 | err_printf(m, " SYNC_2: 0x%08x\n", | |
521 | ee->semaphore_mboxes[2]); | |
84734a04 | 522 | } |
4bdafb9d | 523 | if (HAS_PPGTT(m->i915)) { |
6361f4ba | 524 | err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); |
6c7a01ec | 525 | |
6361f4ba | 526 | if (INTEL_GEN(m->i915) >= 8) { |
6c7a01ec BW |
527 | int i; |
528 | for (i = 0; i < 4; i++) | |
529 | err_printf(m, " PDP%d: 0x%016llx\n", | |
6361f4ba | 530 | i, ee->vm_info.pdp[i]); |
6c7a01ec BW |
531 | } else { |
532 | err_printf(m, " PP_DIR_BASE: 0x%08x\n", | |
6361f4ba | 533 | ee->vm_info.pp_dir_base); |
6c7a01ec BW |
534 | } |
535 | } | |
6361f4ba CW |
536 | err_printf(m, " seqno: 0x%08x\n", ee->seqno); |
537 | err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno); | |
6361f4ba CW |
538 | err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head); |
539 | err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail); | |
eb8d0f5a | 540 | err_printf(m, " hangcheck timestamp: %dms (%lu%s)\n", |
043477b0 | 541 | jiffies_to_msecs(ee->hangcheck_timestamp - epoch), |
3fe3b030 | 542 | ee->hangcheck_timestamp, |
043477b0 | 543 | ee->hangcheck_timestamp == epoch ? "; epoch" : ""); |
702c8f8e | 544 | err_printf(m, " engine reset count: %u\n", ee->reset_count); |
3fe3b030 | 545 | |
76e70087 MK |
546 | for (n = 0; n < ee->num_ports; n++) { |
547 | err_printf(m, " ELSP[%d]:", n); | |
043477b0 | 548 | error_print_request(m, " ", &ee->execlist[n], epoch); |
76e70087 MK |
549 | } |
550 | ||
4fa6053e | 551 | error_print_context(m, " Active context: ", &ee->context); |
84734a04 MK |
552 | } |
553 | ||
554 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) | |
555 | { | |
556 | va_list args; | |
557 | ||
558 | va_start(args, f); | |
559 | i915_error_vprintf(e, f, args); | |
560 | va_end(args); | |
561 | } | |
562 | ||
ab0e7ff9 | 563 | static void print_error_obj(struct drm_i915_error_state_buf *m, |
fc4c79c3 CW |
564 | struct intel_engine_cs *engine, |
565 | const char *name, | |
ab0e7ff9 CW |
566 | struct drm_i915_error_object *obj) |
567 | { | |
489cae63 | 568 | char out[ASCII85_BUFSZ]; |
0a97015d | 569 | int page; |
ab0e7ff9 | 570 | |
fc4c79c3 CW |
571 | if (!obj) |
572 | return; | |
573 | ||
574 | if (name) { | |
575 | err_printf(m, "%s --- %s = 0x%08x %08x\n", | |
576 | engine ? engine->name : "global", name, | |
577 | upper_32_bits(obj->gtt_offset), | |
578 | lower_32_bits(obj->gtt_offset)); | |
579 | } | |
580 | ||
0a97015d CW |
581 | err_compression_marker(m); |
582 | for (page = 0; page < obj->page_count; page++) { | |
583 | int i, len; | |
584 | ||
585 | len = PAGE_SIZE; | |
586 | if (page == obj->page_count - 1) | |
587 | len -= obj->unused; | |
588 | len = ascii85_encode_len(len); | |
589 | ||
489cae63 JC |
590 | for (i = 0; i < len; i++) |
591 | err_puts(m, ascii85_encode(obj->pages[page][i], out)); | |
ab0e7ff9 | 592 | } |
0a97015d | 593 | err_puts(m, "\n"); |
ab0e7ff9 CW |
594 | } |
595 | ||
2bd160a1 | 596 | static void err_print_capabilities(struct drm_i915_error_state_buf *m, |
3fed1808 | 597 | const struct intel_device_info *info, |
0258404f | 598 | const struct intel_runtime_info *runtime, |
3fed1808 | 599 | const struct intel_driver_caps *caps) |
2bd160a1 | 600 | { |
a8c9b849 MW |
601 | struct drm_printer p = i915_error_printer(m); |
602 | ||
603 | intel_device_info_dump_flags(info, &p); | |
3fed1808 | 604 | intel_driver_caps_print(caps, &p); |
0258404f | 605 | intel_device_info_dump_topology(&runtime->sseu, &p); |
2bd160a1 CW |
606 | } |
607 | ||
642c8a72 | 608 | static void err_print_params(struct drm_i915_error_state_buf *m, |
acfb9973 | 609 | const struct i915_params *params) |
642c8a72 | 610 | { |
acfb9973 MW |
611 | struct drm_printer p = i915_error_printer(m); |
612 | ||
613 | i915_params_dump(params, &p); | |
642c8a72 CW |
614 | } |
615 | ||
5a4c6f1b CW |
616 | static void err_print_pciid(struct drm_i915_error_state_buf *m, |
617 | struct drm_i915_private *i915) | |
618 | { | |
619 | struct pci_dev *pdev = i915->drm.pdev; | |
620 | ||
621 | err_printf(m, "PCI ID: 0x%04x\n", pdev->device); | |
622 | err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); | |
623 | err_printf(m, "PCI Subsystem: %04x:%04x\n", | |
624 | pdev->subsystem_vendor, | |
625 | pdev->subsystem_device); | |
626 | } | |
627 | ||
7d41ef34 MW |
628 | static void err_print_uc(struct drm_i915_error_state_buf *m, |
629 | const struct i915_error_uc *error_uc) | |
630 | { | |
631 | struct drm_printer p = i915_error_printer(m); | |
632 | const struct i915_gpu_state *error = | |
633 | container_of(error_uc, typeof(*error), uc); | |
634 | ||
635 | if (!error->device_info.has_guc) | |
636 | return; | |
637 | ||
638 | intel_uc_fw_dump(&error_uc->guc_fw, &p); | |
639 | intel_uc_fw_dump(&error_uc->huc_fw, &p); | |
0397ac13 | 640 | print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log); |
7d41ef34 MW |
641 | } |
642 | ||
0e39037b | 643 | static void err_free_sgl(struct scatterlist *sgl) |
84734a04 | 644 | { |
0e39037b CW |
645 | while (sgl) { |
646 | struct scatterlist *sg; | |
84734a04 | 647 | |
0e39037b CW |
648 | for (sg = sgl; !sg_is_chain(sg); sg++) { |
649 | kfree(sg_virt(sg)); | |
650 | if (sg_is_last(sg)) | |
651 | break; | |
652 | } | |
653 | ||
654 | sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); | |
655 | free_page((unsigned long)sgl); | |
656 | sgl = sg; | |
84734a04 | 657 | } |
0e39037b | 658 | } |
84734a04 | 659 | |
0e39037b CW |
660 | static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, |
661 | struct i915_gpu_state *error) | |
662 | { | |
663 | struct drm_i915_error_object *obj; | |
664 | struct timespec64 ts; | |
665 | int i, j; | |
fb6f0b64 | 666 | |
5a4c6f1b CW |
667 | if (*error->error_msg) |
668 | err_printf(m, "%s\n", error->error_msg); | |
57428bcc CW |
669 | err_printf(m, "Kernel: %s %s\n", |
670 | init_utsname()->release, | |
671 | init_utsname()->machine); | |
c6270dbc AB |
672 | ts = ktime_to_timespec64(error->time); |
673 | err_printf(m, "Time: %lld s %ld us\n", | |
674 | (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); | |
675 | ts = ktime_to_timespec64(error->boottime); | |
676 | err_printf(m, "Boottime: %lld s %ld us\n", | |
677 | (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); | |
678 | ts = ktime_to_timespec64(error->uptime); | |
679 | err_printf(m, "Uptime: %lld s %ld us\n", | |
680 | (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); | |
043477b0 MK |
681 | err_printf(m, "Epoch: %lu jiffies (%u HZ)\n", error->epoch, HZ); |
682 | err_printf(m, "Capture: %lu jiffies; %d ms ago, %d ms after epoch\n", | |
683 | error->capture, | |
684 | jiffies_to_msecs(jiffies - error->capture), | |
685 | jiffies_to_msecs(error->capture - error->epoch)); | |
3fe3b030 | 686 | |
6361f4ba | 687 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) { |
eb8d0f5a CW |
688 | if (!error->engine[i].context.pid) |
689 | continue; | |
690 | ||
691 | err_printf(m, "Active process (on ring %s): %s [%d], score %d%s\n", | |
692 | engine_name(m->i915, i), | |
693 | error->engine[i].context.comm, | |
694 | error->engine[i].context.pid, | |
695 | error->engine[i].context.ban_score, | |
696 | bannable(&error->engine[i].context)); | |
ab0e7ff9 | 697 | } |
48b031e3 | 698 | err_printf(m, "Reset count: %u\n", error->reset_count); |
62d5d69b | 699 | err_printf(m, "Suspend count: %u\n", error->suspend_count); |
2e0d26f8 | 700 | err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); |
0e39037b | 701 | err_print_pciid(m, m->i915); |
642c8a72 | 702 | |
eb5be9d0 | 703 | err_printf(m, "IOMMU enabled?: %d\n", error->iommu); |
0ac7655c | 704 | |
0e39037b CW |
705 | if (HAS_CSR(m->i915)) { |
706 | struct intel_csr *csr = &m->i915->csr; | |
0ac7655c MK |
707 | |
708 | err_printf(m, "DMC loaded: %s\n", | |
709 | yesno(csr->dmc_payload != NULL)); | |
710 | err_printf(m, "DMC fw version: %d.%d\n", | |
711 | CSR_VERSION_MAJOR(csr->version), | |
712 | CSR_VERSION_MINOR(csr->version)); | |
713 | } | |
714 | ||
f73b5674 | 715 | err_printf(m, "GT awake: %s\n", yesno(error->awake)); |
e5aac87e CW |
716 | err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); |
717 | err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); | |
84734a04 MK |
718 | err_printf(m, "EIR: 0x%08x\n", error->eir); |
719 | err_printf(m, "IER: 0x%08x\n", error->ier); | |
5a4c6f1b CW |
720 | for (i = 0; i < error->ngtier; i++) |
721 | err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]); | |
84734a04 MK |
722 | err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); |
723 | err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); | |
724 | err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); | |
725 | err_printf(m, "CCID: 0x%08x\n", error->ccid); | |
726 | ||
5a4c6f1b | 727 | for (i = 0; i < error->nfence; i++) |
84734a04 MK |
728 | err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); |
729 | ||
0e39037b | 730 | if (INTEL_GEN(m->i915) >= 6) { |
84734a04 | 731 | err_printf(m, "ERROR: 0x%08x\n", error->error); |
6c826f34 | 732 | |
0e39037b | 733 | if (INTEL_GEN(m->i915) >= 8) |
6c826f34 MK |
734 | err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", |
735 | error->fault_data1, error->fault_data0); | |
736 | ||
84734a04 MK |
737 | err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); |
738 | } | |
739 | ||
cf819eff | 740 | if (IS_GEN(m->i915, 7)) |
84734a04 MK |
741 | err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); |
742 | ||
6361f4ba CW |
743 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) { |
744 | if (error->engine[i].engine_id != -1) | |
043477b0 | 745 | error_print_engine(m, &error->engine[i], error->epoch); |
6361f4ba | 746 | } |
84734a04 | 747 | |
c0ce4663 CW |
748 | for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) { |
749 | char buf[128]; | |
750 | int len, first = 1; | |
3a448734 | 751 | |
c0ce4663 CW |
752 | if (!error->active_vm[i]) |
753 | break; | |
754 | ||
755 | len = scnprintf(buf, sizeof(buf), "Active ("); | |
756 | for (j = 0; j < ARRAY_SIZE(error->engine); j++) { | |
757 | if (error->engine[j].vm != error->active_vm[i]) | |
758 | continue; | |
759 | ||
760 | len += scnprintf(buf + len, sizeof(buf), "%s%s", | |
761 | first ? "" : ", ", | |
0e39037b | 762 | m->i915->engine[j]->name); |
c0ce4663 CW |
763 | first = 0; |
764 | } | |
765 | scnprintf(buf + len, sizeof(buf), ")"); | |
766 | print_error_buffers(m, buf, | |
3a448734 CW |
767 | error->active_bo[i], |
768 | error->active_bo_count[i]); | |
3a448734 | 769 | } |
84734a04 | 770 | |
c0ce4663 CW |
771 | print_error_buffers(m, "Pinned (global)", |
772 | error->pinned_bo, | |
773 | error->pinned_bo_count); | |
774 | ||
6361f4ba | 775 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) { |
5a4c6f1b | 776 | const struct drm_i915_error_engine *ee = &error->engine[i]; |
6361f4ba CW |
777 | |
778 | obj = ee->batchbuffer; | |
ab0e7ff9 | 779 | if (obj) { |
0e39037b | 780 | err_puts(m, m->i915->engine[i]->name); |
4fa6053e | 781 | if (ee->context.pid) |
302e55d7 | 782 | err_printf(m, " (submitted by %s [%d], ctx %d [%d], score %d%s)", |
4fa6053e CW |
783 | ee->context.comm, |
784 | ee->context.pid, | |
785 | ee->context.handle, | |
786 | ee->context.hw_id, | |
302e55d7 CW |
787 | ee->context.ban_score, |
788 | bannable(&ee->context)); | |
e1f12325 MT |
789 | err_printf(m, " --- gtt_offset = 0x%08x %08x\n", |
790 | upper_32_bits(obj->gtt_offset), | |
791 | lower_32_bits(obj->gtt_offset)); | |
0e39037b | 792 | print_error_obj(m, m->i915->engine[i], NULL, obj); |
84734a04 MK |
793 | } |
794 | ||
b0fd47ad | 795 | for (j = 0; j < ee->user_bo_count; j++) |
0e39037b | 796 | print_error_obj(m, m->i915->engine[i], |
b0fd47ad CW |
797 | "user", ee->user_bo[j]); |
798 | ||
6361f4ba | 799 | if (ee->num_requests) { |
84734a04 | 800 | err_printf(m, "%s --- %d requests\n", |
0e39037b | 801 | m->i915->engine[i]->name, |
6361f4ba | 802 | ee->num_requests); |
35ca039e | 803 | for (j = 0; j < ee->num_requests; j++) |
043477b0 MK |
804 | error_print_request(m, " ", |
805 | &ee->requests[j], | |
806 | error->epoch); | |
84734a04 MK |
807 | } |
808 | ||
0e39037b | 809 | print_error_obj(m, m->i915->engine[i], |
fc4c79c3 | 810 | "ringbuffer", ee->ringbuffer); |
84734a04 | 811 | |
0e39037b | 812 | print_error_obj(m, m->i915->engine[i], |
fc4c79c3 | 813 | "HW Status", ee->hws_page); |
3a5a0393 | 814 | |
0e39037b | 815 | print_error_obj(m, m->i915->engine[i], |
fc4c79c3 | 816 | "HW context", ee->ctx); |
f3ce3821 | 817 | |
0e39037b | 818 | print_error_obj(m, m->i915->engine[i], |
fc4c79c3 | 819 | "WA context", ee->wa_ctx); |
f85db059 | 820 | |
0e39037b | 821 | print_error_obj(m, m->i915->engine[i], |
fc4c79c3 | 822 | "WA batchbuffer", ee->wa_batchbuffer); |
4e90a6e2 | 823 | |
0e39037b | 824 | print_error_obj(m, m->i915->engine[i], |
4e90a6e2 | 825 | "NULL context", ee->default_state); |
84734a04 MK |
826 | } |
827 | ||
828 | if (error->overlay) | |
829 | intel_overlay_print_error_state(m, error->overlay); | |
830 | ||
831 | if (error->display) | |
5a4c6f1b | 832 | intel_display_print_error_state(m, error->display); |
84734a04 | 833 | |
0258404f JN |
834 | err_print_capabilities(m, &error->device_info, &error->runtime_info, |
835 | &error->driver_caps); | |
642c8a72 | 836 | err_print_params(m, &error->params); |
7d41ef34 | 837 | err_print_uc(m, &error->uc); |
0e39037b CW |
838 | } |
839 | ||
840 | static int err_print_to_sgl(struct i915_gpu_state *error) | |
841 | { | |
842 | struct drm_i915_error_state_buf m; | |
843 | ||
844 | if (IS_ERR(error)) | |
845 | return PTR_ERR(error); | |
846 | ||
847 | if (READ_ONCE(error->sgl)) | |
848 | return 0; | |
849 | ||
850 | memset(&m, 0, sizeof(m)); | |
851 | m.i915 = error->i915; | |
852 | ||
853 | __err_print_to_sgl(&m, error); | |
854 | ||
855 | if (m.buf) { | |
856 | __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); | |
857 | m.bytes = 0; | |
858 | m.buf = NULL; | |
859 | } | |
860 | if (m.cur) { | |
861 | GEM_BUG_ON(m.end < m.cur); | |
862 | sg_mark_end(m.cur - 1); | |
863 | } | |
864 | GEM_BUG_ON(m.sgl && !m.cur); | |
865 | ||
866 | if (m.err) { | |
867 | err_free_sgl(m.sgl); | |
868 | return m.err; | |
869 | } | |
642c8a72 | 870 | |
0e39037b CW |
871 | if (cmpxchg(&error->sgl, NULL, m.sgl)) |
872 | err_free_sgl(m.sgl); | |
84734a04 MK |
873 | |
874 | return 0; | |
875 | } | |
876 | ||
0e39037b CW |
877 | ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error, |
878 | char *buf, loff_t off, size_t rem) | |
84734a04 | 879 | { |
0e39037b CW |
880 | struct scatterlist *sg; |
881 | size_t count; | |
882 | loff_t pos; | |
883 | int err; | |
84734a04 | 884 | |
0e39037b CW |
885 | if (!error || !rem) |
886 | return 0; | |
84734a04 | 887 | |
0e39037b CW |
888 | err = err_print_to_sgl(error); |
889 | if (err) | |
890 | return err; | |
84734a04 | 891 | |
0e39037b CW |
892 | sg = READ_ONCE(error->fit); |
893 | if (!sg || off < sg->dma_address) | |
894 | sg = error->sgl; | |
895 | if (!sg) | |
896 | return 0; | |
84734a04 | 897 | |
0e39037b CW |
898 | pos = sg->dma_address; |
899 | count = 0; | |
900 | do { | |
901 | size_t len, start; | |
902 | ||
903 | if (sg_is_chain(sg)) { | |
904 | sg = sg_chain_ptr(sg); | |
905 | GEM_BUG_ON(sg_is_chain(sg)); | |
906 | } | |
84734a04 | 907 | |
0e39037b CW |
908 | len = sg->length; |
909 | if (pos + len <= off) { | |
910 | pos += len; | |
911 | continue; | |
912 | } | |
84734a04 | 913 | |
0e39037b CW |
914 | start = sg->offset; |
915 | if (pos < off) { | |
916 | GEM_BUG_ON(off - pos > len); | |
917 | len -= off - pos; | |
918 | start += off - pos; | |
919 | pos = off; | |
920 | } | |
921 | ||
922 | len = min(len, rem); | |
923 | GEM_BUG_ON(!len || len > sg->length); | |
924 | ||
925 | memcpy(buf, page_address(sg_page(sg)) + start, len); | |
926 | ||
927 | count += len; | |
928 | pos += len; | |
929 | ||
930 | buf += len; | |
931 | rem -= len; | |
932 | if (!rem) { | |
933 | WRITE_ONCE(error->fit, sg); | |
934 | break; | |
935 | } | |
936 | } while (!sg_is_last(sg++)); | |
937 | ||
938 | return count; | |
84734a04 MK |
939 | } |
940 | ||
941 | static void i915_error_object_free(struct drm_i915_error_object *obj) | |
942 | { | |
943 | int page; | |
944 | ||
945 | if (obj == NULL) | |
946 | return; | |
947 | ||
948 | for (page = 0; page < obj->page_count; page++) | |
95374d75 | 949 | free_page((unsigned long)obj->pages[page]); |
84734a04 MK |
950 | |
951 | kfree(obj); | |
952 | } | |
953 | ||
1d6aa7a3 | 954 | |
84a20a8a MW |
955 | static void cleanup_params(struct i915_gpu_state *error) |
956 | { | |
16cabb12 | 957 | i915_params_free(&error->params); |
84a20a8a MW |
958 | } |
959 | ||
7d41ef34 MW |
960 | static void cleanup_uc_state(struct i915_gpu_state *error) |
961 | { | |
962 | struct i915_error_uc *error_uc = &error->uc; | |
963 | ||
964 | kfree(error_uc->guc_fw.path); | |
965 | kfree(error_uc->huc_fw.path); | |
0397ac13 | 966 | i915_error_object_free(error_uc->guc_log); |
7d41ef34 MW |
967 | } |
968 | ||
5a4c6f1b | 969 | void __i915_gpu_state_free(struct kref *error_ref) |
84734a04 | 970 | { |
5a4c6f1b CW |
971 | struct i915_gpu_state *error = |
972 | container_of(error_ref, typeof(*error), ref); | |
b0fd47ad | 973 | long i, j; |
84734a04 | 974 | |
6361f4ba CW |
975 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) { |
976 | struct drm_i915_error_engine *ee = &error->engine[i]; | |
977 | ||
b0fd47ad CW |
978 | for (j = 0; j < ee->user_bo_count; j++) |
979 | i915_error_object_free(ee->user_bo[j]); | |
980 | kfree(ee->user_bo); | |
981 | ||
6361f4ba CW |
982 | i915_error_object_free(ee->batchbuffer); |
983 | i915_error_object_free(ee->wa_batchbuffer); | |
984 | i915_error_object_free(ee->ringbuffer); | |
985 | i915_error_object_free(ee->hws_page); | |
986 | i915_error_object_free(ee->ctx); | |
987 | i915_error_object_free(ee->wa_ctx); | |
988 | ||
989 | kfree(ee->requests); | |
84734a04 MK |
990 | } |
991 | ||
c0ce4663 | 992 | for (i = 0; i < ARRAY_SIZE(error->active_bo); i++) |
0b37a9a9 | 993 | kfree(error->active_bo[i]); |
0b37a9a9 | 994 | kfree(error->pinned_bo); |
c0ce4663 | 995 | |
84734a04 MK |
996 | kfree(error->overlay); |
997 | kfree(error->display); | |
1d6aa7a3 | 998 | |
84a20a8a | 999 | cleanup_params(error); |
7d41ef34 MW |
1000 | cleanup_uc_state(error); |
1001 | ||
0e39037b | 1002 | err_free_sgl(error->sgl); |
84734a04 MK |
1003 | kfree(error); |
1004 | } | |
1005 | ||
1006 | static struct drm_i915_error_object * | |
95374d75 | 1007 | i915_error_object_create(struct drm_i915_private *i915, |
058d88c4 | 1008 | struct i915_vma *vma) |
84734a04 | 1009 | { |
95374d75 CW |
1010 | struct i915_ggtt *ggtt = &i915->ggtt; |
1011 | const u64 slot = ggtt->error_capture.start; | |
84734a04 | 1012 | struct drm_i915_error_object *dst; |
d637c178 | 1013 | struct compress compress; |
95374d75 CW |
1014 | unsigned long num_pages; |
1015 | struct sgt_iter iter; | |
1016 | dma_addr_t dma; | |
83bc0f5b | 1017 | int ret; |
84734a04 | 1018 | |
7f9e20ef | 1019 | if (!vma || !vma->pages) |
058d88c4 CW |
1020 | return NULL; |
1021 | ||
95374d75 | 1022 | num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; |
0a97015d | 1023 | num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ |
95374d75 CW |
1024 | dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), |
1025 | GFP_ATOMIC | __GFP_NOWARN); | |
058d88c4 | 1026 | if (!dst) |
84734a04 MK |
1027 | return NULL; |
1028 | ||
03382dfb CW |
1029 | dst->gtt_offset = vma->node.start; |
1030 | dst->gtt_size = vma->node.size; | |
83bc0f5b | 1031 | dst->num_pages = num_pages; |
95374d75 | 1032 | dst->page_count = 0; |
0a97015d CW |
1033 | dst->unused = 0; |
1034 | ||
d637c178 | 1035 | if (!compress_init(&compress)) { |
0a97015d CW |
1036 | kfree(dst); |
1037 | return NULL; | |
1038 | } | |
03382dfb | 1039 | |
83bc0f5b | 1040 | ret = -EINVAL; |
95374d75 CW |
1041 | for_each_sgt_dma(dma, iter, vma->pages) { |
1042 | void __iomem *s; | |
b3c3f5e6 | 1043 | |
82ad6443 | 1044 | ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0); |
b3c3f5e6 | 1045 | |
73ebd503 | 1046 | s = io_mapping_map_atomic_wc(&ggtt->iomap, slot); |
d637c178 | 1047 | ret = compress_page(&compress, (void __force *)s, dst); |
95374d75 | 1048 | io_mapping_unmap_atomic(s); |
95374d75 | 1049 | if (ret) |
83bc0f5b | 1050 | break; |
84734a04 | 1051 | } |
84734a04 | 1052 | |
83bc0f5b CW |
1053 | if (ret || compress_flush(&compress, dst)) { |
1054 | while (dst->page_count--) | |
1055 | free_page((unsigned long)dst->pages[dst->page_count]); | |
1056 | kfree(dst); | |
1057 | dst = NULL; | |
1058 | } | |
95374d75 | 1059 | |
d637c178 | 1060 | compress_fini(&compress, dst); |
95374d75 | 1061 | return dst; |
84734a04 | 1062 | } |
84734a04 | 1063 | |
d72d908b | 1064 | /* The error capture is special as tries to run underneath the normal |
21950ee7 | 1065 | * locking rules - so we use the raw version of the i915_active_request lookup. |
d72d908b | 1066 | */ |
739f3abd | 1067 | static inline u32 |
21950ee7 | 1068 | __active_get_seqno(struct i915_active_request *active) |
d72d908b | 1069 | { |
e61e0f51 | 1070 | struct i915_request *request; |
24327f83 | 1071 | |
21950ee7 | 1072 | request = __i915_active_request_peek(active); |
24327f83 | 1073 | return request ? request->global_seqno : 0; |
d72d908b CW |
1074 | } |
1075 | ||
1076 | static inline int | |
21950ee7 | 1077 | __active_get_engine_id(struct i915_active_request *active) |
d72d908b | 1078 | { |
e61e0f51 | 1079 | struct i915_request *request; |
d72d908b | 1080 | |
21950ee7 | 1081 | request = __i915_active_request_peek(active); |
24327f83 | 1082 | return request ? request->engine->id : -1; |
d72d908b CW |
1083 | } |
1084 | ||
84734a04 | 1085 | static void capture_bo(struct drm_i915_error_buffer *err, |
3a448734 | 1086 | struct i915_vma *vma) |
84734a04 | 1087 | { |
3a448734 CW |
1088 | struct drm_i915_gem_object *obj = vma->obj; |
1089 | ||
84734a04 MK |
1090 | err->size = obj->base.size; |
1091 | err->name = obj->base.name; | |
d72d908b | 1092 | |
5b8c8aec CW |
1093 | err->wseqno = __active_get_seqno(&obj->frontbuffer_write); |
1094 | err->engine = __active_get_engine_id(&obj->frontbuffer_write); | |
d72d908b | 1095 | |
3a448734 | 1096 | err->gtt_offset = vma->node.start; |
c0a51fd0 CK |
1097 | err->read_domains = obj->read_domains; |
1098 | err->write_domain = obj->write_domain; | |
49ef5294 | 1099 | err->fence_reg = vma->fence ? vma->fence->id : -1; |
3e510a8e | 1100 | err->tiling = i915_gem_object_get_tiling(obj); |
a4f5ea64 CW |
1101 | err->dirty = obj->mm.dirty; |
1102 | err->purgeable = obj->mm.madv != I915_MADV_WILLNEED; | |
5cc9ed4b | 1103 | err->userptr = obj->userptr.mm != NULL; |
84734a04 MK |
1104 | err->cache_level = obj->cache_level; |
1105 | } | |
1106 | ||
c0ce4663 CW |
1107 | static u32 capture_error_bo(struct drm_i915_error_buffer *err, |
1108 | int count, struct list_head *head, | |
499197dc CW |
1109 | unsigned int flags) |
1110 | #define ACTIVE_ONLY BIT(0) | |
1111 | #define PINNED_ONLY BIT(1) | |
84734a04 | 1112 | { |
ca191b13 | 1113 | struct i915_vma *vma; |
84734a04 MK |
1114 | int i = 0; |
1115 | ||
1c7f4bca | 1116 | list_for_each_entry(vma, head, vm_link) { |
520ea7c5 CW |
1117 | if (!vma->obj) |
1118 | continue; | |
1119 | ||
499197dc CW |
1120 | if (flags & ACTIVE_ONLY && !i915_vma_is_active(vma)) |
1121 | continue; | |
1122 | ||
1123 | if (flags & PINNED_ONLY && !i915_vma_is_pinned(vma)) | |
c0ce4663 CW |
1124 | continue; |
1125 | ||
3a448734 | 1126 | capture_bo(err++, vma); |
84734a04 MK |
1127 | if (++i == count) |
1128 | break; | |
1129 | } | |
1130 | ||
1131 | return i; | |
1132 | } | |
1133 | ||
eb8d0f5a CW |
1134 | /* |
1135 | * Generate a semi-unique error code. The code is not meant to have meaning, The | |
011cf577 BW |
1136 | * code's only purpose is to try to prevent false duplicated bug reports by |
1137 | * grossly estimating a GPU error state. | |
1138 | * | |
1139 | * TODO Ideally, hashing the batchbuffer would be a very nice way to determine | |
1140 | * the hang if we could strip the GTT offset information from it. | |
1141 | * | |
1142 | * It's only a small step better than a random number in its current form. | |
1143 | */ | |
eb8d0f5a CW |
1144 | static u32 i915_error_generate_code(struct i915_gpu_state *error, |
1145 | unsigned long engine_mask) | |
011cf577 | 1146 | { |
eb8d0f5a CW |
1147 | /* |
1148 | * IPEHR would be an ideal way to detect errors, as it's the gross | |
011cf577 BW |
1149 | * measure of "the command that hung." However, has some very common |
1150 | * synchronization commands which almost always appear in the case | |
1151 | * strictly a client bug. Use instdone to differentiate those some. | |
1152 | */ | |
eb8d0f5a CW |
1153 | if (engine_mask) { |
1154 | struct drm_i915_error_engine *ee = | |
1155 | &error->engine[ffs(engine_mask)]; | |
cb383002 | 1156 | |
eb8d0f5a | 1157 | return ee->ipehr ^ ee->instdone.instdone; |
cb383002 | 1158 | } |
011cf577 | 1159 | |
eb8d0f5a | 1160 | return 0; |
011cf577 BW |
1161 | } |
1162 | ||
53b725c7 | 1163 | static void gem_record_fences(struct i915_gpu_state *error) |
84734a04 | 1164 | { |
53b725c7 | 1165 | struct drm_i915_private *dev_priv = error->i915; |
84734a04 MK |
1166 | int i; |
1167 | ||
5a4c6f1b | 1168 | if (INTEL_GEN(dev_priv) >= 6) { |
ce38ab05 | 1169 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
5a4c6f1b CW |
1170 | error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); |
1171 | } else if (INTEL_GEN(dev_priv) >= 4) { | |
eecf613a VS |
1172 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
1173 | error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); | |
5a4c6f1b | 1174 | } else { |
eecf613a | 1175 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
5a4c6f1b | 1176 | error->fence[i] = I915_READ(FENCE_REG(i)); |
eecf613a | 1177 | } |
5a4c6f1b | 1178 | error->nfence = i; |
84734a04 MK |
1179 | } |
1180 | ||
6361f4ba CW |
1181 | static void gen6_record_semaphore_state(struct intel_engine_cs *engine, |
1182 | struct drm_i915_error_engine *ee) | |
87f85ebc | 1183 | { |
6361f4ba CW |
1184 | struct drm_i915_private *dev_priv = engine->i915; |
1185 | ||
1186 | ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base)); | |
1187 | ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base)); | |
85e17f59 | 1188 | if (HAS_VEBOX(dev_priv)) |
6361f4ba | 1189 | ee->semaphore_mboxes[2] = |
0bc40be8 | 1190 | I915_READ(RING_SYNC_2(engine->mmio_base)); |
87f85ebc BW |
1191 | } |
1192 | ||
5a4c6f1b | 1193 | static void error_record_engine_registers(struct i915_gpu_state *error, |
6361f4ba CW |
1194 | struct intel_engine_cs *engine, |
1195 | struct drm_i915_error_engine *ee) | |
84734a04 | 1196 | { |
6361f4ba CW |
1197 | struct drm_i915_private *dev_priv = engine->i915; |
1198 | ||
c033666a | 1199 | if (INTEL_GEN(dev_priv) >= 6) { |
6361f4ba | 1200 | ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); |
b03ec3d6 | 1201 | if (INTEL_GEN(dev_priv) >= 8) { |
b03ec3d6 MT |
1202 | ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); |
1203 | } else { | |
6361f4ba | 1204 | gen6_record_semaphore_state(engine, ee); |
b03ec3d6 MT |
1205 | ee->fault_reg = I915_READ(RING_FAULT_REG(engine)); |
1206 | } | |
4e5aabfd BW |
1207 | } |
1208 | ||
c033666a | 1209 | if (INTEL_GEN(dev_priv) >= 4) { |
6361f4ba CW |
1210 | ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base)); |
1211 | ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base)); | |
1212 | ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); | |
6361f4ba CW |
1213 | ee->instps = I915_READ(RING_INSTPS(engine->mmio_base)); |
1214 | ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); | |
c033666a | 1215 | if (INTEL_GEN(dev_priv) >= 8) { |
6361f4ba CW |
1216 | ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32; |
1217 | ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32; | |
13ffadd1 | 1218 | } |
6361f4ba | 1219 | ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base)); |
84734a04 | 1220 | } else { |
6361f4ba CW |
1221 | ee->faddr = I915_READ(DMA_FADD_I8XX); |
1222 | ee->ipeir = I915_READ(IPEIR); | |
1223 | ee->ipehr = I915_READ(IPEHR); | |
84734a04 MK |
1224 | } |
1225 | ||
0e704476 | 1226 | intel_engine_get_instdone(engine, &ee->instdone); |
d636951e | 1227 | |
6361f4ba | 1228 | ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base)); |
7e37f889 | 1229 | ee->acthd = intel_engine_get_active_head(engine); |
6361f4ba | 1230 | ee->seqno = intel_engine_get_seqno(engine); |
cb399eab | 1231 | ee->last_seqno = intel_engine_last_submit(engine); |
6361f4ba CW |
1232 | ee->start = I915_READ_START(engine); |
1233 | ee->head = I915_READ_HEAD(engine); | |
1234 | ee->tail = I915_READ_TAIL(engine); | |
1235 | ee->ctl = I915_READ_CTL(engine); | |
21a2c58a CW |
1236 | if (INTEL_GEN(dev_priv) > 2) |
1237 | ee->mode = I915_READ_MODE(engine); | |
84734a04 | 1238 | |
3177659a | 1239 | if (!HWS_NEEDS_PHYSICAL(dev_priv)) { |
f0f59a00 | 1240 | i915_reg_t mmio; |
f3ce3821 | 1241 | |
cf819eff | 1242 | if (IS_GEN(dev_priv, 7)) { |
0bc40be8 | 1243 | switch (engine->id) { |
f3ce3821 CW |
1244 | default: |
1245 | case RCS: | |
1246 | mmio = RENDER_HWS_PGA_GEN7; | |
1247 | break; | |
1248 | case BCS: | |
1249 | mmio = BLT_HWS_PGA_GEN7; | |
1250 | break; | |
1251 | case VCS: | |
1252 | mmio = BSD_HWS_PGA_GEN7; | |
1253 | break; | |
1254 | case VECS: | |
1255 | mmio = VEBOX_HWS_PGA_GEN7; | |
1256 | break; | |
1257 | } | |
cf819eff | 1258 | } else if (IS_GEN(engine->i915, 6)) { |
0bc40be8 | 1259 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
f3ce3821 CW |
1260 | } else { |
1261 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 1262 | mmio = RING_HWS_PGA(engine->mmio_base); |
f3ce3821 CW |
1263 | } |
1264 | ||
6361f4ba | 1265 | ee->hws = I915_READ(mmio); |
f3ce3821 CW |
1266 | } |
1267 | ||
398c8a30 | 1268 | ee->idle = intel_engine_is_idle(engine); |
eb8d0f5a CW |
1269 | if (!ee->idle) |
1270 | ee->hangcheck_timestamp = engine->hangcheck.action_timestamp; | |
702c8f8e MT |
1271 | ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error, |
1272 | engine); | |
6c7a01ec | 1273 | |
4bdafb9d | 1274 | if (HAS_PPGTT(dev_priv)) { |
6c7a01ec BW |
1275 | int i; |
1276 | ||
6361f4ba | 1277 | ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine)); |
6c7a01ec | 1278 | |
cf819eff | 1279 | if (IS_GEN(dev_priv, 6)) |
6361f4ba | 1280 | ee->vm_info.pp_dir_base = |
0bc40be8 | 1281 | I915_READ(RING_PP_DIR_BASE_READ(engine)); |
cf819eff | 1282 | else if (IS_GEN(dev_priv, 7)) |
6361f4ba | 1283 | ee->vm_info.pp_dir_base = |
0bc40be8 | 1284 | I915_READ(RING_PP_DIR_BASE(engine)); |
c033666a | 1285 | else if (INTEL_GEN(dev_priv) >= 8) |
6c7a01ec | 1286 | for (i = 0; i < 4; i++) { |
6361f4ba | 1287 | ee->vm_info.pdp[i] = |
0bc40be8 | 1288 | I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
6361f4ba CW |
1289 | ee->vm_info.pdp[i] <<= 32; |
1290 | ee->vm_info.pdp[i] |= | |
0bc40be8 | 1291 | I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
6c7a01ec | 1292 | } |
6c7a01ec | 1293 | } |
84734a04 MK |
1294 | } |
1295 | ||
e61e0f51 | 1296 | static void record_request(struct i915_request *request, |
35ca039e CW |
1297 | struct drm_i915_error_request *erq) |
1298 | { | |
4e0d64db CW |
1299 | struct i915_gem_context *ctx = request->gem_context; |
1300 | ||
52c0fdb2 | 1301 | erq->flags = request->fence.flags; |
4e0d64db | 1302 | erq->context = ctx->hw_id; |
b7268c5e | 1303 | erq->sched_attr = request->sched.attr; |
4e0d64db | 1304 | erq->ban_score = atomic_read(&ctx->ban_score); |
65e4760e | 1305 | erq->seqno = request->global_seqno; |
35ca039e | 1306 | erq->jiffies = request->emitted_jiffies; |
3a068721 | 1307 | erq->start = i915_ggtt_offset(request->ring->vma); |
35ca039e CW |
1308 | erq->head = request->head; |
1309 | erq->tail = request->tail; | |
1310 | ||
1311 | rcu_read_lock(); | |
4e0d64db | 1312 | erq->pid = ctx->pid ? pid_nr(ctx->pid) : 0; |
35ca039e CW |
1313 | rcu_read_unlock(); |
1314 | } | |
1315 | ||
57bc699d | 1316 | static void engine_record_requests(struct intel_engine_cs *engine, |
e61e0f51 | 1317 | struct i915_request *first, |
57bc699d CW |
1318 | struct drm_i915_error_engine *ee) |
1319 | { | |
e61e0f51 | 1320 | struct i915_request *request; |
57bc699d CW |
1321 | int count; |
1322 | ||
1323 | count = 0; | |
1324 | request = first; | |
a89d1f92 | 1325 | list_for_each_entry_from(request, &engine->timeline.requests, link) |
57bc699d CW |
1326 | count++; |
1327 | if (!count) | |
1328 | return; | |
1329 | ||
1330 | ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC); | |
1331 | if (!ee->requests) | |
1332 | return; | |
1333 | ||
1334 | ee->num_requests = count; | |
1335 | ||
1336 | count = 0; | |
1337 | request = first; | |
a89d1f92 | 1338 | list_for_each_entry_from(request, &engine->timeline.requests, link) { |
57bc699d CW |
1339 | if (count >= ee->num_requests) { |
1340 | /* | |
1341 | * If the ring request list was changed in | |
1342 | * between the point where the error request | |
1343 | * list was created and dimensioned and this | |
1344 | * point then just exit early to avoid crashes. | |
1345 | * | |
1346 | * We don't need to communicate that the | |
1347 | * request list changed state during error | |
1348 | * state capture and that the error state is | |
1349 | * slightly incorrect as a consequence since we | |
1350 | * are typically only interested in the request | |
1351 | * list state at the point of error state | |
1352 | * capture, not in any changes happening during | |
1353 | * the capture. | |
1354 | */ | |
1355 | break; | |
1356 | } | |
1357 | ||
35ca039e | 1358 | record_request(request, &ee->requests[count++]); |
57bc699d CW |
1359 | } |
1360 | ee->num_requests = count; | |
1361 | } | |
1362 | ||
35ca039e CW |
1363 | static void error_record_engine_execlists(struct intel_engine_cs *engine, |
1364 | struct drm_i915_error_engine *ee) | |
1365 | { | |
76e70087 | 1366 | const struct intel_engine_execlists * const execlists = &engine->execlists; |
35ca039e CW |
1367 | unsigned int n; |
1368 | ||
76e70087 | 1369 | for (n = 0; n < execlists_num_ports(execlists); n++) { |
e61e0f51 | 1370 | struct i915_request *rq = port_request(&execlists->port[n]); |
77f0d0e9 CW |
1371 | |
1372 | if (!rq) | |
1373 | break; | |
1374 | ||
1375 | record_request(rq, &ee->execlist[n]); | |
1376 | } | |
76e70087 MK |
1377 | |
1378 | ee->num_ports = n; | |
35ca039e CW |
1379 | } |
1380 | ||
4fa6053e CW |
1381 | static void record_context(struct drm_i915_error_context *e, |
1382 | struct i915_gem_context *ctx) | |
1383 | { | |
1384 | if (ctx->pid) { | |
1385 | struct task_struct *task; | |
1386 | ||
1387 | rcu_read_lock(); | |
1388 | task = pid_task(ctx->pid, PIDTYPE_PID); | |
1389 | if (task) { | |
1390 | strcpy(e->comm, task->comm); | |
1391 | e->pid = task->pid; | |
1392 | } | |
1393 | rcu_read_unlock(); | |
1394 | } | |
1395 | ||
1396 | e->handle = ctx->user_handle; | |
1397 | e->hw_id = ctx->hw_id; | |
b7268c5e | 1398 | e->sched_attr = ctx->sched; |
77b25a97 | 1399 | e->ban_score = atomic_read(&ctx->ban_score); |
302e55d7 | 1400 | e->bannable = i915_gem_context_is_bannable(ctx); |
77b25a97 CW |
1401 | e->guilty = atomic_read(&ctx->guilty_count); |
1402 | e->active = atomic_read(&ctx->active_count); | |
4fa6053e CW |
1403 | } |
1404 | ||
e61e0f51 | 1405 | static void request_record_user_bo(struct i915_request *request, |
b0fd47ad CW |
1406 | struct drm_i915_error_engine *ee) |
1407 | { | |
e61e0f51 | 1408 | struct i915_capture_list *c; |
b0fd47ad | 1409 | struct drm_i915_error_object **bo; |
8e3ffa8d | 1410 | long count, max; |
b0fd47ad | 1411 | |
8e3ffa8d | 1412 | max = 0; |
b0fd47ad | 1413 | for (c = request->capture_list; c; c = c->next) |
8e3ffa8d CW |
1414 | max++; |
1415 | if (!max) | |
1416 | return; | |
b0fd47ad | 1417 | |
8e3ffa8d CW |
1418 | bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC); |
1419 | if (!bo) { | |
1420 | /* If we can't capture everything, try to capture something. */ | |
1421 | max = min_t(long, max, PAGE_SIZE / sizeof(*bo)); | |
1422 | bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC); | |
1423 | } | |
b0fd47ad CW |
1424 | if (!bo) |
1425 | return; | |
1426 | ||
1427 | count = 0; | |
1428 | for (c = request->capture_list; c; c = c->next) { | |
1429 | bo[count] = i915_error_object_create(request->i915, c->vma); | |
1430 | if (!bo[count]) | |
1431 | break; | |
8e3ffa8d CW |
1432 | if (++count == max) |
1433 | break; | |
b0fd47ad CW |
1434 | } |
1435 | ||
1436 | ee->user_bo = bo; | |
1437 | ee->user_bo_count = count; | |
1438 | } | |
1439 | ||
4e90a6e2 CW |
1440 | static struct drm_i915_error_object * |
1441 | capture_object(struct drm_i915_private *dev_priv, | |
1442 | struct drm_i915_gem_object *obj) | |
1443 | { | |
1444 | if (obj && i915_gem_object_has_pages(obj)) { | |
1445 | struct i915_vma fake = { | |
1446 | .node = { .start = U64_MAX, .size = obj->base.size }, | |
b5e0a941 | 1447 | .size = obj->base.size, |
4e90a6e2 CW |
1448 | .pages = obj->mm.pages, |
1449 | .obj = obj, | |
1450 | }; | |
1451 | ||
1452 | return i915_error_object_create(dev_priv, &fake); | |
1453 | } else { | |
1454 | return NULL; | |
1455 | } | |
1456 | } | |
1457 | ||
53b725c7 | 1458 | static void gem_record_rings(struct i915_gpu_state *error) |
84734a04 | 1459 | { |
53b725c7 DCS |
1460 | struct drm_i915_private *i915 = error->i915; |
1461 | struct i915_ggtt *ggtt = &i915->ggtt; | |
57bc699d | 1462 | int i; |
84734a04 | 1463 | |
666796da | 1464 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
53b725c7 | 1465 | struct intel_engine_cs *engine = i915->engine[i]; |
6361f4ba | 1466 | struct drm_i915_error_engine *ee = &error->engine[i]; |
e61e0f51 | 1467 | struct i915_request *request; |
372fbb8e | 1468 | |
6361f4ba | 1469 | ee->engine_id = -1; |
eee73b46 | 1470 | |
3b3f1650 | 1471 | if (!engine) |
372fbb8e CW |
1472 | continue; |
1473 | ||
6361f4ba | 1474 | ee->engine_id = i; |
372fbb8e | 1475 | |
6361f4ba | 1476 | error_record_engine_registers(error, engine, ee); |
35ca039e | 1477 | error_record_engine_execlists(engine, ee); |
84734a04 | 1478 | |
e2f80391 | 1479 | request = i915_gem_find_active_request(engine); |
ab0e7ff9 | 1480 | if (request) { |
4e0d64db | 1481 | struct i915_gem_context *ctx = request->gem_context; |
7e37f889 | 1482 | struct intel_ring *ring; |
ae6c4806 | 1483 | |
82ad6443 | 1484 | ee->vm = ctx->ppgtt ? &ctx->ppgtt->vm : &ggtt->vm; |
ae6c4806 | 1485 | |
4e0d64db | 1486 | record_context(&ee->context, ctx); |
4fa6053e | 1487 | |
ab0e7ff9 CW |
1488 | /* We need to copy these to an anonymous buffer |
1489 | * as the simplest method to avoid being overwritten | |
1490 | * by userspace. | |
1491 | */ | |
6361f4ba | 1492 | ee->batchbuffer = |
53b725c7 | 1493 | i915_error_object_create(i915, request->batch); |
ab0e7ff9 | 1494 | |
53b725c7 | 1495 | if (HAS_BROKEN_CS_TLB(i915)) |
6361f4ba | 1496 | ee->wa_batchbuffer = |
53b725c7 | 1497 | i915_error_object_create(i915, |
51797499 | 1498 | i915->gt.scratch); |
b0fd47ad | 1499 | request_record_user_bo(request, ee); |
ab0e7ff9 | 1500 | |
058d88c4 | 1501 | ee->ctx = |
53b725c7 | 1502 | i915_error_object_create(i915, |
1fc44d9b | 1503 | request->hw_context->state); |
546b1b6a | 1504 | |
bc3d6744 | 1505 | error->simulated |= |
4e0d64db | 1506 | i915_gem_context_no_error_capture(ctx); |
bc3d6744 | 1507 | |
cdb324bd CW |
1508 | ee->rq_head = request->head; |
1509 | ee->rq_post = request->postfix; | |
1510 | ee->rq_tail = request->tail; | |
1511 | ||
1dae2dfb CW |
1512 | ring = request->ring; |
1513 | ee->cpu_ring_head = ring->head; | |
1514 | ee->cpu_ring_tail = ring->tail; | |
6361f4ba | 1515 | ee->ringbuffer = |
53b725c7 | 1516 | i915_error_object_create(i915, ring->vma); |
57bc699d CW |
1517 | |
1518 | engine_record_requests(engine, request, ee); | |
ba6e0418 | 1519 | } |
84734a04 | 1520 | |
6361f4ba | 1521 | ee->hws_page = |
53b725c7 | 1522 | i915_error_object_create(i915, |
058d88c4 | 1523 | engine->status_page.vma); |
84734a04 | 1524 | |
53b725c7 | 1525 | ee->wa_ctx = i915_error_object_create(i915, engine->wa_ctx.vma); |
4e90a6e2 | 1526 | |
53b725c7 | 1527 | ee->default_state = capture_object(i915, engine->default_state); |
84734a04 MK |
1528 | } |
1529 | } | |
1530 | ||
53b725c7 DCS |
1531 | static void gem_capture_vm(struct i915_gpu_state *error, |
1532 | struct i915_address_space *vm, | |
1533 | int idx) | |
84734a04 | 1534 | { |
c0ce4663 | 1535 | struct drm_i915_error_buffer *active_bo; |
95f5301d | 1536 | struct i915_vma *vma; |
c0ce4663 | 1537 | int count; |
84734a04 | 1538 | |
c0ce4663 | 1539 | count = 0; |
499197dc CW |
1540 | list_for_each_entry(vma, &vm->bound_list, vm_link) |
1541 | if (i915_vma_is_active(vma)) | |
1542 | count++; | |
84734a04 | 1543 | |
c0ce4663 CW |
1544 | active_bo = NULL; |
1545 | if (count) | |
1546 | active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC); | |
95f5301d | 1547 | if (active_bo) |
499197dc CW |
1548 | count = capture_error_bo(active_bo, |
1549 | count, &vm->bound_list, | |
1550 | ACTIVE_ONLY); | |
c0ce4663 CW |
1551 | else |
1552 | count = 0; | |
1553 | ||
1554 | error->active_vm[idx] = vm; | |
1555 | error->active_bo[idx] = active_bo; | |
1556 | error->active_bo_count[idx] = count; | |
95f5301d BW |
1557 | } |
1558 | ||
53b725c7 | 1559 | static void capture_active_buffers(struct i915_gpu_state *error) |
95f5301d | 1560 | { |
c0ce4663 CW |
1561 | int cnt = 0, i, j; |
1562 | ||
1563 | BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo)); | |
1564 | BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm)); | |
1565 | BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count)); | |
1566 | ||
1567 | /* Scan each engine looking for unique active contexts/vm */ | |
1568 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) { | |
1569 | struct drm_i915_error_engine *ee = &error->engine[i]; | |
1570 | bool found; | |
1571 | ||
1572 | if (!ee->vm) | |
1573 | continue; | |
3a448734 | 1574 | |
c0ce4663 CW |
1575 | found = false; |
1576 | for (j = 0; j < i && !found; j++) | |
1577 | found = error->engine[j].vm == ee->vm; | |
1578 | if (!found) | |
53b725c7 | 1579 | gem_capture_vm(error, ee->vm, cnt++); |
3a448734 | 1580 | } |
84734a04 MK |
1581 | } |
1582 | ||
53b725c7 | 1583 | static void capture_pinned_buffers(struct i915_gpu_state *error) |
c0ce4663 | 1584 | { |
82ad6443 | 1585 | struct i915_address_space *vm = &error->i915->ggtt.vm; |
c0ce4663 CW |
1586 | struct drm_i915_error_buffer *bo; |
1587 | struct i915_vma *vma; | |
499197dc | 1588 | int count; |
c0ce4663 | 1589 | |
499197dc CW |
1590 | count = 0; |
1591 | list_for_each_entry(vma, &vm->bound_list, vm_link) | |
1592 | count++; | |
c0ce4663 CW |
1593 | |
1594 | bo = NULL; | |
499197dc CW |
1595 | if (count) |
1596 | bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC); | |
c0ce4663 CW |
1597 | if (!bo) |
1598 | return; | |
1599 | ||
499197dc CW |
1600 | error->pinned_bo_count = |
1601 | capture_error_bo(bo, count, &vm->bound_list, PINNED_ONLY); | |
c0ce4663 CW |
1602 | error->pinned_bo = bo; |
1603 | } | |
1604 | ||
7d41ef34 MW |
1605 | static void capture_uc_state(struct i915_gpu_state *error) |
1606 | { | |
1607 | struct drm_i915_private *i915 = error->i915; | |
1608 | struct i915_error_uc *error_uc = &error->uc; | |
1609 | ||
1610 | /* Capturing uC state won't be useful if there is no GuC */ | |
1611 | if (!error->device_info.has_guc) | |
1612 | return; | |
1613 | ||
1614 | error_uc->guc_fw = i915->guc.fw; | |
1615 | error_uc->huc_fw = i915->huc.fw; | |
1616 | ||
1617 | /* Non-default firmware paths will be specified by the modparam. | |
1618 | * As modparams are generally accesible from the userspace make | |
1619 | * explicit copies of the firmware paths. | |
1620 | */ | |
1621 | error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC); | |
1622 | error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC); | |
0397ac13 | 1623 | error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma); |
27b85bea AG |
1624 | } |
1625 | ||
1d762aad | 1626 | /* Capture all registers which don't fit into another category. */ |
53b725c7 | 1627 | static void capture_reg_state(struct i915_gpu_state *error) |
84734a04 | 1628 | { |
53b725c7 | 1629 | struct drm_i915_private *dev_priv = error->i915; |
885ea5a8 | 1630 | int i; |
84734a04 | 1631 | |
654c90c6 BW |
1632 | /* General organization |
1633 | * 1. Registers specific to a single generation | |
1634 | * 2. Registers which belong to multiple generations | |
1635 | * 3. Feature specific registers. | |
1636 | * 4. Everything else | |
1637 | * Please try to follow the order. | |
1638 | */ | |
84734a04 | 1639 | |
654c90c6 | 1640 | /* 1: Registers specific to a single generation */ |
11a914c2 | 1641 | if (IS_VALLEYVIEW(dev_priv)) { |
885ea5a8 | 1642 | error->gtier[0] = I915_READ(GTIER); |
843db716 | 1643 | error->ier = I915_READ(VLV_IER); |
40181697 | 1644 | error->forcewake = I915_READ_FW(FORCEWAKE_VLV); |
654c90c6 | 1645 | } |
84734a04 | 1646 | |
cf819eff | 1647 | if (IS_GEN(dev_priv, 7)) |
654c90c6 | 1648 | error->err_int = I915_READ(GEN7_ERR_INT); |
84734a04 | 1649 | |
5f56d5f9 | 1650 | if (INTEL_GEN(dev_priv) >= 8) { |
6c826f34 MK |
1651 | error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); |
1652 | error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); | |
1653 | } | |
1654 | ||
cf819eff | 1655 | if (IS_GEN(dev_priv, 6)) { |
40181697 | 1656 | error->forcewake = I915_READ_FW(FORCEWAKE); |
91ec5d11 BW |
1657 | error->gab_ctl = I915_READ(GAB_CTL); |
1658 | error->gfx_mode = I915_READ(GFX_MODE); | |
1659 | } | |
84734a04 | 1660 | |
654c90c6 | 1661 | /* 2: Registers which belong to multiple generations */ |
5f56d5f9 | 1662 | if (INTEL_GEN(dev_priv) >= 7) |
40181697 | 1663 | error->forcewake = I915_READ_FW(FORCEWAKE_MT); |
84734a04 | 1664 | |
5f56d5f9 | 1665 | if (INTEL_GEN(dev_priv) >= 6) { |
654c90c6 | 1666 | error->derrmr = I915_READ(DERRMR); |
84734a04 MK |
1667 | error->error = I915_READ(ERROR_GEN6); |
1668 | error->done_reg = I915_READ(DONE_REG); | |
1669 | } | |
1670 | ||
5de92320 | 1671 | if (INTEL_GEN(dev_priv) >= 5) |
f2e4d76e JL |
1672 | error->ccid = I915_READ(CCID); |
1673 | ||
654c90c6 | 1674 | /* 3: Feature specific registers */ |
f3ce44a0 | 1675 | if (IS_GEN_RANGE(dev_priv, 6, 7)) { |
91ec5d11 BW |
1676 | error->gam_ecochk = I915_READ(GAM_ECOCHK); |
1677 | error->gac_eco = I915_READ(GAC_ECO_BITS); | |
1678 | } | |
1679 | ||
1680 | /* 4: Everything else */ | |
6b7a6a7b OM |
1681 | if (INTEL_GEN(dev_priv) >= 11) { |
1682 | error->ier = I915_READ(GEN8_DE_MISC_IER); | |
1683 | error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); | |
1684 | error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE); | |
1685 | error->gtier[2] = I915_READ(GEN11_GUC_SG_INTR_ENABLE); | |
1686 | error->gtier[3] = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); | |
1687 | error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE); | |
1688 | error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE); | |
1689 | error->ngtier = 6; | |
1690 | } else if (INTEL_GEN(dev_priv) >= 8) { | |
885ea5a8 RV |
1691 | error->ier = I915_READ(GEN8_DE_MISC_IER); |
1692 | for (i = 0; i < 4; i++) | |
1693 | error->gtier[i] = I915_READ(GEN8_GT_IER(i)); | |
5a4c6f1b | 1694 | error->ngtier = 4; |
6e266956 | 1695 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
843db716 | 1696 | error->ier = I915_READ(DEIER); |
885ea5a8 | 1697 | error->gtier[0] = I915_READ(GTIER); |
5a4c6f1b | 1698 | error->ngtier = 1; |
cf819eff | 1699 | } else if (IS_GEN(dev_priv, 2)) { |
843db716 | 1700 | error->ier = I915_READ16(IER); |
11a914c2 | 1701 | } else if (!IS_VALLEYVIEW(dev_priv)) { |
843db716 | 1702 | error->ier = I915_READ(IER); |
654c90c6 | 1703 | } |
654c90c6 BW |
1704 | error->eir = I915_READ(EIR); |
1705 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
1d762aad BW |
1706 | } |
1707 | ||
eb8d0f5a CW |
1708 | static const char * |
1709 | error_msg(struct i915_gpu_state *error, unsigned long engines, const char *msg) | |
cb383002 | 1710 | { |
eb8d0f5a CW |
1711 | int len; |
1712 | int i; | |
cb383002 | 1713 | |
eb8d0f5a CW |
1714 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) |
1715 | if (!error->engine[i].context.pid) | |
1716 | engines &= ~BIT(i); | |
cb383002 | 1717 | |
58174462 | 1718 | len = scnprintf(error->error_msg, sizeof(error->error_msg), |
eb8d0f5a CW |
1719 | "GPU HANG: ecode %d:%lx:0x%08x", |
1720 | INTEL_GEN(error->i915), engines, | |
1721 | i915_error_generate_code(error, engines)); | |
1722 | if (engines) { | |
1723 | /* Just show the first executing process, more is confusing */ | |
1724 | i = ffs(engines); | |
58174462 MK |
1725 | len += scnprintf(error->error_msg + len, |
1726 | sizeof(error->error_msg) - len, | |
1727 | ", in %s [%d]", | |
eb8d0f5a CW |
1728 | error->engine[i].context.comm, |
1729 | error->engine[i].context.pid); | |
1730 | } | |
1731 | if (msg) | |
1732 | len += scnprintf(error->error_msg + len, | |
1733 | sizeof(error->error_msg) - len, | |
1734 | ", %s", msg); | |
58174462 | 1735 | |
eb8d0f5a | 1736 | return error->error_msg; |
cb383002 MK |
1737 | } |
1738 | ||
53b725c7 | 1739 | static void capture_gen_state(struct i915_gpu_state *error) |
48b031e3 | 1740 | { |
53b725c7 DCS |
1741 | struct drm_i915_private *i915 = error->i915; |
1742 | ||
1743 | error->awake = i915->gt.awake; | |
1744 | error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); | |
1745 | error->suspended = i915->runtime_pm.suspended; | |
f73b5674 | 1746 | |
eb5be9d0 CW |
1747 | error->iommu = -1; |
1748 | #ifdef CONFIG_INTEL_IOMMU | |
1749 | error->iommu = intel_iommu_gfx_mapped; | |
1750 | #endif | |
53b725c7 DCS |
1751 | error->reset_count = i915_reset_count(&i915->gpu_error); |
1752 | error->suspend_count = i915->suspend_count; | |
2bd160a1 CW |
1753 | |
1754 | memcpy(&error->device_info, | |
53b725c7 | 1755 | INTEL_INFO(i915), |
2bd160a1 | 1756 | sizeof(error->device_info)); |
0258404f JN |
1757 | memcpy(&error->runtime_info, |
1758 | RUNTIME_INFO(i915), | |
1759 | sizeof(error->runtime_info)); | |
53b725c7 | 1760 | error->driver_caps = i915->caps; |
48b031e3 MK |
1761 | } |
1762 | ||
84a20a8a MW |
1763 | static void capture_params(struct i915_gpu_state *error) |
1764 | { | |
4081cef9 | 1765 | i915_params_copy(&error->params, &i915_modparams); |
84a20a8a MW |
1766 | } |
1767 | ||
043477b0 MK |
1768 | static unsigned long capture_find_epoch(const struct i915_gpu_state *error) |
1769 | { | |
1770 | unsigned long epoch = error->capture; | |
1771 | int i; | |
1772 | ||
1773 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) { | |
1774 | const struct drm_i915_error_engine *ee = &error->engine[i]; | |
1775 | ||
eb8d0f5a | 1776 | if (ee->hangcheck_timestamp && |
043477b0 MK |
1777 | time_before(ee->hangcheck_timestamp, epoch)) |
1778 | epoch = ee->hangcheck_timestamp; | |
1779 | } | |
1780 | ||
1781 | return epoch; | |
1782 | } | |
1783 | ||
8f5c6fe4 CW |
1784 | static void capture_finish(struct i915_gpu_state *error) |
1785 | { | |
1786 | struct i915_ggtt *ggtt = &error->i915->ggtt; | |
1787 | const u64 slot = ggtt->error_capture.start; | |
1788 | ||
1789 | ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); | |
1790 | } | |
1791 | ||
9f267eb8 CW |
1792 | static int capture(void *data) |
1793 | { | |
5a4c6f1b | 1794 | struct i915_gpu_state *error = data; |
9f267eb8 | 1795 | |
c6270dbc AB |
1796 | error->time = ktime_get_real(); |
1797 | error->boottime = ktime_get_boottime(); | |
1798 | error->uptime = ktime_sub(ktime_get(), | |
1799 | error->i915->gt.last_init_time); | |
043477b0 | 1800 | error->capture = jiffies; |
642c8a72 | 1801 | |
84a20a8a | 1802 | capture_params(error); |
53b725c7 | 1803 | capture_gen_state(error); |
7cc62d0b | 1804 | capture_uc_state(error); |
53b725c7 DCS |
1805 | capture_reg_state(error); |
1806 | gem_record_fences(error); | |
1807 | gem_record_rings(error); | |
1808 | capture_active_buffers(error); | |
1809 | capture_pinned_buffers(error); | |
9f267eb8 | 1810 | |
9f267eb8 CW |
1811 | error->overlay = intel_overlay_capture_error_state(error->i915); |
1812 | error->display = intel_display_capture_error_state(error->i915); | |
1813 | ||
043477b0 MK |
1814 | error->epoch = capture_find_epoch(error); |
1815 | ||
8f5c6fe4 | 1816 | capture_finish(error); |
9f267eb8 CW |
1817 | return 0; |
1818 | } | |
1819 | ||
eafc4894 CW |
1820 | #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) |
1821 | ||
5a4c6f1b CW |
1822 | struct i915_gpu_state * |
1823 | i915_capture_gpu_state(struct drm_i915_private *i915) | |
1824 | { | |
1825 | struct i915_gpu_state *error; | |
1826 | ||
e6154e4c CW |
1827 | /* Check if GPU capture has been disabled */ |
1828 | error = READ_ONCE(i915->gpu_error.first_error); | |
1829 | if (IS_ERR(error)) | |
1830 | return error; | |
1831 | ||
5a4c6f1b | 1832 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
e6154e4c CW |
1833 | if (!error) { |
1834 | i915_disable_error_state(i915, -ENOMEM); | |
1835 | return ERR_PTR(-ENOMEM); | |
1836 | } | |
5a4c6f1b CW |
1837 | |
1838 | kref_init(&error->ref); | |
1839 | error->i915 = i915; | |
1840 | ||
1841 | stop_machine(capture, error, NULL); | |
1842 | ||
1843 | return error; | |
1844 | } | |
1845 | ||
1d762aad BW |
1846 | /** |
1847 | * i915_capture_error_state - capture an error record for later analysis | |
d03133a8 CW |
1848 | * @i915: i915 device |
1849 | * @engine_mask: the mask of engines triggering the hang | |
eb8d0f5a | 1850 | * @msg: a message to insert into the error capture header |
1d762aad BW |
1851 | * |
1852 | * Should be called when an error is detected (either a hang or an error | |
1853 | * interrupt) to capture error state from the time of the error. Fills | |
1854 | * out a structure which becomes available in debugfs for user level tools | |
1855 | * to pick up. | |
1856 | */ | |
d03133a8 | 1857 | void i915_capture_error_state(struct drm_i915_private *i915, |
eb8d0f5a CW |
1858 | unsigned long engine_mask, |
1859 | const char *msg) | |
1d762aad | 1860 | { |
53a4c6b2 | 1861 | static bool warned; |
5a4c6f1b | 1862 | struct i915_gpu_state *error; |
1d762aad | 1863 | unsigned long flags; |
1d762aad | 1864 | |
4f044a88 | 1865 | if (!i915_modparams.error_capture) |
98a2f411 CW |
1866 | return; |
1867 | ||
d03133a8 | 1868 | if (READ_ONCE(i915->gpu_error.first_error)) |
9777cca0 CW |
1869 | return; |
1870 | ||
d03133a8 | 1871 | error = i915_capture_gpu_state(i915); |
e6154e4c | 1872 | if (IS_ERR(error)) |
1d762aad | 1873 | return; |
1d762aad | 1874 | |
eb8d0f5a | 1875 | dev_info(i915->drm.dev, "%s\n", error_msg(error, engine_mask, msg)); |
cb383002 | 1876 | |
bc3d6744 | 1877 | if (!error->simulated) { |
d03133a8 CW |
1878 | spin_lock_irqsave(&i915->gpu_error.lock, flags); |
1879 | if (!i915->gpu_error.first_error) { | |
1880 | i915->gpu_error.first_error = error; | |
bc3d6744 CW |
1881 | error = NULL; |
1882 | } | |
d03133a8 | 1883 | spin_unlock_irqrestore(&i915->gpu_error.lock, flags); |
84734a04 | 1884 | } |
84734a04 | 1885 | |
cb383002 | 1886 | if (error) { |
5a4c6f1b | 1887 | __i915_gpu_state_free(&error->ref); |
cb383002 MK |
1888 | return; |
1889 | } | |
1890 | ||
eafc4894 CW |
1891 | if (!warned && |
1892 | ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { | |
cb383002 MK |
1893 | DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); |
1894 | DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); | |
1895 | DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); | |
1896 | DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); | |
91c8a326 | 1897 | DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", |
d03133a8 | 1898 | i915->drm.primary->index); |
cb383002 MK |
1899 | warned = true; |
1900 | } | |
84734a04 MK |
1901 | } |
1902 | ||
5a4c6f1b CW |
1903 | struct i915_gpu_state * |
1904 | i915_first_error_state(struct drm_i915_private *i915) | |
84734a04 | 1905 | { |
5a4c6f1b | 1906 | struct i915_gpu_state *error; |
84734a04 | 1907 | |
5a4c6f1b CW |
1908 | spin_lock_irq(&i915->gpu_error.lock); |
1909 | error = i915->gpu_error.first_error; | |
e6154e4c | 1910 | if (!IS_ERR_OR_NULL(error)) |
5a4c6f1b CW |
1911 | i915_gpu_state_get(error); |
1912 | spin_unlock_irq(&i915->gpu_error.lock); | |
84734a04 | 1913 | |
5a4c6f1b | 1914 | return error; |
84734a04 MK |
1915 | } |
1916 | ||
5a4c6f1b | 1917 | void i915_reset_error_state(struct drm_i915_private *i915) |
84734a04 | 1918 | { |
5a4c6f1b | 1919 | struct i915_gpu_state *error; |
84734a04 | 1920 | |
5a4c6f1b CW |
1921 | spin_lock_irq(&i915->gpu_error.lock); |
1922 | error = i915->gpu_error.first_error; | |
e6154e4c CW |
1923 | if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ |
1924 | i915->gpu_error.first_error = NULL; | |
5a4c6f1b | 1925 | spin_unlock_irq(&i915->gpu_error.lock); |
84734a04 | 1926 | |
e6154e4c | 1927 | if (!IS_ERR_OR_NULL(error)) |
fb6f0b64 CW |
1928 | i915_gpu_state_put(error); |
1929 | } | |
1930 | ||
1931 | void i915_disable_error_state(struct drm_i915_private *i915, int err) | |
1932 | { | |
1933 | spin_lock_irq(&i915->gpu_error.lock); | |
1934 | if (!i915->gpu_error.first_error) | |
1935 | i915->gpu_error.first_error = ERR_PTR(err); | |
1936 | spin_unlock_irq(&i915->gpu_error.lock); | |
84734a04 | 1937 | } |