Commit | Line | Data |
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84734a04 MK |
1 | /* |
2 | * Copyright (c) 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * Mika Kuoppala <mika.kuoppala@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include <generated/utsrelease.h> | |
9f267eb8 | 31 | #include <linux/stop_machine.h> |
0a97015d | 32 | #include <linux/zlib.h> |
84734a04 MK |
33 | #include "i915_drv.h" |
34 | ||
6361f4ba | 35 | static const char *engine_str(int engine) |
84734a04 | 36 | { |
6361f4ba | 37 | switch (engine) { |
84734a04 MK |
38 | case RCS: return "render"; |
39 | case VCS: return "bsd"; | |
40 | case BCS: return "blt"; | |
41 | case VECS: return "vebox"; | |
845f74a7 | 42 | case VCS2: return "bsd2"; |
84734a04 MK |
43 | default: return ""; |
44 | } | |
45 | } | |
46 | ||
84734a04 MK |
47 | static const char *tiling_flag(int tiling) |
48 | { | |
49 | switch (tiling) { | |
50 | default: | |
51 | case I915_TILING_NONE: return ""; | |
52 | case I915_TILING_X: return " X"; | |
53 | case I915_TILING_Y: return " Y"; | |
54 | } | |
55 | } | |
56 | ||
57 | static const char *dirty_flag(int dirty) | |
58 | { | |
59 | return dirty ? " dirty" : ""; | |
60 | } | |
61 | ||
62 | static const char *purgeable_flag(int purgeable) | |
63 | { | |
64 | return purgeable ? " purgeable" : ""; | |
65 | } | |
66 | ||
67 | static bool __i915_error_ok(struct drm_i915_error_state_buf *e) | |
68 | { | |
69 | ||
70 | if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { | |
71 | e->err = -ENOSPC; | |
72 | return false; | |
73 | } | |
74 | ||
75 | if (e->bytes == e->size - 1 || e->err) | |
76 | return false; | |
77 | ||
78 | return true; | |
79 | } | |
80 | ||
81 | static bool __i915_error_seek(struct drm_i915_error_state_buf *e, | |
82 | unsigned len) | |
83 | { | |
84 | if (e->pos + len <= e->start) { | |
85 | e->pos += len; | |
86 | return false; | |
87 | } | |
88 | ||
89 | /* First vsnprintf needs to fit in its entirety for memmove */ | |
90 | if (len >= e->size) { | |
91 | e->err = -EIO; | |
92 | return false; | |
93 | } | |
94 | ||
95 | return true; | |
96 | } | |
97 | ||
98 | static void __i915_error_advance(struct drm_i915_error_state_buf *e, | |
99 | unsigned len) | |
100 | { | |
101 | /* If this is first printf in this window, adjust it so that | |
102 | * start position matches start of the buffer | |
103 | */ | |
104 | ||
105 | if (e->pos < e->start) { | |
106 | const size_t off = e->start - e->pos; | |
107 | ||
108 | /* Should not happen but be paranoid */ | |
109 | if (off > len || e->bytes) { | |
110 | e->err = -EIO; | |
111 | return; | |
112 | } | |
113 | ||
114 | memmove(e->buf, e->buf + off, len - off); | |
115 | e->bytes = len - off; | |
116 | e->pos = e->start; | |
117 | return; | |
118 | } | |
119 | ||
120 | e->bytes += len; | |
121 | e->pos += len; | |
122 | } | |
123 | ||
124 | static void i915_error_vprintf(struct drm_i915_error_state_buf *e, | |
125 | const char *f, va_list args) | |
126 | { | |
127 | unsigned len; | |
128 | ||
129 | if (!__i915_error_ok(e)) | |
130 | return; | |
131 | ||
132 | /* Seek the first printf which is hits start position */ | |
133 | if (e->pos < e->start) { | |
e29bb4eb CW |
134 | va_list tmp; |
135 | ||
136 | va_copy(tmp, args); | |
1d2cb9a5 MK |
137 | len = vsnprintf(NULL, 0, f, tmp); |
138 | va_end(tmp); | |
139 | ||
140 | if (!__i915_error_seek(e, len)) | |
84734a04 MK |
141 | return; |
142 | } | |
143 | ||
144 | len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); | |
145 | if (len >= e->size - e->bytes) | |
146 | len = e->size - e->bytes - 1; | |
147 | ||
148 | __i915_error_advance(e, len); | |
149 | } | |
150 | ||
151 | static void i915_error_puts(struct drm_i915_error_state_buf *e, | |
152 | const char *str) | |
153 | { | |
154 | unsigned len; | |
155 | ||
156 | if (!__i915_error_ok(e)) | |
157 | return; | |
158 | ||
159 | len = strlen(str); | |
160 | ||
161 | /* Seek the first printf which is hits start position */ | |
162 | if (e->pos < e->start) { | |
163 | if (!__i915_error_seek(e, len)) | |
164 | return; | |
165 | } | |
166 | ||
167 | if (len >= e->size - e->bytes) | |
168 | len = e->size - e->bytes - 1; | |
169 | memcpy(e->buf + e->bytes, str, len); | |
170 | ||
171 | __i915_error_advance(e, len); | |
172 | } | |
173 | ||
174 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) | |
175 | #define err_puts(e, s) i915_error_puts(e, s) | |
176 | ||
0a97015d CW |
177 | #ifdef CONFIG_DRM_I915_COMPRESS_ERROR |
178 | ||
179 | static bool compress_init(struct z_stream_s *zstream) | |
180 | { | |
181 | memset(zstream, 0, sizeof(*zstream)); | |
182 | ||
183 | zstream->workspace = | |
184 | kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), | |
185 | GFP_ATOMIC | __GFP_NOWARN); | |
186 | if (!zstream->workspace) | |
187 | return false; | |
188 | ||
189 | if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) { | |
190 | kfree(zstream->workspace); | |
191 | return false; | |
192 | } | |
193 | ||
194 | return true; | |
195 | } | |
196 | ||
197 | static int compress_page(struct z_stream_s *zstream, | |
198 | void *src, | |
199 | struct drm_i915_error_object *dst) | |
200 | { | |
201 | zstream->next_in = src; | |
202 | zstream->avail_in = PAGE_SIZE; | |
203 | ||
204 | do { | |
205 | if (zstream->avail_out == 0) { | |
206 | unsigned long page; | |
207 | ||
208 | page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN); | |
209 | if (!page) | |
210 | return -ENOMEM; | |
211 | ||
212 | dst->pages[dst->page_count++] = (void *)page; | |
213 | ||
214 | zstream->next_out = (void *)page; | |
215 | zstream->avail_out = PAGE_SIZE; | |
216 | } | |
217 | ||
218 | if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK) | |
219 | return -EIO; | |
220 | } while (zstream->avail_in); | |
221 | ||
222 | /* Fallback to uncompressed if we increase size? */ | |
223 | if (0 && zstream->total_out > zstream->total_in) | |
224 | return -E2BIG; | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
229 | static void compress_fini(struct z_stream_s *zstream, | |
230 | struct drm_i915_error_object *dst) | |
231 | { | |
232 | if (dst) { | |
233 | zlib_deflate(zstream, Z_FINISH); | |
234 | dst->unused = zstream->avail_out; | |
235 | } | |
236 | ||
237 | zlib_deflateEnd(zstream); | |
238 | kfree(zstream->workspace); | |
239 | } | |
240 | ||
241 | static void err_compression_marker(struct drm_i915_error_state_buf *m) | |
242 | { | |
243 | err_puts(m, ":"); | |
244 | } | |
245 | ||
246 | #else | |
247 | ||
248 | static bool compress_init(struct z_stream_s *zstream) | |
249 | { | |
250 | return true; | |
251 | } | |
252 | ||
253 | static int compress_page(struct z_stream_s *zstream, | |
254 | void *src, | |
255 | struct drm_i915_error_object *dst) | |
256 | { | |
257 | unsigned long page; | |
258 | ||
259 | page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN); | |
260 | if (!page) | |
261 | return -ENOMEM; | |
262 | ||
263 | dst->pages[dst->page_count++] = | |
264 | memcpy((void *)page, src, PAGE_SIZE); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | static void compress_fini(struct z_stream_s *zstream, | |
270 | struct drm_i915_error_object *dst) | |
271 | { | |
272 | } | |
273 | ||
274 | static void err_compression_marker(struct drm_i915_error_state_buf *m) | |
275 | { | |
276 | err_puts(m, "~"); | |
277 | } | |
278 | ||
279 | #endif | |
280 | ||
84734a04 MK |
281 | static void print_error_buffers(struct drm_i915_error_state_buf *m, |
282 | const char *name, | |
283 | struct drm_i915_error_buffer *err, | |
284 | int count) | |
285 | { | |
b4716185 CW |
286 | int i; |
287 | ||
c0ce4663 | 288 | err_printf(m, "%s [%d]:\n", name, count); |
84734a04 MK |
289 | |
290 | while (count--) { | |
e1f12325 MT |
291 | err_printf(m, " %08x_%08x %8u %02x %02x [ ", |
292 | upper_32_bits(err->gtt_offset), | |
293 | lower_32_bits(err->gtt_offset), | |
84734a04 MK |
294 | err->size, |
295 | err->read_domains, | |
b4716185 | 296 | err->write_domain); |
666796da | 297 | for (i = 0; i < I915_NUM_ENGINES; i++) |
b4716185 CW |
298 | err_printf(m, "%02x ", err->rseqno[i]); |
299 | ||
300 | err_printf(m, "] %02x", err->wseqno); | |
84734a04 MK |
301 | err_puts(m, tiling_flag(err->tiling)); |
302 | err_puts(m, dirty_flag(err->dirty)); | |
303 | err_puts(m, purgeable_flag(err->purgeable)); | |
5cc9ed4b | 304 | err_puts(m, err->userptr ? " userptr" : ""); |
6361f4ba CW |
305 | err_puts(m, err->engine != -1 ? " " : ""); |
306 | err_puts(m, engine_str(err->engine)); | |
0a4cd7c8 | 307 | err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); |
84734a04 MK |
308 | |
309 | if (err->name) | |
310 | err_printf(m, " (name: %d)", err->name); | |
311 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
312 | err_printf(m, " (fence: %d)", err->fence_reg); | |
313 | ||
314 | err_puts(m, "\n"); | |
315 | err++; | |
316 | } | |
317 | } | |
318 | ||
7e37f889 | 319 | static const char *hangcheck_action_to_str(enum intel_engine_hangcheck_action a) |
da661464 MK |
320 | { |
321 | switch (a) { | |
322 | case HANGCHECK_IDLE: | |
323 | return "idle"; | |
324 | case HANGCHECK_WAIT: | |
325 | return "wait"; | |
326 | case HANGCHECK_ACTIVE: | |
327 | return "active"; | |
328 | case HANGCHECK_KICK: | |
329 | return "kick"; | |
330 | case HANGCHECK_HUNG: | |
331 | return "hung"; | |
332 | } | |
333 | ||
334 | return "unknown"; | |
335 | } | |
336 | ||
d636951e BW |
337 | static void error_print_instdone(struct drm_i915_error_state_buf *m, |
338 | struct drm_i915_error_engine *ee) | |
339 | { | |
f9e61372 BW |
340 | int slice; |
341 | int subslice; | |
342 | ||
d636951e BW |
343 | err_printf(m, " INSTDONE: 0x%08x\n", |
344 | ee->instdone.instdone); | |
345 | ||
346 | if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3) | |
347 | return; | |
348 | ||
349 | err_printf(m, " SC_INSTDONE: 0x%08x\n", | |
350 | ee->instdone.slice_common); | |
351 | ||
352 | if (INTEL_GEN(m->i915) <= 6) | |
353 | return; | |
354 | ||
f9e61372 BW |
355 | for_each_instdone_slice_subslice(m->i915, slice, subslice) |
356 | err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
357 | slice, subslice, | |
358 | ee->instdone.sampler[slice][subslice]); | |
359 | ||
360 | for_each_instdone_slice_subslice(m->i915, slice, subslice) | |
361 | err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", | |
362 | slice, subslice, | |
363 | ee->instdone.row[slice][subslice]); | |
d636951e BW |
364 | } |
365 | ||
35ca039e CW |
366 | static void error_print_request(struct drm_i915_error_state_buf *m, |
367 | const char *prefix, | |
368 | struct drm_i915_error_request *erq) | |
369 | { | |
370 | if (!erq->seqno) | |
371 | return; | |
372 | ||
373 | err_printf(m, "%s pid %d, seqno %8x:%08x, emitted %dms ago, head %08x, tail %08x\n", | |
374 | prefix, erq->pid, | |
375 | erq->context, erq->seqno, | |
376 | jiffies_to_msecs(jiffies - erq->jiffies), | |
377 | erq->head, erq->tail); | |
378 | } | |
379 | ||
6361f4ba CW |
380 | static void error_print_engine(struct drm_i915_error_state_buf *m, |
381 | struct drm_i915_error_engine *ee) | |
84734a04 | 382 | { |
6361f4ba CW |
383 | err_printf(m, "%s command stream:\n", engine_str(ee->engine_id)); |
384 | err_printf(m, " START: 0x%08x\n", ee->start); | |
06392e3b | 385 | err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); |
cdb324bd CW |
386 | err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", |
387 | ee->tail, ee->rq_post, ee->rq_tail); | |
6361f4ba | 388 | err_printf(m, " CTL: 0x%08x\n", ee->ctl); |
21a2c58a | 389 | err_printf(m, " MODE: 0x%08x\n", ee->mode); |
6361f4ba CW |
390 | err_printf(m, " HWS: 0x%08x\n", ee->hws); |
391 | err_printf(m, " ACTHD: 0x%08x %08x\n", | |
392 | (u32)(ee->acthd>>32), (u32)ee->acthd); | |
393 | err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); | |
394 | err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); | |
d636951e BW |
395 | |
396 | error_print_instdone(m, ee); | |
397 | ||
03382dfb CW |
398 | if (ee->batchbuffer) { |
399 | u64 start = ee->batchbuffer->gtt_offset; | |
400 | u64 end = start + ee->batchbuffer->gtt_size; | |
401 | ||
402 | err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", | |
403 | upper_32_bits(start), lower_32_bits(start), | |
404 | upper_32_bits(end), lower_32_bits(end)); | |
405 | } | |
6361f4ba | 406 | if (INTEL_GEN(m->i915) >= 4) { |
03382dfb | 407 | err_printf(m, " BBADDR: 0x%08x_%08x\n", |
6361f4ba CW |
408 | (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); |
409 | err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); | |
410 | err_printf(m, " INSTPS: 0x%08x\n", ee->instps); | |
3dda20a9 | 411 | } |
6361f4ba CW |
412 | err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); |
413 | err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), | |
414 | lower_32_bits(ee->faddr)); | |
415 | if (INTEL_GEN(m->i915) >= 6) { | |
416 | err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); | |
417 | err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); | |
85e17f59 CW |
418 | err_printf(m, " SYNC_0: 0x%08x\n", |
419 | ee->semaphore_mboxes[0]); | |
420 | err_printf(m, " SYNC_1: 0x%08x\n", | |
421 | ee->semaphore_mboxes[1]); | |
422 | if (HAS_VEBOX(m->i915)) | |
423 | err_printf(m, " SYNC_2: 0x%08x\n", | |
424 | ee->semaphore_mboxes[2]); | |
84734a04 | 425 | } |
6361f4ba CW |
426 | if (USES_PPGTT(m->i915)) { |
427 | err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); | |
6c7a01ec | 428 | |
6361f4ba | 429 | if (INTEL_GEN(m->i915) >= 8) { |
6c7a01ec BW |
430 | int i; |
431 | for (i = 0; i < 4; i++) | |
432 | err_printf(m, " PDP%d: 0x%016llx\n", | |
6361f4ba | 433 | i, ee->vm_info.pdp[i]); |
6c7a01ec BW |
434 | } else { |
435 | err_printf(m, " PP_DIR_BASE: 0x%08x\n", | |
6361f4ba | 436 | ee->vm_info.pp_dir_base); |
6c7a01ec BW |
437 | } |
438 | } | |
6361f4ba CW |
439 | err_printf(m, " seqno: 0x%08x\n", ee->seqno); |
440 | err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno); | |
441 | err_printf(m, " waiting: %s\n", yesno(ee->waiting)); | |
442 | err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head); | |
443 | err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail); | |
da661464 | 444 | err_printf(m, " hangcheck: %s [%d]\n", |
6361f4ba CW |
445 | hangcheck_action_to_str(ee->hangcheck_action), |
446 | ee->hangcheck_score); | |
35ca039e CW |
447 | error_print_request(m, " ELSP[0]: ", &ee->execlist[0]); |
448 | error_print_request(m, " ELSP[1]: ", &ee->execlist[1]); | |
84734a04 MK |
449 | } |
450 | ||
451 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) | |
452 | { | |
453 | va_list args; | |
454 | ||
455 | va_start(args, f); | |
456 | i915_error_vprintf(e, f, args); | |
457 | va_end(args); | |
458 | } | |
459 | ||
0a97015d CW |
460 | static int |
461 | ascii85_encode_len(int len) | |
462 | { | |
463 | return DIV_ROUND_UP(len, 4); | |
464 | } | |
465 | ||
466 | static bool | |
467 | ascii85_encode(u32 in, char *out) | |
468 | { | |
469 | int i; | |
470 | ||
471 | if (in == 0) | |
472 | return false; | |
473 | ||
474 | out[5] = '\0'; | |
475 | for (i = 5; i--; ) { | |
476 | out[i] = '!' + in % 85; | |
477 | in /= 85; | |
478 | } | |
479 | ||
480 | return true; | |
481 | } | |
482 | ||
ab0e7ff9 | 483 | static void print_error_obj(struct drm_i915_error_state_buf *m, |
fc4c79c3 CW |
484 | struct intel_engine_cs *engine, |
485 | const char *name, | |
ab0e7ff9 CW |
486 | struct drm_i915_error_object *obj) |
487 | { | |
0a97015d CW |
488 | char out[6]; |
489 | int page; | |
ab0e7ff9 | 490 | |
fc4c79c3 CW |
491 | if (!obj) |
492 | return; | |
493 | ||
494 | if (name) { | |
495 | err_printf(m, "%s --- %s = 0x%08x %08x\n", | |
496 | engine ? engine->name : "global", name, | |
497 | upper_32_bits(obj->gtt_offset), | |
498 | lower_32_bits(obj->gtt_offset)); | |
499 | } | |
500 | ||
0a97015d CW |
501 | err_compression_marker(m); |
502 | for (page = 0; page < obj->page_count; page++) { | |
503 | int i, len; | |
504 | ||
505 | len = PAGE_SIZE; | |
506 | if (page == obj->page_count - 1) | |
507 | len -= obj->unused; | |
508 | len = ascii85_encode_len(len); | |
509 | ||
510 | for (i = 0; i < len; i++) { | |
511 | if (ascii85_encode(obj->pages[page][i], out)) | |
512 | err_puts(m, out); | |
513 | else | |
514 | err_puts(m, "z"); | |
ab0e7ff9 CW |
515 | } |
516 | } | |
0a97015d | 517 | err_puts(m, "\n"); |
ab0e7ff9 CW |
518 | } |
519 | ||
2bd160a1 CW |
520 | static void err_print_capabilities(struct drm_i915_error_state_buf *m, |
521 | const struct intel_device_info *info) | |
522 | { | |
523 | #define PRINT_FLAG(x) err_printf(m, #x ": %s\n", yesno(info->x)) | |
604db650 | 524 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
2bd160a1 | 525 | #undef PRINT_FLAG |
2bd160a1 CW |
526 | } |
527 | ||
84734a04 MK |
528 | int i915_error_state_to_str(struct drm_i915_error_state_buf *m, |
529 | const struct i915_error_state_file_priv *error_priv) | |
530 | { | |
531 | struct drm_device *dev = error_priv->dev; | |
fac5e23e | 532 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 533 | struct pci_dev *pdev = dev_priv->drm.pdev; |
84734a04 | 534 | struct drm_i915_error_state *error = error_priv->error; |
0ca36d78 | 535 | struct drm_i915_error_object *obj; |
ab0e7ff9 | 536 | int max_hangcheck_score; |
fc4c79c3 | 537 | int i, j; |
84734a04 MK |
538 | |
539 | if (!error) { | |
540 | err_printf(m, "no error state collected\n"); | |
541 | goto out; | |
542 | } | |
543 | ||
cb383002 | 544 | err_printf(m, "%s\n", error->error_msg); |
84734a04 | 545 | err_printf(m, "Kernel: " UTS_RELEASE "\n"); |
de867c20 CW |
546 | err_printf(m, "Time: %ld s %ld us\n", |
547 | error->time.tv_sec, error->time.tv_usec); | |
548 | err_printf(m, "Boottime: %ld s %ld us\n", | |
549 | error->boottime.tv_sec, error->boottime.tv_usec); | |
550 | err_printf(m, "Uptime: %ld s %ld us\n", | |
551 | error->uptime.tv_sec, error->uptime.tv_usec); | |
2bd160a1 | 552 | err_print_capabilities(m, &error->device_info); |
ab0e7ff9 | 553 | max_hangcheck_score = 0; |
6361f4ba CW |
554 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) { |
555 | if (error->engine[i].hangcheck_score > max_hangcheck_score) | |
556 | max_hangcheck_score = error->engine[i].hangcheck_score; | |
ab0e7ff9 | 557 | } |
6361f4ba CW |
558 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) { |
559 | if (error->engine[i].hangcheck_score == max_hangcheck_score && | |
560 | error->engine[i].pid != -1) { | |
ab0e7ff9 | 561 | err_printf(m, "Active process (on ring %s): %s [%d]\n", |
6361f4ba CW |
562 | engine_str(i), |
563 | error->engine[i].comm, | |
564 | error->engine[i].pid); | |
ab0e7ff9 CW |
565 | } |
566 | } | |
48b031e3 | 567 | err_printf(m, "Reset count: %u\n", error->reset_count); |
62d5d69b | 568 | err_printf(m, "Suspend count: %u\n", error->suspend_count); |
52a05c30 DW |
569 | err_printf(m, "PCI ID: 0x%04x\n", pdev->device); |
570 | err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); | |
06e6ff8f | 571 | err_printf(m, "PCI Subsystem: %04x:%04x\n", |
52a05c30 DW |
572 | pdev->subsystem_vendor, |
573 | pdev->subsystem_device); | |
eb5be9d0 | 574 | err_printf(m, "IOMMU enabled?: %d\n", error->iommu); |
0ac7655c | 575 | |
56b857a5 | 576 | if (HAS_CSR(dev_priv)) { |
0ac7655c MK |
577 | struct intel_csr *csr = &dev_priv->csr; |
578 | ||
579 | err_printf(m, "DMC loaded: %s\n", | |
580 | yesno(csr->dmc_payload != NULL)); | |
581 | err_printf(m, "DMC fw version: %d.%d\n", | |
582 | CSR_VERSION_MAJOR(csr->version), | |
583 | CSR_VERSION_MINOR(csr->version)); | |
584 | } | |
585 | ||
84734a04 MK |
586 | err_printf(m, "EIR: 0x%08x\n", error->eir); |
587 | err_printf(m, "IER: 0x%08x\n", error->ier); | |
885ea5a8 RV |
588 | if (INTEL_INFO(dev)->gen >= 8) { |
589 | for (i = 0; i < 4; i++) | |
590 | err_printf(m, "GTIER gt %d: 0x%08x\n", i, | |
591 | error->gtier[i]); | |
6e266956 | 592 | } else if (HAS_PCH_SPLIT(dev_priv) || IS_VALLEYVIEW(dev_priv)) |
885ea5a8 | 593 | err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); |
84734a04 MK |
594 | err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); |
595 | err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); | |
596 | err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); | |
597 | err_printf(m, "CCID: 0x%08x\n", error->ccid); | |
094f9a54 | 598 | err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); |
84734a04 MK |
599 | |
600 | for (i = 0; i < dev_priv->num_fence_regs; i++) | |
601 | err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); | |
602 | ||
84734a04 MK |
603 | if (INTEL_INFO(dev)->gen >= 6) { |
604 | err_printf(m, "ERROR: 0x%08x\n", error->error); | |
6c826f34 MK |
605 | |
606 | if (INTEL_INFO(dev)->gen >= 8) | |
607 | err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", | |
608 | error->fault_data1, error->fault_data0); | |
609 | ||
84734a04 MK |
610 | err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); |
611 | } | |
612 | ||
5db94019 | 613 | if (IS_GEN7(dev_priv)) |
84734a04 MK |
614 | err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); |
615 | ||
6361f4ba CW |
616 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) { |
617 | if (error->engine[i].engine_id != -1) | |
618 | error_print_engine(m, &error->engine[i]); | |
619 | } | |
84734a04 | 620 | |
c0ce4663 CW |
621 | for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) { |
622 | char buf[128]; | |
623 | int len, first = 1; | |
3a448734 | 624 | |
c0ce4663 CW |
625 | if (!error->active_vm[i]) |
626 | break; | |
627 | ||
628 | len = scnprintf(buf, sizeof(buf), "Active ("); | |
629 | for (j = 0; j < ARRAY_SIZE(error->engine); j++) { | |
630 | if (error->engine[j].vm != error->active_vm[i]) | |
631 | continue; | |
632 | ||
633 | len += scnprintf(buf + len, sizeof(buf), "%s%s", | |
634 | first ? "" : ", ", | |
3b3f1650 | 635 | dev_priv->engine[j]->name); |
c0ce4663 CW |
636 | first = 0; |
637 | } | |
638 | scnprintf(buf + len, sizeof(buf), ")"); | |
639 | print_error_buffers(m, buf, | |
3a448734 CW |
640 | error->active_bo[i], |
641 | error->active_bo_count[i]); | |
3a448734 | 642 | } |
84734a04 | 643 | |
c0ce4663 CW |
644 | print_error_buffers(m, "Pinned (global)", |
645 | error->pinned_bo, | |
646 | error->pinned_bo_count); | |
647 | ||
6361f4ba CW |
648 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) { |
649 | struct drm_i915_error_engine *ee = &error->engine[i]; | |
650 | ||
651 | obj = ee->batchbuffer; | |
ab0e7ff9 | 652 | if (obj) { |
3b3f1650 | 653 | err_puts(m, dev_priv->engine[i]->name); |
6361f4ba | 654 | if (ee->pid != -1) |
ab0e7ff9 | 655 | err_printf(m, " (submitted by %s [%d])", |
6361f4ba CW |
656 | ee->comm, |
657 | ee->pid); | |
e1f12325 MT |
658 | err_printf(m, " --- gtt_offset = 0x%08x %08x\n", |
659 | upper_32_bits(obj->gtt_offset), | |
660 | lower_32_bits(obj->gtt_offset)); | |
3b3f1650 | 661 | print_error_obj(m, dev_priv->engine[i], NULL, obj); |
84734a04 MK |
662 | } |
663 | ||
6361f4ba | 664 | if (ee->num_requests) { |
84734a04 | 665 | err_printf(m, "%s --- %d requests\n", |
3b3f1650 | 666 | dev_priv->engine[i]->name, |
6361f4ba | 667 | ee->num_requests); |
35ca039e CW |
668 | for (j = 0; j < ee->num_requests; j++) |
669 | error_print_request(m, " ", &ee->requests[j]); | |
84734a04 MK |
670 | } |
671 | ||
19eb9189 CW |
672 | if (IS_ERR(ee->waiters)) { |
673 | err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n", | |
3b3f1650 | 674 | dev_priv->engine[i]->name); |
19eb9189 | 675 | } else if (ee->num_waiters) { |
688e6c72 | 676 | err_printf(m, "%s --- %d waiters\n", |
3b3f1650 | 677 | dev_priv->engine[i]->name, |
6361f4ba CW |
678 | ee->num_waiters); |
679 | for (j = 0; j < ee->num_waiters; j++) { | |
688e6c72 | 680 | err_printf(m, " seqno 0x%08x for %s [%d]\n", |
6361f4ba CW |
681 | ee->waiters[j].seqno, |
682 | ee->waiters[j].comm, | |
683 | ee->waiters[j].pid); | |
688e6c72 CW |
684 | } |
685 | } | |
686 | ||
3b3f1650 | 687 | print_error_obj(m, dev_priv->engine[i], |
fc4c79c3 | 688 | "ringbuffer", ee->ringbuffer); |
84734a04 | 689 | |
3b3f1650 | 690 | print_error_obj(m, dev_priv->engine[i], |
fc4c79c3 | 691 | "HW Status", ee->hws_page); |
3a5a0393 | 692 | |
3b3f1650 | 693 | print_error_obj(m, dev_priv->engine[i], |
fc4c79c3 | 694 | "HW context", ee->ctx); |
f3ce3821 | 695 | |
3b3f1650 | 696 | print_error_obj(m, dev_priv->engine[i], |
fc4c79c3 | 697 | "WA context", ee->wa_ctx); |
f85db059 | 698 | |
3b3f1650 | 699 | print_error_obj(m, dev_priv->engine[i], |
fc4c79c3 | 700 | "WA batchbuffer", ee->wa_batchbuffer); |
84734a04 MK |
701 | } |
702 | ||
fc4c79c3 | 703 | print_error_obj(m, NULL, "Semaphores", error->semaphore); |
0ca36d78 | 704 | |
27b85bea AG |
705 | print_error_obj(m, NULL, "GuC log buffer", error->guc_log); |
706 | ||
84734a04 MK |
707 | if (error->overlay) |
708 | intel_overlay_print_error_state(m, error->overlay); | |
709 | ||
710 | if (error->display) | |
711 | intel_display_print_error_state(m, dev, error->display); | |
712 | ||
713 | out: | |
714 | if (m->bytes == 0 && m->err) | |
715 | return m->err; | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
720 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, | |
0a4cd7c8 | 721 | struct drm_i915_private *i915, |
84734a04 MK |
722 | size_t count, loff_t pos) |
723 | { | |
724 | memset(ebuf, 0, sizeof(*ebuf)); | |
0a4cd7c8 | 725 | ebuf->i915 = i915; |
84734a04 MK |
726 | |
727 | /* We need to have enough room to store any i915_error_state printf | |
728 | * so that we can move it to start position. | |
729 | */ | |
730 | ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; | |
731 | ebuf->buf = kmalloc(ebuf->size, | |
732 | GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); | |
733 | ||
734 | if (ebuf->buf == NULL) { | |
735 | ebuf->size = PAGE_SIZE; | |
736 | ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); | |
737 | } | |
738 | ||
739 | if (ebuf->buf == NULL) { | |
740 | ebuf->size = 128; | |
741 | ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); | |
742 | } | |
743 | ||
744 | if (ebuf->buf == NULL) | |
745 | return -ENOMEM; | |
746 | ||
747 | ebuf->start = pos; | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
752 | static void i915_error_object_free(struct drm_i915_error_object *obj) | |
753 | { | |
754 | int page; | |
755 | ||
756 | if (obj == NULL) | |
757 | return; | |
758 | ||
759 | for (page = 0; page < obj->page_count; page++) | |
95374d75 | 760 | free_page((unsigned long)obj->pages[page]); |
84734a04 MK |
761 | |
762 | kfree(obj); | |
763 | } | |
764 | ||
765 | static void i915_error_state_free(struct kref *error_ref) | |
766 | { | |
767 | struct drm_i915_error_state *error = container_of(error_ref, | |
768 | typeof(*error), ref); | |
769 | int i; | |
770 | ||
6361f4ba CW |
771 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) { |
772 | struct drm_i915_error_engine *ee = &error->engine[i]; | |
773 | ||
774 | i915_error_object_free(ee->batchbuffer); | |
775 | i915_error_object_free(ee->wa_batchbuffer); | |
776 | i915_error_object_free(ee->ringbuffer); | |
777 | i915_error_object_free(ee->hws_page); | |
778 | i915_error_object_free(ee->ctx); | |
779 | i915_error_object_free(ee->wa_ctx); | |
780 | ||
781 | kfree(ee->requests); | |
19eb9189 CW |
782 | if (!IS_ERR_OR_NULL(ee->waiters)) |
783 | kfree(ee->waiters); | |
84734a04 MK |
784 | } |
785 | ||
51d545d0 | 786 | i915_error_object_free(error->semaphore); |
27b85bea | 787 | i915_error_object_free(error->guc_log); |
0b37a9a9 | 788 | |
c0ce4663 | 789 | for (i = 0; i < ARRAY_SIZE(error->active_bo); i++) |
0b37a9a9 | 790 | kfree(error->active_bo[i]); |
0b37a9a9 | 791 | kfree(error->pinned_bo); |
c0ce4663 | 792 | |
84734a04 MK |
793 | kfree(error->overlay); |
794 | kfree(error->display); | |
795 | kfree(error); | |
796 | } | |
797 | ||
798 | static struct drm_i915_error_object * | |
95374d75 | 799 | i915_error_object_create(struct drm_i915_private *i915, |
058d88c4 | 800 | struct i915_vma *vma) |
84734a04 | 801 | { |
95374d75 CW |
802 | struct i915_ggtt *ggtt = &i915->ggtt; |
803 | const u64 slot = ggtt->error_capture.start; | |
84734a04 | 804 | struct drm_i915_error_object *dst; |
0a97015d | 805 | struct z_stream_s zstream; |
95374d75 CW |
806 | unsigned long num_pages; |
807 | struct sgt_iter iter; | |
808 | dma_addr_t dma; | |
84734a04 | 809 | |
058d88c4 CW |
810 | if (!vma) |
811 | return NULL; | |
812 | ||
95374d75 | 813 | num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; |
0a97015d | 814 | num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ |
95374d75 CW |
815 | dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), |
816 | GFP_ATOMIC | __GFP_NOWARN); | |
058d88c4 | 817 | if (!dst) |
84734a04 MK |
818 | return NULL; |
819 | ||
03382dfb CW |
820 | dst->gtt_offset = vma->node.start; |
821 | dst->gtt_size = vma->node.size; | |
95374d75 | 822 | dst->page_count = 0; |
0a97015d CW |
823 | dst->unused = 0; |
824 | ||
825 | if (!compress_init(&zstream)) { | |
826 | kfree(dst); | |
827 | return NULL; | |
828 | } | |
03382dfb | 829 | |
95374d75 CW |
830 | for_each_sgt_dma(dma, iter, vma->pages) { |
831 | void __iomem *s; | |
832 | int ret; | |
b3c3f5e6 | 833 | |
95374d75 CW |
834 | ggtt->base.insert_page(&ggtt->base, dma, slot, |
835 | I915_CACHE_NONE, 0); | |
b3c3f5e6 | 836 | |
95374d75 | 837 | s = io_mapping_map_atomic_wc(&ggtt->mappable, slot); |
0a97015d | 838 | ret = compress_page(&zstream, (void __force *)s, dst); |
95374d75 | 839 | io_mapping_unmap_atomic(s); |
84734a04 | 840 | |
95374d75 | 841 | if (ret) |
84734a04 | 842 | goto unwind; |
84734a04 | 843 | } |
95374d75 | 844 | goto out; |
84734a04 MK |
845 | |
846 | unwind: | |
95374d75 CW |
847 | while (dst->page_count--) |
848 | free_page((unsigned long)dst->pages[dst->page_count]); | |
84734a04 | 849 | kfree(dst); |
95374d75 CW |
850 | dst = NULL; |
851 | ||
852 | out: | |
0a97015d | 853 | compress_fini(&zstream, dst); |
4fb84d99 | 854 | ggtt->base.clear_range(&ggtt->base, slot, PAGE_SIZE); |
95374d75 | 855 | return dst; |
84734a04 | 856 | } |
84734a04 | 857 | |
d72d908b CW |
858 | /* The error capture is special as tries to run underneath the normal |
859 | * locking rules - so we use the raw version of the i915_gem_active lookup. | |
860 | */ | |
861 | static inline uint32_t | |
862 | __active_get_seqno(struct i915_gem_active *active) | |
863 | { | |
24327f83 JL |
864 | struct drm_i915_gem_request *request; |
865 | ||
866 | request = __i915_gem_active_peek(active); | |
867 | return request ? request->global_seqno : 0; | |
d72d908b CW |
868 | } |
869 | ||
870 | static inline int | |
871 | __active_get_engine_id(struct i915_gem_active *active) | |
872 | { | |
24327f83 | 873 | struct drm_i915_gem_request *request; |
d72d908b | 874 | |
24327f83 JL |
875 | request = __i915_gem_active_peek(active); |
876 | return request ? request->engine->id : -1; | |
d72d908b CW |
877 | } |
878 | ||
84734a04 | 879 | static void capture_bo(struct drm_i915_error_buffer *err, |
3a448734 | 880 | struct i915_vma *vma) |
84734a04 | 881 | { |
3a448734 | 882 | struct drm_i915_gem_object *obj = vma->obj; |
b4716185 | 883 | int i; |
3a448734 | 884 | |
84734a04 MK |
885 | err->size = obj->base.size; |
886 | err->name = obj->base.name; | |
d72d908b | 887 | |
666796da | 888 | for (i = 0; i < I915_NUM_ENGINES; i++) |
d07f0e59 CW |
889 | err->rseqno[i] = __active_get_seqno(&vma->last_read[i]); |
890 | err->wseqno = __active_get_seqno(&vma->last_write); | |
891 | err->engine = __active_get_engine_id(&vma->last_write); | |
d72d908b | 892 | |
3a448734 | 893 | err->gtt_offset = vma->node.start; |
84734a04 MK |
894 | err->read_domains = obj->base.read_domains; |
895 | err->write_domain = obj->base.write_domain; | |
49ef5294 | 896 | err->fence_reg = vma->fence ? vma->fence->id : -1; |
3e510a8e | 897 | err->tiling = i915_gem_object_get_tiling(obj); |
a4f5ea64 CW |
898 | err->dirty = obj->mm.dirty; |
899 | err->purgeable = obj->mm.madv != I915_MADV_WILLNEED; | |
5cc9ed4b | 900 | err->userptr = obj->userptr.mm != NULL; |
84734a04 MK |
901 | err->cache_level = obj->cache_level; |
902 | } | |
903 | ||
c0ce4663 CW |
904 | static u32 capture_error_bo(struct drm_i915_error_buffer *err, |
905 | int count, struct list_head *head, | |
906 | bool pinned_only) | |
84734a04 | 907 | { |
ca191b13 | 908 | struct i915_vma *vma; |
84734a04 MK |
909 | int i = 0; |
910 | ||
1c7f4bca | 911 | list_for_each_entry(vma, head, vm_link) { |
c0ce4663 CW |
912 | if (pinned_only && !i915_vma_is_pinned(vma)) |
913 | continue; | |
914 | ||
3a448734 | 915 | capture_bo(err++, vma); |
84734a04 MK |
916 | if (++i == count) |
917 | break; | |
918 | } | |
919 | ||
920 | return i; | |
921 | } | |
922 | ||
011cf577 BW |
923 | /* Generate a semi-unique error code. The code is not meant to have meaning, The |
924 | * code's only purpose is to try to prevent false duplicated bug reports by | |
925 | * grossly estimating a GPU error state. | |
926 | * | |
927 | * TODO Ideally, hashing the batchbuffer would be a very nice way to determine | |
928 | * the hang if we could strip the GTT offset information from it. | |
929 | * | |
930 | * It's only a small step better than a random number in its current form. | |
931 | */ | |
932 | static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, | |
cb383002 | 933 | struct drm_i915_error_state *error, |
6361f4ba | 934 | int *engine_id) |
011cf577 BW |
935 | { |
936 | uint32_t error_code = 0; | |
937 | int i; | |
938 | ||
939 | /* IPEHR would be an ideal way to detect errors, as it's the gross | |
940 | * measure of "the command that hung." However, has some very common | |
941 | * synchronization commands which almost always appear in the case | |
942 | * strictly a client bug. Use instdone to differentiate those some. | |
943 | */ | |
666796da | 944 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
6361f4ba CW |
945 | if (error->engine[i].hangcheck_action == HANGCHECK_HUNG) { |
946 | if (engine_id) | |
947 | *engine_id = i; | |
cb383002 | 948 | |
d636951e BW |
949 | return error->engine[i].ipehr ^ |
950 | error->engine[i].instdone.instdone; | |
cb383002 MK |
951 | } |
952 | } | |
011cf577 BW |
953 | |
954 | return error_code; | |
955 | } | |
956 | ||
c033666a | 957 | static void i915_gem_record_fences(struct drm_i915_private *dev_priv, |
84734a04 MK |
958 | struct drm_i915_error_state *error) |
959 | { | |
84734a04 MK |
960 | int i; |
961 | ||
c033666a | 962 | if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) { |
ce38ab05 | 963 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
eecf613a | 964 | error->fence[i] = I915_READ(FENCE_REG(i)); |
c033666a | 965 | } else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) { |
eecf613a VS |
966 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
967 | error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); | |
c033666a | 968 | } else if (INTEL_GEN(dev_priv) >= 6) { |
eecf613a VS |
969 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
970 | error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); | |
971 | } | |
84734a04 MK |
972 | } |
973 | ||
85e17f59 CW |
974 | static inline u32 |
975 | gen8_engine_sync_index(struct intel_engine_cs *engine, | |
976 | struct intel_engine_cs *other) | |
977 | { | |
978 | int idx; | |
979 | ||
980 | /* | |
981 | * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; | |
982 | * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; | |
983 | * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; | |
984 | * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; | |
985 | * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; | |
986 | */ | |
987 | ||
988 | idx = (other - engine) - 1; | |
989 | if (idx < 0) | |
990 | idx += I915_NUM_ENGINES; | |
991 | ||
992 | return idx; | |
993 | } | |
87f85ebc | 994 | |
6361f4ba | 995 | static void gen8_record_semaphore_state(struct drm_i915_error_state *error, |
0bc40be8 | 996 | struct intel_engine_cs *engine, |
6361f4ba | 997 | struct drm_i915_error_engine *ee) |
0ca36d78 | 998 | { |
6361f4ba | 999 | struct drm_i915_private *dev_priv = engine->i915; |
b4558b46 | 1000 | struct intel_engine_cs *to; |
c3232b18 | 1001 | enum intel_engine_id id; |
0ca36d78 | 1002 | |
51d545d0 | 1003 | if (!error->semaphore) |
6361f4ba | 1004 | return; |
0ca36d78 | 1005 | |
3b3f1650 | 1006 | for_each_engine(to, dev_priv, id) { |
b4558b46 RV |
1007 | int idx; |
1008 | u16 signal_offset; | |
1009 | u32 *tmp; | |
0ca36d78 | 1010 | |
0bc40be8 | 1011 | if (engine == to) |
b4558b46 RV |
1012 | continue; |
1013 | ||
6361f4ba CW |
1014 | signal_offset = |
1015 | (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4; | |
51d545d0 | 1016 | tmp = error->semaphore->pages[0]; |
85e17f59 | 1017 | idx = gen8_engine_sync_index(engine, to); |
b4558b46 | 1018 | |
6361f4ba | 1019 | ee->semaphore_mboxes[idx] = tmp[signal_offset]; |
0ca36d78 BW |
1020 | } |
1021 | } | |
1022 | ||
6361f4ba CW |
1023 | static void gen6_record_semaphore_state(struct intel_engine_cs *engine, |
1024 | struct drm_i915_error_engine *ee) | |
87f85ebc | 1025 | { |
6361f4ba CW |
1026 | struct drm_i915_private *dev_priv = engine->i915; |
1027 | ||
1028 | ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base)); | |
1029 | ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base)); | |
85e17f59 | 1030 | if (HAS_VEBOX(dev_priv)) |
6361f4ba | 1031 | ee->semaphore_mboxes[2] = |
0bc40be8 | 1032 | I915_READ(RING_SYNC_2(engine->mmio_base)); |
87f85ebc BW |
1033 | } |
1034 | ||
6361f4ba CW |
1035 | static void error_record_engine_waiters(struct intel_engine_cs *engine, |
1036 | struct drm_i915_error_engine *ee) | |
688e6c72 CW |
1037 | { |
1038 | struct intel_breadcrumbs *b = &engine->breadcrumbs; | |
1039 | struct drm_i915_error_waiter *waiter; | |
1040 | struct rb_node *rb; | |
1041 | int count; | |
1042 | ||
6361f4ba CW |
1043 | ee->num_waiters = 0; |
1044 | ee->waiters = NULL; | |
688e6c72 | 1045 | |
19eb9189 CW |
1046 | if (RB_EMPTY_ROOT(&b->waiters)) |
1047 | return; | |
1048 | ||
f6168e33 | 1049 | if (!spin_trylock_irq(&b->lock)) { |
19eb9189 CW |
1050 | ee->waiters = ERR_PTR(-EDEADLK); |
1051 | return; | |
1052 | } | |
1053 | ||
688e6c72 CW |
1054 | count = 0; |
1055 | for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb)) | |
1056 | count++; | |
f6168e33 | 1057 | spin_unlock_irq(&b->lock); |
688e6c72 CW |
1058 | |
1059 | waiter = NULL; | |
1060 | if (count) | |
1061 | waiter = kmalloc_array(count, | |
1062 | sizeof(struct drm_i915_error_waiter), | |
1063 | GFP_ATOMIC); | |
1064 | if (!waiter) | |
1065 | return; | |
1066 | ||
f6168e33 | 1067 | if (!spin_trylock_irq(&b->lock)) { |
19eb9189 CW |
1068 | kfree(waiter); |
1069 | ee->waiters = ERR_PTR(-EDEADLK); | |
1070 | return; | |
1071 | } | |
688e6c72 | 1072 | |
19eb9189 | 1073 | ee->waiters = waiter; |
688e6c72 CW |
1074 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
1075 | struct intel_wait *w = container_of(rb, typeof(*w), node); | |
1076 | ||
1077 | strcpy(waiter->comm, w->tsk->comm); | |
1078 | waiter->pid = w->tsk->pid; | |
1079 | waiter->seqno = w->seqno; | |
1080 | waiter++; | |
1081 | ||
6361f4ba | 1082 | if (++ee->num_waiters == count) |
688e6c72 CW |
1083 | break; |
1084 | } | |
f6168e33 | 1085 | spin_unlock_irq(&b->lock); |
688e6c72 CW |
1086 | } |
1087 | ||
6361f4ba CW |
1088 | static void error_record_engine_registers(struct drm_i915_error_state *error, |
1089 | struct intel_engine_cs *engine, | |
1090 | struct drm_i915_error_engine *ee) | |
84734a04 | 1091 | { |
6361f4ba CW |
1092 | struct drm_i915_private *dev_priv = engine->i915; |
1093 | ||
c033666a | 1094 | if (INTEL_GEN(dev_priv) >= 6) { |
6361f4ba CW |
1095 | ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); |
1096 | ee->fault_reg = I915_READ(RING_FAULT_REG(engine)); | |
c033666a | 1097 | if (INTEL_GEN(dev_priv) >= 8) |
6361f4ba | 1098 | gen8_record_semaphore_state(error, engine, ee); |
0ca36d78 | 1099 | else |
6361f4ba | 1100 | gen6_record_semaphore_state(engine, ee); |
4e5aabfd BW |
1101 | } |
1102 | ||
c033666a | 1103 | if (INTEL_GEN(dev_priv) >= 4) { |
6361f4ba CW |
1104 | ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base)); |
1105 | ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base)); | |
1106 | ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); | |
6361f4ba CW |
1107 | ee->instps = I915_READ(RING_INSTPS(engine->mmio_base)); |
1108 | ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); | |
c033666a | 1109 | if (INTEL_GEN(dev_priv) >= 8) { |
6361f4ba CW |
1110 | ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32; |
1111 | ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32; | |
13ffadd1 | 1112 | } |
6361f4ba | 1113 | ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base)); |
84734a04 | 1114 | } else { |
6361f4ba CW |
1115 | ee->faddr = I915_READ(DMA_FADD_I8XX); |
1116 | ee->ipeir = I915_READ(IPEIR); | |
1117 | ee->ipehr = I915_READ(IPEHR); | |
84734a04 MK |
1118 | } |
1119 | ||
0e704476 | 1120 | intel_engine_get_instdone(engine, &ee->instdone); |
d636951e | 1121 | |
6361f4ba CW |
1122 | ee->waiting = intel_engine_has_waiter(engine); |
1123 | ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base)); | |
7e37f889 | 1124 | ee->acthd = intel_engine_get_active_head(engine); |
6361f4ba | 1125 | ee->seqno = intel_engine_get_seqno(engine); |
cb399eab | 1126 | ee->last_seqno = intel_engine_last_submit(engine); |
6361f4ba CW |
1127 | ee->start = I915_READ_START(engine); |
1128 | ee->head = I915_READ_HEAD(engine); | |
1129 | ee->tail = I915_READ_TAIL(engine); | |
1130 | ee->ctl = I915_READ_CTL(engine); | |
21a2c58a CW |
1131 | if (INTEL_GEN(dev_priv) > 2) |
1132 | ee->mode = I915_READ_MODE(engine); | |
84734a04 | 1133 | |
3177659a | 1134 | if (!HWS_NEEDS_PHYSICAL(dev_priv)) { |
f0f59a00 | 1135 | i915_reg_t mmio; |
f3ce3821 | 1136 | |
c033666a | 1137 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 1138 | switch (engine->id) { |
f3ce3821 CW |
1139 | default: |
1140 | case RCS: | |
1141 | mmio = RENDER_HWS_PGA_GEN7; | |
1142 | break; | |
1143 | case BCS: | |
1144 | mmio = BLT_HWS_PGA_GEN7; | |
1145 | break; | |
1146 | case VCS: | |
1147 | mmio = BSD_HWS_PGA_GEN7; | |
1148 | break; | |
1149 | case VECS: | |
1150 | mmio = VEBOX_HWS_PGA_GEN7; | |
1151 | break; | |
1152 | } | |
c033666a | 1153 | } else if (IS_GEN6(engine->i915)) { |
0bc40be8 | 1154 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
f3ce3821 CW |
1155 | } else { |
1156 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 1157 | mmio = RING_HWS_PGA(engine->mmio_base); |
f3ce3821 CW |
1158 | } |
1159 | ||
6361f4ba | 1160 | ee->hws = I915_READ(mmio); |
f3ce3821 CW |
1161 | } |
1162 | ||
6361f4ba CW |
1163 | ee->hangcheck_score = engine->hangcheck.score; |
1164 | ee->hangcheck_action = engine->hangcheck.action; | |
6c7a01ec | 1165 | |
c033666a | 1166 | if (USES_PPGTT(dev_priv)) { |
6c7a01ec BW |
1167 | int i; |
1168 | ||
6361f4ba | 1169 | ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine)); |
6c7a01ec | 1170 | |
c033666a | 1171 | if (IS_GEN6(dev_priv)) |
6361f4ba | 1172 | ee->vm_info.pp_dir_base = |
0bc40be8 | 1173 | I915_READ(RING_PP_DIR_BASE_READ(engine)); |
c033666a | 1174 | else if (IS_GEN7(dev_priv)) |
6361f4ba | 1175 | ee->vm_info.pp_dir_base = |
0bc40be8 | 1176 | I915_READ(RING_PP_DIR_BASE(engine)); |
c033666a | 1177 | else if (INTEL_GEN(dev_priv) >= 8) |
6c7a01ec | 1178 | for (i = 0; i < 4; i++) { |
6361f4ba | 1179 | ee->vm_info.pdp[i] = |
0bc40be8 | 1180 | I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
6361f4ba CW |
1181 | ee->vm_info.pdp[i] <<= 32; |
1182 | ee->vm_info.pdp[i] |= | |
0bc40be8 | 1183 | I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
6c7a01ec | 1184 | } |
6c7a01ec | 1185 | } |
84734a04 MK |
1186 | } |
1187 | ||
35ca039e CW |
1188 | static void record_request(struct drm_i915_gem_request *request, |
1189 | struct drm_i915_error_request *erq) | |
1190 | { | |
1191 | erq->context = request->ctx->hw_id; | |
65e4760e | 1192 | erq->seqno = request->global_seqno; |
35ca039e CW |
1193 | erq->jiffies = request->emitted_jiffies; |
1194 | erq->head = request->head; | |
1195 | erq->tail = request->tail; | |
1196 | ||
1197 | rcu_read_lock(); | |
1198 | erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0; | |
1199 | rcu_read_unlock(); | |
1200 | } | |
1201 | ||
57bc699d CW |
1202 | static void engine_record_requests(struct intel_engine_cs *engine, |
1203 | struct drm_i915_gem_request *first, | |
1204 | struct drm_i915_error_engine *ee) | |
1205 | { | |
1206 | struct drm_i915_gem_request *request; | |
1207 | int count; | |
1208 | ||
1209 | count = 0; | |
1210 | request = first; | |
73cb9701 | 1211 | list_for_each_entry_from(request, &engine->timeline->requests, link) |
57bc699d CW |
1212 | count++; |
1213 | if (!count) | |
1214 | return; | |
1215 | ||
1216 | ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC); | |
1217 | if (!ee->requests) | |
1218 | return; | |
1219 | ||
1220 | ee->num_requests = count; | |
1221 | ||
1222 | count = 0; | |
1223 | request = first; | |
73cb9701 | 1224 | list_for_each_entry_from(request, &engine->timeline->requests, link) { |
57bc699d CW |
1225 | if (count >= ee->num_requests) { |
1226 | /* | |
1227 | * If the ring request list was changed in | |
1228 | * between the point where the error request | |
1229 | * list was created and dimensioned and this | |
1230 | * point then just exit early to avoid crashes. | |
1231 | * | |
1232 | * We don't need to communicate that the | |
1233 | * request list changed state during error | |
1234 | * state capture and that the error state is | |
1235 | * slightly incorrect as a consequence since we | |
1236 | * are typically only interested in the request | |
1237 | * list state at the point of error state | |
1238 | * capture, not in any changes happening during | |
1239 | * the capture. | |
1240 | */ | |
1241 | break; | |
1242 | } | |
1243 | ||
35ca039e | 1244 | record_request(request, &ee->requests[count++]); |
57bc699d CW |
1245 | } |
1246 | ee->num_requests = count; | |
1247 | } | |
1248 | ||
35ca039e CW |
1249 | static void error_record_engine_execlists(struct intel_engine_cs *engine, |
1250 | struct drm_i915_error_engine *ee) | |
1251 | { | |
1252 | unsigned int n; | |
1253 | ||
1254 | for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) | |
1255 | if (engine->execlist_port[n].request) | |
1256 | record_request(engine->execlist_port[n].request, | |
1257 | &ee->execlist[n]); | |
1258 | } | |
1259 | ||
c033666a | 1260 | static void i915_gem_record_rings(struct drm_i915_private *dev_priv, |
84734a04 MK |
1261 | struct drm_i915_error_state *error) |
1262 | { | |
72e96d64 | 1263 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
57bc699d | 1264 | int i; |
84734a04 | 1265 | |
51d545d0 | 1266 | error->semaphore = |
058d88c4 | 1267 | i915_error_object_create(dev_priv, dev_priv->semaphore); |
6361f4ba | 1268 | |
666796da | 1269 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
3b3f1650 | 1270 | struct intel_engine_cs *engine = dev_priv->engine[i]; |
6361f4ba | 1271 | struct drm_i915_error_engine *ee = &error->engine[i]; |
57bc699d | 1272 | struct drm_i915_gem_request *request; |
372fbb8e | 1273 | |
6361f4ba CW |
1274 | ee->pid = -1; |
1275 | ee->engine_id = -1; | |
eee73b46 | 1276 | |
3b3f1650 | 1277 | if (!engine) |
372fbb8e CW |
1278 | continue; |
1279 | ||
6361f4ba | 1280 | ee->engine_id = i; |
372fbb8e | 1281 | |
6361f4ba CW |
1282 | error_record_engine_registers(error, engine, ee); |
1283 | error_record_engine_waiters(engine, ee); | |
35ca039e | 1284 | error_record_engine_execlists(engine, ee); |
84734a04 | 1285 | |
e2f80391 | 1286 | request = i915_gem_find_active_request(engine); |
ab0e7ff9 | 1287 | if (request) { |
7e37f889 | 1288 | struct intel_ring *ring; |
c84455b4 | 1289 | struct pid *pid; |
ae6c4806 | 1290 | |
c0ce4663 | 1291 | ee->vm = request->ctx->ppgtt ? |
bc3d6744 | 1292 | &request->ctx->ppgtt->base : &ggtt->base; |
ae6c4806 | 1293 | |
ab0e7ff9 CW |
1294 | /* We need to copy these to an anonymous buffer |
1295 | * as the simplest method to avoid being overwritten | |
1296 | * by userspace. | |
1297 | */ | |
6361f4ba | 1298 | ee->batchbuffer = |
ab0e7ff9 | 1299 | i915_error_object_create(dev_priv, |
058d88c4 | 1300 | request->batch); |
ab0e7ff9 | 1301 | |
2d1fe073 | 1302 | if (HAS_BROKEN_CS_TLB(dev_priv)) |
6361f4ba | 1303 | ee->wa_batchbuffer = |
058d88c4 CW |
1304 | i915_error_object_create(dev_priv, |
1305 | engine->scratch); | |
ab0e7ff9 | 1306 | |
058d88c4 CW |
1307 | ee->ctx = |
1308 | i915_error_object_create(dev_priv, | |
1309 | request->ctx->engine[i].state); | |
546b1b6a | 1310 | |
c84455b4 CW |
1311 | pid = request->ctx->pid; |
1312 | if (pid) { | |
ab0e7ff9 CW |
1313 | struct task_struct *task; |
1314 | ||
1315 | rcu_read_lock(); | |
c84455b4 | 1316 | task = pid_task(pid, PIDTYPE_PID); |
ab0e7ff9 | 1317 | if (task) { |
6361f4ba CW |
1318 | strcpy(ee->comm, task->comm); |
1319 | ee->pid = task->pid; | |
ab0e7ff9 CW |
1320 | } |
1321 | rcu_read_unlock(); | |
1322 | } | |
84734a04 | 1323 | |
bc3d6744 CW |
1324 | error->simulated |= |
1325 | request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE; | |
1326 | ||
cdb324bd CW |
1327 | ee->rq_head = request->head; |
1328 | ee->rq_post = request->postfix; | |
1329 | ee->rq_tail = request->tail; | |
1330 | ||
1dae2dfb CW |
1331 | ring = request->ring; |
1332 | ee->cpu_ring_head = ring->head; | |
1333 | ee->cpu_ring_tail = ring->tail; | |
6361f4ba | 1334 | ee->ringbuffer = |
058d88c4 | 1335 | i915_error_object_create(dev_priv, ring->vma); |
57bc699d CW |
1336 | |
1337 | engine_record_requests(engine, request, ee); | |
ba6e0418 | 1338 | } |
84734a04 | 1339 | |
6361f4ba | 1340 | ee->hws_page = |
058d88c4 CW |
1341 | i915_error_object_create(dev_priv, |
1342 | engine->status_page.vma); | |
84734a04 | 1343 | |
058d88c4 CW |
1344 | ee->wa_ctx = |
1345 | i915_error_object_create(dev_priv, engine->wa_ctx.vma); | |
84734a04 MK |
1346 | } |
1347 | } | |
1348 | ||
95f5301d BW |
1349 | static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, |
1350 | struct drm_i915_error_state *error, | |
1351 | struct i915_address_space *vm, | |
c0ce4663 | 1352 | int idx) |
84734a04 | 1353 | { |
c0ce4663 | 1354 | struct drm_i915_error_buffer *active_bo; |
95f5301d | 1355 | struct i915_vma *vma; |
c0ce4663 | 1356 | int count; |
84734a04 | 1357 | |
c0ce4663 | 1358 | count = 0; |
1c7f4bca | 1359 | list_for_each_entry(vma, &vm->active_list, vm_link) |
c0ce4663 | 1360 | count++; |
84734a04 | 1361 | |
c0ce4663 CW |
1362 | active_bo = NULL; |
1363 | if (count) | |
1364 | active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC); | |
95f5301d | 1365 | if (active_bo) |
c0ce4663 CW |
1366 | count = capture_error_bo(active_bo, count, &vm->active_list, false); |
1367 | else | |
1368 | count = 0; | |
1369 | ||
1370 | error->active_vm[idx] = vm; | |
1371 | error->active_bo[idx] = active_bo; | |
1372 | error->active_bo_count[idx] = count; | |
95f5301d BW |
1373 | } |
1374 | ||
c0ce4663 CW |
1375 | static void i915_capture_active_buffers(struct drm_i915_private *dev_priv, |
1376 | struct drm_i915_error_state *error) | |
95f5301d | 1377 | { |
c0ce4663 CW |
1378 | int cnt = 0, i, j; |
1379 | ||
1380 | BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo)); | |
1381 | BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm)); | |
1382 | BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count)); | |
1383 | ||
1384 | /* Scan each engine looking for unique active contexts/vm */ | |
1385 | for (i = 0; i < ARRAY_SIZE(error->engine); i++) { | |
1386 | struct drm_i915_error_engine *ee = &error->engine[i]; | |
1387 | bool found; | |
1388 | ||
1389 | if (!ee->vm) | |
1390 | continue; | |
3a448734 | 1391 | |
c0ce4663 CW |
1392 | found = false; |
1393 | for (j = 0; j < i && !found; j++) | |
1394 | found = error->engine[j].vm == ee->vm; | |
1395 | if (!found) | |
1396 | i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++); | |
3a448734 | 1397 | } |
84734a04 MK |
1398 | } |
1399 | ||
c0ce4663 CW |
1400 | static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv, |
1401 | struct drm_i915_error_state *error) | |
1402 | { | |
1403 | struct i915_address_space *vm = &dev_priv->ggtt.base; | |
1404 | struct drm_i915_error_buffer *bo; | |
1405 | struct i915_vma *vma; | |
1406 | int count_inactive, count_active; | |
1407 | ||
1408 | count_inactive = 0; | |
1409 | list_for_each_entry(vma, &vm->active_list, vm_link) | |
1410 | count_inactive++; | |
1411 | ||
1412 | count_active = 0; | |
1413 | list_for_each_entry(vma, &vm->inactive_list, vm_link) | |
1414 | count_active++; | |
1415 | ||
1416 | bo = NULL; | |
1417 | if (count_inactive + count_active) | |
1418 | bo = kcalloc(count_inactive + count_active, | |
1419 | sizeof(*bo), GFP_ATOMIC); | |
1420 | if (!bo) | |
1421 | return; | |
1422 | ||
1423 | count_inactive = capture_error_bo(bo, count_inactive, | |
1424 | &vm->active_list, true); | |
1425 | count_active = capture_error_bo(bo + count_inactive, count_active, | |
1426 | &vm->inactive_list, true); | |
1427 | error->pinned_bo_count = count_inactive + count_active; | |
1428 | error->pinned_bo = bo; | |
1429 | } | |
1430 | ||
27b85bea AG |
1431 | static void i915_gem_capture_guc_log_buffer(struct drm_i915_private *dev_priv, |
1432 | struct drm_i915_error_state *error) | |
1433 | { | |
1434 | /* Capturing log buf contents won't be useful if logging was disabled */ | |
1435 | if (!dev_priv->guc.log.vma || (i915.guc_log_level < 0)) | |
1436 | return; | |
1437 | ||
1438 | error->guc_log = i915_error_object_create(dev_priv, | |
1439 | dev_priv->guc.log.vma); | |
1440 | } | |
1441 | ||
1d762aad BW |
1442 | /* Capture all registers which don't fit into another category. */ |
1443 | static void i915_capture_reg_state(struct drm_i915_private *dev_priv, | |
1444 | struct drm_i915_error_state *error) | |
84734a04 | 1445 | { |
91c8a326 | 1446 | struct drm_device *dev = &dev_priv->drm; |
885ea5a8 | 1447 | int i; |
84734a04 | 1448 | |
654c90c6 BW |
1449 | /* General organization |
1450 | * 1. Registers specific to a single generation | |
1451 | * 2. Registers which belong to multiple generations | |
1452 | * 3. Feature specific registers. | |
1453 | * 4. Everything else | |
1454 | * Please try to follow the order. | |
1455 | */ | |
84734a04 | 1456 | |
654c90c6 | 1457 | /* 1: Registers specific to a single generation */ |
11a914c2 | 1458 | if (IS_VALLEYVIEW(dev_priv)) { |
885ea5a8 | 1459 | error->gtier[0] = I915_READ(GTIER); |
843db716 | 1460 | error->ier = I915_READ(VLV_IER); |
40181697 | 1461 | error->forcewake = I915_READ_FW(FORCEWAKE_VLV); |
654c90c6 | 1462 | } |
84734a04 | 1463 | |
5db94019 | 1464 | if (IS_GEN7(dev_priv)) |
654c90c6 | 1465 | error->err_int = I915_READ(GEN7_ERR_INT); |
84734a04 | 1466 | |
6c826f34 MK |
1467 | if (INTEL_INFO(dev)->gen >= 8) { |
1468 | error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); | |
1469 | error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); | |
1470 | } | |
1471 | ||
5db94019 | 1472 | if (IS_GEN6(dev_priv)) { |
40181697 | 1473 | error->forcewake = I915_READ_FW(FORCEWAKE); |
91ec5d11 BW |
1474 | error->gab_ctl = I915_READ(GAB_CTL); |
1475 | error->gfx_mode = I915_READ(GFX_MODE); | |
1476 | } | |
84734a04 | 1477 | |
654c90c6 BW |
1478 | /* 2: Registers which belong to multiple generations */ |
1479 | if (INTEL_INFO(dev)->gen >= 7) | |
40181697 | 1480 | error->forcewake = I915_READ_FW(FORCEWAKE_MT); |
84734a04 MK |
1481 | |
1482 | if (INTEL_INFO(dev)->gen >= 6) { | |
654c90c6 | 1483 | error->derrmr = I915_READ(DERRMR); |
84734a04 MK |
1484 | error->error = I915_READ(ERROR_GEN6); |
1485 | error->done_reg = I915_READ(DONE_REG); | |
1486 | } | |
1487 | ||
654c90c6 | 1488 | /* 3: Feature specific registers */ |
5db94019 | 1489 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
91ec5d11 BW |
1490 | error->gam_ecochk = I915_READ(GAM_ECOCHK); |
1491 | error->gac_eco = I915_READ(GAC_ECO_BITS); | |
1492 | } | |
1493 | ||
1494 | /* 4: Everything else */ | |
0031fb96 | 1495 | if (HAS_HW_CONTEXTS(dev_priv)) |
654c90c6 BW |
1496 | error->ccid = I915_READ(CCID); |
1497 | ||
885ea5a8 RV |
1498 | if (INTEL_INFO(dev)->gen >= 8) { |
1499 | error->ier = I915_READ(GEN8_DE_MISC_IER); | |
1500 | for (i = 0; i < 4; i++) | |
1501 | error->gtier[i] = I915_READ(GEN8_GT_IER(i)); | |
6e266956 | 1502 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
843db716 | 1503 | error->ier = I915_READ(DEIER); |
885ea5a8 | 1504 | error->gtier[0] = I915_READ(GTIER); |
5db94019 | 1505 | } else if (IS_GEN2(dev_priv)) { |
843db716 | 1506 | error->ier = I915_READ16(IER); |
11a914c2 | 1507 | } else if (!IS_VALLEYVIEW(dev_priv)) { |
843db716 | 1508 | error->ier = I915_READ(IER); |
654c90c6 | 1509 | } |
654c90c6 BW |
1510 | error->eir = I915_READ(EIR); |
1511 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
1d762aad BW |
1512 | } |
1513 | ||
c033666a | 1514 | static void i915_error_capture_msg(struct drm_i915_private *dev_priv, |
58174462 | 1515 | struct drm_i915_error_state *error, |
14b730fc | 1516 | u32 engine_mask, |
58174462 | 1517 | const char *error_msg) |
cb383002 | 1518 | { |
cb383002 | 1519 | u32 ecode; |
6361f4ba | 1520 | int engine_id = -1, len; |
cb383002 | 1521 | |
6361f4ba | 1522 | ecode = i915_error_generate_code(dev_priv, error, &engine_id); |
cb383002 | 1523 | |
58174462 | 1524 | len = scnprintf(error->error_msg, sizeof(error->error_msg), |
0b5492d6 | 1525 | "GPU HANG: ecode %d:%d:0x%08x", |
6361f4ba | 1526 | INTEL_GEN(dev_priv), engine_id, ecode); |
58174462 | 1527 | |
6361f4ba | 1528 | if (engine_id != -1 && error->engine[engine_id].pid != -1) |
58174462 MK |
1529 | len += scnprintf(error->error_msg + len, |
1530 | sizeof(error->error_msg) - len, | |
1531 | ", in %s [%d]", | |
6361f4ba CW |
1532 | error->engine[engine_id].comm, |
1533 | error->engine[engine_id].pid); | |
58174462 MK |
1534 | |
1535 | scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, | |
1536 | ", reason: %s, action: %s", | |
1537 | error_msg, | |
14b730fc | 1538 | engine_mask ? "reset" : "continue"); |
cb383002 MK |
1539 | } |
1540 | ||
48b031e3 MK |
1541 | static void i915_capture_gen_state(struct drm_i915_private *dev_priv, |
1542 | struct drm_i915_error_state *error) | |
1543 | { | |
eb5be9d0 CW |
1544 | error->iommu = -1; |
1545 | #ifdef CONFIG_INTEL_IOMMU | |
1546 | error->iommu = intel_iommu_gfx_mapped; | |
1547 | #endif | |
48b031e3 | 1548 | error->reset_count = i915_reset_count(&dev_priv->gpu_error); |
62d5d69b | 1549 | error->suspend_count = dev_priv->suspend_count; |
2bd160a1 CW |
1550 | |
1551 | memcpy(&error->device_info, | |
1552 | INTEL_INFO(dev_priv), | |
1553 | sizeof(error->device_info)); | |
48b031e3 MK |
1554 | } |
1555 | ||
9f267eb8 CW |
1556 | static int capture(void *data) |
1557 | { | |
1558 | struct drm_i915_error_state *error = data; | |
1559 | ||
9f267eb8 CW |
1560 | i915_capture_gen_state(error->i915, error); |
1561 | i915_capture_reg_state(error->i915, error); | |
1562 | i915_gem_record_fences(error->i915, error); | |
1563 | i915_gem_record_rings(error->i915, error); | |
1564 | i915_capture_active_buffers(error->i915, error); | |
1565 | i915_capture_pinned_buffers(error->i915, error); | |
27b85bea | 1566 | i915_gem_capture_guc_log_buffer(error->i915, error); |
9f267eb8 CW |
1567 | |
1568 | do_gettimeofday(&error->time); | |
de867c20 CW |
1569 | error->boottime = ktime_to_timeval(ktime_get_boottime()); |
1570 | error->uptime = | |
1571 | ktime_to_timeval(ktime_sub(ktime_get(), | |
1572 | error->i915->gt.last_init_time)); | |
9f267eb8 CW |
1573 | |
1574 | error->overlay = intel_overlay_capture_error_state(error->i915); | |
1575 | error->display = intel_display_capture_error_state(error->i915); | |
1576 | ||
9f267eb8 CW |
1577 | return 0; |
1578 | } | |
1579 | ||
eafc4894 CW |
1580 | #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) |
1581 | ||
1d762aad BW |
1582 | /** |
1583 | * i915_capture_error_state - capture an error record for later analysis | |
1584 | * @dev: drm device | |
1585 | * | |
1586 | * Should be called when an error is detected (either a hang or an error | |
1587 | * interrupt) to capture error state from the time of the error. Fills | |
1588 | * out a structure which becomes available in debugfs for user level tools | |
1589 | * to pick up. | |
1590 | */ | |
c033666a CW |
1591 | void i915_capture_error_state(struct drm_i915_private *dev_priv, |
1592 | u32 engine_mask, | |
58174462 | 1593 | const char *error_msg) |
1d762aad | 1594 | { |
53a4c6b2 | 1595 | static bool warned; |
1d762aad BW |
1596 | struct drm_i915_error_state *error; |
1597 | unsigned long flags; | |
1d762aad | 1598 | |
98a2f411 CW |
1599 | if (!i915.error_capture) |
1600 | return; | |
1601 | ||
9777cca0 CW |
1602 | if (READ_ONCE(dev_priv->gpu_error.first_error)) |
1603 | return; | |
1604 | ||
1d762aad BW |
1605 | /* Account for pipe specific data like PIPE*STAT */ |
1606 | error = kzalloc(sizeof(*error), GFP_ATOMIC); | |
1607 | if (!error) { | |
1608 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); | |
1609 | return; | |
1610 | } | |
1611 | ||
011cf577 | 1612 | kref_init(&error->ref); |
9f267eb8 | 1613 | error->i915 = dev_priv; |
011cf577 | 1614 | |
9f267eb8 | 1615 | stop_machine(capture, error, NULL); |
84734a04 | 1616 | |
c033666a | 1617 | i915_error_capture_msg(dev_priv, error, engine_mask, error_msg); |
cb383002 MK |
1618 | DRM_INFO("%s\n", error->error_msg); |
1619 | ||
bc3d6744 CW |
1620 | if (!error->simulated) { |
1621 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); | |
1622 | if (!dev_priv->gpu_error.first_error) { | |
1623 | dev_priv->gpu_error.first_error = error; | |
1624 | error = NULL; | |
1625 | } | |
1626 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); | |
84734a04 | 1627 | } |
84734a04 | 1628 | |
cb383002 | 1629 | if (error) { |
84734a04 | 1630 | i915_error_state_free(&error->ref); |
cb383002 MK |
1631 | return; |
1632 | } | |
1633 | ||
eafc4894 CW |
1634 | if (!warned && |
1635 | ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { | |
cb383002 MK |
1636 | DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); |
1637 | DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); | |
1638 | DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); | |
1639 | DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); | |
91c8a326 CW |
1640 | DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", |
1641 | dev_priv->drm.primary->index); | |
cb383002 MK |
1642 | warned = true; |
1643 | } | |
84734a04 MK |
1644 | } |
1645 | ||
1646 | void i915_error_state_get(struct drm_device *dev, | |
1647 | struct i915_error_state_file_priv *error_priv) | |
1648 | { | |
fac5e23e | 1649 | struct drm_i915_private *dev_priv = to_i915(dev); |
84734a04 | 1650 | |
5b254c59 | 1651 | spin_lock_irq(&dev_priv->gpu_error.lock); |
84734a04 MK |
1652 | error_priv->error = dev_priv->gpu_error.first_error; |
1653 | if (error_priv->error) | |
1654 | kref_get(&error_priv->error->ref); | |
5b254c59 | 1655 | spin_unlock_irq(&dev_priv->gpu_error.lock); |
84734a04 MK |
1656 | } |
1657 | ||
1658 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv) | |
1659 | { | |
1660 | if (error_priv->error) | |
1661 | kref_put(&error_priv->error->ref, i915_error_state_free); | |
1662 | } | |
1663 | ||
1664 | void i915_destroy_error_state(struct drm_device *dev) | |
1665 | { | |
fac5e23e | 1666 | struct drm_i915_private *dev_priv = to_i915(dev); |
84734a04 | 1667 | struct drm_i915_error_state *error; |
84734a04 | 1668 | |
5b254c59 | 1669 | spin_lock_irq(&dev_priv->gpu_error.lock); |
84734a04 MK |
1670 | error = dev_priv->gpu_error.first_error; |
1671 | dev_priv->gpu_error.first_error = NULL; | |
5b254c59 | 1672 | spin_unlock_irq(&dev_priv->gpu_error.lock); |
84734a04 MK |
1673 | |
1674 | if (error) | |
1675 | kref_put(&error->ref, i915_error_state_free); | |
1676 | } |