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drm/i915: Move common code out of i915_gpu_error.c
[linux-block.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
6361f4ba 33static const char *engine_str(int engine)
84734a04 34{
6361f4ba 35 switch (engine) {
84734a04
MK		 36 case RCS: return "render";
37 case VCS: return "bsd";
38 case BCS: return "blt";
39 case VECS: return "vebox";
845f74a7 40 case VCS2: return "bsd2";
84734a04
MK		 41 default: return "";
42 }
43}
44
84734a04
MK		 45static const char *tiling_flag(int tiling)
46{
47 switch (tiling) {
48 default:
49 case I915_TILING_NONE: return "";
50 case I915_TILING_X: return " X";
51 case I915_TILING_Y: return " Y";
52 }
53}
54
55static const char *dirty_flag(int dirty)
56{
57 return dirty ? " dirty" : "";
58}
59
60static const char *purgeable_flag(int purgeable)
61{
62 return purgeable ? " purgeable" : "";
63}
64
65static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
66{
67
68 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
69 e->err = -ENOSPC;
70 return false;
71 }
72
73 if (e->bytes == e->size - 1 || e->err)
74 return false;
75
76 return true;
77}
78
79static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
80 unsigned len)
81{
82 if (e->pos + len <= e->start) {
83 e->pos += len;
84 return false;
85 }
86
87 /* First vsnprintf needs to fit in its entirety for memmove */
88 if (len >= e->size) {
89 e->err = -EIO;
90 return false;
91 }
92
93 return true;
94}
95
96static void __i915_error_advance(struct drm_i915_error_state_buf *e,
97 unsigned len)
98{
99 /* If this is first printf in this window, adjust it so that
100 * start position matches start of the buffer
101 */
102
103 if (e->pos < e->start) {
104 const size_t off = e->start - e->pos;
105
106 /* Should not happen but be paranoid */
107 if (off > len || e->bytes) {
108 e->err = -EIO;
109 return;
110 }
111
112 memmove(e->buf, e->buf + off, len - off);
113 e->bytes = len - off;
114 e->pos = e->start;
115 return;
116 }
117
118 e->bytes += len;
119 e->pos += len;
120}
121
122static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
123 const char *f, va_list args)
124{
125 unsigned len;
126
127 if (!__i915_error_ok(e))
128 return;
129
130 /* Seek the first printf which is hits start position */
131 if (e->pos < e->start) {
e29bb4eb
CW		 132 va_list tmp;
133
134 va_copy(tmp, args);
1d2cb9a5
MK		 135 len = vsnprintf(NULL, 0, f, tmp);
136 va_end(tmp);
137
138 if (!__i915_error_seek(e, len))
84734a04
MK		 139 return;
140 }
141
142 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
143 if (len >= e->size - e->bytes)
144 len = e->size - e->bytes - 1;
145
146 __i915_error_advance(e, len);
147}
148
149static void i915_error_puts(struct drm_i915_error_state_buf *e,
150 const char *str)
151{
152 unsigned len;
153
154 if (!__i915_error_ok(e))
155 return;
156
157 len = strlen(str);
158
159 /* Seek the first printf which is hits start position */
160 if (e->pos < e->start) {
161 if (!__i915_error_seek(e, len))
162 return;
163 }
164
165 if (len >= e->size - e->bytes)
166 len = e->size - e->bytes - 1;
167 memcpy(e->buf + e->bytes, str, len);
168
169 __i915_error_advance(e, len);
170}
171
172#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
173#define err_puts(e, s) i915_error_puts(e, s)
174
175static void print_error_buffers(struct drm_i915_error_state_buf *m,
176 const char *name,
177 struct drm_i915_error_buffer *err,
178 int count)
179{
b4716185
CW		 180 int i;
181
c0ce4663 182 err_printf(m, "%s [%d]:\n", name, count);
84734a04
MK		 183
184 while (count--) {
e1f12325
MT		 185 err_printf(m, " %08x_%08x %8u %02x %02x [ ",
186 upper_32_bits(err->gtt_offset),
187 lower_32_bits(err->gtt_offset),
84734a04
MK		 188 err->size,
189 err->read_domains,
b4716185 190 err->write_domain);
666796da 191 for (i = 0; i < I915_NUM_ENGINES; i++)
b4716185
CW		 192 err_printf(m, "%02x ", err->rseqno[i]);
193
194 err_printf(m, "] %02x", err->wseqno);
84734a04
MK		 195 err_puts(m, tiling_flag(err->tiling));
196 err_puts(m, dirty_flag(err->dirty));
197 err_puts(m, purgeable_flag(err->purgeable));
5cc9ed4b 198 err_puts(m, err->userptr ? " userptr" : "");
6361f4ba
CW		 199 err_puts(m, err->engine != -1 ? " " : "");
200 err_puts(m, engine_str(err->engine));
0a4cd7c8 201 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
84734a04
MK		 202
203 if (err->name)
204 err_printf(m, " (name: %d)", err->name);
205 if (err->fence_reg != I915_FENCE_REG_NONE)
206 err_printf(m, " (fence: %d)", err->fence_reg);
207
208 err_puts(m, "\n");
209 err++;
210 }
211}
212
7e37f889 213static const char *hangcheck_action_to_str(enum intel_engine_hangcheck_action a)
da661464
MK		 214{
215 switch (a) {
216 case HANGCHECK_IDLE:
217 return "idle";
218 case HANGCHECK_WAIT:
219 return "wait";
220 case HANGCHECK_ACTIVE:
221 return "active";
222 case HANGCHECK_KICK:
223 return "kick";
224 case HANGCHECK_HUNG:
225 return "hung";
226 }
227
228 return "unknown";
229}
230
d636951e
BW		 231static void error_print_instdone(struct drm_i915_error_state_buf *m,
232 struct drm_i915_error_engine *ee)
233{
f9e61372
BW		 234 int slice;
235 int subslice;
236
d636951e
BW		 237 err_printf(m, " INSTDONE: 0x%08x\n",
238 ee->instdone.instdone);
239
240 if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
241 return;
242
243 err_printf(m, " SC_INSTDONE: 0x%08x\n",
244 ee->instdone.slice_common);
245
246 if (INTEL_GEN(m->i915) <= 6)
247 return;
248
f9e61372
BW		 249 for_each_instdone_slice_subslice(m->i915, slice, subslice)
250 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
251 slice, subslice,
252 ee->instdone.sampler[slice][subslice]);
253
254 for_each_instdone_slice_subslice(m->i915, slice, subslice)
255 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
256 slice, subslice,
257 ee->instdone.row[slice][subslice]);
d636951e
BW		 258}
259
6361f4ba
CW		 260static void error_print_engine(struct drm_i915_error_state_buf *m,
261 struct drm_i915_error_engine *ee)
84734a04 262{
6361f4ba
CW		 263 err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
264 err_printf(m, " START: 0x%08x\n", ee->start);
cdb324bd
CW		 265 err_printf(m, " HEAD: 0x%08x\n [0x%08x]", ee->head, ee->rq_head);
266 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n",
267 ee->tail, ee->rq_post, ee->rq_tail);
6361f4ba 268 err_printf(m, " CTL: 0x%08x\n", ee->ctl);
21a2c58a 269 err_printf(m, " MODE: 0x%08x\n", ee->mode);
6361f4ba
CW		 270 err_printf(m, " HWS: 0x%08x\n", ee->hws);
271 err_printf(m, " ACTHD: 0x%08x %08x\n",
272 (u32)(ee->acthd>>32), (u32)ee->acthd);
273 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
274 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
d636951e
BW		 275
276 error_print_instdone(m, ee);
277
03382dfb
CW		 278 if (ee->batchbuffer) {
279 u64 start = ee->batchbuffer->gtt_offset;
280 u64 end = start + ee->batchbuffer->gtt_size;
281
282 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n",
283 upper_32_bits(start), lower_32_bits(start),
284 upper_32_bits(end), lower_32_bits(end));
285 }
6361f4ba 286 if (INTEL_GEN(m->i915) >= 4) {
03382dfb 287 err_printf(m, " BBADDR: 0x%08x_%08x\n",
6361f4ba
CW		 288 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
289 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
290 err_printf(m, " INSTPS: 0x%08x\n", ee->instps);
3dda20a9 291 }
6361f4ba
CW		 292 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
293 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
294 lower_32_bits(ee->faddr));
295 if (INTEL_GEN(m->i915) >= 6) {
296 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
297 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
84734a04 298 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
6361f4ba
CW		 299 ee->semaphore_mboxes[0],
300 ee->semaphore_seqno[0]);
84734a04 301 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
6361f4ba
CW		 302 ee->semaphore_mboxes[1],
303 ee->semaphore_seqno[1]);
304 if (HAS_VEBOX(m->i915)) {
4e5aabfd 305 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
6361f4ba
CW		 306 ee->semaphore_mboxes[2],
307 ee->semaphore_seqno[2]);
4e5aabfd 308 }
84734a04 309 }
6361f4ba
CW		 310 if (USES_PPGTT(m->i915)) {
311 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
6c7a01ec 312
6361f4ba 313 if (INTEL_GEN(m->i915) >= 8) {
6c7a01ec
BW		 314 int i;
315 for (i = 0; i < 4; i++)
316 err_printf(m, " PDP%d: 0x%016llx\n",
6361f4ba 317 i, ee->vm_info.pdp[i]);
6c7a01ec
BW		 318 } else {
319 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
6361f4ba 320 ee->vm_info.pp_dir_base);
6c7a01ec
BW		 321 }
322 }
6361f4ba
CW		 323 err_printf(m, " seqno: 0x%08x\n", ee->seqno);
324 err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno);
325 err_printf(m, " waiting: %s\n", yesno(ee->waiting));
326 err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head);
327 err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail);
da661464 328 err_printf(m, " hangcheck: %s [%d]\n",
6361f4ba
CW		 329 hangcheck_action_to_str(ee->hangcheck_action),
330 ee->hangcheck_score);
84734a04
MK		 331}
332
333void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
334{
335 va_list args;
336
337 va_start(args, f);
338 i915_error_vprintf(e, f, args);
339 va_end(args);
340}
341
ab0e7ff9
CW		 342static void print_error_obj(struct drm_i915_error_state_buf *m,
343 struct drm_i915_error_object *obj)
344{
345 int page, offset, elt;
346
347 for (page = offset = 0; page < obj->page_count; page++) {
348 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
349 err_printf(m, "%08x : %08x\n", offset,
350 obj->pages[page][elt]);
351 offset += 4;
352 }
353 }
354}
355
2bd160a1
CW		 356static void err_print_capabilities(struct drm_i915_error_state_buf *m,
357 const struct intel_device_info *info)
358{
359#define PRINT_FLAG(x) err_printf(m, #x ": %s\n", yesno(info->x))
604db650 360 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
2bd160a1 361#undef PRINT_FLAG
2bd160a1
CW		 362}
363
84734a04
MK		 364int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
365 const struct i915_error_state_file_priv *error_priv)
366{
367 struct drm_device *dev = error_priv->dev;
fac5e23e 368 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 369 struct pci_dev *pdev = dev_priv->drm.pdev;
84734a04 370 struct drm_i915_error_state *error = error_priv->error;
0ca36d78 371 struct drm_i915_error_object *obj;
ab0e7ff9
CW		 372 int i, j, offset, elt;
373 int max_hangcheck_score;
84734a04
MK		 374
375 if (!error) {
376 err_printf(m, "no error state collected\n");
377 goto out;
378 }
379
cb383002 380 err_printf(m, "%s\n", error->error_msg);
84734a04
MK		 381 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
382 error->time.tv_usec);
383 err_printf(m, "Kernel: " UTS_RELEASE "\n");
2bd160a1 384 err_print_capabilities(m, &error->device_info);
ab0e7ff9 385 max_hangcheck_score = 0;
6361f4ba
CW		 386 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
387 if (error->engine[i].hangcheck_score > max_hangcheck_score)
388 max_hangcheck_score = error->engine[i].hangcheck_score;
ab0e7ff9 389 }
6361f4ba
CW		 390 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
391 if (error->engine[i].hangcheck_score == max_hangcheck_score &&
392 error->engine[i].pid != -1) {
ab0e7ff9 393 err_printf(m, "Active process (on ring %s): %s [%d]\n",
6361f4ba
CW		 394 engine_str(i),
395 error->engine[i].comm,
396 error->engine[i].pid);
ab0e7ff9
CW		 397 }
398 }
48b031e3 399 err_printf(m, "Reset count: %u\n", error->reset_count);
62d5d69b 400 err_printf(m, "Suspend count: %u\n", error->suspend_count);
52a05c30
DW		 401 err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
402 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
06e6ff8f 403 err_printf(m, "PCI Subsystem: %04x:%04x\n",
52a05c30
DW		 404 pdev->subsystem_vendor,
405 pdev->subsystem_device);
eb5be9d0 406 err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
0ac7655c
MK		 407
408 if (HAS_CSR(dev)) {
409 struct intel_csr *csr = &dev_priv->csr;
410
411 err_printf(m, "DMC loaded: %s\n",
412 yesno(csr->dmc_payload != NULL));
413 err_printf(m, "DMC fw version: %d.%d\n",
414 CSR_VERSION_MAJOR(csr->version),
415 CSR_VERSION_MINOR(csr->version));
416 }
417
84734a04
MK		 418 err_printf(m, "EIR: 0x%08x\n", error->eir);
419 err_printf(m, "IER: 0x%08x\n", error->ier);
885ea5a8
RV		 420 if (INTEL_INFO(dev)->gen >= 8) {
421 for (i = 0; i < 4; i++)
422 err_printf(m, "GTIER gt %d: 0x%08x\n", i,
423 error->gtier[i]);
424 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
425 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
84734a04
MK		 426 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
427 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
428 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
429 err_printf(m, "CCID: 0x%08x\n", error->ccid);
094f9a54 430 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
84734a04
MK		 431
432 for (i = 0; i < dev_priv->num_fence_regs; i++)
433 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
434
84734a04
MK		 435 if (INTEL_INFO(dev)->gen >= 6) {
436 err_printf(m, "ERROR: 0x%08x\n", error->error);
6c826f34
MK		 437
438 if (INTEL_INFO(dev)->gen >= 8)
439 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
440 error->fault_data1, error->fault_data0);
441
84734a04
MK		 442 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
443 }
444
7e22dbbb 445 if (IS_GEN7(dev))
84734a04
MK		 446 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
447
6361f4ba
CW		 448 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
449 if (error->engine[i].engine_id != -1)
450 error_print_engine(m, &error->engine[i]);
451 }
84734a04 452
c0ce4663
CW		 453 for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
454 char buf[128];
455 int len, first = 1;
3a448734 456
c0ce4663
CW		 457 if (!error->active_vm[i])
458 break;
459
460 len = scnprintf(buf, sizeof(buf), "Active (");
461 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
462 if (error->engine[j].vm != error->active_vm[i])
463 continue;
464
465 len += scnprintf(buf + len, sizeof(buf), "%s%s",
466 first ? "" : ", ",
467 dev_priv->engine[j].name);
468 first = 0;
469 }
470 scnprintf(buf + len, sizeof(buf), ")");
471 print_error_buffers(m, buf,
3a448734
CW		 472 error->active_bo[i],
473 error->active_bo_count[i]);
3a448734 474 }
84734a04 475
c0ce4663
CW		 476 print_error_buffers(m, "Pinned (global)",
477 error->pinned_bo,
478 error->pinned_bo_count);
479
6361f4ba
CW		 480 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
481 struct drm_i915_error_engine *ee = &error->engine[i];
482
483 obj = ee->batchbuffer;
ab0e7ff9 484 if (obj) {
4a570db5 485 err_puts(m, dev_priv->engine[i].name);
6361f4ba 486 if (ee->pid != -1)
ab0e7ff9 487 err_printf(m, " (submitted by %s [%d])",
6361f4ba
CW		 488 ee->comm,
489 ee->pid);
e1f12325
MT		 490 err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
491 upper_32_bits(obj->gtt_offset),
492 lower_32_bits(obj->gtt_offset));
ab0e7ff9
CW		 493 print_error_obj(m, obj);
494 }
495
6361f4ba 496 obj = ee->wa_batchbuffer;
ab0e7ff9
CW		 497 if (obj) {
498 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
4a570db5 499 dev_priv->engine[i].name,
e1f12325 500 lower_32_bits(obj->gtt_offset));
ab0e7ff9 501 print_error_obj(m, obj);
84734a04
MK		 502 }
503
6361f4ba 504 if (ee->num_requests) {
84734a04 505 err_printf(m, "%s --- %d requests\n",
4a570db5 506 dev_priv->engine[i].name,
6361f4ba
CW		 507 ee->num_requests);
508 for (j = 0; j < ee->num_requests; j++) {
c84455b4
CW		 509 err_printf(m, " pid %d, seqno 0x%08x, emitted %ld, head 0x%08x, tail 0x%08x\n",
510 ee->requests[j].pid,
6361f4ba
CW		 511 ee->requests[j].seqno,
512 ee->requests[j].jiffies,
d045446d 513 ee->requests[j].head,
6361f4ba 514 ee->requests[j].tail);
84734a04
MK		 515 }
516 }
517
19eb9189
CW		 518 if (IS_ERR(ee->waiters)) {
519 err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
520 dev_priv->engine[i].name);
521 } else if (ee->num_waiters) {
688e6c72
CW		 522 err_printf(m, "%s --- %d waiters\n",
523 dev_priv->engine[i].name,
6361f4ba
CW		 524 ee->num_waiters);
525 for (j = 0; j < ee->num_waiters; j++) {
688e6c72 526 err_printf(m, " seqno 0x%08x for %s [%d]\n",
6361f4ba
CW		 527 ee->waiters[j].seqno,
528 ee->waiters[j].comm,
529 ee->waiters[j].pid);
688e6c72
CW		 530 }
531 }
532
6361f4ba 533 if ((obj = ee->ringbuffer)) {
84734a04 534 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
4a570db5 535 dev_priv->engine[i].name,
e1f12325 536 lower_32_bits(obj->gtt_offset));
ab0e7ff9 537 print_error_obj(m, obj);
84734a04
MK		 538 }
539
6361f4ba 540 if ((obj = ee->hws_page)) {
3a5a0393
JB		 541 u64 hws_offset = obj->gtt_offset;
542 u32 *hws_page = &obj->pages[0][0];
543
544 if (i915.enable_execlists) {
545 hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
546 hws_page = &obj->pages[LRC_PPHWSP_PN][0];
547 }
d1675198 548 err_printf(m, "%s --- HW Status = 0x%08llx\n",
4a570db5 549 dev_priv->engine[i].name, hws_offset);
f3ce3821
CW		 550 offset = 0;
551 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
552 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
553 offset,
3a5a0393
JB		 554 hws_page[elt],
555 hws_page[elt+1],
556 hws_page[elt+2],
557 hws_page[elt+3]);
a98b7e58 558 offset += 16;
f3ce3821
CW		 559 }
560 }
561
6361f4ba 562 obj = ee->wa_ctx;
f85db059 563 if (obj) {
564 u64 wa_ctx_offset = obj->gtt_offset;
565 u32 *wa_ctx_page = &obj->pages[0][0];
4a570db5 566 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
e2f80391
TU		 567 u32 wa_ctx_size = (engine->wa_ctx.indirect_ctx.size +
568 engine->wa_ctx.per_ctx.size);
f85db059 569
570 err_printf(m, "%s --- WA ctx batch buffer = 0x%08llx\n",
4a570db5 571 dev_priv->engine[i].name, wa_ctx_offset);
f85db059 572 offset = 0;
573 for (elt = 0; elt < wa_ctx_size; elt += 4) {
574 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
575 offset,
576 wa_ctx_page[elt + 0],
577 wa_ctx_page[elt + 1],
578 wa_ctx_page[elt + 2],
579 wa_ctx_page[elt + 3]);
580 offset += 16;
581 }
582 }
583
6361f4ba 584 if ((obj = ee->ctx)) {
84734a04 585 err_printf(m, "%s --- HW Context = 0x%08x\n",
4a570db5 586 dev_priv->engine[i].name,
e1f12325 587 lower_32_bits(obj->gtt_offset));
17d36749 588 print_error_obj(m, obj);
84734a04
MK		 589 }
590 }
591
51d545d0 592 if ((obj = error->semaphore)) {
e1f12325
MT		 593 err_printf(m, "Semaphore page = 0x%08x\n",
594 lower_32_bits(obj->gtt_offset));
0ca36d78
BW		 595 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
596 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
597 elt * 4,
598 obj->pages[0][elt],
599 obj->pages[0][elt+1],
600 obj->pages[0][elt+2],
601 obj->pages[0][elt+3]);
602 }
603 }
604
84734a04
MK		 605 if (error->overlay)
606 intel_overlay_print_error_state(m, error->overlay);
607
608 if (error->display)
609 intel_display_print_error_state(m, dev, error->display);
610
611out:
612 if (m->bytes == 0 && m->err)
613 return m->err;
614
615 return 0;
616}
617
618int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
0a4cd7c8 619 struct drm_i915_private *i915,
84734a04
MK		 620 size_t count, loff_t pos)
621{
622 memset(ebuf, 0, sizeof(*ebuf));
0a4cd7c8 623 ebuf->i915 = i915;
84734a04
MK		 624
625 /* We need to have enough room to store any i915_error_state printf
626 * so that we can move it to start position.
627 */
628 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
629 ebuf->buf = kmalloc(ebuf->size,
630 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
631
632 if (ebuf->buf == NULL) {
633 ebuf->size = PAGE_SIZE;
634 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
635 }
636
637 if (ebuf->buf == NULL) {
638 ebuf->size = 128;
639 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
640 }
641
642 if (ebuf->buf == NULL)
643 return -ENOMEM;
644
645 ebuf->start = pos;
646
647 return 0;
648}
649
650static void i915_error_object_free(struct drm_i915_error_object *obj)
651{
652 int page;
653
654 if (obj == NULL)
655 return;
656
657 for (page = 0; page < obj->page_count; page++)
658 kfree(obj->pages[page]);
659
660 kfree(obj);
661}
662
663static void i915_error_state_free(struct kref *error_ref)
664{
665 struct drm_i915_error_state *error = container_of(error_ref,
666 typeof(*error), ref);
667 int i;
668
6361f4ba
CW		 669 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
670 struct drm_i915_error_engine *ee = &error->engine[i];
671
672 i915_error_object_free(ee->batchbuffer);
673 i915_error_object_free(ee->wa_batchbuffer);
674 i915_error_object_free(ee->ringbuffer);
675 i915_error_object_free(ee->hws_page);
676 i915_error_object_free(ee->ctx);
677 i915_error_object_free(ee->wa_ctx);
678
679 kfree(ee->requests);
19eb9189
CW		 680 if (!IS_ERR_OR_NULL(ee->waiters))
681 kfree(ee->waiters);
84734a04
MK		 682 }
683
51d545d0 684 i915_error_object_free(error->semaphore);
0b37a9a9 685
c0ce4663 686 for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
0b37a9a9 687 kfree(error->active_bo[i]);
0b37a9a9 688 kfree(error->pinned_bo);
c0ce4663 689
84734a04
MK		 690 kfree(error->overlay);
691 kfree(error->display);
692 kfree(error);
693}
694
695static struct drm_i915_error_object *
8ae62dc6 696i915_error_object_create(struct drm_i915_private *dev_priv,
058d88c4 697 struct i915_vma *vma)
84734a04 698{
72e96d64 699 struct i915_ggtt *ggtt = &dev_priv->ggtt;
058d88c4 700 struct drm_i915_gem_object *src;
84734a04 701 struct drm_i915_error_object *dst;
8ae62dc6 702 int num_pages;
b3c3f5e6
CW		 703 bool use_ggtt;
704 int i = 0;
e1f12325 705 u64 reloc_offset;
84734a04 706
058d88c4
CW		 707 if (!vma)
708 return NULL;
709
710 src = vma->obj;
711 if (!src->pages)
84734a04
MK		 712 return NULL;
713
8ae62dc6
CW		 714 num_pages = src->base.size >> PAGE_SHIFT;
715
84734a04 716 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
058d88c4 717 if (!dst)
84734a04
MK		 718 return NULL;
719
03382dfb
CW		 720 dst->gtt_offset = vma->node.start;
721 dst->gtt_size = vma->node.size;
722
723 reloc_offset = dst->gtt_offset;
b3c3f5e6 724 use_ggtt = (src->cache_level == I915_CACHE_NONE &&
058d88c4 725 (vma->flags & I915_VMA_GLOBAL_BIND) &&
72e96d64 726 reloc_offset + num_pages * PAGE_SIZE <= ggtt->mappable_end);
b3c3f5e6
CW		 727
728 /* Cannot access stolen address directly, try to use the aperture */
729 if (src->stolen) {
730 use_ggtt = true;
731
058d88c4 732 if (!(vma->flags & I915_VMA_GLOBAL_BIND))
b3c3f5e6
CW		 733 goto unwind;
734
058d88c4 735 reloc_offset = vma->node.start;
72e96d64 736 if (reloc_offset + num_pages * PAGE_SIZE > ggtt->mappable_end)
b3c3f5e6
CW		 737 goto unwind;
738 }
739
740 /* Cannot access snooped pages through the aperture */
2d1fe073
JL		 741 if (use_ggtt && src->cache_level != I915_CACHE_NONE &&
742 !HAS_LLC(dev_priv))
b3c3f5e6
CW		 743 goto unwind;
744
745 dst->page_count = num_pages;
746 while (num_pages--) {
84734a04
MK		 747 unsigned long flags;
748 void *d;
749
750 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
751 if (d == NULL)
752 goto unwind;
753
754 local_irq_save(flags);
b3c3f5e6 755 if (use_ggtt) {
84734a04
MK		 756 void __iomem *s;
757
758 /* Simply ignore tiling or any overlapping fence.
759 * It's part of the error state, and this hopefully
760 * captures what the GPU read.
761 */
762
f7bbe788 763 s = io_mapping_map_atomic_wc(&ggtt->mappable,
84734a04
MK		 764 reloc_offset);
765 memcpy_fromio(d, s, PAGE_SIZE);
766 io_mapping_unmap_atomic(s);
84734a04
MK		 767 } else {
768 struct page *page;
769 void *s;
770
771 page = i915_gem_object_get_page(src, i);
772
773 drm_clflush_pages(&page, 1);
774
775 s = kmap_atomic(page);
776 memcpy(d, s, PAGE_SIZE);
777 kunmap_atomic(s);
778
779 drm_clflush_pages(&page, 1);
780 }
781 local_irq_restore(flags);
782
b3c3f5e6 783 dst->pages[i++] = d;
84734a04
MK		 784 reloc_offset += PAGE_SIZE;
785 }
84734a04
MK		 786
787 return dst;
788
789unwind:
790 while (i--)
791 kfree(dst->pages[i]);
792 kfree(dst);
793 return NULL;
794}
84734a04 795
d72d908b
CW		 796/* The error capture is special as tries to run underneath the normal
797 * locking rules - so we use the raw version of the i915_gem_active lookup.
798 */
799static inline uint32_t
800__active_get_seqno(struct i915_gem_active *active)
801{
802 return i915_gem_request_get_seqno(__i915_gem_active_peek(active));
803}
804
805static inline int
806__active_get_engine_id(struct i915_gem_active *active)
807{
808 struct intel_engine_cs *engine;
809
810 engine = i915_gem_request_get_engine(__i915_gem_active_peek(active));
811 return engine ? engine->id : -1;
812}
813
84734a04 814static void capture_bo(struct drm_i915_error_buffer *err,
3a448734 815 struct i915_vma *vma)
84734a04 816{
3a448734 817 struct drm_i915_gem_object *obj = vma->obj;
b4716185 818 int i;
3a448734 819
84734a04
MK		 820 err->size = obj->base.size;
821 err->name = obj->base.name;
d72d908b 822
666796da 823 for (i = 0; i < I915_NUM_ENGINES; i++)
d72d908b
CW		 824 err->rseqno[i] = __active_get_seqno(&obj->last_read[i]);
825 err->wseqno = __active_get_seqno(&obj->last_write);
826 err->engine = __active_get_engine_id(&obj->last_write);
827
3a448734 828 err->gtt_offset = vma->node.start;
84734a04
MK		 829 err->read_domains = obj->base.read_domains;
830 err->write_domain = obj->base.write_domain;
49ef5294 831 err->fence_reg = vma->fence ? vma->fence->id : -1;
3e510a8e 832 err->tiling = i915_gem_object_get_tiling(obj);
84734a04
MK		 833 err->dirty = obj->dirty;
834 err->purgeable = obj->madv != I915_MADV_WILLNEED;
5cc9ed4b 835 err->userptr = obj->userptr.mm != NULL;
84734a04
MK		 836 err->cache_level = obj->cache_level;
837}
838
c0ce4663
CW		 839static u32 capture_error_bo(struct drm_i915_error_buffer *err,
840 int count, struct list_head *head,
841 bool pinned_only)
84734a04 842{
ca191b13 843 struct i915_vma *vma;
84734a04
MK		 844 int i = 0;
845
1c7f4bca 846 list_for_each_entry(vma, head, vm_link) {
c0ce4663
CW		 847 if (pinned_only && !i915_vma_is_pinned(vma))
848 continue;
849
3a448734 850 capture_bo(err++, vma);
84734a04
MK		 851 if (++i == count)
852 break;
853 }
854
855 return i;
856}
857
011cf577
BW		 858/* Generate a semi-unique error code. The code is not meant to have meaning, The
859 * code's only purpose is to try to prevent false duplicated bug reports by
860 * grossly estimating a GPU error state.
861 *
862 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
863 * the hang if we could strip the GTT offset information from it.
864 *
865 * It's only a small step better than a random number in its current form.
866 */
867static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
cb383002 868 struct drm_i915_error_state *error,
6361f4ba 869 int *engine_id)
011cf577
BW		 870{
871 uint32_t error_code = 0;
872 int i;
873
874 /* IPEHR would be an ideal way to detect errors, as it's the gross
875 * measure of "the command that hung." However, has some very common
876 * synchronization commands which almost always appear in the case
877 * strictly a client bug. Use instdone to differentiate those some.
878 */
666796da 879 for (i = 0; i < I915_NUM_ENGINES; i++) {
6361f4ba
CW		 880 if (error->engine[i].hangcheck_action == HANGCHECK_HUNG) {
881 if (engine_id)
882 *engine_id = i;
cb383002 883
d636951e
BW		 884 return error->engine[i].ipehr ^
885 error->engine[i].instdone.instdone;
cb383002
MK		 886 }
887 }
011cf577
BW		 888
889 return error_code;
890}
891
c033666a 892static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
84734a04
MK		 893 struct drm_i915_error_state *error)
894{
84734a04
MK		 895 int i;
896
c033666a 897 if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
ce38ab05 898 for (i = 0; i < dev_priv->num_fence_regs; i++)
eecf613a 899 error->fence[i] = I915_READ(FENCE_REG(i));
c033666a 900 } else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
eecf613a
VS		 901 for (i = 0; i < dev_priv->num_fence_regs; i++)
902 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
c033666a 903 } else if (INTEL_GEN(dev_priv) >= 6) {
eecf613a
VS		 904 for (i = 0; i < dev_priv->num_fence_regs; i++)
905 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
906 }
84734a04
MK		 907}
908
87f85ebc 909
6361f4ba 910static void gen8_record_semaphore_state(struct drm_i915_error_state *error,
0bc40be8 911 struct intel_engine_cs *engine,
6361f4ba 912 struct drm_i915_error_engine *ee)
0ca36d78 913{
6361f4ba 914 struct drm_i915_private *dev_priv = engine->i915;
b4558b46 915 struct intel_engine_cs *to;
c3232b18 916 enum intel_engine_id id;
0ca36d78 917
51d545d0 918 if (!error->semaphore)
6361f4ba 919 return;
0ca36d78 920
c3232b18 921 for_each_engine_id(to, dev_priv, id) {
b4558b46
RV		 922 int idx;
923 u16 signal_offset;
924 u32 *tmp;
0ca36d78 925
0bc40be8 926 if (engine == to)
b4558b46
RV		 927 continue;
928
6361f4ba
CW		 929 signal_offset =
930 (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
51d545d0 931 tmp = error->semaphore->pages[0];
7e37f889 932 idx = intel_engine_sync_index(engine, to);
b4558b46 933
6361f4ba
CW		 934 ee->semaphore_mboxes[idx] = tmp[signal_offset];
935 ee->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
0ca36d78
BW		 936 }
937}
938
6361f4ba
CW		 939static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
940 struct drm_i915_error_engine *ee)
87f85ebc 941{
6361f4ba
CW		 942 struct drm_i915_private *dev_priv = engine->i915;
943
944 ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
945 ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
946 ee->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
947 ee->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
87f85ebc 948
2d1fe073 949 if (HAS_VEBOX(dev_priv)) {
6361f4ba 950 ee->semaphore_mboxes[2] =
0bc40be8 951 I915_READ(RING_SYNC_2(engine->mmio_base));
6361f4ba 952 ee->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
87f85ebc
BW		 953 }
954}
955
6361f4ba
CW		 956static void error_record_engine_waiters(struct intel_engine_cs *engine,
957 struct drm_i915_error_engine *ee)
688e6c72
CW		 958{
959 struct intel_breadcrumbs *b = &engine->breadcrumbs;
960 struct drm_i915_error_waiter *waiter;
961 struct rb_node *rb;
962 int count;
963
6361f4ba
CW		 964 ee->num_waiters = 0;
965 ee->waiters = NULL;
688e6c72 966
19eb9189
CW		 967 if (RB_EMPTY_ROOT(&b->waiters))
968 return;
969
970 if (!spin_trylock(&b->lock)) {
971 ee->waiters = ERR_PTR(-EDEADLK);
972 return;
973 }
974
688e6c72
CW		 975 count = 0;
976 for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
977 count++;
978 spin_unlock(&b->lock);
979
980 waiter = NULL;
981 if (count)
982 waiter = kmalloc_array(count,
983 sizeof(struct drm_i915_error_waiter),
984 GFP_ATOMIC);
985 if (!waiter)
986 return;
987
19eb9189
CW		 988 if (!spin_trylock(&b->lock)) {
989 kfree(waiter);
990 ee->waiters = ERR_PTR(-EDEADLK);
991 return;
992 }
688e6c72 993
19eb9189 994 ee->waiters = waiter;
688e6c72
CW		 995 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
996 struct intel_wait *w = container_of(rb, typeof(*w), node);
997
998 strcpy(waiter->comm, w->tsk->comm);
999 waiter->pid = w->tsk->pid;
1000 waiter->seqno = w->seqno;
1001 waiter++;
1002
6361f4ba 1003 if (++ee->num_waiters == count)
688e6c72
CW		 1004 break;
1005 }
1006 spin_unlock(&b->lock);
1007}
1008
6361f4ba
CW		 1009static void error_record_engine_registers(struct drm_i915_error_state *error,
1010 struct intel_engine_cs *engine,
1011 struct drm_i915_error_engine *ee)
84734a04 1012{
6361f4ba
CW		 1013 struct drm_i915_private *dev_priv = engine->i915;
1014
c033666a 1015 if (INTEL_GEN(dev_priv) >= 6) {
6361f4ba
CW		 1016 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
1017 ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
c033666a 1018 if (INTEL_GEN(dev_priv) >= 8)
6361f4ba 1019 gen8_record_semaphore_state(error, engine, ee);
0ca36d78 1020 else
6361f4ba 1021 gen6_record_semaphore_state(engine, ee);
4e5aabfd
BW		 1022 }
1023
c033666a 1024 if (INTEL_GEN(dev_priv) >= 4) {
6361f4ba
CW		 1025 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1026 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
1027 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
6361f4ba
CW		 1028 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
1029 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
c033666a 1030 if (INTEL_GEN(dev_priv) >= 8) {
6361f4ba
CW		 1031 ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
1032 ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
13ffadd1 1033 }
6361f4ba 1034 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
84734a04 1035 } else {
6361f4ba
CW		 1036 ee->faddr = I915_READ(DMA_FADD_I8XX);
1037 ee->ipeir = I915_READ(IPEIR);
1038 ee->ipehr = I915_READ(IPEHR);
84734a04
MK		 1039 }
1040
0e704476 1041 intel_engine_get_instdone(engine, &ee->instdone);
d636951e 1042
6361f4ba
CW		 1043 ee->waiting = intel_engine_has_waiter(engine);
1044 ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
7e37f889 1045 ee->acthd = intel_engine_get_active_head(engine);
6361f4ba
CW		 1046 ee->seqno = intel_engine_get_seqno(engine);
1047 ee->last_seqno = engine->last_submitted_seqno;
1048 ee->start = I915_READ_START(engine);
1049 ee->head = I915_READ_HEAD(engine);
1050 ee->tail = I915_READ_TAIL(engine);
1051 ee->ctl = I915_READ_CTL(engine);
21a2c58a
CW		 1052 if (INTEL_GEN(dev_priv) > 2)
1053 ee->mode = I915_READ_MODE(engine);
84734a04 1054
3177659a 1055 if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
f0f59a00 1056 i915_reg_t mmio;
f3ce3821 1057
c033666a 1058 if (IS_GEN7(dev_priv)) {
0bc40be8 1059 switch (engine->id) {
f3ce3821
CW		 1060 default:
1061 case RCS:
1062 mmio = RENDER_HWS_PGA_GEN7;
1063 break;
1064 case BCS:
1065 mmio = BLT_HWS_PGA_GEN7;
1066 break;
1067 case VCS:
1068 mmio = BSD_HWS_PGA_GEN7;
1069 break;
1070 case VECS:
1071 mmio = VEBOX_HWS_PGA_GEN7;
1072 break;
1073 }
c033666a 1074 } else if (IS_GEN6(engine->i915)) {
0bc40be8 1075 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
f3ce3821
CW		 1076 } else {
1077 /* XXX: gen8 returns to sanity */
0bc40be8 1078 mmio = RING_HWS_PGA(engine->mmio_base);
f3ce3821
CW		 1079 }
1080
6361f4ba 1081 ee->hws = I915_READ(mmio);
f3ce3821
CW		 1082 }
1083
6361f4ba
CW		 1084 ee->hangcheck_score = engine->hangcheck.score;
1085 ee->hangcheck_action = engine->hangcheck.action;
6c7a01ec 1086
c033666a 1087 if (USES_PPGTT(dev_priv)) {
6c7a01ec
BW		 1088 int i;
1089
6361f4ba 1090 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
6c7a01ec 1091
c033666a 1092 if (IS_GEN6(dev_priv))
6361f4ba 1093 ee->vm_info.pp_dir_base =
0bc40be8 1094 I915_READ(RING_PP_DIR_BASE_READ(engine));
c033666a 1095 else if (IS_GEN7(dev_priv))
6361f4ba 1096 ee->vm_info.pp_dir_base =
0bc40be8 1097 I915_READ(RING_PP_DIR_BASE(engine));
c033666a 1098 else if (INTEL_GEN(dev_priv) >= 8)
6c7a01ec 1099 for (i = 0; i < 4; i++) {
6361f4ba 1100 ee->vm_info.pdp[i] =
0bc40be8 1101 I915_READ(GEN8_RING_PDP_UDW(engine, i));
6361f4ba
CW		 1102 ee->vm_info.pdp[i] <<= 32;
1103 ee->vm_info.pdp[i] |=
0bc40be8 1104 I915_READ(GEN8_RING_PDP_LDW(engine, i));
6c7a01ec 1105 }
6c7a01ec 1106 }
84734a04
MK		 1107}
1108
57bc699d
CW		 1109static void engine_record_requests(struct intel_engine_cs *engine,
1110 struct drm_i915_gem_request *first,
1111 struct drm_i915_error_engine *ee)
1112{
1113 struct drm_i915_gem_request *request;
1114 int count;
1115
1116 count = 0;
1117 request = first;
1118 list_for_each_entry_from(request, &engine->request_list, link)
1119 count++;
1120 if (!count)
1121 return;
1122
1123 ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1124 if (!ee->requests)
1125 return;
1126
1127 ee->num_requests = count;
1128
1129 count = 0;
1130 request = first;
1131 list_for_each_entry_from(request, &engine->request_list, link) {
1132 struct drm_i915_error_request *erq;
1133
1134 if (count >= ee->num_requests) {
1135 /*
1136 * If the ring request list was changed in
1137 * between the point where the error request
1138 * list was created and dimensioned and this
1139 * point then just exit early to avoid crashes.
1140 *
1141 * We don't need to communicate that the
1142 * request list changed state during error
1143 * state capture and that the error state is
1144 * slightly incorrect as a consequence since we
1145 * are typically only interested in the request
1146 * list state at the point of error state
1147 * capture, not in any changes happening during
1148 * the capture.
1149 */
1150 break;
1151 }
1152
1153 erq = &ee->requests[count++];
1154 erq->seqno = request->fence.seqno;
1155 erq->jiffies = request->emitted_jiffies;
1156 erq->head = request->head;
1157 erq->tail = request->tail;
1158
1159 rcu_read_lock();
1160 erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0;
1161 rcu_read_unlock();
1162 }
1163 ee->num_requests = count;
1164}
1165
c033666a 1166static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
84734a04
MK		 1167 struct drm_i915_error_state *error)
1168{
72e96d64 1169 struct i915_ggtt *ggtt = &dev_priv->ggtt;
57bc699d 1170 int i;
84734a04 1171
51d545d0 1172 error->semaphore =
058d88c4 1173 i915_error_object_create(dev_priv, dev_priv->semaphore);
6361f4ba 1174
666796da 1175 for (i = 0; i < I915_NUM_ENGINES; i++) {
4a570db5 1176 struct intel_engine_cs *engine = &dev_priv->engine[i];
6361f4ba 1177 struct drm_i915_error_engine *ee = &error->engine[i];
57bc699d 1178 struct drm_i915_gem_request *request;
372fbb8e 1179
6361f4ba
CW		 1180 ee->pid = -1;
1181 ee->engine_id = -1;
eee73b46 1182
c033666a 1183 if (!intel_engine_initialized(engine))
372fbb8e
CW		 1184 continue;
1185
6361f4ba 1186 ee->engine_id = i;
372fbb8e 1187
6361f4ba
CW		 1188 error_record_engine_registers(error, engine, ee);
1189 error_record_engine_waiters(engine, ee);
84734a04 1190
e2f80391 1191 request = i915_gem_find_active_request(engine);
ab0e7ff9 1192 if (request) {
7e37f889 1193 struct intel_ring *ring;
c84455b4 1194 struct pid *pid;
ae6c4806 1195
c0ce4663 1196 ee->vm = request->ctx->ppgtt ?
bc3d6744 1197 &request->ctx->ppgtt->base : &ggtt->base;
ae6c4806 1198
ab0e7ff9
CW		 1199 /* We need to copy these to an anonymous buffer
1200 * as the simplest method to avoid being overwritten
1201 * by userspace.
1202 */
6361f4ba 1203 ee->batchbuffer =
ab0e7ff9 1204 i915_error_object_create(dev_priv,
058d88c4 1205 request->batch);
ab0e7ff9 1206
2d1fe073 1207 if (HAS_BROKEN_CS_TLB(dev_priv))
6361f4ba 1208 ee->wa_batchbuffer =
058d88c4
CW		 1209 i915_error_object_create(dev_priv,
1210 engine->scratch);
ab0e7ff9 1211
058d88c4
CW		 1212 ee->ctx =
1213 i915_error_object_create(dev_priv,
1214 request->ctx->engine[i].state);
546b1b6a 1215
c84455b4
CW		 1216 pid = request->ctx->pid;
1217 if (pid) {
ab0e7ff9
CW		 1218 struct task_struct *task;
1219
1220 rcu_read_lock();
c84455b4 1221 task = pid_task(pid, PIDTYPE_PID);
ab0e7ff9 1222 if (task) {
6361f4ba
CW		 1223 strcpy(ee->comm, task->comm);
1224 ee->pid = task->pid;
ab0e7ff9
CW		 1225 }
1226 rcu_read_unlock();
1227 }
84734a04 1228
bc3d6744
CW		 1229 error->simulated |=
1230 request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;
1231
cdb324bd
CW		 1232 ee->rq_head = request->head;
1233 ee->rq_post = request->postfix;
1234 ee->rq_tail = request->tail;
1235
1dae2dfb
CW		 1236 ring = request->ring;
1237 ee->cpu_ring_head = ring->head;
1238 ee->cpu_ring_tail = ring->tail;
6361f4ba 1239 ee->ringbuffer =
058d88c4 1240 i915_error_object_create(dev_priv, ring->vma);
57bc699d
CW		 1241
1242 engine_record_requests(engine, request, ee);
ba6e0418 1243 }
84734a04 1244
6361f4ba 1245 ee->hws_page =
058d88c4
CW		 1246 i915_error_object_create(dev_priv,
1247 engine->status_page.vma);
84734a04 1248
058d88c4
CW		 1249 ee->wa_ctx =
1250 i915_error_object_create(dev_priv, engine->wa_ctx.vma);
84734a04
MK		 1251 }
1252}
1253
95f5301d
BW		 1254static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1255 struct drm_i915_error_state *error,
1256 struct i915_address_space *vm,
c0ce4663 1257 int idx)
84734a04 1258{
c0ce4663 1259 struct drm_i915_error_buffer *active_bo;
95f5301d 1260 struct i915_vma *vma;
c0ce4663 1261 int count;
84734a04 1262
c0ce4663 1263 count = 0;
1c7f4bca 1264 list_for_each_entry(vma, &vm->active_list, vm_link)
c0ce4663 1265 count++;
84734a04 1266
c0ce4663
CW		 1267 active_bo = NULL;
1268 if (count)
1269 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
95f5301d 1270 if (active_bo)
c0ce4663
CW		 1271 count = capture_error_bo(active_bo, count, &vm->active_list, false);
1272 else
1273 count = 0;
1274
1275 error->active_vm[idx] = vm;
1276 error->active_bo[idx] = active_bo;
1277 error->active_bo_count[idx] = count;
95f5301d
BW		 1278}
1279
c0ce4663
CW		 1280static void i915_capture_active_buffers(struct drm_i915_private *dev_priv,
1281 struct drm_i915_error_state *error)
95f5301d 1282{
c0ce4663
CW		 1283 int cnt = 0, i, j;
1284
1285 BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1286 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1287 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1288
1289 /* Scan each engine looking for unique active contexts/vm */
1290 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1291 struct drm_i915_error_engine *ee = &error->engine[i];
1292 bool found;
1293
1294 if (!ee->vm)
1295 continue;
3a448734 1296
c0ce4663
CW		 1297 found = false;
1298 for (j = 0; j < i && !found; j++)
1299 found = error->engine[j].vm == ee->vm;
1300 if (!found)
1301 i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++);
3a448734 1302 }
84734a04
MK		 1303}
1304
c0ce4663
CW		 1305static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv,
1306 struct drm_i915_error_state *error)
1307{
1308 struct i915_address_space *vm = &dev_priv->ggtt.base;
1309 struct drm_i915_error_buffer *bo;
1310 struct i915_vma *vma;
1311 int count_inactive, count_active;
1312
1313 count_inactive = 0;
1314 list_for_each_entry(vma, &vm->active_list, vm_link)
1315 count_inactive++;
1316
1317 count_active = 0;
1318 list_for_each_entry(vma, &vm->inactive_list, vm_link)
1319 count_active++;
1320
1321 bo = NULL;
1322 if (count_inactive + count_active)
1323 bo = kcalloc(count_inactive + count_active,
1324 sizeof(*bo), GFP_ATOMIC);
1325 if (!bo)
1326 return;
1327
1328 count_inactive = capture_error_bo(bo, count_inactive,
1329 &vm->active_list, true);
1330 count_active = capture_error_bo(bo + count_inactive, count_active,
1331 &vm->inactive_list, true);
1332 error->pinned_bo_count = count_inactive + count_active;
1333 error->pinned_bo = bo;
1334}
1335
1d762aad
BW		 1336/* Capture all registers which don't fit into another category. */
1337static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1338 struct drm_i915_error_state *error)
84734a04 1339{
91c8a326 1340 struct drm_device *dev = &dev_priv->drm;
885ea5a8 1341 int i;
84734a04 1342
654c90c6
BW		 1343 /* General organization
1344 * 1. Registers specific to a single generation
1345 * 2. Registers which belong to multiple generations
1346 * 3. Feature specific registers.
1347 * 4. Everything else
1348 * Please try to follow the order.
1349 */
84734a04 1350
654c90c6
BW		 1351 /* 1: Registers specific to a single generation */
1352 if (IS_VALLEYVIEW(dev)) {
885ea5a8 1353 error->gtier[0] = I915_READ(GTIER);
843db716 1354 error->ier = I915_READ(VLV_IER);
40181697 1355 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
654c90c6 1356 }
84734a04 1357
654c90c6
BW		 1358 if (IS_GEN7(dev))
1359 error->err_int = I915_READ(GEN7_ERR_INT);
84734a04 1360
6c826f34
MK		 1361 if (INTEL_INFO(dev)->gen >= 8) {
1362 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1363 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1364 }
1365
91ec5d11 1366 if (IS_GEN6(dev)) {
40181697 1367 error->forcewake = I915_READ_FW(FORCEWAKE);
91ec5d11
BW		 1368 error->gab_ctl = I915_READ(GAB_CTL);
1369 error->gfx_mode = I915_READ(GFX_MODE);
1370 }
84734a04 1371
654c90c6
BW		 1372 /* 2: Registers which belong to multiple generations */
1373 if (INTEL_INFO(dev)->gen >= 7)
40181697 1374 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
84734a04
MK		 1375
1376 if (INTEL_INFO(dev)->gen >= 6) {
654c90c6 1377 error->derrmr = I915_READ(DERRMR);
84734a04
MK		 1378 error->error = I915_READ(ERROR_GEN6);
1379 error->done_reg = I915_READ(DONE_REG);
1380 }
1381
654c90c6 1382 /* 3: Feature specific registers */
91ec5d11
BW		 1383 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1384 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1385 error->gac_eco = I915_READ(GAC_ECO_BITS);
1386 }
1387
1388 /* 4: Everything else */
654c90c6
BW		 1389 if (HAS_HW_CONTEXTS(dev))
1390 error->ccid = I915_READ(CCID);
1391
885ea5a8
RV		 1392 if (INTEL_INFO(dev)->gen >= 8) {
1393 error->ier = I915_READ(GEN8_DE_MISC_IER);
1394 for (i = 0; i < 4; i++)
1395 error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1396 } else if (HAS_PCH_SPLIT(dev)) {
843db716 1397 error->ier = I915_READ(DEIER);
885ea5a8 1398 error->gtier[0] = I915_READ(GTIER);
843db716
RV		 1399 } else if (IS_GEN2(dev)) {
1400 error->ier = I915_READ16(IER);
1401 } else if (!IS_VALLEYVIEW(dev)) {
1402 error->ier = I915_READ(IER);
654c90c6 1403 }
654c90c6
BW		 1404 error->eir = I915_READ(EIR);
1405 error->pgtbl_er = I915_READ(PGTBL_ER);
1d762aad
BW		 1406}
1407
c033666a 1408static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
58174462 1409 struct drm_i915_error_state *error,
14b730fc 1410 u32 engine_mask,
58174462 1411 const char *error_msg)
cb383002 1412{
cb383002 1413 u32 ecode;
6361f4ba 1414 int engine_id = -1, len;
cb383002 1415
6361f4ba 1416 ecode = i915_error_generate_code(dev_priv, error, &engine_id);
cb383002 1417
58174462 1418 len = scnprintf(error->error_msg, sizeof(error->error_msg),
0b5492d6 1419 "GPU HANG: ecode %d:%d:0x%08x",
6361f4ba 1420 INTEL_GEN(dev_priv), engine_id, ecode);
58174462 1421
6361f4ba 1422 if (engine_id != -1 && error->engine[engine_id].pid != -1)
58174462
MK		 1423 len += scnprintf(error->error_msg + len,
1424 sizeof(error->error_msg) - len,
1425 ", in %s [%d]",
6361f4ba
CW		 1426 error->engine[engine_id].comm,
1427 error->engine[engine_id].pid);
58174462
MK		 1428
1429 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1430 ", reason: %s, action: %s",
1431 error_msg,
14b730fc 1432 engine_mask ? "reset" : "continue");
cb383002
MK		 1433}
1434
48b031e3
MK		 1435static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1436 struct drm_i915_error_state *error)
1437{
eb5be9d0
CW		 1438 error->iommu = -1;
1439#ifdef CONFIG_INTEL_IOMMU
1440 error->iommu = intel_iommu_gfx_mapped;
1441#endif
48b031e3 1442 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
62d5d69b 1443 error->suspend_count = dev_priv->suspend_count;
2bd160a1
CW		 1444
1445 memcpy(&error->device_info,
1446 INTEL_INFO(dev_priv),
1447 sizeof(error->device_info));
48b031e3
MK		 1448}
1449
1d762aad
BW		 1450/**
1451 * i915_capture_error_state - capture an error record for later analysis
1452 * @dev: drm device
1453 *
1454 * Should be called when an error is detected (either a hang or an error
1455 * interrupt) to capture error state from the time of the error. Fills
1456 * out a structure which becomes available in debugfs for user level tools
1457 * to pick up.
1458 */
c033666a
CW		 1459void i915_capture_error_state(struct drm_i915_private *dev_priv,
1460 u32 engine_mask,
58174462 1461 const char *error_msg)
1d762aad 1462{
53a4c6b2 1463 static bool warned;
1d762aad
BW		 1464 struct drm_i915_error_state *error;
1465 unsigned long flags;
1d762aad 1466
9777cca0
CW		 1467 if (READ_ONCE(dev_priv->gpu_error.first_error))
1468 return;
1469
1d762aad
BW		 1470 /* Account for pipe specific data like PIPE*STAT */
1471 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1472 if (!error) {
1473 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1474 return;
1475 }
1476
011cf577
BW		 1477 kref_init(&error->ref);
1478
48b031e3 1479 i915_capture_gen_state(dev_priv, error);
011cf577 1480 i915_capture_reg_state(dev_priv, error);
c033666a
CW		 1481 i915_gem_record_fences(dev_priv, error);
1482 i915_gem_record_rings(dev_priv, error);
c0ce4663
CW		 1483 i915_capture_active_buffers(dev_priv, error);
1484 i915_capture_pinned_buffers(dev_priv, error);
1d762aad 1485
84734a04
MK		 1486 do_gettimeofday(&error->time);
1487
c033666a
CW		 1488 error->overlay = intel_overlay_capture_error_state(dev_priv);
1489 error->display = intel_display_capture_error_state(dev_priv);
84734a04 1490
c033666a 1491 i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
cb383002
MK		 1492 DRM_INFO("%s\n", error->error_msg);
1493
bc3d6744
CW		 1494 if (!error->simulated) {
1495 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1496 if (!dev_priv->gpu_error.first_error) {
1497 dev_priv->gpu_error.first_error = error;
1498 error = NULL;
1499 }
1500 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
84734a04 1501 }
84734a04 1502
cb383002 1503 if (error) {
84734a04 1504 i915_error_state_free(&error->ref);
cb383002
MK		 1505 return;
1506 }
1507
1508 if (!warned) {
1509 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1510 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1511 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1512 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
91c8a326
CW		 1513 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1514 dev_priv->drm.primary->index);
cb383002
MK		 1515 warned = true;
1516 }
84734a04
MK		 1517}
1518
1519void i915_error_state_get(struct drm_device *dev,
1520 struct i915_error_state_file_priv *error_priv)
1521{
fac5e23e 1522 struct drm_i915_private *dev_priv = to_i915(dev);
84734a04 1523
5b254c59 1524 spin_lock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1525 error_priv->error = dev_priv->gpu_error.first_error;
1526 if (error_priv->error)
1527 kref_get(&error_priv->error->ref);
5b254c59 1528 spin_unlock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1529
1530}
1531
1532void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1533{
1534 if (error_priv->error)
1535 kref_put(&error_priv->error->ref, i915_error_state_free);
1536}
1537
1538void i915_destroy_error_state(struct drm_device *dev)
1539{
fac5e23e 1540 struct drm_i915_private *dev_priv = to_i915(dev);
84734a04 1541 struct drm_i915_error_state *error;
84734a04 1542
5b254c59 1543 spin_lock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1544 error = dev_priv->gpu_error.first_error;
1545 dev_priv->gpu_error.first_error = NULL;
5b254c59 1546 spin_unlock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1547
1548 if (error)
1549 kref_put(&error->ref, i915_error_state_free);
1550}
Linux 6.x block layer and io_uring tree(s)