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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
280b713b EA |
28 | #include "linux/string.h" |
29 | #include "linux/bitops.h" | |
673a394b EA |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "i915_drm.h" | |
33 | #include "i915_drv.h" | |
34 | ||
35 | /** @file i915_gem_tiling.c | |
36 | * | |
37 | * Support for managing tiling state of buffer objects. | |
38 | * | |
39 | * The idea behind tiling is to increase cache hit rates by rearranging | |
40 | * pixel data so that a group of pixel accesses are in the same cacheline. | |
41 | * Performance improvement from doing this on the back/depth buffer are on | |
42 | * the order of 30%. | |
43 | * | |
44 | * Intel architectures make this somewhat more complicated, though, by | |
45 | * adjustments made to addressing of data when the memory is in interleaved | |
46 | * mode (matched pairs of DIMMS) to improve memory bandwidth. | |
47 | * For interleaved memory, the CPU sends every sequential 64 bytes | |
48 | * to an alternate memory channel so it can get the bandwidth from both. | |
49 | * | |
50 | * The GPU also rearranges its accesses for increased bandwidth to interleaved | |
51 | * memory, and it matches what the CPU does for non-tiled. However, when tiled | |
52 | * it does it a little differently, since one walks addresses not just in the | |
53 | * X direction but also Y. So, along with alternating channels when bit | |
54 | * 6 of the address flips, it also alternates when other bits flip -- Bits 9 | |
55 | * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) | |
56 | * are common to both the 915 and 965-class hardware. | |
57 | * | |
58 | * The CPU also sometimes XORs in higher bits as well, to improve | |
59 | * bandwidth doing strided access like we do so frequently in graphics. This | |
60 | * is called "Channel XOR Randomization" in the MCH documentation. The result | |
61 | * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address | |
62 | * decode. | |
63 | * | |
64 | * All of this bit 6 XORing has an effect on our memory management, | |
65 | * as we need to make sure that the 3d driver can correctly address object | |
66 | * contents. | |
67 | * | |
68 | * If we don't have interleaved memory, all tiling is safe and no swizzling is | |
69 | * required. | |
70 | * | |
71 | * When bit 17 is XORed in, we simply refuse to tile at all. Bit | |
72 | * 17 is not just a page offset, so as we page an objet out and back in, | |
73 | * individual pages in it will have different bit 17 addresses, resulting in | |
74 | * each 64 bytes being swapped with its neighbor! | |
75 | * | |
76 | * Otherwise, if interleaved, we have to tell the 3d driver what the address | |
77 | * swizzling it needs to do is, since it's writing with the CPU to the pages | |
78 | * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the | |
79 | * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling | |
80 | * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order | |
81 | * to match what the GPU expects. | |
82 | */ | |
83 | ||
84 | /** | |
85 | * Detects bit 6 swizzling of address lookup between IGD access and CPU | |
86 | * access through main memory. | |
87 | */ | |
88 | void | |
89 | i915_gem_detect_bit_6_swizzle(struct drm_device *dev) | |
90 | { | |
91 | drm_i915_private_t *dev_priv = dev->dev_private; | |
92 | uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; | |
93 | uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; | |
94 | ||
95 | if (!IS_I9XX(dev)) { | |
96 | /* As far as we know, the 865 doesn't have these bit 6 | |
97 | * swizzling issues. | |
98 | */ | |
99 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; | |
100 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; | |
568d9a8f | 101 | } else if (IS_MOBILE(dev)) { |
673a394b EA |
102 | uint32_t dcc; |
103 | ||
568d9a8f EA |
104 | /* On mobile 9xx chipsets, channel interleave by the CPU is |
105 | * determined by DCC. For single-channel, neither the CPU | |
106 | * nor the GPU do swizzling. For dual channel interleaved, | |
107 | * the GPU's interleave is bit 9 and 10 for X tiled, and bit | |
108 | * 9 for Y tiled. The CPU's interleave is independent, and | |
109 | * can be based on either bit 11 (haven't seen this yet) or | |
110 | * bit 17 (common). | |
673a394b EA |
111 | */ |
112 | dcc = I915_READ(DCC); | |
113 | switch (dcc & DCC_ADDRESSING_MODE_MASK) { | |
114 | case DCC_ADDRESSING_MODE_SINGLE_CHANNEL: | |
115 | case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC: | |
116 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; | |
117 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; | |
118 | break; | |
119 | case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED: | |
568d9a8f EA |
120 | if (dcc & DCC_CHANNEL_XOR_DISABLE) { |
121 | /* This is the base swizzling by the GPU for | |
122 | * tiled buffers. | |
123 | */ | |
673a394b EA |
124 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
125 | swizzle_y = I915_BIT_6_SWIZZLE_9; | |
568d9a8f EA |
126 | } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { |
127 | /* Bit 11 swizzling by the CPU in addition. */ | |
673a394b EA |
128 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_11; |
129 | swizzle_y = I915_BIT_6_SWIZZLE_9_11; | |
130 | } else { | |
568d9a8f | 131 | /* Bit 17 swizzling by the CPU in addition. */ |
280b713b EA |
132 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; |
133 | swizzle_y = I915_BIT_6_SWIZZLE_9_17; | |
673a394b EA |
134 | } |
135 | break; | |
136 | } | |
137 | if (dcc == 0xffffffff) { | |
138 | DRM_ERROR("Couldn't read from MCHBAR. " | |
139 | "Disabling tiling.\n"); | |
140 | swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; | |
141 | swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; | |
142 | } | |
143 | } else { | |
144 | /* The 965, G33, and newer, have a very flexible memory | |
145 | * configuration. It will enable dual-channel mode | |
146 | * (interleaving) on as much memory as it can, and the GPU | |
147 | * will additionally sometimes enable different bit 6 | |
148 | * swizzling for tiled objects from the CPU. | |
149 | * | |
150 | * Here's what I found on the G965: | |
151 | * slot fill memory size swizzling | |
152 | * 0A 0B 1A 1B 1-ch 2-ch | |
153 | * 512 0 0 0 512 0 O | |
154 | * 512 0 512 0 16 1008 X | |
155 | * 512 0 0 512 16 1008 X | |
156 | * 0 512 0 512 16 1008 X | |
157 | * 1024 1024 1024 0 2048 1024 O | |
158 | * | |
159 | * We could probably detect this based on either the DRB | |
160 | * matching, which was the case for the swizzling required in | |
161 | * the table above, or from the 1-ch value being less than | |
162 | * the minimum size of a rank. | |
163 | */ | |
164 | if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) { | |
165 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; | |
166 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; | |
167 | } else { | |
168 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; | |
169 | swizzle_y = I915_BIT_6_SWIZZLE_9; | |
170 | } | |
171 | } | |
172 | ||
173 | dev_priv->mm.bit_6_swizzle_x = swizzle_x; | |
174 | dev_priv->mm.bit_6_swizzle_y = swizzle_y; | |
175 | } | |
176 | ||
0f973f27 JB |
177 | |
178 | /** | |
179 | * Returns the size of the fence for a tiled object of the given size. | |
180 | */ | |
181 | static int | |
182 | i915_get_fence_size(struct drm_device *dev, int size) | |
183 | { | |
184 | int i; | |
185 | int start; | |
186 | ||
187 | if (IS_I965G(dev)) { | |
188 | /* The 965 can have fences at any page boundary. */ | |
189 | return ALIGN(size, 4096); | |
190 | } else { | |
191 | /* Align the size to a power of two greater than the smallest | |
192 | * fence size. | |
193 | */ | |
194 | if (IS_I9XX(dev)) | |
195 | start = 1024 * 1024; | |
196 | else | |
197 | start = 512 * 1024; | |
198 | ||
199 | for (i = start; i < size; i <<= 1) | |
200 | ; | |
201 | ||
202 | return i; | |
203 | } | |
204 | } | |
205 | ||
206 | /* Check pitch constriants for all chips & tiling formats */ | |
207 | static bool | |
208 | i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) | |
209 | { | |
210 | int tile_width; | |
211 | ||
212 | /* Linear is always fine */ | |
213 | if (tiling_mode == I915_TILING_NONE) | |
214 | return true; | |
215 | ||
e76a16de EA |
216 | if (!IS_I9XX(dev) || |
217 | (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) | |
0f973f27 JB |
218 | tile_width = 128; |
219 | else | |
220 | tile_width = 512; | |
221 | ||
8d7773a3 DV |
222 | /* check maximum stride & object size */ |
223 | if (IS_I965G(dev)) { | |
224 | /* i965 stores the end address of the gtt mapping in the fence | |
225 | * reg, so dont bother to check the size */ | |
226 | if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) | |
227 | return false; | |
228 | } else if (IS_I9XX(dev)) { | |
e76a16de EA |
229 | uint32_t pitch_val = ffs(stride / tile_width) - 1; |
230 | ||
231 | /* XXX: For Y tiling, FENCE_MAX_PITCH_VAL is actually 6 (8KB) | |
232 | * instead of 4 (2KB) on 945s. | |
233 | */ | |
234 | if (pitch_val > I915_FENCE_MAX_PITCH_VAL || | |
8d7773a3 DV |
235 | size > (I830_FENCE_MAX_SIZE_VAL << 20)) |
236 | return false; | |
237 | } else { | |
e76a16de EA |
238 | uint32_t pitch_val = ffs(stride / tile_width) - 1; |
239 | ||
240 | if (pitch_val > I830_FENCE_MAX_PITCH_VAL || | |
8d7773a3 DV |
241 | size > (I830_FENCE_MAX_SIZE_VAL << 19)) |
242 | return false; | |
243 | } | |
244 | ||
0f973f27 JB |
245 | /* 965+ just needs multiples of tile width */ |
246 | if (IS_I965G(dev)) { | |
247 | if (stride & (tile_width - 1)) | |
248 | return false; | |
249 | return true; | |
250 | } | |
251 | ||
252 | /* Pre-965 needs power of two tile widths */ | |
253 | if (stride < tile_width) | |
254 | return false; | |
255 | ||
256 | if (stride & (stride - 1)) | |
257 | return false; | |
258 | ||
259 | /* We don't handle the aperture area covered by the fence being bigger | |
260 | * than the object size. | |
261 | */ | |
262 | if (i915_get_fence_size(dev, size) != size) | |
263 | return false; | |
264 | ||
265 | return true; | |
266 | } | |
267 | ||
673a394b EA |
268 | /** |
269 | * Sets the tiling mode of an object, returning the required swizzling of | |
270 | * bit 6 of addresses in the object. | |
271 | */ | |
272 | int | |
273 | i915_gem_set_tiling(struct drm_device *dev, void *data, | |
274 | struct drm_file *file_priv) | |
275 | { | |
276 | struct drm_i915_gem_set_tiling *args = data; | |
277 | drm_i915_private_t *dev_priv = dev->dev_private; | |
278 | struct drm_gem_object *obj; | |
279 | struct drm_i915_gem_object *obj_priv; | |
280 | ||
281 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
282 | if (obj == NULL) | |
283 | return -EINVAL; | |
284 | obj_priv = obj->driver_private; | |
285 | ||
72daad40 CW |
286 | if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) { |
287 | drm_gem_object_unreference(obj); | |
0f973f27 | 288 | return -EINVAL; |
72daad40 | 289 | } |
0f973f27 | 290 | |
673a394b EA |
291 | mutex_lock(&dev->struct_mutex); |
292 | ||
293 | if (args->tiling_mode == I915_TILING_NONE) { | |
673a394b EA |
294 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
295 | } else { | |
296 | if (args->tiling_mode == I915_TILING_X) | |
297 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; | |
298 | else | |
299 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; | |
280b713b EA |
300 | |
301 | /* Hide bit 17 swizzling from the user. This prevents old Mesa | |
302 | * from aborting the application on sw fallbacks to bit 17, | |
303 | * and we use the pread/pwrite bit17 paths to swizzle for it. | |
304 | * If there was a user that was relying on the swizzle | |
305 | * information for drm_intel_bo_map()ed reads/writes this would | |
306 | * break it, but we don't have any of those. | |
307 | */ | |
308 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) | |
309 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; | |
310 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) | |
311 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; | |
312 | ||
673a394b EA |
313 | /* If we can't handle the swizzling, make it untiled. */ |
314 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) { | |
315 | args->tiling_mode = I915_TILING_NONE; | |
316 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; | |
317 | } | |
318 | } | |
0f973f27 JB |
319 | if (args->tiling_mode != obj_priv->tiling_mode) { |
320 | int ret; | |
321 | ||
322 | /* Unbind the object, as switching tiling means we're | |
323 | * switching the cache organization due to fencing, probably. | |
324 | */ | |
325 | ret = i915_gem_object_unbind(obj); | |
326 | if (ret != 0) { | |
327 | WARN(ret != -ERESTARTSYS, | |
328 | "failed to unbind object for tiling switch"); | |
329 | args->tiling_mode = obj_priv->tiling_mode; | |
330 | mutex_unlock(&dev->struct_mutex); | |
72daad40 | 331 | drm_gem_object_unreference(obj); |
0f973f27 JB |
332 | |
333 | return ret; | |
334 | } | |
335 | obj_priv->tiling_mode = args->tiling_mode; | |
336 | } | |
de151cf6 | 337 | obj_priv->stride = args->stride; |
673a394b | 338 | |
673a394b | 339 | drm_gem_object_unreference(obj); |
d6873102 | 340 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
341 | |
342 | return 0; | |
343 | } | |
344 | ||
345 | /** | |
346 | * Returns the current tiling mode and required bit 6 swizzling for the object. | |
347 | */ | |
348 | int | |
349 | i915_gem_get_tiling(struct drm_device *dev, void *data, | |
350 | struct drm_file *file_priv) | |
351 | { | |
352 | struct drm_i915_gem_get_tiling *args = data; | |
353 | drm_i915_private_t *dev_priv = dev->dev_private; | |
354 | struct drm_gem_object *obj; | |
355 | struct drm_i915_gem_object *obj_priv; | |
356 | ||
357 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
358 | if (obj == NULL) | |
359 | return -EINVAL; | |
360 | obj_priv = obj->driver_private; | |
361 | ||
362 | mutex_lock(&dev->struct_mutex); | |
363 | ||
364 | args->tiling_mode = obj_priv->tiling_mode; | |
365 | switch (obj_priv->tiling_mode) { | |
366 | case I915_TILING_X: | |
367 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; | |
368 | break; | |
369 | case I915_TILING_Y: | |
370 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; | |
371 | break; | |
372 | case I915_TILING_NONE: | |
373 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; | |
374 | break; | |
375 | default: | |
376 | DRM_ERROR("unknown tiling mode\n"); | |
377 | } | |
378 | ||
280b713b EA |
379 | /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ |
380 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) | |
381 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; | |
382 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) | |
383 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; | |
384 | ||
673a394b | 385 | drm_gem_object_unreference(obj); |
d6873102 | 386 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
387 | |
388 | return 0; | |
389 | } | |
280b713b EA |
390 | |
391 | /** | |
392 | * Swap every 64 bytes of this page around, to account for it having a new | |
393 | * bit 17 of its physical address and therefore being interpreted differently | |
394 | * by the GPU. | |
395 | */ | |
396 | static int | |
397 | i915_gem_swizzle_page(struct page *page) | |
398 | { | |
399 | char *vaddr; | |
400 | int i; | |
401 | char temp[64]; | |
402 | ||
403 | vaddr = kmap(page); | |
404 | if (vaddr == NULL) | |
405 | return -ENOMEM; | |
406 | ||
407 | for (i = 0; i < PAGE_SIZE; i += 128) { | |
408 | memcpy(temp, &vaddr[i], 64); | |
409 | memcpy(&vaddr[i], &vaddr[i + 64], 64); | |
410 | memcpy(&vaddr[i + 64], temp, 64); | |
411 | } | |
412 | ||
413 | kunmap(page); | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
418 | void | |
419 | i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj) | |
420 | { | |
421 | struct drm_device *dev = obj->dev; | |
422 | drm_i915_private_t *dev_priv = dev->dev_private; | |
423 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
424 | int page_count = obj->size >> PAGE_SHIFT; | |
425 | int i; | |
426 | ||
427 | if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17) | |
428 | return; | |
429 | ||
430 | if (obj_priv->bit_17 == NULL) | |
431 | return; | |
432 | ||
433 | for (i = 0; i < page_count; i++) { | |
434 | char new_bit_17 = page_to_phys(obj_priv->pages[i]) >> 17; | |
435 | if ((new_bit_17 & 0x1) != | |
436 | (test_bit(i, obj_priv->bit_17) != 0)) { | |
437 | int ret = i915_gem_swizzle_page(obj_priv->pages[i]); | |
438 | if (ret != 0) { | |
439 | DRM_ERROR("Failed to swizzle page\n"); | |
440 | return; | |
441 | } | |
442 | set_page_dirty(obj_priv->pages[i]); | |
443 | } | |
444 | } | |
445 | } | |
446 | ||
447 | void | |
448 | i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj) | |
449 | { | |
450 | struct drm_device *dev = obj->dev; | |
451 | drm_i915_private_t *dev_priv = dev->dev_private; | |
452 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
453 | int page_count = obj->size >> PAGE_SHIFT; | |
454 | int i; | |
455 | ||
456 | if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17) | |
457 | return; | |
458 | ||
459 | if (obj_priv->bit_17 == NULL) { | |
460 | obj_priv->bit_17 = kmalloc(BITS_TO_LONGS(page_count) * | |
461 | sizeof(long), GFP_KERNEL); | |
462 | if (obj_priv->bit_17 == NULL) { | |
463 | DRM_ERROR("Failed to allocate memory for bit 17 " | |
464 | "record\n"); | |
465 | return; | |
466 | } | |
467 | } | |
468 | ||
469 | for (i = 0; i < page_count; i++) { | |
470 | if (page_to_phys(obj_priv->pages[i]) & (1 << 17)) | |
471 | __set_bit(i, obj_priv->bit_17); | |
472 | else | |
473 | __clear_bit(i, obj_priv->bit_17); | |
474 | } | |
475 | } |