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9d0a6fa6 MK |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Mika Kuoppala <mika.kuoppala@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
7c2fa7fa | 29 | #include "i915_gem_render_state.h" |
9d0a6fa6 MK |
30 | #include "intel_renderstate.h" |
31 | ||
4e50f082 | 32 | struct intel_render_state { |
e40f9ee6 | 33 | const struct intel_renderstate_rodata *rodata; |
7c2fa7fa | 34 | struct drm_i915_gem_object *obj; |
a5e85c8a | 35 | struct i915_vma *vma; |
4e50f082 CW |
36 | u32 batch_offset; |
37 | u32 batch_size; | |
38 | u32 aux_offset; | |
39 | u32 aux_size; | |
e40f9ee6 CW |
40 | }; |
41 | ||
9d0a6fa6 | 42 | static const struct intel_renderstate_rodata * |
4e50f082 | 43 | render_state_get_rodata(const struct intel_engine_cs *engine) |
9d0a6fa6 | 44 | { |
7c2fa7fa CW |
45 | if (engine->id != RCS) |
46 | return NULL; | |
47 | ||
4e50f082 | 48 | switch (INTEL_GEN(engine->i915)) { |
9d0a6fa6 MK |
49 | case 6: |
50 | return &gen6_null_state; | |
51 | case 7: | |
52 | return &gen7_null_state; | |
53 | case 8: | |
54 | return &gen8_null_state; | |
ff7a60f2 AR |
55 | case 9: |
56 | return &gen9_null_state; | |
9d0a6fa6 MK |
57 | } |
58 | ||
59 | return NULL; | |
60 | } | |
61 | ||
84e81020 AS |
62 | /* |
63 | * Macro to add commands to auxiliary batch. | |
64 | * This macro only checks for page overflow before inserting the commands, | |
65 | * this is sufficient as the null state generator makes the final batch | |
66 | * with two passes to build command and state separately. At this point | |
67 | * the size of both are known and it compacts them by relocating the state | |
550116d2 | 68 | * right after the commands taking care of alignment so we should sufficient |
84e81020 AS |
69 | * space below them for adding new commands. |
70 | */ | |
71 | #define OUT_BATCH(batch, i, val) \ | |
72 | do { \ | |
4e50f082 CW |
73 | if ((i) >= PAGE_SIZE / sizeof(u32)) \ |
74 | goto err; \ | |
84e81020 AS |
75 | (batch)[(i)++] = (val); \ |
76 | } while(0) | |
77 | ||
4e50f082 CW |
78 | static int render_state_setup(struct intel_render_state *so, |
79 | struct drm_i915_private *i915) | |
1ce826d4 CW |
80 | { |
81 | const struct intel_renderstate_rodata *rodata = so->rodata; | |
82 | unsigned int i = 0, reloc_index = 0; | |
4e50f082 | 83 | unsigned int needs_clflush; |
1ce826d4 CW |
84 | u32 *d; |
85 | int ret; | |
86 | ||
7c2fa7fa | 87 | ret = i915_gem_obj_prepare_shmem_write(so->obj, &needs_clflush); |
9d0a6fa6 MK |
88 | if (ret) |
89 | return ret; | |
90 | ||
7c2fa7fa | 91 | d = kmap_atomic(i915_gem_object_get_dirty_page(so->obj, 0)); |
1ce826d4 | 92 | |
9d0a6fa6 MK |
93 | while (i < rodata->batch_items) { |
94 | u32 s = rodata->batch[i]; | |
95 | ||
1ce826d4 | 96 | if (i * 4 == rodata->reloc[reloc_index]) { |
a5e85c8a | 97 | u64 r = s + so->vma->node.start; |
1ce826d4 | 98 | s = lower_32_bits(r); |
dfc5148f | 99 | if (HAS_64BIT_RELOC(i915)) { |
9d0a6fa6 | 100 | if (i + 1 >= rodata->batch_items || |
4e50f082 CW |
101 | rodata->batch[i + 1] != 0) |
102 | goto err; | |
9d0a6fa6 | 103 | |
1ce826d4 CW |
104 | d[i++] = s; |
105 | s = upper_32_bits(r); | |
9d0a6fa6 MK |
106 | } |
107 | ||
108 | reloc_index++; | |
109 | } | |
110 | ||
1ce826d4 | 111 | d[i++] = s; |
9d0a6fa6 | 112 | } |
84e81020 | 113 | |
4e50f082 CW |
114 | if (rodata->reloc[reloc_index] != -1) { |
115 | DRM_ERROR("only %d relocs resolved\n", reloc_index); | |
116 | goto err; | |
117 | } | |
118 | ||
7c2fa7fa | 119 | so->batch_offset = i915_ggtt_offset(so->vma); |
4e50f082 CW |
120 | so->batch_size = rodata->batch_items * sizeof(u32); |
121 | ||
84e81020 AS |
122 | while (i % CACHELINE_DWORDS) |
123 | OUT_BATCH(d, i, MI_NOOP); | |
124 | ||
4e50f082 | 125 | so->aux_offset = i * sizeof(u32); |
84e81020 | 126 | |
4e50f082 | 127 | if (HAS_POOLED_EU(i915)) { |
33e141ed | 128 | /* |
129 | * We always program 3x6 pool config but depending upon which | |
130 | * subslice is disabled HW drops down to appropriate config | |
131 | * shown below. | |
132 | * | |
133 | * In the below table 2x6 config always refers to | |
134 | * fused-down version, native 2x6 is not available and can | |
135 | * be ignored | |
136 | * | |
137 | * SNo subslices config eu pool configuration | |
138 | * ----------------------------------------------------------- | |
139 | * 1 3 subslices enabled (3x6) - 0x00777000 (9+9) | |
140 | * 2 ss0 disabled (2x6) - 0x00777000 (3+9) | |
141 | * 3 ss1 disabled (2x6) - 0x00770000 (6+6) | |
142 | * 4 ss2 disabled (2x6) - 0x00007000 (9+3) | |
143 | */ | |
144 | u32 eu_pool_config = 0x00777000; | |
145 | ||
146 | OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); | |
147 | OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); | |
148 | OUT_BATCH(d, i, eu_pool_config); | |
149 | OUT_BATCH(d, i, 0); | |
150 | OUT_BATCH(d, i, 0); | |
151 | OUT_BATCH(d, i, 0); | |
152 | } | |
153 | ||
84e81020 | 154 | OUT_BATCH(d, i, MI_BATCH_BUFFER_END); |
4e50f082 CW |
155 | so->aux_size = i * sizeof(u32) - so->aux_offset; |
156 | so->aux_offset += so->batch_offset; | |
84e81020 AS |
157 | /* |
158 | * Since we are sending length, we need to strictly conform to | |
159 | * all requirements. For Gen2 this must be a multiple of 8. | |
160 | */ | |
4e50f082 | 161 | so->aux_size = ALIGN(so->aux_size, 8); |
9d0a6fa6 | 162 | |
4e50f082 CW |
163 | if (needs_clflush) |
164 | drm_clflush_virt_range(d, i * sizeof(u32)); | |
165 | kunmap_atomic(d); | |
dd72bde0 | 166 | |
7c2fa7fa | 167 | ret = i915_gem_object_set_to_gtt_domain(so->obj, false); |
4e50f082 | 168 | out: |
7c2fa7fa | 169 | i915_gem_obj_finish_shmem_access(so->obj); |
dd72bde0 | 170 | return ret; |
4e50f082 CW |
171 | |
172 | err: | |
173 | kunmap_atomic(d); | |
174 | ret = -EINVAL; | |
175 | goto out; | |
9d0a6fa6 MK |
176 | } |
177 | ||
84e81020 AS |
178 | #undef OUT_BATCH |
179 | ||
e61e0f51 | 180 | int i915_gem_render_state_emit(struct i915_request *rq) |
9d0a6fa6 | 181 | { |
7c2fa7fa CW |
182 | struct intel_engine_cs *engine = rq->engine; |
183 | struct intel_render_state so = {}; /* keep the compiler happy */ | |
184 | int err; | |
9d0a6fa6 | 185 | |
7c2fa7fa CW |
186 | so.rodata = render_state_get_rodata(engine); |
187 | if (!so.rodata) | |
4e50f082 | 188 | return 0; |
46470fc9 | 189 | |
7c2fa7fa | 190 | if (so.rodata->batch_items * 4 > PAGE_SIZE) |
15d21db8 | 191 | return -EINVAL; |
564ddb2f | 192 | |
7c2fa7fa CW |
193 | so.obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); |
194 | if (IS_ERR(so.obj)) | |
195 | return PTR_ERR(so.obj); | |
564ddb2f | 196 | |
82ad6443 | 197 | so.vma = i915_vma_instance(so.obj, &engine->i915->ggtt.vm, NULL); |
7c2fa7fa CW |
198 | if (IS_ERR(so.vma)) { |
199 | err = PTR_ERR(so.vma); | |
a5e85c8a | 200 | goto err_obj; |
4e50f082 CW |
201 | } |
202 | ||
7c2fa7fa CW |
203 | err = i915_vma_pin(so.vma, 0, 0, PIN_GLOBAL | PIN_HIGH); |
204 | if (err) | |
205 | goto err_vma; | |
9d0a6fa6 | 206 | |
7c2fa7fa CW |
207 | err = render_state_setup(&so, rq->i915); |
208 | if (err) | |
209 | goto err_unpin; | |
4e50f082 | 210 | |
7c2fa7fa CW |
211 | err = engine->emit_bb_start(rq, |
212 | so.batch_offset, so.batch_size, | |
213 | I915_DISPATCH_SECURE); | |
214 | if (err) | |
15d21db8 | 215 | goto err_unpin; |
9d0a6fa6 | 216 | |
7c2fa7fa CW |
217 | if (so.aux_size > 8) { |
218 | err = engine->emit_bb_start(rq, | |
219 | so.aux_offset, so.aux_size, | |
220 | I915_DISPATCH_SECURE); | |
221 | if (err) | |
15d21db8 | 222 | goto err_unpin; |
84e81020 AS |
223 | } |
224 | ||
a5236978 | 225 | err = i915_vma_move_to_active(so.vma, rq, 0); |
15d21db8 | 226 | err_unpin: |
7c2fa7fa CW |
227 | i915_vma_unpin(so.vma); |
228 | err_vma: | |
229 | i915_vma_close(so.vma); | |
230 | err_obj: | |
231 | __i915_gem_object_release_unless_active(so.obj); | |
232 | return err; | |
4e50f082 | 233 | } |