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drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT
[linux-block.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
CommitLineData
76aaf220
DV		 1/*
2 * Copyright © 2010 Daniel Vetter
c4ac524c 3 * Copyright © 2011-2014 Intel Corporation
76aaf220
DV		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
0e46ce2e 26#include <linux/seq_file.h>
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/i915_drm.h>
76aaf220 29#include "i915_drv.h"
5dda8fa3 30#include "i915_vgpu.h"
76aaf220
DV		 31#include "i915_trace.h"
32#include "intel_drv.h"
33
45f8f69a
TU		 34/**
35 * DOC: Global GTT views
36 *
37 * Background and previous state
38 *
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
42 *
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
46 *
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
49 * (2x2 pages):
50 *
51 * 12
52 * 34
53 *
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
57 *
58 * 1212
59 * 3434
60 *
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
63 *
64 * Implementation and usage
65 *
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
68 *
69 * A new flavour of core GEM functions which work with GGTT bound objects were
ec7adb6e
JL		 70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
45f8f69a
TU		 73 *
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
78 *
79 * Code wanting to add or use a new GGTT view needs to:
80 *
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
84 *
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
88 *
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
92 *
93 */
94
70b9f6f8
DV		 95static int
96i915_get_ggtt_vma_pages(struct i915_vma *vma);
97
fe14d5f4 98const struct i915_ggtt_view i915_ggtt_view_normal;
9abc4648
JL		 99const struct i915_ggtt_view i915_ggtt_view_rotated = {
100 .type = I915_GGTT_VIEW_ROTATED
101};
fe14d5f4 102
cfa7c862
DV		 103static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
104{
1893a71b
CW		 105 bool has_aliasing_ppgtt;
106 bool has_full_ppgtt;
107
108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
1893a71b 110
71ba2d64
YZ		 111 if (intel_vgpu_active(dev))
112 has_full_ppgtt = false; /* emulation is too hard */
113
70ee45e1
DL		 114 /*
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
117 */
118 if (INTEL_INFO(dev)->gen < 9 &&
119 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
cfa7c862
DV		 120 return 0;
121
122 if (enable_ppgtt == 1)
123 return 1;
124
1893a71b 125 if (enable_ppgtt == 2 && has_full_ppgtt)
cfa7c862
DV		 126 return 2;
127
93a25a9e
DV		 128#ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
cfa7c862 132 return 0;
93a25a9e
DV		 133 }
134#endif
135
62942ed7 136 /* Early VLV doesn't have this */
ca2aed6c
VS		 137 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
138 dev->pdev->revision < 0xb) {
62942ed7
JB		 139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
140 return 0;
141 }
142
2f82bbdf
MT		 143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
144 return 2;
145 else
146 return has_aliasing_ppgtt ? 1 : 0;
93a25a9e
DV		 147}
148
70b9f6f8
DV		 149static int ppgtt_bind_vma(struct i915_vma *vma,
150 enum i915_cache_level cache_level,
151 u32 unused)
47552659
DV		 152{
153 u32 pte_flags = 0;
154
155 /* Currently applicable only to VLV */
156 if (vma->obj->gt_ro)
157 pte_flags |= PTE_READ_ONLY;
158
159 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
160 cache_level, pte_flags);
70b9f6f8
DV		 161
162 return 0;
47552659
DV		 163}
164
165static void ppgtt_unbind_vma(struct i915_vma *vma)
166{
167 vma->vm->clear_range(vma->vm,
168 vma->node.start,
169 vma->obj->base.size,
170 true);
171}
6f65e29a 172
2c642b07
DV		 173static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
175 bool valid)
94ec8f61 176{
07749ef3 177 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
94ec8f61 178 pte |= addr;
63c42e56
BW		 179
180 switch (level) {
181 case I915_CACHE_NONE:
fbe5d36e 182 pte |= PPAT_UNCACHED_INDEX;
63c42e56
BW		 183 break;
184 case I915_CACHE_WT:
185 pte |= PPAT_DISPLAY_ELLC_INDEX;
186 break;
187 default:
188 pte |= PPAT_CACHED_INDEX;
189 break;
190 }
191
94ec8f61
BW		 192 return pte;
193}
194
fe36f55d
MK		 195static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
196 const enum i915_cache_level level)
b1fe6673 197{
07749ef3 198 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
b1fe6673
BW		 199 pde |= addr;
200 if (level != I915_CACHE_NONE)
201 pde |= PPAT_CACHED_PDE_INDEX;
202 else
203 pde |= PPAT_UNCACHED_INDEX;
204 return pde;
205}
206
07749ef3
MT		 207static gen6_pte_t snb_pte_encode(dma_addr_t addr,
208 enum i915_cache_level level,
209 bool valid, u32 unused)
54d12527 210{
07749ef3 211 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
54d12527 212 pte |= GEN6_PTE_ADDR_ENCODE(addr);
e7210c3c
BW		 213
214 switch (level) {
350ec881
CW		 215 case I915_CACHE_L3_LLC:
216 case I915_CACHE_LLC:
217 pte |= GEN6_PTE_CACHE_LLC;
218 break;
219 case I915_CACHE_NONE:
220 pte |= GEN6_PTE_UNCACHED;
221 break;
222 default:
5f77eeb0 223 MISSING_CASE(level);
350ec881
CW		 224 }
225
226 return pte;
227}
228
07749ef3
MT		 229static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
230 enum i915_cache_level level,
231 bool valid, u32 unused)
350ec881 232{
07749ef3 233 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
350ec881
CW		 234 pte |= GEN6_PTE_ADDR_ENCODE(addr);
235
236 switch (level) {
237 case I915_CACHE_L3_LLC:
238 pte |= GEN7_PTE_CACHE_L3_LLC;
e7210c3c
BW		 239 break;
240 case I915_CACHE_LLC:
241 pte |= GEN6_PTE_CACHE_LLC;
242 break;
243 case I915_CACHE_NONE:
9119708c 244 pte |= GEN6_PTE_UNCACHED;
e7210c3c
BW		 245 break;
246 default:
5f77eeb0 247 MISSING_CASE(level);
e7210c3c
BW		 248 }
249
54d12527
BW		 250 return pte;
251}
252
07749ef3
MT		 253static gen6_pte_t byt_pte_encode(dma_addr_t addr,
254 enum i915_cache_level level,
255 bool valid, u32 flags)
93c34e70 256{
07749ef3 257 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
93c34e70
KG		 258 pte |= GEN6_PTE_ADDR_ENCODE(addr);
259
24f3a8cf
AG		 260 if (!(flags & PTE_READ_ONLY))
261 pte |= BYT_PTE_WRITEABLE;
93c34e70
KG		 262
263 if (level != I915_CACHE_NONE)
264 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
265
266 return pte;
267}
268
07749ef3
MT		 269static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
270 enum i915_cache_level level,
271 bool valid, u32 unused)
9119708c 272{
07749ef3 273 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
0d8ff15e 274 pte |= HSW_PTE_ADDR_ENCODE(addr);
9119708c
KG		 275
276 if (level != I915_CACHE_NONE)
87a6b688 277 pte |= HSW_WB_LLC_AGE3;
9119708c
KG		 278
279 return pte;
280}
281
07749ef3
MT		 282static gen6_pte_t iris_pte_encode(dma_addr_t addr,
283 enum i915_cache_level level,
284 bool valid, u32 unused)
4d15c145 285{
07749ef3 286 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
4d15c145
BW		 287 pte |= HSW_PTE_ADDR_ENCODE(addr);
288
651d794f
CW		 289 switch (level) {
290 case I915_CACHE_NONE:
291 break;
292 case I915_CACHE_WT:
c51e9701 293 pte |= HSW_WT_ELLC_LLC_AGE3;
651d794f
CW		 294 break;
295 default:
c51e9701 296 pte |= HSW_WB_ELLC_LLC_AGE3;
651d794f
CW		 297 break;
298 }
4d15c145
BW		 299
300 return pte;
301}
302
c114f76a
MK		 303static int __setup_page_dma(struct drm_device *dev,
304 struct i915_page_dma *p, gfp_t flags)
678d96fb
BW		 305{
306 struct device *device = &dev->pdev->dev;
307
c114f76a 308 p->page = alloc_page(flags);
44159ddb
MK		 309 if (!p->page)
310 return -ENOMEM;
678d96fb 311
44159ddb
MK		 312 p->daddr = dma_map_page(device,
313 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
678d96fb 314
44159ddb
MK		 315 if (dma_mapping_error(device, p->daddr)) {
316 __free_page(p->page);
317 return -EINVAL;
318 }
1266cdb1
MT		 319
320 return 0;
678d96fb
BW		 321}
322
c114f76a
MK		 323static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
324{
325 return __setup_page_dma(dev, p, GFP_KERNEL);
326}
327
44159ddb 328static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
06fda602 329{
44159ddb 330 if (WARN_ON(!p->page))
06fda602 331 return;
678d96fb 332
44159ddb
MK		 333 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
334 __free_page(p->page);
335 memset(p, 0, sizeof(*p));
336}
337
d1c54acd 338static void *kmap_page_dma(struct i915_page_dma *p)
73eeea53 339{
d1c54acd
MK		 340 return kmap_atomic(p->page);
341}
73eeea53 342
d1c54acd
MK		 343/* We use the flushing unmap only with ppgtt structures:
344 * page directories, page tables and scratch pages.
345 */
346static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
347{
73eeea53
MK		 348 /* There are only few exceptions for gen >=6. chv and bxt.
349 * And we are not sure about the latter so play safe for now.
350 */
351 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
352 drm_clflush_virt_range(vaddr, PAGE_SIZE);
353
354 kunmap_atomic(vaddr);
355}
356
567047be 357#define kmap_px(px) kmap_page_dma(px_base(px))
d1c54acd
MK		 358#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
359
567047be
MK		 360#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
361#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
362#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
363#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
364
d1c54acd
MK		 365static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
366 const uint64_t val)
367{
368 int i;
369 uint64_t * const vaddr = kmap_page_dma(p);
370
371 for (i = 0; i < 512; i++)
372 vaddr[i] = val;
373
374 kunmap_page_dma(dev, vaddr);
375}
376
73eeea53
MK		 377static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
378 const uint32_t val32)
379{
380 uint64_t v = val32;
381
382 v = v << 32 | val32;
383
384 fill_page_dma(dev, p, v);
385}
386
4ad2af1e
MK		 387static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
388{
389 struct i915_page_scratch *sp;
390 int ret;
391
392 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
393 if (sp == NULL)
394 return ERR_PTR(-ENOMEM);
395
396 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
397 if (ret) {
398 kfree(sp);
399 return ERR_PTR(ret);
400 }
401
402 set_pages_uc(px_page(sp), 1);
403
404 return sp;
405}
406
407static void free_scratch_page(struct drm_device *dev,
408 struct i915_page_scratch *sp)
409{
410 set_pages_wb(px_page(sp), 1);
411
412 cleanup_px(dev, sp);
413 kfree(sp);
414}
415
8a1ebd74 416static struct i915_page_table *alloc_pt(struct drm_device *dev)
06fda602 417{
ec565b3c 418 struct i915_page_table *pt;
678d96fb
BW		 419 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
420 GEN8_PTES : GEN6_PTES;
421 int ret = -ENOMEM;
06fda602
BW		 422
423 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
424 if (!pt)
425 return ERR_PTR(-ENOMEM);
426
678d96fb
BW		 427 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
428 GFP_KERNEL);
429
430 if (!pt->used_ptes)
431 goto fail_bitmap;
432
567047be 433 ret = setup_px(dev, pt);
678d96fb 434 if (ret)
44159ddb 435 goto fail_page_m;
06fda602
BW		 436
437 return pt;
678d96fb 438
44159ddb 439fail_page_m:
678d96fb
BW		 440 kfree(pt->used_ptes);
441fail_bitmap:
442 kfree(pt);
443
444 return ERR_PTR(ret);
06fda602
BW		 445}
446
2e906bea 447static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
06fda602 448{
2e906bea
MK		 449 cleanup_px(dev, pt);
450 kfree(pt->used_ptes);
451 kfree(pt);
452}
453
454static void gen8_initialize_pt(struct i915_address_space *vm,
455 struct i915_page_table *pt)
456{
457 gen8_pte_t scratch_pte;
458
459 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
460 I915_CACHE_LLC, true);
461
462 fill_px(vm->dev, pt, scratch_pte);
463}
464
465static void gen6_initialize_pt(struct i915_address_space *vm,
466 struct i915_page_table *pt)
467{
468 gen6_pte_t scratch_pte;
469
470 WARN_ON(px_dma(vm->scratch_page) == 0);
471
472 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
473 I915_CACHE_LLC, true, 0);
474
475 fill32_px(vm->dev, pt, scratch_pte);
06fda602
BW		 476}
477
8a1ebd74 478static struct i915_page_directory *alloc_pd(struct drm_device *dev)
06fda602 479{
ec565b3c 480 struct i915_page_directory *pd;
33c8819f 481 int ret = -ENOMEM;
06fda602
BW		 482
483 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
484 if (!pd)
485 return ERR_PTR(-ENOMEM);
486
33c8819f
MT		 487 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
488 sizeof(*pd->used_pdes), GFP_KERNEL);
489 if (!pd->used_pdes)
a08e111a 490 goto fail_bitmap;
33c8819f 491
567047be 492 ret = setup_px(dev, pd);
33c8819f 493 if (ret)
a08e111a 494 goto fail_page_m;
e5815a2e 495
06fda602 496 return pd;
33c8819f 497
a08e111a 498fail_page_m:
33c8819f 499 kfree(pd->used_pdes);
a08e111a 500fail_bitmap:
33c8819f
MT		 501 kfree(pd);
502
503 return ERR_PTR(ret);
06fda602
BW		 504}
505
2e906bea
MK		 506static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
507{
508 if (px_page(pd)) {
509 cleanup_px(dev, pd);
510 kfree(pd->used_pdes);
511 kfree(pd);
512 }
513}
514
515static void gen8_initialize_pd(struct i915_address_space *vm,
516 struct i915_page_directory *pd)
517{
518 gen8_pde_t scratch_pde;
519
520 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
521
522 fill_px(vm->dev, pd, scratch_pde);
523}
524
6ac18502
MT		 525static int __pdp_init(struct drm_device *dev,
526 struct i915_page_directory_pointer *pdp)
527{
528 size_t pdpes = I915_PDPES_PER_PDP(dev);
529
530 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
531 sizeof(unsigned long),
532 GFP_KERNEL);
533 if (!pdp->used_pdpes)
534 return -ENOMEM;
535
536 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
537 GFP_KERNEL);
538 if (!pdp->page_directory) {
539 kfree(pdp->used_pdpes);
540 /* the PDP might be the statically allocated top level. Keep it
541 * as clean as possible */
542 pdp->used_pdpes = NULL;
543 return -ENOMEM;
544 }
545
546 return 0;
547}
548
549static void __pdp_fini(struct i915_page_directory_pointer *pdp)
550{
551 kfree(pdp->used_pdpes);
552 kfree(pdp->page_directory);
553 pdp->page_directory = NULL;
554}
555
556static void free_pdp(struct drm_device *dev,
557 struct i915_page_directory_pointer *pdp)
558{
559 __pdp_fini(pdp);
560}
561
94e409c1 562/* Broadwell Page Directory Pointer Descriptors */
e85b26dc 563static int gen8_write_pdp(struct drm_i915_gem_request *req,
7cb6d7ac
MT		 564 unsigned entry,
565 dma_addr_t addr)
94e409c1 566{
e85b26dc 567 struct intel_engine_cs *ring = req->ring;
94e409c1
BW		 568 int ret;
569
570 BUG_ON(entry >= 4);
571
5fb9de1a 572 ret = intel_ring_begin(req, 6);
94e409c1
BW		 573 if (ret)
574 return ret;
575
576 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
577 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
7cb6d7ac 578 intel_ring_emit(ring, upper_32_bits(addr));
94e409c1
BW		 579 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
580 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
7cb6d7ac 581 intel_ring_emit(ring, lower_32_bits(addr));
94e409c1
BW		 582 intel_ring_advance(ring);
583
584 return 0;
585}
586
eeb9488e 587static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 588 struct drm_i915_gem_request *req)
94e409c1 589{
eeb9488e 590 int i, ret;
94e409c1 591
7cb6d7ac 592 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
d852c7bf
MK		 593 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
594
e85b26dc 595 ret = gen8_write_pdp(req, i, pd_daddr);
eeb9488e
BW		 596 if (ret)
597 return ret;
94e409c1 598 }
d595bd4b 599
eeb9488e 600 return 0;
94e409c1
BW		 601}
602
f9b5b782
MT		 603static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
604 struct i915_page_directory_pointer *pdp,
605 uint64_t start,
606 uint64_t length,
607 gen8_pte_t scratch_pte)
459108b8
BW		 608{
609 struct i915_hw_ppgtt *ppgtt =
610 container_of(vm, struct i915_hw_ppgtt, base);
f9b5b782 611 gen8_pte_t *pt_vaddr;
7ad47cf2
BW		 612 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
613 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
614 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
782f1495 615 unsigned num_entries = length >> PAGE_SHIFT;
459108b8
BW		 616 unsigned last_pte, i;
617
f9b5b782
MT		 618 if (WARN_ON(!pdp))
619 return;
459108b8
BW		 620
621 while (num_entries) {
ec565b3c
MT		 622 struct i915_page_directory *pd;
623 struct i915_page_table *pt;
06fda602 624
d4ec9da0 625 if (WARN_ON(!pdp->page_directory[pdpe]))
00245266 626 break;
06fda602 627
d4ec9da0 628 pd = pdp->page_directory[pdpe];
06fda602
BW		 629
630 if (WARN_ON(!pd->page_table[pde]))
00245266 631 break;
06fda602
BW		 632
633 pt = pd->page_table[pde];
634
567047be 635 if (WARN_ON(!px_page(pt)))
00245266 636 break;
06fda602 637
7ad47cf2 638 last_pte = pte + num_entries;
07749ef3
MT		 639 if (last_pte > GEN8_PTES)
640 last_pte = GEN8_PTES;
459108b8 641
d1c54acd 642 pt_vaddr = kmap_px(pt);
459108b8 643
7ad47cf2 644 for (i = pte; i < last_pte; i++) {
459108b8 645 pt_vaddr[i] = scratch_pte;
7ad47cf2
BW		 646 num_entries--;
647 }
459108b8 648
d1c54acd 649 kunmap_px(ppgtt, pt);
459108b8 650
7ad47cf2 651 pte = 0;
07749ef3 652 if (++pde == I915_PDES) {
7ad47cf2
BW		 653 pdpe++;
654 pde = 0;
655 }
459108b8
BW		 656 }
657}
658
f9b5b782
MT		 659static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
660 uint64_t start,
661 uint64_t length,
662 bool use_scratch)
9df15b49
BW		 663{
664 struct i915_hw_ppgtt *ppgtt =
665 container_of(vm, struct i915_hw_ppgtt, base);
d4ec9da0 666 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
f9b5b782
MT		 667
668 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
669 I915_CACHE_LLC, use_scratch);
670
671 gen8_ppgtt_clear_pte_range(vm, pdp, start, length, scratch_pte);
672}
673
674static void
675gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
676 struct i915_page_directory_pointer *pdp,
677 struct sg_table *pages,
678 uint64_t start,
679 enum i915_cache_level cache_level)
680{
681 struct i915_hw_ppgtt *ppgtt =
682 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 683 gen8_pte_t *pt_vaddr;
7ad47cf2
BW		 684 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
685 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
686 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
9df15b49
BW		 687 struct sg_page_iter sg_iter;
688
6f1cc993 689 pt_vaddr = NULL;
7ad47cf2 690
9df15b49 691 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
76643600 692 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
7ad47cf2
BW		 693 break;
694
d7b3de91 695 if (pt_vaddr == NULL) {
d4ec9da0 696 struct i915_page_directory *pd = pdp->page_directory[pdpe];
ec565b3c 697 struct i915_page_table *pt = pd->page_table[pde];
d1c54acd 698 pt_vaddr = kmap_px(pt);
d7b3de91 699 }
9df15b49 700
7ad47cf2 701 pt_vaddr[pte] =
6f1cc993
CW		 702 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
703 cache_level, true);
07749ef3 704 if (++pte == GEN8_PTES) {
d1c54acd 705 kunmap_px(ppgtt, pt_vaddr);
6f1cc993 706 pt_vaddr = NULL;
07749ef3 707 if (++pde == I915_PDES) {
7ad47cf2
BW		 708 pdpe++;
709 pde = 0;
710 }
711 pte = 0;
9df15b49
BW		 712 }
713 }
d1c54acd
MK		 714
715 if (pt_vaddr)
716 kunmap_px(ppgtt, pt_vaddr);
9df15b49
BW		 717}
718
f9b5b782
MT		 719static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
720 struct sg_table *pages,
721 uint64_t start,
722 enum i915_cache_level cache_level,
723 u32 unused)
724{
725 struct i915_hw_ppgtt *ppgtt =
726 container_of(vm, struct i915_hw_ppgtt, base);
727 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
728
729 gen8_ppgtt_insert_pte_entries(vm, pdp, pages, start, cache_level);
730}
731
f37c0505
MT		 732static void gen8_free_page_tables(struct drm_device *dev,
733 struct i915_page_directory *pd)
7ad47cf2
BW		 734{
735 int i;
736
567047be 737 if (!px_page(pd))
7ad47cf2
BW		 738 return;
739
33c8819f 740 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
06fda602
BW		 741 if (WARN_ON(!pd->page_table[i]))
742 continue;
7ad47cf2 743
a08e111a 744 free_pt(dev, pd->page_table[i]);
06fda602
BW		 745 pd->page_table[i] = NULL;
746 }
d7b3de91
BW		 747}
748
8776f02b
MK		 749static int gen8_init_scratch(struct i915_address_space *vm)
750{
751 struct drm_device *dev = vm->dev;
752
753 vm->scratch_page = alloc_scratch_page(dev);
754 if (IS_ERR(vm->scratch_page))
755 return PTR_ERR(vm->scratch_page);
756
757 vm->scratch_pt = alloc_pt(dev);
758 if (IS_ERR(vm->scratch_pt)) {
759 free_scratch_page(dev, vm->scratch_page);
760 return PTR_ERR(vm->scratch_pt);
761 }
762
763 vm->scratch_pd = alloc_pd(dev);
764 if (IS_ERR(vm->scratch_pd)) {
765 free_pt(dev, vm->scratch_pt);
766 free_scratch_page(dev, vm->scratch_page);
767 return PTR_ERR(vm->scratch_pd);
768 }
769
770 gen8_initialize_pt(vm, vm->scratch_pt);
771 gen8_initialize_pd(vm, vm->scratch_pd);
772
773 return 0;
774}
775
776static void gen8_free_scratch(struct i915_address_space *vm)
777{
778 struct drm_device *dev = vm->dev;
779
780 free_pd(dev, vm->scratch_pd);
781 free_pt(dev, vm->scratch_pt);
782 free_scratch_page(dev, vm->scratch_page);
783}
784
061dd493 785static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
b45a6715 786{
061dd493
DV		 787 struct i915_hw_ppgtt *ppgtt =
788 container_of(vm, struct i915_hw_ppgtt, base);
d4ec9da0
MT		 789 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
790 struct drm_device *dev = ppgtt->base.dev;
b45a6715
BW		 791 int i;
792
d4ec9da0
MT		 793 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
794 if (WARN_ON(!pdp->page_directory[i]))
06fda602
BW		 795 continue;
796
d4ec9da0
MT		 797 gen8_free_page_tables(dev, pdp->page_directory[i]);
798 free_pd(dev, pdp->page_directory[i]);
7ad47cf2 799 }
69876bed 800
d4ec9da0
MT		 801 free_pdp(dev, pdp);
802
8776f02b 803 gen8_free_scratch(vm);
b45a6715
BW		 804}
805
d7b2633d
MT		 806/**
807 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
d4ec9da0
MT		 808 * @vm: Master vm structure.
809 * @pd: Page directory for this address range.
d7b2633d 810 * @start: Starting virtual address to begin allocations.
d4ec9da0 811 * @length: Size of the allocations.
d7b2633d
MT		 812 * @new_pts: Bitmap set by function with new allocations. Likely used by the
813 * caller to free on error.
814 *
815 * Allocate the required number of page tables. Extremely similar to
816 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
817 * the page directory boundary (instead of the page directory pointer). That
818 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
819 * possible, and likely that the caller will need to use multiple calls of this
820 * function to achieve the appropriate allocation.
821 *
822 * Return: 0 if success; negative error code otherwise.
823 */
d4ec9da0 824static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
e5815a2e 825 struct i915_page_directory *pd,
5441f0cb 826 uint64_t start,
d7b2633d
MT		 827 uint64_t length,
828 unsigned long *new_pts)
bf2b4ed2 829{
d4ec9da0 830 struct drm_device *dev = vm->dev;
d7b2633d 831 struct i915_page_table *pt;
5441f0cb
MT		 832 uint64_t temp;
833 uint32_t pde;
bf2b4ed2 834
d7b2633d
MT		 835 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
836 /* Don't reallocate page tables */
6ac18502 837 if (test_bit(pde, pd->used_pdes)) {
d7b2633d 838 /* Scratch is never allocated this way */
d4ec9da0 839 WARN_ON(pt == vm->scratch_pt);
d7b2633d
MT		 840 continue;
841 }
842
8a1ebd74 843 pt = alloc_pt(dev);
d7b2633d 844 if (IS_ERR(pt))
5441f0cb
MT		 845 goto unwind_out;
846
d4ec9da0 847 gen8_initialize_pt(vm, pt);
d7b2633d 848 pd->page_table[pde] = pt;
966082c9 849 __set_bit(pde, new_pts);
7ad47cf2
BW		 850 }
851
bf2b4ed2 852 return 0;
7ad47cf2
BW		 853
854unwind_out:
d7b2633d 855 for_each_set_bit(pde, new_pts, I915_PDES)
a08e111a 856 free_pt(dev, pd->page_table[pde]);
7ad47cf2 857
d7b3de91 858 return -ENOMEM;
bf2b4ed2
BW		 859}
860
d7b2633d
MT		 861/**
862 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
d4ec9da0 863 * @vm: Master vm structure.
d7b2633d
MT		 864 * @pdp: Page directory pointer for this address range.
865 * @start: Starting virtual address to begin allocations.
d4ec9da0
MT		 866 * @length: Size of the allocations.
867 * @new_pds: Bitmap set by function with new allocations. Likely used by the
d7b2633d
MT		 868 * caller to free on error.
869 *
870 * Allocate the required number of page directories starting at the pde index of
871 * @start, and ending at the pde index @start + @length. This function will skip
872 * over already allocated page directories within the range, and only allocate
873 * new ones, setting the appropriate pointer within the pdp as well as the
874 * correct position in the bitmap @new_pds.
875 *
876 * The function will only allocate the pages within the range for a give page
877 * directory pointer. In other words, if @start + @length straddles a virtually
878 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
879 * required by the caller, This is not currently possible, and the BUG in the
880 * code will prevent it.
881 *
882 * Return: 0 if success; negative error code otherwise.
883 */
d4ec9da0
MT		 884static int
885gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
886 struct i915_page_directory_pointer *pdp,
887 uint64_t start,
888 uint64_t length,
889 unsigned long *new_pds)
bf2b4ed2 890{
d4ec9da0 891 struct drm_device *dev = vm->dev;
d7b2633d 892 struct i915_page_directory *pd;
69876bed
MT		 893 uint64_t temp;
894 uint32_t pdpe;
6ac18502 895 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
69876bed 896
6ac18502 897 WARN_ON(!bitmap_empty(new_pds, pdpes));
d7b2633d 898
d7b2633d 899 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
6ac18502 900 if (test_bit(pdpe, pdp->used_pdpes))
d7b2633d 901 continue;
33c8819f 902
8a1ebd74 903 pd = alloc_pd(dev);
d7b2633d 904 if (IS_ERR(pd))
d7b3de91 905 goto unwind_out;
69876bed 906
d4ec9da0 907 gen8_initialize_pd(vm, pd);
d7b2633d 908 pdp->page_directory[pdpe] = pd;
966082c9 909 __set_bit(pdpe, new_pds);
d7b3de91
BW		 910 }
911
bf2b4ed2 912 return 0;
d7b3de91
BW		 913
914unwind_out:
6ac18502 915 for_each_set_bit(pdpe, new_pds, pdpes)
a08e111a 916 free_pd(dev, pdp->page_directory[pdpe]);
d7b3de91
BW		 917
918 return -ENOMEM;
bf2b4ed2
BW		 919}
920
d7b2633d 921static void
6ac18502
MT		 922free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts,
923 uint32_t pdpes)
d7b2633d
MT		 924{
925 int i;
926
6ac18502 927 for (i = 0; i < pdpes; i++)
d7b2633d
MT		 928 kfree(new_pts[i]);
929 kfree(new_pts);
930 kfree(new_pds);
931}
932
933/* Fills in the page directory bitmap, and the array of page tables bitmap. Both
934 * of these are based on the number of PDPEs in the system.
935 */
936static
937int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
6ac18502
MT		 938 unsigned long ***new_pts,
939 uint32_t pdpes)
d7b2633d
MT		 940{
941 int i;
942 unsigned long *pds;
943 unsigned long **pts;
944
6ac18502 945 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_KERNEL);
d7b2633d
MT		 946 if (!pds)
947 return -ENOMEM;
948
6ac18502 949 pts = kcalloc(pdpes, sizeof(unsigned long *), GFP_KERNEL);
d7b2633d
MT		 950 if (!pts) {
951 kfree(pds);
952 return -ENOMEM;
953 }
954
6ac18502 955 for (i = 0; i < pdpes; i++) {
d7b2633d
MT		 956 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
957 sizeof(unsigned long), GFP_KERNEL);
958 if (!pts[i])
959 goto err_out;
960 }
961
962 *new_pds = pds;
963 *new_pts = pts;
964
965 return 0;
966
967err_out:
6ac18502 968 free_gen8_temp_bitmaps(pds, pts, pdpes);
d7b2633d
MT		 969 return -ENOMEM;
970}
971
5b7e4c9c
MK		 972/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
973 * the page table structures, we mark them dirty so that
974 * context switching/execlist queuing code takes extra steps
975 * to ensure that tlbs are flushed.
976 */
977static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
978{
979 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
980}
981
e5815a2e 982static int gen8_alloc_va_range(struct i915_address_space *vm,
d4ec9da0 983 uint64_t start, uint64_t length)
bf2b4ed2 984{
e5815a2e
MT		 985 struct i915_hw_ppgtt *ppgtt =
986 container_of(vm, struct i915_hw_ppgtt, base);
d7b2633d 987 unsigned long *new_page_dirs, **new_page_tables;
d4ec9da0
MT		 988 struct drm_device *dev = vm->dev;
989 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
5441f0cb 990 struct i915_page_directory *pd;
33c8819f
MT		 991 const uint64_t orig_start = start;
992 const uint64_t orig_length = length;
5441f0cb
MT		 993 uint64_t temp;
994 uint32_t pdpe;
d4ec9da0 995 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
bf2b4ed2
BW		 996 int ret;
997
d7b2633d
MT		 998 /* Wrap is never okay since we can only represent 48b, and we don't
999 * actually use the other side of the canonical address space.
1000 */
1001 if (WARN_ON(start + length < start))
a05d80ee
MK		 1002 return -ENODEV;
1003
d4ec9da0 1004 if (WARN_ON(start + length > vm->total))
a05d80ee 1005 return -ENODEV;
d7b2633d 1006
6ac18502 1007 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
bf2b4ed2
BW		 1008 if (ret)
1009 return ret;
1010
d7b2633d 1011 /* Do the allocations first so we can easily bail out */
d4ec9da0
MT		 1012 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1013 new_page_dirs);
d7b2633d 1014 if (ret) {
6ac18502 1015 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
d7b2633d
MT		 1016 return ret;
1017 }
1018
1019 /* For every page directory referenced, allocate page tables */
d4ec9da0
MT		 1020 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1021 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
d7b2633d 1022 new_page_tables[pdpe]);
5441f0cb
MT		 1023 if (ret)
1024 goto err_out;
5441f0cb
MT		 1025 }
1026
33c8819f
MT		 1027 start = orig_start;
1028 length = orig_length;
1029
d7b2633d
MT		 1030 /* Allocations have completed successfully, so set the bitmaps, and do
1031 * the mappings. */
d4ec9da0 1032 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
d1c54acd 1033 gen8_pde_t *const page_directory = kmap_px(pd);
33c8819f 1034 struct i915_page_table *pt;
09120d4e 1035 uint64_t pd_len = length;
33c8819f
MT		 1036 uint64_t pd_start = start;
1037 uint32_t pde;
1038
d7b2633d
MT		 1039 /* Every pd should be allocated, we just did that above. */
1040 WARN_ON(!pd);
1041
1042 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1043 /* Same reasoning as pd */
1044 WARN_ON(!pt);
1045 WARN_ON(!pd_len);
1046 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1047
1048 /* Set our used ptes within the page table */
1049 bitmap_set(pt->used_ptes,
1050 gen8_pte_index(pd_start),
1051 gen8_pte_count(pd_start, pd_len));
1052
1053 /* Our pde is now pointing to the pagetable, pt */
966082c9 1054 __set_bit(pde, pd->used_pdes);
d7b2633d
MT		 1055
1056 /* Map the PDE to the page table */
fe36f55d
MK		 1057 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1058 I915_CACHE_LLC);
d7b2633d
MT		 1059
1060 /* NB: We haven't yet mapped ptes to pages. At this
1061 * point we're still relying on insert_entries() */
33c8819f 1062 }
d7b2633d 1063
d1c54acd 1064 kunmap_px(ppgtt, page_directory);
d4ec9da0 1065 __set_bit(pdpe, pdp->used_pdpes);
33c8819f
MT		 1066 }
1067
6ac18502 1068 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
5b7e4c9c 1069 mark_tlbs_dirty(ppgtt);
d7b3de91 1070 return 0;
bf2b4ed2 1071
d7b3de91 1072err_out:
d7b2633d
MT		 1073 while (pdpe--) {
1074 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
d4ec9da0 1075 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
d7b2633d
MT		 1076 }
1077
6ac18502 1078 for_each_set_bit(pdpe, new_page_dirs, pdpes)
d4ec9da0 1079 free_pd(dev, pdp->page_directory[pdpe]);
d7b2633d 1080
6ac18502 1081 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
5b7e4c9c 1082 mark_tlbs_dirty(ppgtt);
bf2b4ed2
BW		 1083 return ret;
1084}
1085
eb0b44ad 1086/*
f3a964b9
BW		 1087 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1088 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1089 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1090 * space.
37aca44a 1091 *
f3a964b9 1092 */
5c5f6457 1093static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
37aca44a 1094{
8776f02b 1095 int ret;
7cb6d7ac 1096
8776f02b
MK		 1097 ret = gen8_init_scratch(&ppgtt->base);
1098 if (ret)
1099 return ret;
69876bed 1100
d7b2633d 1101 ppgtt->base.start = 0;
5c5f6457 1102 ppgtt->base.total = 1ULL << 32;
501fd70f
MT		 1103 if (IS_ENABLED(CONFIG_X86_32))
1104 /* While we have a proliferation of size_t variables
1105 * we cannot represent the full ppgtt size on 32bit,
1106 * so limit it to the same size as the GGTT (currently
1107 * 2GiB).
1108 */
1109 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
d7b2633d 1110 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
5c5f6457 1111 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
d7b2633d 1112 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
c7e16f22 1113 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
777dc5bb
DV		 1114 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1115 ppgtt->base.bind_vma = ppgtt_bind_vma;
d7b2633d
MT		 1116
1117 ppgtt->switch_mm = gen8_mm_switch;
1118
6ac18502
MT		 1119 ret = __pdp_init(false, &ppgtt->pdp);
1120
1121 if (ret)
1122 goto free_scratch;
1123
d7b2633d 1124 return 0;
6ac18502
MT		 1125
1126free_scratch:
1127 gen8_free_scratch(&ppgtt->base);
1128 return ret;
d7b2633d
MT		 1129}
1130
87d60b63
BW		 1131static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1132{
87d60b63 1133 struct i915_address_space *vm = &ppgtt->base;
09942c65 1134 struct i915_page_table *unused;
07749ef3 1135 gen6_pte_t scratch_pte;
87d60b63 1136 uint32_t pd_entry;
09942c65
MT		 1137 uint32_t pte, pde, temp;
1138 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
87d60b63 1139
79ab9370
MK		 1140 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1141 I915_CACHE_LLC, true, 0);
87d60b63 1142
09942c65 1143 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
87d60b63 1144 u32 expected;
07749ef3 1145 gen6_pte_t *pt_vaddr;
567047be 1146 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
09942c65 1147 pd_entry = readl(ppgtt->pd_addr + pde);
87d60b63
BW		 1148 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1149
1150 if (pd_entry != expected)
1151 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1152 pde,
1153 pd_entry,
1154 expected);
1155 seq_printf(m, "\tPDE: %x\n", pd_entry);
1156
d1c54acd
MK		 1157 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1158
07749ef3 1159 for (pte = 0; pte < GEN6_PTES; pte+=4) {
87d60b63 1160 unsigned long va =
07749ef3 1161 (pde * PAGE_SIZE * GEN6_PTES) +
87d60b63
BW		 1162 (pte * PAGE_SIZE);
1163 int i;
1164 bool found = false;
1165 for (i = 0; i < 4; i++)
1166 if (pt_vaddr[pte + i] != scratch_pte)
1167 found = true;
1168 if (!found)
1169 continue;
1170
1171 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1172 for (i = 0; i < 4; i++) {
1173 if (pt_vaddr[pte + i] != scratch_pte)
1174 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1175 else
1176 seq_puts(m, " SCRATCH ");
1177 }
1178 seq_puts(m, "\n");
1179 }
d1c54acd 1180 kunmap_px(ppgtt, pt_vaddr);
87d60b63
BW		 1181 }
1182}
1183
678d96fb 1184/* Write pde (index) from the page directory @pd to the page table @pt */
ec565b3c
MT		 1185static void gen6_write_pde(struct i915_page_directory *pd,
1186 const int pde, struct i915_page_table *pt)
6197349b 1187{
678d96fb
BW		 1188 /* Caller needs to make sure the write completes if necessary */
1189 struct i915_hw_ppgtt *ppgtt =
1190 container_of(pd, struct i915_hw_ppgtt, pd);
1191 u32 pd_entry;
6197349b 1192
567047be 1193 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
678d96fb 1194 pd_entry |= GEN6_PDE_VALID;
6197349b 1195
678d96fb
BW		 1196 writel(pd_entry, ppgtt->pd_addr + pde);
1197}
6197349b 1198
678d96fb
BW		 1199/* Write all the page tables found in the ppgtt structure to incrementing page
1200 * directories. */
1201static void gen6_write_page_range(struct drm_i915_private *dev_priv,
ec565b3c 1202 struct i915_page_directory *pd,
678d96fb
BW		 1203 uint32_t start, uint32_t length)
1204{
ec565b3c 1205 struct i915_page_table *pt;
678d96fb
BW		 1206 uint32_t pde, temp;
1207
1208 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1209 gen6_write_pde(pd, pde, pt);
1210
1211 /* Make sure write is complete before other code can use this page
1212 * table. Also require for WC mapped PTEs */
1213 readl(dev_priv->gtt.gsm);
3e302542
BW		 1214}
1215
b4a74e3a 1216static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
3e302542 1217{
44159ddb 1218 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
b4a74e3a 1219
44159ddb 1220 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
b4a74e3a
BW		 1221}
1222
90252e5c 1223static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1224 struct drm_i915_gem_request *req)
90252e5c 1225{
e85b26dc 1226 struct intel_engine_cs *ring = req->ring;
90252e5c
BW		 1227 int ret;
1228
90252e5c 1229 /* NB: TLBs must be flushed and invalidated before a switch */
a84c3ae1 1230 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1231 if (ret)
1232 return ret;
1233
5fb9de1a 1234 ret = intel_ring_begin(req, 6);
90252e5c
BW		 1235 if (ret)
1236 return ret;
1237
1238 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1239 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1240 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1241 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1242 intel_ring_emit(ring, get_pd_offset(ppgtt));
1243 intel_ring_emit(ring, MI_NOOP);
1244 intel_ring_advance(ring);
1245
1246 return 0;
1247}
1248
71ba2d64 1249static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1250 struct drm_i915_gem_request *req)
71ba2d64 1251{
e85b26dc 1252 struct intel_engine_cs *ring = req->ring;
71ba2d64
YZ		 1253 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1254
1255 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1256 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1257 return 0;
1258}
1259
48a10389 1260static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1261 struct drm_i915_gem_request *req)
48a10389 1262{
e85b26dc 1263 struct intel_engine_cs *ring = req->ring;
48a10389
BW		 1264 int ret;
1265
48a10389 1266 /* NB: TLBs must be flushed and invalidated before a switch */
a84c3ae1 1267 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
48a10389
BW		 1268 if (ret)
1269 return ret;
1270
5fb9de1a 1271 ret = intel_ring_begin(req, 6);
48a10389
BW		 1272 if (ret)
1273 return ret;
1274
1275 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1276 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1277 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1278 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1279 intel_ring_emit(ring, get_pd_offset(ppgtt));
1280 intel_ring_emit(ring, MI_NOOP);
1281 intel_ring_advance(ring);
1282
90252e5c
BW		 1283 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1284 if (ring->id != RCS) {
a84c3ae1 1285 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1286 if (ret)
1287 return ret;
1288 }
1289
48a10389
BW		 1290 return 0;
1291}
1292
eeb9488e 1293static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1294 struct drm_i915_gem_request *req)
eeb9488e 1295{
e85b26dc 1296 struct intel_engine_cs *ring = req->ring;
eeb9488e
BW		 1297 struct drm_device *dev = ppgtt->base.dev;
1298 struct drm_i915_private *dev_priv = dev->dev_private;
1299
48a10389 1300
eeb9488e
BW		 1301 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1302 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1303
1304 POSTING_READ(RING_PP_DIR_DCLV(ring));
1305
1306 return 0;
1307}
1308
82460d97 1309static void gen8_ppgtt_enable(struct drm_device *dev)
eeb9488e 1310{
eeb9488e 1311 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1312 struct intel_engine_cs *ring;
82460d97 1313 int j;
3e302542 1314
eeb9488e
BW		 1315 for_each_ring(ring, dev_priv, j) {
1316 I915_WRITE(RING_MODE_GEN7(ring),
1317 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
eeb9488e 1318 }
eeb9488e 1319}
6197349b 1320
82460d97 1321static void gen7_ppgtt_enable(struct drm_device *dev)
3e302542 1322{
50227e1c 1323 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1324 struct intel_engine_cs *ring;
b4a74e3a 1325 uint32_t ecochk, ecobits;
3e302542 1326 int i;
6197349b 1327
b4a74e3a
BW		 1328 ecobits = I915_READ(GAC_ECO_BITS);
1329 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
a65c2fcd 1330
b4a74e3a
BW		 1331 ecochk = I915_READ(GAM_ECOCHK);
1332 if (IS_HASWELL(dev)) {
1333 ecochk |= ECOCHK_PPGTT_WB_HSW;
1334 } else {
1335 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1336 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1337 }
1338 I915_WRITE(GAM_ECOCHK, ecochk);
a65c2fcd 1339
b4a74e3a 1340 for_each_ring(ring, dev_priv, i) {
6197349b 1341 /* GFX_MODE is per-ring on gen7+ */
b4a74e3a
BW		 1342 I915_WRITE(RING_MODE_GEN7(ring),
1343 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b 1344 }
b4a74e3a 1345}
6197349b 1346
82460d97 1347static void gen6_ppgtt_enable(struct drm_device *dev)
b4a74e3a 1348{
50227e1c 1349 struct drm_i915_private *dev_priv = dev->dev_private;
b4a74e3a 1350 uint32_t ecochk, gab_ctl, ecobits;
a65c2fcd 1351
b4a74e3a
BW		 1352 ecobits = I915_READ(GAC_ECO_BITS);
1353 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1354 ECOBITS_PPGTT_CACHE64B);
6197349b 1355
b4a74e3a
BW		 1356 gab_ctl = I915_READ(GAB_CTL);
1357 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1358
1359 ecochk = I915_READ(GAM_ECOCHK);
1360 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1361
1362 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b
BW		 1363}
1364
1d2a314c 1365/* PPGTT support for Sandybdrige/Gen6 and later */
853ba5d2 1366static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1367 uint64_t start,
1368 uint64_t length,
828c7908 1369 bool use_scratch)
1d2a314c 1370{
853ba5d2
BW		 1371 struct i915_hw_ppgtt *ppgtt =
1372 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1373 gen6_pte_t *pt_vaddr, scratch_pte;
782f1495
BW		 1374 unsigned first_entry = start >> PAGE_SHIFT;
1375 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1376 unsigned act_pt = first_entry / GEN6_PTES;
1377 unsigned first_pte = first_entry % GEN6_PTES;
7bddb01f 1378 unsigned last_pte, i;
1d2a314c 1379
c114f76a
MK		 1380 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1381 I915_CACHE_LLC, true, 0);
1d2a314c 1382
7bddb01f
DV		 1383 while (num_entries) {
1384 last_pte = first_pte + num_entries;
07749ef3
MT		 1385 if (last_pte > GEN6_PTES)
1386 last_pte = GEN6_PTES;
7bddb01f 1387
d1c54acd 1388 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1d2a314c 1389
7bddb01f
DV		 1390 for (i = first_pte; i < last_pte; i++)
1391 pt_vaddr[i] = scratch_pte;
1d2a314c 1392
d1c54acd 1393 kunmap_px(ppgtt, pt_vaddr);
1d2a314c 1394
7bddb01f
DV		 1395 num_entries -= last_pte - first_pte;
1396 first_pte = 0;
a15326a5 1397 act_pt++;
7bddb01f 1398 }
1d2a314c
DV		 1399}
1400
853ba5d2 1401static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
def886c3 1402 struct sg_table *pages,
782f1495 1403 uint64_t start,
24f3a8cf 1404 enum i915_cache_level cache_level, u32 flags)
def886c3 1405{
853ba5d2
BW		 1406 struct i915_hw_ppgtt *ppgtt =
1407 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1408 gen6_pte_t *pt_vaddr;
782f1495 1409 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1410 unsigned act_pt = first_entry / GEN6_PTES;
1411 unsigned act_pte = first_entry % GEN6_PTES;
6e995e23
ID		 1412 struct sg_page_iter sg_iter;
1413
cc79714f 1414 pt_vaddr = NULL;
6e995e23 1415 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
cc79714f 1416 if (pt_vaddr == NULL)
d1c54acd 1417 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
6e995e23 1418
cc79714f
CW		 1419 pt_vaddr[act_pte] =
1420 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
24f3a8cf
AG		 1421 cache_level, true, flags);
1422
07749ef3 1423 if (++act_pte == GEN6_PTES) {
d1c54acd 1424 kunmap_px(ppgtt, pt_vaddr);
cc79714f 1425 pt_vaddr = NULL;
a15326a5 1426 act_pt++;
6e995e23 1427 act_pte = 0;
def886c3 1428 }
def886c3 1429 }
cc79714f 1430 if (pt_vaddr)
d1c54acd 1431 kunmap_px(ppgtt, pt_vaddr);
def886c3
DV		 1432}
1433
678d96fb 1434static int gen6_alloc_va_range(struct i915_address_space *vm,
a05d80ee 1435 uint64_t start_in, uint64_t length_in)
678d96fb 1436{
4933d519
MT		 1437 DECLARE_BITMAP(new_page_tables, I915_PDES);
1438 struct drm_device *dev = vm->dev;
1439 struct drm_i915_private *dev_priv = dev->dev_private;
678d96fb
BW		 1440 struct i915_hw_ppgtt *ppgtt =
1441 container_of(vm, struct i915_hw_ppgtt, base);
ec565b3c 1442 struct i915_page_table *pt;
a05d80ee 1443 uint32_t start, length, start_save, length_save;
678d96fb 1444 uint32_t pde, temp;
4933d519
MT		 1445 int ret;
1446
a05d80ee
MK		 1447 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1448 return -ENODEV;
1449
1450 start = start_save = start_in;
1451 length = length_save = length_in;
4933d519
MT		 1452
1453 bitmap_zero(new_page_tables, I915_PDES);
1454
1455 /* The allocation is done in two stages so that we can bail out with
1456 * minimal amount of pain. The first stage finds new page tables that
1457 * need allocation. The second stage marks use ptes within the page
1458 * tables.
1459 */
1460 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
79ab9370 1461 if (pt != vm->scratch_pt) {
4933d519
MT		 1462 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1463 continue;
1464 }
1465
1466 /* We've already allocated a page table */
1467 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1468
8a1ebd74 1469 pt = alloc_pt(dev);
4933d519
MT		 1470 if (IS_ERR(pt)) {
1471 ret = PTR_ERR(pt);
1472 goto unwind_out;
1473 }
1474
1475 gen6_initialize_pt(vm, pt);
1476
1477 ppgtt->pd.page_table[pde] = pt;
966082c9 1478 __set_bit(pde, new_page_tables);
72744cb1 1479 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
4933d519
MT		 1480 }
1481
1482 start = start_save;
1483 length = length_save;
678d96fb
BW		 1484
1485 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1486 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1487
1488 bitmap_zero(tmp_bitmap, GEN6_PTES);
1489 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1490 gen6_pte_count(start, length));
1491
966082c9 1492 if (__test_and_clear_bit(pde, new_page_tables))
4933d519
MT		 1493 gen6_write_pde(&ppgtt->pd, pde, pt);
1494
72744cb1
MT		 1495 trace_i915_page_table_entry_map(vm, pde, pt,
1496 gen6_pte_index(start),
1497 gen6_pte_count(start, length),
1498 GEN6_PTES);
4933d519 1499 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
678d96fb
BW		 1500 GEN6_PTES);
1501 }
1502
4933d519
MT		 1503 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1504
1505 /* Make sure write is complete before other code can use this page
1506 * table. Also require for WC mapped PTEs */
1507 readl(dev_priv->gtt.gsm);
1508
563222a7 1509 mark_tlbs_dirty(ppgtt);
678d96fb 1510 return 0;
4933d519
MT		 1511
1512unwind_out:
1513 for_each_set_bit(pde, new_page_tables, I915_PDES) {
ec565b3c 1514 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
4933d519 1515
79ab9370 1516 ppgtt->pd.page_table[pde] = vm->scratch_pt;
a08e111a 1517 free_pt(vm->dev, pt);
4933d519
MT		 1518 }
1519
1520 mark_tlbs_dirty(ppgtt);
1521 return ret;
678d96fb
BW		 1522}
1523
8776f02b
MK		 1524static int gen6_init_scratch(struct i915_address_space *vm)
1525{
1526 struct drm_device *dev = vm->dev;
1527
1528 vm->scratch_page = alloc_scratch_page(dev);
1529 if (IS_ERR(vm->scratch_page))
1530 return PTR_ERR(vm->scratch_page);
1531
1532 vm->scratch_pt = alloc_pt(dev);
1533 if (IS_ERR(vm->scratch_pt)) {
1534 free_scratch_page(dev, vm->scratch_page);
1535 return PTR_ERR(vm->scratch_pt);
1536 }
1537
1538 gen6_initialize_pt(vm, vm->scratch_pt);
1539
1540 return 0;
1541}
1542
1543static void gen6_free_scratch(struct i915_address_space *vm)
1544{
1545 struct drm_device *dev = vm->dev;
1546
1547 free_pt(dev, vm->scratch_pt);
1548 free_scratch_page(dev, vm->scratch_page);
1549}
1550
061dd493 1551static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
a00d825d 1552{
061dd493
DV		 1553 struct i915_hw_ppgtt *ppgtt =
1554 container_of(vm, struct i915_hw_ppgtt, base);
09942c65
MT		 1555 struct i915_page_table *pt;
1556 uint32_t pde;
4933d519 1557
061dd493
DV		 1558 drm_mm_remove_node(&ppgtt->node);
1559
09942c65 1560 gen6_for_all_pdes(pt, ppgtt, pde) {
79ab9370 1561 if (pt != vm->scratch_pt)
a08e111a 1562 free_pt(ppgtt->base.dev, pt);
4933d519 1563 }
06fda602 1564
8776f02b 1565 gen6_free_scratch(vm);
3440d265
DV		 1566}
1567
b146520f 1568static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
3440d265 1569{
8776f02b 1570 struct i915_address_space *vm = &ppgtt->base;
853ba5d2 1571 struct drm_device *dev = ppgtt->base.dev;
1d2a314c 1572 struct drm_i915_private *dev_priv = dev->dev_private;
e3cc1995 1573 bool retried = false;
b146520f 1574 int ret;
1d2a314c 1575
c8d4c0d6
BW		 1576 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1577 * allocator works in address space sizes, so it's multiplied by page
1578 * size. We allocate at the top of the GTT to avoid fragmentation.
1579 */
1580 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
4933d519 1581
8776f02b
MK		 1582 ret = gen6_init_scratch(vm);
1583 if (ret)
1584 return ret;
4933d519 1585
e3cc1995 1586alloc:
c8d4c0d6
BW		 1587 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1588 &ppgtt->node, GEN6_PD_SIZE,
1589 GEN6_PD_ALIGN, 0,
1590 0, dev_priv->gtt.base.total,
3e8b5ae9 1591 DRM_MM_TOPDOWN);
e3cc1995
BW		 1592 if (ret == -ENOSPC && !retried) {
1593 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1594 GEN6_PD_SIZE, GEN6_PD_ALIGN,
d23db88c
CW		 1595 I915_CACHE_NONE,
1596 0, dev_priv->gtt.base.total,
1597 0);
e3cc1995 1598 if (ret)
678d96fb 1599 goto err_out;
e3cc1995
BW		 1600
1601 retried = true;
1602 goto alloc;
1603 }
c8d4c0d6 1604
c8c26622 1605 if (ret)
678d96fb
BW		 1606 goto err_out;
1607
c8c26622 1608
c8d4c0d6
BW		 1609 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1610 DRM_DEBUG("Forced to use aperture for PDEs\n");
1d2a314c 1611
c8c26622 1612 return 0;
678d96fb
BW		 1613
1614err_out:
8776f02b 1615 gen6_free_scratch(vm);
678d96fb 1616 return ret;
b146520f
BW		 1617}
1618
b146520f
BW		 1619static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1620{
2f2cf682 1621 return gen6_ppgtt_allocate_page_directories(ppgtt);
4933d519 1622}
06dc68d6 1623
4933d519
MT		 1624static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1625 uint64_t start, uint64_t length)
1626{
ec565b3c 1627 struct i915_page_table *unused;
4933d519 1628 uint32_t pde, temp;
1d2a314c 1629
4933d519 1630 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
79ab9370 1631 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
b146520f
BW		 1632}
1633
5c5f6457 1634static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
b146520f
BW		 1635{
1636 struct drm_device *dev = ppgtt->base.dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 int ret;
1639
1640 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1641 if (IS_GEN6(dev)) {
b146520f
BW		 1642 ppgtt->switch_mm = gen6_mm_switch;
1643 } else if (IS_HASWELL(dev)) {
b146520f
BW		 1644 ppgtt->switch_mm = hsw_mm_switch;
1645 } else if (IS_GEN7(dev)) {
b146520f
BW		 1646 ppgtt->switch_mm = gen7_mm_switch;
1647 } else
1648 BUG();
1649
71ba2d64
YZ		 1650 if (intel_vgpu_active(dev))
1651 ppgtt->switch_mm = vgpu_mm_switch;
1652
b146520f
BW		 1653 ret = gen6_ppgtt_alloc(ppgtt);
1654 if (ret)
1655 return ret;
1656
5c5f6457 1657 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
b146520f
BW		 1658 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1659 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
777dc5bb
DV		 1660 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1661 ppgtt->base.bind_vma = ppgtt_bind_vma;
b146520f 1662 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
b146520f 1663 ppgtt->base.start = 0;
09942c65 1664 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
87d60b63 1665 ppgtt->debug_dump = gen6_dump_ppgtt;
1d2a314c 1666
44159ddb 1667 ppgtt->pd.base.ggtt_offset =
07749ef3 1668 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1d2a314c 1669
678d96fb 1670 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
44159ddb 1671 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
678d96fb 1672
5c5f6457 1673 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1d2a314c 1674
678d96fb
BW		 1675 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1676
440fd528 1677 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
b146520f
BW		 1678 ppgtt->node.size >> 20,
1679 ppgtt->node.start / PAGE_SIZE);
3440d265 1680
fa76da34 1681 DRM_DEBUG("Adding PPGTT at offset %x\n",
44159ddb 1682 ppgtt->pd.base.ggtt_offset << 10);
fa76da34 1683
b146520f 1684 return 0;
3440d265
DV		 1685}
1686
5c5f6457 1687static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
3440d265 1688{
853ba5d2 1689 ppgtt->base.dev = dev;
3440d265 1690
3ed124b2 1691 if (INTEL_INFO(dev)->gen < 8)
5c5f6457 1692 return gen6_ppgtt_init(ppgtt);
3ed124b2 1693 else
d7b2633d 1694 return gen8_ppgtt_init(ppgtt);
fa76da34 1695}
c114f76a 1696
fa76da34
DV		 1697int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1698{
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 int ret = 0;
3ed124b2 1701
5c5f6457 1702 ret = __hw_ppgtt_init(dev, ppgtt);
fa76da34 1703 if (ret == 0) {
c7c48dfd 1704 kref_init(&ppgtt->ref);
93bd8649
BW		 1705 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1706 ppgtt->base.total);
7e0d96bc 1707 i915_init_vm(dev_priv, &ppgtt->base);
93bd8649 1708 }
1d2a314c
DV		 1709
1710 return ret;
1711}
1712
82460d97
DV		 1713int i915_ppgtt_init_hw(struct drm_device *dev)
1714{
671b5013
TD		 1715 /* In the case of execlists, PPGTT is enabled by the context descriptor
1716 * and the PDPs are contained within the context itself. We don't
1717 * need to do anything here. */
1718 if (i915.enable_execlists)
1719 return 0;
1720
82460d97
DV		 1721 if (!USES_PPGTT(dev))
1722 return 0;
1723
1724 if (IS_GEN6(dev))
1725 gen6_ppgtt_enable(dev);
1726 else if (IS_GEN7(dev))
1727 gen7_ppgtt_enable(dev);
1728 else if (INTEL_INFO(dev)->gen >= 8)
1729 gen8_ppgtt_enable(dev);
1730 else
5f77eeb0 1731 MISSING_CASE(INTEL_INFO(dev)->gen);
82460d97 1732
4ad2fd88
JH		 1733 return 0;
1734}
1d2a314c 1735
b3dd6b96 1736int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
4ad2fd88 1737{
b3dd6b96 1738 struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
4ad2fd88
JH		 1739 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1740
1741 if (i915.enable_execlists)
1742 return 0;
1743
1744 if (!ppgtt)
1745 return 0;
1746
e85b26dc 1747 return ppgtt->switch_mm(ppgtt, req);
1d2a314c 1748}
4ad2fd88 1749
4d884705
DV		 1750struct i915_hw_ppgtt *
1751i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1752{
1753 struct i915_hw_ppgtt *ppgtt;
1754 int ret;
1755
1756 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1757 if (!ppgtt)
1758 return ERR_PTR(-ENOMEM);
1759
1760 ret = i915_ppgtt_init(dev, ppgtt);
1761 if (ret) {
1762 kfree(ppgtt);
1763 return ERR_PTR(ret);
1764 }
1765
1766 ppgtt->file_priv = fpriv;
1767
198c974d
DCS		 1768 trace_i915_ppgtt_create(&ppgtt->base);
1769
4d884705
DV		 1770 return ppgtt;
1771}
1772
ee960be7
DV		 1773void i915_ppgtt_release(struct kref *kref)
1774{
1775 struct i915_hw_ppgtt *ppgtt =
1776 container_of(kref, struct i915_hw_ppgtt, ref);
1777
198c974d
DCS		 1778 trace_i915_ppgtt_release(&ppgtt->base);
1779
ee960be7
DV		 1780 /* vmas should already be unbound */
1781 WARN_ON(!list_empty(&ppgtt->base.active_list));
1782 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1783
19dd120c
DV		 1784 list_del(&ppgtt->base.global_link);
1785 drm_mm_takedown(&ppgtt->base.mm);
1786
ee960be7
DV		 1787 ppgtt->base.cleanup(&ppgtt->base);
1788 kfree(ppgtt);
1789}
1d2a314c 1790
a81cc00c
BW		 1791extern int intel_iommu_gfx_mapped;
1792/* Certain Gen5 chipsets require require idling the GPU before
1793 * unmapping anything from the GTT when VT-d is enabled.
1794 */
2c642b07 1795static bool needs_idle_maps(struct drm_device *dev)
a81cc00c
BW		 1796{
1797#ifdef CONFIG_INTEL_IOMMU
1798 /* Query intel_iommu to see if we need the workaround. Presumably that
1799 * was loaded first.
1800 */
1801 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1802 return true;
1803#endif
1804 return false;
1805}
1806
5c042287
BW		 1807static bool do_idling(struct drm_i915_private *dev_priv)
1808{
1809 bool ret = dev_priv->mm.interruptible;
1810
a81cc00c 1811 if (unlikely(dev_priv->gtt.do_idle_maps)) {
5c042287 1812 dev_priv->mm.interruptible = false;
b2da9fe5 1813 if (i915_gpu_idle(dev_priv->dev)) {
5c042287
BW		 1814 DRM_ERROR("Couldn't idle GPU\n");
1815 /* Wait a bit, in hopes it avoids the hang */
1816 udelay(10);
1817 }
1818 }
1819
1820 return ret;
1821}
1822
1823static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1824{
a81cc00c 1825 if (unlikely(dev_priv->gtt.do_idle_maps))
5c042287
BW		 1826 dev_priv->mm.interruptible = interruptible;
1827}
1828
828c7908
BW		 1829void i915_check_and_clear_faults(struct drm_device *dev)
1830{
1831 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1832 struct intel_engine_cs *ring;
828c7908
BW		 1833 int i;
1834
1835 if (INTEL_INFO(dev)->gen < 6)
1836 return;
1837
1838 for_each_ring(ring, dev_priv, i) {
1839 u32 fault_reg;
1840 fault_reg = I915_READ(RING_FAULT_REG(ring));
1841 if (fault_reg & RING_FAULT_VALID) {
1842 DRM_DEBUG_DRIVER("Unexpected fault\n"
59a5d290 1843 "\tAddr: 0x%08lx\n"
828c7908
BW		 1844 "\tAddress space: %s\n"
1845 "\tSource ID: %d\n"
1846 "\tType: %d\n",
1847 fault_reg & PAGE_MASK,
1848 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1849 RING_FAULT_SRCID(fault_reg),
1850 RING_FAULT_FAULT_TYPE(fault_reg));
1851 I915_WRITE(RING_FAULT_REG(ring),
1852 fault_reg & ~RING_FAULT_VALID);
1853 }
1854 }
1855 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1856}
1857
91e56499
CW		 1858static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1859{
1860 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1861 intel_gtt_chipset_flush();
1862 } else {
1863 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1864 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1865 }
1866}
1867
828c7908
BW		 1868void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1869{
1870 struct drm_i915_private *dev_priv = dev->dev_private;
1871
1872 /* Don't bother messing with faults pre GEN6 as we have little
1873 * documentation supporting that it's a good idea.
1874 */
1875 if (INTEL_INFO(dev)->gen < 6)
1876 return;
1877
1878 i915_check_and_clear_faults(dev);
1879
1880 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
782f1495
BW		 1881 dev_priv->gtt.base.start,
1882 dev_priv->gtt.base.total,
e568af1c 1883 true);
91e56499
CW		 1884
1885 i915_ggtt_flush(dev_priv);
828c7908
BW		 1886}
1887
74163907 1888int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
7c2e6fdf 1889{
9da3da66
CW		 1890 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1891 obj->pages->sgl, obj->pages->nents,
1892 PCI_DMA_BIDIRECTIONAL))
1893 return -ENOSPC;
1894
1895 return 0;
7c2e6fdf
DV		 1896}
1897
2c642b07 1898static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
94ec8f61
BW		 1899{
1900#ifdef writeq
1901 writeq(pte, addr);
1902#else
1903 iowrite32((u32)pte, addr);
1904 iowrite32(pte >> 32, addr + 4);
1905#endif
1906}
1907
1908static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1909 struct sg_table *st,
782f1495 1910 uint64_t start,
24f3a8cf 1911 enum i915_cache_level level, u32 unused)
94ec8f61
BW		 1912{
1913 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 1914 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1915 gen8_pte_t __iomem *gtt_entries =
1916 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
94ec8f61
BW		 1917 int i = 0;
1918 struct sg_page_iter sg_iter;
57007df7 1919 dma_addr_t addr = 0; /* shut up gcc */
94ec8f61
BW		 1920
1921 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1922 addr = sg_dma_address(sg_iter.sg) +
1923 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1924 gen8_set_pte(&gtt_entries[i],
1925 gen8_pte_encode(addr, level, true));
1926 i++;
1927 }
1928
1929 /*
1930 * XXX: This serves as a posting read to make sure that the PTE has
1931 * actually been updated. There is some concern that even though
1932 * registers and PTEs are within the same BAR that they are potentially
1933 * of NUMA access patterns. Therefore, even with the way we assume
1934 * hardware should work, we must keep this posting read for paranoia.
1935 */
1936 if (i != 0)
1937 WARN_ON(readq(&gtt_entries[i-1])
1938 != gen8_pte_encode(addr, level, true));
1939
94ec8f61
BW		 1940 /* This next bit makes the above posting read even more important. We
1941 * want to flush the TLBs only after we're certain all the PTE updates
1942 * have finished.
1943 */
1944 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1945 POSTING_READ(GFX_FLSH_CNTL_GEN6);
94ec8f61
BW		 1946}
1947
e76e9aeb
BW		 1948/*
1949 * Binds an object into the global gtt with the specified cache level. The object
1950 * will be accessible to the GPU via commands whose operands reference offsets
1951 * within the global GTT as well as accessible by the GPU through the GMADR
1952 * mapped BAR (dev_priv->mm.gtt->gtt).
1953 */
853ba5d2 1954static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
7faf1ab2 1955 struct sg_table *st,
782f1495 1956 uint64_t start,
24f3a8cf 1957 enum i915_cache_level level, u32 flags)
e76e9aeb 1958{
853ba5d2 1959 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 1960 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1961 gen6_pte_t __iomem *gtt_entries =
1962 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
6e995e23
ID		 1963 int i = 0;
1964 struct sg_page_iter sg_iter;
57007df7 1965 dma_addr_t addr = 0;
e76e9aeb 1966
6e995e23 1967 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2db76d7c 1968 addr = sg_page_iter_dma_address(&sg_iter);
24f3a8cf 1969 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
6e995e23 1970 i++;
e76e9aeb
BW		 1971 }
1972
e76e9aeb
BW		 1973 /* XXX: This serves as a posting read to make sure that the PTE has
1974 * actually been updated. There is some concern that even though
1975 * registers and PTEs are within the same BAR that they are potentially
1976 * of NUMA access patterns. Therefore, even with the way we assume
1977 * hardware should work, we must keep this posting read for paranoia.
1978 */
57007df7
PM		 1979 if (i != 0) {
1980 unsigned long gtt = readl(&gtt_entries[i-1]);
1981 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1982 }
0f9b91c7
BW		 1983
1984 /* This next bit makes the above posting read even more important. We
1985 * want to flush the TLBs only after we're certain all the PTE updates
1986 * have finished.
1987 */
1988 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1989 POSTING_READ(GFX_FLSH_CNTL_GEN6);
e76e9aeb
BW		 1990}
1991
94ec8f61 1992static void gen8_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1993 uint64_t start,
1994 uint64_t length,
94ec8f61
BW		 1995 bool use_scratch)
1996{
1997 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 1998 unsigned first_entry = start >> PAGE_SHIFT;
1999 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 2000 gen8_pte_t scratch_pte, __iomem *gtt_base =
2001 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
94ec8f61
BW		 2002 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2003 int i;
2004
2005 if (WARN(num_entries > max_entries,
2006 "First entry = %d; Num entries = %d (max=%d)\n",
2007 first_entry, num_entries, max_entries))
2008 num_entries = max_entries;
2009
c114f76a 2010 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
94ec8f61
BW		 2011 I915_CACHE_LLC,
2012 use_scratch);
2013 for (i = 0; i < num_entries; i++)
2014 gen8_set_pte(&gtt_base[i], scratch_pte);
2015 readl(gtt_base);
2016}
2017
853ba5d2 2018static void gen6_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2019 uint64_t start,
2020 uint64_t length,
828c7908 2021 bool use_scratch)
7faf1ab2 2022{
853ba5d2 2023 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 2024 unsigned first_entry = start >> PAGE_SHIFT;
2025 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 2026 gen6_pte_t scratch_pte, __iomem *gtt_base =
2027 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
a54c0c27 2028 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
7faf1ab2
DV		 2029 int i;
2030
2031 if (WARN(num_entries > max_entries,
2032 "First entry = %d; Num entries = %d (max=%d)\n",
2033 first_entry, num_entries, max_entries))
2034 num_entries = max_entries;
2035
c114f76a
MK		 2036 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2037 I915_CACHE_LLC, use_scratch, 0);
828c7908 2038
7faf1ab2
DV		 2039 for (i = 0; i < num_entries; i++)
2040 iowrite32(scratch_pte, &gtt_base[i]);
2041 readl(gtt_base);
2042}
2043
d369d2d9
DV		 2044static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2045 struct sg_table *pages,
2046 uint64_t start,
2047 enum i915_cache_level cache_level, u32 unused)
7faf1ab2
DV		 2048{
2049 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2050 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2051
d369d2d9 2052 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
0875546c 2053
7faf1ab2
DV		 2054}
2055
853ba5d2 2056static void i915_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2057 uint64_t start,
2058 uint64_t length,
828c7908 2059 bool unused)
7faf1ab2 2060{
782f1495
BW		 2061 unsigned first_entry = start >> PAGE_SHIFT;
2062 unsigned num_entries = length >> PAGE_SHIFT;
7faf1ab2
DV		 2063 intel_gtt_clear_range(first_entry, num_entries);
2064}
2065
70b9f6f8
DV		 2066static int ggtt_bind_vma(struct i915_vma *vma,
2067 enum i915_cache_level cache_level,
2068 u32 flags)
d5bd1449 2069{
6f65e29a 2070 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2071 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2072 struct drm_i915_gem_object *obj = vma->obj;
ec7adb6e 2073 struct sg_table *pages = obj->pages;
f329f5f6 2074 u32 pte_flags = 0;
70b9f6f8
DV		 2075 int ret;
2076
2077 ret = i915_get_ggtt_vma_pages(vma);
2078 if (ret)
2079 return ret;
2080 pages = vma->ggtt_view.pages;
7faf1ab2 2081
24f3a8cf
AG		 2082 /* Currently applicable only to VLV */
2083 if (obj->gt_ro)
f329f5f6 2084 pte_flags |= PTE_READ_ONLY;
24f3a8cf 2085
ec7adb6e 2086
6f65e29a 2087 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
0875546c
DV		 2088 vma->vm->insert_entries(vma->vm, pages,
2089 vma->node.start,
2090 cache_level, pte_flags);
d0e30adc
CW		 2091
2092 /* Note the inconsistency here is due to absence of the
2093 * aliasing ppgtt on gen4 and earlier. Though we always
2094 * request PIN_USER for execbuffer (translated to LOCAL_BIND),
2095 * without the appgtt, we cannot honour that request and so
2096 * must substitute it with a global binding. Since we do this
2097 * behind the upper layers back, we need to explicitly set
2098 * the bound flag ourselves.
2099 */
2100 vma->bound |= GLOBAL_BIND;
2101
6f65e29a 2102 }
d5bd1449 2103
0875546c 2104 if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
6f65e29a 2105 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
ec7adb6e 2106 appgtt->base.insert_entries(&appgtt->base, pages,
782f1495 2107 vma->node.start,
f329f5f6 2108 cache_level, pte_flags);
6f65e29a 2109 }
70b9f6f8
DV		 2110
2111 return 0;
d5bd1449
CW		 2112}
2113
6f65e29a 2114static void ggtt_unbind_vma(struct i915_vma *vma)
74163907 2115{
6f65e29a 2116 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2117 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2118 struct drm_i915_gem_object *obj = vma->obj;
06615ee5
JL		 2119 const uint64_t size = min_t(uint64_t,
2120 obj->base.size,
2121 vma->node.size);
6f65e29a 2122
aff43766 2123 if (vma->bound & GLOBAL_BIND) {
782f1495
BW		 2124 vma->vm->clear_range(vma->vm,
2125 vma->node.start,
06615ee5 2126 size,
6f65e29a 2127 true);
6f65e29a 2128 }
74898d7e 2129
0875546c 2130 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
6f65e29a 2131 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
06615ee5 2132
6f65e29a 2133 appgtt->base.clear_range(&appgtt->base,
782f1495 2134 vma->node.start,
06615ee5 2135 size,
6f65e29a 2136 true);
6f65e29a 2137 }
74163907
DV		 2138}
2139
2140void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2141{
5c042287
BW		 2142 struct drm_device *dev = obj->base.dev;
2143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 bool interruptible;
2145
2146 interruptible = do_idling(dev_priv);
2147
5ec5b516
ID		 2148 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2149 PCI_DMA_BIDIRECTIONAL);
5c042287
BW		 2150
2151 undo_idling(dev_priv, interruptible);
7c2e6fdf 2152}
644ec02b 2153
42d6ab48
CW		 2154static void i915_gtt_color_adjust(struct drm_mm_node *node,
2155 unsigned long color,
440fd528
TR		 2156 u64 *start,
2157 u64 *end)
42d6ab48
CW		 2158{
2159 if (node->color != color)
2160 *start += 4096;
2161
2162 if (!list_empty(&node->node_list)) {
2163 node = list_entry(node->node_list.next,
2164 struct drm_mm_node,
2165 node_list);
2166 if (node->allocated && node->color != color)
2167 *end -= 4096;
2168 }
2169}
fbe5d36e 2170
f548c0e9
DV		 2171static int i915_gem_setup_global_gtt(struct drm_device *dev,
2172 unsigned long start,
2173 unsigned long mappable_end,
2174 unsigned long end)
644ec02b 2175{
e78891ca
BW		 2176 /* Let GEM Manage all of the aperture.
2177 *
2178 * However, leave one page at the end still bound to the scratch page.
2179 * There are a number of places where the hardware apparently prefetches
2180 * past the end of the object, and we've seen multiple hangs with the
2181 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2182 * aperture. One page should be enough to keep any prefetching inside
2183 * of the aperture.
2184 */
40d74980
BW		 2185 struct drm_i915_private *dev_priv = dev->dev_private;
2186 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
ed2f3452
CW		 2187 struct drm_mm_node *entry;
2188 struct drm_i915_gem_object *obj;
2189 unsigned long hole_start, hole_end;
fa76da34 2190 int ret;
644ec02b 2191
35451cb6
BW		 2192 BUG_ON(mappable_end > end);
2193
ed2f3452 2194 /* Subtract the guard page ... */
40d74980 2195 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
5dda8fa3
YZ		 2196
2197 dev_priv->gtt.base.start = start;
2198 dev_priv->gtt.base.total = end - start;
2199
2200 if (intel_vgpu_active(dev)) {
2201 ret = intel_vgt_balloon(dev);
2202 if (ret)
2203 return ret;
2204 }
2205
42d6ab48 2206 if (!HAS_LLC(dev))
93bd8649 2207 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
644ec02b 2208
ed2f3452 2209 /* Mark any preallocated objects as occupied */
35c20a60 2210 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
40d74980 2211 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
fa76da34 2212
edd41a87 2213 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
c6cfb325
BW		 2214 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2215
2216 WARN_ON(i915_gem_obj_ggtt_bound(obj));
40d74980 2217 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
6c5566a8
DV		 2218 if (ret) {
2219 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2220 return ret;
2221 }
aff43766 2222 vma->bound |= GLOBAL_BIND;
ed2f3452
CW		 2223 }
2224
ed2f3452 2225 /* Clear any non-preallocated blocks */
40d74980 2226 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
ed2f3452
CW		 2227 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2228 hole_start, hole_end);
782f1495
BW		 2229 ggtt_vm->clear_range(ggtt_vm, hole_start,
2230 hole_end - hole_start, true);
ed2f3452
CW		 2231 }
2232
2233 /* And finally clear the reserved guard page */
782f1495 2234 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
6c5566a8 2235
fa76da34
DV		 2236 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2237 struct i915_hw_ppgtt *ppgtt;
2238
2239 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2240 if (!ppgtt)
2241 return -ENOMEM;
2242
5c5f6457
DV		 2243 ret = __hw_ppgtt_init(dev, ppgtt);
2244 if (ret) {
2245 ppgtt->base.cleanup(&ppgtt->base);
2246 kfree(ppgtt);
2247 return ret;
2248 }
2249
2250 if (ppgtt->base.allocate_va_range)
2251 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2252 ppgtt->base.total);
4933d519 2253 if (ret) {
061dd493 2254 ppgtt->base.cleanup(&ppgtt->base);
4933d519 2255 kfree(ppgtt);
fa76da34 2256 return ret;
4933d519 2257 }
fa76da34 2258
5c5f6457
DV		 2259 ppgtt->base.clear_range(&ppgtt->base,
2260 ppgtt->base.start,
2261 ppgtt->base.total,
2262 true);
2263
fa76da34
DV		 2264 dev_priv->mm.aliasing_ppgtt = ppgtt;
2265 }
2266
6c5566a8 2267 return 0;
e76e9aeb
BW		 2268}
2269
d7e5008f
BW		 2270void i915_gem_init_global_gtt(struct drm_device *dev)
2271{
2272 struct drm_i915_private *dev_priv = dev->dev_private;
c44ef60e 2273 u64 gtt_size, mappable_size;
d7e5008f 2274
853ba5d2 2275 gtt_size = dev_priv->gtt.base.total;
93d18799 2276 mappable_size = dev_priv->gtt.mappable_end;
d7e5008f 2277
e78891ca 2278 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
e76e9aeb
BW		 2279}
2280
90d0a0e8
DV		 2281void i915_global_gtt_cleanup(struct drm_device *dev)
2282{
2283 struct drm_i915_private *dev_priv = dev->dev_private;
2284 struct i915_address_space *vm = &dev_priv->gtt.base;
2285
70e32544
DV		 2286 if (dev_priv->mm.aliasing_ppgtt) {
2287 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2288
2289 ppgtt->base.cleanup(&ppgtt->base);
2290 }
2291
90d0a0e8 2292 if (drm_mm_initialized(&vm->mm)) {
5dda8fa3
YZ		 2293 if (intel_vgpu_active(dev))
2294 intel_vgt_deballoon();
2295
90d0a0e8
DV		 2296 drm_mm_takedown(&vm->mm);
2297 list_del(&vm->global_link);
2298 }
2299
2300 vm->cleanup(vm);
2301}
70e32544 2302
2c642b07 2303static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2304{
2305 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2306 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2307 return snb_gmch_ctl << 20;
2308}
2309
2c642b07 2310static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
9459d252
BW		 2311{
2312 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2313 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2314 if (bdw_gmch_ctl)
2315 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
562d55d9
BW		 2316
2317#ifdef CONFIG_X86_32
2318 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2319 if (bdw_gmch_ctl > 4)
2320 bdw_gmch_ctl = 4;
2321#endif
2322
9459d252
BW		 2323 return bdw_gmch_ctl << 20;
2324}
2325
2c642b07 2326static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
d7f25f23
DL		 2327{
2328 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2329 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2330
2331 if (gmch_ctrl)
2332 return 1 << (20 + gmch_ctrl);
2333
2334 return 0;
2335}
2336
2c642b07 2337static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2338{
2339 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2340 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2341 return snb_gmch_ctl << 25; /* 32 MB units */
2342}
2343
2c642b07 2344static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
9459d252
BW		 2345{
2346 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2347 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2348 return bdw_gmch_ctl << 25; /* 32 MB units */
2349}
2350
d7f25f23
DL		 2351static size_t chv_get_stolen_size(u16 gmch_ctrl)
2352{
2353 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2354 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2355
2356 /*
2357 * 0x0 to 0x10: 32MB increments starting at 0MB
2358 * 0x11 to 0x16: 4MB increments starting at 8MB
2359 * 0x17 to 0x1d: 4MB increments start at 36MB
2360 */
2361 if (gmch_ctrl < 0x11)
2362 return gmch_ctrl << 25;
2363 else if (gmch_ctrl < 0x17)
2364 return (gmch_ctrl - 0x11 + 2) << 22;
2365 else
2366 return (gmch_ctrl - 0x17 + 9) << 22;
2367}
2368
66375014
DL		 2369static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2370{
2371 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2372 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2373
2374 if (gen9_gmch_ctl < 0xf0)
2375 return gen9_gmch_ctl << 25; /* 32 MB units */
2376 else
2377 /* 4MB increments starting at 0xf0 for 4MB */
2378 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2379}
2380
63340133
BW		 2381static int ggtt_probe_common(struct drm_device *dev,
2382 size_t gtt_size)
2383{
2384 struct drm_i915_private *dev_priv = dev->dev_private;
4ad2af1e 2385 struct i915_page_scratch *scratch_page;
21c34607 2386 phys_addr_t gtt_phys_addr;
63340133
BW		 2387
2388 /* For Modern GENs the PTEs and register space are split in the BAR */
21c34607 2389 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
63340133
BW		 2390 (pci_resource_len(dev->pdev, 0) / 2);
2391
2a073f89
ID		 2392 /*
2393 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2394 * dropped. For WC mappings in general we have 64 byte burst writes
2395 * when the WC buffer is flushed, so we can't use it, but have to
2396 * resort to an uncached mapping. The WC issue is easily caught by the
2397 * readback check when writing GTT PTE entries.
2398 */
2399 if (IS_BROXTON(dev))
2400 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2401 else
2402 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
63340133
BW		 2403 if (!dev_priv->gtt.gsm) {
2404 DRM_ERROR("Failed to map the gtt page table\n");
2405 return -ENOMEM;
2406 }
2407
4ad2af1e
MK		 2408 scratch_page = alloc_scratch_page(dev);
2409 if (IS_ERR(scratch_page)) {
63340133
BW		 2410 DRM_ERROR("Scratch setup failed\n");
2411 /* iounmap will also get called at remove, but meh */
2412 iounmap(dev_priv->gtt.gsm);
4ad2af1e 2413 return PTR_ERR(scratch_page);
63340133
BW		 2414 }
2415
4ad2af1e
MK		 2416 dev_priv->gtt.base.scratch_page = scratch_page;
2417
2418 return 0;
63340133
BW		 2419}
2420
fbe5d36e
BW		 2421/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2422 * bits. When using advanced contexts each context stores its own PAT, but
2423 * writing this data shouldn't be harmful even in those cases. */
ee0ce478 2424static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
fbe5d36e 2425{
fbe5d36e
BW		 2426 uint64_t pat;
2427
2428 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2429 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2430 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2431 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2432 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2433 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2434 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2435 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2436
d6a8b72e
RV		 2437 if (!USES_PPGTT(dev_priv->dev))
2438 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2439 * so RTL will always use the value corresponding to
2440 * pat_sel = 000".
2441 * So let's disable cache for GGTT to avoid screen corruptions.
2442 * MOCS still can be used though.
2443 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2444 * before this patch, i.e. the same uncached + snooping access
2445 * like on gen6/7 seems to be in effect.
2446 * - So this just fixes blitter/render access. Again it looks
2447 * like it's not just uncached access, but uncached + snooping.
2448 * So we can still hold onto all our assumptions wrt cpu
2449 * clflushing on LLC machines.
2450 */
2451 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2452
fbe5d36e
BW		 2453 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2454 * write would work. */
2455 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2456 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2457}
2458
ee0ce478
VS		 2459static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2460{
2461 uint64_t pat;
2462
2463 /*
2464 * Map WB on BDW to snooped on CHV.
2465 *
2466 * Only the snoop bit has meaning for CHV, the rest is
2467 * ignored.
2468 *
cf3d262e
VS		 2469 * The hardware will never snoop for certain types of accesses:
2470 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2471 * - PPGTT page tables
2472 * - some other special cycles
2473 *
2474 * As with BDW, we also need to consider the following for GT accesses:
2475 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2476 * so RTL will always use the value corresponding to
2477 * pat_sel = 000".
2478 * Which means we must set the snoop bit in PAT entry 0
2479 * in order to keep the global status page working.
ee0ce478
VS		 2480 */
2481 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2482 GEN8_PPAT(1, 0) |
2483 GEN8_PPAT(2, 0) |
2484 GEN8_PPAT(3, 0) |
2485 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2486 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2487 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2488 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2489
2490 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2491 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2492}
2493
63340133 2494static int gen8_gmch_probe(struct drm_device *dev,
c44ef60e 2495 u64 *gtt_total,
63340133
BW		 2496 size_t *stolen,
2497 phys_addr_t *mappable_base,
c44ef60e 2498 u64 *mappable_end)
63340133
BW		 2499{
2500 struct drm_i915_private *dev_priv = dev->dev_private;
c44ef60e 2501 u64 gtt_size;
63340133
BW		 2502 u16 snb_gmch_ctl;
2503 int ret;
2504
2505 /* TODO: We're not aware of mappable constraints on gen8 yet */
2506 *mappable_base = pci_resource_start(dev->pdev, 2);
2507 *mappable_end = pci_resource_len(dev->pdev, 2);
2508
2509 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2510 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2511
2512 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2513
66375014
DL		 2514 if (INTEL_INFO(dev)->gen >= 9) {
2515 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2516 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2517 } else if (IS_CHERRYVIEW(dev)) {
d7f25f23
DL		 2518 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2519 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2520 } else {
2521 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2522 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2523 }
63340133 2524
07749ef3 2525 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
63340133 2526
5a4e33a3 2527 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
ee0ce478
VS		 2528 chv_setup_private_ppat(dev_priv);
2529 else
2530 bdw_setup_private_ppat(dev_priv);
fbe5d36e 2531
63340133
BW		 2532 ret = ggtt_probe_common(dev, gtt_size);
2533
94ec8f61
BW		 2534 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2535 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
777dc5bb
DV		 2536 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2537 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
63340133
BW		 2538
2539 return ret;
2540}
2541
baa09f5f 2542static int gen6_gmch_probe(struct drm_device *dev,
c44ef60e 2543 u64 *gtt_total,
41907ddc
BW		 2544 size_t *stolen,
2545 phys_addr_t *mappable_base,
c44ef60e 2546 u64 *mappable_end)
e76e9aeb
BW		 2547{
2548 struct drm_i915_private *dev_priv = dev->dev_private;
baa09f5f 2549 unsigned int gtt_size;
e76e9aeb 2550 u16 snb_gmch_ctl;
e76e9aeb
BW		 2551 int ret;
2552
41907ddc
BW		 2553 *mappable_base = pci_resource_start(dev->pdev, 2);
2554 *mappable_end = pci_resource_len(dev->pdev, 2);
2555
baa09f5f
BW		 2556 /* 64/512MB is the current min/max we actually know of, but this is just
2557 * a coarse sanity check.
e76e9aeb 2558 */
41907ddc 2559 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
c44ef60e 2560 DRM_ERROR("Unknown GMADR size (%llx)\n",
baa09f5f
BW		 2561 dev_priv->gtt.mappable_end);
2562 return -ENXIO;
e76e9aeb
BW		 2563 }
2564
e76e9aeb
BW		 2565 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2566 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
e76e9aeb 2567 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
e76e9aeb 2568
c4ae25ec 2569 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
a93e4161 2570
63340133 2571 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
07749ef3 2572 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
e76e9aeb 2573
63340133 2574 ret = ggtt_probe_common(dev, gtt_size);
e76e9aeb 2575
853ba5d2
BW		 2576 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2577 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
777dc5bb
DV		 2578 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2579 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
7faf1ab2 2580
e76e9aeb
BW		 2581 return ret;
2582}
2583
853ba5d2 2584static void gen6_gmch_remove(struct i915_address_space *vm)
e76e9aeb 2585{
853ba5d2
BW		 2586
2587 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
5ed16782 2588
853ba5d2 2589 iounmap(gtt->gsm);
4ad2af1e 2590 free_scratch_page(vm->dev, vm->scratch_page);
644ec02b 2591}
baa09f5f
BW		 2592
2593static int i915_gmch_probe(struct drm_device *dev,
c44ef60e 2594 u64 *gtt_total,
41907ddc
BW		 2595 size_t *stolen,
2596 phys_addr_t *mappable_base,
c44ef60e 2597 u64 *mappable_end)
baa09f5f
BW		 2598{
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 int ret;
2601
baa09f5f
BW		 2602 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2603 if (!ret) {
2604 DRM_ERROR("failed to set up gmch\n");
2605 return -EIO;
2606 }
2607
41907ddc 2608 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
baa09f5f
BW		 2609
2610 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
d369d2d9 2611 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
853ba5d2 2612 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
d369d2d9
DV		 2613 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2614 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
baa09f5f 2615
c0a7f818
CW		 2616 if (unlikely(dev_priv->gtt.do_idle_maps))
2617 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2618
baa09f5f
BW		 2619 return 0;
2620}
2621
853ba5d2 2622static void i915_gmch_remove(struct i915_address_space *vm)
baa09f5f
BW		 2623{
2624 intel_gmch_remove();
2625}
2626
2627int i915_gem_gtt_init(struct drm_device *dev)
2628{
2629 struct drm_i915_private *dev_priv = dev->dev_private;
2630 struct i915_gtt *gtt = &dev_priv->gtt;
baa09f5f
BW		 2631 int ret;
2632
baa09f5f 2633 if (INTEL_INFO(dev)->gen <= 5) {
b2f21b4d 2634 gtt->gtt_probe = i915_gmch_probe;
853ba5d2 2635 gtt->base.cleanup = i915_gmch_remove;
63340133 2636 } else if (INTEL_INFO(dev)->gen < 8) {
b2f21b4d 2637 gtt->gtt_probe = gen6_gmch_probe;
853ba5d2 2638 gtt->base.cleanup = gen6_gmch_remove;
4d15c145 2639 if (IS_HASWELL(dev) && dev_priv->ellc_size)
853ba5d2 2640 gtt->base.pte_encode = iris_pte_encode;
4d15c145 2641 else if (IS_HASWELL(dev))
853ba5d2 2642 gtt->base.pte_encode = hsw_pte_encode;
b2f21b4d 2643 else if (IS_VALLEYVIEW(dev))
853ba5d2 2644 gtt->base.pte_encode = byt_pte_encode;
350ec881
CW		 2645 else if (INTEL_INFO(dev)->gen >= 7)
2646 gtt->base.pte_encode = ivb_pte_encode;
b2f21b4d 2647 else
350ec881 2648 gtt->base.pte_encode = snb_pte_encode;
63340133
BW		 2649 } else {
2650 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2651 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
baa09f5f
BW		 2652 }
2653
c114f76a
MK		 2654 gtt->base.dev = dev;
2655
853ba5d2 2656 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
b2f21b4d 2657 &gtt->mappable_base, &gtt->mappable_end);
a54c0c27 2658 if (ret)
baa09f5f 2659 return ret;
baa09f5f 2660
baa09f5f 2661 /* GMADR is the PCI mmio aperture into the global GTT. */
c44ef60e 2662 DRM_INFO("Memory usable by graphics device = %lluM\n",
853ba5d2 2663 gtt->base.total >> 20);
c44ef60e 2664 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
b2f21b4d 2665 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
5db6c735
DV		 2666#ifdef CONFIG_INTEL_IOMMU
2667 if (intel_iommu_gfx_mapped)
2668 DRM_INFO("VT-d active for gfx access\n");
2669#endif
cfa7c862
DV		 2670 /*
2671 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2672 * user's requested state against the hardware/driver capabilities. We
2673 * do this now so that we can print out any log messages once rather
2674 * than every time we check intel_enable_ppgtt().
2675 */
2676 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2677 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
baa09f5f
BW		 2678
2679 return 0;
2680}
6f65e29a 2681
fa42331b
DV		 2682void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2683{
2684 struct drm_i915_private *dev_priv = dev->dev_private;
2685 struct drm_i915_gem_object *obj;
2686 struct i915_address_space *vm;
2c3d9984
TU		 2687 struct i915_vma *vma;
2688 bool flush;
fa42331b
DV		 2689
2690 i915_check_and_clear_faults(dev);
2691
2692 /* First fill our portion of the GTT with scratch pages */
2693 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2694 dev_priv->gtt.base.start,
2695 dev_priv->gtt.base.total,
2696 true);
2697
2c3d9984
TU		 2698 /* Cache flush objects bound into GGTT and rebind them. */
2699 vm = &dev_priv->gtt.base;
fa42331b 2700 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2c3d9984
TU		 2701 flush = false;
2702 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2703 if (vma->vm != vm)
2704 continue;
fa42331b 2705
2c3d9984
TU		 2706 WARN_ON(i915_vma_bind(vma, obj->cache_level,
2707 PIN_UPDATE));
fa42331b 2708
2c3d9984
TU		 2709 flush = true;
2710 }
2711
2712 if (flush)
2713 i915_gem_clflush_object(obj, obj->pin_display);
2714 }
fa42331b
DV		 2715
2716 if (INTEL_INFO(dev)->gen >= 8) {
2717 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2718 chv_setup_private_ppat(dev_priv);
2719 else
2720 bdw_setup_private_ppat(dev_priv);
2721
2722 return;
2723 }
2724
2725 if (USES_PPGTT(dev)) {
2726 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2727 /* TODO: Perhaps it shouldn't be gen6 specific */
2728
2729 struct i915_hw_ppgtt *ppgtt =
2730 container_of(vm, struct i915_hw_ppgtt,
2731 base);
2732
2733 if (i915_is_ggtt(vm))
2734 ppgtt = dev_priv->mm.aliasing_ppgtt;
2735
2736 gen6_write_page_range(dev_priv, &ppgtt->pd,
2737 0, ppgtt->base.total);
2738 }
2739 }
2740
2741 i915_ggtt_flush(dev_priv);
2742}
2743
ec7adb6e
JL		 2744static struct i915_vma *
2745__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2746 struct i915_address_space *vm,
2747 const struct i915_ggtt_view *ggtt_view)
6f65e29a 2748{
dabde5c7 2749 struct i915_vma *vma;
6f65e29a 2750
ec7adb6e
JL		 2751 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2752 return ERR_PTR(-EINVAL);
e20d2ab7
CW		 2753
2754 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
dabde5c7
DC		 2755 if (vma == NULL)
2756 return ERR_PTR(-ENOMEM);
ec7adb6e 2757
6f65e29a
BW		 2758 INIT_LIST_HEAD(&vma->vma_link);
2759 INIT_LIST_HEAD(&vma->mm_list);
2760 INIT_LIST_HEAD(&vma->exec_list);
2761 vma->vm = vm;
2762 vma->obj = obj;
2763
777dc5bb 2764 if (i915_is_ggtt(vm))
ec7adb6e 2765 vma->ggtt_view = *ggtt_view;
6f65e29a 2766
f7635669
TU		 2767 list_add_tail(&vma->vma_link, &obj->vma_list);
2768 if (!i915_is_ggtt(vm))
e07f0552 2769 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
6f65e29a
BW		 2770
2771 return vma;
2772}
2773
2774struct i915_vma *
ec7adb6e
JL		 2775i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2776 struct i915_address_space *vm)
2777{
2778 struct i915_vma *vma;
2779
2780 vma = i915_gem_obj_to_vma(obj, vm);
2781 if (!vma)
2782 vma = __i915_gem_vma_create(obj, vm,
2783 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2784
2785 return vma;
2786}
2787
2788struct i915_vma *
2789i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
fe14d5f4 2790 const struct i915_ggtt_view *view)
6f65e29a 2791{
ec7adb6e 2792 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
6f65e29a
BW		 2793 struct i915_vma *vma;
2794
ec7adb6e
JL		 2795 if (WARN_ON(!view))
2796 return ERR_PTR(-EINVAL);
2797
2798 vma = i915_gem_obj_to_ggtt_view(obj, view);
2799
2800 if (IS_ERR(vma))
2801 return vma;
2802
6f65e29a 2803 if (!vma)
ec7adb6e 2804 vma = __i915_gem_vma_create(obj, ggtt, view);
6f65e29a
BW		 2805
2806 return vma;
ec7adb6e 2807
6f65e29a 2808}
fe14d5f4 2809
50470bb0
TU		 2810static void
2811rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2812 struct sg_table *st)
2813{
2814 unsigned int column, row;
2815 unsigned int src_idx;
2816 struct scatterlist *sg = st->sgl;
2817
2818 st->nents = 0;
2819
2820 for (column = 0; column < width; column++) {
2821 src_idx = width * (height - 1) + column;
2822 for (row = 0; row < height; row++) {
2823 st->nents++;
2824 /* We don't need the pages, but need to initialize
2825 * the entries so the sg list can be happily traversed.
2826 * The only thing we need are DMA addresses.
2827 */
2828 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2829 sg_dma_address(sg) = in[src_idx];
2830 sg_dma_len(sg) = PAGE_SIZE;
2831 sg = sg_next(sg);
2832 src_idx -= width;
2833 }
2834 }
2835}
2836
2837static struct sg_table *
2838intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2839 struct drm_i915_gem_object *obj)
2840{
50470bb0 2841 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
84fe03f7 2842 unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
50470bb0
TU		 2843 struct sg_page_iter sg_iter;
2844 unsigned long i;
2845 dma_addr_t *page_addr_list;
2846 struct sg_table *st;
1d00dad5 2847 int ret = -ENOMEM;
50470bb0 2848
50470bb0 2849 /* Allocate a temporary list of source pages for random access. */
84fe03f7
TU		 2850 page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
2851 sizeof(dma_addr_t));
50470bb0
TU		 2852 if (!page_addr_list)
2853 return ERR_PTR(ret);
2854
2855 /* Allocate target SG list. */
2856 st = kmalloc(sizeof(*st), GFP_KERNEL);
2857 if (!st)
2858 goto err_st_alloc;
2859
84fe03f7 2860 ret = sg_alloc_table(st, size_pages, GFP_KERNEL);
50470bb0
TU		 2861 if (ret)
2862 goto err_sg_alloc;
2863
2864 /* Populate source page list from the object. */
2865 i = 0;
2866 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2867 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2868 i++;
2869 }
2870
2871 /* Rotate the pages. */
84fe03f7
TU		 2872 rotate_pages(page_addr_list,
2873 rot_info->width_pages, rot_info->height_pages,
2874 st);
50470bb0
TU		 2875
2876 DRM_DEBUG_KMS(
84fe03f7 2877 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
c9f8fd2d 2878 obj->base.size, rot_info->pitch, rot_info->height,
84fe03f7
TU		 2879 rot_info->pixel_format, rot_info->width_pages,
2880 rot_info->height_pages, size_pages);
50470bb0
TU		 2881
2882 drm_free_large(page_addr_list);
2883
2884 return st;
2885
2886err_sg_alloc:
2887 kfree(st);
2888err_st_alloc:
2889 drm_free_large(page_addr_list);
2890
2891 DRM_DEBUG_KMS(
84fe03f7 2892 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
c9f8fd2d 2893 obj->base.size, ret, rot_info->pitch, rot_info->height,
84fe03f7
TU		 2894 rot_info->pixel_format, rot_info->width_pages,
2895 rot_info->height_pages, size_pages);
50470bb0
TU		 2896 return ERR_PTR(ret);
2897}
ec7adb6e 2898
8bd7ef16
JL		 2899static struct sg_table *
2900intel_partial_pages(const struct i915_ggtt_view *view,
2901 struct drm_i915_gem_object *obj)
2902{
2903 struct sg_table *st;
2904 struct scatterlist *sg;
2905 struct sg_page_iter obj_sg_iter;
2906 int ret = -ENOMEM;
2907
2908 st = kmalloc(sizeof(*st), GFP_KERNEL);
2909 if (!st)
2910 goto err_st_alloc;
2911
2912 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2913 if (ret)
2914 goto err_sg_alloc;
2915
2916 sg = st->sgl;
2917 st->nents = 0;
2918 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2919 view->params.partial.offset)
2920 {
2921 if (st->nents >= view->params.partial.size)
2922 break;
2923
2924 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2925 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2926 sg_dma_len(sg) = PAGE_SIZE;
2927
2928 sg = sg_next(sg);
2929 st->nents++;
2930 }
2931
2932 return st;
2933
2934err_sg_alloc:
2935 kfree(st);
2936err_st_alloc:
2937 return ERR_PTR(ret);
2938}
2939
70b9f6f8 2940static int
50470bb0 2941i915_get_ggtt_vma_pages(struct i915_vma *vma)
fe14d5f4 2942{
50470bb0
TU		 2943 int ret = 0;
2944
fe14d5f4
TU		 2945 if (vma->ggtt_view.pages)
2946 return 0;
2947
2948 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2949 vma->ggtt_view.pages = vma->obj->pages;
50470bb0
TU		 2950 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2951 vma->ggtt_view.pages =
2952 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
8bd7ef16
JL		 2953 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2954 vma->ggtt_view.pages =
2955 intel_partial_pages(&vma->ggtt_view, vma->obj);
fe14d5f4
TU		 2956 else
2957 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2958 vma->ggtt_view.type);
2959
2960 if (!vma->ggtt_view.pages) {
ec7adb6e 2961 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
fe14d5f4 2962 vma->ggtt_view.type);
50470bb0
TU		 2963 ret = -EINVAL;
2964 } else if (IS_ERR(vma->ggtt_view.pages)) {
2965 ret = PTR_ERR(vma->ggtt_view.pages);
2966 vma->ggtt_view.pages = NULL;
2967 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2968 vma->ggtt_view.type, ret);
fe14d5f4
TU		 2969 }
2970
50470bb0 2971 return ret;
fe14d5f4
TU		 2972}
2973
2974/**
2975 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2976 * @vma: VMA to map
2977 * @cache_level: mapping cache level
2978 * @flags: flags like global or local mapping
2979 *
2980 * DMA addresses are taken from the scatter-gather table of this object (or of
2981 * this VMA in case of non-default GGTT views) and PTE entries set up.
2982 * Note that DMA addresses are also the only part of the SG table we care about.
2983 */
2984int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2985 u32 flags)
2986{
75d04a37
MK		 2987 int ret;
2988 u32 bind_flags;
1d335d1b 2989
75d04a37
MK		 2990 if (WARN_ON(flags == 0))
2991 return -EINVAL;
1d335d1b 2992
75d04a37 2993 bind_flags = 0;
0875546c
DV		 2994 if (flags & PIN_GLOBAL)
2995 bind_flags |= GLOBAL_BIND;
2996 if (flags & PIN_USER)
2997 bind_flags |= LOCAL_BIND;
2998
2999 if (flags & PIN_UPDATE)
3000 bind_flags |= vma->bound;
3001 else
3002 bind_flags &= ~vma->bound;
3003
75d04a37
MK		 3004 if (bind_flags == 0)
3005 return 0;
3006
3007 if (vma->bound == 0 && vma->vm->allocate_va_range) {
3008 trace_i915_va_alloc(vma->vm,
3009 vma->node.start,
3010 vma->node.size,
3011 VM_TO_TRACE_NAME(vma->vm));
3012
b2dd4511
MK		 3013 /* XXX: i915_vma_pin() will fix this +- hack */
3014 vma->pin_count++;
75d04a37
MK		 3015 ret = vma->vm->allocate_va_range(vma->vm,
3016 vma->node.start,
3017 vma->node.size);
b2dd4511 3018 vma->pin_count--;
75d04a37
MK		 3019 if (ret)
3020 return ret;
3021 }
3022
3023 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
70b9f6f8
DV		 3024 if (ret)
3025 return ret;
0875546c
DV		 3026
3027 vma->bound |= bind_flags;
fe14d5f4
TU		 3028
3029 return 0;
3030}
91e6711e
JL		 3031
3032/**
3033 * i915_ggtt_view_size - Get the size of a GGTT view.
3034 * @obj: Object the view is of.
3035 * @view: The view in question.
3036 *
3037 * @return The size of the GGTT view in bytes.
3038 */
3039size_t
3040i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3041 const struct i915_ggtt_view *view)
3042{
9e759ff1 3043 if (view->type == I915_GGTT_VIEW_NORMAL) {
91e6711e 3044 return obj->base.size;
9e759ff1
TU		 3045 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3046 return view->rotation_info.size;
8bd7ef16
JL		 3047 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3048 return view->params.partial.size << PAGE_SHIFT;
91e6711e
JL		 3049 } else {
3050 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3051 return obj->base.size;
3052 }
3053}
Linux 6.x block layer and io_uring tree(s)