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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
d31eb10e | 33 | typedef uint64_t gen8_gtt_pte_t; |
37aca44a | 34 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; |
6670a5a5 | 35 | |
26b1ff35 BW |
36 | /* PPGTT stuff */ |
37 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 38 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
39 | |
40 | #define GEN6_PDE_VALID (1 << 0) | |
41 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
42 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
43 | ||
44 | #define GEN6_PTE_VALID (1 << 0) | |
45 | #define GEN6_PTE_UNCACHED (1 << 1) | |
46 | #define HSW_PTE_UNCACHED (0) | |
47 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 48 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 49 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
50 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
51 | ||
52 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
53 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
54 | */ | |
55 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
56 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 57 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 58 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 59 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
651d794f | 60 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
26b1ff35 | 61 | |
459108b8 | 62 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) |
37aca44a BW |
63 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
64 | #define GEN8_LEGACY_PDPS 4 | |
65 | ||
fbe5d36e BW |
66 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
67 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
68 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
69 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
70 | ||
94ec8f61 BW |
71 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
72 | enum i915_cache_level level, | |
73 | bool valid) | |
74 | { | |
75 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
76 | pte |= addr; | |
fbe5d36e BW |
77 | if (level != I915_CACHE_NONE) |
78 | pte |= PPAT_CACHED_INDEX; | |
79 | else | |
80 | pte |= PPAT_UNCACHED_INDEX; | |
94ec8f61 BW |
81 | return pte; |
82 | } | |
83 | ||
b1fe6673 BW |
84 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
85 | dma_addr_t addr, | |
86 | enum i915_cache_level level) | |
87 | { | |
88 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
89 | pde |= addr; | |
90 | if (level != I915_CACHE_NONE) | |
91 | pde |= PPAT_CACHED_PDE_INDEX; | |
92 | else | |
93 | pde |= PPAT_UNCACHED_INDEX; | |
94 | return pde; | |
95 | } | |
96 | ||
350ec881 | 97 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
98 | enum i915_cache_level level, |
99 | bool valid) | |
54d12527 | 100 | { |
b35b380e | 101 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 102 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
103 | |
104 | switch (level) { | |
350ec881 CW |
105 | case I915_CACHE_L3_LLC: |
106 | case I915_CACHE_LLC: | |
107 | pte |= GEN6_PTE_CACHE_LLC; | |
108 | break; | |
109 | case I915_CACHE_NONE: | |
110 | pte |= GEN6_PTE_UNCACHED; | |
111 | break; | |
112 | default: | |
113 | WARN_ON(1); | |
114 | } | |
115 | ||
116 | return pte; | |
117 | } | |
118 | ||
119 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
120 | enum i915_cache_level level, |
121 | bool valid) | |
350ec881 | 122 | { |
b35b380e | 123 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
124 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
125 | ||
126 | switch (level) { | |
127 | case I915_CACHE_L3_LLC: | |
128 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
129 | break; |
130 | case I915_CACHE_LLC: | |
131 | pte |= GEN6_PTE_CACHE_LLC; | |
132 | break; | |
133 | case I915_CACHE_NONE: | |
9119708c | 134 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
135 | break; |
136 | default: | |
350ec881 | 137 | WARN_ON(1); |
e7210c3c BW |
138 | } |
139 | ||
54d12527 BW |
140 | return pte; |
141 | } | |
142 | ||
93c34e70 KG |
143 | #define BYT_PTE_WRITEABLE (1 << 1) |
144 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
145 | ||
80a74f7f | 146 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
147 | enum i915_cache_level level, |
148 | bool valid) | |
93c34e70 | 149 | { |
b35b380e | 150 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
151 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
152 | ||
153 | /* Mark the page as writeable. Other platforms don't have a | |
154 | * setting for read-only/writable, so this matches that behavior. | |
155 | */ | |
156 | pte |= BYT_PTE_WRITEABLE; | |
157 | ||
158 | if (level != I915_CACHE_NONE) | |
159 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
160 | ||
161 | return pte; | |
162 | } | |
163 | ||
80a74f7f | 164 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
165 | enum i915_cache_level level, |
166 | bool valid) | |
9119708c | 167 | { |
b35b380e | 168 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 169 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
170 | |
171 | if (level != I915_CACHE_NONE) | |
87a6b688 | 172 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
173 | |
174 | return pte; | |
175 | } | |
176 | ||
4d15c145 | 177 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
178 | enum i915_cache_level level, |
179 | bool valid) | |
4d15c145 | 180 | { |
b35b380e | 181 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
182 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
183 | ||
651d794f CW |
184 | switch (level) { |
185 | case I915_CACHE_NONE: | |
186 | break; | |
187 | case I915_CACHE_WT: | |
188 | pte |= HSW_WT_ELLC_LLC_AGE0; | |
189 | break; | |
190 | default: | |
4d15c145 | 191 | pte |= HSW_WB_ELLC_LLC_AGE0; |
651d794f CW |
192 | break; |
193 | } | |
4d15c145 BW |
194 | |
195 | return pte; | |
196 | } | |
197 | ||
94e409c1 BW |
198 | /* Broadwell Page Directory Pointer Descriptors */ |
199 | static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry, | |
e178f705 | 200 | uint64_t val, bool synchronous) |
94e409c1 | 201 | { |
e178f705 | 202 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
94e409c1 BW |
203 | int ret; |
204 | ||
205 | BUG_ON(entry >= 4); | |
206 | ||
e178f705 BW |
207 | if (synchronous) { |
208 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); | |
209 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); | |
210 | return 0; | |
211 | } | |
212 | ||
94e409c1 BW |
213 | ret = intel_ring_begin(ring, 6); |
214 | if (ret) | |
215 | return ret; | |
216 | ||
217 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
218 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
219 | intel_ring_emit(ring, (u32)(val >> 32)); | |
220 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
221 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
222 | intel_ring_emit(ring, (u32)(val)); | |
223 | intel_ring_advance(ring); | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | static int gen8_ppgtt_enable(struct drm_device *dev) | |
229 | { | |
230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231 | struct intel_ring_buffer *ring; | |
232 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
233 | int i, j, ret; | |
234 | ||
235 | /* bit of a hack to find the actual last used pd */ | |
236 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
237 | ||
238 | for_each_ring(ring, dev_priv, j) { | |
239 | I915_WRITE(RING_MODE_GEN7(ring), | |
240 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
241 | } | |
242 | ||
243 | for (i = used_pd - 1; i >= 0; i--) { | |
244 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
245 | for_each_ring(ring, dev_priv, j) { | |
e178f705 BW |
246 | ret = gen8_write_pdp(ring, i, addr, |
247 | i915_reset_in_progress(&dev_priv->gpu_error)); | |
94e409c1 | 248 | if (ret) |
d595bd4b | 249 | goto err_out; |
94e409c1 BW |
250 | } |
251 | } | |
252 | return 0; | |
d595bd4b BW |
253 | |
254 | err_out: | |
255 | for_each_ring(ring, dev_priv, j) | |
256 | I915_WRITE(RING_MODE_GEN7(ring), | |
257 | _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); | |
258 | return ret; | |
94e409c1 BW |
259 | } |
260 | ||
459108b8 BW |
261 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
262 | unsigned first_entry, | |
263 | unsigned num_entries, | |
264 | bool use_scratch) | |
265 | { | |
266 | struct i915_hw_ppgtt *ppgtt = | |
267 | container_of(vm, struct i915_hw_ppgtt, base); | |
268 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
269 | unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; | |
270 | unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE; | |
271 | unsigned last_pte, i; | |
272 | ||
273 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
274 | I915_CACHE_LLC, use_scratch); | |
275 | ||
276 | while (num_entries) { | |
277 | struct page *page_table = &ppgtt->gen8_pt_pages[act_pt]; | |
278 | ||
279 | last_pte = first_pte + num_entries; | |
280 | if (last_pte > GEN8_PTES_PER_PAGE) | |
281 | last_pte = GEN8_PTES_PER_PAGE; | |
282 | ||
283 | pt_vaddr = kmap_atomic(page_table); | |
284 | ||
285 | for (i = first_pte; i < last_pte; i++) | |
286 | pt_vaddr[i] = scratch_pte; | |
287 | ||
288 | kunmap_atomic(pt_vaddr); | |
289 | ||
290 | num_entries -= last_pte - first_pte; | |
291 | first_pte = 0; | |
292 | act_pt++; | |
293 | } | |
294 | } | |
295 | ||
9df15b49 BW |
296 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
297 | struct sg_table *pages, | |
298 | unsigned first_entry, | |
299 | enum i915_cache_level cache_level) | |
300 | { | |
301 | struct i915_hw_ppgtt *ppgtt = | |
302 | container_of(vm, struct i915_hw_ppgtt, base); | |
303 | gen8_gtt_pte_t *pt_vaddr; | |
304 | unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; | |
305 | unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE; | |
306 | struct sg_page_iter sg_iter; | |
307 | ||
308 | pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]); | |
309 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { | |
310 | dma_addr_t page_addr; | |
311 | ||
312 | page_addr = sg_dma_address(sg_iter.sg) + | |
313 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
314 | pt_vaddr[act_pte] = gen8_pte_encode(page_addr, cache_level, | |
315 | true); | |
316 | if (++act_pte == GEN8_PTES_PER_PAGE) { | |
317 | kunmap_atomic(pt_vaddr); | |
318 | act_pt++; | |
319 | pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]); | |
320 | act_pte = 0; | |
321 | ||
322 | } | |
323 | } | |
324 | kunmap_atomic(pt_vaddr); | |
325 | } | |
326 | ||
37aca44a BW |
327 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
328 | { | |
329 | struct i915_hw_ppgtt *ppgtt = | |
330 | container_of(vm, struct i915_hw_ppgtt, base); | |
331 | int i, j; | |
332 | ||
686e1f6f BW |
333 | drm_mm_takedown(&vm->mm); |
334 | ||
37aca44a BW |
335 | for (i = 0; i < ppgtt->num_pd_pages ; i++) { |
336 | if (ppgtt->pd_dma_addr[i]) { | |
337 | pci_unmap_page(ppgtt->base.dev->pdev, | |
338 | ppgtt->pd_dma_addr[i], | |
339 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
340 | ||
341 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
342 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
343 | if (addr) | |
344 | pci_unmap_page(ppgtt->base.dev->pdev, | |
345 | addr, | |
346 | PAGE_SIZE, | |
347 | PCI_DMA_BIDIRECTIONAL); | |
348 | ||
349 | } | |
350 | } | |
351 | kfree(ppgtt->gen8_pt_dma_addr[i]); | |
352 | } | |
353 | ||
230f955f BW |
354 | __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT)); |
355 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); | |
37aca44a BW |
356 | } |
357 | ||
358 | /** | |
359 | * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a | |
360 | * net effect resembling a 2-level page table in normal x86 terms. Each PDP | |
361 | * represents 1GB of memory | |
362 | * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space. | |
363 | * | |
364 | * TODO: Do something with the size parameter | |
365 | **/ | |
366 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) | |
367 | { | |
368 | struct page *pt_pages; | |
369 | int i, j, ret = -ENOMEM; | |
370 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); | |
371 | const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; | |
372 | ||
373 | if (size % (1<<30)) | |
374 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
375 | ||
376 | /* FIXME: split allocation into smaller pieces. For now we only ever do | |
377 | * this once, but with full PPGTT, the multiple contiguous allocations | |
378 | * will be bad. | |
379 | */ | |
380 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
381 | if (!ppgtt->pd_pages) | |
382 | return -ENOMEM; | |
383 | ||
384 | pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT)); | |
385 | if (!pt_pages) { | |
386 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
387 | return -ENOMEM; | |
388 | } | |
389 | ||
390 | ppgtt->gen8_pt_pages = pt_pages; | |
391 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
392 | ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT); | |
393 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
94e409c1 | 394 | ppgtt->enable = gen8_ppgtt_enable; |
459108b8 | 395 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
9df15b49 | 396 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
37aca44a | 397 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
686e1f6f BW |
398 | ppgtt->base.start = 0; |
399 | ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE; | |
37aca44a BW |
400 | |
401 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
402 | ||
403 | /* | |
404 | * - Create a mapping for the page directories. | |
405 | * - For each page directory: | |
406 | * allocate space for page table mappings. | |
407 | * map each page table | |
408 | */ | |
409 | for (i = 0; i < max_pdp; i++) { | |
410 | dma_addr_t temp; | |
411 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
412 | &ppgtt->pd_pages[i], 0, | |
413 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
414 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
415 | goto err_out; | |
416 | ||
417 | ppgtt->pd_dma_addr[i] = temp; | |
418 | ||
419 | ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL); | |
420 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
421 | goto err_out; | |
422 | ||
423 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
424 | struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j]; | |
425 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
426 | p, 0, PAGE_SIZE, | |
427 | PCI_DMA_BIDIRECTIONAL); | |
428 | ||
429 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
430 | goto err_out; | |
431 | ||
432 | ppgtt->gen8_pt_dma_addr[i][j] = temp; | |
433 | } | |
434 | } | |
435 | ||
b1fe6673 BW |
436 | /* For now, the PPGTT helper functions all require that the PDEs are |
437 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we | |
438 | * will never need to touch the PDEs again */ | |
439 | for (i = 0; i < max_pdp; i++) { | |
440 | gen8_ppgtt_pde_t *pd_vaddr; | |
441 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
442 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
443 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
444 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
445 | I915_CACHE_LLC); | |
446 | } | |
447 | kunmap_atomic(pd_vaddr); | |
448 | } | |
449 | ||
459108b8 BW |
450 | ppgtt->base.clear_range(&ppgtt->base, 0, |
451 | ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE, | |
452 | true); | |
453 | ||
37aca44a BW |
454 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
455 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
456 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
457 | ppgtt->num_pt_pages, | |
458 | (ppgtt->num_pt_pages - num_pt_pages) + | |
459 | size % (1<<30)); | |
28cf5415 | 460 | return 0; |
37aca44a BW |
461 | |
462 | err_out: | |
463 | ppgtt->base.cleanup(&ppgtt->base); | |
464 | return ret; | |
465 | } | |
466 | ||
3e302542 | 467 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 468 | { |
853ba5d2 | 469 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
470 | gen6_gtt_pte_t __iomem *pd_addr; |
471 | uint32_t pd_entry; | |
472 | int i; | |
473 | ||
0a732870 | 474 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
475 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
476 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
477 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
478 | dma_addr_t pt_addr; | |
479 | ||
480 | pt_addr = ppgtt->pt_dma_addr[i]; | |
481 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
482 | pd_entry |= GEN6_PDE_VALID; | |
483 | ||
484 | writel(pd_entry, pd_addr + i); | |
485 | } | |
486 | readl(pd_addr); | |
3e302542 BW |
487 | } |
488 | ||
489 | static int gen6_ppgtt_enable(struct drm_device *dev) | |
490 | { | |
491 | drm_i915_private_t *dev_priv = dev->dev_private; | |
492 | uint32_t pd_offset; | |
493 | struct intel_ring_buffer *ring; | |
494 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
495 | int i; | |
496 | ||
497 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
498 | ||
499 | gen6_write_pdes(ppgtt); | |
6197349b BW |
500 | |
501 | pd_offset = ppgtt->pd_offset; | |
502 | pd_offset /= 64; /* in cachelines, */ | |
503 | pd_offset <<= 16; | |
504 | ||
505 | if (INTEL_INFO(dev)->gen == 6) { | |
506 | uint32_t ecochk, gab_ctl, ecobits; | |
507 | ||
508 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
509 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
510 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
511 | |
512 | gab_ctl = I915_READ(GAB_CTL); | |
513 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
514 | ||
515 | ecochk = I915_READ(GAM_ECOCHK); | |
516 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
517 | ECOCHK_PPGTT_CACHE64B); | |
518 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
519 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 520 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
521 | |
522 | ecobits = I915_READ(GAC_ECO_BITS); | |
523 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
524 | ||
a6f429a5 VS |
525 | ecochk = I915_READ(GAM_ECOCHK); |
526 | if (IS_HASWELL(dev)) { | |
527 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
528 | } else { | |
529 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
530 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
531 | } | |
532 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
533 | /* GFX_MODE is per-ring on gen7+ */ |
534 | } | |
535 | ||
536 | for_each_ring(ring, dev_priv, i) { | |
537 | if (INTEL_INFO(dev)->gen >= 7) | |
538 | I915_WRITE(RING_MODE_GEN7(ring), | |
539 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
540 | ||
541 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
542 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
543 | } | |
b7c36d25 | 544 | return 0; |
6197349b BW |
545 | } |
546 | ||
1d2a314c | 547 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 548 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
1d2a314c | 549 | unsigned first_entry, |
828c7908 BW |
550 | unsigned num_entries, |
551 | bool use_scratch) | |
1d2a314c | 552 | { |
853ba5d2 BW |
553 | struct i915_hw_ppgtt *ppgtt = |
554 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 555 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 556 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
557 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
558 | unsigned last_pte, i; | |
1d2a314c | 559 | |
b35b380e | 560 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 561 | |
7bddb01f DV |
562 | while (num_entries) { |
563 | last_pte = first_pte + num_entries; | |
564 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
565 | last_pte = I915_PPGTT_PT_ENTRIES; | |
566 | ||
a15326a5 | 567 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 568 | |
7bddb01f DV |
569 | for (i = first_pte; i < last_pte; i++) |
570 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
571 | |
572 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 573 | |
7bddb01f DV |
574 | num_entries -= last_pte - first_pte; |
575 | first_pte = 0; | |
a15326a5 | 576 | act_pt++; |
7bddb01f | 577 | } |
1d2a314c DV |
578 | } |
579 | ||
853ba5d2 | 580 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 DV |
581 | struct sg_table *pages, |
582 | unsigned first_entry, | |
583 | enum i915_cache_level cache_level) | |
584 | { | |
853ba5d2 BW |
585 | struct i915_hw_ppgtt *ppgtt = |
586 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 587 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 588 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
589 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
590 | struct sg_page_iter sg_iter; | |
591 | ||
a15326a5 | 592 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
593 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
594 | dma_addr_t page_addr; | |
595 | ||
2db76d7c | 596 | page_addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 597 | pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true); |
6e995e23 ID |
598 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
599 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
600 | act_pt++; |
601 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 602 | act_pte = 0; |
def886c3 | 603 | |
def886c3 | 604 | } |
def886c3 | 605 | } |
6e995e23 | 606 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
607 | } |
608 | ||
853ba5d2 | 609 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 610 | { |
853ba5d2 BW |
611 | struct i915_hw_ppgtt *ppgtt = |
612 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
613 | int i; |
614 | ||
93bd8649 BW |
615 | drm_mm_takedown(&ppgtt->base.mm); |
616 | ||
3440d265 DV |
617 | if (ppgtt->pt_dma_addr) { |
618 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 619 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
620 | ppgtt->pt_dma_addr[i], |
621 | 4096, PCI_DMA_BIDIRECTIONAL); | |
622 | } | |
623 | ||
624 | kfree(ppgtt->pt_dma_addr); | |
625 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
626 | __free_page(ppgtt->pt_pages[i]); | |
627 | kfree(ppgtt->pt_pages); | |
628 | kfree(ppgtt); | |
629 | } | |
630 | ||
631 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
632 | { | |
853ba5d2 | 633 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 634 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 635 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
636 | int i; |
637 | int ret = -ENOMEM; | |
638 | ||
639 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
640 | * entries. For aliasing ppgtt support we just steal them at the end for | |
641 | * now. */ | |
e1b73cba | 642 | first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); |
1d2a314c | 643 | |
08c45263 | 644 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
6670a5a5 | 645 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
6197349b | 646 | ppgtt->enable = gen6_ppgtt_enable; |
853ba5d2 BW |
647 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
648 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
649 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
650 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
686e1f6f BW |
651 | ppgtt->base.start = 0; |
652 | ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; | |
a1e22653 | 653 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c DV |
654 | GFP_KERNEL); |
655 | if (!ppgtt->pt_pages) | |
3440d265 | 656 | return -ENOMEM; |
1d2a314c DV |
657 | |
658 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
659 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
660 | if (!ppgtt->pt_pages[i]) | |
661 | goto err_pt_alloc; | |
662 | } | |
663 | ||
a1e22653 | 664 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 BW |
665 | GFP_KERNEL); |
666 | if (!ppgtt->pt_dma_addr) | |
667 | goto err_pt_alloc; | |
1d2a314c | 668 | |
8d2e6308 BW |
669 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
670 | dma_addr_t pt_addr; | |
211c568b | 671 | |
8d2e6308 BW |
672 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
673 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 674 | |
8d2e6308 BW |
675 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
676 | ret = -EIO; | |
677 | goto err_pd_pin; | |
1d2a314c | 678 | |
211c568b | 679 | } |
8d2e6308 | 680 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 681 | } |
1d2a314c | 682 | |
853ba5d2 | 683 | ppgtt->base.clear_range(&ppgtt->base, 0, |
828c7908 | 684 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); |
1d2a314c | 685 | |
e7c2b58b | 686 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 687 | |
1d2a314c DV |
688 | return 0; |
689 | ||
690 | err_pd_pin: | |
691 | if (ppgtt->pt_dma_addr) { | |
692 | for (i--; i >= 0; i--) | |
693 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
694 | 4096, PCI_DMA_BIDIRECTIONAL); | |
695 | } | |
696 | err_pt_alloc: | |
697 | kfree(ppgtt->pt_dma_addr); | |
698 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
699 | if (ppgtt->pt_pages[i]) | |
700 | __free_page(ppgtt->pt_pages[i]); | |
701 | } | |
702 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
703 | |
704 | return ret; | |
705 | } | |
706 | ||
707 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
708 | { | |
709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
710 | struct i915_hw_ppgtt *ppgtt; | |
711 | int ret; | |
712 | ||
713 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
714 | if (!ppgtt) | |
715 | return -ENOMEM; | |
716 | ||
853ba5d2 | 717 | ppgtt->base.dev = dev; |
3440d265 | 718 | |
3ed124b2 BW |
719 | if (INTEL_INFO(dev)->gen < 8) |
720 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 721 | else if (IS_GEN8(dev)) |
37aca44a | 722 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
723 | else |
724 | BUG(); | |
725 | ||
3440d265 DV |
726 | if (ret) |
727 | kfree(ppgtt); | |
93bd8649 | 728 | else { |
3440d265 | 729 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
93bd8649 BW |
730 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
731 | ppgtt->base.total); | |
732 | } | |
1d2a314c DV |
733 | |
734 | return ret; | |
735 | } | |
736 | ||
737 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
738 | { | |
739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
740 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
741 | |
742 | if (!ppgtt) | |
743 | return; | |
744 | ||
853ba5d2 | 745 | ppgtt->base.cleanup(&ppgtt->base); |
5963cf04 | 746 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
747 | } |
748 | ||
7bddb01f DV |
749 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
750 | struct drm_i915_gem_object *obj, | |
751 | enum i915_cache_level cache_level) | |
752 | { | |
853ba5d2 BW |
753 | ppgtt->base.insert_entries(&ppgtt->base, obj->pages, |
754 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
755 | cache_level); | |
7bddb01f DV |
756 | } |
757 | ||
758 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
759 | struct drm_i915_gem_object *obj) | |
760 | { | |
853ba5d2 BW |
761 | ppgtt->base.clear_range(&ppgtt->base, |
762 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
828c7908 BW |
763 | obj->base.size >> PAGE_SHIFT, |
764 | true); | |
7bddb01f DV |
765 | } |
766 | ||
a81cc00c BW |
767 | extern int intel_iommu_gfx_mapped; |
768 | /* Certain Gen5 chipsets require require idling the GPU before | |
769 | * unmapping anything from the GTT when VT-d is enabled. | |
770 | */ | |
771 | static inline bool needs_idle_maps(struct drm_device *dev) | |
772 | { | |
773 | #ifdef CONFIG_INTEL_IOMMU | |
774 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
775 | * was loaded first. | |
776 | */ | |
777 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
778 | return true; | |
779 | #endif | |
780 | return false; | |
781 | } | |
782 | ||
5c042287 BW |
783 | static bool do_idling(struct drm_i915_private *dev_priv) |
784 | { | |
785 | bool ret = dev_priv->mm.interruptible; | |
786 | ||
a81cc00c | 787 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 788 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 789 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
790 | DRM_ERROR("Couldn't idle GPU\n"); |
791 | /* Wait a bit, in hopes it avoids the hang */ | |
792 | udelay(10); | |
793 | } | |
794 | } | |
795 | ||
796 | return ret; | |
797 | } | |
798 | ||
799 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
800 | { | |
a81cc00c | 801 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
802 | dev_priv->mm.interruptible = interruptible; |
803 | } | |
804 | ||
828c7908 BW |
805 | void i915_check_and_clear_faults(struct drm_device *dev) |
806 | { | |
807 | struct drm_i915_private *dev_priv = dev->dev_private; | |
808 | struct intel_ring_buffer *ring; | |
809 | int i; | |
810 | ||
811 | if (INTEL_INFO(dev)->gen < 6) | |
812 | return; | |
813 | ||
814 | for_each_ring(ring, dev_priv, i) { | |
815 | u32 fault_reg; | |
816 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
817 | if (fault_reg & RING_FAULT_VALID) { | |
818 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
819 | "\tAddr: 0x%08lx\\n" | |
820 | "\tAddress space: %s\n" | |
821 | "\tSource ID: %d\n" | |
822 | "\tType: %d\n", | |
823 | fault_reg & PAGE_MASK, | |
824 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
825 | RING_FAULT_SRCID(fault_reg), | |
826 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
827 | I915_WRITE(RING_FAULT_REG(ring), | |
828 | fault_reg & ~RING_FAULT_VALID); | |
829 | } | |
830 | } | |
831 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
832 | } | |
833 | ||
834 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
835 | { | |
836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
837 | ||
838 | /* Don't bother messing with faults pre GEN6 as we have little | |
839 | * documentation supporting that it's a good idea. | |
840 | */ | |
841 | if (INTEL_INFO(dev)->gen < 6) | |
842 | return; | |
843 | ||
844 | i915_check_and_clear_faults(dev); | |
845 | ||
846 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
847 | dev_priv->gtt.base.start / PAGE_SIZE, | |
848 | dev_priv->gtt.base.total / PAGE_SIZE, | |
849 | false); | |
850 | } | |
851 | ||
76aaf220 DV |
852 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
853 | { | |
854 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 855 | struct drm_i915_gem_object *obj; |
76aaf220 | 856 | |
828c7908 BW |
857 | i915_check_and_clear_faults(dev); |
858 | ||
bee4a186 | 859 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 BW |
860 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
861 | dev_priv->gtt.base.start / PAGE_SIZE, | |
828c7908 BW |
862 | dev_priv->gtt.base.total / PAGE_SIZE, |
863 | true); | |
bee4a186 | 864 | |
35c20a60 | 865 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2c22569b | 866 | i915_gem_clflush_object(obj, obj->pin_display); |
74163907 | 867 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
868 | } |
869 | ||
e76e9aeb | 870 | i915_gem_chipset_flush(dev); |
76aaf220 | 871 | } |
7c2e6fdf | 872 | |
74163907 | 873 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 874 | { |
9da3da66 | 875 | if (obj->has_dma_mapping) |
74163907 | 876 | return 0; |
9da3da66 CW |
877 | |
878 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
879 | obj->pages->sgl, obj->pages->nents, | |
880 | PCI_DMA_BIDIRECTIONAL)) | |
881 | return -ENOSPC; | |
882 | ||
883 | return 0; | |
7c2e6fdf DV |
884 | } |
885 | ||
94ec8f61 BW |
886 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
887 | { | |
888 | #ifdef writeq | |
889 | writeq(pte, addr); | |
890 | #else | |
891 | iowrite32((u32)pte, addr); | |
892 | iowrite32(pte >> 32, addr + 4); | |
893 | #endif | |
894 | } | |
895 | ||
896 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
897 | struct sg_table *st, | |
898 | unsigned int first_entry, | |
899 | enum i915_cache_level level) | |
900 | { | |
901 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
902 | gen8_gtt_pte_t __iomem *gtt_entries = | |
903 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
904 | int i = 0; | |
905 | struct sg_page_iter sg_iter; | |
906 | dma_addr_t addr; | |
907 | ||
908 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
909 | addr = sg_dma_address(sg_iter.sg) + | |
910 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
911 | gen8_set_pte(>t_entries[i], | |
912 | gen8_pte_encode(addr, level, true)); | |
913 | i++; | |
914 | } | |
915 | ||
916 | /* | |
917 | * XXX: This serves as a posting read to make sure that the PTE has | |
918 | * actually been updated. There is some concern that even though | |
919 | * registers and PTEs are within the same BAR that they are potentially | |
920 | * of NUMA access patterns. Therefore, even with the way we assume | |
921 | * hardware should work, we must keep this posting read for paranoia. | |
922 | */ | |
923 | if (i != 0) | |
924 | WARN_ON(readq(>t_entries[i-1]) | |
925 | != gen8_pte_encode(addr, level, true)); | |
926 | ||
927 | #if 0 /* TODO: Still needed on GEN8? */ | |
928 | /* This next bit makes the above posting read even more important. We | |
929 | * want to flush the TLBs only after we're certain all the PTE updates | |
930 | * have finished. | |
931 | */ | |
932 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
933 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
934 | #endif | |
935 | } | |
936 | ||
e76e9aeb BW |
937 | /* |
938 | * Binds an object into the global gtt with the specified cache level. The object | |
939 | * will be accessible to the GPU via commands whose operands reference offsets | |
940 | * within the global GTT as well as accessible by the GPU through the GMADR | |
941 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
942 | */ | |
853ba5d2 | 943 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
944 | struct sg_table *st, |
945 | unsigned int first_entry, | |
946 | enum i915_cache_level level) | |
e76e9aeb | 947 | { |
853ba5d2 | 948 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
949 | gen6_gtt_pte_t __iomem *gtt_entries = |
950 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
951 | int i = 0; |
952 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
953 | dma_addr_t addr; |
954 | ||
6e995e23 | 955 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 956 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 957 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 958 | i++; |
e76e9aeb BW |
959 | } |
960 | ||
e76e9aeb BW |
961 | /* XXX: This serves as a posting read to make sure that the PTE has |
962 | * actually been updated. There is some concern that even though | |
963 | * registers and PTEs are within the same BAR that they are potentially | |
964 | * of NUMA access patterns. Therefore, even with the way we assume | |
965 | * hardware should work, we must keep this posting read for paranoia. | |
966 | */ | |
967 | if (i != 0) | |
853ba5d2 | 968 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 969 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
970 | |
971 | /* This next bit makes the above posting read even more important. We | |
972 | * want to flush the TLBs only after we're certain all the PTE updates | |
973 | * have finished. | |
974 | */ | |
975 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
976 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
977 | } |
978 | ||
94ec8f61 BW |
979 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
980 | unsigned int first_entry, | |
981 | unsigned int num_entries, | |
982 | bool use_scratch) | |
983 | { | |
984 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
985 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = | |
986 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
987 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
988 | int i; | |
989 | ||
990 | if (WARN(num_entries > max_entries, | |
991 | "First entry = %d; Num entries = %d (max=%d)\n", | |
992 | first_entry, num_entries, max_entries)) | |
993 | num_entries = max_entries; | |
994 | ||
995 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
996 | I915_CACHE_LLC, | |
997 | use_scratch); | |
998 | for (i = 0; i < num_entries; i++) | |
999 | gen8_set_pte(>t_base[i], scratch_pte); | |
1000 | readl(gtt_base); | |
1001 | } | |
1002 | ||
853ba5d2 | 1003 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 1004 | unsigned int first_entry, |
828c7908 BW |
1005 | unsigned int num_entries, |
1006 | bool use_scratch) | |
7faf1ab2 | 1007 | { |
853ba5d2 | 1008 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
1009 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1010 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1011 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1012 | int i; |
1013 | ||
1014 | if (WARN(num_entries > max_entries, | |
1015 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1016 | first_entry, num_entries, max_entries)) | |
1017 | num_entries = max_entries; | |
1018 | ||
828c7908 BW |
1019 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
1020 | ||
7faf1ab2 DV |
1021 | for (i = 0; i < num_entries; i++) |
1022 | iowrite32(scratch_pte, >t_base[i]); | |
1023 | readl(gtt_base); | |
1024 | } | |
1025 | ||
853ba5d2 | 1026 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
1027 | struct sg_table *st, |
1028 | unsigned int pg_start, | |
1029 | enum i915_cache_level cache_level) | |
1030 | { | |
1031 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
1032 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1033 | ||
1034 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
1035 | ||
1036 | } | |
1037 | ||
853ba5d2 | 1038 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 1039 | unsigned int first_entry, |
828c7908 BW |
1040 | unsigned int num_entries, |
1041 | bool unused) | |
7faf1ab2 DV |
1042 | { |
1043 | intel_gtt_clear_range(first_entry, num_entries); | |
1044 | } | |
1045 | ||
1046 | ||
74163907 DV |
1047 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
1048 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
1049 | { |
1050 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 | 1051 | struct drm_i915_private *dev_priv = dev->dev_private; |
853ba5d2 | 1052 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 1053 | |
853ba5d2 BW |
1054 | dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages, |
1055 | entry, | |
1056 | cache_level); | |
d5bd1449 | 1057 | |
74898d7e | 1058 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
1059 | } |
1060 | ||
05394f39 | 1061 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 1062 | { |
7faf1ab2 DV |
1063 | struct drm_device *dev = obj->base.dev; |
1064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 | 1065 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 1066 | |
853ba5d2 BW |
1067 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
1068 | entry, | |
828c7908 BW |
1069 | obj->base.size >> PAGE_SHIFT, |
1070 | true); | |
74898d7e DV |
1071 | |
1072 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
1073 | } |
1074 | ||
1075 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1076 | { |
5c042287 BW |
1077 | struct drm_device *dev = obj->base.dev; |
1078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1079 | bool interruptible; | |
1080 | ||
1081 | interruptible = do_idling(dev_priv); | |
1082 | ||
9da3da66 CW |
1083 | if (!obj->has_dma_mapping) |
1084 | dma_unmap_sg(&dev->pdev->dev, | |
1085 | obj->pages->sgl, obj->pages->nents, | |
1086 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1087 | |
1088 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1089 | } |
644ec02b | 1090 | |
42d6ab48 CW |
1091 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1092 | unsigned long color, | |
1093 | unsigned long *start, | |
1094 | unsigned long *end) | |
1095 | { | |
1096 | if (node->color != color) | |
1097 | *start += 4096; | |
1098 | ||
1099 | if (!list_empty(&node->node_list)) { | |
1100 | node = list_entry(node->node_list.next, | |
1101 | struct drm_mm_node, | |
1102 | node_list); | |
1103 | if (node->allocated && node->color != color) | |
1104 | *end -= 4096; | |
1105 | } | |
1106 | } | |
fbe5d36e | 1107 | |
d7e5008f BW |
1108 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
1109 | unsigned long start, | |
1110 | unsigned long mappable_end, | |
1111 | unsigned long end) | |
644ec02b | 1112 | { |
e78891ca BW |
1113 | /* Let GEM Manage all of the aperture. |
1114 | * | |
1115 | * However, leave one page at the end still bound to the scratch page. | |
1116 | * There are a number of places where the hardware apparently prefetches | |
1117 | * past the end of the object, and we've seen multiple hangs with the | |
1118 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1119 | * aperture. One page should be enough to keep any prefetching inside | |
1120 | * of the aperture. | |
1121 | */ | |
40d74980 BW |
1122 | struct drm_i915_private *dev_priv = dev->dev_private; |
1123 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1124 | struct drm_mm_node *entry; |
1125 | struct drm_i915_gem_object *obj; | |
1126 | unsigned long hole_start, hole_end; | |
644ec02b | 1127 | |
35451cb6 BW |
1128 | BUG_ON(mappable_end > end); |
1129 | ||
ed2f3452 | 1130 | /* Subtract the guard page ... */ |
40d74980 | 1131 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1132 | if (!HAS_LLC(dev)) |
93bd8649 | 1133 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1134 | |
ed2f3452 | 1135 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1136 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1137 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 1138 | int ret; |
edd41a87 | 1139 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1140 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1141 | ||
1142 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1143 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 1144 | if (ret) |
b3a070cc | 1145 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 CW |
1146 | obj->has_global_gtt_mapping = 1; |
1147 | } | |
1148 | ||
853ba5d2 BW |
1149 | dev_priv->gtt.base.start = start; |
1150 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1151 | |
ed2f3452 | 1152 | /* Clear any non-preallocated blocks */ |
40d74980 | 1153 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
853ba5d2 | 1154 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
ed2f3452 CW |
1155 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1156 | hole_start, hole_end); | |
828c7908 | 1157 | ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); |
ed2f3452 CW |
1158 | } |
1159 | ||
1160 | /* And finally clear the reserved guard page */ | |
828c7908 | 1161 | ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); |
e76e9aeb BW |
1162 | } |
1163 | ||
d7e5008f BW |
1164 | static bool |
1165 | intel_enable_ppgtt(struct drm_device *dev) | |
1166 | { | |
1167 | if (i915_enable_ppgtt >= 0) | |
1168 | return i915_enable_ppgtt; | |
1169 | ||
1170 | #ifdef CONFIG_INTEL_IOMMU | |
1171 | /* Disable ppgtt on SNB if VT-d is on. */ | |
1172 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
1173 | return false; | |
1174 | #endif | |
1175 | ||
1176 | return true; | |
1177 | } | |
1178 | ||
1179 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
1180 | { | |
1181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1182 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1183 | |
853ba5d2 | 1184 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1185 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
1186 | |
1187 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 1188 | int ret; |
3eb1c005 BW |
1189 | |
1190 | if (INTEL_INFO(dev)->gen <= 7) { | |
1191 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
1192 | * aperture accordingly when using aliasing ppgtt. */ | |
6670a5a5 | 1193 | gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
3eb1c005 | 1194 | } |
d7e5008f BW |
1195 | |
1196 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
1197 | ||
1198 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 1199 | if (!ret) |
d7e5008f | 1200 | return; |
e78891ca BW |
1201 | |
1202 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
93bd8649 | 1203 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
b42218c1 VS |
1204 | if (INTEL_INFO(dev)->gen < 8) |
1205 | gtt_size += GEN6_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
d7e5008f | 1206 | } |
e78891ca | 1207 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1208 | } |
1209 | ||
1210 | static int setup_scratch_page(struct drm_device *dev) | |
1211 | { | |
1212 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1213 | struct page *page; | |
1214 | dma_addr_t dma_addr; | |
1215 | ||
1216 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1217 | if (page == NULL) | |
1218 | return -ENOMEM; | |
1219 | get_page(page); | |
1220 | set_pages_uc(page, 1); | |
1221 | ||
1222 | #ifdef CONFIG_INTEL_IOMMU | |
1223 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1224 | PCI_DMA_BIDIRECTIONAL); | |
1225 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1226 | return -EINVAL; | |
1227 | #else | |
1228 | dma_addr = page_to_phys(page); | |
1229 | #endif | |
853ba5d2 BW |
1230 | dev_priv->gtt.base.scratch.page = page; |
1231 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1232 | |
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | static void teardown_scratch_page(struct drm_device *dev) | |
1237 | { | |
1238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1239 | struct page *page = dev_priv->gtt.base.scratch.page; |
1240 | ||
1241 | set_pages_wb(page, 1); | |
1242 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1243 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1244 | put_page(page); |
1245 | __free_page(page); | |
e76e9aeb BW |
1246 | } |
1247 | ||
1248 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1249 | { | |
1250 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1251 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1252 | return snb_gmch_ctl << 20; | |
1253 | } | |
1254 | ||
9459d252 BW |
1255 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1256 | { | |
1257 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1258 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1259 | if (bdw_gmch_ctl) | |
1260 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
3a2ffb65 BW |
1261 | if (bdw_gmch_ctl > 4) { |
1262 | WARN_ON(!i915_preliminary_hw_support); | |
1263 | return 4<<20; | |
1264 | } | |
1265 | ||
9459d252 BW |
1266 | return bdw_gmch_ctl << 20; |
1267 | } | |
1268 | ||
baa09f5f | 1269 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1270 | { |
1271 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1272 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1273 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1274 | } | |
1275 | ||
9459d252 BW |
1276 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1277 | { | |
1278 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1279 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1280 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1281 | } | |
1282 | ||
63340133 BW |
1283 | static int ggtt_probe_common(struct drm_device *dev, |
1284 | size_t gtt_size) | |
1285 | { | |
1286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1287 | phys_addr_t gtt_bus_addr; | |
1288 | int ret; | |
1289 | ||
1290 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
1291 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
1292 | (pci_resource_len(dev->pdev, 0) / 2); | |
1293 | ||
1294 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); | |
1295 | if (!dev_priv->gtt.gsm) { | |
1296 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1297 | return -ENOMEM; | |
1298 | } | |
1299 | ||
1300 | ret = setup_scratch_page(dev); | |
1301 | if (ret) { | |
1302 | DRM_ERROR("Scratch setup failed\n"); | |
1303 | /* iounmap will also get called at remove, but meh */ | |
1304 | iounmap(dev_priv->gtt.gsm); | |
1305 | } | |
1306 | ||
1307 | return ret; | |
1308 | } | |
1309 | ||
fbe5d36e BW |
1310 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1311 | * bits. When using advanced contexts each context stores its own PAT, but | |
1312 | * writing this data shouldn't be harmful even in those cases. */ | |
1313 | static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) | |
1314 | { | |
1315 | #define GEN8_PPAT_UC (0<<0) | |
1316 | #define GEN8_PPAT_WC (1<<0) | |
1317 | #define GEN8_PPAT_WT (2<<0) | |
1318 | #define GEN8_PPAT_WB (3<<0) | |
1319 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
1320 | /* FIXME(BDW): Bspec is completely confused about cache control bits. */ | |
1321 | #define GEN8_PPAT_LLC (1<<2) | |
1322 | #define GEN8_PPAT_LLCELLC (2<<2) | |
1323 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
1324 | #define GEN8_PPAT_AGE(x) (x<<4) | |
1325 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
1326 | uint64_t pat; | |
1327 | ||
1328 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1329 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1330 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1331 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1332 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1333 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1334 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1335 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1336 | ||
1337 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1338 | * write would work. */ | |
1339 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1340 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1341 | } | |
1342 | ||
63340133 BW |
1343 | static int gen8_gmch_probe(struct drm_device *dev, |
1344 | size_t *gtt_total, | |
1345 | size_t *stolen, | |
1346 | phys_addr_t *mappable_base, | |
1347 | unsigned long *mappable_end) | |
1348 | { | |
1349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1350 | unsigned int gtt_size; | |
1351 | u16 snb_gmch_ctl; | |
1352 | int ret; | |
1353 | ||
1354 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1355 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1356 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1357 | ||
1358 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1359 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1360 | ||
1361 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1362 | ||
1363 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1364 | ||
1365 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 1366 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1367 | |
fbe5d36e BW |
1368 | gen8_setup_private_ppat(dev_priv); |
1369 | ||
63340133 BW |
1370 | ret = ggtt_probe_common(dev, gtt_size); |
1371 | ||
94ec8f61 BW |
1372 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1373 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1374 | |
1375 | return ret; | |
1376 | } | |
1377 | ||
baa09f5f BW |
1378 | static int gen6_gmch_probe(struct drm_device *dev, |
1379 | size_t *gtt_total, | |
41907ddc BW |
1380 | size_t *stolen, |
1381 | phys_addr_t *mappable_base, | |
1382 | unsigned long *mappable_end) | |
e76e9aeb BW |
1383 | { |
1384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1385 | unsigned int gtt_size; |
e76e9aeb | 1386 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1387 | int ret; |
1388 | ||
41907ddc BW |
1389 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1390 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1391 | ||
baa09f5f BW |
1392 | /* 64/512MB is the current min/max we actually know of, but this is just |
1393 | * a coarse sanity check. | |
e76e9aeb | 1394 | */ |
41907ddc | 1395 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1396 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1397 | dev_priv->gtt.mappable_end); | |
1398 | return -ENXIO; | |
e76e9aeb BW |
1399 | } |
1400 | ||
e76e9aeb BW |
1401 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1402 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1403 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1404 | |
c4ae25ec | 1405 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 1406 | |
63340133 BW |
1407 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1408 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 1409 | |
63340133 | 1410 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1411 | |
853ba5d2 BW |
1412 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1413 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1414 | |
e76e9aeb BW |
1415 | return ret; |
1416 | } | |
1417 | ||
853ba5d2 | 1418 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1419 | { |
853ba5d2 BW |
1420 | |
1421 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 BW |
1422 | |
1423 | drm_mm_takedown(&vm->mm); | |
853ba5d2 BW |
1424 | iounmap(gtt->gsm); |
1425 | teardown_scratch_page(vm->dev); | |
644ec02b | 1426 | } |
baa09f5f BW |
1427 | |
1428 | static int i915_gmch_probe(struct drm_device *dev, | |
1429 | size_t *gtt_total, | |
41907ddc BW |
1430 | size_t *stolen, |
1431 | phys_addr_t *mappable_base, | |
1432 | unsigned long *mappable_end) | |
baa09f5f BW |
1433 | { |
1434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1435 | int ret; | |
1436 | ||
baa09f5f BW |
1437 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1438 | if (!ret) { | |
1439 | DRM_ERROR("failed to set up gmch\n"); | |
1440 | return -EIO; | |
1441 | } | |
1442 | ||
41907ddc | 1443 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1444 | |
1445 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 BW |
1446 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
1447 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; | |
baa09f5f BW |
1448 | |
1449 | return 0; | |
1450 | } | |
1451 | ||
853ba5d2 | 1452 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1453 | { |
1454 | intel_gmch_remove(); | |
1455 | } | |
1456 | ||
1457 | int i915_gem_gtt_init(struct drm_device *dev) | |
1458 | { | |
1459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1460 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1461 | int ret; |
1462 | ||
baa09f5f | 1463 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 1464 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 1465 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 1466 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 1467 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 1468 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 1469 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 1470 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 1471 | else if (IS_HASWELL(dev)) |
853ba5d2 | 1472 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 1473 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 1474 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
1475 | else if (INTEL_INFO(dev)->gen >= 7) |
1476 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 1477 | else |
350ec881 | 1478 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
1479 | } else { |
1480 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
1481 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
1482 | } |
1483 | ||
853ba5d2 | 1484 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 1485 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 1486 | if (ret) |
baa09f5f | 1487 | return ret; |
baa09f5f | 1488 | |
853ba5d2 BW |
1489 | gtt->base.dev = dev; |
1490 | ||
baa09f5f | 1491 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
1492 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
1493 | gtt->base.total >> 20); | |
b2f21b4d BW |
1494 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
1495 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
1496 | |
1497 | return 0; | |
1498 | } |