Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
d31eb10e | 33 | typedef uint64_t gen8_gtt_pte_t; |
37aca44a | 34 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; |
6670a5a5 | 35 | |
26b1ff35 BW |
36 | /* PPGTT stuff */ |
37 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 38 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
39 | |
40 | #define GEN6_PDE_VALID (1 << 0) | |
41 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
42 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
43 | ||
44 | #define GEN6_PTE_VALID (1 << 0) | |
45 | #define GEN6_PTE_UNCACHED (1 << 1) | |
46 | #define HSW_PTE_UNCACHED (0) | |
47 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 48 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 49 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
50 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
51 | ||
52 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
53 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
54 | */ | |
55 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
56 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 57 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 58 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 59 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
651d794f | 60 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
26b1ff35 | 61 | |
37aca44a BW |
62 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
63 | #define GEN8_LEGACY_PDPS 4 | |
64 | ||
fbe5d36e BW |
65 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
66 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
67 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
68 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
69 | ||
94ec8f61 BW |
70 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
71 | enum i915_cache_level level, | |
72 | bool valid) | |
73 | { | |
74 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
75 | pte |= addr; | |
fbe5d36e BW |
76 | if (level != I915_CACHE_NONE) |
77 | pte |= PPAT_CACHED_INDEX; | |
78 | else | |
79 | pte |= PPAT_UNCACHED_INDEX; | |
94ec8f61 BW |
80 | return pte; |
81 | } | |
82 | ||
b1fe6673 BW |
83 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
84 | dma_addr_t addr, | |
85 | enum i915_cache_level level) | |
86 | { | |
87 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
88 | pde |= addr; | |
89 | if (level != I915_CACHE_NONE) | |
90 | pde |= PPAT_CACHED_PDE_INDEX; | |
91 | else | |
92 | pde |= PPAT_UNCACHED_INDEX; | |
93 | return pde; | |
94 | } | |
95 | ||
350ec881 | 96 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
97 | enum i915_cache_level level, |
98 | bool valid) | |
54d12527 | 99 | { |
b35b380e | 100 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 101 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
102 | |
103 | switch (level) { | |
350ec881 CW |
104 | case I915_CACHE_L3_LLC: |
105 | case I915_CACHE_LLC: | |
106 | pte |= GEN6_PTE_CACHE_LLC; | |
107 | break; | |
108 | case I915_CACHE_NONE: | |
109 | pte |= GEN6_PTE_UNCACHED; | |
110 | break; | |
111 | default: | |
112 | WARN_ON(1); | |
113 | } | |
114 | ||
115 | return pte; | |
116 | } | |
117 | ||
118 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
119 | enum i915_cache_level level, |
120 | bool valid) | |
350ec881 | 121 | { |
b35b380e | 122 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
123 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
124 | ||
125 | switch (level) { | |
126 | case I915_CACHE_L3_LLC: | |
127 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
128 | break; |
129 | case I915_CACHE_LLC: | |
130 | pte |= GEN6_PTE_CACHE_LLC; | |
131 | break; | |
132 | case I915_CACHE_NONE: | |
9119708c | 133 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
134 | break; |
135 | default: | |
350ec881 | 136 | WARN_ON(1); |
e7210c3c BW |
137 | } |
138 | ||
54d12527 BW |
139 | return pte; |
140 | } | |
141 | ||
93c34e70 KG |
142 | #define BYT_PTE_WRITEABLE (1 << 1) |
143 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
144 | ||
80a74f7f | 145 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
146 | enum i915_cache_level level, |
147 | bool valid) | |
93c34e70 | 148 | { |
b35b380e | 149 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
150 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
151 | ||
152 | /* Mark the page as writeable. Other platforms don't have a | |
153 | * setting for read-only/writable, so this matches that behavior. | |
154 | */ | |
155 | pte |= BYT_PTE_WRITEABLE; | |
156 | ||
157 | if (level != I915_CACHE_NONE) | |
158 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
159 | ||
160 | return pte; | |
161 | } | |
162 | ||
80a74f7f | 163 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
164 | enum i915_cache_level level, |
165 | bool valid) | |
9119708c | 166 | { |
b35b380e | 167 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 168 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
169 | |
170 | if (level != I915_CACHE_NONE) | |
87a6b688 | 171 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
172 | |
173 | return pte; | |
174 | } | |
175 | ||
4d15c145 | 176 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
177 | enum i915_cache_level level, |
178 | bool valid) | |
4d15c145 | 179 | { |
b35b380e | 180 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
181 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
182 | ||
651d794f CW |
183 | switch (level) { |
184 | case I915_CACHE_NONE: | |
185 | break; | |
186 | case I915_CACHE_WT: | |
187 | pte |= HSW_WT_ELLC_LLC_AGE0; | |
188 | break; | |
189 | default: | |
4d15c145 | 190 | pte |= HSW_WB_ELLC_LLC_AGE0; |
651d794f CW |
191 | break; |
192 | } | |
4d15c145 BW |
193 | |
194 | return pte; | |
195 | } | |
196 | ||
37aca44a BW |
197 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
198 | { | |
199 | struct i915_hw_ppgtt *ppgtt = | |
200 | container_of(vm, struct i915_hw_ppgtt, base); | |
201 | int i, j; | |
202 | ||
203 | for (i = 0; i < ppgtt->num_pd_pages ; i++) { | |
204 | if (ppgtt->pd_dma_addr[i]) { | |
205 | pci_unmap_page(ppgtt->base.dev->pdev, | |
206 | ppgtt->pd_dma_addr[i], | |
207 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
208 | ||
209 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
210 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
211 | if (addr) | |
212 | pci_unmap_page(ppgtt->base.dev->pdev, | |
213 | addr, | |
214 | PAGE_SIZE, | |
215 | PCI_DMA_BIDIRECTIONAL); | |
216 | ||
217 | } | |
218 | } | |
219 | kfree(ppgtt->gen8_pt_dma_addr[i]); | |
220 | } | |
221 | ||
222 | __free_pages(ppgtt->gen8_pt_pages, ppgtt->num_pt_pages << PAGE_SHIFT); | |
223 | __free_pages(ppgtt->pd_pages, ppgtt->num_pd_pages << PAGE_SHIFT); | |
224 | } | |
225 | ||
226 | /** | |
227 | * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a | |
228 | * net effect resembling a 2-level page table in normal x86 terms. Each PDP | |
229 | * represents 1GB of memory | |
230 | * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space. | |
231 | * | |
232 | * TODO: Do something with the size parameter | |
233 | **/ | |
234 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) | |
235 | { | |
236 | struct page *pt_pages; | |
237 | int i, j, ret = -ENOMEM; | |
238 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); | |
239 | const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; | |
240 | ||
241 | if (size % (1<<30)) | |
242 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
243 | ||
244 | /* FIXME: split allocation into smaller pieces. For now we only ever do | |
245 | * this once, but with full PPGTT, the multiple contiguous allocations | |
246 | * will be bad. | |
247 | */ | |
248 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
249 | if (!ppgtt->pd_pages) | |
250 | return -ENOMEM; | |
251 | ||
252 | pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT)); | |
253 | if (!pt_pages) { | |
254 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
255 | return -ENOMEM; | |
256 | } | |
257 | ||
258 | ppgtt->gen8_pt_pages = pt_pages; | |
259 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
260 | ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT); | |
261 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
262 | ppgtt->base.clear_range = NULL; | |
263 | ppgtt->base.insert_entries = NULL; | |
264 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
265 | ||
266 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
267 | ||
268 | /* | |
269 | * - Create a mapping for the page directories. | |
270 | * - For each page directory: | |
271 | * allocate space for page table mappings. | |
272 | * map each page table | |
273 | */ | |
274 | for (i = 0; i < max_pdp; i++) { | |
275 | dma_addr_t temp; | |
276 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
277 | &ppgtt->pd_pages[i], 0, | |
278 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
279 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
280 | goto err_out; | |
281 | ||
282 | ppgtt->pd_dma_addr[i] = temp; | |
283 | ||
284 | ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL); | |
285 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
286 | goto err_out; | |
287 | ||
288 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
289 | struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j]; | |
290 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
291 | p, 0, PAGE_SIZE, | |
292 | PCI_DMA_BIDIRECTIONAL); | |
293 | ||
294 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
295 | goto err_out; | |
296 | ||
297 | ppgtt->gen8_pt_dma_addr[i][j] = temp; | |
298 | } | |
299 | } | |
300 | ||
b1fe6673 BW |
301 | /* For now, the PPGTT helper functions all require that the PDEs are |
302 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we | |
303 | * will never need to touch the PDEs again */ | |
304 | for (i = 0; i < max_pdp; i++) { | |
305 | gen8_ppgtt_pde_t *pd_vaddr; | |
306 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
307 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
308 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
309 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
310 | I915_CACHE_LLC); | |
311 | } | |
312 | kunmap_atomic(pd_vaddr); | |
313 | } | |
314 | ||
37aca44a BW |
315 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
316 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
317 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
318 | ppgtt->num_pt_pages, | |
319 | (ppgtt->num_pt_pages - num_pt_pages) + | |
320 | size % (1<<30)); | |
321 | return -ENOSYS; /* Not ready yet */ | |
322 | ||
323 | err_out: | |
324 | ppgtt->base.cleanup(&ppgtt->base); | |
325 | return ret; | |
326 | } | |
327 | ||
3e302542 | 328 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 329 | { |
853ba5d2 | 330 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
331 | gen6_gtt_pte_t __iomem *pd_addr; |
332 | uint32_t pd_entry; | |
333 | int i; | |
334 | ||
0a732870 | 335 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
336 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
337 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
338 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
339 | dma_addr_t pt_addr; | |
340 | ||
341 | pt_addr = ppgtt->pt_dma_addr[i]; | |
342 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
343 | pd_entry |= GEN6_PDE_VALID; | |
344 | ||
345 | writel(pd_entry, pd_addr + i); | |
346 | } | |
347 | readl(pd_addr); | |
3e302542 BW |
348 | } |
349 | ||
350 | static int gen6_ppgtt_enable(struct drm_device *dev) | |
351 | { | |
352 | drm_i915_private_t *dev_priv = dev->dev_private; | |
353 | uint32_t pd_offset; | |
354 | struct intel_ring_buffer *ring; | |
355 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
356 | int i; | |
357 | ||
358 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
359 | ||
360 | gen6_write_pdes(ppgtt); | |
6197349b BW |
361 | |
362 | pd_offset = ppgtt->pd_offset; | |
363 | pd_offset /= 64; /* in cachelines, */ | |
364 | pd_offset <<= 16; | |
365 | ||
366 | if (INTEL_INFO(dev)->gen == 6) { | |
367 | uint32_t ecochk, gab_ctl, ecobits; | |
368 | ||
369 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
370 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
371 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
372 | |
373 | gab_ctl = I915_READ(GAB_CTL); | |
374 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
375 | ||
376 | ecochk = I915_READ(GAM_ECOCHK); | |
377 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
378 | ECOCHK_PPGTT_CACHE64B); | |
379 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
380 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 381 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
382 | |
383 | ecobits = I915_READ(GAC_ECO_BITS); | |
384 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
385 | ||
a6f429a5 VS |
386 | ecochk = I915_READ(GAM_ECOCHK); |
387 | if (IS_HASWELL(dev)) { | |
388 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
389 | } else { | |
390 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
391 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
392 | } | |
393 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
394 | /* GFX_MODE is per-ring on gen7+ */ |
395 | } | |
396 | ||
397 | for_each_ring(ring, dev_priv, i) { | |
398 | if (INTEL_INFO(dev)->gen >= 7) | |
399 | I915_WRITE(RING_MODE_GEN7(ring), | |
400 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
401 | ||
402 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
403 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
404 | } | |
b7c36d25 | 405 | return 0; |
6197349b BW |
406 | } |
407 | ||
1d2a314c | 408 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 409 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
1d2a314c | 410 | unsigned first_entry, |
828c7908 BW |
411 | unsigned num_entries, |
412 | bool use_scratch) | |
1d2a314c | 413 | { |
853ba5d2 BW |
414 | struct i915_hw_ppgtt *ppgtt = |
415 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 416 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 417 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
418 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
419 | unsigned last_pte, i; | |
1d2a314c | 420 | |
b35b380e | 421 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 422 | |
7bddb01f DV |
423 | while (num_entries) { |
424 | last_pte = first_pte + num_entries; | |
425 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
426 | last_pte = I915_PPGTT_PT_ENTRIES; | |
427 | ||
a15326a5 | 428 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 429 | |
7bddb01f DV |
430 | for (i = first_pte; i < last_pte; i++) |
431 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
432 | |
433 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 434 | |
7bddb01f DV |
435 | num_entries -= last_pte - first_pte; |
436 | first_pte = 0; | |
a15326a5 | 437 | act_pt++; |
7bddb01f | 438 | } |
1d2a314c DV |
439 | } |
440 | ||
853ba5d2 | 441 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 DV |
442 | struct sg_table *pages, |
443 | unsigned first_entry, | |
444 | enum i915_cache_level cache_level) | |
445 | { | |
853ba5d2 BW |
446 | struct i915_hw_ppgtt *ppgtt = |
447 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 448 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 449 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
450 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
451 | struct sg_page_iter sg_iter; | |
452 | ||
a15326a5 | 453 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
454 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
455 | dma_addr_t page_addr; | |
456 | ||
2db76d7c | 457 | page_addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 458 | pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true); |
6e995e23 ID |
459 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
460 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
461 | act_pt++; |
462 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 463 | act_pte = 0; |
def886c3 | 464 | |
def886c3 | 465 | } |
def886c3 | 466 | } |
6e995e23 | 467 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
468 | } |
469 | ||
853ba5d2 | 470 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 471 | { |
853ba5d2 BW |
472 | struct i915_hw_ppgtt *ppgtt = |
473 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
474 | int i; |
475 | ||
93bd8649 BW |
476 | drm_mm_takedown(&ppgtt->base.mm); |
477 | ||
3440d265 DV |
478 | if (ppgtt->pt_dma_addr) { |
479 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 480 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
481 | ppgtt->pt_dma_addr[i], |
482 | 4096, PCI_DMA_BIDIRECTIONAL); | |
483 | } | |
484 | ||
485 | kfree(ppgtt->pt_dma_addr); | |
486 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
487 | __free_page(ppgtt->pt_pages[i]); | |
488 | kfree(ppgtt->pt_pages); | |
489 | kfree(ppgtt); | |
490 | } | |
491 | ||
492 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
493 | { | |
853ba5d2 | 494 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 495 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 496 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
497 | int i; |
498 | int ret = -ENOMEM; | |
499 | ||
500 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
501 | * entries. For aliasing ppgtt support we just steal them at the end for | |
502 | * now. */ | |
e1b73cba | 503 | first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); |
1d2a314c | 504 | |
08c45263 | 505 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
6670a5a5 | 506 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
6197349b | 507 | ppgtt->enable = gen6_ppgtt_enable; |
853ba5d2 BW |
508 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
509 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
510 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
511 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
a1e22653 | 512 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c DV |
513 | GFP_KERNEL); |
514 | if (!ppgtt->pt_pages) | |
3440d265 | 515 | return -ENOMEM; |
1d2a314c DV |
516 | |
517 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
518 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
519 | if (!ppgtt->pt_pages[i]) | |
520 | goto err_pt_alloc; | |
521 | } | |
522 | ||
a1e22653 | 523 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 BW |
524 | GFP_KERNEL); |
525 | if (!ppgtt->pt_dma_addr) | |
526 | goto err_pt_alloc; | |
1d2a314c | 527 | |
8d2e6308 BW |
528 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
529 | dma_addr_t pt_addr; | |
211c568b | 530 | |
8d2e6308 BW |
531 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
532 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 533 | |
8d2e6308 BW |
534 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
535 | ret = -EIO; | |
536 | goto err_pd_pin; | |
1d2a314c | 537 | |
211c568b | 538 | } |
8d2e6308 | 539 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 540 | } |
1d2a314c | 541 | |
853ba5d2 | 542 | ppgtt->base.clear_range(&ppgtt->base, 0, |
828c7908 | 543 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); |
1d2a314c | 544 | |
e7c2b58b | 545 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 546 | |
1d2a314c DV |
547 | return 0; |
548 | ||
549 | err_pd_pin: | |
550 | if (ppgtt->pt_dma_addr) { | |
551 | for (i--; i >= 0; i--) | |
552 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
553 | 4096, PCI_DMA_BIDIRECTIONAL); | |
554 | } | |
555 | err_pt_alloc: | |
556 | kfree(ppgtt->pt_dma_addr); | |
557 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
558 | if (ppgtt->pt_pages[i]) | |
559 | __free_page(ppgtt->pt_pages[i]); | |
560 | } | |
561 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
562 | |
563 | return ret; | |
564 | } | |
565 | ||
566 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
567 | { | |
568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
569 | struct i915_hw_ppgtt *ppgtt; | |
570 | int ret; | |
571 | ||
572 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
573 | if (!ppgtt) | |
574 | return -ENOMEM; | |
575 | ||
853ba5d2 | 576 | ppgtt->base.dev = dev; |
3440d265 | 577 | |
3ed124b2 BW |
578 | if (INTEL_INFO(dev)->gen < 8) |
579 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 580 | else if (IS_GEN8(dev)) |
37aca44a | 581 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
582 | else |
583 | BUG(); | |
584 | ||
3440d265 DV |
585 | if (ret) |
586 | kfree(ppgtt); | |
93bd8649 | 587 | else { |
3440d265 | 588 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
93bd8649 BW |
589 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
590 | ppgtt->base.total); | |
591 | } | |
1d2a314c DV |
592 | |
593 | return ret; | |
594 | } | |
595 | ||
596 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
597 | { | |
598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
599 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
600 | |
601 | if (!ppgtt) | |
602 | return; | |
603 | ||
853ba5d2 | 604 | ppgtt->base.cleanup(&ppgtt->base); |
5963cf04 | 605 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
606 | } |
607 | ||
7bddb01f DV |
608 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
609 | struct drm_i915_gem_object *obj, | |
610 | enum i915_cache_level cache_level) | |
611 | { | |
853ba5d2 BW |
612 | ppgtt->base.insert_entries(&ppgtt->base, obj->pages, |
613 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
614 | cache_level); | |
7bddb01f DV |
615 | } |
616 | ||
617 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
618 | struct drm_i915_gem_object *obj) | |
619 | { | |
853ba5d2 BW |
620 | ppgtt->base.clear_range(&ppgtt->base, |
621 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
828c7908 BW |
622 | obj->base.size >> PAGE_SHIFT, |
623 | true); | |
7bddb01f DV |
624 | } |
625 | ||
a81cc00c BW |
626 | extern int intel_iommu_gfx_mapped; |
627 | /* Certain Gen5 chipsets require require idling the GPU before | |
628 | * unmapping anything from the GTT when VT-d is enabled. | |
629 | */ | |
630 | static inline bool needs_idle_maps(struct drm_device *dev) | |
631 | { | |
632 | #ifdef CONFIG_INTEL_IOMMU | |
633 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
634 | * was loaded first. | |
635 | */ | |
636 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
637 | return true; | |
638 | #endif | |
639 | return false; | |
640 | } | |
641 | ||
5c042287 BW |
642 | static bool do_idling(struct drm_i915_private *dev_priv) |
643 | { | |
644 | bool ret = dev_priv->mm.interruptible; | |
645 | ||
a81cc00c | 646 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 647 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 648 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
649 | DRM_ERROR("Couldn't idle GPU\n"); |
650 | /* Wait a bit, in hopes it avoids the hang */ | |
651 | udelay(10); | |
652 | } | |
653 | } | |
654 | ||
655 | return ret; | |
656 | } | |
657 | ||
658 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
659 | { | |
a81cc00c | 660 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
661 | dev_priv->mm.interruptible = interruptible; |
662 | } | |
663 | ||
828c7908 BW |
664 | void i915_check_and_clear_faults(struct drm_device *dev) |
665 | { | |
666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
667 | struct intel_ring_buffer *ring; | |
668 | int i; | |
669 | ||
670 | if (INTEL_INFO(dev)->gen < 6) | |
671 | return; | |
672 | ||
673 | for_each_ring(ring, dev_priv, i) { | |
674 | u32 fault_reg; | |
675 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
676 | if (fault_reg & RING_FAULT_VALID) { | |
677 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
678 | "\tAddr: 0x%08lx\\n" | |
679 | "\tAddress space: %s\n" | |
680 | "\tSource ID: %d\n" | |
681 | "\tType: %d\n", | |
682 | fault_reg & PAGE_MASK, | |
683 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
684 | RING_FAULT_SRCID(fault_reg), | |
685 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
686 | I915_WRITE(RING_FAULT_REG(ring), | |
687 | fault_reg & ~RING_FAULT_VALID); | |
688 | } | |
689 | } | |
690 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
691 | } | |
692 | ||
693 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
694 | { | |
695 | struct drm_i915_private *dev_priv = dev->dev_private; | |
696 | ||
697 | /* Don't bother messing with faults pre GEN6 as we have little | |
698 | * documentation supporting that it's a good idea. | |
699 | */ | |
700 | if (INTEL_INFO(dev)->gen < 6) | |
701 | return; | |
702 | ||
703 | i915_check_and_clear_faults(dev); | |
704 | ||
705 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
706 | dev_priv->gtt.base.start / PAGE_SIZE, | |
707 | dev_priv->gtt.base.total / PAGE_SIZE, | |
708 | false); | |
709 | } | |
710 | ||
76aaf220 DV |
711 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
712 | { | |
713 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 714 | struct drm_i915_gem_object *obj; |
76aaf220 | 715 | |
828c7908 BW |
716 | i915_check_and_clear_faults(dev); |
717 | ||
bee4a186 | 718 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 BW |
719 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
720 | dev_priv->gtt.base.start / PAGE_SIZE, | |
828c7908 BW |
721 | dev_priv->gtt.base.total / PAGE_SIZE, |
722 | true); | |
bee4a186 | 723 | |
35c20a60 | 724 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2c22569b | 725 | i915_gem_clflush_object(obj, obj->pin_display); |
74163907 | 726 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
727 | } |
728 | ||
e76e9aeb | 729 | i915_gem_chipset_flush(dev); |
76aaf220 | 730 | } |
7c2e6fdf | 731 | |
74163907 | 732 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 733 | { |
9da3da66 | 734 | if (obj->has_dma_mapping) |
74163907 | 735 | return 0; |
9da3da66 CW |
736 | |
737 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
738 | obj->pages->sgl, obj->pages->nents, | |
739 | PCI_DMA_BIDIRECTIONAL)) | |
740 | return -ENOSPC; | |
741 | ||
742 | return 0; | |
7c2e6fdf DV |
743 | } |
744 | ||
94ec8f61 BW |
745 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
746 | { | |
747 | #ifdef writeq | |
748 | writeq(pte, addr); | |
749 | #else | |
750 | iowrite32((u32)pte, addr); | |
751 | iowrite32(pte >> 32, addr + 4); | |
752 | #endif | |
753 | } | |
754 | ||
755 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
756 | struct sg_table *st, | |
757 | unsigned int first_entry, | |
758 | enum i915_cache_level level) | |
759 | { | |
760 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
761 | gen8_gtt_pte_t __iomem *gtt_entries = | |
762 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
763 | int i = 0; | |
764 | struct sg_page_iter sg_iter; | |
765 | dma_addr_t addr; | |
766 | ||
767 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
768 | addr = sg_dma_address(sg_iter.sg) + | |
769 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
770 | gen8_set_pte(>t_entries[i], | |
771 | gen8_pte_encode(addr, level, true)); | |
772 | i++; | |
773 | } | |
774 | ||
775 | /* | |
776 | * XXX: This serves as a posting read to make sure that the PTE has | |
777 | * actually been updated. There is some concern that even though | |
778 | * registers and PTEs are within the same BAR that they are potentially | |
779 | * of NUMA access patterns. Therefore, even with the way we assume | |
780 | * hardware should work, we must keep this posting read for paranoia. | |
781 | */ | |
782 | if (i != 0) | |
783 | WARN_ON(readq(>t_entries[i-1]) | |
784 | != gen8_pte_encode(addr, level, true)); | |
785 | ||
786 | #if 0 /* TODO: Still needed on GEN8? */ | |
787 | /* This next bit makes the above posting read even more important. We | |
788 | * want to flush the TLBs only after we're certain all the PTE updates | |
789 | * have finished. | |
790 | */ | |
791 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
792 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
793 | #endif | |
794 | } | |
795 | ||
e76e9aeb BW |
796 | /* |
797 | * Binds an object into the global gtt with the specified cache level. The object | |
798 | * will be accessible to the GPU via commands whose operands reference offsets | |
799 | * within the global GTT as well as accessible by the GPU through the GMADR | |
800 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
801 | */ | |
853ba5d2 | 802 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
803 | struct sg_table *st, |
804 | unsigned int first_entry, | |
805 | enum i915_cache_level level) | |
e76e9aeb | 806 | { |
853ba5d2 | 807 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
808 | gen6_gtt_pte_t __iomem *gtt_entries = |
809 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
810 | int i = 0; |
811 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
812 | dma_addr_t addr; |
813 | ||
6e995e23 | 814 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 815 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 816 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 817 | i++; |
e76e9aeb BW |
818 | } |
819 | ||
e76e9aeb BW |
820 | /* XXX: This serves as a posting read to make sure that the PTE has |
821 | * actually been updated. There is some concern that even though | |
822 | * registers and PTEs are within the same BAR that they are potentially | |
823 | * of NUMA access patterns. Therefore, even with the way we assume | |
824 | * hardware should work, we must keep this posting read for paranoia. | |
825 | */ | |
826 | if (i != 0) | |
853ba5d2 | 827 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 828 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
829 | |
830 | /* This next bit makes the above posting read even more important. We | |
831 | * want to flush the TLBs only after we're certain all the PTE updates | |
832 | * have finished. | |
833 | */ | |
834 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
835 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
836 | } |
837 | ||
94ec8f61 BW |
838 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
839 | unsigned int first_entry, | |
840 | unsigned int num_entries, | |
841 | bool use_scratch) | |
842 | { | |
843 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
844 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = | |
845 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
846 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
847 | int i; | |
848 | ||
849 | if (WARN(num_entries > max_entries, | |
850 | "First entry = %d; Num entries = %d (max=%d)\n", | |
851 | first_entry, num_entries, max_entries)) | |
852 | num_entries = max_entries; | |
853 | ||
854 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
855 | I915_CACHE_LLC, | |
856 | use_scratch); | |
857 | for (i = 0; i < num_entries; i++) | |
858 | gen8_set_pte(>t_base[i], scratch_pte); | |
859 | readl(gtt_base); | |
860 | } | |
861 | ||
853ba5d2 | 862 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 863 | unsigned int first_entry, |
828c7908 BW |
864 | unsigned int num_entries, |
865 | bool use_scratch) | |
7faf1ab2 | 866 | { |
853ba5d2 | 867 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
868 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
869 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 870 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
871 | int i; |
872 | ||
873 | if (WARN(num_entries > max_entries, | |
874 | "First entry = %d; Num entries = %d (max=%d)\n", | |
875 | first_entry, num_entries, max_entries)) | |
876 | num_entries = max_entries; | |
877 | ||
828c7908 BW |
878 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
879 | ||
7faf1ab2 DV |
880 | for (i = 0; i < num_entries; i++) |
881 | iowrite32(scratch_pte, >t_base[i]); | |
882 | readl(gtt_base); | |
883 | } | |
884 | ||
853ba5d2 | 885 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
886 | struct sg_table *st, |
887 | unsigned int pg_start, | |
888 | enum i915_cache_level cache_level) | |
889 | { | |
890 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
891 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
892 | ||
893 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
894 | ||
895 | } | |
896 | ||
853ba5d2 | 897 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 898 | unsigned int first_entry, |
828c7908 BW |
899 | unsigned int num_entries, |
900 | bool unused) | |
7faf1ab2 DV |
901 | { |
902 | intel_gtt_clear_range(first_entry, num_entries); | |
903 | } | |
904 | ||
905 | ||
74163907 DV |
906 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
907 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
908 | { |
909 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 | 910 | struct drm_i915_private *dev_priv = dev->dev_private; |
853ba5d2 | 911 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 912 | |
853ba5d2 BW |
913 | dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages, |
914 | entry, | |
915 | cache_level); | |
d5bd1449 | 916 | |
74898d7e | 917 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
918 | } |
919 | ||
05394f39 | 920 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 921 | { |
7faf1ab2 DV |
922 | struct drm_device *dev = obj->base.dev; |
923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 | 924 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 925 | |
853ba5d2 BW |
926 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
927 | entry, | |
828c7908 BW |
928 | obj->base.size >> PAGE_SHIFT, |
929 | true); | |
74898d7e DV |
930 | |
931 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
932 | } |
933 | ||
934 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 935 | { |
5c042287 BW |
936 | struct drm_device *dev = obj->base.dev; |
937 | struct drm_i915_private *dev_priv = dev->dev_private; | |
938 | bool interruptible; | |
939 | ||
940 | interruptible = do_idling(dev_priv); | |
941 | ||
9da3da66 CW |
942 | if (!obj->has_dma_mapping) |
943 | dma_unmap_sg(&dev->pdev->dev, | |
944 | obj->pages->sgl, obj->pages->nents, | |
945 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
946 | |
947 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 948 | } |
644ec02b | 949 | |
42d6ab48 CW |
950 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
951 | unsigned long color, | |
952 | unsigned long *start, | |
953 | unsigned long *end) | |
954 | { | |
955 | if (node->color != color) | |
956 | *start += 4096; | |
957 | ||
958 | if (!list_empty(&node->node_list)) { | |
959 | node = list_entry(node->node_list.next, | |
960 | struct drm_mm_node, | |
961 | node_list); | |
962 | if (node->allocated && node->color != color) | |
963 | *end -= 4096; | |
964 | } | |
965 | } | |
fbe5d36e | 966 | |
d7e5008f BW |
967 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
968 | unsigned long start, | |
969 | unsigned long mappable_end, | |
970 | unsigned long end) | |
644ec02b | 971 | { |
e78891ca BW |
972 | /* Let GEM Manage all of the aperture. |
973 | * | |
974 | * However, leave one page at the end still bound to the scratch page. | |
975 | * There are a number of places where the hardware apparently prefetches | |
976 | * past the end of the object, and we've seen multiple hangs with the | |
977 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
978 | * aperture. One page should be enough to keep any prefetching inside | |
979 | * of the aperture. | |
980 | */ | |
40d74980 BW |
981 | struct drm_i915_private *dev_priv = dev->dev_private; |
982 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
983 | struct drm_mm_node *entry; |
984 | struct drm_i915_gem_object *obj; | |
985 | unsigned long hole_start, hole_end; | |
644ec02b | 986 | |
35451cb6 BW |
987 | BUG_ON(mappable_end > end); |
988 | ||
ed2f3452 | 989 | /* Subtract the guard page ... */ |
40d74980 | 990 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 991 | if (!HAS_LLC(dev)) |
93bd8649 | 992 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 993 | |
ed2f3452 | 994 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 995 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 996 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 997 | int ret; |
edd41a87 | 998 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
999 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1000 | ||
1001 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1002 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 1003 | if (ret) |
b3a070cc | 1004 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 | 1005 | obj->has_global_gtt_mapping = 1; |
2f633156 | 1006 | list_add(&vma->vma_link, &obj->vma_list); |
ed2f3452 CW |
1007 | } |
1008 | ||
853ba5d2 BW |
1009 | dev_priv->gtt.base.start = start; |
1010 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1011 | |
ed2f3452 | 1012 | /* Clear any non-preallocated blocks */ |
40d74980 | 1013 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
853ba5d2 | 1014 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
ed2f3452 CW |
1015 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1016 | hole_start, hole_end); | |
828c7908 | 1017 | ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); |
ed2f3452 CW |
1018 | } |
1019 | ||
1020 | /* And finally clear the reserved guard page */ | |
828c7908 | 1021 | ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); |
e76e9aeb BW |
1022 | } |
1023 | ||
d7e5008f BW |
1024 | static bool |
1025 | intel_enable_ppgtt(struct drm_device *dev) | |
1026 | { | |
1027 | if (i915_enable_ppgtt >= 0) | |
1028 | return i915_enable_ppgtt; | |
1029 | ||
1030 | #ifdef CONFIG_INTEL_IOMMU | |
1031 | /* Disable ppgtt on SNB if VT-d is on. */ | |
1032 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
1033 | return false; | |
1034 | #endif | |
1035 | ||
1036 | return true; | |
1037 | } | |
1038 | ||
1039 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
1040 | { | |
1041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1042 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1043 | |
853ba5d2 | 1044 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1045 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
1046 | |
1047 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 1048 | int ret; |
3eb1c005 BW |
1049 | |
1050 | if (INTEL_INFO(dev)->gen <= 7) { | |
1051 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
1052 | * aperture accordingly when using aliasing ppgtt. */ | |
6670a5a5 | 1053 | gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
3eb1c005 | 1054 | } |
d7e5008f BW |
1055 | |
1056 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
1057 | ||
1058 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 1059 | if (!ret) |
d7e5008f | 1060 | return; |
e78891ca BW |
1061 | |
1062 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
93bd8649 | 1063 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
6670a5a5 | 1064 | gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
d7e5008f | 1065 | } |
e78891ca | 1066 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1067 | } |
1068 | ||
1069 | static int setup_scratch_page(struct drm_device *dev) | |
1070 | { | |
1071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1072 | struct page *page; | |
1073 | dma_addr_t dma_addr; | |
1074 | ||
1075 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1076 | if (page == NULL) | |
1077 | return -ENOMEM; | |
1078 | get_page(page); | |
1079 | set_pages_uc(page, 1); | |
1080 | ||
1081 | #ifdef CONFIG_INTEL_IOMMU | |
1082 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1083 | PCI_DMA_BIDIRECTIONAL); | |
1084 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1085 | return -EINVAL; | |
1086 | #else | |
1087 | dma_addr = page_to_phys(page); | |
1088 | #endif | |
853ba5d2 BW |
1089 | dev_priv->gtt.base.scratch.page = page; |
1090 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1091 | |
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | static void teardown_scratch_page(struct drm_device *dev) | |
1096 | { | |
1097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1098 | struct page *page = dev_priv->gtt.base.scratch.page; |
1099 | ||
1100 | set_pages_wb(page, 1); | |
1101 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1102 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1103 | put_page(page); |
1104 | __free_page(page); | |
e76e9aeb BW |
1105 | } |
1106 | ||
1107 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1108 | { | |
1109 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1110 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1111 | return snb_gmch_ctl << 20; | |
1112 | } | |
1113 | ||
9459d252 BW |
1114 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1115 | { | |
1116 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1117 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1118 | if (bdw_gmch_ctl) | |
1119 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
1120 | return bdw_gmch_ctl << 20; | |
1121 | } | |
1122 | ||
baa09f5f | 1123 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1124 | { |
1125 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1126 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1127 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1128 | } | |
1129 | ||
9459d252 BW |
1130 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1131 | { | |
1132 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1133 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1134 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1135 | } | |
1136 | ||
63340133 BW |
1137 | static int ggtt_probe_common(struct drm_device *dev, |
1138 | size_t gtt_size) | |
1139 | { | |
1140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1141 | phys_addr_t gtt_bus_addr; | |
1142 | int ret; | |
1143 | ||
1144 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
1145 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
1146 | (pci_resource_len(dev->pdev, 0) / 2); | |
1147 | ||
1148 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); | |
1149 | if (!dev_priv->gtt.gsm) { | |
1150 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1151 | return -ENOMEM; | |
1152 | } | |
1153 | ||
1154 | ret = setup_scratch_page(dev); | |
1155 | if (ret) { | |
1156 | DRM_ERROR("Scratch setup failed\n"); | |
1157 | /* iounmap will also get called at remove, but meh */ | |
1158 | iounmap(dev_priv->gtt.gsm); | |
1159 | } | |
1160 | ||
1161 | return ret; | |
1162 | } | |
1163 | ||
fbe5d36e BW |
1164 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1165 | * bits. When using advanced contexts each context stores its own PAT, but | |
1166 | * writing this data shouldn't be harmful even in those cases. */ | |
1167 | static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) | |
1168 | { | |
1169 | #define GEN8_PPAT_UC (0<<0) | |
1170 | #define GEN8_PPAT_WC (1<<0) | |
1171 | #define GEN8_PPAT_WT (2<<0) | |
1172 | #define GEN8_PPAT_WB (3<<0) | |
1173 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
1174 | /* FIXME(BDW): Bspec is completely confused about cache control bits. */ | |
1175 | #define GEN8_PPAT_LLC (1<<2) | |
1176 | #define GEN8_PPAT_LLCELLC (2<<2) | |
1177 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
1178 | #define GEN8_PPAT_AGE(x) (x<<4) | |
1179 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
1180 | uint64_t pat; | |
1181 | ||
1182 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1183 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1184 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1185 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1186 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1187 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1188 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1189 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1190 | ||
1191 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1192 | * write would work. */ | |
1193 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1194 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1195 | } | |
1196 | ||
63340133 BW |
1197 | static int gen8_gmch_probe(struct drm_device *dev, |
1198 | size_t *gtt_total, | |
1199 | size_t *stolen, | |
1200 | phys_addr_t *mappable_base, | |
1201 | unsigned long *mappable_end) | |
1202 | { | |
1203 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1204 | unsigned int gtt_size; | |
1205 | u16 snb_gmch_ctl; | |
1206 | int ret; | |
1207 | ||
1208 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1209 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1210 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1211 | ||
1212 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1213 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1214 | ||
1215 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1216 | ||
1217 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1218 | ||
1219 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 1220 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1221 | |
fbe5d36e BW |
1222 | gen8_setup_private_ppat(dev_priv); |
1223 | ||
63340133 BW |
1224 | ret = ggtt_probe_common(dev, gtt_size); |
1225 | ||
94ec8f61 BW |
1226 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1227 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1228 | |
1229 | return ret; | |
1230 | } | |
1231 | ||
baa09f5f BW |
1232 | static int gen6_gmch_probe(struct drm_device *dev, |
1233 | size_t *gtt_total, | |
41907ddc BW |
1234 | size_t *stolen, |
1235 | phys_addr_t *mappable_base, | |
1236 | unsigned long *mappable_end) | |
e76e9aeb BW |
1237 | { |
1238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1239 | unsigned int gtt_size; |
e76e9aeb | 1240 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1241 | int ret; |
1242 | ||
41907ddc BW |
1243 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1244 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1245 | ||
baa09f5f BW |
1246 | /* 64/512MB is the current min/max we actually know of, but this is just |
1247 | * a coarse sanity check. | |
e76e9aeb | 1248 | */ |
41907ddc | 1249 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1250 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1251 | dev_priv->gtt.mappable_end); | |
1252 | return -ENXIO; | |
e76e9aeb BW |
1253 | } |
1254 | ||
e76e9aeb BW |
1255 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1256 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1257 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1258 | |
63340133 | 1259 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 1260 | |
63340133 BW |
1261 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1262 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
a93e4161 | 1263 | |
63340133 | 1264 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1265 | |
853ba5d2 BW |
1266 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1267 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1268 | |
e76e9aeb BW |
1269 | return ret; |
1270 | } | |
1271 | ||
853ba5d2 | 1272 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1273 | { |
853ba5d2 BW |
1274 | |
1275 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
1276 | iounmap(gtt->gsm); | |
1277 | teardown_scratch_page(vm->dev); | |
644ec02b | 1278 | } |
baa09f5f BW |
1279 | |
1280 | static int i915_gmch_probe(struct drm_device *dev, | |
1281 | size_t *gtt_total, | |
41907ddc BW |
1282 | size_t *stolen, |
1283 | phys_addr_t *mappable_base, | |
1284 | unsigned long *mappable_end) | |
baa09f5f BW |
1285 | { |
1286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1287 | int ret; | |
1288 | ||
baa09f5f BW |
1289 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1290 | if (!ret) { | |
1291 | DRM_ERROR("failed to set up gmch\n"); | |
1292 | return -EIO; | |
1293 | } | |
1294 | ||
41907ddc | 1295 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1296 | |
1297 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 BW |
1298 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
1299 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; | |
baa09f5f BW |
1300 | |
1301 | return 0; | |
1302 | } | |
1303 | ||
853ba5d2 | 1304 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1305 | { |
1306 | intel_gmch_remove(); | |
1307 | } | |
1308 | ||
1309 | int i915_gem_gtt_init(struct drm_device *dev) | |
1310 | { | |
1311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1312 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1313 | int ret; |
1314 | ||
baa09f5f | 1315 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 1316 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 1317 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 1318 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 1319 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 1320 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 1321 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 1322 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 1323 | else if (IS_HASWELL(dev)) |
853ba5d2 | 1324 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 1325 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 1326 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
1327 | else if (INTEL_INFO(dev)->gen >= 7) |
1328 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 1329 | else |
350ec881 | 1330 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
1331 | } else { |
1332 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
1333 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
1334 | } |
1335 | ||
853ba5d2 | 1336 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 1337 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 1338 | if (ret) |
baa09f5f | 1339 | return ret; |
baa09f5f | 1340 | |
853ba5d2 BW |
1341 | gtt->base.dev = dev; |
1342 | ||
baa09f5f | 1343 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
1344 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
1345 | gtt->base.total >> 20); | |
b2f21b4d BW |
1346 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
1347 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
1348 | |
1349 | return 0; | |
1350 | } |