Commit | Line | Data |
---|---|---|
76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
33 | ||
26b1ff35 BW |
34 | /* PPGTT stuff */ |
35 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 36 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
37 | |
38 | #define GEN6_PDE_VALID (1 << 0) | |
39 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
40 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
41 | ||
42 | #define GEN6_PTE_VALID (1 << 0) | |
43 | #define GEN6_PTE_UNCACHED (1 << 1) | |
44 | #define HSW_PTE_UNCACHED (0) | |
45 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
46 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) | |
47 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
0d8ff15e BW |
48 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
49 | ||
50 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
51 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
52 | */ | |
53 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
54 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 55 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 56 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 57 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
26b1ff35 | 58 | |
80a74f7f | 59 | static gen6_gtt_pte_t gen6_pte_encode(dma_addr_t addr, |
2d04befb | 60 | enum i915_cache_level level) |
54d12527 | 61 | { |
e7c2b58b | 62 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 63 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
64 | |
65 | switch (level) { | |
66 | case I915_CACHE_LLC_MLC: | |
9119708c | 67 | pte |= GEN6_PTE_CACHE_LLC_MLC; |
e7210c3c BW |
68 | break; |
69 | case I915_CACHE_LLC: | |
70 | pte |= GEN6_PTE_CACHE_LLC; | |
71 | break; | |
72 | case I915_CACHE_NONE: | |
9119708c | 73 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
74 | break; |
75 | default: | |
76 | BUG(); | |
77 | } | |
78 | ||
54d12527 BW |
79 | return pte; |
80 | } | |
81 | ||
93c34e70 KG |
82 | #define BYT_PTE_WRITEABLE (1 << 1) |
83 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
84 | ||
80a74f7f | 85 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
93c34e70 KG |
86 | enum i915_cache_level level) |
87 | { | |
88 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
89 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | |
90 | ||
91 | /* Mark the page as writeable. Other platforms don't have a | |
92 | * setting for read-only/writable, so this matches that behavior. | |
93 | */ | |
94 | pte |= BYT_PTE_WRITEABLE; | |
95 | ||
96 | if (level != I915_CACHE_NONE) | |
97 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
98 | ||
99 | return pte; | |
100 | } | |
101 | ||
80a74f7f | 102 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
9119708c KG |
103 | enum i915_cache_level level) |
104 | { | |
105 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
0d8ff15e | 106 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
107 | |
108 | if (level != I915_CACHE_NONE) | |
87a6b688 | 109 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
110 | |
111 | return pte; | |
112 | } | |
113 | ||
4d15c145 BW |
114 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
115 | enum i915_cache_level level) | |
116 | { | |
117 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
118 | pte |= HSW_PTE_ADDR_ENCODE(addr); | |
119 | ||
120 | if (level != I915_CACHE_NONE) | |
121 | pte |= HSW_WB_ELLC_LLC_AGE0; | |
122 | ||
123 | return pte; | |
124 | } | |
125 | ||
3e302542 | 126 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 127 | { |
853ba5d2 | 128 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
129 | gen6_gtt_pte_t __iomem *pd_addr; |
130 | uint32_t pd_entry; | |
131 | int i; | |
132 | ||
0a732870 | 133 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
134 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
135 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
136 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
137 | dma_addr_t pt_addr; | |
138 | ||
139 | pt_addr = ppgtt->pt_dma_addr[i]; | |
140 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
141 | pd_entry |= GEN6_PDE_VALID; | |
142 | ||
143 | writel(pd_entry, pd_addr + i); | |
144 | } | |
145 | readl(pd_addr); | |
3e302542 BW |
146 | } |
147 | ||
148 | static int gen6_ppgtt_enable(struct drm_device *dev) | |
149 | { | |
150 | drm_i915_private_t *dev_priv = dev->dev_private; | |
151 | uint32_t pd_offset; | |
152 | struct intel_ring_buffer *ring; | |
153 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
154 | int i; | |
155 | ||
156 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
157 | ||
158 | gen6_write_pdes(ppgtt); | |
6197349b BW |
159 | |
160 | pd_offset = ppgtt->pd_offset; | |
161 | pd_offset /= 64; /* in cachelines, */ | |
162 | pd_offset <<= 16; | |
163 | ||
164 | if (INTEL_INFO(dev)->gen == 6) { | |
165 | uint32_t ecochk, gab_ctl, ecobits; | |
166 | ||
167 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
168 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
169 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
170 | |
171 | gab_ctl = I915_READ(GAB_CTL); | |
172 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
173 | ||
174 | ecochk = I915_READ(GAM_ECOCHK); | |
175 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
176 | ECOCHK_PPGTT_CACHE64B); | |
177 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
178 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 179 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
180 | |
181 | ecobits = I915_READ(GAC_ECO_BITS); | |
182 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
183 | ||
a6f429a5 VS |
184 | ecochk = I915_READ(GAM_ECOCHK); |
185 | if (IS_HASWELL(dev)) { | |
186 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
187 | } else { | |
188 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
189 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
190 | } | |
191 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
192 | /* GFX_MODE is per-ring on gen7+ */ |
193 | } | |
194 | ||
195 | for_each_ring(ring, dev_priv, i) { | |
196 | if (INTEL_INFO(dev)->gen >= 7) | |
197 | I915_WRITE(RING_MODE_GEN7(ring), | |
198 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
199 | ||
200 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
201 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
202 | } | |
b7c36d25 | 203 | return 0; |
6197349b BW |
204 | } |
205 | ||
1d2a314c | 206 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 207 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
1d2a314c DV |
208 | unsigned first_entry, |
209 | unsigned num_entries) | |
210 | { | |
853ba5d2 BW |
211 | struct i915_hw_ppgtt *ppgtt = |
212 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 213 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 214 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
215 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
216 | unsigned last_pte, i; | |
1d2a314c | 217 | |
853ba5d2 | 218 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC); |
1d2a314c | 219 | |
7bddb01f DV |
220 | while (num_entries) { |
221 | last_pte = first_pte + num_entries; | |
222 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
223 | last_pte = I915_PPGTT_PT_ENTRIES; | |
224 | ||
a15326a5 | 225 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 226 | |
7bddb01f DV |
227 | for (i = first_pte; i < last_pte; i++) |
228 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
229 | |
230 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 231 | |
7bddb01f DV |
232 | num_entries -= last_pte - first_pte; |
233 | first_pte = 0; | |
a15326a5 | 234 | act_pt++; |
7bddb01f | 235 | } |
1d2a314c DV |
236 | } |
237 | ||
853ba5d2 | 238 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 DV |
239 | struct sg_table *pages, |
240 | unsigned first_entry, | |
241 | enum i915_cache_level cache_level) | |
242 | { | |
853ba5d2 BW |
243 | struct i915_hw_ppgtt *ppgtt = |
244 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 245 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 246 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
247 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
248 | struct sg_page_iter sg_iter; | |
249 | ||
a15326a5 | 250 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
251 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
252 | dma_addr_t page_addr; | |
253 | ||
2db76d7c | 254 | page_addr = sg_page_iter_dma_address(&sg_iter); |
853ba5d2 | 255 | pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level); |
6e995e23 ID |
256 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
257 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
258 | act_pt++; |
259 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 260 | act_pte = 0; |
def886c3 | 261 | |
def886c3 | 262 | } |
def886c3 | 263 | } |
6e995e23 | 264 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
265 | } |
266 | ||
853ba5d2 | 267 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 268 | { |
853ba5d2 BW |
269 | struct i915_hw_ppgtt *ppgtt = |
270 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
271 | int i; |
272 | ||
93bd8649 BW |
273 | drm_mm_takedown(&ppgtt->base.mm); |
274 | ||
3440d265 DV |
275 | if (ppgtt->pt_dma_addr) { |
276 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 277 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
278 | ppgtt->pt_dma_addr[i], |
279 | 4096, PCI_DMA_BIDIRECTIONAL); | |
280 | } | |
281 | ||
282 | kfree(ppgtt->pt_dma_addr); | |
283 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
284 | __free_page(ppgtt->pt_pages[i]); | |
285 | kfree(ppgtt->pt_pages); | |
286 | kfree(ppgtt); | |
287 | } | |
288 | ||
289 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
290 | { | |
853ba5d2 | 291 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 292 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 293 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
294 | int i; |
295 | int ret = -ENOMEM; | |
296 | ||
297 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
298 | * entries. For aliasing ppgtt support we just steal them at the end for | |
299 | * now. */ | |
e1b73cba | 300 | first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); |
1d2a314c | 301 | |
08c45263 | 302 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
6670a5a5 | 303 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
6197349b | 304 | ppgtt->enable = gen6_ppgtt_enable; |
853ba5d2 BW |
305 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
306 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
307 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
308 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
1d2a314c DV |
309 | ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, |
310 | GFP_KERNEL); | |
311 | if (!ppgtt->pt_pages) | |
3440d265 | 312 | return -ENOMEM; |
1d2a314c DV |
313 | |
314 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
315 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
316 | if (!ppgtt->pt_pages[i]) | |
317 | goto err_pt_alloc; | |
318 | } | |
319 | ||
8d2e6308 BW |
320 | ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries, |
321 | GFP_KERNEL); | |
322 | if (!ppgtt->pt_dma_addr) | |
323 | goto err_pt_alloc; | |
1d2a314c | 324 | |
8d2e6308 BW |
325 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
326 | dma_addr_t pt_addr; | |
211c568b | 327 | |
8d2e6308 BW |
328 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
329 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 330 | |
8d2e6308 BW |
331 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
332 | ret = -EIO; | |
333 | goto err_pd_pin; | |
1d2a314c | 334 | |
211c568b | 335 | } |
8d2e6308 | 336 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 337 | } |
1d2a314c | 338 | |
853ba5d2 BW |
339 | ppgtt->base.clear_range(&ppgtt->base, 0, |
340 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES); | |
1d2a314c | 341 | |
e7c2b58b | 342 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 343 | |
1d2a314c DV |
344 | return 0; |
345 | ||
346 | err_pd_pin: | |
347 | if (ppgtt->pt_dma_addr) { | |
348 | for (i--; i >= 0; i--) | |
349 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
350 | 4096, PCI_DMA_BIDIRECTIONAL); | |
351 | } | |
352 | err_pt_alloc: | |
353 | kfree(ppgtt->pt_dma_addr); | |
354 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
355 | if (ppgtt->pt_pages[i]) | |
356 | __free_page(ppgtt->pt_pages[i]); | |
357 | } | |
358 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
359 | |
360 | return ret; | |
361 | } | |
362 | ||
363 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
364 | { | |
365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
366 | struct i915_hw_ppgtt *ppgtt; | |
367 | int ret; | |
368 | ||
369 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
370 | if (!ppgtt) | |
371 | return -ENOMEM; | |
372 | ||
853ba5d2 | 373 | ppgtt->base.dev = dev; |
3440d265 | 374 | |
3ed124b2 BW |
375 | if (INTEL_INFO(dev)->gen < 8) |
376 | ret = gen6_ppgtt_init(ppgtt); | |
377 | else | |
378 | BUG(); | |
379 | ||
3440d265 DV |
380 | if (ret) |
381 | kfree(ppgtt); | |
93bd8649 | 382 | else { |
3440d265 | 383 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
93bd8649 BW |
384 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
385 | ppgtt->base.total); | |
386 | } | |
1d2a314c DV |
387 | |
388 | return ret; | |
389 | } | |
390 | ||
391 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
392 | { | |
393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
394 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
395 | |
396 | if (!ppgtt) | |
397 | return; | |
398 | ||
853ba5d2 | 399 | ppgtt->base.cleanup(&ppgtt->base); |
5963cf04 | 400 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
401 | } |
402 | ||
7bddb01f DV |
403 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
404 | struct drm_i915_gem_object *obj, | |
405 | enum i915_cache_level cache_level) | |
406 | { | |
853ba5d2 BW |
407 | ppgtt->base.insert_entries(&ppgtt->base, obj->pages, |
408 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
409 | cache_level); | |
7bddb01f DV |
410 | } |
411 | ||
412 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
413 | struct drm_i915_gem_object *obj) | |
414 | { | |
853ba5d2 BW |
415 | ppgtt->base.clear_range(&ppgtt->base, |
416 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
417 | obj->base.size >> PAGE_SHIFT); | |
7bddb01f DV |
418 | } |
419 | ||
a81cc00c BW |
420 | extern int intel_iommu_gfx_mapped; |
421 | /* Certain Gen5 chipsets require require idling the GPU before | |
422 | * unmapping anything from the GTT when VT-d is enabled. | |
423 | */ | |
424 | static inline bool needs_idle_maps(struct drm_device *dev) | |
425 | { | |
426 | #ifdef CONFIG_INTEL_IOMMU | |
427 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
428 | * was loaded first. | |
429 | */ | |
430 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
431 | return true; | |
432 | #endif | |
433 | return false; | |
434 | } | |
435 | ||
5c042287 BW |
436 | static bool do_idling(struct drm_i915_private *dev_priv) |
437 | { | |
438 | bool ret = dev_priv->mm.interruptible; | |
439 | ||
a81cc00c | 440 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 441 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 442 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
443 | DRM_ERROR("Couldn't idle GPU\n"); |
444 | /* Wait a bit, in hopes it avoids the hang */ | |
445 | udelay(10); | |
446 | } | |
447 | } | |
448 | ||
449 | return ret; | |
450 | } | |
451 | ||
452 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
453 | { | |
a81cc00c | 454 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
455 | dev_priv->mm.interruptible = interruptible; |
456 | } | |
457 | ||
76aaf220 DV |
458 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
459 | { | |
460 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 461 | struct drm_i915_gem_object *obj; |
76aaf220 | 462 | |
bee4a186 | 463 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 BW |
464 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
465 | dev_priv->gtt.base.start / PAGE_SIZE, | |
466 | dev_priv->gtt.base.total / PAGE_SIZE); | |
bee4a186 | 467 | |
35c20a60 | 468 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
a8e93126 | 469 | i915_gem_clflush_object(obj); |
74163907 | 470 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
471 | } |
472 | ||
e76e9aeb | 473 | i915_gem_chipset_flush(dev); |
76aaf220 | 474 | } |
7c2e6fdf | 475 | |
74163907 | 476 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 477 | { |
9da3da66 | 478 | if (obj->has_dma_mapping) |
74163907 | 479 | return 0; |
9da3da66 CW |
480 | |
481 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
482 | obj->pages->sgl, obj->pages->nents, | |
483 | PCI_DMA_BIDIRECTIONAL)) | |
484 | return -ENOSPC; | |
485 | ||
486 | return 0; | |
7c2e6fdf DV |
487 | } |
488 | ||
e76e9aeb BW |
489 | /* |
490 | * Binds an object into the global gtt with the specified cache level. The object | |
491 | * will be accessible to the GPU via commands whose operands reference offsets | |
492 | * within the global GTT as well as accessible by the GPU through the GMADR | |
493 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
494 | */ | |
853ba5d2 | 495 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
496 | struct sg_table *st, |
497 | unsigned int first_entry, | |
498 | enum i915_cache_level level) | |
e76e9aeb | 499 | { |
853ba5d2 | 500 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
501 | gen6_gtt_pte_t __iomem *gtt_entries = |
502 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
503 | int i = 0; |
504 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
505 | dma_addr_t addr; |
506 | ||
6e995e23 | 507 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 508 | addr = sg_page_iter_dma_address(&sg_iter); |
853ba5d2 | 509 | iowrite32(vm->pte_encode(addr, level), >t_entries[i]); |
6e995e23 | 510 | i++; |
e76e9aeb BW |
511 | } |
512 | ||
e76e9aeb BW |
513 | /* XXX: This serves as a posting read to make sure that the PTE has |
514 | * actually been updated. There is some concern that even though | |
515 | * registers and PTEs are within the same BAR that they are potentially | |
516 | * of NUMA access patterns. Therefore, even with the way we assume | |
517 | * hardware should work, we must keep this posting read for paranoia. | |
518 | */ | |
519 | if (i != 0) | |
853ba5d2 BW |
520 | WARN_ON(readl(>t_entries[i-1]) != |
521 | vm->pte_encode(addr, level)); | |
0f9b91c7 BW |
522 | |
523 | /* This next bit makes the above posting read even more important. We | |
524 | * want to flush the TLBs only after we're certain all the PTE updates | |
525 | * have finished. | |
526 | */ | |
527 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
528 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
529 | } |
530 | ||
853ba5d2 | 531 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 DV |
532 | unsigned int first_entry, |
533 | unsigned int num_entries) | |
534 | { | |
853ba5d2 | 535 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
536 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
537 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 538 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
539 | int i; |
540 | ||
541 | if (WARN(num_entries > max_entries, | |
542 | "First entry = %d; Num entries = %d (max=%d)\n", | |
543 | first_entry, num_entries, max_entries)) | |
544 | num_entries = max_entries; | |
545 | ||
853ba5d2 | 546 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC); |
7faf1ab2 DV |
547 | for (i = 0; i < num_entries; i++) |
548 | iowrite32(scratch_pte, >t_base[i]); | |
549 | readl(gtt_base); | |
550 | } | |
551 | ||
552 | ||
853ba5d2 | 553 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
554 | struct sg_table *st, |
555 | unsigned int pg_start, | |
556 | enum i915_cache_level cache_level) | |
557 | { | |
558 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
559 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
560 | ||
561 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
562 | ||
563 | } | |
564 | ||
853ba5d2 | 565 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 DV |
566 | unsigned int first_entry, |
567 | unsigned int num_entries) | |
568 | { | |
569 | intel_gtt_clear_range(first_entry, num_entries); | |
570 | } | |
571 | ||
572 | ||
74163907 DV |
573 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
574 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
575 | { |
576 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 | 577 | struct drm_i915_private *dev_priv = dev->dev_private; |
853ba5d2 | 578 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 579 | |
853ba5d2 BW |
580 | dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages, |
581 | entry, | |
582 | cache_level); | |
d5bd1449 | 583 | |
74898d7e | 584 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
585 | } |
586 | ||
05394f39 | 587 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 588 | { |
7faf1ab2 DV |
589 | struct drm_device *dev = obj->base.dev; |
590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 | 591 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 592 | |
853ba5d2 BW |
593 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
594 | entry, | |
595 | obj->base.size >> PAGE_SHIFT); | |
74898d7e DV |
596 | |
597 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
598 | } |
599 | ||
600 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 601 | { |
5c042287 BW |
602 | struct drm_device *dev = obj->base.dev; |
603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
604 | bool interruptible; | |
605 | ||
606 | interruptible = do_idling(dev_priv); | |
607 | ||
9da3da66 CW |
608 | if (!obj->has_dma_mapping) |
609 | dma_unmap_sg(&dev->pdev->dev, | |
610 | obj->pages->sgl, obj->pages->nents, | |
611 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
612 | |
613 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 614 | } |
644ec02b | 615 | |
42d6ab48 CW |
616 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
617 | unsigned long color, | |
618 | unsigned long *start, | |
619 | unsigned long *end) | |
620 | { | |
621 | if (node->color != color) | |
622 | *start += 4096; | |
623 | ||
624 | if (!list_empty(&node->node_list)) { | |
625 | node = list_entry(node->node_list.next, | |
626 | struct drm_mm_node, | |
627 | node_list); | |
628 | if (node->allocated && node->color != color) | |
629 | *end -= 4096; | |
630 | } | |
631 | } | |
d7e5008f BW |
632 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
633 | unsigned long start, | |
634 | unsigned long mappable_end, | |
635 | unsigned long end) | |
644ec02b | 636 | { |
e78891ca BW |
637 | /* Let GEM Manage all of the aperture. |
638 | * | |
639 | * However, leave one page at the end still bound to the scratch page. | |
640 | * There are a number of places where the hardware apparently prefetches | |
641 | * past the end of the object, and we've seen multiple hangs with the | |
642 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
643 | * aperture. One page should be enough to keep any prefetching inside | |
644 | * of the aperture. | |
645 | */ | |
40d74980 BW |
646 | struct drm_i915_private *dev_priv = dev->dev_private; |
647 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
648 | struct drm_mm_node *entry; |
649 | struct drm_i915_gem_object *obj; | |
650 | unsigned long hole_start, hole_end; | |
644ec02b | 651 | |
35451cb6 BW |
652 | BUG_ON(mappable_end > end); |
653 | ||
ed2f3452 | 654 | /* Subtract the guard page ... */ |
40d74980 | 655 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 656 | if (!HAS_LLC(dev)) |
93bd8649 | 657 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 658 | |
ed2f3452 | 659 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 660 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 661 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 662 | int ret; |
edd41a87 | 663 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
664 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
665 | ||
666 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 667 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 668 | if (ret) |
b3a070cc | 669 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 | 670 | obj->has_global_gtt_mapping = 1; |
2f633156 | 671 | list_add(&vma->vma_link, &obj->vma_list); |
ed2f3452 CW |
672 | } |
673 | ||
853ba5d2 BW |
674 | dev_priv->gtt.base.start = start; |
675 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 676 | |
ed2f3452 | 677 | /* Clear any non-preallocated blocks */ |
40d74980 | 678 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
853ba5d2 | 679 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
ed2f3452 CW |
680 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
681 | hole_start, hole_end); | |
40d74980 | 682 | ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count); |
ed2f3452 CW |
683 | } |
684 | ||
685 | /* And finally clear the reserved guard page */ | |
40d74980 | 686 | ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1); |
e76e9aeb BW |
687 | } |
688 | ||
d7e5008f BW |
689 | static bool |
690 | intel_enable_ppgtt(struct drm_device *dev) | |
691 | { | |
692 | if (i915_enable_ppgtt >= 0) | |
693 | return i915_enable_ppgtt; | |
694 | ||
695 | #ifdef CONFIG_INTEL_IOMMU | |
696 | /* Disable ppgtt on SNB if VT-d is on. */ | |
697 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
698 | return false; | |
699 | #endif | |
700 | ||
701 | return true; | |
702 | } | |
703 | ||
704 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
705 | { | |
706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
707 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 708 | |
853ba5d2 | 709 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 710 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
711 | |
712 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 713 | int ret; |
3eb1c005 BW |
714 | |
715 | if (INTEL_INFO(dev)->gen <= 7) { | |
716 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
717 | * aperture accordingly when using aliasing ppgtt. */ | |
6670a5a5 | 718 | gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
3eb1c005 | 719 | } |
d7e5008f BW |
720 | |
721 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
722 | ||
723 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 724 | if (!ret) |
d7e5008f | 725 | return; |
e78891ca BW |
726 | |
727 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
93bd8649 | 728 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
6670a5a5 | 729 | gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
d7e5008f | 730 | } |
e78891ca | 731 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
732 | } |
733 | ||
734 | static int setup_scratch_page(struct drm_device *dev) | |
735 | { | |
736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
737 | struct page *page; | |
738 | dma_addr_t dma_addr; | |
739 | ||
740 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
741 | if (page == NULL) | |
742 | return -ENOMEM; | |
743 | get_page(page); | |
744 | set_pages_uc(page, 1); | |
745 | ||
746 | #ifdef CONFIG_INTEL_IOMMU | |
747 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
748 | PCI_DMA_BIDIRECTIONAL); | |
749 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
750 | return -EINVAL; | |
751 | #else | |
752 | dma_addr = page_to_phys(page); | |
753 | #endif | |
853ba5d2 BW |
754 | dev_priv->gtt.base.scratch.page = page; |
755 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
756 | |
757 | return 0; | |
758 | } | |
759 | ||
760 | static void teardown_scratch_page(struct drm_device *dev) | |
761 | { | |
762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
763 | struct page *page = dev_priv->gtt.base.scratch.page; |
764 | ||
765 | set_pages_wb(page, 1); | |
766 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 767 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
768 | put_page(page); |
769 | __free_page(page); | |
e76e9aeb BW |
770 | } |
771 | ||
772 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
773 | { | |
774 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
775 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
776 | return snb_gmch_ctl << 20; | |
777 | } | |
778 | ||
baa09f5f | 779 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
780 | { |
781 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
782 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
783 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
784 | } | |
785 | ||
baa09f5f BW |
786 | static int gen6_gmch_probe(struct drm_device *dev, |
787 | size_t *gtt_total, | |
41907ddc BW |
788 | size_t *stolen, |
789 | phys_addr_t *mappable_base, | |
790 | unsigned long *mappable_end) | |
e76e9aeb BW |
791 | { |
792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
793 | phys_addr_t gtt_bus_addr; | |
baa09f5f | 794 | unsigned int gtt_size; |
e76e9aeb | 795 | u16 snb_gmch_ctl; |
e76e9aeb BW |
796 | int ret; |
797 | ||
41907ddc BW |
798 | *mappable_base = pci_resource_start(dev->pdev, 2); |
799 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
800 | ||
baa09f5f BW |
801 | /* 64/512MB is the current min/max we actually know of, but this is just |
802 | * a coarse sanity check. | |
e76e9aeb | 803 | */ |
41907ddc | 804 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
805 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
806 | dev_priv->gtt.mappable_end); | |
807 | return -ENXIO; | |
e76e9aeb BW |
808 | } |
809 | ||
e76e9aeb BW |
810 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
811 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 812 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
baa09f5f | 813 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
e76e9aeb | 814 | |
c4ae25ec | 815 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
e7c2b58b | 816 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 817 | |
a93e4161 BW |
818 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
819 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
820 | (pci_resource_len(dev->pdev, 0) / 2); | |
821 | ||
baa09f5f | 822 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); |
5d4545ae | 823 | if (!dev_priv->gtt.gsm) { |
e76e9aeb | 824 | DRM_ERROR("Failed to map the gtt page table\n"); |
baa09f5f | 825 | return -ENOMEM; |
e76e9aeb BW |
826 | } |
827 | ||
baa09f5f BW |
828 | ret = setup_scratch_page(dev); |
829 | if (ret) | |
830 | DRM_ERROR("Scratch setup failed\n"); | |
e76e9aeb | 831 | |
853ba5d2 BW |
832 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
833 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 834 | |
e76e9aeb BW |
835 | return ret; |
836 | } | |
837 | ||
853ba5d2 | 838 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 839 | { |
853ba5d2 BW |
840 | |
841 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
842 | iounmap(gtt->gsm); | |
843 | teardown_scratch_page(vm->dev); | |
644ec02b | 844 | } |
baa09f5f BW |
845 | |
846 | static int i915_gmch_probe(struct drm_device *dev, | |
847 | size_t *gtt_total, | |
41907ddc BW |
848 | size_t *stolen, |
849 | phys_addr_t *mappable_base, | |
850 | unsigned long *mappable_end) | |
baa09f5f BW |
851 | { |
852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853 | int ret; | |
854 | ||
baa09f5f BW |
855 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
856 | if (!ret) { | |
857 | DRM_ERROR("failed to set up gmch\n"); | |
858 | return -EIO; | |
859 | } | |
860 | ||
41907ddc | 861 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
862 | |
863 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 BW |
864 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
865 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; | |
baa09f5f BW |
866 | |
867 | return 0; | |
868 | } | |
869 | ||
853ba5d2 | 870 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
871 | { |
872 | intel_gmch_remove(); | |
873 | } | |
874 | ||
875 | int i915_gem_gtt_init(struct drm_device *dev) | |
876 | { | |
877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
878 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
879 | int ret; |
880 | ||
baa09f5f | 881 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 882 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 883 | gtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 884 | } else { |
b2f21b4d | 885 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 886 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 887 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 888 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 889 | else if (IS_HASWELL(dev)) |
853ba5d2 | 890 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 891 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 892 | gtt->base.pte_encode = byt_pte_encode; |
b2f21b4d | 893 | else |
853ba5d2 | 894 | gtt->base.pte_encode = gen6_pte_encode; |
baa09f5f BW |
895 | } |
896 | ||
853ba5d2 | 897 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 898 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 899 | if (ret) |
baa09f5f | 900 | return ret; |
baa09f5f | 901 | |
853ba5d2 BW |
902 | gtt->base.dev = dev; |
903 | ||
baa09f5f | 904 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
905 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
906 | gtt->base.total >> 20); | |
b2f21b4d BW |
907 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
908 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
909 | |
910 | return 0; | |
911 | } |