Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
d31eb10e | 33 | typedef uint64_t gen8_gtt_pte_t; |
6670a5a5 | 34 | |
26b1ff35 BW |
35 | /* PPGTT stuff */ |
36 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 37 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
38 | |
39 | #define GEN6_PDE_VALID (1 << 0) | |
40 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
41 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
42 | ||
43 | #define GEN6_PTE_VALID (1 << 0) | |
44 | #define GEN6_PTE_UNCACHED (1 << 1) | |
45 | #define HSW_PTE_UNCACHED (0) | |
46 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 47 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 48 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
49 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
50 | ||
51 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
52 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
53 | */ | |
54 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
55 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 56 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 57 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 58 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
651d794f | 59 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
26b1ff35 | 60 | |
94ec8f61 BW |
61 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
62 | enum i915_cache_level level, | |
63 | bool valid) | |
64 | { | |
65 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
66 | pte |= addr; | |
67 | return pte; | |
68 | } | |
69 | ||
350ec881 | 70 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
71 | enum i915_cache_level level, |
72 | bool valid) | |
54d12527 | 73 | { |
b35b380e | 74 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 75 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
76 | |
77 | switch (level) { | |
350ec881 CW |
78 | case I915_CACHE_L3_LLC: |
79 | case I915_CACHE_LLC: | |
80 | pte |= GEN6_PTE_CACHE_LLC; | |
81 | break; | |
82 | case I915_CACHE_NONE: | |
83 | pte |= GEN6_PTE_UNCACHED; | |
84 | break; | |
85 | default: | |
86 | WARN_ON(1); | |
87 | } | |
88 | ||
89 | return pte; | |
90 | } | |
91 | ||
92 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
93 | enum i915_cache_level level, |
94 | bool valid) | |
350ec881 | 95 | { |
b35b380e | 96 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
97 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
98 | ||
99 | switch (level) { | |
100 | case I915_CACHE_L3_LLC: | |
101 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
102 | break; |
103 | case I915_CACHE_LLC: | |
104 | pte |= GEN6_PTE_CACHE_LLC; | |
105 | break; | |
106 | case I915_CACHE_NONE: | |
9119708c | 107 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
108 | break; |
109 | default: | |
350ec881 | 110 | WARN_ON(1); |
e7210c3c BW |
111 | } |
112 | ||
54d12527 BW |
113 | return pte; |
114 | } | |
115 | ||
93c34e70 KG |
116 | #define BYT_PTE_WRITEABLE (1 << 1) |
117 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
118 | ||
80a74f7f | 119 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
120 | enum i915_cache_level level, |
121 | bool valid) | |
93c34e70 | 122 | { |
b35b380e | 123 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
124 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
125 | ||
126 | /* Mark the page as writeable. Other platforms don't have a | |
127 | * setting for read-only/writable, so this matches that behavior. | |
128 | */ | |
129 | pte |= BYT_PTE_WRITEABLE; | |
130 | ||
131 | if (level != I915_CACHE_NONE) | |
132 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
133 | ||
134 | return pte; | |
135 | } | |
136 | ||
80a74f7f | 137 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
138 | enum i915_cache_level level, |
139 | bool valid) | |
9119708c | 140 | { |
b35b380e | 141 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 142 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
143 | |
144 | if (level != I915_CACHE_NONE) | |
87a6b688 | 145 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
146 | |
147 | return pte; | |
148 | } | |
149 | ||
4d15c145 | 150 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
151 | enum i915_cache_level level, |
152 | bool valid) | |
4d15c145 | 153 | { |
b35b380e | 154 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
155 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
156 | ||
651d794f CW |
157 | switch (level) { |
158 | case I915_CACHE_NONE: | |
159 | break; | |
160 | case I915_CACHE_WT: | |
161 | pte |= HSW_WT_ELLC_LLC_AGE0; | |
162 | break; | |
163 | default: | |
4d15c145 | 164 | pte |= HSW_WB_ELLC_LLC_AGE0; |
651d794f CW |
165 | break; |
166 | } | |
4d15c145 BW |
167 | |
168 | return pte; | |
169 | } | |
170 | ||
3e302542 | 171 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 172 | { |
853ba5d2 | 173 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
174 | gen6_gtt_pte_t __iomem *pd_addr; |
175 | uint32_t pd_entry; | |
176 | int i; | |
177 | ||
0a732870 | 178 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
179 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
180 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
181 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
182 | dma_addr_t pt_addr; | |
183 | ||
184 | pt_addr = ppgtt->pt_dma_addr[i]; | |
185 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
186 | pd_entry |= GEN6_PDE_VALID; | |
187 | ||
188 | writel(pd_entry, pd_addr + i); | |
189 | } | |
190 | readl(pd_addr); | |
3e302542 BW |
191 | } |
192 | ||
193 | static int gen6_ppgtt_enable(struct drm_device *dev) | |
194 | { | |
195 | drm_i915_private_t *dev_priv = dev->dev_private; | |
196 | uint32_t pd_offset; | |
197 | struct intel_ring_buffer *ring; | |
198 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
199 | int i; | |
200 | ||
201 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
202 | ||
203 | gen6_write_pdes(ppgtt); | |
6197349b BW |
204 | |
205 | pd_offset = ppgtt->pd_offset; | |
206 | pd_offset /= 64; /* in cachelines, */ | |
207 | pd_offset <<= 16; | |
208 | ||
209 | if (INTEL_INFO(dev)->gen == 6) { | |
210 | uint32_t ecochk, gab_ctl, ecobits; | |
211 | ||
212 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
213 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
214 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
215 | |
216 | gab_ctl = I915_READ(GAB_CTL); | |
217 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
218 | ||
219 | ecochk = I915_READ(GAM_ECOCHK); | |
220 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
221 | ECOCHK_PPGTT_CACHE64B); | |
222 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
223 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 224 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
225 | |
226 | ecobits = I915_READ(GAC_ECO_BITS); | |
227 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
228 | ||
a6f429a5 VS |
229 | ecochk = I915_READ(GAM_ECOCHK); |
230 | if (IS_HASWELL(dev)) { | |
231 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
232 | } else { | |
233 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
234 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
235 | } | |
236 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
237 | /* GFX_MODE is per-ring on gen7+ */ |
238 | } | |
239 | ||
240 | for_each_ring(ring, dev_priv, i) { | |
241 | if (INTEL_INFO(dev)->gen >= 7) | |
242 | I915_WRITE(RING_MODE_GEN7(ring), | |
243 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
244 | ||
245 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
246 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
247 | } | |
b7c36d25 | 248 | return 0; |
6197349b BW |
249 | } |
250 | ||
1d2a314c | 251 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 252 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
1d2a314c | 253 | unsigned first_entry, |
828c7908 BW |
254 | unsigned num_entries, |
255 | bool use_scratch) | |
1d2a314c | 256 | { |
853ba5d2 BW |
257 | struct i915_hw_ppgtt *ppgtt = |
258 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 259 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 260 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
261 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
262 | unsigned last_pte, i; | |
1d2a314c | 263 | |
b35b380e | 264 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 265 | |
7bddb01f DV |
266 | while (num_entries) { |
267 | last_pte = first_pte + num_entries; | |
268 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
269 | last_pte = I915_PPGTT_PT_ENTRIES; | |
270 | ||
a15326a5 | 271 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 272 | |
7bddb01f DV |
273 | for (i = first_pte; i < last_pte; i++) |
274 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
275 | |
276 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 277 | |
7bddb01f DV |
278 | num_entries -= last_pte - first_pte; |
279 | first_pte = 0; | |
a15326a5 | 280 | act_pt++; |
7bddb01f | 281 | } |
1d2a314c DV |
282 | } |
283 | ||
853ba5d2 | 284 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 DV |
285 | struct sg_table *pages, |
286 | unsigned first_entry, | |
287 | enum i915_cache_level cache_level) | |
288 | { | |
853ba5d2 BW |
289 | struct i915_hw_ppgtt *ppgtt = |
290 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 291 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 292 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
293 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
294 | struct sg_page_iter sg_iter; | |
295 | ||
a15326a5 | 296 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
297 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
298 | dma_addr_t page_addr; | |
299 | ||
2db76d7c | 300 | page_addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 301 | pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true); |
6e995e23 ID |
302 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
303 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
304 | act_pt++; |
305 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 306 | act_pte = 0; |
def886c3 | 307 | |
def886c3 | 308 | } |
def886c3 | 309 | } |
6e995e23 | 310 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
311 | } |
312 | ||
853ba5d2 | 313 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 314 | { |
853ba5d2 BW |
315 | struct i915_hw_ppgtt *ppgtt = |
316 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
317 | int i; |
318 | ||
93bd8649 BW |
319 | drm_mm_takedown(&ppgtt->base.mm); |
320 | ||
3440d265 DV |
321 | if (ppgtt->pt_dma_addr) { |
322 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 323 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
324 | ppgtt->pt_dma_addr[i], |
325 | 4096, PCI_DMA_BIDIRECTIONAL); | |
326 | } | |
327 | ||
328 | kfree(ppgtt->pt_dma_addr); | |
329 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
330 | __free_page(ppgtt->pt_pages[i]); | |
331 | kfree(ppgtt->pt_pages); | |
332 | kfree(ppgtt); | |
333 | } | |
334 | ||
335 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
336 | { | |
853ba5d2 | 337 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 338 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 339 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
340 | int i; |
341 | int ret = -ENOMEM; | |
342 | ||
343 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
344 | * entries. For aliasing ppgtt support we just steal them at the end for | |
345 | * now. */ | |
e1b73cba | 346 | first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); |
1d2a314c | 347 | |
08c45263 | 348 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
6670a5a5 | 349 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
6197349b | 350 | ppgtt->enable = gen6_ppgtt_enable; |
853ba5d2 BW |
351 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
352 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
353 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
354 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
a1e22653 | 355 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c DV |
356 | GFP_KERNEL); |
357 | if (!ppgtt->pt_pages) | |
3440d265 | 358 | return -ENOMEM; |
1d2a314c DV |
359 | |
360 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
361 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
362 | if (!ppgtt->pt_pages[i]) | |
363 | goto err_pt_alloc; | |
364 | } | |
365 | ||
a1e22653 | 366 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 BW |
367 | GFP_KERNEL); |
368 | if (!ppgtt->pt_dma_addr) | |
369 | goto err_pt_alloc; | |
1d2a314c | 370 | |
8d2e6308 BW |
371 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
372 | dma_addr_t pt_addr; | |
211c568b | 373 | |
8d2e6308 BW |
374 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
375 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 376 | |
8d2e6308 BW |
377 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
378 | ret = -EIO; | |
379 | goto err_pd_pin; | |
1d2a314c | 380 | |
211c568b | 381 | } |
8d2e6308 | 382 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 383 | } |
1d2a314c | 384 | |
853ba5d2 | 385 | ppgtt->base.clear_range(&ppgtt->base, 0, |
828c7908 | 386 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); |
1d2a314c | 387 | |
e7c2b58b | 388 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 389 | |
1d2a314c DV |
390 | return 0; |
391 | ||
392 | err_pd_pin: | |
393 | if (ppgtt->pt_dma_addr) { | |
394 | for (i--; i >= 0; i--) | |
395 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
396 | 4096, PCI_DMA_BIDIRECTIONAL); | |
397 | } | |
398 | err_pt_alloc: | |
399 | kfree(ppgtt->pt_dma_addr); | |
400 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
401 | if (ppgtt->pt_pages[i]) | |
402 | __free_page(ppgtt->pt_pages[i]); | |
403 | } | |
404 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
405 | |
406 | return ret; | |
407 | } | |
408 | ||
409 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
410 | { | |
411 | struct drm_i915_private *dev_priv = dev->dev_private; | |
412 | struct i915_hw_ppgtt *ppgtt; | |
413 | int ret; | |
414 | ||
415 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
416 | if (!ppgtt) | |
417 | return -ENOMEM; | |
418 | ||
853ba5d2 | 419 | ppgtt->base.dev = dev; |
3440d265 | 420 | |
3ed124b2 BW |
421 | if (INTEL_INFO(dev)->gen < 8) |
422 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 DV |
423 | else if (IS_GEN8(dev)) |
424 | ret = -ENOSYS; | |
3ed124b2 BW |
425 | else |
426 | BUG(); | |
427 | ||
3440d265 DV |
428 | if (ret) |
429 | kfree(ppgtt); | |
93bd8649 | 430 | else { |
3440d265 | 431 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
93bd8649 BW |
432 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
433 | ppgtt->base.total); | |
434 | } | |
1d2a314c DV |
435 | |
436 | return ret; | |
437 | } | |
438 | ||
439 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
440 | { | |
441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
442 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
443 | |
444 | if (!ppgtt) | |
445 | return; | |
446 | ||
853ba5d2 | 447 | ppgtt->base.cleanup(&ppgtt->base); |
5963cf04 | 448 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
449 | } |
450 | ||
7bddb01f DV |
451 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
452 | struct drm_i915_gem_object *obj, | |
453 | enum i915_cache_level cache_level) | |
454 | { | |
853ba5d2 BW |
455 | ppgtt->base.insert_entries(&ppgtt->base, obj->pages, |
456 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
457 | cache_level); | |
7bddb01f DV |
458 | } |
459 | ||
460 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
461 | struct drm_i915_gem_object *obj) | |
462 | { | |
853ba5d2 BW |
463 | ppgtt->base.clear_range(&ppgtt->base, |
464 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, | |
828c7908 BW |
465 | obj->base.size >> PAGE_SHIFT, |
466 | true); | |
7bddb01f DV |
467 | } |
468 | ||
a81cc00c BW |
469 | extern int intel_iommu_gfx_mapped; |
470 | /* Certain Gen5 chipsets require require idling the GPU before | |
471 | * unmapping anything from the GTT when VT-d is enabled. | |
472 | */ | |
473 | static inline bool needs_idle_maps(struct drm_device *dev) | |
474 | { | |
475 | #ifdef CONFIG_INTEL_IOMMU | |
476 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
477 | * was loaded first. | |
478 | */ | |
479 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
480 | return true; | |
481 | #endif | |
482 | return false; | |
483 | } | |
484 | ||
5c042287 BW |
485 | static bool do_idling(struct drm_i915_private *dev_priv) |
486 | { | |
487 | bool ret = dev_priv->mm.interruptible; | |
488 | ||
a81cc00c | 489 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 490 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 491 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
492 | DRM_ERROR("Couldn't idle GPU\n"); |
493 | /* Wait a bit, in hopes it avoids the hang */ | |
494 | udelay(10); | |
495 | } | |
496 | } | |
497 | ||
498 | return ret; | |
499 | } | |
500 | ||
501 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
502 | { | |
a81cc00c | 503 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
504 | dev_priv->mm.interruptible = interruptible; |
505 | } | |
506 | ||
828c7908 BW |
507 | void i915_check_and_clear_faults(struct drm_device *dev) |
508 | { | |
509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
510 | struct intel_ring_buffer *ring; | |
511 | int i; | |
512 | ||
513 | if (INTEL_INFO(dev)->gen < 6) | |
514 | return; | |
515 | ||
516 | for_each_ring(ring, dev_priv, i) { | |
517 | u32 fault_reg; | |
518 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
519 | if (fault_reg & RING_FAULT_VALID) { | |
520 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
521 | "\tAddr: 0x%08lx\\n" | |
522 | "\tAddress space: %s\n" | |
523 | "\tSource ID: %d\n" | |
524 | "\tType: %d\n", | |
525 | fault_reg & PAGE_MASK, | |
526 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
527 | RING_FAULT_SRCID(fault_reg), | |
528 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
529 | I915_WRITE(RING_FAULT_REG(ring), | |
530 | fault_reg & ~RING_FAULT_VALID); | |
531 | } | |
532 | } | |
533 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
534 | } | |
535 | ||
536 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
537 | { | |
538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
539 | ||
540 | /* Don't bother messing with faults pre GEN6 as we have little | |
541 | * documentation supporting that it's a good idea. | |
542 | */ | |
543 | if (INTEL_INFO(dev)->gen < 6) | |
544 | return; | |
545 | ||
546 | i915_check_and_clear_faults(dev); | |
547 | ||
548 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
549 | dev_priv->gtt.base.start / PAGE_SIZE, | |
550 | dev_priv->gtt.base.total / PAGE_SIZE, | |
551 | false); | |
552 | } | |
553 | ||
76aaf220 DV |
554 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
555 | { | |
556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 557 | struct drm_i915_gem_object *obj; |
76aaf220 | 558 | |
828c7908 BW |
559 | i915_check_and_clear_faults(dev); |
560 | ||
bee4a186 | 561 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 BW |
562 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
563 | dev_priv->gtt.base.start / PAGE_SIZE, | |
828c7908 BW |
564 | dev_priv->gtt.base.total / PAGE_SIZE, |
565 | true); | |
bee4a186 | 566 | |
35c20a60 | 567 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2c22569b | 568 | i915_gem_clflush_object(obj, obj->pin_display); |
74163907 | 569 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
570 | } |
571 | ||
e76e9aeb | 572 | i915_gem_chipset_flush(dev); |
76aaf220 | 573 | } |
7c2e6fdf | 574 | |
74163907 | 575 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 576 | { |
9da3da66 | 577 | if (obj->has_dma_mapping) |
74163907 | 578 | return 0; |
9da3da66 CW |
579 | |
580 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
581 | obj->pages->sgl, obj->pages->nents, | |
582 | PCI_DMA_BIDIRECTIONAL)) | |
583 | return -ENOSPC; | |
584 | ||
585 | return 0; | |
7c2e6fdf DV |
586 | } |
587 | ||
94ec8f61 BW |
588 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
589 | { | |
590 | #ifdef writeq | |
591 | writeq(pte, addr); | |
592 | #else | |
593 | iowrite32((u32)pte, addr); | |
594 | iowrite32(pte >> 32, addr + 4); | |
595 | #endif | |
596 | } | |
597 | ||
598 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
599 | struct sg_table *st, | |
600 | unsigned int first_entry, | |
601 | enum i915_cache_level level) | |
602 | { | |
603 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
604 | gen8_gtt_pte_t __iomem *gtt_entries = | |
605 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
606 | int i = 0; | |
607 | struct sg_page_iter sg_iter; | |
608 | dma_addr_t addr; | |
609 | ||
610 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
611 | addr = sg_dma_address(sg_iter.sg) + | |
612 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
613 | gen8_set_pte(>t_entries[i], | |
614 | gen8_pte_encode(addr, level, true)); | |
615 | i++; | |
616 | } | |
617 | ||
618 | /* | |
619 | * XXX: This serves as a posting read to make sure that the PTE has | |
620 | * actually been updated. There is some concern that even though | |
621 | * registers and PTEs are within the same BAR that they are potentially | |
622 | * of NUMA access patterns. Therefore, even with the way we assume | |
623 | * hardware should work, we must keep this posting read for paranoia. | |
624 | */ | |
625 | if (i != 0) | |
626 | WARN_ON(readq(>t_entries[i-1]) | |
627 | != gen8_pte_encode(addr, level, true)); | |
628 | ||
629 | #if 0 /* TODO: Still needed on GEN8? */ | |
630 | /* This next bit makes the above posting read even more important. We | |
631 | * want to flush the TLBs only after we're certain all the PTE updates | |
632 | * have finished. | |
633 | */ | |
634 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
635 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
636 | #endif | |
637 | } | |
638 | ||
e76e9aeb BW |
639 | /* |
640 | * Binds an object into the global gtt with the specified cache level. The object | |
641 | * will be accessible to the GPU via commands whose operands reference offsets | |
642 | * within the global GTT as well as accessible by the GPU through the GMADR | |
643 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
644 | */ | |
853ba5d2 | 645 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
646 | struct sg_table *st, |
647 | unsigned int first_entry, | |
648 | enum i915_cache_level level) | |
e76e9aeb | 649 | { |
853ba5d2 | 650 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
651 | gen6_gtt_pte_t __iomem *gtt_entries = |
652 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
653 | int i = 0; |
654 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
655 | dma_addr_t addr; |
656 | ||
6e995e23 | 657 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 658 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 659 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 660 | i++; |
e76e9aeb BW |
661 | } |
662 | ||
e76e9aeb BW |
663 | /* XXX: This serves as a posting read to make sure that the PTE has |
664 | * actually been updated. There is some concern that even though | |
665 | * registers and PTEs are within the same BAR that they are potentially | |
666 | * of NUMA access patterns. Therefore, even with the way we assume | |
667 | * hardware should work, we must keep this posting read for paranoia. | |
668 | */ | |
669 | if (i != 0) | |
853ba5d2 | 670 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 671 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
672 | |
673 | /* This next bit makes the above posting read even more important. We | |
674 | * want to flush the TLBs only after we're certain all the PTE updates | |
675 | * have finished. | |
676 | */ | |
677 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
678 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
679 | } |
680 | ||
94ec8f61 BW |
681 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
682 | unsigned int first_entry, | |
683 | unsigned int num_entries, | |
684 | bool use_scratch) | |
685 | { | |
686 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
687 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = | |
688 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
689 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
690 | int i; | |
691 | ||
692 | if (WARN(num_entries > max_entries, | |
693 | "First entry = %d; Num entries = %d (max=%d)\n", | |
694 | first_entry, num_entries, max_entries)) | |
695 | num_entries = max_entries; | |
696 | ||
697 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
698 | I915_CACHE_LLC, | |
699 | use_scratch); | |
700 | for (i = 0; i < num_entries; i++) | |
701 | gen8_set_pte(>t_base[i], scratch_pte); | |
702 | readl(gtt_base); | |
703 | } | |
704 | ||
853ba5d2 | 705 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 706 | unsigned int first_entry, |
828c7908 BW |
707 | unsigned int num_entries, |
708 | bool use_scratch) | |
7faf1ab2 | 709 | { |
853ba5d2 | 710 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
711 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
712 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 713 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
714 | int i; |
715 | ||
716 | if (WARN(num_entries > max_entries, | |
717 | "First entry = %d; Num entries = %d (max=%d)\n", | |
718 | first_entry, num_entries, max_entries)) | |
719 | num_entries = max_entries; | |
720 | ||
828c7908 BW |
721 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
722 | ||
7faf1ab2 DV |
723 | for (i = 0; i < num_entries; i++) |
724 | iowrite32(scratch_pte, >t_base[i]); | |
725 | readl(gtt_base); | |
726 | } | |
727 | ||
853ba5d2 | 728 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
729 | struct sg_table *st, |
730 | unsigned int pg_start, | |
731 | enum i915_cache_level cache_level) | |
732 | { | |
733 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
734 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
735 | ||
736 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
737 | ||
738 | } | |
739 | ||
853ba5d2 | 740 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 741 | unsigned int first_entry, |
828c7908 BW |
742 | unsigned int num_entries, |
743 | bool unused) | |
7faf1ab2 DV |
744 | { |
745 | intel_gtt_clear_range(first_entry, num_entries); | |
746 | } | |
747 | ||
748 | ||
74163907 DV |
749 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
750 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
751 | { |
752 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 | 753 | struct drm_i915_private *dev_priv = dev->dev_private; |
853ba5d2 | 754 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 755 | |
853ba5d2 BW |
756 | dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages, |
757 | entry, | |
758 | cache_level); | |
d5bd1449 | 759 | |
74898d7e | 760 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
761 | } |
762 | ||
05394f39 | 763 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 764 | { |
7faf1ab2 DV |
765 | struct drm_device *dev = obj->base.dev; |
766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 | 767 | const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; |
7faf1ab2 | 768 | |
853ba5d2 BW |
769 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
770 | entry, | |
828c7908 BW |
771 | obj->base.size >> PAGE_SHIFT, |
772 | true); | |
74898d7e DV |
773 | |
774 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
775 | } |
776 | ||
777 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 778 | { |
5c042287 BW |
779 | struct drm_device *dev = obj->base.dev; |
780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
781 | bool interruptible; | |
782 | ||
783 | interruptible = do_idling(dev_priv); | |
784 | ||
9da3da66 CW |
785 | if (!obj->has_dma_mapping) |
786 | dma_unmap_sg(&dev->pdev->dev, | |
787 | obj->pages->sgl, obj->pages->nents, | |
788 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
789 | |
790 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 791 | } |
644ec02b | 792 | |
42d6ab48 CW |
793 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
794 | unsigned long color, | |
795 | unsigned long *start, | |
796 | unsigned long *end) | |
797 | { | |
798 | if (node->color != color) | |
799 | *start += 4096; | |
800 | ||
801 | if (!list_empty(&node->node_list)) { | |
802 | node = list_entry(node->node_list.next, | |
803 | struct drm_mm_node, | |
804 | node_list); | |
805 | if (node->allocated && node->color != color) | |
806 | *end -= 4096; | |
807 | } | |
808 | } | |
d7e5008f BW |
809 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
810 | unsigned long start, | |
811 | unsigned long mappable_end, | |
812 | unsigned long end) | |
644ec02b | 813 | { |
e78891ca BW |
814 | /* Let GEM Manage all of the aperture. |
815 | * | |
816 | * However, leave one page at the end still bound to the scratch page. | |
817 | * There are a number of places where the hardware apparently prefetches | |
818 | * past the end of the object, and we've seen multiple hangs with the | |
819 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
820 | * aperture. One page should be enough to keep any prefetching inside | |
821 | * of the aperture. | |
822 | */ | |
40d74980 BW |
823 | struct drm_i915_private *dev_priv = dev->dev_private; |
824 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
825 | struct drm_mm_node *entry; |
826 | struct drm_i915_gem_object *obj; | |
827 | unsigned long hole_start, hole_end; | |
644ec02b | 828 | |
35451cb6 BW |
829 | BUG_ON(mappable_end > end); |
830 | ||
ed2f3452 | 831 | /* Subtract the guard page ... */ |
40d74980 | 832 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 833 | if (!HAS_LLC(dev)) |
93bd8649 | 834 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 835 | |
ed2f3452 | 836 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 837 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 838 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 839 | int ret; |
edd41a87 | 840 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
841 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
842 | ||
843 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 844 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 845 | if (ret) |
b3a070cc | 846 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 | 847 | obj->has_global_gtt_mapping = 1; |
2f633156 | 848 | list_add(&vma->vma_link, &obj->vma_list); |
ed2f3452 CW |
849 | } |
850 | ||
853ba5d2 BW |
851 | dev_priv->gtt.base.start = start; |
852 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 853 | |
ed2f3452 | 854 | /* Clear any non-preallocated blocks */ |
40d74980 | 855 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
853ba5d2 | 856 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
ed2f3452 CW |
857 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
858 | hole_start, hole_end); | |
828c7908 | 859 | ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); |
ed2f3452 CW |
860 | } |
861 | ||
862 | /* And finally clear the reserved guard page */ | |
828c7908 | 863 | ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); |
e76e9aeb BW |
864 | } |
865 | ||
d7e5008f BW |
866 | static bool |
867 | intel_enable_ppgtt(struct drm_device *dev) | |
868 | { | |
869 | if (i915_enable_ppgtt >= 0) | |
870 | return i915_enable_ppgtt; | |
871 | ||
872 | #ifdef CONFIG_INTEL_IOMMU | |
873 | /* Disable ppgtt on SNB if VT-d is on. */ | |
874 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
875 | return false; | |
876 | #endif | |
877 | ||
878 | return true; | |
879 | } | |
880 | ||
881 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
882 | { | |
883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
884 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 885 | |
853ba5d2 | 886 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 887 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
888 | |
889 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 890 | int ret; |
3eb1c005 BW |
891 | |
892 | if (INTEL_INFO(dev)->gen <= 7) { | |
893 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
894 | * aperture accordingly when using aliasing ppgtt. */ | |
6670a5a5 | 895 | gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
3eb1c005 | 896 | } |
d7e5008f BW |
897 | |
898 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
899 | ||
900 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 901 | if (!ret) |
d7e5008f | 902 | return; |
e78891ca BW |
903 | |
904 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
93bd8649 | 905 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
6670a5a5 | 906 | gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
d7e5008f | 907 | } |
e78891ca | 908 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
909 | } |
910 | ||
911 | static int setup_scratch_page(struct drm_device *dev) | |
912 | { | |
913 | struct drm_i915_private *dev_priv = dev->dev_private; | |
914 | struct page *page; | |
915 | dma_addr_t dma_addr; | |
916 | ||
917 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
918 | if (page == NULL) | |
919 | return -ENOMEM; | |
920 | get_page(page); | |
921 | set_pages_uc(page, 1); | |
922 | ||
923 | #ifdef CONFIG_INTEL_IOMMU | |
924 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
925 | PCI_DMA_BIDIRECTIONAL); | |
926 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
927 | return -EINVAL; | |
928 | #else | |
929 | dma_addr = page_to_phys(page); | |
930 | #endif | |
853ba5d2 BW |
931 | dev_priv->gtt.base.scratch.page = page; |
932 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
933 | |
934 | return 0; | |
935 | } | |
936 | ||
937 | static void teardown_scratch_page(struct drm_device *dev) | |
938 | { | |
939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
940 | struct page *page = dev_priv->gtt.base.scratch.page; |
941 | ||
942 | set_pages_wb(page, 1); | |
943 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 944 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
945 | put_page(page); |
946 | __free_page(page); | |
e76e9aeb BW |
947 | } |
948 | ||
949 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
950 | { | |
951 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
952 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
953 | return snb_gmch_ctl << 20; | |
954 | } | |
955 | ||
9459d252 BW |
956 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
957 | { | |
958 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
959 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
960 | if (bdw_gmch_ctl) | |
961 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
962 | return bdw_gmch_ctl << 20; | |
963 | } | |
964 | ||
baa09f5f | 965 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
966 | { |
967 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
968 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
969 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
970 | } | |
971 | ||
9459d252 BW |
972 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
973 | { | |
974 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
975 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
976 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
977 | } | |
978 | ||
63340133 BW |
979 | static int ggtt_probe_common(struct drm_device *dev, |
980 | size_t gtt_size) | |
981 | { | |
982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
983 | phys_addr_t gtt_bus_addr; | |
984 | int ret; | |
985 | ||
986 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
987 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
988 | (pci_resource_len(dev->pdev, 0) / 2); | |
989 | ||
990 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); | |
991 | if (!dev_priv->gtt.gsm) { | |
992 | DRM_ERROR("Failed to map the gtt page table\n"); | |
993 | return -ENOMEM; | |
994 | } | |
995 | ||
996 | ret = setup_scratch_page(dev); | |
997 | if (ret) { | |
998 | DRM_ERROR("Scratch setup failed\n"); | |
999 | /* iounmap will also get called at remove, but meh */ | |
1000 | iounmap(dev_priv->gtt.gsm); | |
1001 | } | |
1002 | ||
1003 | return ret; | |
1004 | } | |
1005 | ||
1006 | static int gen8_gmch_probe(struct drm_device *dev, | |
1007 | size_t *gtt_total, | |
1008 | size_t *stolen, | |
1009 | phys_addr_t *mappable_base, | |
1010 | unsigned long *mappable_end) | |
1011 | { | |
1012 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1013 | unsigned int gtt_size; | |
1014 | u16 snb_gmch_ctl; | |
1015 | int ret; | |
1016 | ||
1017 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1018 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1019 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1020 | ||
1021 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1022 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1023 | ||
1024 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1025 | ||
1026 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1027 | ||
1028 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 1029 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 BW |
1030 | |
1031 | ret = ggtt_probe_common(dev, gtt_size); | |
1032 | ||
94ec8f61 BW |
1033 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1034 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1035 | |
1036 | return ret; | |
1037 | } | |
1038 | ||
baa09f5f BW |
1039 | static int gen6_gmch_probe(struct drm_device *dev, |
1040 | size_t *gtt_total, | |
41907ddc BW |
1041 | size_t *stolen, |
1042 | phys_addr_t *mappable_base, | |
1043 | unsigned long *mappable_end) | |
e76e9aeb BW |
1044 | { |
1045 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1046 | unsigned int gtt_size; |
e76e9aeb | 1047 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1048 | int ret; |
1049 | ||
41907ddc BW |
1050 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1051 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1052 | ||
baa09f5f BW |
1053 | /* 64/512MB is the current min/max we actually know of, but this is just |
1054 | * a coarse sanity check. | |
e76e9aeb | 1055 | */ |
41907ddc | 1056 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1057 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1058 | dev_priv->gtt.mappable_end); | |
1059 | return -ENXIO; | |
e76e9aeb BW |
1060 | } |
1061 | ||
e76e9aeb BW |
1062 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1063 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1064 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1065 | |
63340133 | 1066 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 1067 | |
63340133 BW |
1068 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1069 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
a93e4161 | 1070 | |
63340133 | 1071 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1072 | |
853ba5d2 BW |
1073 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1074 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1075 | |
e76e9aeb BW |
1076 | return ret; |
1077 | } | |
1078 | ||
853ba5d2 | 1079 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1080 | { |
853ba5d2 BW |
1081 | |
1082 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
1083 | iounmap(gtt->gsm); | |
1084 | teardown_scratch_page(vm->dev); | |
644ec02b | 1085 | } |
baa09f5f BW |
1086 | |
1087 | static int i915_gmch_probe(struct drm_device *dev, | |
1088 | size_t *gtt_total, | |
41907ddc BW |
1089 | size_t *stolen, |
1090 | phys_addr_t *mappable_base, | |
1091 | unsigned long *mappable_end) | |
baa09f5f BW |
1092 | { |
1093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1094 | int ret; | |
1095 | ||
baa09f5f BW |
1096 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1097 | if (!ret) { | |
1098 | DRM_ERROR("failed to set up gmch\n"); | |
1099 | return -EIO; | |
1100 | } | |
1101 | ||
41907ddc | 1102 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1103 | |
1104 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 BW |
1105 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
1106 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; | |
baa09f5f BW |
1107 | |
1108 | return 0; | |
1109 | } | |
1110 | ||
853ba5d2 | 1111 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1112 | { |
1113 | intel_gmch_remove(); | |
1114 | } | |
1115 | ||
1116 | int i915_gem_gtt_init(struct drm_device *dev) | |
1117 | { | |
1118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1119 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1120 | int ret; |
1121 | ||
baa09f5f | 1122 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 1123 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 1124 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 1125 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 1126 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 1127 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 1128 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 1129 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 1130 | else if (IS_HASWELL(dev)) |
853ba5d2 | 1131 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 1132 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 1133 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
1134 | else if (INTEL_INFO(dev)->gen >= 7) |
1135 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 1136 | else |
350ec881 | 1137 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
1138 | } else { |
1139 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
1140 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
1141 | } |
1142 | ||
853ba5d2 | 1143 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 1144 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 1145 | if (ret) |
baa09f5f | 1146 | return ret; |
baa09f5f | 1147 | |
853ba5d2 BW |
1148 | gtt->base.dev = dev; |
1149 | ||
baa09f5f | 1150 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
1151 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
1152 | gtt->base.total >> 20); | |
b2f21b4d BW |
1153 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
1154 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
1155 | |
1156 | return 0; | |
1157 | } |